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80386 AND 80486 PROCESSORS

LIMITATIONS OF 80286 THAT LEAD TO


80386
80286

has only a 16 bit processor.

Maximum
80286

segment size of 80286 is 64 KB.

cannot be easily switched between real

mode and protected mode.


The

amount of memory addressable by the 80286

is 16M byte.
To increase

the over all system performance.

80386 MICROPROCESSOR

Flexible

The
32

32-bitmicroprocessorintroduced byIntelin 1985.

chip of 80386 contains 132 pins & total 129 instructions.

bit data bus 32 bit address bus.

Integrated
Based
The

memory management unit

on CHMOS Technology.

execution of the instructions is highlypipelined and

the processor is designed to operate ina multiuser and


multitasking.
Upward
Very

Compatibility

large memory addressing capabilities

80386
MICROPROCESSOR

Four level protection mechanism


Pipelined instruction Execution.
High speed numeric support via
80287 and 80387 coprocessor.
Uses 3-stage pipelines.
Supports multitasking with
protection.
High speed numeric support with
80386DX coprocessor
Very large memory space

VERSIONS OF 80386
80386DX the full version
The first member in 80386 family
this CPU could work with 16-bit and 32-bit external buses.
Comprises of both 32-bit internal registers and 32-bit
external bus.
80386SX the reduced bus version
low cost version of the 80386.
This processor had 16 bit external data bus,32-bit internal
registers and 24-bit external address bus.
80386SL
low-power microprocessor with power management
features, with 16-bit external data bus and 24-bit external
address bus.
The processor included ISA bus controller, memory
controller and cache controller.

REGISTER ORGANIZATION OF 80386

REGISTER ORGANIZATION OF 80386


(1). The 80386 has eight 32 - bit general purpose registers which may be used as
either 8 bit or 16 bit registers.
(2). A 32 - bit register known as an extended register, is represented by the register
name with prefix E.
(3). Example : A 32 bit register corresponding to AX is EAX, similarly BX is EBX etc.
(4). The 16 bit registers BP, SP, SI and DI in 8086 are now available with their
extended size of 32 bit and are names as EBP,ESP,ESI and EDI.
(5). AX represents the lower 16 bit of the 32 bit register EAX.
(6). BP, SP, SI, DI represents the lower 16 bit of their 32 bit counterparts, and can
be used as independent 16 bit registers.
(7). The CS and SS are the code and the stack segment registers respectively, while
DS, ES, FS, GS are 4 data segment registers.

System

Address Registers:

The

80386 supports Three types of descriptor


table, viz.
(1) Global Descriptor Table (GDT),
(2) Interrupt Descriptor Table (IDT),
(3) Local Descriptor Table (LDT),

They

holds the addresses of corresponding


segments.
8

SEGMENT SELECTORS
Once

the descriptors are defined ,


how does the processor make use of
them?
Any 16 bit value that u write into a
segment register is called a selector,
because it selects a segment
descriptor from a descriptor table.

15

INDEX

TI RPL

LOADING SEGMENT
SELECTORS
Any

given selector value selects one and only


one descriptor

When

that

The

loading segment selector ,the 80386 check

selector index is within the descriptor table limit


The selector references the correct descriptor table
The descriptor is of correct type
The selector uses the correct privilege level

LOCAL DESCRIPTOR TABLE

Local Descriptor
Table(LDT)
GDTR

15

0
LIMIT

31

task can have


access
to
own
private
descriptor
table(LDT)
in
addition to GDT.

LDTR

15

selector

LDTR
0
15
cache
LIMIT
31

LDT0

BASE
programinvisible

descriptors
that provide access
to code and data in
segments of memory

GDT

BASE

Each

Contains

LDTn

11

LOADING SEGMENT
SELECTORS

2 1
Inde
x

TI

Offset

0
RP
L

GDTR

GDT 2
GDT 1
GDT 0

GDT

FLAG REGISTER OF 80386


MICROPROCESSOR

The Flag register of 80386 is a 32 bit register. Out of the 32


bits, Intel has reserved bits D18 to D31, D5 and D3, while D1 is
always set at 1.
Two extra new flags are added to the 80286 flag to derive the
flag register of 80386. They are VM and RF flags.

FLAG REGISTER OF 80386


MICROPROCESSOR
(1). IOPL

(Input Output Privilege Level) flags:- For


protected mode operations indicates the privilege level, 0
to 3, at which your code must be running in order to
execute any I/O-related instructions.

(2). VM Virtual 8086 mode flag:- When it is set, the x86


processor is basically converted into a high-speed 8086
processor.
(3). RF:- Resume Flag Used with debugging to selectively
mask some exceptions.
(4). NT :- (Nested Task) It indicates that current task is
nested within another task in protected mode operation.
This flag is set when nested by software

Central Processing Unit

Memory Management Unit

Bus Control Unit

ARCHITECTURE OF
80386
Central

Processing Unit

Memory
Bus

Management Unit

Control Unit

CENTRAL PROCESSING UNIT

The CPU is further divided into:


Execution Unit
Instruction Unit
Execution
Execution

Unit:

unit has 8 General and Special purpose registers,


which are either used for handling data or calculating offset
addresses.
The 64-bit barrel shifter increases the speed of all
shift, rotate.
Multiply/divide logic implements the bit-shift-rotate
algorithms to complete the operation in minimum
time.

Instruction Unit:
It

decodes the opcode bytes received


from the 16-byte instruction code
queue and arrange them into a 3decoded instruction queue.

After

decoding it is passed to control


section for deriving necessary control
signals

THE 80486 MICROPROCESSOR

80486isthenextinIntelsupwardcompatible80x86
architecture.

Onlyfewdifferencesbetweenthe80486and80386,but
thesedifferencescreatedasignificantperformance
improvement.

32bitmicroprocessorandsameregistersetas80386.

Fewadditionalinstructionswereaddedtoitsinstructionset.

4gigabyteaddressingspace.

MEMORY MANAGEMENT UNIT

MMU consists of a segmentation unit and paging unit.

Segmentation

Unit:

Uses

of two address components - segment and offset for


relocability and sharing of data.

It

allows a maximum segment size of 4GB.

MEMORY MANAGEMENT
UNIT
Paging
It

Unit

organizes physical memory in terms of pages of


4KB size.
It works under the control of segmentation unit
i.e. each segment is divided into pages.
It converts linear addresses into physical
addresses.
The control and attribute PLA checks privileges
at page level.

BUS CONTROL UNIT


It

has a prioritizer to resolve the


priority of various bus requests. This
controls the access of the bus.

The

address driver drives the bus


enable and address signals A2 A31.

MEMORY SYSTEM OF THE 80386


ThememorybankareaccessedviafourbankenablesignalsBE0,BE1,BE2
andBE3.
Bank3

1G*8

Bank 2

Bank1

1G*8

1G*8

Bank 0

1G*8

32 bit

BE0,BE1,BE2andBE3areactivelowsignals.

PRIVILEGE PROTECTION
80386

protection mechanism
Memory management
Privilege protection

privilege level protection

PL0
PL1

(highest)

PL2

PL3(lowest)

numerically
Smaller PL means a
Higher privilege.

IMPROVEMENTS MADE IN
80486
The

new design of 80486 allows the instruction to

execute with fewer clock cycles.


486

is packed with 168 pin grid array package

instead of the 132 pin used for 386 processor.


These

small differences made 80486 more

powerful processor.

IMPROVEMENTS MADE IN
80486

Highly integrated device

80486 was powered with a 8KB cache memory.

Some new 80486 instructions are included to maintain the


cache.

Math co-processor is integrated on the chip allows it to


execute instructions 3 times faster as 386/387 combination.

Built-in parity checker & generator

Burst mode memory read & write

WHY MODE MATTERS

Key

differences among the x86 modes:

How

memory is addressed and mapped


What instruction-set is available
Which registers are accessible
Which exceptions may be generated
What data-structures are required
How task-switching can be accomplished
How interrupts will be processed

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