FUNDAMENTALS OF LOGIC GATES 2.1 Logic Gates
A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. The logic normally performed is Boolean logic and is most commonly found in digital circuits. Logic gates are primarily implemented electronically using diodes or transistors, but can also be constructed using electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements. In electronic logic, a logic level is represented by a voltage or current, (which depends on the type of electronic logic in use). Each logic gate requires power so that it can source and sink currents to achieve the correct output voltage. In logic circuit diagrams the power is not shown, but in a full electronic schematic, power connections are required.
2.2.1 Basic Logic Gates a. OR Gate
The OR gate is a digital logic gate that implements logical disjunction - it behaves according to the truth table to the right. A HIGH output (1) results if one or both the inputs to the gate are HIGH (1). If neither input is HIGH, a LOW output (0) results. In another sense, the function of OR effectively finds the maximum between two binary digits, just as the complementary AND function finds the minimum INPUT OUTPUT A B A+B 0 0 1 1 0 1 0 1 0 1 1 1
There are three symbols for OR gates: the American (ANSI or 'military') symbol and the IEC ('European' or 'rectangular') symbol, as well as the deprecated DIN symbol. For more INPUT OUTPUT information see Logic Gate A B A AND B Symbols. 0 0 1 1 0 1 0 1 0 0 0 1
b. AND Gate The AND gate is a digital logic gate that implements logical conjunction - it behaves according to the truth table to the right. A HIGH output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one input to the AND gate is HIGH, a LOW output results. In another sense, the function of AND effectively finds the minimum between two binary digits, just as the OR function finds the maximum. Truth Table
c. NOT Gate
In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. The truth table is shown on the right. This represents perfect switching behavior, which is the defining assumption in Digital electronics. In practice, actual devices have electrical characteristics that must be carefully considered when designing inverters. In fact, the non-ideal transition region behavior of a CMOS inverter makes it useful in analog electronics as a class A amplifier (e.g., as the output stage of an operational amplifier). Truth Table INPUT OUTPUT A NOT A 0 1 1 0
NOT Gate symbol
2.1.2 Universal Gates
Universal gates are the ones which can be used for implementing any gate like AND, OR and NOT, or any combination of these basic gates; NAND and NOR gates are universal gates. But there are some rules that need to be followed when implementing NAND or NOR based gates.
To facilitate the conversion to NAND and NOR logic, we have two new graphic symbols for these gates.
a. NAND Gate The NAND operation is a logical operation on two logical values, typically the values of two propositions, that produces a value of false if and only if both of its operands are true. In other words, it produces a value of true if and only if at least one of its operands is false.
Truth Table INPUT OUTPUT A 0 0 1 1 B A NAND B 0 1 0 1 1 1 1 0
NAND Gate b. NOR Gate The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0). If one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of
the OR operator. NOR is a functionally complete operation—combinations of NOR gates can be combined to generate any other logical function. By contrast, the OR operator is monotonic as it can only change LOW to HIGH but not vice versa. In most, but not all, circuit implementations, the negation comes for free —including CMOS and TTL. In such logic families, the only way to implement OR is with 2 or more gates, such as a NOR followed by an inverter. A significant exception is some forms of the domino logic family. Truth Table INPUT OUTPUT A B A NOR B 0 0 1 1 0 1 0 1 1 0 0 0
2.1.3 Coincidence Gates
A circuit that produces a specified output pulse only when a specified number or combination of two or more input terminals receives pulses within an assigned time interval. Also known as coincidence counter; coincidence gate.
a. Exclusive OR Gate (XOR Gate) The XOR gate (sometimes EOR gate) is a digital logic gate that implements exclusive disjunction - it behaves according to the truth table above. A HIGH output (1) results if one, and only one, of the inputs to the gate is HIGH (1). If both inputs are LOW (0) or both are HIGH (1), a LOW output (0) results. XOR gate is short for exclusive OR. This means that precisely one input must be 1 (true) for the output to be 1 (true). A way to remember XOR is "one or the other but not both." This function is addition modulo 2. As a result, XOR gates are used to implement binary addition in computers. A half adder consists of an XOR gate and an AND gate. Truth Table INPUT A B 0 0 1 1 0 1 0 1 OUTPUT A XOR B 0 1 1 0
Exclusive OR Gate (XOR Gate)
b. Exclusive NOR Gate (NOR Gate) The XNOR gate (sometimes spelled "exnor" or "enor") is a digital logic gate whose function is the inverse of the exclusive OR (XOR)
gate. The two-input version implements logical equality, behaving according to the truth table to the right. A HIGH output (1) results if both of the inputs to the gate are the same. If one but not both inputs are HIGH (1), a LOW output (0) results.
INPUT OUTPUT A B A XNOR B 0 0 1 1 0 1 0 1 1 0 0 1 Truth Table
Exclusive NOR Gate (NOR Gate)
2.2 Logic Diagram
Basic Logic Diagrams Basic logic diagrams are used to show the operation of a particular unit or component. Basic logic symbols are shown in their proper relationship so as to show operation only in the most simplified form possible. Figure 6-24 shows a basic logic diagram
for a serial subtractor. The operation of the unit is described briefly in the next paragraph. In the basic subtractor in figure 6-24, assume you want to subtract binary 011 (decimal 1) from binary 100 (decimal 4). At time Io, the 0 input at A and 1 input at B of inhibitor I1 results in a 0 output from inhibitor I1 and a 1 output from inhibitor I2. The 0 output from I1 and the 1 output from I2 are applied to OR gate G1, producing a 1 output from G1. The 1 output from I2 is also applied to the delay line. The I output from G1 along with the 0 output from the delay line produces 1 output from I3. The 1 input from G1 and the 0 input from the delay line produce a 0 output from inhibitor I4. The 0 output from L and the 1 output from I3 are applied to OR gate G2 producing a 1 output.
Figure 6-24.—Serial subtractor, basic logic diagrams. At time t1 the 0 inputs on the A and B input lines of I 1 produce 0 outputs from I1 and I2. The 0 inputs on both input lines of OR gate G 1 result in a 0 output from G1. The I input applied to the delay line at time to emerges (1 bit time delay) and is now applied to the inhibit line of 13 producing an 0 output from I3. The 1 output from the delay line is also applied to inhibitor I4, and along with the 0 output from G1 produces a 1 output from I4. The I4 output is recycled back into the delay line, and also applied to OR gate G2. As a result of the 0 and 1 inputs from I3, and I4, OR gate G2 produces a 1 output. At time t2, the 1 input on the A line and the 0 input on the B line of I1 produce a 1 output from I1 and a 0 output from I2. These outputs applied to OR gate G1 produce a 1 output from G1, which is applied to 13 and I4.
The delay line now produces a 1 output (recycled in at time t1), which is applied to I3 and I4. The 1 output from the delay line along with the 1 output from G1 produces a 0 output from I3. The 1 output from G1 along with the 1 output from the delay line produces a 0 output from I4. With 0 outputs from I3 and I4, OR gate G2 produces a 0 output.
2.3 Truth Table
A truth table is a mathematical table used in logic—specifically in connection with Boolean 0 0 0 algebra, boolean functions, and propositional 0 1 1 calculus—to compute the functional values of 1 0 1 logical expressions on each of their functional arguments, that is, on each combination of 1 1 1 values taken by their logical variables (Enderton 2001). In particular, truth tables can be used to tell whether a propositional expression is true for all legitimate input values, that is, logically valid. Practically, a truth table is composed of one column for each input variable (for example, A and B), and one final column for all of the possible results of the logical operation that the table is meant to represent (for example, A XOR B). Each row of the truth table therefore contains one possible configuration of the input variables (for instance, A=true B=false), and the result of the operation for those values. See the examples below for further clarification. Example Truth Table of OR Gate where 0 = True, 1=False INPUT OUTPUT A B A+B
2.4 Circuit Making
3. EQUIVALENT CIRCUIT
An equivalent circuit refers to the simplest form of a circuit that retains all of the electrical characteristics of the original (and more complex) circuit. In its most common form, an equivalent circuit is made up of linear, passive elements. However, more complex equivalent circuits are used that approximate the nonlinear behavior of the original circuit as well. These more complex circuits often are called macromodels of the original circuit. An example of a macromodel is the Boyle circuit for the 741 operational amplifier. There are two very renowned two-terminal equivalent circuits:
Thévenin equivalent - reduces a two-terminal circuit to a single voltage source and a series Thévenin impedance Norton equivalent - reduces a two terminal circuit to a current source and a parallel Norton impedance
For a restricted set of linear four-terminal circuits, equivalent two-port networks can be set up. The restriction upon a two-port representation is that of a port: the current entering each port must be the same as the current leaving that port. By linearizing a nonlinear circuit about its operating point, such a two-port representation can be made for transistors: see hybrid pi and h-parameter circuits. Equivalent circuits also can describe and model the electrical properties of materials or biological systems like the cell membrane. The latter is modelled as a capacitor (i.e. the lipid bilayer) in parallel with resistancebattery combinations (i.e. ion channels powered by an ion gradient across the membrane). 3.1 NAND Gate Implementation The NAND gate has the property of functional completeness. That is, any other logic function (AND, OR, etc.) can be implemented using only NAND gates. An entire processor can be created using NAND gates alone. In TTL ICs using multiple-emitter transistors, it also requires fewer transistors than any other gate.
CMOS NAND Gate 3.2 NOR Gate Implementation
TTL NAND Gate
The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0). If one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. NOR is a functionally complete operation—combinations of NOR gates can be combined to generate any other logical function. By contrast, the OR operator is monotonic as it can only change LOW to HIGH but not vice versa. In most, but not all, circuit implementations, the negation comes for free— including CMOS and TTL. In such logic families, the only way to implement OR is with 2 or more gates, such as a NOR followed by an inverter. A significant exception is some forms of the domino logic family.