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Designing of Arithmetic and logic circuits using Sub-threshold pass transistor logic

Designing of Arithmetic and logic circuits using Sub-threshold pass transistor logic

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INTRODUCTION

1.1 INTRODUCTION TO LOW POWER:

The need for portable devices operating at low power and at high speeds is growing

day by day. During the recent years there is a huge demand for portable devices and they all

demand for low power dissipation. Hence low power design has emerged as a very striking

and fast growing field. High performance digital systems such as microprocessors and other

applications demand for low power design. The low power operation is essential mainly to

increase the battery life and to reduce the excess of heat. In view of this it is essential to

minimize the power dissipation in digital integrated circuits.

The various techniques that are employed to reduce the power dissipation are

recycling the energy that might be stored in nodal capacitances, reduction in voltages and

currents, reduction in transitions (0 to 1 or 1 to 0), and so on. The techniques based on

operation at very low currents usually below the normal conduction region, especially in FET

based circuits is known as sub threshold operation. Sub-threshold circuits work generally

with a supply voltage less than the threshold voltage of transistor and leakage current used as

operating current. As power is related quadratically to the voltage, reducing the voltage to

low levels causes a reduction in power consumption. These circuits are limited to low

frequency applications, because of low current operation.

Conventional digital CMOS circuits have two modes of operation called ON mode

(saturation) and OFF mode (sub threshold mode). But sub threshold circuits are either in OFF

mode or almost ON mode (still circuit is in sub threshold region). This has fascinated several

investigators, as it has flexibility to choose their own logic levels and power dissipation. But

the main drawback of this technique is the circuits suffer from large delays and hence the

realization of high frequency circuits becomes complicated. This is due to small driving

current.

1.2 OBJECTIVE:

The main objective of this project is to design Sub-Threshold based Pass Transistor

Arithmetic and Logic circuits, which are responsible in building up an ALU (Arithmetic and

Logic Unit)

1.3 MOTIVATION:

Power consumption is a major concern for integrated electronic circuits. It influences

the design and fabrication of circuits and systems. The need for portable devices operating at

low power and at high speeds is growing day by day. During the recent years there is a huge

demand for portable devices and they all demand for low power dissipation. Hence low

power design has emerged as a very striking and fast growing field. High performance digital

systems such as DSP, microprocessors, and other applications demand low power design.

The low power operation is essential mainly to increase the battery life and avoid failures of

hot spots.

In modern VLSI design transistor sizes are scaling down to integrate millions of

transistors in a single chip, from this SOC (System on chip) has arrived. Such high level of

integration leads to increase in power consumption and area. For more power and area

efficient design, we need to examine different logic families. There are two logic families

such as Static CMOS logic and Dynamic CMOS logic design. Static CMOS has been the

most dominant design in the VLSI design in recent decades.

However, it may not be the most power and area efficient design. Early PseudoNMOS design requires only N+1 transistor i.e. (NMOS transistors and one more PMOS

transistor which is constantly ON). Pseudo-NMOS logic is Ratioed logic, i.e. the correct

function relies on the proper sizing of the transistors. These limit the application of PseudoNMOS logic.

Dynamic logic may require less number of transistors, thus leading to more area

efficient design. These works in pre-charge and evaluation phases and outputs are valid only

in evaluation phase. Furthermore, dynamic circuits suffer from charge leakage effect. Due to

charge leakage in the output nodes, the voltage level gradually decreases and eventually

cannot be recognized to logic 1, this leads to logic error of the circuit.

Coming to Pass Transistor Logic, it seems to have advantages of reduced transistor

count, smaller circuit area and low power consumption. It does not suffer from charge

leakage problem. The outputs are valid all the time as in Static-CMOS. Thus Pass Transistor

Logic could be a good choice for low power VLSI design. Pass Transistor Logic has been

widely used in Low Power VLSI design. In Pass Transistor Logic, there are different types of

approaches.

The Project investigates to find more power efficient circuits which aim in exploiting

the PTL for building blocks of ALU. There are two aspects in this project. Firstly, the project

focused on Pass Transistor Logic circuits instead of CMOS logic circuits and concluded that

PTL has lower leakage and requires less number of transistors compares to CMOS logic.

Second aspect is the use of transistor in Sub-Threshold region as a method of Low Power

Consumption compared to CMOS logic.

The techniques based on operation at very low currents usually below the normal

conduction region, especially in FET based circuits is known as sub-threshold operation. Subthreshold circuits work generally with a supply voltage less than the threshold voltage of

transistor and leakage current is used as operating current. As the power is related

quadratically to the voltage, reducing the voltage to lower levels causes a reduction in power

consumption. Transistor operating in the Sub-Threshold region consumes small amount of

energy, but at the cost of circuit performance in terms of speed. However, the approach is

concerned that performance is not a major part and primary concern is Power Consumption.

The Project study includes power efficient structural methods for complex circuits. The

motivation of the project is to show that PTL logic circuits are more power efficient than

CMOS logic and PTL can be operated with sub-threshold voltage. The project validates subthreshold PTL for limited number of basic logic circuits and small hierarchical structures.

And these lead towards building larger circuit blocks like ALU. If this is successful, it can be

advantageous for energy constraint applications.

1.4 The Project:

The whole design of the project was conducted in Cadence Virtuoso 180nm process

design kit. The MOSFET transistors used in this project are obtained from the gpdk-180 built

in library where transistors are fully characterised for all three regions of operations including

sub-threshold. Therefore, the simulation results are expected to be valid and accurate. The

project started with studying of Pass-transistor logic and corresponding CMOS basic circuits

for the purpose of comparison. The basic logic circuits are added carefully in order to develop

efficient hierarchical structures of ALU. All the Pass-Transistor logic circuits are

characterised in terms of propagation delay and power consumption for sub-threshold supply

voltage. The characterisations were carried out for all PTL circuits and basic logic gate

CMOS circuits only. This is because the project goal was to develop larger PTL circuits.

Both Arithmetic and Logic circuit designs are implemented, in order to enable the

circuits to be useful for realising ALU.

1.5 Organisation of the Project:

Chapter 1 gives a brief introduction to low power followed with the Motivation and

considerations to take up the project.

Chapter 2 explains about Operation of MOSFET and CMOS Logic gates, thereafter a

description of sub-threshold conduction followed by sub-threshold swing and sub-threshold

slope. Characteristics of CMOS inverter and pass transistor logic circuits, these follow

description of PTL circuits with different styles.

Chapter 3 includes Arithmetic circuits (Adder, Sub-tractor, Multiplier, Multiplexer

and Divider) designed with Pass Transistor logic.

Chapter 4 includes the Circuit characterisation, which deals with propagation delay

and power consumption.

Chapter 5, in this chapter the conclusion about the suitability of sub-threshold PTL for

ALU has been discussed.

Last Section includes References which are taken into consideration to this project.

CHAPTER 2

BASIC CONCEPTS AND LITERATURE REVIEW

2.1 Introduction:

This chapter gives the information about CMOS behaviour and its characteristics in

sub-threshold region and Pass Transistor Logic styles.

2.2 Operations of MOSFET and CMOS Logic Gates:

2.2.1 Strong Inversion:

The requirement for the normal operation of a MOSFET is the gate voltage to be

bigger than the device threshold voltage. The region of this operation can be referred to as

strong inversion operation.

(2.1)

There are two regions of operation for Strong Inversion (Triode and Saturation

region). Both region of operation is controlled by the bias voltage of the device. For an

NMOS transistor, below expressions gives conditions for triode and saturation region of

operation.

(2.2)

(2.3)

In Triode (linear) region, the device behaves like a linear resistor whose value is

controlled by VGS. In saturation, the device current reaches a maximum value and the device

is said to be pinched off.

5

A MOSFET is said to be in cut-off region for gate voltages less than the device

threshold voltages. Theoretically, there is no current flow. However, in practical a weak

inversion layer exists which causes the flow of diffusion carriers in the channel. Therefore,

the device current

2.2.2.1 Sub-Threshold conduction:

Basically the Sub-threshold conduction is nothing but the Sub-threshold leakage or

Sub-threshold drain current is the current that flows between the source and drain of the

MOSFET, when the transistor is in Sub-threshold region or weak inversion region, i.e. gate to

source voltages below the threshold voltage.

(2.4)

The Sub-threshold current varies exponentially with

(2.5)

Where

(2.6)

Sub-threshold swing coefficient

Where

Depletion capacitance

Oxide capacitance

VT = Thermal voltage

Zero bias electron mobility in the channel

Width over length ratio of the device

Threshold voltage

(2.7)

Also the transistor OFF state current (

(2.8)

It is observed that the drain current changes exponentially with

inversion, drain current responds relatively with

where as in strong

There are two parameters that are normally defined in the region and they are

1. Sub-threshold slope

2. Sub-threshold swing

2.2.2.2 Sub-threshold slope and Sub-threshold swing:

The dependence of the gate voltage swing needed to change the drain current by an

order of magnitude is defined as sub-threshold slope S and S is defined as

S=

(2.9)

region. The smaller the S value is the higher the drive current

A NMOS transistor operating in different gate voltage,

voltage i.e. 0.5V and the corresponding drain current

Inverter in sub-threshold mode requires the supply voltage

threshold voltage

, to ensure the weak inversion operation for both the NMOS and PMOS

Although the sub-threshold inverter implementation is feasible, many researchers are

concerned on the delay of such logic gates. The propagation delay of asymmetric inverter for

<

is stated in below expression, from where it can be seen that the delay is strongly

the speed

(tpd) of a normal inverter is insignificant. In the sub-threshold region, the speed decreases.

(2.10)

(2.11)

The voltage transfer characteristics shown in figure 2.5 and 2.6 is of a static CMOS

inverter is similar in both normal and sub-threshold operation. This is a key fact that makes

the sub-threshold implementation of logic cell possible without any large scale adjustment

in design.

The most important feature of sub-threshold design is that it can offer minimal energy

consumption in electronic circuits. However, such energy efficiency comes at the expense of

performance which is the large propagation delay in circuits. Figure 2.7 gives a rough idea of

how speed can be affected by low power.

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Figure 2.7: Delay vs. Energy for Minimum delay and energy point

Dependence of threshold voltage on the temperature along with process is another

major concern for sub-threshold design.

On the other hand, sub-threshold design does not require immense amount of design

effort and hence easier to implement. A number of applications are implemented in subthreshold technique since it ensures that low power consumption and easier design process.

As mentioned earlier in this chapter that portable applications like mobile phone, dynamic

range of power and process operation. Ultra Dynamic Voltage Scaling (UDVS) is used to

ensure the low power consumption in such devices for extending the battery life. For high

performance critical operations, it allows devices to run in high voltage or in high frequency.

While in sleep mode, the devices run in sub-threshold voltage to minimize power

consumption. Another major platform of sub-threshold technique exploration is the energy

constrained applications. These applications typically do not require high performance

process and strive for low power consumption.

2.3 Pass Transistor Logic:

In electronics, pass transistor logic (PTL) describes several logic families used in the

design of integrated circuits. It reduces the count of transistors used to make different logic

gates, by eliminating redundant transistors. Transistors are used as switches to pass the

voltage logic levels between nodes of a circuit, instead of as switches connected directly to

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supply voltages. This reduces the number of active devices, but has the disadvantage is that

the difference of the voltage between high and low logic levels decreases at each stage.

In standard CMOS logic circuits all input signals are applied to the gate of both

NMOS and PMOS transistors. When in static mode, the complementary transistors are either

in cut-off mode or in saturation mode depending on the input signals state. However, in Passtransistor logic the input signals is connected to both drain and source of a transistor.

2.3.1 Operation Principle:

Pass Transistor Logic requires comparatively fewer number of transistor than CMOS

and easier to implement. Below figure shows an NMOS transistor implemented as in PTL

AND gate. Source voltage of the transistor is

much bigger than the voltage drop caused by

and the output voltage is considered as logic

1. However, it is inadequate to carry out the AND operation for the arrangement where

circuit goes to high impendence state for gate logic 0. Therefore another NMOS is added to

the design. The addition of NMOS is essential for the static design since it ensures low

impendence path to the supply rail (input rail for PTL).

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Pass Transistor logic makes the design much easier with fewer transistor and variety

of logic operations. Compared to six transistors in CMOS design implementation, it uses only

two transistors for the AND operation. Other logic operations are also achievable with the

appropriate change of wiring. The output logic was obtained by drain and gate voltages of the

NMOS. The below expression shows the logic function of a Pass-Transistor Logic AND gate.

(2.10)

A major concern for Pass Transistor Logic design is the lower output voltage due to

drop, as mentioned earlier. A PTL AND gate should not be connected the input of another

gate for the

drop at output end shown in the figure 2.9. The degraded output ultimately

becomes insufficient to drive the next gate. When connected in series, the input signal is

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degraded for

drop throughout the chain given in figure 2.10. Therefore, it does not allow a

However, this signal degradation can be recovered by using a level restorer circuit i.e. buffer

or either PMOS or NMOS with always ON state for recovery of voltage logic level

degradation. Conventionally, a CMOS inverter is used to restore the signal to voltage logic

values logic1 =

dissipation.

2.3.2 Complementary Pass Transistor Logic (CPL):

Complementary Pass Transistor Logic is based on the true and complementary signal

at both the input and output end. The operation is based on the PTL AND gate in the figure

(2.8(b)). The logic is also known as differential pass transistor logic for the complementary

outputs. The Figure 2.11(a) (b) shows AND/NAND and OR/NOR gate. They follow the same

topology with input signal combinations defining the type of logic operation. Furthermore an

XOR/XNOR gate could also be derived from the same topology. The main feature of CPL is

that it offers a simple Full Adder implementation. Simple design of XOR/XNOR gate allows

designing a Full-Adder very easily.

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2.3.3 Dual Pass Transistor Logic (DPL):

Dual Pass Transistor Logic overcomes the CPL threshold voltage drop when passing

logic 1. Unlike CPL logic which uses a CMOS inverter to overcome the voltage drop, DPL

uses PMOS logic in parallel with NMOS. Figure 2.13 shows general DPL AND/NAND gate.

In this approach, the PMOS transistor passes logic 1 without any threshold loss while logic

0 is passed by NMOS transistor.

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As concerned with the DPL logic, it can be implemented simply with single NMOS

and single PMOS. For this logic simple OR gate is given below. By taking this logic into

consideration, complete circuits that are included in this project are designed with this logic.

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Similarly for CPL, DPL offers a very efficient Full-Adder design. Other logic gates

such as OR/NOR and XOR/XNOR could also be designed effectively. Furthermore, the

circuit capacitance in DPL is equally distributed for each output as well as for the inputs.

2.3.4 LEAP (Lean Integration with Pass Transistor):

Lean Integration with Pass Transistor (LEAP) was introduced in 1996. The

researchers successfully developed a smart and small PTL based cell library (7 cells) with a

synthesis tool defined as cell inventor. The main objective of the research was to optimize

area, speed and power optimization in digital design. Furthermore, LEAP was more cost

effective compared to CMOS. Along with 4 different inverters used to meet the drive

requirement, the cell library consists of 3 logic cells Y1, Y2 and Y3 shown in the below

figure. These 3 cells are capable of executing basic logic function with different number of

input signals as necessary.

2.4 Sub-Threshold Pass Transistor Logic:

Number of researches has been conducted on sub-threshold voltage implementation

and pass-transistor logic separately for different parameter optimization such as speed, power

consumption and area. However, there is only a limited amount of research discussing about

combining both the techniques. Most of the researches concentrate on circuit performance in

terms of speed for different design techniques.

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As mentioned earlier, many researchers declared that different type of PTL designs

are to be more energy efficient than CMOS design. Moreover, sub-threshold implementation

is capable of optimizing the design for minimal power consumption. Combination of these

two techniques indicates a substantially power efficient design at the cost of speed.

Therefore, sub-threshold Pass Transistor Logic design could be greatly beneficial for selfpower constraint application where, power is scarce resource and performance is not the main

concern.

2.5 Literature Review:

This section deal with the low power circuits, power reduction, Pass-transistor logic

circuits in sub-threshold operation.

Anantha P. Chandrakasan in his article [16] focused on the supply voltage reduction

for obtaining low power. The switching power consumed is a quadratic function of the

operating voltage. Hence reducing the operating voltage, results in considerable reduction of

switching power. However reducing the operating voltage increases the delay of the different

logic circuits, since the delay is proportional to the capacitor being charged and discharged

and inversely proportional to

concluded that power reduction through supply voltage reduction results in increase in delay

and in turn reduces the throughput.

Reto Zimmermann in his research [3] identified that the previous works on PTL

focused developing Full-Adders only which is relatively easier to design in CPL or DPL

compared to least efficient CMOS approach. Furthermore, design topology of PTL requires

immense design effort and layout of such design is complicated as well. In fact the outcome

research [3] is based on the variety of digital application in CMOS which does not thoroughly

cancel out the merits of PTL design. It completely compares the CMOS logic and PTL logic.

B Paul and K Roy [11] concluded that sub-threshold CMOS circuits can provide

excellent power reduction over strong inversion CMOS circuits. They designed devices

which are suitable for sub threshold operation. Results indicate that the optimized device

improves the speed and power delay product (PDP) of an inverter chain by 44% and 51%,

respectively, over the normal super-threshold device operated in the sub threshold region.

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Ramesh Vaddi and S Dasgupta [9] has done research on device level optimization in

sub-threshold region and concluded that as supply voltage continues to scale with each new

generation of CMOS technology, Sub-threshold design is an inevitable choice in the semiconductor road map for achieving ultra low-power consumption. Device optimization is a

must for optimal sub-threshold operation to further reduce power and enhance performance.

This showed that double gate SOI devices and CNFETs are better candidates to work for

Sub-threshold operation than Bulk CMOS devices.

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CHAPTER 3

ARITHMETIC AND LOGIC CIRCUITS

3.1 Introduction:

The objective of this chapter is to design Arithmetic and Logic circuits and evaluate

their behaviour. Firstly, basic logic circuits are implemented in CMOS logic style and as well

as pass transistor logic style i.e. Dual Pass Transistor Logic Style. Later, based on the logic

circuits arithmetic circuits are implemented which includes (adder, subtractor, multiplier,

multiplexer and divider circuits).

3.2 Basic Circuits:

The Basic circuits, which included in this project are AND, OR, XOR, NAND, NOR

these are designed with Static CMOS logic and Dual Pass Transistor logic (DPL) and

compared with Power consumption, propagation delay and number of transistors which

defines the area of the circuit. The following section includes design details and features of

each circuit.

3.2.1 CMOS Circuits:

All the basic Logic gate circuits which are needed is designed and characteristics are

taken which includes power consumption, propagation delay. The complete designs are done

in Cadence Virtuoso IC6.1.5, it includes 180nm technology. The Width and Lengths for

PMOS (width = 1.6 m and length = 180nm) and for NMOS (width = 0.8 m and length =

180nm). Characteristics of the circuits is taken with voltage range of 0.3V to 0.5V i.e.

propagation delay measurement, power consumption and power delay product. These

characteristics decide the performance of the circuits.

CMOS Inverter plays a key role in both CMOS circuits and as well as in passtransistor logic circuits, it is integrated in all the circuits. However, there was no separate

circuit designed and characterised for inverter operation. Of course there are other approaches

for designing a circuit for inverter logic but, this includes only Static CMOS inverter.

Moreover, for larger design blocks, inverter is used extensively. Transistor sizes of the

inverter are same as the ones used in other basic circuits. In Dual Pass Transistor Logic style

circuits, inverter plays a key role at output logic levels.

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AND gate:

This logic circuit includes 2 input AND gate with an inverter which is used to drive

the output. It has 3 PMOS transistors and 3 NMOS transistors with width (1.6

0.8

PMOS,

Figure 3.1: 2 input AND gate circuit and simulation waveform with CMOS at 0.5V

supply

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The input of figure3.1 is taken 0.4V with 0.5V supply and many simulations are done

with different voltages i.e. with 0.3V to 0.5V. And Power Delay Product (Figure of merit) is

measured from obtained Propagation delay and Power.

OR gate:

This logic circuit includes 2 input OR gate arranged with two parallel NMOS

transistors in series with serial PMOS transistors as shown in figure 3.2. A separate inverter is

arranged at the output of the circuit to invert complimentary output to the exact OR logic

output.

Figure 3.2: 2 input CMOS OR gate and simulation waveform with 0.5v supply

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XOR gate:

This XOR logic circuit contains 4PMOS in pull up circuit and 4NMOS in pull down

circuit. For driving different inputs inverters are using i.e. for satisfying the XOR logic.

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NAND gate:

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NOR gate:

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The Logic gates are designed to measure power consumption and propagation delay

to compare these characteristics with the Pass Transistor Logic circuits, which take part in the

rest of the circuits included in this project.

3.2.2 Pass Transistor Logic circuits:

Design of the circuits are firstly made with Complementary Pass Transistor logic, this

design includes either PMOS or NMOS. Logic gates (AND, OR, NAND, XOR) are designed

with Complementary Pass Transistor logic and logical outputs are taken, Later shifted to Dual

Pass Transistor Logic which includes both PMOS and NMOS. The main intention in taking

Dual Pass Transistor Logic is area and power efficient when compare to other PTL logic

styles and as well as CMOS logic styles

The main advantage of using PTL is that one pass transistor (either a PMOS or an

NMOS) is sufficient to perform a logical operation, which greatly reduces the number of

transistors used, compared with a circuit using a conventional CMOS configuration to

achieve the same logic. One major drawback in the Complementary PTL is that although an

N-type pass transistor produces a strong 0 or ground, it produces only a weak 1 by

lowering the output below

, where

contrast, a P-type pass-transistor produces a strong 1, but a weak 0 by raising the output

above |

drawback results from different threshold voltages for NMOS and PMOS FETs, and the

change in the output is usually referred to as threshold voltage drop. However, benefitting

from the small threshold voltage near zero, the threshold voltage drops for both NMOS and

PMOS pass transistors are much smaller, which show threshold voltages that are typically ten

times larger. On the basis of these high-performance pass transistors, we are using CMOS

based Pass Transistor Logic it is nothing but Dual Pass Transistor Logic (DPL).

3.2.2.1 Logic Circuits with PTL:

OR gate:

OR gate is shown in figure 3.6. It consists of one PMOS transistor and one NMOS

transistor to pass either input A OR B to output. The gate input of both transistors is

connected to input B.

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The above circuit was simulated in cadence virtuoso, the output logic levels are

occurring with some glitches, this is due to the threshold drop of pass transistors. As we

know, MOS transistor needs to maintain its

voltage in order for the transistor to be turned ON. In order to maintain the threshold drop,

PMOS transistor passes a strong 1 but a weak 0, NMOS transistor pass a strong 0 but a

weak 1. This indicates that voltage passing through pass transistors will have level

degradation issue. If it is only a single PTL gate, this may not be a big problem. However, if

multiple PTL logic gates are cascaded to each other, this level degradation may become even

worse and eventually cause logic error. Thus certain action needs to be taken to overcome

this level degradation problem of PTL logic.

For this problem a level restorer circuit can be used to restore the logic levels

whenever voltage drops. Level restorer circuits can be of different types, but here we are

using CMOS buffer circuit because CMOS logic can recover logic level to full power rails.

When output of CMOS is logic 1 or 0, it is connected to either

or Ground, hence

achieving strong rail-to-rail voltage levels. Adding CMOS buffers will introduce extra gates,

hence leading to power and area overhead. However, this ensures the correct function of the

PTL circuit. However, this circuit consumes less power when compared to CMOS logic. OR

gate with a level restorer circuit is shown in figure 3.7.

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The simulated waveforms for OR gate are show in figure 3.8. As we can see from

figure 3.8, when input AB=00, output is 0, when input AB=01, 10, or 11, output is 1.

Coming to the logic, the circuit is completely made based on the truth table of the OR gate.

For example, take input as A=1, B=0, then corresponding PMOS gate is ON, it will gives

logic 1 as output and for 11 it gives 1 and likewise OR gate logic is obtained using DPL

logic.

NOR gate:

For DPL NOR gate, we only use CMOS inverter at the end for level restoration, by

this both CMOS and DPL logic has the same number of transistors. And rest of the circuitry

is same as DPL OR gate logic.

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AND gate:

DPL AND gate logic circuit was given below. The AND logic gate is designed by

interchanging the PMOS and NMOS positions, thus it gives (A.B) logic based on the two

input signals.

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The figure 3.12 waveform shows the AND operation logic and the circuit includes a

level restorer circuit and logic levels at outputs, when both inputs are 1 the corresponding

output is 1.

NAND gate:

The logic of NAND gate is obtained by adding a level restorer circuit to the DPL

AND gate circuit, this give the NAND operation.

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XOR gate:

The XOR gate includes AND logic design and buffer circuit, but difference is giving

inputs to the two transistors. In every circuit one of the input is given as common to the gates

and connected to the second input i.e. to drain, but in XOR logic one separate input is given

to the gates of two transistors and input one is inverted and given to the other input, which is

shown in figure 3.15.

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The waveforms shown in figure 3.16 gives the XOR gate logic with respect to the

inputs, but there is a glitch that occurred at one stage where input 1 rising from low to high

and input 2 falling from high to low. That unwanted glitch should be reduced.

3.3.1 Adders:

1 Bit Adder:

The design of 1 Bit Adder is with logical AND, XOR and in DPL logic. The figure

3.17 shows the design of Pass Transistor Full Adder circuit. As shown in the figure, two

CMOS inverters are connected to Sum and Carryout outputs of the PTL full adder. They are

used as buffers to recover the logic levels of PTL full adder. This ensures that there is no

voltage threshold drop for the PTL full adder. This is important because for 8-bitadder

design, we need to cascade eight 1-bit full adder circuits in series. If not corrected, voltage

degradation in PTL full adders can be added up and eventually causes logic error of the

circuit.

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Firstly, without using level restorer circuit we have output with level degradation i.e.

output waveform without using buffer circuit in figure 3.18. And with the addition of level

restorer circuit i.e. buffer circuit, the level degradation was reduced is shown in figure 3.19.

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2-Bit Adder:

The 2-bit adder circuit was built up by using 2 1-bit full adder circuits, these two are

cascaded in series and first output carry is forwarded to second. Design is given in the figure3.20. For given inputs a0=1, b0=1, co=0, a1=1, b1=0 the waveform is in figure 3.21.

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For the different combinations given to the 2 bit adder continuously with the help of

different time period which covers maximum combinations and simulated waveform is

shown in figure 3.22.

In the figure 3.22, the output waveform contains unwanted glitches which are

obtained from the logical transitions of inputs given. There is continuous generation of

sequences at the input and output waveform takes some time to generate. From the figure

3.22, observed that there is a glitch when input 1 changing it state from 0 to 1 and input 2

changing its state from 1 to 0, here it takes time to change their states. At that particular

transitions the output suddenly changing to logic 1 i.e. 0.2us a minute change it can be

neglected.

4-Bit Adder:

The 4-bit adder is nothing but the Ripple Carry Adder, which first output carry drives

next one and so on up to 4 bits of A and B inputs. It is designed with 1-bit Full adder circuit

blocks.

36

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8-Bit Adder:

This is also designed by using 1-bit Full adder circuits as same as ripple carry adder,

but here we use 8 1-bit Full adder circuits.

The inputs to the 8 bit adder is given with different time periods, from 2us i.e.

multiples of 2 and extended to 128us. But, simulation waveform is taken up to 50us so that

complete combinational outputs are not there in figure 3.26.

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3.3.2 Subtractors:

1-bit Subtractor:

The design of the 1-bit Subtractor is based on the 1-bit Full adder circuit, where and

extra CMOS inverter is enough to change the logic from Adder to Subtractor.

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2-bit Subtractor:

The 2-bit Subtractor can be designed in two ways, one is by using 1-bit full adders

and inverter circuit and another is by using 1-bit full Subtractor which was shown previously.

40

4-Bit Subtractor:

41

8-Bit Subtractor:

The 8-bit Subtractor is designed by using 1-bit full Subtractor circuits.

42

The inputs to the circuit is given with all 8 combinations for first 1 bit subtractor and

later on following with 2 combinational inputs to the rest of the inputs. Coming to the

glitches, as discussed earlier if there is a sudden change in transitions in opposite direction for

2 inputs, at that particular state there is sudden change to logic 1 which gives a glitch. If we

are applying only one logical input to one input, the outcome would appear with a small

delay and the rest of the output logic would be as expected.

3.3.3 Multipliers:

Multiplier is also a major one in arithmetic circuits which works in multiply Shift and

Add theory, for this case Array multiplier is used in this design. Each carry output will

carried to the next circuit i.e. output at the second stage depends upon the previous stage

output.

4 bit Multiplier:

Design is the Array multiplier designed with AND logic circuit, Half adder and Full

Adder circuits. Figure 3.35 gives the array multiplier design.

43

The Inputs are given with single logic level i.e. either logic 1 or logic 0 and

corresponding outputs are taken. Here delay is occurring at waveforms i.e. it is going on

increasing from one output to the other.

Figure 3.36: Simulation waveform for 4 bit multiplier with single input

For a combination of inputs the output waveform would be completely

different and delay of one stage depends on the previous stage. Multiplier with different

combination of inputs given in sequence is shown in figure 3.37.

44

8*8 Multiplier:

This design is also based on the Array design.

45

The input for 8*8 multiplier is given as all 1s for input A and B and outputs are

taken, the outputs are obtained with delay which is carried from one stage to another. The

output is given in figure 3.40.

The delay is carrying for all the outputs because, it takes time to evaluate one input

and for carrying to the other input it would take some time to get second block output.

3.3.4 Multiplexers:

Multiplexer is designed to select either input 1 or input 2 based on the select lines that

are given by the designer. In this project multiplexer designs are made by using DPL logic

with only two transistors, one PMOS and one NMOS. Here, a level restorer circuit is also

used to reduce the level degradation of the logic levels.

2*1 Multiplexer:

The 2*1 Multiplexer helps in building 4*1 multiplexer, 8*1 multiplexer circuits and

useful in complex circuits that are used in processors.

46

4*1 Multiplexer:

This 4*1 Multiplexer is designed with the help of 2*1 multiplexers and followed

outputs are obtained based on select lines.

47

8*1 Multiplexer:

The 8*1 Multiplexer is designed by combining both 2 bit multiplexer and 4 bit

multiplexer i.e. two 4*1 multiplexers in series and their outputs are given as inputs to the 2*1

multiplexer.

48

49

The design of the Divider is based on subtraction and comparison. For this circuit

design is based on the number of inputs that are taken as Dividend and Divisor. Logic is to

subtract the Divisor from Dividend and compare that subtracted output with the divisor, if the

divisor is greater than subtracted output, divisor again subtracted from the output obtained. A

comparator is arranged at the outputs of every Subtraction to compare the obtained output

and divisor, if outcome is greater than divisor, subtraction continues and if output obtained is

less than the divisor and then we need to stop the operation. The obtained one is remainder,

number of outcomes from the comparator is taken and there are to be added, obtained one is

coefficient. The inputs are given as dividend 1101 and divisor 0011

Coefficient was obtained by counting the number of subtractions done with respect to

the divisor.

The comparator circuit designed with CMOS logic in this 4 bit divider circuit, which

gives the partial coefficient is obtained and then based on the counting of the number of

coefficient outcomes gives the original coefficient.

50

At the output there is a delay in the waveform, which is giving an unwanted signal.

This unwanted delay could be reduced by making small modifications and rest of the signal

output is coming as per the logic. From this same logic an 8 bit divider circuit can also be

implemented.

This chapter gives the designs of Dual Pass Transistor logic based Sub-threshold

Arithmetic and logic circuits and concludes that the Sub-threshold based DPL circuits are

more power efficient with low performance. All the Arithmetic and logic circuit

characteristics are taken for different voltages where the output driving without larger delay.

The circuit characterisations are included in chapter 4.

51

CHAPTER 4

CIRCUIT CHARACTERISATION

4.1 Introduction:

This chapter gives the characteristics i.e. propagation delay and power consumption

of logic circuits and Arithmetic circuits.

4.2 Design characterisation:

All the design work in this project was carried out in the Cadence virtuoso IC6.1.5

with 180nm process. This technology is chosen specifically for two reasons. Firstly, the

Spectre simulator included in this process can provide very detailed and precise simulation on

analogue circuits with user friendly interface. Most importantly it can characterise the MOS

devices from its own library for sub-threshold operation. Secondly, this technology is well

known and has been widely used for years. It is available

The basic logic circuits designed in this project and were characterized in terms of

propagation delay and power consumption (static and dynamic) for an inverter under

different simulation conditions such as different ambient temperatures with a single supply

voltage and for the rest of the logic circuits, only with one supply voltage at room

temperature

. However, the simulations were mainly carried out on PTL basic circuits

and only a few CMOS circuits were characterised. This is because the project intended for

designing complex and practical circuits based on PTL method only. The supply voltage for

the circuits is taken as 0.5V as common to all, which runs circuits in sub-threshold region.

4.2.1 Propagation Delay measurement:

Delay time definitions of CMOS Inverter:

The input and output voltage waveforms of a typical inverter circuit are shown in

figure. The delay parameters include tphl (high to low propagation delay), tplh (low to high

propagation delay), the output signal used to fall at first transition is the fall time and next

transition is the rise time.

52

The propagation delay times tphl and tplh determines the input to output signal delay

during the high to low and low to high transition of the output respectively. By definition,

tphl is the time delay between the 50% transition of the rising input voltage and the 50%

transition of the falling output voltage. Similarly, tplh is the time delay between the 50%

transition of the falling input voltage and the 50% transition of the raising output voltage.

The rise time is defined as the time required for the output voltage to rise from the

10% level to 90% level. Similarly, the fall time is defined as the time required for the output

voltage to drop from the 90% level to 10% level. Reducing gate delays in digital circuits

allows the data processing at a faster rate and improves overall performance.

Propagation Delay measurements:

Inverter: Here load is given with 0.82f Farad

Supply(v)

0.5

Delay(

2.565

Table 4.1: Delay for Logic circuits

Logic

Delay(

gates

CMOS

PTL

AND

4.58

4.582

53

OR

10.053

9.674

NOR

5.0186

5.1094

NAND

0.1360

0.1466

XOR

5.0206

5.1094

Arithmetic Circuits:

Table 4.2: Delay for Adder circuits

Adder types

Delay(

1 bit adder

10.729

2 bit adder

10.687

4 bit adder

10.675

8 bit adder

7.5203

Subtractor type

Delay(

1 bit

7.73

2 bit

7.672

4 bit

6.943

8 bit

6.878

Multiplexer circuits:

Table 4.4: Delay for Multiplexer circuits

Type

Delay(

2*1 MUX

10.077

8*1 MUX

9.668

Table 4.5: Delay for Multiplier circuit

Type

4 bit multiplier

Delay(

12.151

54

Power Consumption measurement is the most important simulation procedure in this

project since this project objective is to design power efficient circuits. Static and Dynamic

consumptions were measured for CMOS logic circuits and total power in PTL circuits.

Similarly propagation delay measurement, the procedure is also focused on PTL circuits such

as AND/NAND, OR/NOR, XOR/XNOR, Adder, Subtractor, multiplier and divider circuits.

The simulations were carried out single supply voltage and later it will extend to different

ambient temperatures.

4.2.2.1 Static power:

The static power will be obtained in two stages i.e. logic 0 and logic 1, For a clear

understanding of static power consumption, the CMOS inverter modes are considered and are

shown in figure. As shown in Figure 4.2, case 1, if the input is at logic 0, PMOS device is on

and the NMOS device is off. The output voltage is logic 1. Similarly, when logic 1 input is

applied, the NMOS device is on and the PMOS device is off. The output voltage is logic 0.

From the figure 4.2, it is observed that one of the transistors is always off. When the gate

input is in either of these logic states, dc current that flows from VDD to GND, is only the

sub threshold conduction or leakage current. Static power consumption is the product of the

device leakage current and the supply voltage. Total static power consumption is given in

equation.

Power =

55

Compared to the dynamic power consumption, static power consumption has been

considered as negligible. But in modern CMOS processes, due to decrease in supply voltage

and sub threshold voltage, the leakage current increases, causing increase in static power

consumption. Hence in modern CMOS technologies, the static power dissipation component

cannot be neglected.

4.2.2.2 Dynamic power consumption:

In conventional CMOS technologies, the dynamic (switching) power consumption is

the major contributor to the total power dissipation. It is due to switching capacitance,

diffusion capacitance, inter connect capacitances and the junction capacitance. The CMOS

inverter circuit is shown in Figure 4.3. The output capacitor C constitutes the lumped

parasitic capacitances. When input switches from high to low, the NMOS transistor is turned

OFF and PMOS transistor is ON and capacitor C is charged. The total energy that is drawn

from power supply during this charging process is equal to C

dissipated in PMOS transistor and other half is stored in capacitor C. When input switches

from low to high, the NMOS transistor turns ON. The capacitance C discharges through

NMOS transistor. For any logic gate, if inputs to the gate are assumed to switch at a rate of f

times per second, then the average switching power is given as.

=

(4.3)

Where

is the switching activity factor which, indicate the probability of the output

is the

switching frequency.

56

Short circuit power arises when a conducting path exists between supply and ground

i.e. when both PMOS and NMOS are simultaneously ON. Short circuit current flows when

the rise time and fall time of the input signal is slow. The pull-up and pull-down devices

should be sized properly to achieve slow rise or fall time. This component of power

consumption can be significant in pre-charge and evaluate circuits.

Power consumption measurements:

Power consumption is measured based on the static power consumption and dynamic

power consumption. In cadence virtuoso IC6.1.5, the measurement of power is done in

multiple ways like transition power, dc output power and dc output information are taken for

the circuits. All the asserted values are taken with 0.5V as supply and as well as input to the

circuits.

Table 4.6: Inverter circuit with 2p F load at different input voltages with 0.5v supply:

Inputs(V)

Total power( W)

0.5

0.0501

0.4

0.0501

0.3

0.0091

0.2

0.0006

Supply and input

Total power

0.5

4.685e-12

Average Power

Logic gates

CMOS

PTL

OR

0.2167e-9

0.532e-9

AND

0.418e-9

0.2827e-9

NOR

0.113e-9

0.378e-9

NAND

0.2216e-9

0.1595e-9

XOR

0.5066e-9

1.281e-9

57

In the table 4.8, the DPL based logic gates consumes some more power because of the

circuitry i.e. using an inverter and a separate level restorer circuit. So, few logic circuits

consume more power. The Logic gate circuits OR and NOR gates interchanges their

transistors as per the logic function and this increases the driving capability. Therefore,

exhibiting little bit more power than CMOS logic circuits.

Arithmetic circuits:

Table 4.9: Adders average power:

Adder types

Average Power

1 bit adder

6.842e-9

2 bit adder

13.27e-9

4 bit adder

26.12e-9

8 bit adder

73.46e-9

Type

Average power

1 bit Sub

8.918e-9

2 bit Sub

16.44e-9

4 bit Sub

24.96e-9

8 bit Sub

45.65e-9

4 bit Multiplier

56.56e-9

2*1 MUX

2.069e-9

4*1 MUX

2.112e-9

8*1 MUX

6.316e-9

4 Bit Divider

203.3e-9

58

NAND gate

Average power(n watts)

0.25

0.2

0.15

cmos

0.1

dpl

0.05

0

0.3

0.4

0.5

Volatge (V)

Figure 4.4: Power comparison for NAND gate (CMOS & DPL)

Figure 4.4 gives a detailed comparison of power for NAND gate logic circuit. Where,

Dual Pass Transistor logic has consuming low power than CMOS logic circuit. And Figure4.5 shows AND gate circuit power comparison. These figures show that the power

consumption is less in DPL when compared to CMOS circuit.

AND gate

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0

cmos

dpl

0.3

0.4

0.5

Voltage(V)

4.2.3 Power Delay Product:

The Power Delay Product is a fundamental parameter which gives performance of the

circuit. It measures quality performance of gate. It is an average energy required for a CMOS

gate for switching of output voltage from logic one state to another logic state. In other words

59

it is a figure of merit correlated with the energy efficiency of a CMOS logic gate. And it is

called as switching energy, it is the product of average power consumption on a switching

event times the delay. It calculates the energy consumed for switching event and it has

dimension of energy. PDP is taken in consideration when optimization of both power and

performance is possible. The minimization of power delay product is consideration for low

power and high performance application.

PDP

= Average Power

= Delay factor

Power Delay Product is measured for voltages range from 0.3V to 0.5V and figure of

merit of the circuit is identified when Low PDP is obtained.

Table 4.11: CMOS Inverter PDP

Inverter

Supply

0.3

86.121

60.82

5.237

0.35

39.2

79.14

3.102

0.4

25.790

98.61

2.5431

0.45

20.297

118

2.395

0.5

16.402

139.7

2.2914

PDP

(E-12)

Inverter PDP

6

PDP 10^(-18)

5

4

3

Series1

2

1

0

0

0.1

0.2

0.3

0.4

0.5

0.6

Supply voltage(V)

60

Figure 4.6 shows the Power delay product of Inverter with a range of 0.3V to 0.5V.

The figure of merit is high at 0.3V and low at 0.5V, it shows that 0.5V is the effective voltage

for driving inverter logic. The lower the PDP, the more effective the inverter and the logic

circuits.

4.2.3.1 Logic Circuits PDP:

Table 4.12: CMOS AND & OR gate PDP

gate

AND

OR

Supply

0.3

5.0563

123.3

6.234

10.218

83.98

8.581

0.4

5.031

283

14.237

10.066

143.2

14.414

0.5

4.58

418.5

19.167

10.053

216.7

21.784

(E-12)

PDP

(E-12)

PDP

gate

NAND

NOR

Supply

0.3

0.1623

78.83

0.127

5.155

45.03

2.321

0.4

0.1522

152.6

0.2322

5.0331

75.32

3.79

0.5

0.136

221.6

0.3013

5.0186

113.5

5.696

(E-12)

PDP

(E-12)

PDP

gate

XOR

Supply

0.3

5.1603

191.5

9.881

0.4

5.0339

345.3

17.382

0.5

5.0206

506.6

25.434

(E-12)

PDP

61

30

PDP 10^(-16)

25

20

AND

15

OR

10

NOR

XOR

5

0

0

0.1

0.2

0.3

0.4

0.5

0.6

Figure 4.7: Graph of Power delay product for CMOS logic circuits

Figure 4.7 and 4.8 shows that, how power delay product is varying from one voltage

to the other in CMOS logic circuit operating in Sub-threshold. For every logic circuit PDP is

very low for 0.3V and high for 0.5V. It shows the figure of merit of each logic circuit.

0.35

PDP Multiple 10^(-16)

0.3

0.25

0.2

0.15

NAND

0.1

0.05

0

0

0.1

0.2

0.3

0.4

0.5

0.6

Supply voltage

Figure 4.8: Graph of Power delay product for CMOS NAND circuit

In Figure 4.8, it shows that PDP is occurring at very low levels which are more

effective in the terms of figure of merit.

62

gate

AND

OR

Supply

0.3

4.977

94.57

4.706

11.426

89.76

10.25

0.35

4.742

127

6.022

10.766

128.9

13.878

0.4

4.635

164.3

7.615

10.356

220.9

22.877

0.45

4.607

211.3

9.734

10.175

324.9

33.058

0.5

4.582

282.2

12.93

9.674

532.4

51.504

PDP

(E-12)

(E-12)

PDP

gate

NAND

Supply

0.3

0.271

49.72

0.134

6.833

56.39

3.853

0.35

0.214

68.54

0.146

5.860

77.25

4.527

0.4

0.176

86.39

0.152

5.428

154.4

8.381

0.45

0.158

126.42

0.199

5.198

242.2

12.59

0.5

0.146

159.5

0.232

5.109

378.2

19.323

(E-12)

PDP

NOR

(

(E-12)

PDP

gate

XOR

Supply

0.3

11.205

210.1

23.54

0.35

9.065

296.2

26.85

(E-12)

PDP

63

0.4

5.6708

516.2

29.26

0.45

5.1958

856.2

44.486

0.5

5.1094

1281

65.44

PDP multiple of 10^(-16)

70

60

50

40

And

30

OR

NOR

20

XOR

10

0

0

0.1

0.2

0.3

0.4

0.5

0.6

Supply voltage

Figure 4.9: Graph of Power delay product for DPL logic circuits

Figure 4.9 and 4.10 shows that, how power delay product is varying from one voltage

to the other in CMOS logic circuit operating in Sub-threshold. For every logic circuit PDP is

very low for 0.3V and high for 0.5V. It shows the figure of merit of each logic circuit.

PDP multiple of 10^(-16)

0.25

0.2

0.15

0.1

NAND

0.05

0

0

0.1

0.2

0.3

0.4

0.5

0.6

Supply voltage

Figure 4.10: Graph of Power delay product for DPL NAND circuit

64

ADDER Circuits:

Table 4.18: PDP for 1bit and 2bit adder circuits

1Bit adder

2Bit adder

Supply

0.4

11.833

1.112

13.158

11.739

2.391

28.067

0.45

11.164

2.119

23.656

11.104

4.361

48.426

0.5

10.729

6.842

73.409

10.689

13.27

141.81

PDP

(E-9)

PDP

(E-9)

4Bit adder

8Bit adder

Supply

PDP

0.4

11.7162

4.965

58.17

7.8414

17.9

140.36

0.45

11.0899

8.847

98.11

7.7864

29.6

230.4

0.5

10.675

26.12

278.83

7.5203

73.46

552.44

(E-9)

(E-9)

PDP

600

PDP 10^(-15)

500

400

1B adder

300

2B adder

200

4B adder

8B adder

100

0

0

0.1

0.2

0.3

0.4

0.5

0.6

65

Figure 4.11 shows how Power delay product is obtained for arithmetic circuits i.e.

Adder circuits. The power is going on increasing for 4bit adder, 8 bit adder circuits and

power delay product is very low for the 1bit Adder circuit that to for lower voltage 0.3V.

Subtractor circuits:

Table 4.20: PDP for 1bit and 2bit subtractor circuits

1Bit subtractor

2Bit subtractor

Supply

PDP

0.4

8.198

1.488

12.198

8.006

2.673

21.20

0.45

7.421

3.249

24.112

7.789

5.078

39.552

0.5

7.731

8.918

68.949

7.672

16.44

126.12

(E-9)

PDP

(E-9)

4Bit subtractor

Supply

PDP

0.4

6.44

7.478

48.158

0.45

11.32

7.401

83.783

0.5

24.96

6.943

173.29

(E-9)

PDP 10^(-15)

200

180

160

140

120

100

80

60

40

20

0

1B sub

2B sub

4B sub

0.1

0.2

0.3

0.4

0.5

0.6

Supply voltage(V)

66

Multiplexer Circuits:

Table 4.22: PDP for 2*1 and 4*1 multiplexer circuits

2*1 MUX

4*1 MUX

Supply

PDP

0.4

11.426

0.089

1.025

7.84

0.606

4.751

0.45

10.356

0.220

2.287

7.692

0.892

6.864

0.5

10.07

2.069

20.83

7.631

2.112

16.117

(E-9)

PDP

(E-9)

25

PDP 10^(-15)

20

15

2*1 MUX

10

4*1 MUX

5

0

0

0.1

0.2

0.3

0.4

0.5

0.6

Supply voltage(V)

Multiplier Circuit:

Table 4.23: PDP for 4*4 multiplier

4*4 multiplier

Supply

0.4

12.685

13.12

166.4

0.45

12.495

22.28

278

0.5

12.151

56.56

687

PDP

(E-9)

67

4*4 multiplier

800

700

PDP 10^(-15)

600

500

400

300

4*4 multiplier

200

100

0

0

0.2

0.4

0.6

supply voltage(V)

Figure 4.14 is the graph for 4*4 multiplier where power delay product is extensively

increasing by increasing the voltage. Because of larger circuitry, there is large amount of

power dissipating when compared to other arithmetic circuits.

The circuit characterisations are carried out in this chapter and conclude that for a

lower voltage there is a low figure of merit in Dual Pass Transistor Logic based arithmetic

and logic circuits.

68

CHAPTER 5

CONCLUSION AND FUTURE SCOPE

The project results reported in this paper assert that the sub-threshold pass-transistor

logic can be thoroughly implemented in a large and complex hierarchical blocks for ALU(Arithmetic Logic Unit). Results are analysed for basic logic circuits of both PTL and CMOS

design and results confirmed that PTL circuits are power efficient when compared to the

CMOS version for sub-threshold design. This project however, was focused on arithmetic

and logic circuits.

This report provides solid assessment of basic logic circuits that can operate in subthreshold supply for pass-transistor style logic design. It is also clear that measurements of

propagation delay and power consumption are feasible for such designs. Special attention

was taken for PTL styles to avoid glitches.

The measurement of power is taken with a voltage range 0.3 to 0.5 as supply

and power that consumed in the circuits is in Nano watts and Pico watts. The DPL circuits are

designed with the use of PMOS and NMOS transistors together. Though original logic

implementation of DPL requires few transistors, for example, designing of an AND gate uses

only 1 PMOS and 1 NMOS transistor. Further, circuitry was added for minimizing level

degradation even though it increases the transistor count.

Future Scope:

Technology size can be another prospect for future work. The current project was

carried out in Cadence virtuoso IC6.1.5 180nm technology. The third process that is

described here may be extended to realise the Dual Pass Transistor logic with sub-micron

technologies like 90nm. However it is not very clear whether this can be extended to

technologies like 22nm and below. It is known that the device characteristics at lower

technologies are somewhat different from those realised at higher technologies. In view of

this, one should develop DPL or similar to DPL logic which will overcome some of the

drawbacks that likely to arise. However, in the long run it is necessary to adapt newer

technology sizes to maintain the design considering the advantages offered by PTL.

It may be further seen from this report that the speed of operation of sub-threshold

circuits is limited. Perhaps in future this problem may be solved by making use of the

Substrate biasing [7]. It is called as Variable Threshold MOS (VTMOS) operation.

69

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Reto Zimmermann and Wolfgang Fichtner, Low-Power Logic Styles: CMOS versus

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[4]

Li Ding, Zhiyong Zhang, Shibo Liang, Tian Pei, Sheng Wang, Yan Li, Wewei Zhou,

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