# ANALOG ELECTRONICS ASSIGNMENT (EE001-3-2-AE

)

NAME : MAULANA AJI MARWANTO

ID NUMBER : TP017422

INTAKE CODE : UC2F0909ME

SUBMISSION DATE : 28 JANUARY 2010

LECTURER NAME : HARIKRISHNAN RAMIAH

SCHEMATIC

Figure1: Schematic circuit

I

୍୬

I

୭୳୲

I

ି

ൌ Ͳ

v

ି

െ v

୍୬

R

ଵ

v

ି

െ v

୳୲

R

ଷ

Ͳ ൌ Ͳ

Ͳ െ v

୍୬

R

ଵ

Ͳ െ v

୳୲

R

ଷ

Ͳ ൌ Ͳ

െ v

୳୲

R

ଷ

ൌ

v

୍୬

R

ଵ

v

୳୲

v

୍୬

ൌ െ

R

ଷ

R

ଵ

v

ା

െ v

୍୬

R

ଶ

Ͳ Ͳ ൌ Ͳ

v

ା

R

ଶ

ൌ

v

୍୬

R

ଶ

v

୳୲

R

ଶ

ൌ

v

୍୬

R

ଶ

v

୳୲

v

୍୬

ൌ

R

ଶ

R

ଶ

v

୳୲

v

୍୬

ൌ ͳ

Calculation for R1 and R3

Ideal OPAMP condition (virtual ground) v

ା

؆ v

ି

؆ Ͳ

Apply KCL to the inverting node:

Calculation for R2

Ideal OPAMP condition (virtual ground) v

ା

؆ v

ି

؆ Ͳ

Apply KCL to the non-inverting node

So,

ో౫౪

ൌ െ

ୖ

య

ୖ

భ

ൌ

ୖ

మ

ୖ

మ

Or we can said if R

1

= R

2

= R

3

Then I choose the all of the R value is 10 K

ͳ

R

ଷ

C

ଵ

߱

C

ଵ

൏

ͳ

R

ଷ

ሺʹfሻ

C

ଵ

൏

ͳ

ͷ ሺʹ ൈ Ͳሻ

C

ଵ

൏ ͳǤͳͳ x ͳͲ

ିସ

F

ሺ R

ସ

i ሻC

ଶ

ൌ

Ɏ

ͷɘ

C

ଶ

ൌ

Ɏ

ͷሺʹfሻ

ͳ

ሺ R

ସ

i ሻ

C

ଶ

ൌ

Ɏ

ͷሺʹxͲሻ

ͳ

ሺ ͳͲͲͲͲ Ͳ ሻ

C

ଶ

ൌ ͷʹǤ͵ ൈ ͳͲ

ି

F

C

ଶ

ൌ ͷʹǤ͵ ρF

Calculation for C1

Calculation for C2

A1

A2

D2

D1

V1

5 Vrms

50 Hz

0°

R3

R2

R1

0

13 12

6

7

0

8

A3

D4

C2

R4

D3

C1

6

0

7

8

1

V1

12 Vrms

60 Hz

0°

R1

10kȍ

R2

10kȍ

R3

10kȍ

R4

10kȍ

C1

3.3pF

D3

D1N4148

D4

D1N4148

D2

D1N4148

D1

D1N4148

GND

GND

GND

C2

1µF

U1

LM107J

3

2

4

7

6 U3

LM107J

3

2

4

7

6

U2

LM107J

3

2

4

7

6

SIMULATION RESULT

Figure 3: V out (simulation)

Figure 4: Vs out (simulation)

Figure 5: V peak (simulation)

Figure 2: Simulation circuit

HARDWARE OUTPUT

1 box in the oscilloscope is equal with 1 s. The frequency difference from simulation and the practical is:

݂

௦

ൌ

ଵ

ଵ

ൌ ͳ ܪݖ

݂

ൌ

ଵ

ଷ௦

ൌ ͲǤ͵͵ ܪݖ

Figure 7: V out (practical)

Figure 8: Vs out (practical)

Figure 9: V peak (practical)

R1

A1

A2

A3

C2

D4

R4

D3 C1

R3

R2

D2 D1

Figure 6: Schematic circuit

A2

V1

5 Vrms

50 Hz

0°

R2

0

1

2 3

A1

A2

D2

V1

5Vrms

50Hz

0°

R3

R1

0

0

6

1 2

3

4

A1

A2

D2

D1

V1

5Vrms

50Hz

0°

R3

R2

0

0

1

2

3

4

5

A1

A2 D2

D1

V1

5Vrms

50Hz

0°

R1

0

2

0

3

4

5

1

EXPLANATION

y Posi ive h l y le on the AC signal

When positi e input volt e si nal going to OP-AMP A1 the output in A1 is inverted to the negative output

signal voltage. The negative voltage signal is now able to pass through to the D1 because the negative

voltage signal forward-biased and D2 is in Reverse-bias, so we don¶t have some signals passing through on

the that place. Therefore, the negative signal will going back because there is a feedback to the inverting

input of A1 and change to positive signal voltage. And then the signal will pass through D2. This signal

will be same at V

out

because input for Op-Amp A2 that acts as a buffer is non-inverting.

When positive input voltage signal going to this part, the input voltage signal will go to OP-AMP A2

directl and will not pass through Diode (D2) because it¶s an open circuit. Positive voltage signal can be

obtain in V

out.

y Negative hal cycle in the AC Signal

When negative input voltage signal going to the output in Op-Amp A1, it¶s inverted to positive output

voltage signal. This voltage signal will pass to the D2, because of the Forward-biases diode. Then the

voltage signal will pass to Op-Amp A2, positive voltage signal can be obtain in V

out.

When negative input voltage signal will going straight away to OP-AMP A2 and will also pass through D2

and D1. This is because the negative voltage signal has Forward-biases at the D2 and D1. Both negative

voltage signals will feedback to the same path.

A3

D4

C2

R4

D3

C1

6

0

7

8

1

y Peak Detector

During the positive half-cycle the output of Op-Amp A3 is positive because the input is non-inverting.

Therefore, D3 is in Reverse-bias and D4 is in Forward-bias. C2 is charges through D4 until V

peak

reaches the

highest positive value of V

out

. Ideally V

out

will be decay or discharge as fast as the envelope of V

out

changes.

That decay will be through the R4 and D3. And because of this decay, there is a small peak formed in signal

wave.

CONCLUSION

Full wave Rectifier operational amplifier with peak detector circuit is the circuit that has a function to

detect the amplitude of audio signal.

During the assignment, we must do the calculation well, because if we don¶t do that we can¶t reach the

signal waveform that we suppose to find them in the basic shape of Full wave rectifier. And there are some

different output results if we compare from the simulation and the practical. It happen because of there aren¶t a

same component when I search in the market .So, I used the different component in my practical.

V

out

V

peak