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A

B

C

D

E

ZZZ

PCB

MB
DA80000TI10

ZZZ1
1

1

DDR

Samsung
X76-S@

X76418BOL01

ZZZ1
DDR

Hynix

X76-H@

Compal Confidential

X76418BOL02

S1

Frame

2

2

Nvdia(T30L) + DDRIIIL
V0JET (A210)_ LA8981P

REV: 1.0

2012-06-11

※The content in this document contains confidential information of Compal Electronics, Inc.
that is protected under all applicable trade secrets laws and regulations.
If you are not the intended recipient or otherwise authorized to receive such information,
please do not copy, distribute or otherwise use the information contained herein and please
destroy this communication accordingly.

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/05/20

Deciphered Date

2012/01/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Cover Page
Size
C
Date:

Document Number

V0JET(A210)-LA8981P
Wednesday, June 13, 2012
E

Sheet

1

of

35

Rev
1.0

A

B

C

D

E

Compal Confidential
Model Name : NVIDIA T30L System Block Diagram
12MHz
32KHz
DDR3L
1GB

1

Power ON

PMU
CORE_PWR_REQ
TPS6591104
CPU_PWR_REQ

JTAG

1

Debug
Test Point

SYS_RESET_N

VIN

PWR_I2C
PMU_32K_IN
PWR_I2S
UART4
TPS62361

Audience
eS305

Audio Codec
WM8903

EEPROM
AT24C02C

Thermal
NCT72

BATTERY

2

2

Nvidia
Touch Panel
Control

T30L

GEN2_I2C

LVDS

LVDS Transmitter
SN75LVDS83

Client

Standard USB

Host

CAMERA
2M

UART2

Broadcom
BCM47511

UART3
SDMMC3

AzureWave
AW-NH660

LCD

Micro USB
3

Speaker x 2
(1W)

GPS Antenna

GEN2_I2C
10.1" LCD
1280*800

Audio AMP
APA2010

MIC & HP Jack

BT/WLAN Antenna
3

CIS(MIPI)
CAM_I2C

GEN1_I2C

SDMMC4
(1.8V)
eMMC

SDMMC1
(3.3V)

GYRO Sensor IME G-Sensor
KXTF9-4100
MPU-3050

HS uSD slot

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/05/20

Deciphered Date

2012/01/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

SYSTEM BLOCK
Size
C
Date:

Document Number

V0JET(A210)-LA8981P
Wednesday, June 13, 2012
E

Sheet

2

of

35

Rev
1.0

5

4

3

2

1

V0JET (A210)
Voltage Rails

V0JET

D

VDD_1V8_PMU_VRTC

VDD_PMU_LDO4
(VDD_1V2_RTC_TEGRA)
VDD_PMU_LDO5
(+VDD_3V3_SDMMC1_TEGRA)
VDD_PMU_LDO6
(+AVDD_1V2_DSI_CSI_TEGRA)
VDD_PMU_LDO7
(+AVDD_1V1_PLL_TEGRA)
VDD_PMU_LDO8
(+VDD_1V0_DDR_HS_TEGRA)

L: A211

H:

A210

PCB_ID1

H

H

H

L:

H:

NH660

PCB_ID2

H

H

H

L:

H: A210/A211

PCB_ID3

H

H

H

L:

H: A210/A211

ON

V0JET

Vender PN

ON

K4B2G0846D-HYH9
DDR3L (Samaung)
H5TC2G83CFR-H9A
(Hynix)

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

DDR RX power rail

OFF

OFF

ON

T30 VDD_CPU Power

OFF

OFF

ON

T30 VDD_CORE Power

OFF

OFF

DDR power rail

OFF

OFF

OFF

OFF

ON

OFF

OFF

ON

OFF

OFF

ON

Power for RTC and always-on core logic

VDD_1V2_MEM
VDD_1V35_DDR3_MEM
VDD_1V0_GEN
VDD_1V2_SOC
VDD_1V35_DDR3_MEM
VDD_PMU_LDO1
VDD_PMU_LDO2
VDD_PMU_LDO3

H

ON

Power for always-on

VDD_5V0_SBY

PVT

H

IDLE

AC or battery power rail for power circuit.

B+

DVT

H

DCIN

Adapter power supply (12V)

VIN

EVT

PCB_ID0

Standby

ACIN

Power Plane

T30 VDD_RTC power rail

OFF

OFF

ON

T30 VDDIO_SDMMC1 power rail

OFF

OFF

ON

T30 AVDD_DSI power rail

OFF

OFF

T30 AVDD_PLL power rail

OFF

OFF

T30 VDD_DDR_HS power rail

OFF

OFF

+5VS

5V System power rail

OFF

OFF

+3VALW

3.3V System power rail

OFF

OFF

OFF

OFF

MP

Acer PN

NAND_D4

NAND_D5

KN.2GB0B.038

0

0

KN.2GB0G.003

1

0

EDJ2108EDBG-DJ-FEl
KN.2GB09.001
(Elpida)

0

1

DVT

PVT

Board ID0

V0JET

EVT
0

1

0

1

Board ID1

0

0

1

1

D

MP

C

C

+3VS

3.3V power rail for standby mode
1.8V System power rail

OFF

OFF

+AVDD_1V8_USB_PLL_TEGRA

T30 USB power rail

OFF

OFF

+T30S_USB1
+VDD_2V85_EMMC
+LEDVDD
+LCDVDD
+VDD_1V8_AUDIO_LDO
+2.8V_2M_AVDD_R
+VDD_3V3_SDCARD
+VDD_CAM_1V8
+VDD_3V3_FUSE_TEGRA
+VDD_1V8_SENSOR
+VDD_3V3_SENSOR

USB power rail

OFF

OFF

OFF

OFF

LCD power rail

OFF

OFF

LCD power rail

OFF

OFF

Audio power rail

OFF

OFF

CAMERA power rail

OFF

OFF

Micro SD power rail

OFF

OFF

CAMERA power rail

OFF

OFF

T30 VPP_Fuse power rail

OFF

OFF

3.3V Sensor power rail

OFF

OFF

3.3V Sensor power rail

OFF

OFF

VDD_1V8_GEN

Core voltage for EMMC

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/05/20

Deciphered Date

2012/01/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Notes List
Size
C
Date:

Document Number

V0JET(A210)-LA8981P
Wednesday, June 13, 2012
1

Sheet

3

of

35

Rev
1.0

7) VDAC_VREF need check with WC of GPIO AT24C02C-XHM-T_TSSOP8 VDAC_RSET need check with SW Roger AA5 AA6 T30L-P-A3-1.2G_FCBGA728 Issued Date Compal Electronics.31.8V) 20mA VDD_1V8_GEN HDMI_RSET D8 1 2 HDMI_RSET AK3 AK4 2 AE4 AF4 @ R26 1K_0402_1% C5 4.31.8V) VDAC_R VDAC_G VDAC_B Z Z Z Z Z Z Z Z A9 C7 PU PU C9 Z EMMC_DA0 EMMC_DA1 EMMC_DA2 EMMC_DA3 EMMC_DA4 EMMC_DA5 EMMC_DA6 EMMC_DA7 (14) (14) (14) (14) (14) (14) (14) (14) EMMC_CLK (14) EMMC_CMD (14) EMMC_RST# (14) AB7 AA9 AA7 A BOARD_ID_WP (7) PWR_I2C_SCL (16.3V6M 2 T30L-P-A3-1.4] -->0000 H5TC2G83CFR-H9A [7.2/1. INC.1U_0402_10V7K B SDMMC4_CLK SDMMC4_CMD +VDD_1V8_SYS_TEGRA 2 C115 U54 1 2 3 4 A0 A1 A2 GND 1 VCC WP SCL SDA 8 7 6 5 SDMMC4_RST* 9/22 VDAC AK6 AVDD_VDAC (2.2G_FCBGA728 1 LCD_PWR0 LCD_PWR1 LCD_PWR2 PU PD PU PU 100K_0402_5% LCD_M1 PD R1 K4B2G0846D-HYH9 [7.5 4 4/22 GMI C LCD_DC0 LCD_DC1 CRT_HSYNC CRT_VSYNC DDC_SCL DDC_SDA HDMI_INT AG12 LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 LCD_D06 LCD_D07 LCD_D08 LCD_D09 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 (15) (15) (15) (15) (15) (15) (15) (15) (15) (15) (15) (15) (15) (15) (15) (15) (15) (15) GMI_A16 GMI_A17 GMI_A18 GMI_A19 GMI_CS0* GMI_CS1* GMI_CS2* GMI_CS3* GMI_CS4* GMI_CS6* GMI_CS7* GMI_ADV* GMI_CLK GMI_RST* GMI_WAIT GMI_WP* GMI_IORDY PD AJ9 AG10 AH12 PD PD PD AG15 AJ15 AC10 AJ13 AH10 PU PU PU PU PU AE15 AE12 PD PD AD13 AJ16 PU PU AG14 AJ10 Z Z AG13 Z GMI_OE* GMI_WR* LCD_PWM_OUT (15) DISPOFF# (15) EN_T30S_FUSE_3V3 (23) IMG_EN (15) PCB_ID0 PCB_ID1 PCB_ID2 E6 1 A4 0 GMI_DQS BOOT_PD 0_0402_5% R403 1 1 1 2 X76@ 2 1 100K_0402_5% NAND_D5 R43 2 X76@ 1 100K_0402_5% NAND_D6 R84 2 @ 1 100K_0402_5% NAND_D7 R85 2 @ 1 100K_0402_5% NAND_D4 R5 2 X76@ 1 100K_0402_5% NAND_D5 R6 2 1 100K_0402_5% NAND_D6 R7 2 1 100K_0402_5% NAND_D7 R8 2 1 100K_0402_5% PCB_ID0 R63 2 PCB_ID1 R87 2 D BOARD_ID1 R78 2 R88 2 V10 M R17 GEN2_I2C_SCL (15) GEN2_I2C_SDA (15) 1 100K_0402_5% A210@ 1 100K_0402_5% 1 100K_0402_5% R12 PCB_ID0 R152 2 PCB_ID1 R153 2 PCB_ID2 R154 2 1 100K_0402_5% A211@ 1 100K_0402_5% A211@ 1 100K_0402_5% A211@ BOARD_ID0 R79 BOARD_ID1 R89 2 @ 2 @ EN_WIFI_VDD 2.1 DVT PCB_ID[3.2G_FCBGA728 1 2 C6 2 1 VDDIO_SDMMC4 SDMMC4_DAT0 SDMMC4_DAT1 SDMMC4_DAT2 SDMMC4_DAT3 SDMMC4_DAT4 SDMMC4_DAT5 SDMMC4_DAT6 SDMMC4_DAT7 0.1U_0402_10V7K 0. Inc.boot strap EMMC 0001 NAND[D4:D7] -..00] --> 1111 +VDD_3V3_GMI_TEGRA T30L-P-A3-1.29.2K_0402_1% 1 100K_0402_5% NH660@ 1 100K_0402_5% R10 +VDD_3V3_GMI_TEGRA 1 100K_0402_5% R100 2 BOARD_ID0 SD_DET# (21.2G_FCBGA728 4 3 2 Title T30L-LCD/CRT/HDMI/NAND Size C Date: Document Number V0JET(A210)-LA8981P Wednesday.17.7) +VDD_3V3_GMI_TEGRA FORCE_RECOVERY# NOR_BOOT R22 2 R11 GEN2_I2C_SCL GEN2_I2C_SDA R38 PCB_ID2 Z Z +VDD_3V3_GMI_TEGRA NAND_D4 A210@ 100K_0402_5% 1 R24 +VDD_3V3_GMI_TEGRA TS_PWR_EN 2 100K_0402_5% +VDD_3V3_GMI_TEGRA G3 Z TS_RST# (15) +VDD_3V3_GMI_TEGRA G5 G7 1 100K_0402_5% Change BOM structure @ R18 100K_0402_5% TEMP_ALERT# (7) 2... June 13.3V) HDMI_TXCN HDMI_TXCP HDMI_TXD0N HDMI_TXD0P @R420 0_0402_5% 2 HDMI_TXD1N HDMI_TXD1P HDMI_TXD2N HDMI_TXD2P AF7 AVDD_HDMI_PLL 1 (1.0] -->0.ram code For Boost Strap 2 2 VDDIO_LCD_1 VDDIO_LCD_2 C2 1 NAND_D0 BOOT_PD 1 2 2 C4 Z Z Z Z Z Z Z Z PD PD PD PD Z Z Z Z 1 AB13 AC13 1 2 F8 G6 D3 E4 G2 D2 B3 G1 H6 F4 E7 F3 F5 F7 J2 F1 2 20mA 1 GMI_AD00 GMI_AD01 GMI_AD02 GMI_AD03 GMI_AD04 GMI_AD05 GMI_AD06 GMI_AD07 GMI_AD08 GMI_AD09 GMI_AD10 GMI_AD11 GMI_AD12 GMI_AD13 GMI_AD14 GMI_AD15 2 C1 0.. INC.8/3.7U_0402_6.7) PWR_I2C_SDA (16.2G_FCBGA728 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. INC.3V) 110mA +3VS 0.17.1U_0402_10V6K PN:SA00004KS00 2k bit A 47K_0402_1% 2 FORCE_RECOVERY# D 2 G R54 1M_0402_1% 3 10/22 HDMI R90 1 U55 3 1 (22.1U_0402_10V7K +3VS 1 VDDIO_GMI_1 VDDIO_GMI_2 VDDIO_GMI_3 1 C147 C1 C2 D1 2 2 U1I (1.7) VOL_DOWN# B A Y 1 4 Q44 S TR DMN3150LW-7 1N SOT-323-3 S Vth=1.8V) @R425 0_0402_5% HDMI_PROBE B AJ4 AH4 AH6 AJ6 AK7 AJ7 +VDD_1V8_SDMMC4_TEGRA U1E AG1 SDMMC4 : eMMC 5/22 SDMMC4 AH3 (1.0 .33. 2012 1 Sheet 4 of 35 Rev 1. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.1U_0402_10V7K 12P_0402_50V4Z 12P_0402_50V4Z 2 8/22 LCD D 1 U1D RF +VDD_3V3_LCD_TEGRA 2 +VDD_3V3_GMI_TEGRA LCD_PCLK (15) C3 2 3 +VDD_3V3_GMI_TEGRA 27NH_LQG15HS27NJ02D_5%_0402 2 1 C165 C164 4.29.2K_0402_1% EN_3V3_EMMC1 (14) EN_3V3_SDCARD (21) 2 X76@ R14 1 LVDS_SHTDN# (15) R2 +VDD_3V3_GMI_TEGRA TS_INT# (15) EN_SENSOR_3V3 CHARGER_STAT (27) 2 C3 BOOT_PD 2 PU D4 B4 D5 F2 G4 VIB_EN_T30S (22) TS_PWR_EN (15) EN_VDDLCD_T30S (15) EN_WIFI_VDD (25) 10K_0402_5% R1411 1 @ PU PU 1 BOARD_ID0 1 BOARD_ID1 J4 K7 F6 A3 D6 J5 J7 1 100K_0402_5% EN_SENSOR_3V3 (23) H4 J6 C4 J3 1 PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD LCD_DE (15) LCD_HSYNC (15) LCD_VSYNC (15) 100K_0402_5% LCD_SCK LCD_CS0* LCD_CS1* LCD_SDOUT LCD_SDIN AE8 AF12 AD10 AK15 AK16 AK10 AK12 AG16 AG8 AD15 AK9 AJ12 AF9 AC12 AD12 AE18 AF13 AH15 AE9 AE10 AH13 AH9 AE13 AK13 NV_LCD_PCLK 2 1 100K_0402_5% C 1 100K_0402_5% V10 M DVT BOARD_ID[1. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.4] -->0001 NAND_D4 NAND_D5 NAND_D6 NAND_D7 2 LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 LCD_D06 LCD_D07 LCD_D08 LCD_D09 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_D18 LCD_D19 LCD_D20 LCD_D21 LCD_D22 LCD_D23 AG11 AH16 AG9 AF16 AF10 NAND_D0 Change BOM structure to DDR3L 1 1 LCD_PCLK LCD_WR* LCD_DE LCD_HSYNC LCD_VSYNC (1.33.4V 74AUP1G02GW_TSSOP5 AVDD_HDMI_1 AVDD_HDMI_2 1 (3. 5 B9 B6 C6 A6 B7 A7 D7 D9 U1J 0.3V6M L49 LCD_PCLK_R 1 1 3300P_0402_50V7K R453 2 1 47_0402_5% NV_LCD_PCLK R23 47K_0402_1% 2 +VDD_1V8_SYS_TEGRA 9/29 Leakage Issue U1K 2 (22.8 ~ 3. Compal Secret Data Security Classification T30L-P-A3-1.7U_0402_6.7) VOL_UP# 1 5 Modify R10&R11 from mount to unmount G Vcc T30L-P-A3-1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS..3V) NAND[D0:D3] -.

12) DDR_WE# (11.25/1.7U_0402_6.35/1.12) 1 10K_0402_5% R55 QUSE0 QUSE1 QUSE2 QUSE3 2 +VDD_1V35_MEM_TEGRA DDR_RESET# (11.2_0402_1% SDMMC3_COMP_PUR31 1 SDMMC3_COMP_PDR32 1 33.0] (1.2_0402_1% T30L-P-A3-1.7U_0402_6.2G_FCBGA728 A IC_USB_REXT V8 A Issued Date Compal Electronics.0 . INC.12) DDR_CS0# (11.2V) (11.8/2.7U_0402_6.8/2.3V6M C110 2 1 1U_0402_10V6K C109 2 1 1U_0402_10V6K C111 1 1U_0402_10V6K C30 1 2 +VDD_1V8_SDMMC3_TEGRA VDD_DDR_RX +VDD_1V0_DDR_HS_TEGRA T30L-P-A3-1.2P_0402_50V8 W6 1 DDR_CLKN 2 (1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.12) DDR_BA1 (11.8V) 0.00V) VDD_DDR_HS_1 VDD_DDR_HS_2 DDR_DQS0N DDR_DQS0P 4.3V6M C17 1 (1..12) 0 D19 Trace 50ohm DDR_WE_N T30L-P-A3-1.3V6M 2 4.12) DDR_CLKP (11.8/3.3_0402_1% 2 R21 45.01U_0402_25V7 IC_USB_DN IC_USB_DP 9 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 50OHM_NETCLASS2 DDR_DM0 (11) DDR_DM1 (12) DDR_DM2 (11) DDR_DM3 (12) 50OHM_NETCLASS2 50OHM_NETCLASS2 50OHM_NETCLASS2 B12 A12 DDR_DQS1_PAIR E24 D23 DDR_DQS2_PAIR C DDR_DQS0N (11) DDR_DQS0P (11) DDR_DQS0_PAIR DDR_DQS1N (12) DDR_DQS1P (12) DDR_DQS1_PAIR DDR_DQS2N (11) DDR_DQS2P (11) DDR_DQS2_PAIR E12 D11 DDR_DQS3N (12) DDR_DQS3P (12) DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 DDR_A[14.8 ~ 3.3V) A27 C23 2 +3VS 4.12) F19 Trace 50ohm E18 DDR_CKE0 (11.1 15/22 HSIC V6 V7 DDR_CKE0 DDR_CKE1 2.7U_0402_6.12) DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_RAS# (11. June 13.2_0402_1% K6 SDMMC1_COMP_PD 2 1U_0402_10V6K SDMMC1_COMP_PU C 33.. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.5) G16 G19 H15 H16 H18 H19 H21 H22 J15 J16 J18 J19 J21 J23 K22 K23 VDDIO_DDR_01 VDDIO_DDR_02 VDDIO_DDR_03 VDDIO_DDR_04 VDDIO_DDR_05 VDDIO_DDR_06 VDDIO_DDR_07 VDDIO_DDR_08 VDDIO_DDR_09 VDDIO_DDR_10 VDDIO_DDR_11 VDDIO_DDR_12 VDDIO_DDR_13 VDDIO_DDR_14 VDDIO_DDR_15 VDDIO_DDR_16 DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31 +VDD_3V3_SDMMC1_TEGRA +VDD_3V3_DDR_RX_TEGRA 50mA 1 2 CP_GPIO (27) DDR_DM0 DDR_DM1 DDR_DM2 DDR_DM3 2 VDD_PMU_LDO8 30mA E10 H9 C24 1 2 : WIFI (1.2G_FCBGA728 W7 DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3 DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7 DDR_DQ8 DDR_DQ9 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31 G18 Trace 50ohm D17 Trace 50ohm DDR_RAS_N DDR_CAS_N +VDD_1V8_SDMMC3_TEGRA 2 C22 D12 E22 G12 D20 G15 A18 D14 B19 A16 C21 A15 D15 C16 E16 D18 E15 A19 B16 DDR_A00 DDR_A01 DDR_A02 DDR_A03 DDR_A04 DDR_A05 DDR_A06 DDR_A07 DDR_A08 DDR_A09 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 U1O D24 B25 A25 D21 A24 A21 A22 B22 C15 A13 C12 B13 C13 A10 B10 C10 G22 D22 D25 F23 G21 E25 F24 F22 F13 G13 G10 D13 G9 F10 D10 F12 1 +VDD_1V35_MEM_TEGRA Note:Place at the T-point DDR_COMP_PU 2 W8 W9 DDR_COMP_PD B21 DDR_COMP_PU R35 1 2 40.3V6M +VDD_1V35_MEM_TEGRA +VDD_1V35_MEM_TEGRA U1C VDD_1V35_DDR3_MEM U1P PU PU 1 2 SDMMC_CLK (21) SDMMC_CMD (21) 1 2 1 2 0.7U_0402_6.12) D16 Trace 50ohm F18 DDR_ODT0 (11. 2012 1 Sheet 5 of 35 Rev 1.2_0402_1% SDMMC1_COMP_PUR29 1 L4 DDR_DQS1N DDR_DQS1P DDR_DQS2N DDR_DQS2P DDR_DQS3N DDR_DQS3P 6/22 SDMMC3 (1.3V) J1 C14 20mA 0.8 ~ 3. INC. Inc.2/1.2G_FCBGA728 V9 7 11 12 B24 C24 DDR_CLKP DDR_RESET U1N 5 6 10 B18 DDR_CLKN C18 DDR_CLKP DDR_CLK_N DDR_CLK C2674 HSIC_REXT 4 F16 Trace 50ohm E19 Trace 50ohm DDR_ODT0 DDR_ODT1 HSIC_DATA HSIC_STROBE 2 3 F15 Trace 50ohm E21 Trace 50ohm F21 Trace 50ohm DDR_CS0_N DDR_CS1_N VDDIO_HSIC D 1 2 U1M (1.3_0402_1% AVDD_IC_USB 8 DDR_DQS0_PAIR C19 1 1 T30L-P-A3-1.1U_0402_10V7K 2 VDDIO_SDMMC1 4.3V6M 2 1 1U_0402_10V6K 1 C21 2 C20 1 1U_0402_10V6K PD Z 2 C19 K5 N5 2 1U_0402_10V6K CLK2_OUT CLK2_REQ Z Z 1 1U_0402_10V6K GPIO_PV2 GPIO_PV3 M5 M1 C18 SDMMC1_COMP_PDR30 1 33.7U_0402_6.7U_0402_6.1U_0402_10V7K M6 N6 SDMMC1_CLK SDMMC1_CMD SDMMC_DAT0 (21) SDMMC_DAT1 (21) SDMMC_DAT2 (21) SDMMC_DAT3 (21) C15 SDMMC1_DAT0 SDMMC1_DAT1 SDMMC1_DAT2 SDMMC1_DAT3 PU PU PU PU C22 K1 K3 K2 K4 0.2G_FCBGA728 SDMMC3 (2.12) DDR_CAS# (11.5 4 3 2 1 2 1 C13 C12 1 2 4. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.12) B DDR_BA0 (11.3V6M VDD_1V8_GEN L27 J26 J28 K26 J27 K25 K24 K28 SDMMC3_DAT0 SDMMC3_DAT1 SDMMC3_DAT2 SDMMC3_DAT3 SDMMC3_DAT4 SDMMC3_DAT5 SDMMC3_DAT6 SDMMC3_DAT7 WFMMC_DAT0 (25) WFMMC_DAT1 (25) WFMMC_DAT2 (25) WFMMC_DAT3 (25) EN_3V3_EMMC (14) R64 2 @ G30 PU J29 PU SDMMC3_CLK SDMMC3_CMD J25 SDMMC3_COMP_PU K27 SDMMC3_COMP_PD B PU PU PU PU PU PU PU PU 1 100K_0402_5% WFMMC_CLK (25) WFMMC_CMD (25) 33.3V6M 1 D 4.2_0402_1% DDR_BA0 DDR_BA1 DDR_BA2 NV DG V1.2_0402_1% B15 DDR_COMP_PD R36 1 2 40.12) D27 D26 E9 F9 DDR_CLKN (11.12) R33 1 2 0_0402_5% R34 1 2 0_0402_5% 2 C482 16/22 IC_USB DDR_QUSE0 DDR_QUSE1 DDR_QUSE2 DDR_QUSE3 R20 45.12) DDR_A15 (11. 5 4 3 2 Title T30SL-OSC/PLL/SYS/DDR Size C Date: Document Number V0JET(A210)-LA8981P Wednesday.12) DDR_BA2 (11.7U_0402_6.3V) 24mA C26 1 1 2 2 G24 VDDIO_SDMMC3 C25 0. INC.0] 50OHM_NETCLASS2 (11. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.1U_0402_10V7K 4.1U_0402_10V7K 17/22 SDMMC1 VDD_PMU_LDO5 50OHM_NETCLASS2 3/22 DDR3/LPDDR2 740mA DDR_DQ[31.3V6M SDMMC1 : SD card +VDD_3V3_SDMMC1_TEGRA 1 C11 C10 2 4.

2G_FCBGA728 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. INC.A B C D E U1L 11/22 USB +AVDD_3V3_USB_TEGRA U12 1 C27 1 +VDD_1V8_AUDIO_TEGRA 2 U1Q RF note 13/22 AUDIO CLK1_OUT CLK1_REQ (1.1A 1 10MIL R5 R1423 1 USB3_VBUS 2 0_0402_5% @ Q18 AO3413_SOT23-3 +T30S_USB1 2 T30L-P-A3-1.1U_0402_10V7K 2 VDDIO_AUDIO 1 1 C30 2 C28 20mA 0.9_0402_1% 2012/05/20 Deciphered Date 2012/01/09 Title T30L-USB/SDIO/UART/AUDIO 2 Issued Date Compal Electronics. A B C D Size C Date: Document Number V0JET(A210)-LA8981P Wednesday.1U_0402_10V6K R42 1M_0402_1% D18 @ C2673 1 2 USB_REXT 1 1K_0402_1% T30L-P-A3-1.3V) 130mA +3VS V5 USB2_VBUS T6 T5 USB2_DN USB2_DP W4 ACC2_DETECT CORE_PWR_REQ BATT_LEARN (27) COMPASS_DRDY (19) 2 2 SC400003Z00 R1432 1 +USB_CLIENT 1 3 2 G 2 EN_T30S_USB1 0. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.7U_0402_6.7) CORE_PWR_REQ SPI1_SCK SPI1_CS0* SPI1_MOSI SPI1_MISO 3 1 2 2 6 R323 1M_0402_1% (1. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.2K_0402_1% U1G 18/22 CAM 1 @ 39P 50V J NPO 0402 R40 2.2V) AB6 C32 0.3V) 20mA VDD_1V8_GEN AG3 AG2 R41 2.3V6M C31 3 S 2 G U1H 7/22 DSI & CSI 56mA 1 D 3 +AVDD_1V2_DSI_CSI_TEGRA For HOST USB R39 BZT52-B5V6S_SOD323-2 2 +AVDD_3V3_USB_TEGRA VDD_PMU_LDO6 USB_HOST_DN (21) USB_HOST_DP (21) V4 ACC3_DETECT 1 2 0_0402_5% +T30S_USB1 @ V3 V2 USB3_DN USB3_DP 1 0.7U_0402_6.3V6M U1Q is not place on grid .2G_FCBGA728 DSI_CLKAN DSI_CLKAP RF note CAM_I2C_SCL (20) CAM_I2C_SDA (20) 1 C187 2 2 2 1 2 2M_CAM_DA1#_R (20) 2M_CAM_DA1_R (20) AH2 AH1 C34 AD1 AE1 AD9 0.2G_FCBGA728 Vth = 1.5 S HP_DET# (17) CDC_IRQ# (17) EN_ES305_OSC (16) GYRO_INT_R (19) D SPI2_SCK SPI2_CS0* SPI2_CS1* SPI2_CS2* SPI2_MOSI SPI2_MISO AA2 AA3 R44 453_0402_1% 4 DSI_CSI_RUP AG4 DSI_CSI_RUP AJ3 DSI_CSI_RDN AB4 1 DSI_CSI_RDN 1 2 4 R1424 49.3V) C27 F26 AUDIO_CLK R37 1 2 0_0402_5% Option AUDIO_CLK_R (17) VDD_1V8_GEN +T30S_USB1 W3 W2 USB1_DN USB1_DP USB1_DN (21) USB1_DP (21) For CLIENT USB 1 T7 ACC1_DETECT 1 R1422 2 1K_0402_5% @ USB1_ID (21) +AVDD_1V8_USB_PLL_TEGRA DAP1_SCLK DAP1_FS DAP1_DOUT DAP1_DIN G29 D28 G26 G25 PD PD PD C28 C29 G27 F27 PD PD PD PD H27 A28 PU PU B28 J24 F29 F28 PU PU PU PD D29 G28 F25 E27 B27 D30 PU PU PU PU PD PD AUDIO_SEL (16) AUDIO_RST# (16) ES305_INT_R (16) 1 2 @ R399 0_0402_5% L4 4 SPDIF_IN SPDIF_OUT AUDIO_SCLK2 (16) AUDIO_FS2 (16) AUDIO_DOUT2 (16) AUDIO_DIN2 (16) (31.2G_FCBGA728 Q5 BSS138W-7-F_SOT323-3 CAM_I2C_SCL C35 2 2 VDDIO_CAM CAM_I2C_SCL CAM_I2C_SDA CAM_MCLK GPIO_PBB0 GPIO_PBB3 GPIO_PBB4 GPIO_PBB5 GPIO_PBB6 GPIO_PBB7 GPIO_PCC1 GPIO_PCC2 AG5 AH7 Z Z AD5 Z R72 AF6 AD6 AG7 AE5 AE6 AE7 AC6 AG6 Z Z Z Z Z Z 2M_CAM_RST# (20) 2M_CAM_PWDN (20) PU PU @ R16 100K_0402_5% DSI_D2AN DSI_D2AP 3 2 2M_CAM_RST# 2M_CAM_PWDN @ R25 R15 @ 100K_0402_5% @ 2 CAM_MCLK (20) 1 R27 @ 100K_0402_5% 100K_0402_5% 1 1 AA1 AB1 1 V10 Add +VDD_1V8_CAM_TEGRA +AVDD_1V2_DSI_CSI_TEGRA AB2 AB3 1 DSI_D1AN DSI_D1AP 2 0_0402_5% C372 T30L-P-A3-1.7U_0402_6. Compal Secret Data Security Classification 2 DSI_CSI_TEST_OUT T30L-P-A3-1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_10V7K 4.8/3.8 ~ 3. June 13. INC.3V6M CSI_D1BN CSI_D1BP 2M_CAM_CLK#_R (20) 2M_CAM_CLK_R (20) (1. 2012 E Sheet 6 of 35 Rev 1.1U_0402_10V7K VDD_1V8_GEN W5 AVDD_USB 4. INC.8/2.1U_0402_10V7K CSI_D2BN CSI_D2BP 1 4. need check connection USB1_VBUS (3.8V) 10mA U4 MPZ1005S300CT_2P 5 C29 DAP2_SCLK DAP2_FS DAP2_DOUT DAP2_DIN 1 1 2 FDG6331L_SC70-6 SB00000SM00 Q34 AVDD_USB_PLL 0. Inc.0 .2K_0402_1% +VDD_1V8_CAM_TEGRA CSI_CLKBN CSI_CLKBP CAM_I2C_SDA C186 39P 50V J NPO 0402 USB VBUS overvoltage protection AE2 AE3 1 CSI_D2AN CSI_D2AP 1 2 +VDD_1V8_CAM_TEGRA AD3 AD2 10P_0402_25V8K CSI_D1AN CSI_D1AP 1 1 1 CSI_CLKAN CSI_CLKAP 2 AVDD_DSI_CSI AC4 AD4 2 2 2 Y4 USB_REXT (1.9_0402_1% R45 49.

2G_FCBGA728 VDD_1V8_GEN 20mA 2 2 1 1 1 U1B L3 BT_PCM_IN (25) BT_PCM_OUT (25) BT_PCM_SYNC (25) BT_PCM_CLK (25) 0 Z 2 AVDD_OSC VDD_1V8_GEN 2 PD PD PD PD 1 1 AA29 W28 AA24 AA26 For BT 4.4) EN_CAM_2V8 (20) BOARD_ID_WP (4) +VDD_1V8_SYS_TEGRA WAKEUP_LED (27) 3 PCB_ID3 EN_CAM_1V8# (23) UART_SW (18) @ PAD T10 SHORT_DET (17) WF_WAKE# (25) @ PAD T14 1 @ 2 R405 0_0402_5% SD_DET# (21.7) PWR_I2C_SDA (16.33.4) G_ACC_INT (19) BT_IRQ# (25) T27 R29 T28 R23 T22 V24 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST# JTAG_RTCK M30 M29 NV_THERM_DN NV_THERM_DP @ PAD T4 @ PAD T5 @ PAD T6 @ PAD T7 @ PAD T8 @ PAD T9 N22 AC18 R28 TEST_MODE_EN T30L-P-A3-1.33.1V) AVDD_PLLM 1 C41 1 1 C40 54mA VDD_PMU_LDO7 2 1 3 4 1 2/22 OSC. INC. INC.4.05V) 2 W1 1 (1.29.17.3V6M UART3_TXD UART3_RXD UART3_RTS* UART3_CTS* 100K_0402_5% CORE_PWR_REQ CPU_PWR_REQ C42 UART2_TXD UART2_RXD UART2_RTS* UART2_CTS* 100K_0402_5% 2.4. A T26 M23 V27 M28 N24 N30 T24 T25 R27 M26 R25 M27 N23 V28 M25 V26 PMU_CLK_32K (31) CLK_32K_OUT (25) 100K_0402_5% Vcc 2 D+ D- 1 1 THERMD_F_N PWR_I2C_SCL PWR_I2C_SDA R60 U4 2 3 THERM_DN THERM_DP +VDD_1V8_SYS_TEGRA +3VS R58 THERMD_F_P ACES_87036-1001-CP @ +3VS_TH PU PU PU PU PU PU PU PU 2 1 1000P_0402_50V7K R61 C46 100_0402_1% 2 1 2 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG_RTCK 0 J30 N26 V25 R26 W26 R30 P27 N29 PAD T2 R62 NV_THERM_DP 2 1 2 3 4 5 6 7 8 9 10 GND GND R22 U27 SYS_CLK_REQ 0_0402_5% 4 1 0.33.31.7) 0.4) VOL_DOWN# (22.8/3.7) N28 2 SYS_RESET_N 12/22 BB R52 Z Z 1 U1S M24 N27 2 1 PWR_I2C_SCL PWR_I2C_SDA 1 0_0402_5% (1.7) BT_PD# (25) (1.31.8K_0402_5% R51 2 AA22 +VDD_1V8_BB_TEGRA VDDIO_BB 2 @ (1.31.3V) 1.2G_FCBGA728 (22) HOT_RST# C45 max current is 350uA VR1 =17mV NV_THERM_DN (16.17.1V) AVDD_PLLX +VDD_1V8_SYS_TEGRA AVDD_PLLU_D 2 (1. June 13. Inc.3V) VDDIO_SYS_1 VDDIO_SYS_2 SYS_CLK_REQ CLK_32K_IN CLK_32K_OUT Deep Sleep : ON 100K_0402_5% 1 R379 WF_RST# (25) BT_WAKEUP (25) EN_SENSOR_3V3_2 (23) R164 2 1100K_0402_5% RB751V-40_SOD323-2 2 1 D20 +VDD_1V8_BB_TEGRA 0_0402_5% 2 R65 1 2 @ 0_0402_5% JTAG_TRST#2 R1561 JTAG_TDI JTAG_TMS JTAG_TCK JTAG_RTCK JTAG_TDO T30L-P-A3-1.2G_FCBGA728 1 100K_0402_5% 4 AP_OVERHEAT# (31) TEMP_ALERT# (4) 5 NCT72CMNR2G_DFN8_3x3 Issued Date Compal Electronics.31.7P_0402_50V8J C37 1 2 0.7) PWR_I2C_SCL (16.17. Compal Secret Data Security Classification Thermal 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.1U_0402_10V6K Z BT_RST# (25) Z Z GPS_PWRON (24) Z GPS_RESET# (24) Z Z DEBUG_UART1_RX_R 1@ R149 2 Z BT_PD# 0_0402_5% 1100K_0402_5% R372 2 For GPS BT_UART_TXD (25) BT_UART_RXD (25) BT_UART_RTS# (25) BT_UART_CTS# (25) T30_XTAL_OUT 1 AA28 V30 AB30 AB27 AC25 W30 AA27 GEN1_I2C_SCL (19) GEN1_I2C_SDA (19) GPS_UART_TXD (24) GPS_UART_RXD (24) GPS_UART_RTS# (24) GPS_UART_CTS# (24) Y10 12MHZ_7PF_FL1200105 R50 2M_0402_5% 1 PU PU PU PU 2 2 2 2 2 AC27 W27 AB29 W29 Y27 W24 CLK3_OUT CLK3_REQ 2 PU PU PU PU 100K_0402_5% 2 DAP4_DIN DAP4_DOUT DAP4_FS DAP4_SCLK Z Z W25 AB28 AB26 AA25 C39 GPIO_PU0 GPIO_PU1 GPIO_PU2 GPIO_PU3 GPIO_PU4 GPIO_PU5 GPIO_PU6 AB25 V29 4.1U_0402_10V6K ULPI_CLK ULPI_DIR ULPI_NXT ULPI_STP R3 PU V1 PU N1 PU T3 PU P4 PU T4 PU T1 PU T2 PU C44 C43 0.8V) AVDD_OSC XTAL_IN Deep Sleep : OFF XTAL_OUT T30 T30_XTAL_IN T29 T30_XTAL_OUT H12 PLL_S_PLL_LF +AVDD_1V1_PLL_TEGRA H13 CLK_12M_ES305 (16) 2 J12 J13 AA8 AD7 (1.1V) AVDD_PLLU_D2 AVDD_PLLE 2 R53 VDD_1V8_GEN 20mA M2 M4 Z N2 Z N4 Z AUDIO_UART4_TX (16) AUDIO_UART4_RX (16) EN_VDD_GPS (24) EN_SENSOR_1V8# (23) +VDD_1V8_BB_TEGRA 1 2 K29 K30 CORE_PWR_REQ CPU_PWR_REQ (1.1U_0402_10V6K AA30 1 PMU_OSC32KOUT (31) 10K_0402_5% 20mA VDD_1V8_GEN R47 2. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.17. 2012 E Sheet 7 of 35 Rev 1.2K_0402_1% 0.33.1U_0402_10V6K GEN1_I2C_SCL GEN1_I2C_SDA 4. PLL & SYS MPZ1005S300CT_2P T30L-P-A3-1.1V) (1.4.768KHZ_12.29.8/3.2K_0402_1% Open Drain 14/22 UART 1 100K_0402_5% R46 U1R 2 R75 32.29.1V) AVDD_PLLA_P_C NC (1.4. INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.1U_0402_10V6K 2 ULPI_DATA0 ULPI_DATA1 ULPI_DATA2 ULPI_DATA3 ULPI_DATA4 ULPI_DATA5 ULPI_DATA6 ULPI_DATA7 PWR_I2C_SCL (16.7) PWR_I2C_SDA VDD_1V8_PMU_VRTC 8 7 OWR JTAG_TDI R155 1 HDMI_CEC JTAG_TMS R159 1 TEST_MODE_EN JTAG_RTCK R160 1 JTAG_TCK 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 1 100K_0402_5% R161 2 JTAG_TRST# R162 2 THERM# ALERT#/ THERM2# SCLK SDATA GND 1 100K_0402_5% 4 6 PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD @ SC_LOCK# (22) VOL_UP# (22.29.7P_0402_50V8J C36 1 2 T30_XTAL_IN @ R49 R1572 2 (1.5P_1TJF125DP1A000D 1 1 +VDD_1V8_UART_TEGRA 1 (31) PMU_OSC32KIN 1 1 Y1 R56 B C D Title T30L-UART/OSC/PLL Size C Date: Document Number V0JET(A210)-LA8981P Wednesday.9_0402_1% R59 100_0402_1% 1 2 ONKEY_R# For JTAG R57 1 +3VS JDBUG1 1 2 3 4 5 6 7 8 9 10 11 12 1 Z R163 +VDD_1V8_SYS_TEGRA CORE_PWR_REQ (31.6) CPU_PWR_REQ (31) T23 @ @ R1560 100K_0402_5% PMU_INT# (31) N25 R24 10K_0402_5% KB_ROW00 KB_ROW01 KB_ROW02 KB_ROW03 KB_ROW04 KB_ROW05 KB_ROW06 KB_ROW07 KB_ROW08 KB_ROW09 KB_ROW10 KB_ROW11 KB_ROW12 KB_ROW13 KB_ROW14 KB_ROW15 ONKEY_R# (22) 1 R1 Z ON_KEY# R2 Z KB_COL00 KB_COL01 KB_COL02 KB_COL03 KB_COL04 KB_COL05 KB_COL06 KB_COL07 M22 A210@ R195 2 1 R77 100K_0402_5% 2 N3 PD M3 PD R4 PD R6 PD 3 GPIO_PV0 GPIO_PV1 PWR_INT_N +VDD_1V8_SYS_TEGRA WAKE_UP_ACIN (27) PMU_RESET_OUT_1V8# (31) 10K_0402_5% DAP3_DIN DAP3_DOUT DAP3_FS DAP3_SCLK DEBUG_UART1_TX (18) DEBUG_UART1_RX (18.0 .7U_0402_6.1U_0402_10V6K 2 49.1U_0402_10V6K C38 0.8K_0402_5% 1.A B C D E +VDD_1V8_SYS_TEGRA BT_RST# +VDD_1V8_SENSOR For PMU RTC CLOCK GPS_RESET# 1 2 AVDD_OSC10mA F30 1 2 DEBUG_UART1_RX (18.8/3.3V) VDDIO_UART R48 0.

INC.3V6M C25641 2 4.3V(max) (1. Compal Secret Data Security Classification F G Title T30L-Core Power Size Document Number Custom Date: Rev 1.1U_0402_10V6K 5 VDD_RTC_0001 VDD_RTC_0002 0.7U_0402_6.7U_0402_6.1U_0402_10V6K 2 A2 A29 AC11 AC14 AC17 AC2 AC20 AC23 AC26 AC29 AC5 AC8 AF11 AF14 AF17 AF2 AF20 AF23 AF26 AF29 AF5 AF8 AJ1 AJ11 AJ14 AJ17 AJ2 AJ20 AJ23 AJ26 AJ29 AJ30 AJ5 AJ8 AK2 AK29 B1 B11 B14 B17 B2 B20 B23 B26 B29 B30 B5 B8 E11 E14 E17 E2 E20 E23 E26 E29 E5 E8 H11 H14 H17 H2 H20 H23 H26 H29 H5 H8 L2 L23 L26 L29 L5 L8 M12 M14 M16 M18 N13 N15 N17 N19 P12 P18 P2 P23 P26 P29 P5 P8 R13 R15 R16 R19 T12 T15 T16 T18 U13 U19 U2 U23 U26 U29 U5 U8 V12 V14 V16 V18 W12 W13 W15 W17 W19 Y2 Y23 Y26 Y29 Y5 Y8 1 1 5 T30L-P-A3-1.3V6M 4.3V) 0.2375V(max) (0.2V) 0.7U_0402_6.3V6M C25631 0.3V6M 2 4.7U_0402_6. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. limint by H=0.3V6M 2 C2589 2 2 2 2 2 2 2 2 2 1U_0402_10V6K C2587 2 1U_0402_10V6K C2586 2 1 1U_0402_10V6K C2585 2 1 1U_0402_10V6K C2584 2 1 1U_0402_10V6K C2655 2 1 4.2V (1.5mm VDD_1V0_GEN VDD_1V0_CPU_TEGRA J1 2 @ 1 1 C2599 1 1 C2598 C2567 1 C2568 1 C2569 1 C2570 1 C2571 C2572 1 C2573 1 C2574 1 C2575 1 C2576 1 C2577 1 C2578 1 C2579 1 C2580 2 2 2 2 2 2 1U_0402_10V6K 2 1U_0402_10V6K 2 1U_0402_10V6K 2 1U_0402_10V6K 2 1U_0402_10V6K 2 VDD_1V0_CPU_TEGRA 1 1U_0402_10V6K 2 1 1U_0402_10V6K 2 2 JUMP_43X118 1U_0402_10V6K 2 4.1U_0402_10V6K 2 For placement question.7U_0402_6.7U_0402_6.7U_0402_6. pair ( Z = 90 ohm ) VDD_CORE_SENSE (33) GND_CORE_SENSE (33) +VDD_3V3_FUSE_TEGRA AA4 VPP_KFUSE R1395 10K_0402_5% C2600 1 2 VPP_KFUSE R1396 1K_0402_5% 2 1 VPP_FUSE (3.0 V0JET(A210)-LA8981P Wednesday.3V6M 2 4.1U_0402_10V6K For placement question.9 ~ 1.3V6M 2 4.0 ~ 1.3V6M C25831 4.2G_FCBGA728 Issued Date 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.7U_0402_6.3V6M 2 4.0V) VDD_CPU_01 VDD_CPU_02 VDD_CPU_03 VDD_CPU_04 VDD_CPU_05 VDD_CPU_06 VDD_CPU_07 VDD_CPU_08 VDD_CPU_09 VDD_CPU_10 VDD_CPU_11 VDD_CPU_12 VDD_CPU_13 VDD_CPU_14 VDD_CPU_15 VDD_CPU_16 VDD_CPU_17 VDD_CPU_18 VDD_CPU_19 VDD_CPU_20 VDD_CPU_21 VDD_CPU_22 1 1 C2562 0.1U_0402_10V6K VDD_CORE_01 VDD_CORE_02 VDD_CORE_03 VDD_CORE_04 VDD_CORE_05 VDD_CORE_06 VDD_CORE_07 VDD_CORE_08 VDD_CORE_09 VDD_CORE_10 VDD_CORE_11 VDD_CORE_12 VDD_CORE_13 VDD_CORE_14 VDD_CORE_15 VDD_CORE_16 VDD_CORE_17 VDD_CORE_18 VDD_CORE_19 VDD_CORE_20 VDD_CORE_21 VDD_CORE_22 VDD_CORE_23 VDD_CORE_24 VDD_CORE_25 VDD_CORE_26 VDD_CORE_27 VDD_CORE_28 VDD_1V2_SOC R1392 3A@ 1.A B C D E F G H T30 Core Power U1A VDD_1V2_RTC_TEGRA 1/22 CORE POWER V22 V23 VDD_PMU_LDO4 0.3V6M 2 4. pair ( Z = 90 ohm ) 90DIFF_NETCLASS1 VDD_CPU_SENSE (33) GND_CPU_SENSE (33) 90DIFF_NETCLASS1 4 Layout route as Diff. A B C D E Compal Electronics. INC.1U_0402_10V6K 3 @ PAD T22 @ PAD T23 VDD_CPU_SENSE GND_CPU_SENSE AB12 VDD_CPU_SENSE_PAIR AB15 VDD_CPU_SENSE_PAIR Layout route as Diff. 2012 Sheet H 8 of 35 .7U_0402_6.5mm VDD_1V2_CORE_TEGRA M13 M15 M17 M19 N12 N14 N16 N18 N7 P13 P19 R12 R18 R7 R8 R9 T13 T19 T8 T9 U18 V13 V15 V17 V19 W14 W16 W18 2 VDD_1V2_CORE_TEGRA 1 0_0805_5% 1 C2590 1 C2591 1 C2592 1 C2593 1 C2594 1 C2595 1 C2596 1 C2597 C2588 4.7U_0402_6.7U_0402_6.3V6M 2 1 1U_0402_10V6K C2656 2 1 1U_0402_10V6K 1 1U_0402_10V6K 1 4.3V6M C25661 2 4. Inc.1U_0402_10V6K H10 J10 J8 K8 K9 M7 M8 M9 N8 N9 P14 P15 P16 P17 R14 R17 T14 T17 U14 U15 U16 U17 2 10A@ 1. INC.3V6M C25651 2 4.3V6M 4.3V) 40mA@ 3.1U_0402_10V6K 4 20mA@ 1.7U_0402_6.0 ~ 1.3V AB8 2 (3.7U_0402_6.1U_0402_10V6K 3 GND_001 GND_002 GND_003 GND_004 GND_005 GND_006 GND_007 GND_008 GND_009 GND_010 GND_011 GND_012 GND_013 GND_014 GND_015 GND_016 GND_017 GND_018 GND_019 GND_020 GND_021 GND_022 GND_023 GND_024 GND_025 GND_026 GND_027 GND_028 GND_029 GND_030 GND_031 GND_032 GND_033 GND_034 GND_035 GND_036 GND_037 GND_038 GND_039 GND_040 GND_041 GND_042 GND_043 GND_044 GND_045 GND_046 GND_047 GND_048 GND_049 GND_050 GND_051 GND_052 GND_053 GND_054 GND_055 GND_056 GND_057 GND_058 GND_059 GND_060 GND_061 GND_062 GND_063 GND_064 GND_065 GND_066 GND_067 GND_068 GND_069 GND_070 GND_071 GND_072 GND_073 GND_074 GND_075 GND_076 GND_077 GND_078 GND_079 GND_080 GND_081 GND_082 GND_083 GND_084 GND_085 GND_086 GND_087 GND_088 GND_089 GND_090 GND_091 GND_092 GND_093 GND_094 GND_095 GND_096 GND_097 GND_098 GND_099 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.7U_0402_6. June 13.2V) 0.3V6M C25821 4.7U_0402_6. limint by H=0.3V6M C25811 0. pair ( Z = 90 ohm ) VVDD_CPU_SENSE VGND_CORE_SENSE AB16 VVDD_CPU_SENSE VVDD_CPU_SENSE_PAIR 90DIFF_NETCLASS1 AA23 VGND_CORE_SENSE VVDD_CPU_SENSE_PAIR 90DIFF_NETCLASS1 @ PAD T24 @ PAD T25 @ PAD T26 @ PAD T27 VDD_CORE_SENSE GND_CORE_SENSE W23 VDD_CORE_SENSE W22 GND_CORE_SENSE Layout route as Diff. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.7U_0402_6.

2G_FCBGA728 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 C PEX_L4_RXN PEX_L4_RXP (1.3V) AB21 D AF19 AG19 PEX_L2_RXN PEX_L2_RXP VDDIO_VI VI_MCLK VI_PCLK AJ18 AH18 AE26 PD/H AF25 PD/H AD27 AG30 PD/H PD/H AF27 AD30 AH29 AG28 AE27 AE25 AG29 AD29 AE29 AD28 AE30 AE28 PD/H PD/H PD/H PD/H/W PD/H PD/H PD/H PD/H PD/H PD/H PD/H PD/H T30 SPARE Pins U1V 22/22 NC VI_HSYNC VI_VSYNC AK19 AK18 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43 HVDD_PEX PEX_L3_TXN PEX_L3_TXP PEX_L3_RXN PEX_L3_RXP VI_D00 VI_D01 VI_D02 VI_D03 VI_D04 VI_D05 VI_D06 VI_D07 VI_D08 VI_D09 VI_D10 VI_D11 AK24 AK25 AJ21 AH21 AB10 AB5 AC19 AC9 C25 E13 H25 (1.05V) AD22 VDD_PEXA PEX_L1_RXN PEX_L1_RXP AK22 AK21 19/22 VI (1. June 13.05V) HVDD_SATA (3.3V) AVDD_SATA_PLL SATA_L0_TXN SATA_L0_TXP (1.05V 10mA@ 3.2G_FCBGA728 AC21 AE22 AG25 AF22 AJ28 AH28 A AG20 T30L-P-A3-1.05V) AE23 PEX_L5_TXN PEX_L5_TXP AJ24 AH24 AJ25 AH25 VDD_PEXB PEX_L5_RXN PEX_L5_RXP AG22 AG23 T30 SATA Interface (1.05V) SATA_L0_RXN SATA_L0_RXP SATA_TESTCLKN SATA_TESTCLKP VDDIO_PEX_CTL PEX_L0_CLKREQ* PEX_L0_PRSNT* PEX_L0_RST* PEX_L1_CLKREQ* PEX_L1_PRSNT* PEX_L1_RST* PEX_L2_CLKREQ* PEX_L2_PRSNT* PEX_L2_RST* PEX_WAKE* PEX_TESTCLKN PEX_TESTCLKP A PEX_TERMP AD16 AE16 AE19 AD19 AJ22 AH22 (3.05V) VDD_SATA (1.0 V0JET(A210)-LA8981P Wednesday. 2012 1 Sheet 9 of 35 .2G_FCBGA728 21/22 NC AVDD_SATA SATA_TERMP AG24 AD25 AG26 AD26 AD24 AG27 AE21 AD21 AD18 T30L-P-A3-1.2G_FCBGA728 Title T30L-PEX/SATA/VI Size C Date: 5 4 3 2 Document Number Rev 1.8V) AH30 PEX_L2_TXN PEX_L2_TXP (3.3V) AF24 B T30L-P-A3-1.05V) AE24 AVDD_PEX_PLL PEX_CLK1N PEX_CLK1P AK28 AK27 AB11 AB14 AB17 AB20 AB22 AB9 AE11 AE14 AE17 AE20 F11 F14 F17 F20 J11 J14 J17 J20 J22 J9 L22 L25 L6 L9 P22 P25 P6 P9 U22 U25 U6 U9 Y22 Y25 Y6 Y9 C U1U B PEX_CLK2N PEX_CLK2P PEX_CLK3N PEX_CLK3P AB24 AB23 75mA@ 1.05V) AC22 AVDD_PEXB PEX_L4_TXN PEX_L4_TXP AG21 AF21 T30L-P-A3-1.5 4 3 2 1 T30 PEX Interface U1T 20/22 PEX T30 VI Interface (1.05V PEX_REFCLKN PEX_REFCLKP AC15 VDD_SATA AF15 HVDD_SATA AC16 AVDD_SATA_PLL AG17 AVDD_SATA (1.3V AH27 AJ27 120mA@ 1.2 / 1.05V 18mA@ 1.05V) AB18 AB19 AVDD_PEXA_1 AVDD_PEXA_2 PEX_L0_TXN PEX_L0_TXP PEX_L0_RXN PEX_L0_RXP AG18 AF18 POR State/ After Wake State/ Wake-Up Events PU: Pull Up PD: Pull Down Z: High Impendance R: Reset H: Hold W: Wake-Up Event AJ19 AH19 D PEX_L1_TXN PEX_L1_TXP U1F (1.

June 13. 2012 1 Sheet 10 of 35 .5 4 3 2 1 D D C C B B A A Title <Title> Size C Date: 5 4 3 2 Document Number V0JET(A210)-LA8981P Rev 1.0 Wednesday.

7U_0402_6.1U_0402_10V6K (12.1U_0402_10V6K RESET* 1 C2604 A3 A10 D8 G3 G9 K2 K10 M2 M10 0.1U_0402_10V6K C2617 2 VDDQ[0] VDDQ[1] VDDQ[2] VDDQ[3] 0. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.0] 0. DDR3_part1 Document Number A B C D E Rev 1.A B C D DDR3/DDR3L (page 1/2): 4pcs.1U_0402_10V6K (12.5) DDR_A15 M1_ZQ VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] 1 C2603 RAS* CAS* WE* CS* 0.5) DDR_CLKP (12.5) DDR_BA2 2 K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 VDD[0] VDD[1] VDD[2] VDD[3] VDD[4] VDD[5] VDD[6] VDD[7] VDD[8] 0.1U_0402_10V6K X76@ DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 4.5) DDR_ODT0 BA[0] BA[1] BA[2] 1 C2602 DDR_RAS# DDR_CAS# DDR_WE# DDR_CS0# 0. INC.7U_0402_6. INC.5) 4.5) DDR_CLKN A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10]/AP A[11] A[12]/BC* A[13] A[14] A3 A10 D8 G3 G9 K2 K10 M2 M10 0.5) (12.0] U150B DDR_DQ4 DDR_DQ7 DDR_DQ0 DDR_DQ5 DDR_DQ2 DDR_DQ3 DDR_DQ1 DDR_DQ6 (5) DDR_DM0 (5) DDR_DQS0P (5) DDR_DQS0N 4 B4 C8 C3 C9 E4 E9 D3 E8 A8 B8 C4 D4 X76@ U151B DQ[0] DQ[1] DQ[2] DQ[3] DQ[4] DQ[5] DQ[6] DQ[7] NF/TDQS* DM/TDQS DQS DQS* DDR_DQ23 DDR_DQ18 DDR_DQ17 DDR_DQ22 DDR_DQ20 DDR_DQ19 DDR_DQ16 DDR_DQ21 (5) DDR_DM2 (5) DDR_DQS2P (5) DDR_DQS2N H5TC4G83MFR-PBA_FBGA82 B4 C8 C3 C9 E4 E9 D3 E8 A8 B8 C4 D4 X76@ U150 X76-S@ K4B2G0846D-HYH9 U150 X76-H@ H5TC2G83CFR-H9A SA00005KI10 U151 X76-S@ K4B2G0846D-HYH9 U151 X76-H@H5TC2G83CFR-H9A SA00005KI10 X76-H@H5TC2G83CFR-H9A X76-S@ K4B2G0846D-HYH9 U153 5 U153 X76-H@H5TC2G83CFR-H9A X76-S@ K4B2G0846D-HYH9 X76-E@ EDJ2108EDBG-DJ-F X76-E@ EDJ2108EDBG-DJ-F SA000055E10 U159 SA000055910 SA00005KI10 X76-E@ EDJ2108EDBG-DJ-F SA000055E10 U160 SA000055910 SA00005KI10 HH5TC4G83MFR-PBA_FBGA82 SA000055E10 U155 SA000055910 U152 U152 U156 SA000055910 DQ[0] DQ[1] DQ[2] DQ[3] DQ[4] DQ[5] DQ[6] DQ[7] NF/TDQS* DM/TDQS DQS DQS* X76-E@ EDJ2108EDBG-DJ-F SA000055E10 Issued Date Compal Electronics.3V6M U150A NB DDR3 design 2 R1401 1K_0402_1% (12.5) DDR_CKE0 (12..5) DDR_RESET# VSSQ[0] VSSQ[1] VSSQ[2] VSSQ[3] VSSQ[4] 2 0.1U_0402_10V6K DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 U151A RAS* CAS* WE* CS* 0.1U_0402_10V6K N3 (12.1U_0402_10V6K DDR_A15 H9 A1 A11 N1 N11 A4 J8 NC_F2 NC_F10 NC_H2 NC_H10 2 VDD[0] VDD[1] VDD[2] VDD[3] VDD[4] VDD[5] VDD[6] VDD[7] VDD[8] 0.3V6M 4.5) DDR_BA1 (12.1U_0402_10V6K 1R1398 2 243_0402_1% CKE CK CK* 2 F4 G4 H4 H3 0.5) (12.1U_0402_10V6K G10 F8 G8 (12.5) (12.7U_0402_6.1U_0402_10V6K H5TC2G83BFR-PBA_FBGA82 3 DDR_A15 H9 A1 A11 N1 N11 A4 J8 A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10]/AP A[11] A[12]/BC* A[13] A[14] 1 VREFDQ VREFCA E2 J9 0..35V VDD_1V35_DDR3_MEM VDD_1V35_DDR3_MEM 1 C2605 2 VDD_1V35_DDR3_MEM 4. June 13.1U_0402_10V6K F4 G4 H4 H3 DDR_RAS# DDR_CAS# DDR_WE# DDR_CS0# DDR_A[14.5) DDR_DQ[31.5) DDR_BA0 (12. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.0 V0JET(A210)-LA8981P Date: Wednesday.7U_0402_6. INC.1U_0402_10V6K 1 0. 2012 F Sheet 11 of 35 G .5) (12.1U_0402_10V6K J3 K9 J4 (12. 2Gbx4 memory chips: RANK 0: LOW 16 BITS E F G Note: Layout use the 82 ball biggest packages and co-Layout 78 ball A210 use 78 ball H5TC2G83CFR-H9A 1 700mA@ 1. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.3V6M 2 0.1U_0402_10V6K G2 (12. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_10V6K F2 F10 H2 H10 VDDQ[0] VDDQ[1] VDDQ[2] VDDQ[3] 1 C2601 0.3V6M B10 C2 E3 E10 B3 B9 C10 D2 D10 1 C2611 2 1 1 C2612 2 C2613 2 K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 DDR_BA0 DDR_BA1 DDR_BA2 J3 K9 J4 F2 F10 H2 H10 N3 DDR_RESET# G2 DDR_ODT0 1 R1399 2 243_0402_1% ZQ NC_A1 NC_A11 NC_N1 NC_N11 NC_A4 NC_J8 G10 F8 G8 DDR_CKE0 DDR_CLKP DDR_CLKN A2 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10 ODT M4_ZQ VDD_0V675_DDR3_VREF BA[0] BA[1] BA[2] CKE CK CK* C2618 VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] NC_F2 NC_F10 NC_H2 NC_H10 RESET* 2 1 1 C2607 2 C2608 2 1 C2609 2 1 C2610 2 VDD_1V35_DDR3_MEM B10 C2 E3 E10 B3 B9 C10 D2 D10 1 C2614 2 1 1 C2615 2 C2616 2 A2 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10 ODT ZQ NC_A1 NC_A11 NC_N1 NC_N11 NC_A4 NC_J8 X76@ 1 VSSQ[0] VSSQ[1] VSSQ[2] VSSQ[3] VSSQ[4] 1 C2606 VDD_0V675_DDR3_VREF VREFDQ VREFCA E2 J9 H5TC4G83MFR-PBA _FBGA82 VDD_1V35_DDR3_MEM 2 1 C2619 2 1 C2620 2 1 2 R1400 1K_0402_1% VDD_0V675_DDR3_VREF 0. Inc.

0] (5) DDR_DM1 (5) DDR_DQS1P (5) DDR_DQS1N DDR_DQ29 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ24 DDR_DQ30 DDR_DQ31 U152B DDR_DQ11 DDR_DQ10 DDR_DQ12 DDR_DQ13 DDR_DQ9 DDR_DQ14 DDR_DQ8 DDR_DQ15 B4 C8 C3 C9 E4 E9 D3 E8 A8 B8 C4 D4 X76@ DQ[0] DQ[1] DQ[2] DQ[3] DQ[4] DQ[5] DQ[6] DQ[7] NF/TDQS* DM/TDQS DQS DQS* (5) DDR_DM3 (5) DDR_DQS3P (5) DDR_DQS3N B4 C8 C3 C9 E4 E9 D3 E8 A8 B8 C4 D4 X76@ DQ[0] DQ[1] DQ[2] DQ[3] DQ[4] DQ[5] DQ[6] DQ[7] NF/TDQS* DM/TDQS DQS DQS* H5TC4G83MFR-PBA_FBGA82 H5TC4G83MFR-PBA_FBGA82 4 5 Issued Date Compal Electronics.1U_0402_10V6K (11. Date: DDR3_part2 Document Number Rev 1.. 2Gbx4 memory chips: RANK 0: HIGH 16 BITS VDD_1V35_DDR3_MEM 1 VDD_1V35_DDR3_MEM C2632 2 C2633 2 G2 DDR_ODT0 1R1403 2 243_0402_1% M2_ZQ VDD_0V675_DDR3_VREF VREFDQ VREFCA DDR_A15 BA[0] BA[1] BA[2] CKE CK CK* RESET* 1 C2627 2 C2628 2 1 C2629 2 1 C2630 2 1 C2634 2 1 1 C2635 2 C2636 2 ODT ZQ NC_A1 NC_A11 NC_N1 NC_N11 NC_A4 NC_J8 X76@ 1 1 A2 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10 VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] NC_F2 NC_F10 NC_H2 NC_H10 2 VDD_0V675_DDR3_VREF E2 J9 VREFDQ VREFCA H5TC4G83MFR-PBA_FBGA82 C2638 2 1 C2639 2 0.5) DDR_BA1 (11.1U_0402_10V6K RESET* B3 B9 C10 D2 D10 1 C2631 F4 G4 H4 H3 0.1U_0402_10V6K J3 K9 J4 (11. June 13. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.5) DDR_CKE0 (11. Inc.5) DDR_ODT0 CKE CK CK* C2622 2 1 0.1U_0402_10V6K G2 (11.5) 1 C2640 2 3 U153B (11.7U_0402_6.3V6M U152A (11.7U_0402_6.1U_0402_10V6K 1R1402 2 243_0402_1% VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] C2623 2 1 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_10V6K X76@ N3 DDR_RESET# ODT ZQ NC_A1 NC_A11 NC_N1 NC_N11 NC_A4 NC_J8 G10 F8 G8 F2 F10 H2 H10 M3_ZQ H9 A1 A11 N1 N11 A4 DDR_A15 J8 J3 K9 J4 DDR_BA0 DDR_BA1 DDR_BA2 DDR_CKE0 DDR_CLKP DDR_CLKN A2 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10 A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10]/AP A[11] A[12]/BC* A[13] A[14] 4.1U_0402_10V6K C2637 2 H9 A1 A11 N1 N11 A4 J8 B3 B9 C10 D2 D10 VSSQ[0] VSSQ[1] VSSQ[2] VSSQ[3] VSSQ[4] 1 C2626 VDD_1V35_DDR3_MEM B10 C2 E3 E10 VDDQ[0] VDDQ[1] VDDQ[2] VDDQ[3] 0.0 V0JET(A210)-LA8981P Wednesday.5) DDR_BA0 (11.5) (11.5) DDR_A15 NC_F2 NC_F10 NC_H2 NC_H10 VDD_1V35_DDR3_MEM B10 C2 E3 E10 C2624 2 DDR_RAS# DDR_CAS# DDR_WE# DDR_CS0# 0.5) (11.3V6M 4.1U_0402_10V6K 1 0.3V6M 1 K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 A3 A10 D8 G3 G9 K2 K10 M2 M10 VDD[0] VDD[1] VDD[2] VDD[3] VDD[4] VDD[5] VDD[6] VDD[7] VDD[8] 0.0] 4.7U_0402_6.1U_0402_10V6K H5TC4G83MFR-PBA _FBGA82 E2 J9 0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.1U_0402_10V6K F2 F10 H2 H10 VDDQ[0] VDDQ[1] VDDQ[2] VDDQ[3] 1 C2621 0. 2012 Sheet 12 of 35 .5) (11.1U_0402_10V6K F4 G4 H4 H3 DDR_RAS# DDR_CAS# DDR_WE# DDR_CS0# DDR_A[14.. INC.1U_0402_10V6K 2 1 DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 C2625 2 RAS* CAS* WE* CS* 0. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.3V6M 4.1U_0402_10V6K DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 U153A RAS* CAS* WE* CS* 0.5) DDR_CLKN A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10]/AP A[11] A[12]/BC* A[13] A[14] A3 A10 D8 G3 G9 K2 K10 M2 M10 0.7U_0402_6.5) DDR_DQ[31.5) DDR_CLKP (11. INC.DDR3/DDR3L(page 2/2): 4pcs.1U_0402_10V6K (11.1U_0402_10V6K N3 VSSQ[0] VSSQ[1] VSSQ[2] VSSQ[3] VSSQ[4] 2 1 0.5) DDR_RESET# BA[0] BA[1] BA[2] 1 0.5) DDR_BA2 2 K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 VDD[0] VDD[1] VDD[2] VDD[3] VDD[4] VDD[5] VDD[6] VDD[7] VDD[8] 0.5) (11. INC.1U_0402_10V6K G10 F8 G8 (11.

AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. INC. June 13. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. 5 4 3 2 Title EC(Reserved) Size C Date: Document Number V0JET(A210)-LA8981P Wednesday. INC. INC. Inc.0 . 2012 1 Sheet 13 of 35 Rev 1.5 4 3 2 1 D D C C B B A A Issued Date Compal Electronics. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.

June 13. INC.1U_0402_10V6K 1 1 C118 10U_0402_6.5 4 3 2 +VDD_2V85_EMMC 1 +3VS K6 W4 Y4 AA3 AA5 1 2 1 2 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_10V6K VCCQ VCCQ VCCQ VCCQ VCCQ M6 N5 T10 U9 2 1 @ C150 4.1U_0402_10V6K R104 R105 R106 R107 R108 R109 R110 R111 1 1 1 1 1 1 1 1 2 0_0402_5% 2 C122 12P_0402_50V4Z 2 2 2 2 2 2 2 2 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% EMMC_CLK (4) 1 R103 1 EMMC_DA0 EMMC_DA1 EMMC_DA2 EMMC_DA3 EMMC_DA4 EMMC_DA5 EMMC_DA6 EMMC_DA7 (4) (4) (4) (4) (4) (4) (4) (4) R114 EMMC_CMD_R MMC_RST# 2 C MMC_RST# R112 1 2 0_0402_5% EMMC_RST# (4) U13 SS8GB@ KLM8G2FE3B-B001 SA00005KM10 U13 SD8GB@ SDIN5D1-8G-L SA00005MV10 U13 SS16GB@ KLMAG2GE4A-A001 SA00005KG10 U13 B SD16GB@ SDIN5C1-16G-L SA00004XA30 1 2 3 4 5 6 7 8 9 10 11 12 SDIN5F1-64G_TFBGA169 A Issued Date Compal Electronics.3V6M 1 2 C120 0. 5 0_0402_5% 2 4 EN VSS VSS VSS VSS U8 R10 P5 M7 VSSQ VSSQ VSSQ VSSQ VSSQ NC NC NC NC NC NC NC NC NC NC NC NC AA6 AA4 Y5 Y2 K4 2 2 W6 1 R102 1 EMMC_CMD_R 2 W5 close U13 @ 1 (5) EN_3V3_EMMC (4) EN_3V3_EMMC1 R113 CLK A 2 0_0402_5% R440 1 R437 2 1 5 +VDDIO_1V8_EMMC CMD NC NC NC NC NC NC NC NC NC NC NC NC 1 VIN C121 0.7K_0402_5% B VCC VCC VCC VCC U13 C 1 2.3VM A4 A6 A9 A11 B2 B13 D1 D14 H1 H2 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J7 J8 J9 J10 J11 J12 J13 J14 K1 K3 K5 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L12 L13 L14 M1 M2 M3 M5 M8 M9 M10 M12 M13 M14 N1 N2 N3 N10 N12 N13 N14 P1 P2 P3 P10 P12 P13 P14 R1 R2 R3 R5 R12 R13 R14 T1 T2 T3 T5 T12 T13 T14 2 200mA @ C148 2 33mA C119 D R422 1 @ 0_0402_5% 2 R101 1 0_0402_5% +3VS 22U_0603_6.3V6M +VDDIO_1V8_EMMC +VDD_2V85_EMMC +VDD_2V85_EMMC U51 +VDDIO_1V8_EMMC VDD_1V8_GEN 4 3 2 Title eMMC Size C Date: Document Number V0JET(A210)-LA8981P Wednesday. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.2U_0402_6.7K_0402_5% 13 14 15 16 17 18 19 20 21 22 23 24 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 1 C149 4. INC. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. 2012 1 Sheet 14 of 35 Rev 1. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.2U_0402_6.0 .3V6M 2 10U_0402_6. INC.3V6M 2 DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 VDDi NC NC NC RSTN NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 3 VOUT GND NC 2 R439 G9001-300TO1U TSOT-23 5P LDO 0_0402_5% @ EMMC_CLK_R 2 33_0402_5% 1 C365 1U_0402_10V4Z D SA00005II00 EMMC_CMD (4) 1 H3 H4 H5 J2 J3 J4 J5 J6 EMMC_DAT0_R EMMC_DAT1_R EMMC_DAT2_R EMMC_DAT3_R EMMC_DAT4_R EMMC_DAT5_R EMMC_DAT6_R EMMC_DAT7_R K2 C123 1 U1 U2 U3 U5 U6 U7 U10 U12 U13 U14 V1 V2 V3 V12 V13 V14 W1 W2 W3 W7 W8 W9 W10 W11 W12 W13 W14 Y1 Y3 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 AA1 AA2 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AE1 AE14 AG2 AG13 AH4 AH6 AH9 AH11 0.3V6M 2 1 10U_0402_6. Inc.1U_0402_10V6K 2 C117 C385 2.

4) GEN2_I2C_SCL (15.7U_0603_6.4) GEN2_I2C_SCL (15.7U_0603_6. INC.3V6K 1 1 2 R1293 100K_0402_5% 3 +3VS (4) EN_VDDLCD_T30S GND IN IN EN# 280mA FBMA-L11-201209-221LMA30T_0805 1 2 L6 +LCDVDD_L U97 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A 2 R1389 2 R1390 (15.1U_0402_10V7K D EN_VDDLCD_T30S 2 G OUT OUT OUT OC# 4.1U_0402_25V4Z 4 3 5 C C for EMI Close JLVDS3 JLVDS3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 +LEDVDD 1 R1332 2 0_0402_5% LVDS_A0 LVDS_A00 2 (4) IMG_EN 1 R1027 4.7K_0402_5% R218 +3VS Close to U10 37 38 5 13 21 53 29 33 35 36 43 49 1 0_0603_5% 1 R1375 2 100P_0402_50V8J 27 28 Y3P Y3M LVDS_A1 LVDS_A1# 2 1 LCD_HSYNC LCD_VSYNC Y2P Y2M D15 D18 D19 D20 D21 D22 D16 D17 45 46 2 R138 0_0402_5%1 0_0402_5% C2657 C474 1 1 3 15 19 20 22 23 24 16 18 Y1P Y1M C191 1 +VDD_BIO LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 D7 D8 D9 D12 D13 D14 D10 D11 +LEDVDD FDC604P_NL_SSOT6 Q56 6 4 5 2 1 B+ 10U_0805_25V6K LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 4 6 7 11 12 14 8 10 LVDS_A0 LVDS_A0# +LEDVDD +LCDVDD +VDD_LVDS 47 48 2 @ R140 0_0402_5%1 G (4) (4) (4) (4) (4) (4) 1. INC.1U_0402_10V7K JP58 C1501 2 1 (4) TS_INT# 1 2 3 4 5 6 7 8 TS_I2C_SCL TS_I2C_SDA 33_0402_5% 2 R1388 (4) TS_RST# 1 R1339 2 0_0402_5% LVDS_ACLK# 1 0_0402_5% C1474 1U_0402_10V4Z 2 WCM-2012HS-900T_0805 4 B 1 0_0402_5% 2 @ R1029 +5VS 1 R1337 2 0_0402_5% AP_SMB_SDA 2 R1030 +3VS 3 LVDS_A2# LCD 31 32 33 34 35 36 Focaltech Request 2 WCM-2012HS-900T_0805 4 GND1 GND2 GND3 GND4 GND5 GND6 SP010011S00 STARC_107K30-000001-G2 LVDS_ACLK0# (4) TS_PWR_EN @ 1 2 R1031 33_0402_5% 2 9 10 @ R1308 100K_0402_5% 1 2 3 4 5 6 7 8 GND GND ACES_50208-00801-003 1 1 @ C1502 22P_0402_50V8J 2 1 20_0402_5% LVDS_A00# 1 R1334 2 0_0402_5% LVDS_A1 EDID 3 2 2 1 C1220 4 3 L87 1 R1333 2 0_0402_5% 1 2 1 C2660 1 39P 50V J NPO 0402 2 1 @ LVDS_A0# C2654 C1211 APL3510DXI-TRG MSOP 8P Q50 BSS138W-7-F_SOT323-3~D 0.3 for EMI (4) LCD_HSYNC (4) LCD_VSYNC (4) LVDS_SHTDN# (4) LCD_DE LVDS_SHTDN# LCD_DE 32 30 25 31 17 LCD_PCLK (4) LCD_PCLK 1 2 CLKOUTP CLKOUTM GND GND GND GND GND PLLGND PLLGND LVDSGND LVDSGND LVDSGND D24 D25 SHTDN# D26 D23 CLKIN CLKSEL 41 42 LVDS_A2 LVDS_A2# 39 40 1 3 2 1 2 LEDVDD_GATE R825 120K_0402_5% S D S EN_VDDLCD_T30S 2 G 1 @ 1 C2651 2 2 1 2 2 BSS138W-7-F_SOT323-3~D Q55 2 G C2650 C605 0.1U_0402_10V7K S 4 +LCDVDD 1 R1410 100K_0402_5% 8 7 6 5 0. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.01U_0402_25V7 LVDS Bridge 2 0_0402_5% 1 2 C190 2 R1418 C2659 330P_0402_50V7K Close to U10 0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. INC.1U_0402_25V6 C2652 1 C2653 2 D for EMI Q57 BSS138W-7-F_SOT323-3~D LVDS_ACLK LVDS_ACLK# LVDS_SHTDN# R1409 10K_0402_5% LVDS_A00 C101 1 2 12P_0402_50V4Z LVDS_A00# C102 1 2 12P_0402_50V4Z LVDS_A01 C103 1 2 12P_0402_50V4Z LVDS_A01# C104 1 2 12P_0402_50V4Z LVDS_A02 C105 1 2 12P_0402_50V4Z LVDS_A02# C106 1 2 12P_0402_50V4Z LVDS_ACLK0 C107 1 2 12P_0402_50V4Z LVDS_ACLK0# C108 1 2 12P_0402_50V4Z R99 100K_0402_5% 1 : Rising edge 0 : Falling edge 2 SN75LVDS83DGGRG4_TSSOP56 2 1 R519 100K_0402_5% 1 2 D 1 2 4.8V level LCD_D06 LCD_D07 LCD_D08 LCD_D09 LCD_D10 LCD_D11 +VDD_BIO S LCD_D06 LCD_D07 LCD_D08 LCD_D09 LCD_D10 LCD_D11 Y0P Y0M 1 9 26 44 34 @ R139 0_0402_5%1 1 B+ to +LEDVDD Transfer D (4) (4) (4) (4) (4) (4) Vcc Vcc Vcc LVDSVcc PLLVcc VDD_1V8_GEN 1U_0402_10V4Z 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 233P 50V J NPO 0201 D0 D1 D2 D3 D4 D6 D27 D5 2 4. 2012 1 Sheet 15 of 35 Rev 1. 5 4 3 2 Title LCD PANEL Size C Date: Document Number V0JET(A210)-LA8981P Wednesday. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.4) GEN2_I2C_SDA 1 0_0402_5% 1 0_0402_5% AP_SMB_SCL For LVDS_A02# LVDS_ACLK 1 R1338 2 0_0402_5% LVDS_ACLK0 1 1 2 4 L90 3 Atmel Request @ 2 22P_0402_50V8J 1@ 3 +TS_LDO 1 1 C1475 2 0.3V6K @ C1433 1 @ C1434 1 @ C1435 1 @ C1436 1 @ C1437 1 @ C1438 1 @ C1439 1 @ C1440 1 @ C1441 1 @ C1442 1 @ C1443 1 @ C1444 1 @ C1445 1 @ C1446 1 @ C1447 1 @ C1448 1 @ C1449 1 @ C1450 1 @ C1451 1 @ C1452 1 @ C1453 1 51 52 54 55 56 3 50 2 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 1 2 0. Inc. June 13.0 . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.4) GEN2_I2C_SDA 1 TS_I2C_SCL 0_0402_5% 1 TS_I2C_SDA 0_0402_5% For A TP Issued Date Compal Electronics.01U_0402_25V7 U10 0.7K_0402_5% LCD POWER CIRCUIT 1 1 2 +LCDVDD 2 +3VS WCM-2012HS-900T_0805 2 2 LVDS_A01 2 (4) LCD_PWM_OUT 1 R1026 0_0402_5% 1 2 1 1 2 4 L88 3 2 @ C1232 39P 50V J NPO 0402 WCM-2012HS-900T_0805 4 @ R1344 1 AP_SMB_SCL AP_SMB_SDA (4) DISPOFF# 2 R1025 100K_0402_5% DISPOFF# LVDS_ACLK0 LVDS_ACLK0# LVDS_A02 LVDS_A02# R1417 100K_0402_5% 1 3 LVDS_A01 LVDS_A01# B LVDS_A1# 1 R1335 2 0_0402_5% LVDS_A01# LVDS_A2 1 R1336 2 0_0402_5% LVDS_A02 1 2 4 L89 3 LVDS_A00 LVDS_A00# @ 2 R1425 2 R1426 (15.01U_0402_25V7 D LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_D06 LCD_D07 LCD_D08 LCD_D09 LCD_D10 LCD_D11 LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 LCD_HSYNC LCD_VSYNC LCD_DE (4) (4) (4) (4) (4) (4) 1 0.

Audio Block Diagram Issued Date Compal Electronics. INC.7) PWR_I2C_SCL ADC VDD_P_305 A6 R186 1 2 0_0402_5% ES305_CLK_IN A4 R172 1 2 0_0402_5% UART_SIN A3 R175 1 2 0_0402_5% UART_SOUT B4 R176 1 2 0_0402_5% ES305_INT B3 R226 1 2 0_0402_5% ES305_I2C_SDA B5 R246 1 2 0_0402_5% ES305_I2C_SCL C5 R179 1 2 0_0402_5% AUDIO_RST#_R D5 R185 1 (7) CLK_12M_ES305 SW C_DO (6) AUDIO_RST# @ T30S AUDIO_FS2 A_CLK C_FS A_FS ES305 B_DO A AUDIO_SCLK2_VOICE AUDIO_FS2_VOICE D_DI B_CLK D_CLK B_FS D_FS CLK VDD_DAL PORTA_DO VDD_DPD PORTA_CLK VDD_P PORTA_FS CLK_IN PORTB_DI 12M ~ 16M UART_SIN PORTB_DO UART_SOUT PORTB_CLK GPIO_A PORTB_FS A5 E5 E6 F6 UART_SOUT WM8903 A2 CODEC_OUT (17) B2 CODEC_IN (17) A1 AUDIO_SCLK2_VOICE B1 AUDIO_FS2_VOICE F3 AUDIO_DOUT2_R ES305_INT F4 R173 2 1 100K_0402_5% E4 AUDIO_SCLK2 E3 AUDIO_FS2 F2 AUDIO_DOUT2_R E2 AUDIO_DIN2_R E1 AUDIO_SCLK2 F1 AUDIO_FS2 B I2C_DATA I2C_CLK RESET_ PORTC_DI PORTC_DO low active TEST PORTC_CLK PORTC_FS For 24M or 26M R180 @ 10K_0402_5% GND_P PORTD_DI GND PORTD_DO GND PORTD_CLK GND PORTD_FS D1 C1 C2 D2 R181 100K_0402_5% ES305_BGA32 10/11 Change P/N from SA00004Y400 to SA00004Y410 R205 470K_0402_5% A Support for input clock frequencies of 24 MHz and 26 MHz requires a 10kΩ pull-up resistor on the UART_SOUT pin.31. 2 0_0402_5% F5 DAP2_DOUT C AUDIO_FS2 (6) SJ000004400 B6 AUDIO_DIN2 (6) AUDIO_SCLK2 (6) CPU.0 . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.1U_0402_10V6K R167 @ 10K_0402_5% 1 (6) AUDIO_SEL 1U_0402_10V4Z 2 IN C199 0. portC and U24 DAP2_DIN AUDIO_DIN2 AUDIO_SCLK2_VOICE connect to portA and CODEC ES305_CLK_12M 12MHZ_15PF_FK1200007 1 Vcount R182 1 AUDIO_DOUT2 (6) AUDIO_FS2_VOICE connect to portA and CODEC. portC and 4 3 VDD_IO_305 D6 VDD_DAL_305 C6 ES305_CLK_12M (7) AUDIO_UART4_TX T28PAD @ B (7) AUDIO_UART4_RX (6) ES305_INT_R T29PAD @ (17. June 13.7) PWR_I2C_SDA T30PAD @ CODEC_OUT A_DI (17. 5 20110823 Modify for Acer request PORTA_DI +VDD_1V8_AUDIO LRC D_DO B_DI DAC 1 C_CLK CODEC_IN 2 DAP2_FS A_DO 2 AUDIO_SCLK2 DAP2_SCLK C_DI Active --> 17 mA Sleep --> 35 uA VDD_IO 1 AUDIO_DOUT2 CPU.33. X5 (6) EN_ES305_OSC 0. INC. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.29.5 4 3 2 1 +VDD_1V8_AUDIO 1 R168 2 0_0402_5% VDD_IO_305 1 2 1 C193 1U_0402_10V4Z 2 C194 0.29.1U_0402_10V6K D D +VDD_1V8_AUDIO VDD_DAL_305 1U_0402_10V4Z 2 1 C197 0.4.4. AUDIO_SCLK2 connect to portB. INC.33. 2012 1 Sheet 16 of 35 Rev 1. Inc. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.1U_0402_10V6K Modify for Acer request 2 2 C380 0.31.1U_0402_10V6K NC to COM COM to NC AUDIO_DOUT2 NO to COM COM to NO AUDIO_DIN2 L ON OFF ES305 H OFF ON CODEC R170 470K_0402_5% 1 2 3 4 5 IN1 NO1 GND NO2 IN2 +VDD_1V8_AUDIO COM1 NC1 V+ NC2 COM2 10 9 8 7 6 CODEC_IN 1 CODEC_OUT TS5A23157RSER_QFN10_2X1P5 2 +VDD_1V8_AUDIO AUDIO_DOUT2_R 1 R177 2 0_0402_5% AUDIO_DIN2_R 1 R178 2 0_0402_5% 1 R171 2 0_0402_5% 1 R174 2 0_0402_5% (17) AUDIO_SCLK2_VOICE 1 1 1 C (17) AUDIO_FS2_VOICE Output H OPEN L OSC out OSC out High Z 2 0_0402_5% 1 2 2 R183 470K_0402_5% OE GND VDD OUTPUT AUDIO_FS2 connect to portB.01U_0402_25V7 2 R187 0_0402_5% @ R184 10K_0402_5% C195 SA000039100 2 2 1 C198 U23 AUDIO_SEL_R 1 1 R169 2 0_0402_5% 2 VDD_P_305 2 2 1 C196 1 1 4 3 2 Title ES305 Size C Date: Document Number V0JET(A210)-LA8981P Wednesday.

Speaker Conn.3V6M 1U_0402_10V4Z C250 2 CDC_LEFT_P 1 2 CDC_LEFT_N 1 C251 1U_0402_10V4Z AMIC_L+ AMIC_L- 1 2 1 EAR_JACK_GND R200 0_0402_5% +5VS A 1 1 1 5 6 +3VS 2 C261 2 ACES_88266-04001 ME@ 100P_0402_50V8J 1 100P_0402_50V8J 1 1 100P_0402_50V8J C240 C241 C242 C243 2 2 2 D7 100P_0402_50V8J 3 2 TVNST52302AB0_SOT523-3 D6 TVNST52302AB0_SOT523-3 2 1 2 2 SPK1 1 2 3 4 SPK_L# SPK_L SPK_R# SPK_R 1 2 2 2 2 3 L20 L21 L22 L23 2 SPKR_LEFT# SPKR_LEFT SPKR_RIGHT# SPKR_RIGHT L50 L51 47P_0402_50V8J 1 R221 620_0402_5% 2 2 C237 R260 620_0402_5% 47P_0402_50V8J 4. B 1 FBMA-101_0402 1 FBMA-101_0402 1 FBMA-101_0402 1 FBMA-101_0402 1 2 1 1 2 3 4 G1 G2 3 3 4 1 2 1 G1 G2 E&T_3800-E02N-00R SP02000S010 D8 TVNST52302AB0_SOT523-3 EAR_JACK_GND (18) GND GND 2 1 5 4 +VDD_1V8_AUDIO_LDO 2 1 LDO@ C144 0.3VM C399 1 620_0402_5% C2531 47P_0402_50V8J S Q23 NONLDO@ BSS138W-7-F_SOT323-3 1 NONLDO@ 2 MIC_GND 2 0_0402_5% D 2 G +MIC_BIAS 1 SD028000080 3 2 Title Audio Codec / AMP Size C Date: Document Number Rev 1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.29.4. INC.7U_0402_6.33.5 4 3 AUDIO_SCLK2_VOICE +AVDD_CDC C213 1U_0402_10V4Z 2 300K_0402_1% R457 1 1 2 2 1 1 C214 1U_0402_10V4Z Close U113. 5 JMIC1 2 1 AMIC_L+_R +3VS 0_0603_5% 1 R1376 2 2 C238 SHUTDOWN# A2 B3 C2 C206 2 1 33P 50V J NPO 0402 C207 33P 50V J NPO 0402 0_0603_5% 2 @1 R445 @ 1 C239 VO+ VO- 620_0402_5% 1 +AMP_VDD VDD PVDD IN+ IN- 2 @ +AMP_VDD EN_SPEK resistor is for gain setting A1 C1 2 R269 2 close to 8903 for psudo differential SP02000SC00 +AMP_VDD U2 100K_0402_1% 1 R259 2 1 2 R263 100K_0402_1% 2 AMIC_L+ AMIC_L- B 1 10U_0402_6. Compal Secret Data Security Classification Issued Date 4 LDO@ C116 0.31.4.1U_0402_10V6K LDO@ CE VDD NC GND VOUT RP114Q182D-TR-FE_SC-88A5 1 LDO@ C145 1U_0402_10V4Z 2 B1 B2 VO+ VO- C2 1 2 3 2 VDD PVDD IN+ IN- resistor is for gain setting APA2010HAI-TRG WLCSP 9P CLASS D AMP U8 2 0_0402_5% 1 GND GND EN_SPEK A1 C1 2 0_0402_5% @ A2 B3 SPKR_LEFT SPKR_LEFT# 100K_0402_1% 1 R267 2 1 2 R268 100K_0402_1% R448 1 LDO@ +VDD_1V8_AUDIO_EN R449 1 2 1U_0402_10V4Z B1 B2 C3 A3 1U_0402_10V4Z 2 2 1U_0402_10V4Z +MIC_BIAS 1 10U_0402_6.10 1 Close U113.1U_0402_10V7K 2 C C202 +VDD_1V8_AUDIO 2 2 0_0402_5% +VDD_1V8_MIC R151 1 NONLDO@ +VDD_1V8_AUDIO_LDO 2 0_0402_5% R165 1 LDO@ C237 Main MIC R243 620_0402_5% LDO@ 1 1 C270 R265 1 1 AMIC_LEFT+ AMIC_LEFT- referece to Acer Int.3VM 2 2 1 2 C236 33P 50V J NPO 0402 +CPVDD 1 R191 @ 0_0402_5% 2 R190 @ 0_0402_5% 2 +VDD_1V8_AUDIO EN_SPEK 1 1 AUDIO_CLK_R R28 1 1K_0402_5% HP_IN (18) HP_IN 2 2 HP_DET# (6) 1 C9 0.3VM +VDD_1V8_AUDIO Close to U25 29 +MIC_BIAS 25 14 15 +VMID_CDC +VPOS_CDC +VNEG_CDC +MIC_BIAS +VMID_CDC +VPOS_CDC +VNEG_CDC R9 100K_0402_5% 12 26 41 1 CPGND AGND GNDPAD DGND IN3R IN3L TP38 TP39 CDC_LEFT_P CDC_LEFT_N CDC_RIGHT_P CDC_RIGHT_N 11 13 CFB1 CFB2 GPIO3/ADDR DMIC_DAT/GPIO2 DMIC_LR/GPIO1 HPGND (18) R447 10_0402_5%2 22 23 28 27 LOP LON ROP RON DACDAT ADCDAT CDC_HP_R (18) CDC_HP_L (18) C226 C227 1 2 WM8903LGEFK-RV_QFN40_5X5 SA00003MP00 4.5 2 2.0 V0JET(A210)-LA8981P Wednesday. INC.3V6M 2 2.3V6M U25 (16.1U_0402_10V6K 2 1U_0402_10V6K 30 33 1 R198 38 3 4 EN_SPEK 2 0_0402_5% SHORT_DETECT +VDD_1V8_AUDIO_EN R430 1 (7) SHORT_DET DCVDD DBVDD CPVDD AVDD 16 18 17 HPOUTR HPOUTL HPGND CDC_HP_R CDC_HP_L R443 10_0402_5%2 @ 1 R157 1 0_0402_5% 2 200mA +VDD_1V8_AUDIO D R446 10_0402_5%2 SCLK SDIN INTERRUPT 19 21 20 LINEOUTR LINEOUTL LINEGND MCLK BCLK LRC MICBIAS IN1R IN1L VMID VPOS VNEG IN2R IN2L C223 1 CFB1 CFB2 2 2.2U_0402_6.1U_0402_10V6K 2 1U_0402_10V6K 31 34 AMIC_LEFT- C269 1 C258 1 2 0.1U_0402_10V6K +VDD_1V8_AUDIO 2 2 C220 1 D (18) COM_MIC R194 2 0. INC.2U_0402_6.7U_0402_6.7) PWR_I2C_SDA R196 2 Audio Codec +VDD_1V8_AUDIO 0_0402_5% 1 20_0402_5% 0.1U_0402_10V6K A C3 A3 SPKR_RIGHT SPKR_RIGHT# SHUTDOWN# APA2010HAI-TRG WLCSP 9P CLASS D AMP Compal Electronics.24 VDD_1V8_GEN 1 2 FBMA-10-100505-121T_0402 R322 1 R256 1 +CPVDD +AVDD_CDC 2 0_0402_5% 2 0_0402_5% 37 36 5 (6) CDC_IRQ# 2 6 8 (6) AUDIO_CLK_R (16) AUDIO_SCLK2_VOICE (16) AUDIO_FS2_VOICE 7 9 (16) CODEC_IN (16) CODEC_OUT R3921 COM_MIC 1 2 1K_0402_5% CDC_COM_MIC 2 C230 1 C231 1 2 C209 2. Inc.3V6M 1 S SUPPRE_ KC FBMA-11-100505-680T 0402 S SUPPRE_ KC FBMA-11-100505-680T 0402 AMIC_LEFT+ AMIC_LEFT- C2561 3 2 C2551 2 1 10U_0402_6.39 2 C212 1U_0402_10V4Z Close to U25 C216 1U_0402_10V4Z C217 2 Close U113.29.1U_0402_10V6K 1 2 C228 2 C 1 C229 2 1 2 C219 68P_0402_50V8J 1 @ +MIC_BIAS 1 2.3V6M U5 C248 CDC_RIGHT_P 1 CDC_RIGHT_N 1 C249 LDO@ C143 1U_0402_10V4Z 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.3VM C218 68P_0402_50V8J 1 @ Close U113.7U_0402_6. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. June 13.2K_0402_1% 1 R197 100P_0402_50V8J 2 1U_0402_10V6K 2 1U_0402_10V6K 32 35 AMIC_LEFT+ C224 1 C225 1 2 0.33.7U_0402_6.3V6M C2541 47P_0402_50V8J Vth (Max) = 1.2U_0402_6.40 4. 2012 1 Sheet 17 of 35 .2U_0402_6.31. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.3V6M 1 20_0402_5% 1 39 40 10 24 L41 L17 1 2 FBMA-10-100505-121T_0402 2 4.7) PWR_I2C_SCL (16.

June 13.1U_0402_10V7K HP Switch A A Title <Title> Size C Date: 5 4 3 2 Document Number V0JET(A210)-LA8981P Rev 1. 2012 1 Sheet 18 of 35 .0 Wednesday.5 4 3 2 1 Audio Jack ME@ 2 COM_MIC_JACK_R R1427 HP_LEFT HP_IN HP_RIGHT COM_MIC_JACK EAR_JACK_GND EAR_JACK_GND (17) 0_0402_5% D 1 2 0_0402_5% COM_MIC (17) 3 SINGA_2SJ3005-008211 2 2 @ 1 R1428 @ COM_MIC 1 EAR JACK GND_R HP_IN (17) HP_LEFT D2 TVNST52302AB0 SOT523 R1429 0_0402_5% 2 6 R1320 1 COM_MIC_JACK 0_0402_5% 1 2 10K_0402_5% 7 5 4 3 1 2 10K_0402_5% 1 2 JLINE1 D R1431 R1430 0_0402_5% 2 1 R436 2 3 1 HP_RIGHT SCA00001W00 JLINE1 HPGND (17) HP_LEFT 2 @ 0_0402_5% 1 R409 HP_L R429 0_0402_5% 2 1 HP_RIGHT @ 0_0402_5% 2 1 R423 HP_R 2 100P_0402_50V8J C210 L(4) CDC_HP_R (17) C211 2 @ C CDC_HP_L (17) 1 R431 0_0402_5% 2 @ 1 1 C2641 2 @ 1 C2642 2 @ 1 100P_0402_50V8J 0_0402_5% 1 R426 2 100P_0402_50V8J CLOSE TO SCA00001W00 100P_0402_50V8J 1 D1 TVNST52302AB0 SOT523 C GND(5) R(1) MIC(7) 1 +VDD_3V3_GMI_TEGRA +VDD_1V8_BB_TEGRA B (7) DEBUG_UART1_RX DEBUG_UART1_RX For debug port leakage 2 R438 0_0402_5% 1 2 R1365 100K_0402_5% 2 U146 D29 RB751V-40_SOD323-2 2 1 HP_LEFT HP_L A2 A3 B3 C3 D3 (7) UART_SW NC to COM COM to NC V+ NO2 NO1 COM2 COM1 NC2 NC1 IN2 IN1 GND A1 B1 C1 D1 D2 DEBUG_UART1_TX (7) HP_RIGHT HP_R TS5A22362YZPR_DSBGA10 NO to COM COM to NO ON OFF HP H OFF ON Debug SA00005AE00 @ R1366 100K_0402_5% 2 L 1 IN B @ 1 C1484 0.

0 V0JET(A210)-LA8981P Wednesday.7) GEN1_I2C_SDA (19. INC.1U_0402_10V6K 1 2 0.5 4 GYRO_FSYNC 2 1 V_logic must be <= VDD at all time 1 1 GYRO_CLKIN 3 R255 @ 10K_0402_5% +VDD_3V3_SENSOR 2 2 R253 @ 10K_0402_5% D D 2 3 4 5 14 15 16 17 R224 2 10K_0402_5% 2 NC NC NC NC NC NC NC NC 1 C255 SCL SDA 1 2 0_0402_5% H2 HOLEA H3 HOLEA H4 HOLEA H5 HOLEA H11 HOLEA 1 GYRO_INT 2 2200P_0402_25V7K 23 24 H1 HOLEA 1 R220 1 2 0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. INC. June 13.7) 2 0_0402_5% IME_DA 2 IME_CL 0_0402_5% 1 2 R231 0_0402_5% C G_ACC_INT (7) KXTI9-4100_LGA10_3X3 +VDD_1V8_SENSOR CLIP14 EMIST_SUL-12A2M_1P CLIP16 EMIST_SUL-12A2M_1P 1 1 1 CLIP15 EMIST_SUL-12A2M_1P CLIP12 EMIST_SUL-12A2M_1P CLIP17 EMIST_SUL-12A2M_1P CLIP18 EMIST_SUL-12A2M_1P C1 CLIP19 EMIST_SUL-12A2M_1P AK8975C_BGA14 CLIP21 EMIST_SUL-12A2M_1P CLIP22 EMIST_SUL-12A2M_1P CLIP23 EMIST_SUL-12A2M_1P CLIP24 EMIST_SUL-12A2M_1P CLIP25 EMIST_SUL-12A2M_1P CLIP34 EMIST_SUL-12A2M_1P 1 1 CLIP33 EMIST_SUL-12A2M_1P 1 CLIP31 EMIST_SUL-12A2M_1P CLIP32 EMIST_SUL-12A2M_1P 1 CLIP30 EMIST_SUL-12A2M_1P 1 CLIP29 EMIST_SUL-12A2M_1P 1 1 CLIP26 CLIP27 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P 1 1 1 B Ecompass 1 note: IC 上下層不走power trace B 1 1 CLIP13 EMIST_SUL-12A2M_1P C2644 0.7) GEN1_I2C_SDA DRDY CLIP1 EMIST_SUL-12A2M_1P +VDD_3V3_SENSOR U147 1 ECOM@ 2 C3 R1404 0_0402_5% A3 R1414 1ECOM@ 2 0_0402_5% 1 2 D4 R1412 ECOM@ 0_0402_5% B4 1 (6) COMPASS_DRDY 1 +VDD_ECP ECOM@ 10mil A A Issued Date Compal Electronics. Inc.7) H6 HOLEA H7 HOLEA 1 1 VDD REGOUT FSYNC INT CPOUT CLKOUT 1 AD0 1 C256 0.1U_0402_10V6K CLKIN IME_DA IME_CL VLOGIC AD0 H9 HOLEA 1 1 6 7 8 9 GYRO_CLKIN IME_DA IME_CL +VDD_1V8_SENSOR H12 HOLEA 1 U29 1 GYRO FD1 FD2 1 FD3 1 FD4 1 18 GND 19 21 RESV RESV MPU-3050_QFN24_4X4 G Sensor R235 1 GS@ 1 R234 GS@ U31 R225 1 2 0_0402_5% +VDD_1V8_SENSOR 1 2 3 4 5 1 C C259 0.7) GEN1_I2C_SDA (19.7) GEN1_I2C_SCL (19. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.1U_0402_10V6K 2 IO VDD DNC DNC GND VDD SDA SCL DNC INT DNC R2331 1 R232 10 9 8 7 6 G_INT 2 0_0402_5% 2 0_0402_5% GEN1_I2C_SCL (19.1U_0402_10V6K 1 1 1 C253 1 C254 GYRO_FSYNC 1 13 10 11 12 20 22 H8 HOLEA GYRO_INT_R (6) GEN1_I2C_SCL (19. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_10V7K ECOM@ 1 A2 C4 B1 1 +VDD_ECP VID VDD 1 (19. 5 4 3 2 Title GYRO/G-Sen/E-Compass/Clip Size C Date: Document Number Rev 1.1U_0402_10V7K 2 ECOM@ CLIP11 EMIST_SUL-12A2M_1P CLIP35 EMIST_SUL-12A2M_1P 1 VSS 1 1 RSV 350 μA CLIP10 EMIST_SUL-12A2M_1P 1 D1 D2 CAD0 CAD1 2 CLIP3 EMIST_SUL-12A2M_1P 1 CSB# 1 CLIP2 EMIST_SUL-12A2M_1P 1 A1 C2 B3 350 μA 1 A4 SCL/SK SDA/SI TST1 TST2 SO TST6 0_0402_5% ECOM@ R222 2 1 2 1 ECOM@ R223 0_0402_5% C2643 0. INC. 2012 1 Sheet 19 of 35 .

2012 1 20 of 35 Rev 1. Inc.0 . INC.7U_0402_6.8V_2M_AVDD_R +2.1U_0402_10V6K 1 1 C1389 2.3V6M @ C VIN 1 (7) EN_CAM_2V8 Recever C2685 @ 0. June 13.2U_0603_10V6K 2 +3VS 10K_0402_5% 2 2 2 1 +2.1U_0402_25V6 R1369 0_0402_5% 1 +VDD_CAM_1V8 1 R1340 2 @ 0_0402_5% (6) 2M_CAM_CLK#_R 4 B WCM-2012HS-900T_0805 L91 1 4 2 +VDD_CAM_1V8 2 1 R1342 2 @ 0_0402_5% CSI_CLKB_PP 1 R1343 2 @ 0_0402_5% CSI_D1B_NN WCM-2012HS-900T_0805 L92 1 1 2 CAM_MCLK 1 R1341 2 0_0402_5% 3 @ C1476 10P_0402_25V8K 2 1 R1416 2 @ 0_0402_5% (6) 2M_CAM_DA1_R (6) 2M_CAM_RST# (6) CAM_I2C_SDA (6) 2M_CAM_PWDN (6) CAM_I2C_SCL (6) CAM_MCLK 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. Compal Secret Data Security Classification 2012/05/20 2012/01/09 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.8V_2M_AVDD_R (6) 2M_CAM_CLK_R 4 21 22 3 (6) 2M_CAM_DA1#_R 4 ACES_88194-2041 2 1 3 1 2+VDD_CAMIO_1V8 C1494 10P_0402_25V8K CSI_CLKB_NN 2 1 CSI_D1B_PP CSI_CLKB_NN CSI_CLKB_PP CSI_D1B_NN CSI_D1B_PP GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 JP14 B SP01001CB10 2M connector A A Issued Date Compal Electronics. INC.01U_0402_25V6 4.3M_AGND 0_0402_5% R1152 2M_CAM_RST# CAM_I2C_SDA 2M_CAM_PWDN CAM_I2C_SCL +2. 5 4 3 2 Title 2M CAMERA Size Document Number Custom Date: V0JET(A210)-LA8981P Sheet Wednesday.8V_AVDD U141 C1401 0. INC.5 4 3 2 1 D D VDD_1V8_GEN +VDD_CAMIO_1V8 2N7002KW_SOT323-3 @ Q73 2 G S 3 D 1 @ R1573 2 +VDD_CAM_1V8 1 1 C 2 3 VOUT 5 2 R143 0_0402_5% GND NC 1 C1413 EN 2 APL5603-28BI-TRG SOT-23 -5 R1415 100K_0402_5% 1 2 1 4 C1402 0.

June 13. 5 4 3 2 Title USB / Micro SD Size C Date: Document Number V0JET(A210)-LA8981P Wednesday. INC. INC. Inc.0 .3VM_R35M PJDLC05C_SOT23-3 USB3_DN_COMM 2 USB3_DP_COMM 3 4 2 VCC GND1 D- GND2 D+ GND3 GND GND4 5 6 7 D 8 39P 50V J NPO 0402 1 R1036 @ (6) USB_HOST_DP 2 0_0402_5% USB3_DP_COMM TYCO_2041149-1 @ TVNST52302AB0_SOT523-3 +USB_VOUT_F 2 +USB_CLIENT 3 1 @ R1037 1 @ D35 0_0402_5% 2 USB1_DN_COMM D16 1 L24 WCM-2012HS-900T_0805 2 4 3 2 2 JP70 1 3 2 0_0402_5% USB1_DP_COMM C1233 @ 2 1 @ @ R1295 100K_0402_5% PJDLC05C_SOT23-3 R1038 C 1 +USB_CLIENT 3 4 (6) USB1_DP 1 1 (6) USB1_DN 0.3V6K 1 2 3 4 +3VS +VDD_3V3_SDCARD 1 C431 C311 0.3V6K C124 1 2 2 2 4 2 0_0402_5% USB3_DN_COMM 1 4 D 2 3 JP72 U104 1 2 3 4 1 R1184 GND IN IN EN OUT OUT OUT OC# 8 7 6 5 1 1 G547F1P81U_MSOP8 100K_0402_5% C1225 C48 1 + 2 150U_B2_6. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.7U_0603_6. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.47U_0402_6.01U_0402_25V7 2 1 2 2 C430 1 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. INC.1U_0402_25V4Z 1 2 2 2 USB1_DP_COMM 3 C1234 (6) USB1_ID 4 0.1U_0402_25V4Z 5 VBUS GND4 GND3 CND2 GND1 DD+ 9 8 7 6 C ID GND ACON_MUC4A-557700 1 TP37 1 USB1_DN_COMM 2 @ R1300 100K_0402_5% USB Port Micro SD +VDD_3V_SD @ R1413 1 2 0_0402_5% 45mA +VDD_3V3_SDCARD 1 +VDD_3V3_SDCARD U56 2 R1559 1 OUT OUT OUT OC# 8 7 6 5 APL3510DXI-TRG MSOP 8P 1 D 3 100K_0402_5% (4) EN_3V3_SDCARD GND IN IN EN# S 2 G Q69 MESS138W-G_SOT323-3 R441 1 0_0402_5% B 2 +VDD_3V3_SDCARD 0.7) SD_DET# R343 2 R342 2 R341 2 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% R368 2 1 0_0402_5% SDMMC_CLK_R R340 2 R339 2 1 0_0402_5% 1 0_0402_5% SDMMC_DAT0_R SDMMC_DAT1_R SD_DET# pin Normal : H Insert Card reference Acer schematic 1 2 3 4 5 6 7 8 9 SDMMC_DAT2_R SDMMC_DAT3_R SDMMC_CMD_R 1 : L DAT2 CD/DAT3 G6 CMD G5 VDD G4 CLK G3 Vss G2 DAT0 G1 DAT1 SWITCH TERM CD 15 14 13 12 11 10 C325 10P_0402_25V8K UPDATE LIBRARY 1 2 2 R344 0_0402_5% SDMMC_CLK_R SDMMC_DAT0_R SDMMC_DAT1_R SDMMC_DAT2_R SDMMC_DAT3_R SDMMC_CMD_R A A 1 1 C367 10P_0402_25V8K 2 2 C368 10P_0402_25V8K 1 2 C369 10P_0402_25V8K 1 2 C370 10P_0402_25V8K 1 1 C371 10P_0402_25V8K 2 C310 10P_0402_25V8K 2 Issued Date Compal Electronics. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. 2012 1 Sheet 21 of 35 Rev 1.1U_0402_25V4Z B 2 C312 1U_0402_10V4Z JMDS1 (5) SDMMC_DAT2 (5) SDMMC_DAT3 (5) SDMMC_CMD (5) SDMMC_CLK (5) SDMMC_DAT0 (5) SDMMC_DAT1 (4.5 4 R1035 1 @ (6) USB_HOST_DN 1 1 L25 WCM-2012HS-900T_0805 D19 +5VS +3VS 2 3 3 3 2 1 +USB_VOUT_F 4.

INC.1U_0402_10V6K 2 HOT_RST#_R 4 TAFG1-12WQR_3P 1 D C47 2 D11 1 2 2 Ground 1 1 10K_0402_5% 2 3 ONKEY# (22.5 1 MRDLY VCC GND RESET CD MR 1 2 1 10P_0402_25V8K C2648 3 4 R1569 100K_0402_5% U158 1 2 3 C2684 2 1 R1565 100K_0402_5% R1564 0_0402_5% 2 1 0_0402_5% 1 3 2 1 VOL_UP# (4. TMR(ms) =88000 x CMR (uF) = 8000 x 0. TCD(ms)=1860 CD (uF) = 1860 x 0. Inc.01(uF) =880 ms After Power BTN release. June 13. 2012 1 Sheet 22 of 35 . INC. RESET output high after TCD.47U_0402_6. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.31) 2N7002KW_SOT323-3 ONKEY_R# 1 HOT_RST# (7) HOT_RST# 2 5 D Q72 2 1 1U_0402_10V4Z 1 TVNST52302AB0 SOT523 3 1 2 3 SW2 NTC325-AA1J-A160C_3P 1 D SW1 RB751V-40_SOD323-2 D21 1R1566 S 0_0402_5% 2 G @ 2 Bottom Side Power Button VDD_1V8_PMU_VRTC VDD_1V8_PMU_VRTC 1 1/17 M 1 VDD_5V0_SBY 56K_0402_5% R433 6 5 4 2 1 Q4 BSS138W-7-F_SOT323-3 S ONKEY# (22.1U_0402_10V6K 2 1 R1407 1K_0402_1% VOL_UP#_R 2 2 1 1 2 1 2 +3VALW SW4 TC303-CA1G-D180T-B SPST H3.5 R317 2 GND +3VALW VCC VB1 KHN4NZ3RB_3P volume button up / down Issued Date Compal Electronics. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.5 4 3 2 1 1 +5VS 2 R1435 100K_0402_5% R13 ONKEY_R# (7) 3 C2645 3 4 5 6 7 8 D30 TVNST52302AB0 SOT523 0.31) ONKEY_R# G677L308A31U_ADFN6_1P5x1P5 1 1 1 2 C2680 0. ONKEY# pulling LOW.7) 2 2 A 2 2 D32 TVNST52302AB0 SOT523 1 C2649 1 10P_0402_25V8K 3 3 4 A 1 C2682 SW5 NTC303-CA1G-D180T-B SPST H3. INC.47U_0402_6.01(uF)=18.3V6K 2 1 R1408 1K_0402_1% VOL_DOWN#_R 2 6 5 4 1 R320 VIB_EN_T30S (4) 0_0402_5% R321 100K_0402_5% VOL_DOWN# (4.1U_0402_10V6K VIBRATOR 2 B 1 +3VS 0_0402_5% 1 1 +3VALW +3VALW 2 R1567 100K_0402_5% +3VALW 2 G1 G2 GND 1 R1570 100K_0402_5% Q71 5 1 S1 D1 D2 S2 4 3 6 1 R1571 @ 1K_0402_1% R318 @ 2 1 D 0_0402_5% DMN2004DWK-7_SOT363-6 BSS138W-7-F_SOT323-3 Q20 2 1 2 G S 3 2 0.0 V0JET(A210)-LA8981P Wednesday.7) 1 2 C2681 0. 5 4 3 2 Title Power LED/Lock LED/Ecompass Size C Date: Document Number Rev 1. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.6 ms C SW3 1 2 3 2 3 SC_LOCK# (7) 4 5 3 GND GND 1 SS-B70-BK-S100_3P 2 C2679 0.01U_0402_25V7 100P_0402_50V8J 2 2 Lock C Press Power BTN "TMR" sec.022U_0402_25V7 MRDLY VCC GND RESET CD MR HDRST (31) D 2 G HOT_RST# To PMU 3 1 2 3 @ C2683 R1434 @ 100K_0402_5% 2 2 R1562 100K_0402_5% U157 2 power button delay 1 sec circuit 1 1 R432 100K_0402_5% 1 D31 TVNST52302AB0 SOT523 Power LED 1 2 R1406 1K_0402_1% @ C2646 1000P_0402_50V7K 1 1 2 2 W_LED_CTL_R O_LED_CTL_R 5mA 2 5mA 3 R1563 1 2 1 VDD_5V0_SBY 0_0402_5% Amber HT-210UD5-BP5_AMBER-WHITE +3VS_VB R316 @ C2647 1000P_0402_50V7K +3VS_VB O_LED_CTL (27) O_LED_CTL B LED1 White 1 R1405 2 470_0402_1% W_LED_CTL (27) W_LED_CTL 2 C303 0.3V6K 0.

1U_0402_10V6K 1 C163 1U_0402_10V4Z 2 1 47K_0402_1% 2 6 2 R414 200K_0402_1% @ (4) EN_SENSOR_3V3 R427 1 2 0_0402_5% R424 1 2 0_0402_5% 1 100K_0402_5% 1 Q25A DMN2004DWK-7_SOT363-6 2 C391 0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.01U_0603_50V7K 3VS_GATE Q70A DMN66D0LDW-7_SOT363-6 4 VDD_1V8_GEN 1 2 3 VDD_5V0_SBY 1 2 C458 1U_0603_10V6K 3. INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.1U_0402_10V6K C460 10U_0805_10V4Z 2 2 1 C JUMP_43X118 2 1 3 Q46 S TR DMN3150LW-7 1N SOT-323-3 R300 2 (7) EN_CAM_1V8# +3VALW TO +3VS 1 G D 2 G 2 3 D 1 S C +VDD_3V3_FUSE_TEGRA Q33 ME2301A-G_SOT23-3 R19 2. Change C160 1U_0402_10V4Z 2 +3VS +VDD_3V3_SENSOR B B Q38 ME2301A-G_SOT23-3 S 2 1 2 G (7) EN_SENSOR_1V8# 1 D 3 R330 1 SB00000JL00 VDD_5V0_SBY C390 @ 0.0 . VDD_1V8_GEN +VDD_CAM_1V8 Q26 ME2301A-G_SOT23-3 D 1 2 S SB00000JL00 VDD_5V0_SBY 1 +3VALW +3VS C159 1U_0402_10V4Z 1 J3 1 R326 200K_0402_1% 100K_0402_5% U21 2 C389 0.3V 2 R415 2 (7) EN_SENSOR_3V3_2 1.1U_0402_10V6K 1 3.2K_0402_1% 2 2 1 +3VS 6 C33 1U_0402_10V4Z 1 2 G 1 1 Q33 close to T30S SB00000JL00 4 S 3 R05. June 13. 2012 1 Sheet 23 of 35 Rev 1.8V A A Issued Date Compal Electronics. INC.3V 1 @ C461 10U_0805_10V4Z 5 (4) EN_T30S_FUSE_3V3 1 100K_0402_5% 1 AO4409L_SO8 8 7 6 5 1 2 3 R325 2 C459 10U_0805_10V4Z 3 C384 0. 5 4 3 2 Title DC interface/Power Button Size C Date: Document Number V0JET(A210)-LA8981P Wednesday. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.5 4 3 2 1 VDD_1V8_GEN VDD_PMU_LDO5 2 R390 1 +VDD_1V8_SDMMC4_TEGRA 0_0402_5% +3VS +3VS 1 2 0_0402_5% R444 1 2 0_0402_5% R395 2 R397 +VDD_1V8_SDMMC3_TEGRA 1 2 R418 +VDD_1V8_AUDIO_TEGRA 0_0402_5% 2 R393 1 @ 0_0402_5% 1 0_0402_5% 1 +VDD_3V3_LCD_TEGRA 2 0_0402_5% @ R442 1 1 R419 D 1 R401 2 1 2 1 2 R402 1 2 R412 VDD_1V35_DDR3_MEM +VDD_3V3_DDR_RX_TEGRA 2 +AVDD_3V3_USB_TEGRA 1 2 R410 1 1 +VDD_1V0_DDR_HS_TEGRA +VDD_1V35_MEM_TEGRA D 1 0_0402_5% +AVDD_1V2_DSI_CSI_TEGRA VDD_PMU_LDO7 1 2 0_0402_5% +AVDD_1V1_PLL_TEGRA 2 1 0_0402_5% VDD_1V2_RTC_TEGRA R411 +VDD_3V3_LCD_TEGRA 0_0402_5% 2 JUMP_43X79 VDD_PMU_LDO6 +VDD_1V8_BB_TEGRA 0_0402_5% 2 R450 0_0402_5% 2 0_0402_5% +VDD_1V8_SYS_TEGRA 0_0402_5% R404 1 R396 +VDD_1V8_UART_TEGRA 0_0402_5% R406 2 2 0_0402_5% J2 +VDD_1V8_CAM_TEGRA 0_0402_5% +VDD_3V3_SDMMC1_TEGRA VDD_PMU_LDO8 +VDD_3V3_GMI_TEGRA VDD_PMU_LDO4 R407 Q26 close to Camera Conn. Inc. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.1U_0402_10V6K 2 4 Q25B DMN2004DWK-7_SOT363-6 1 20mil 2 2 10mil R385 2 1 510K_0402_5% Q35 ME2301A-G_SOT23-3 (31) EN_3V3_SW S D 2 G SB00000JL00 1 R380 470_0603_5% 2 1 2 EN_3V3_SW 5 Q70B DMN66D0LDW-7_SOT363-6 1 2 3VS_GATE +VDD_1V8_SENSOR 3 1 C463 0. INC.

6V EN_VDD_GPS 1. C2 D10 B4 A9 A10 B9 C9 B10 +1V8_GPS R346 GPS@ 100K_0402_5% F5 E4 E2 6 2 1 FDG6331L_SC70-6 GPS@ C331 1U_0402_10V4Z GPS@ VDD_PRE NC PWR VDDIFP VDDC VDDC VDDC AVSS AVSS VDD1P2_CORE VSSC VSSC VSSC VSSC VSSC VDDIO VDDIO VDDIO E8 J3 K3 G3 F4 B8 C5 D3 2 +3V3_GPS SA00004YJ00 1/17 Add U50 1 2 C333 2.01U_0402_25V7 GPS@ J10 U47 4 GPS_IN3 C2666 1 VDD1P2_GRF Output GPS_VDDPL Input K7 GPS_PWRON_R GPS_VDDIF 1 5 2 BLM15AG601SN1D_2P 2.5 A SA00004BW00 For Antenna circuit Issued Date Compal Electronics.7P_0402_50V8C 2 3 0.2U_0402_6. Inc.2P_0402_50V8 @C2669 @C2669 2 1 3 C2665 2 1 C2670 @ 1 U154 GPS@ IC BGU7005 1 1 0.8V A 1 0. 2012 1 Sheet 24 of 35 .1U_0402_10V7K ACES_20262-0001 2 C315 1 22P_0402_50V8J 2.3V6M SB00000SM00 +3V3_GPS Q29 4 VDD_PRE 1 2 2.3V6M R428 1 GPS@ 2 0_0402_5% @ C319 +3VS H5 GPS_VDDC 1 GPS@ C320 E9 G2 C7 C3 2 K5 +1V8_GPS C6 D7 F3 3 D_GPIO_5 D_GPIO_6 TM1 TM2 TM3 REF_CAP A3 B5 A2 H1 J6 C317 1 GPS_REF_CAP 2 0. INC. 5 4 3 2 Title GPS BCM47511 Size C Date: Document Number Rev 1.2U_0402_6. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.1U_0402_10V7K C2662 1/11 M GPSANT 2 2 L95 BLM15AG601SN1D_2P Antenna GND GND 3 1 +2V8_GPS 2 3 5 5 C335 GPS@ 2.4 GND GND GND 2 7.8V R304 1M_0402_1% GPS@ 10/06 Modify R304 from @ to mount.768KHZ_15PF_KK3270032 (7) GPS_PWRON B H10 CAL_REQ LPO_IN VDD_AUX_IN (7) GPS_RESET# VDD_1V8_GEN J7 CLK IF VDD_AUX_O C139 @ 1P_0402_50V NPO C C323 GPS@ 1U_0402_10V4Z GPS_AUXOP GPS_AUXON TCXO 2 0_0402_5% GPS_CLK_32K_R GND GND 1 OE D TP40 RF GPS_VSSIF GPS_VSSPLL GPS_VSSLNA GPS_VSSLNA GND_IFP 1 4 GPS_RFIP 2 OUTPUT 3 NC NC 4 X3 ENABLE/DISABLE 5 1 K2 F8 VCC 2 G10 F10 26MHZ_10PF_TX6214 GPS@ X2 2 1/31 M Footprint BCM4751IFBG_FBGA_100P-NH 2 VDD 2 J8 J9 K8 K10 E10 A4 1 6 GPS@ K9 C2677 @ 1P_0402_50V NPO GPS_CLK_26M_R C316 0.1U_0402_10V6K GPS@ FDG6331L_SC70-6 GPS@ F2 F7 H3 H4 J2 G8 G7 J1 1 C353 68P_0402_50V8J 1 GPS@ 2 C324 4.3V6M GPS@ GPS_VDDLNA 4 Vcc 6 1 GND @ 1 C313 GPS@ 1 L35 +1V8_GPS 1 0.5NH +-0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. Compal Secret Data Security Classification GPS POWER SOURCE 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. INC.3V4Z GPS@ 1 2 2 GPS_PWRON_R 3 VIN 5 VOUT GND 4 NC +2V8_GPS 1 EN 2 Vth=1.01U_0402_25V7 GPS@ C_GPIO_2 C_GPIO_3 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC E1 D1 B2 A1 R417 R421 R434 R435 1 1 1 1 2 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% GPS_UART_RXD (7) GPS_UART_TXD (7) GPS_UART_CTS# (7) GPS_UART_RTS# (7) E5 B1 E6 D4 C4 E3 F6 E7 9/25 Modify R346 from @ to mount for leakage issue.5 2 1.7P_0402_50V8C C2668 2 2.3V6M APL5603-28BI-TRG_SOT23-5 GPS@ Vth = 1.1NH LQP15MN7N5B02D 1 2GPS_ANT4 1 C2671 2 2 1 GPS_CLK_32K_R GPS_CLK_26M_R GPS@ 1 2 G9 Clock Output 3 GPS_CLK_32K R351 1 GPS@ GPS_CAL 2 A8 A7 R383 1 2 0_0402_5% GPS_RESET#_R A5 R416 1 2 0_0402_5% GPS_PWRON_R J4 H2 K1 B3 GPS_PWRON_R 4 D2 C1 LNA_EN 1 1 1 2 2 2 1 C332 1U_0402_10V4Z GPS@ 2 2 C326 0.22U_0402_6.2U_0402_6.2U_0402_6.1U_0402_10V7K D 1 1 L8 GPS@ L96 470P_0402_50V7K SAFFB1G58KB0F0A C2664 6. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.7U_0402_6.3V6M GPS@ G6 G4 G1 F1 G5 C10 C8 D5 1 Vth = 1. D8 D6 D9 J5 +3V3_GPS 2.8NH_LQG15HN6N8J02D_5% 1 2 1 2 4 Input Output 2 3 5 ANT 0.2U_0402_6.0 V0JET(A210)-LA8981P Wednesday.3V4Z A6 BCM47511IFBG_FBGA100 2 2 C_GPIO_6 C_GPIO_7 REGPU 5 R305 1M_0402_1% GPS@ +3V3_GPS MEMORY 1 GPS@ C318 2 +GPS_AUX_OUT C RST_N 3 6 (7) EN_VDD_GPS 1 K6 HOST_REQ K4 H6 H7 IFVALID SCL2/UART_TX SDA2/UART_RX UART_nRTS UART_nCTS 2 2 AUX_HI GPS_SYNC/PPS_OUT Acer request 5 R303 1M_0402_1% GPS@ H9 F9 NC 1 +1V8_GPS Q28 B7 NC 2 SB00000SM00 H8 UART/I2C IF R348 GPS@ 100K_0402_5% C330 1U_0402_10V4Z GPS@ NC NC NC SYS IF 32.1U_0402_10V6K C379 1 C2663 39P 50V J NPO 0402 L98 RFOUT GND GND GND GND RFIN SHDN +GPS_AUX_OUT 2 L9 GPS@ SAFFB1G58KA0F0AR14_5P 2 2 2 39P 50V J NPO 0402 @ 1 2.3V6M GPS@ B GPS_UART_RXD VDD_BAT GPS@ 1 1 1 B6 C347 68P_0402_50V8J 1 GPS@ C329 1U_0402_6. INC. June 13.

1U_0402_10V6K WIFI@ 1 VOUT_2P5_IN VOUT_2P5_OUT +3VS_WIFI 2 1 2 1 1 +1.1U_0402_10V6K 2 WIFI@ 2 2 @ C388 33P 50V J NPO 0402 2 2 100K_0402_5% @ 2 0_0402_5% 1 1 1 @ C387 22P_0402_50V8J 1 internal weak pull up resister to VDDIO R272 (5) WFMMC_CLK B R367 VBAT_IN WFMMC_CMD_R F1. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.1U +1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.G3 WIFI@ CBUCK_OUT U53 +1.4RF_IN_L (25.8VS_WIFI A3 H9 H2 B9 G9 A2 1 SR_PA_OUT VDD_WL_PA_A_MODE VDDIO_RF VDD_BT_PA VDD_WL_PA C2678 1P_0402_50V NPO WIFI@ R388 33K_0402_5% +VDD_WL_PA 2 C360 0.4RF_IN_L H4 H6 +1.F3.01U_0402_25V7 C344 WIFI@ 1 2 4.01U_0402_25V7 C357 WIFI@ 1 2 4.3V6M H3 J2 (7) CLK_32K_OUT R384 1 WIFI@ 2 0_0402_5% RTC_32K_WIFI D3 H8 D9 C355 WIFI@ 1 2 +VDD_CORE 0.3V6M VDD_LN_IN VDD_LN_OUT VDD1P2_CLDO_OUT VDD_CORE R373 R374 R376 R377 R378 2 3 1 (5) (5) (5) (5) (5) 1 C350 0.7U_0402_6.8VS_WIFI 2 WIFI@ 4 S1 3 D1 6 D2 1 S2 1 G2 2 G1 C 2 0_0402_5% +5VS 1 2 @ +VDD_CORE 2 Q47 5 EN_WIFI_VDD R94 1K_0402_1% WIFI@ 2 R93 100K_0402_5% WIFI@ R361 1 8/22 Change BOM structure U53 NH660@ 8/22 Change BOM structure @ PK29S003400 AW-AH663_86P A PK29S003200 Footprint use AH662 co-lay +CBUCK_OUT 2. Reserve " 2 Pi " filter 1 2 1 1 1 5 6 R308 1M_0402_1% WIFI@ C339 1U_0402_10V4Z WIFI@ 2 1 C342 1 4. June 13.5 VDD_1V8_GEN C348 1U_0402_10V4Z WIFI@ 2 2 1 D ACES_20262-0001 R375 C341 C340 0. +VDD_WL_PA 3 2 2 R307 1M_0402_5% @ 4 2 2.7U_0402_6.4) EN_WIFI_VDD C136 @ 1P_0402_50V NPO R387 1 WIFI@2 0_0402_5% 2 1 1 2.5 +SR_PA_OUT +3VS +VDD_LN +3VS_WIFI +3VS_WIFI Acer RF request +VDD_WL_PA 1 1 reserve C +VDD1P4_WIFI Q37 C343 4.F2.G2.8VS_WIFI Q32 +SR_PA_OUT 2 2.7U_0402_6.4) EN_WIFI_VDD VIN_LDO B4 B3 FM power +CBUCK_OUT +VDD_WL_PA B1 1 WL_GPIO_1 WL_GPIO_2 4. 5 4 3 2 Title WIFI/BT AH662 Size C Date: Document Number V0JET(A210)-LA8981P Wednesday.8A_20% 10U_0402_6.7U_0402_6.3V6M WIFI@ DMN2004DWK-7_SOT363-6 2 1P_0402_50V NPO C2675 WIFI@ WFMMC_CMD WFMMC_DAT0 WFMMC_DAT1 WFMMC_DAT2 WFMMC_DAT3 1 1 1 1 1 WIFI@ WIFI@ WIFI@ WIFI@ WIFI@ 2 2 2 2 2 WFMMC_CLK_R WFMMC_CMD_R WFMMC_DAT0_R WFMMC_DAT1_R WFMMC_DAT2_R WFMMC_DAT3_R 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 08/09 Add C387. INC.3V6M 68P_0402_50V8J 1 WIFI@ WIFI@ C359 1U_0402_10V4Z WIFI@ 1 1 2 R319 1M_0402_1% WIFI@ Compal ESD request.C388.7U_0402_6.4RF_IN_R 1. AH663 use 0.7U_0402_6. Inc. INC. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.0 .4RF_IN C356 1U_0402_10V4Z NH660@ 6 2 1 2 FDG6331L_SC70-6 WIFI@ C349 1U_0402_10V4Z WIFI@ 1 1 C354 0.5 4 SB00000SM00 +3VS 3 2 1 +3VS_WIFI Q31 4 3 dual-Band wifi RF matching .R272 for WFMMC_CLK C387&C388 from mount to unmount G1 G3 F2 F1 G2 F3 E6 E4 D6 C6 (7) WF_RST# (7) WF_WAKE# R382 1 WIFI@ 2 0_0402_5% TP36 WF_RST#_R +SR_PA_OUT 0.1U_0402_10V6K 68P_0402_50V8J 1 WIFI@ WIFI@ FDG6331L_SC70-6 WIFI@ 2 2 C337 1U_0402_10V4Z WIFI@ 2 1 close to H2 C2672 @ 1P_0402_50V NPO close to G9 close to WIFANT EN_WIFI_VDD Vth = 1. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.3V6M Issued Date Compal Electronics. INC.4RF_IN 2 C137 @ 1P_0402_50V NPO 1 ANT 2 3 C138 @ 1P_0402_50V NPO GND GND WIFANT D 1 SB00000SM00 AH662 use 1U.1U_0402_10V6K C346 R456 @ 15K_0402_5% 2 1 1 1 H1 VDDIO J3 C2 D1 E2 C1 2 +VDD_LN FM_AUDIO_L FM_AUDIO_R ANT_FM_TX ANT_FM_RX ANT_MAIN_EN ANT_AUX_EN BT_I2S_DI BT_I2S_DO BT_I2S_WS BT_I2S_CLK WL_GPIO_5 WL_GPIO_6 BT_PCM_SYNC BT_PCM_CLK BT_PCM_IN BT_PCM_OUT WL_SHUTDOWN#_RST# WL_HOST_WAKE WL_UART_TX WL_UART_RX BT_DEVICE_WAKE BT_HOST_WAKE BT_SHUTDOWN# BT_RST# HSIC_DATA HSIC_STROBE BT_UART_RTS# BT_UART_CTS# RTC_CLK BT_UART_TXD BT_UART_RXD A8 A7 A6 A5 J7 B 2.7U_0402_6.3V6M L40 1 +VDD1P4_WIFI C336 WIFI@ 2 1 1 1 2 2 WIFI@ 0.8VS_WIFI D7 D5 C7 B6 +3VS_WIFI @ R366 100K_0402_5% G4 F5 F4 G5 BT_PCM_SYNC (7) BT_PCM_CLK (7) BT_PCM_OUT (7) BT_PCM_IN (7) C8 B7 C3 C4 @ PAD T11 @ PAD T12 @ PAD T13 BT_WAKEUP (7) BT_IRQ# (7) BT_PD# (7) E7 F7 R365 R370 1 WIFI@ 1 WIFI@ 2 0_0402_5% 2 0_0402_5% F8 E8 R371 R369 1 WIFI@ 1 WIFI@ 2 0_0402_5% 2 0_0402_5% BT_UART_RXD @ R386 100K_0402_5% R381 1 WIFI@ 2 0_0402_5% BT_RST# (7) BT_UART_CTS# (7) BT_UART_RTS# (7) BT_UART_RXD (7) BT_UART_TXD (7) NC NC WIFI@ 2 R356 0_0402_5% C378 WIFI@ WIFI@ RP111N331D-TR-FE_SOT23-5 WIFI@ R389 1M_0402_1% WIFI@ ANT_2G4_5G A1 A4 A9 B2 B5 B8 C5 C9 D4 D8 E1 E5 E9 F9 G6 G8 H5 H7 J1 J4 J5 J6 J8 J9 A10 C10 E10 G10 J10 C358 WIFI@ 1 2 4 VFB CE C2676 WIFI@ 1P_0402_50V NPO (25.5P_0402_50V NPO WIFI@ Vth = 1.1U_0402_10V6K 2 WIFI@ 2 1 1 1 5 2 C352 C351 4.3V6M 2 WIFI@ 2 SHI0000FQ00 2 1 2.3V6M A 5 VOUT GND 2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND +VDD_LN D2 F6 E3 G7 TP34 TP35 C345 WIFI@ 1 2 SDIO_CLK_SPI_CLK SDIO_CMD_SPI_DI SDIO_DATA0_SPI_DO SDIO_DATA1_SPI_IRQ SDIO_DATA2_SPI_NC SDIO_DATA3_SPI_CS 2 VDD 4.2UH_VLS252012T-2R2M1R3_1. 2012 1 Sheet 25 of 35 Rev 1.

Inc. INC. INC. 5 4 3 2 Title PWR BLOCK Size C Date: Document Number V0JET(A210)-LA8981P Wednesday. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. 2012 1 Sheet 26 of 35 Rev 1. Compal Secret Data Security Classification 2012/05/20 Deciphered Date 2012/01/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.5 4 3 2 1 D D VIN AC=12V Charger IC BQ24171 +5VS B+ RT8243AZQW SYSTEM Boost-Buck IC +3VALW Battery 2S1P G920AT24U Charge PUMP Boost IC C +5V0_SBY TPS51212DSCR DDR3L PWR RAIL VDD_1V35_DDR3_MEM TPS6591104A2ZRCR T30L PWR RAIL PMU IC B C T30L CHIP B TPS62361YZHR T30L PWR RAIL Boost-Buck IC A A Issued Date Compal Electronics. INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.0 . June 13.

1K_0402_1% 2 1 1 1 PD7 PR215 1 2 1M_0402_1% PR210 1 2 1 VDD_3V3_BQ24171_VREF P2 PQ15 2N7002KW_SOT323-3 3 3 4 PQ13B S SI1034CX-T1-GE3_SC89-6 CHARGER_LED# 6 3 4 S 2 G SI1034CX-T1-GE3_SC89-6 PQ13A S D 5 G 2 Orange LED PQ11B PQ11A D 5 2 G G DMN66D0LDW-7_SOT363-6 SDMN66D0LDW-7_SOT363-6 D IDECT D D PR14 100_0402_1% DMN66D0LDW-7_SOT363-6 PQ36A 2 G BATT+ O_LED_CTL (22) (4) CHARGER_STAT 2 1 PR57 100K_0201_1% 1 100K_0402_1% +3VALW White LED VDD_3V3_BQ24171_VREF S PR31 30K_0402_1% (22) 2 W_LED_CTL BATDRV# 1 6 2 PR54 51K_0402_1% 2 PR55 @ PQ14 SSM3K7002FU_SC70-3 1 2 1 1 D 2 G 3 TTC_PRECH VDD_3V3_BQ24171_VREF 1 1 2 PC36 0.01U_0603_50V7K 2 1 2 1 PD4 @ 1 1 3. input over-voltage.755V Iin=Vacset/(20*PR8)=0.047U_0402_25V7K 2 2 PU2 D 2 G 2. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.7U_0402_6.3 2 PD1 VIN SBR3U40P1-7_POWERDI123-2 2 1 4 Charge_in 1 2 2 WAKE_UP_ACIN (7) 1 RB751V-40_SOD323-2 PC11 0.01)=1.1U_0402_25V6 PC22 10U_0805_25V6K 1 0.02K_0402_1% 2 3 PC23 PVCC PVCC 6 BQ24171_ACP S PR20 1M_0201_1% 0.01U_0402_50V7K DMN66D0LDW-7_SOT363-6 PQ35B 5 2 PR56 1 P2 G 100K_0402_1% PR61 100K_0402_1% 2 Issued Date 2011/06/20 Deciphered Date GND 2 8 P 2 S 2 PR13 1 3 1 191K_0402_1% 1 2 VDD RESET/RESET RT9818A-36PV_SOT23-3 A Batt OVP : Batt+ over 8.2K_0402_1% 4 SW BQ24171_ISET 68K_0402_1% PR34 5 G PQ10B S SI1034CX-T1-GE3_SC89-6 (5) CP_GPIO 1 BATT+ PC25 0.6V*(768+100)/100=13.5V VR=40V 1 1 PQ4 SI7716ADN-T1-GE3_POWERPAK8-5 1 2 3 5 100K_0402_5% PR3 PD2 2 42.022U_0402_25V7K 2 1 PR59 26.888V 0.4)]= 0.6V ## 1.68K_0402_1% 1 2 2 1 @ PR47 10K_0201_1% 10 OVPSET PGND P2 A 1 PC32 0.02_1206_1% BQ24171_SRP 0. 3 D 5 G PQ36B DMN66D0LDW-7_SOT363-6 PR17 1 2 Compal Secret Data Security Classification 2 4 VDECT LM393DMR2G_MICRO8 Change voltage detect and add charge current detect solution to meet Battery taper current 1 4 L: charge in progress H : charge is complete or in sleep mode Blink (0. INC.888V" & "UVP 4.01UF_0402_25V7K 1 ACN 0.314V Setting "OVP 13.2U_0402_6.3*PR33/(PR28+PR33)=1. Low:Disable charge termination & timer.1U_0402_25V6 Battery OVP protect PC21 0. INC. Inc.1% BQ24171RGYR_VQFN24_3P5X5P5 @ PR49 1 2 10K_0402_5% 1 @ PR52 0_0201_5% 2 1 BQ24171_SRP Boot : Static White LED Wake up : Static White LED 5sec PC33 0.1U_0402_25V6 3 2 1 BAT54CW_SOT323-3 2 (7) WAKEUP_LED PR201 226K_0402_1% D 2 G PR60 1M_0402_5% PC127 2 1 S 3 4.047U_0402_25V7K @ 1 JUMP_43X118 BQ24171_ISET Charge Current setting: ICHG=VISET/(20*PR26) <<AC adaptor charge>> VISET=VREF*[PR34/(PR29+PR34)]              =3.01UF_0402_25V7K PC12 0.2UH_PCME051E-2R2MS_3.43K_0402_1% 18 BQ24171_TTC 11 FB PGND TTC 2 9 CHARGER_LED# 14 BQ24171_TS PR37 82K_0402_0.0 Picasso M R02 Wednesday.1U_0402_16V4Z 806K_0402_1% PR16 6 2 1 1 1 2 1 2 1 BTB_OFF 2 2 8 G O - 7 1 O PU1 IDECT PQ35A D P + 4 2 6 PU11B PR25 69.05_1206_1% PC15 1 SRP SRN 1 1 2 2 1 PR36 2.02K_0402_1% 2 BATDRV# PD5 2 PR23 1 19 1 VDD_3V3_BQ24171_VREF B+ ACP BATDRV# 4.4K_0402_0. timer fault and battery absent) 2 20120515 SDMN66D0LDW-7_SOT363-6 1 PR19 2K_0402_1% 2 PR18 2 G 100K_0402_1% PR209 1 S PC40 @ 0.2_0603_5% 16 3 BQ24171_SRN 4 PR35 10_0805_1% 1 1 2 21 4 2 2 BTST PJ1 1 PC29 10U_0603_10V6M VREF 13 BQ24171_SRP 1 12 PR26 1 2 2. INC.1U_0402_25V6 2 1 1@ PR15 2 499K_0402_1% S SI1034CX-T1-GE3_SC89-6 2 6 D PC24 1 2 PR40 2 CHARGER_LED# SB000005N00 PC20 PC19 0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.01UF_0402_25V7K D 3 4 4 2 1 1 PR8 1 D IF=3A VF=0.3V6M WAKEUP_LED 2 G SI1034CX-T1-GE3_SC89-6 PQ10A 1 6 PC37 0.395A <<System on>> Vacset=3.635A PC28 1 2 1 charger_out 3 P2 ISET 17 BQ24171_ACSET PC34 1U_0603_25V6K 1 2 BQ24171_BTST PR30 1 2 2.2K_0402_1% P3 VDD_1V8_GEN PR5 VIN Max Rds(on) 16. June 13.1U_0402_25V6 BQ24171_ACN PQ5A 2 G BTB_OFF PR58 0_0201_5% 1 2 2 2 RB751V-40_SOD323-2 PC18 0.1U_0402_16V4Z PR39 7.5mohm PQ3 SI7716ADN-T1-GE3_POWERPAK8-5 1 2 5 3 P2 1 AC Insert or remove --> Wake up T30S USB Insert or remove --> Wake up T30S SW to check if Acer USB --> Change charge current to 1A 2 CHARGER BQ24171 2 4 OVP UVP Range setting: ##OVPSET voltage is between  0.755A 20 2 1 PD6 BAT54CW_SOT323-3 2 B BQ24171_SRN VDD_3V3_BQ24171_VREF PR42 768K_0402_1% S SI1034CX-T1-GE3_SC89-6 15 2 1U_0402_16V6K 3 D PC31 1 ACSET REGN 1 PR50 0_0201_5% 2 PR44 499_0402_1% (6) BATT_LEARN 3 PQ5B 5 G 2 4 1 0.9K_0402_1% 1 D 1 SBR3U40P1-7_POWERDI123-2 ACDRV BQ24171 internal regulator 267K_0402_1% PR29 PR28 100K_0402_1% 2 CMSRC 8 C 1 2 7 1 4.5Hz): fault occur (charge suspend.1U_0402_25V6 PR48 27.3V6M PC126 2 1 D 2.497V*(768+100)/100=4.3_1206_5% PR11 Title Charger Size A2 2005/4/21 Date: Document Number Rev 1.2U_0603_16V6K 5 PR22 1 2 3 1 PQ27 SSM3K7002FU_SC70-3 2 PC16 0.3V6K 49. ## NVDC must keep TTC low ## Termination current is 10% of fast charge.3*[29. Connect capacitor:Set fast charge timer.314V" 1 2 PR6 10K_0402_5% 5 0.3*(PR33//PR40)/(PR28+(PR33//PR40))=0.01UF_0402_25V7K BATT+ SW PC27 1U_0402_6.1U_0402_25V6 2 G 2 1 1 S 1 2 VDD_3V3_BQ24171_VREF PR205 180K_0402_1% 2 150K_0402_1% VDD_5V0_SBY 1 2 PC45 0.1*(1+R27/R37) 1 2 B 6 1 20K_0402_1% PC43 0. LED status: No charge :  LED off Fully charged : Static White LED  Charging : Static Orange LED Charging error : Flash Orange LED C 0.497~1.395V Iin=Vacset/(20*PR8)=1.327V ICHG=0.allow termination. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.3A_20% BQ24171_SW 24 1 2 PC26 10U_0603_10V6M PL3 2 1 2 1 2 2 2 1 2 1 2 3 1 PR33 73.1U_0402_16V4Z 1 2 BQ24171_OVPSET VDD_3V3_BQ24171_VREF PR45 100K_0402_1% TTC setting: High:Disable charge timer. 2012 1 Sheet 27 of 35 . 2012/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.8V Back to back will turn off Compal Electronics.1% PR43 0_0402_5% 1 2 BQ24171_FB STAT THERMALPAD BATT_TEMP (29) Charging 0-58C LNJT103F011-20 22 23 25 Vbat=2.327/(20*0.8K_0402_1% LM393DMR2G_MICRO8 PR21 @ PD10 @ 200K_0402_1% SBR3U40P1-7_POWERDI123-2 2 1 PU11A PR53 @ 0_0402_5% BATT+ 2 2 PR24 100K_0402_1% 1 1 1 1 2 1 5 2 3 D S 5 PR214 47K_0402_1% - BATT+ 806K_0402_1% PR12 BQ24171_SRN PR27 100_0402_1% 1M_0402_1% + 4 PR211 0_0402_5% 1 PC30 0.4/(267+29.1U_0402_16V4Z PC35 1 2 BQ24171_REGN AVCC TS 2 2 4 BQ24171_AVCC 1 1 PR41 0_0402_5% CP setting: Idpm=Vacset/(20*PR8) <<system off & standby>> Vacset=3.

5m ohm 3 2 1 2 PQ22 SI7716ADN-T1-GE3_POWERPAK8-5 LG_3V LG_5V +5VS Typ: 225mA +5VS 1 PC53 + 2 Rds(on)=13.5m ohm(max) .3VALWP Ipeak=1. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION.0 Thor 4 3 2 Sheet 1 28 of 35 . Imax=0.1U_0603_25V7K UG_3V C 4 EN_3_5V 19 3 2 1 VCLK 8 LX_3V PL4 2.206A .5 4 3 2 D 1 D +3VL PR76 13. INC.5m ohm(max) .7_1206_5% 2 1 5 PC48 PR83 2 12 1BST_3V 0_0603_5% 0. 2012 Date: Rev 1.1U_0402_16V4Z 2 1 VIN1 SI1555DL-T1-GE3 SOT363-6 1 @ PR64 2 Reserve discharge Circuit for 3/5 V Enable pin 17 PR84 0_0603_5% 1 2 BST_5V 5 0_0402_5% 20120515 LX_5V 4 1 PR66 2 1 0_0402_5% PR63 13 SI7716ADN-T1-GE3_POWERPAK8-5 1M_0402_1% (28.5-16.5m ohm(typical) Vtrip=(Rcs*Ics)/8+1mV Vtrip=(36K*9u)/8+1mV=41.2u*300K)*(8.283=1. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. 3VALW/5VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.491A S S 3 6 D 1 EN_3V_5V_SYS# D 2 (28.2u*355K)*(8.095A A @ 2 @ 1 PR32 100K_0402_1% 2 @ PR67 0_0402_5% 2 1 VDD_5V0_SBY A <1> +3.33) EN_3V_5V_SYS 5 4 G PQ37A DMN66D0LDW-7_SOT363-6 PQ37B 5 EN_3V_5V_SYS# G DMN66D0LDW-7_SOT363-6 Compal Secret Data Security Classification 2011/06/13 Issued Date 2012/06/13 Deciphered Date Title Compal Electronics.4-3. Inc.5m*1.096+1. INC.5m*1.2u*355K)*(8.4-5)*5/8.5m*1.5m/(13.2)+(1/(2*L*f)*(Vin-Vout)*Vout/Vin) Iocp_min= 3.533=3.7U_0805_10V6K Typ: 175mA 2 1 Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO 1 PR68 0_0402_5% <1> +5VS Ipeak=3.5-16.31.1A F=300K Hz Rds(on)=16.363m/(13.170+1.2)+(1/(2*2.283=1.3VM_R45M EN1 7 21 PR86 4. Imax=2.2)+(1/(2*2.7_1206_5% PAD PC52 680P_0402_50V7K EN2 2 4 5 6 5 SPOK PU4 CS1 2 1 PR1400_0402_5% VFB1 4 VREG3 (28.8442A F=355K Hz Rds(on)=16.363mV Iocp=Vtrip/(Rds(on)*1.4) =2.7U_0805_10V6K PQ18 2 3 1 2 0_0402_5% 2 PR65 1 VIN1 <1>5V=300KHz 6 3V=355KHz EN_3_5V PC38 0.4-3.1K*9u)/8+1mV=3.33) EN_3V_5V_SYS 3 0_0402_5% 2 CS2 1 VFB2 @ PR89 +3VL EN_3_5V 5 PQ19 SIS412DN-T1-GE3_POWERPAK8-5 C +3VALW 1 36K_0402_1% 5 2 PC47 0.3)*3.1U_0603_25V7K 2 1 1 JUMP_43X118 TPS51225_B+ PC46 2200P_0402_50V7K 2 1 PJ2 B+ PR77 30K_0402_1% 2 1 PR79 20K_0402_1% 1 2 PC44 10U_0805_25V6K 2 1 TPS51225_B+ PC55 4.3/8.2)+(1/(2*2.562+1.453A Iocp_max= 3. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. Rds(on)=13.363m/(16.5m ohm VL PC56 1 2 B 4.3/8. Rds(on)=13.0A .3VM_R45M PR85 4.4) =0.629A Iocp_max= 41.5m ohm(typical) Vtrip=(Rcs*Ics)/8+1mV Vtrip=(2.2UH_MMD-06AH-2R2M-X2A_6A_20% 1 2 UG_5V 15 4 1 14 2 VO1 DRVH1 16 Rds(on)=13.4) =2.31. Wednesday.2UH_MMD-06AH-2R2M-X2A_6A_20% 2 1 20 PQ20 150U_B2_6.1U_0603_25V7K 2 1 PR80 30K_0402_1% 1 2 2 PC42 2200P_0402_50V7K 2 1 2 PC41 10U_0805_25V6K 2 1 1 PC39 0.2)+(1/(2*2.5m/(16.533=4.31.5m*1.2)+(1/(2*L*f)*(Vin-Vout)*Vout/Vin) Iocp_min= 41.3)*3.7K_0402_1% 1 2 PR78 20K_0402_1% 2 1 PR82 1 1 2 3 PGOOD 9 VBST2 PC49 0. June 13.4) =0.2u*300K)*(8.33) EN_3V_5V_SYS VREG5 PQ21 VIN DRVL2 DRVH2 TPS51225_B+ B 18 1 VBST1 10 4 1 2 3 2 SW1 12 + TPS51225CRUKR_QFN20_3X3 SW2 11 1 PC51 680P_0402_50V7K 2 1 PC50 150U_B2_6.5mV Iocp=Vtrip/(Rds(on)*1.1U_0603_25V7K 1 2 DRVL1 SIS412DN-T1-GE3_POWERPAK8-5 PL5 2. INC.208+1.4-5)*5/8.

01U_0603_50V7K 2 ACES_88266-04001 1 PL2 HCB2012KF-121T50_0805 1 2 PC8 1000P_0603_50V7K 1 2 3 4 5 6 PC7 1000P_0603_50V7K 1 2 3 4 GND GND 1 C DC_IN PSG1 @ @PJP3 @ PJP3 1 PD9 LL4148_LL34-2 G922T11U_SOT23-5 B ADJ 5 4 2 887K_0402_1% PR7 EN PU9 2 2 OUT GND 1 1 PD14 IN PC13 0.31. 2012 1 Sheet 29 of 35 .31. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.4. Compal Secret Data Security Classification 2011/06/20 Deciphered Date 2012/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. INC. 5 4 3 2 Title DC IN/BATT IN Size C Date: Document Number Rev 1.01UF_0402_25V7K PWR_I2C_SDA (16.33. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.17. INC.3V6K B 2 267K_0402_1% PR9 A A Issued Date Compal Electronics. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.0 Thor Wednesday.01U_0402_50V7K 1 PD8 LL4148_LL34-2 1 2 1 BATT+ PC212 4.7) 1 0_0402_5% 2 2 0_0402_5% 1 PR1 1 1 PR2 2 2 ACES_88231-07001 PC1 33P_0402_50V8J 8 9 1 2 3 4 5 6 7 1 2 3 4 5 G1 6 G2 7 PC3 1 PL1 FBMA-L11-160808-301LMA20T 1 2 @PJP2 @ PJP2 PC2 1000P_0402_50V7K D 1 BATT_TEMP (27) VIN SPARK_79X118 1 2 PC10 1000P_0603_50V7K 1 2 2 VIN C PC9 1000P_0603_50V7K 2 1 2 1 PC6 0.4.7) D 0.5 4 3 2 SP02000I600 BATT+ 1 2 PC5 0.1U_0402_16V4Z 0_0402_5% 1 VDD_5V0_SBY RB751V-40_SOD323-2 1 PR4 2 PC211 1U_0805_25V6K 2 1 3 2 2 1 1 2 2 PR212 200_0805_5% PC14 1 0. INC.033U_0402_16V7K 1 2 PC4 2200P_0402_50V7K 2 PWR_I2C_SCL (16. Inc.33.17. June 13.7U_0805_6.

Compal Secret Data Security Classification 2011/06/13 2012/06/13 Deciphered Date Title DDR Regualtor THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. INC.35VSP 8 SW_+1.4-1. INC.35VSP 1 @ PC64 0.31K_0402_1% 2 1 1 VFB=0.5m*1.4) =1.1U_0402_16V7K 2 1 (31) EN_DDR_BUCK 2 3 2 1 PU5 PR96 30K_0402_1% 2 1 PR97 0_0402_5% 1 2 PC63 0.35VSP_B+ 2 B+ 5 SW VFB V5IN TST DRVL TP UG_+1.276A B B A A Issued Date Compal Electronics. Date: 5 4 3 2 Rev 1.5m ohm.2uH Ipeak=1.35VSP PGOOD 1 2 2 1 TRIP_+1. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.4) =1. INC. L=2.388+0.148A Rcs=20Kohm .7V PC62 4.0 Thor Sheet Wednesday.2)+(1/(2*2. Inc.2u*290K)*((8.704V Vo=VFB*(1+PR100/PR101)= 1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0603_25V7K 1 2 PC61 4.5VM_R35 2 PC67 680P_0402_50V7K 2 Rds=13.35VSP 1 RF_+1.35/8.35VSP VDD_1V35_DDR3_MEM 1 + PR98 4.2)+(1/(2*2.35VSP EN 10 9 2 4 DRVH 1 3 FB_+1.136+0.024 A Iocp_max= 180m/(8*13.64A Imax= 1.35/8.5V D 1 JUMP_43X79 5 PR94 0_0402_5% 2 1 VFB= 0.5mΩ(Typ) 16.18V Iocp=Vtrip/(8*Rds(on))*(1/(2*L*f)*((Vin-Vo)*Vo/Vin) Iocp_min= 180m/(8*16.5 4 3 2 1 1 +3VALW PR93 10K_0402_5% PJ3 1 2 +1.5mΩ(Max) C C PR100 9. Ics=9uA Vtrip=Rcs*Ics=20K*9u=0.2u*290K)*((8.5m*1. 2012 1 30 of 35 . 290KHz(typ) 2 PR101 10K_0402_1% Rds(on)=13.35)*1.35VSP 6 11 LG_+1.35)*1.1U_0402_25V6 2 1 PQ24 SIS412DN-T1-GE3_POWERPAK8-5 PGOOD_1.4-1.888=2.888=2.7U_0805_25V6-K 2 1 4 PR95 0_0603_5% 1 2 PC60 2200P_0402_50V7K 2 1 PC59 0.35V Freq= 266~314KHz .7U_0805_25V6-K 2 1 PL6 2.35VSP VBST TRIP D 5 EN_+1. 16m ohm .7_1206_5% 4 PC65 1U_0402_10V6K PQ25 SI7716ADN-T1-GE3_POWERPAK8-5 3 2 1 PC66 220U_B2_2.2UH_MMD-06AH-2R2M-X2A_6A_20% 1 2 +5VS 7 TPS51212DSCR_SON10_3X3 2 PR99 470K_0402_1% BST_+1. June 13.

Date: 5 4 3 2 PMU part1 Document Number Rev 1.33) L4 EN_DDR_BUCK K5 (30) EN_5V0_SYS L2 EN_VDD_SOC (33) G3 EN_3V3_SW (23) INT1 PR213 1 1 M6 1 10K_0402_5% 2 2 PR105 1 1 VDD_1V8_GEN PR104 2 PR136 EN1 @ PR143 1 M7 2 (7) CPU_PWR_REQ PR110 2 0_0402_5% PMU_OSC32KIN 1 2 F8 2 1 OSC32KIN SDA 2 PR106 SCL PC69 22P_0402_50V8J M5 1 M4 0_0402_5% PC68 22P_0402_50V8J 2 1 0_0402_5% 2 100K_0402_1% 2 1 D @ PR109 100K_0402_1% 1 PR103 PMU_OSC32KIN (7) 100K_0402_1% PR102 PMU_OSC32KOUT (7) PMU_OSC32KOUT 100K_0402_1% (16.17.4.33. c.0 Thor Wednesday.1U_0402_25V6 G7 TESTV AGND1 AGND2 AGND3 AGND4 AGND5 AGND6 AGND7 AGND8 AGND9 AGND10 AGND11 AGND21 AGND22 DGND1 DGND2 DGND3 2 TPS6591104A2ZRCR_BGA98 PR141 @ 442K_0402_1% A 1 A Issued Date Compal Electronics.29.3V6K 2 2 @ PR117 0_0402_5% @ PR146 100K_0402_1% PC72 4.7) CORE_PWR_REQ 1 2 0_0402_5% F1 SLEEP 2 GPIO2 GPIO6 L3 (7) PMU_INT# @ VDD_1V8_GEN GPIO1 2 POWERHOLD 0_0402_5% PR112 1 (7) AP_OVERHEAT# 0_0402_5% 2 N1 N2 D L5 EN_3V_5V_SYS (28.3V6M (22) ONKEY# 2 PR115 1 2 0_0402_5% PMU_ONKEY# E4 PWRON 2 PR116 1 1 1 VDD_1V8_PMU_VRTC VRTC PMU_VCCS E8 BOOT1 2 1 REFGND B8 D6 E6 E5 F5 G4 H6 J3 J4 J6 K3 H5 2 PR134 @ 1 2 412K_0402_1% 1 PMU_VCCS M8 N8 D A1 B1 B2 @ 3 2N7002KW_SOT323-3 S B 0.2U_0402_6. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.33.17.7U_0402_6. Compal Secret Data Security Classification 2011/06/20 Deciphered Date 2012/06/20 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.29.05A 1 1 J5 10MIL G8 2 PMU_BOOT1 B+ 1 VDD_0V85_PMU_VREF 0. INC.3V6M 1. b. d. INC. e.85V 1 = EEPROM @ PR139 0_0402_5% PQ12 PC74 2.8V 0_0402_5% PC75 0. 2012 1 Sheet 31 of 35 . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.3V6K GPIO4 GPIO5 VDDIO N7 2 1 VDD_5V0_SBY VDD_5V0_SBY B6 1 VCC7 PC71 4.5 4 3 2 1 a. June 13. PMU-TPS65911 1/3 GP0: GP2: GP6: GP7: GP8: EN_5V_CP Follow ACER circuit 6/22 EN_SOC EN_3V3_SYS EN_DDR (Optional on Cardhu S since we are using VDD2 for memory) EN_5V0 Compal P/N: SA000056800 S IC TPS6591104A2ZRCR BGA 98P PMU +3VALW PU6A VDD_1V8_GEN EN2 GPIO0 GPIO7 1 PR107 10K_0402_5% GPIO8 PR108 (6. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.4. INC.7) PWR_I2C_SDA F7 100K_0402_1% OSC32KOUT GPIO3 PWRHOLD CLK32KOUT F6 B7 TP3 PAD F4 PR111 33_0402_1% 1 2 H4 PR113 0_0402_5% 1 2 PMU_CLK_32K (7) PWRDN TP4 PAD HDRST (22) HDRST L6 HDRST NRESPWRON NRESPWRON2 PMU_RESET_OUT_1V8# (7) C7 1 TP5 PAD 2 VDD_1V8_GEN C C @ PR114 D7 PMU_VBACKUP 1 VBACKUP 100K_0402_5% 0_0402_5% 2 H7 PR138 1 0_0402_5% 2 G6 2 VDD_1V8_GEN PR137 1 PC70 1U_0402_6.7) PWR_I2C_SCL (16.05A 10MIL B5 VCCS 2 2 PR118 0_0402_5% B 2 VDD_1V8_PMU_VRTC 1 PC73 1U_0402_6. Inc.7U_0402_6.3V6M 0 = Hardcode VREF G Always on 0.

2A LDO3 VDD_PMU_LDO3 C8 VDD_PMU_LDO4 VDD_PMU_LDO3 30MIL VDD_PMU_LDO4 20MIL 1 PC79 4.7U_0402_6. 2012 1 Sheet 32 of 35 .3V6M PC81 2.7uF cap according to TI on July 6th PMU-TPS65911 2/3 Compal P/N: SA000056800 S IC TPS6591104A2ZRCR BGA 98P PMU D D PU6B 1. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.2U_0402_6. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.0V 0.1A 0.02A VDD_PMU_LDO7 VDD_PMU_LDO8 B 10MIL 2 PC85 2.3V6M M2 PC86 2.2U_0402_6. Compal Secret Data Security Classification 2011/06/20 Deciphered Date 2012/06/20 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. INC.2V 0.7U_0402_6.3V6M 2 2 0.7U_0402_6.2V 0.7U_0402_6.3V6M 2 LDO6 1 VCC3 2 N3 VDD_1V8_GEN B 1.2U_0402_6.5 4 3 2 1 Note: LDO1 & LDO2 need 4.2A 1 1 5V 20MIL K1 PC83 2.7U_0402_6.2U_0402_6. INC. Inc.7U_0402_6. June 13.3V6M TPS6591104A2ZRCR_BGA98 A A Issued Date Compal Electronics.2A VDD_PMU_LDO1 LDO1 N6 VDD_PMU_LDO1 N4 VDD_PMU_LDO2 VDD_PMU_LDO2 30MIL 1 PC76 4.2V 1.3V PR119 0_0402_5% 30MIL L1 +5VS VCC4 LDO5 1 0.2V 1. Date: 5 4 3 2 PMU part2 Document Number Rev 1.3V6M 2 N5 VDD_1V8_GEN 1.2U_0402_6.2U_0402_6. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.1A M3 VDD_PMU_LDO7 M1 VDD_PMU_LDO8 0.5A 0.2V 0.3V6M 1.3V6M PC78 4.3V6M 2 D8 +3VALW C C 3.3V6M 1 LDO8 VDD_PMU_LDO6 1 2 1 LDO7 PC84 4.0 Thor Wednesday.05V 1. INC.2A VDD_PMU_LDO5 2 PC82 4.3V6M 2 2 1 LDO4 E7 1 VCC5 PC80 2.05A VDD_PMU_LDO6 10MIL PC87 2.3V6M 2 2 1 LDO2 1 VCC6 PC77 4.

3V6M 2 1 PC91 22U_0603_6.1U_0402_25V6 PC106 10U_0805_25V6K VBST PC105 10U_0805_25V6K 2 1 2 PC102 V5IN PC104 0.31.75A_20% B3 B4 EN VDD SDA SCL SENSE+ SENSE - VSEL0 VSEL1 AGND PGND PGND PGND B1 VDD_CORE_SENSE (8) C1 GND_CORE_SENSE (8) 1 2 D Close to CPU D4 C3 C4 Ipeak =2.1U_0402_25V6 A3 2 PR125 DRVH 1 PC107 0.2UH_PCMB041B-2R2MS_2.3 2 1 +3VALW 2 2 1 VDD_1V8_GEN @ PR135 100K_0402_5% PC89 0. Inc.9K_0402_1% +3VALW SWIO2 K8 PMU_SWIO 1 2.3V6M G2 PC95 PR120 100K_0402_5% 2 1 (28.1U_0402_25V6 SWIO1 VCCIO2 PC113 10U_0603_6.2UH_VLS252012T-2R2M1R3_1.8V GNDIO2 J7 1 2 GNDIO1 PR128 0_0402_5% J8 1 2 PC114 0.29.7) 1 2 1 2 D4 1 G1 PL7 VIN AVIN @ PR131 100K_0402_5% J2 2 2 1 PC98 0. Compal Secret Data Security Classification TPS6591104A2ZRCR_BGA98 2011/06/20 Deciphered Date 2012/06/20 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.31. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_25V6 1 2 PC103 1U_0402_16V6K A5 1 PMU_PGOOD PAD @ PR130 1 100_0402_1% 2 VDD_CPU_SENSE (8) 0_0402_5% 2 GND_CPU_SENSE (8) TP8 D5 C6 B3 1 PMU_TRIP 2 PR127 90.8A(60us) sustained TPS62361YZHR_XBGA16 TPS62361B TPS62361YZHR_XBGA16 @ 2.3V6M L8 1 2A A 50OHM_NETCLASS1 VFBIO H8 Issued Date Compal Electronics.1U_0402_25V6 PC216 2 2 @ PR126 0_0402_5% 1 1 2 3 1 VDD_1V0_GEN 1 @ PR132 1_0603_5% B VOUT B4 1 C5 PGOOD A7 GNDC1 EN GNDC2 TRAN TRIP C4 + 2 B PR129 1 2 50OHM_NETCLASS1 330P_0402_50V7K A8 1 PMU_VOUT PC110 VFB 1V 8A 200MIL FDMC7200_POWER33-8-10 PQ26 2 PMU_DRVL PL9 2.1U_0402_25V6 1 2 PC96 10U_0603_6.8A_20% PL10 2 50MIL VDD_1V8_GEN K7 1.3V6M 1 1 (28.1U_0402_25V6 2 0.2V H1 50MIL VDD_1V2_MEM 2A 1.1U_0402_25V6 1 2 PC97 10U_0603_6. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.2UH_VLS252012T-2R2M1R3_1.17.29.5A( 6us) Imax = 1.4. 2012 1 Sheet 33 of 35 .7) PR123 0_0402_5% C2 A3 1 A2 SW SW 1 2 TPS62361_SW 2.4.3V6M E1 1 2 1 PC99 0.1U_0402_25V6 PC93 2 1 PC88 10U_0603_6.8A_20% PL8 1 2 50MIL H2 1. June 13. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION.1U_0402_25V6 2 VCCA1 GNDSWA1 GNDSWA2 GNDSWA3 VFB1 C2 C1 D3 VCCBB1 SWB1 VCCB2 SWB2 GNDSWB2 C VFB2 D2 D3 PWR_I2C_SCL (16.0 Thor Wednesday.1U_0402_25V6 1 2 A PC111 10U_0603_6.2V @ PR124 0_0402_5% GNDSWB1 PR122 0_0402_5% PWR_I2C_SDA (16. INC.17.1A 1 G2 Change C_B3 footprint PMU_DRVL 0.1A Tj<70 degree ==>5.3V6M 2 1 5 C VL B+ 2 PMU_DRVH_R PMU_DRVH_R 2 Tj<90 degree ==>6. Date: 5 4 3 2 PMU part3 Document Number Rev 1.31.33) EN_3V_5V_SYS +3VALW 30MIL 2 +3VALW VCCA3 J1 50OHM_NETCLASS1 K2 PMU_VFB2 A2 PMU_VBST 1 1 2 2A @ PC101 0. INC.2UH_MMD-06AH-2R2M-X2A_6A_20% 2 PMU_SW 1 2 A6 G1 D1 S2 S2 7 @ DRVL 9 D2/S1 6 S2 D1 8 10 PMU_SW 5 A4 PC115 1000P_0603_50V7 1 2 1 SW D1 D1 4 0_0402_5% PC109 330U_B2_2VM_R15M 1 PMU_DRVH PC108 0.3V6M 1 PMU-TPS65911 3/3 Compal P/N: SA000056800 S IC TPS6591104A2ZRCR BGA 98P PMU FOR VDD_1V2_CORE_TEGRA 22U_0603_6. INC.3V6M 20MIL 2 +3VALW D VDD_1V2_SOC PU7 @ PR121 22U_0603_6.1U_0402_25V6 A4 A1 2 2 100K_0402_5% B2 (31) EN_VDD_SOC PU6C F3 SWA1 SWA2 SWA3 VCCA2 1 0.31.33) EN_3V_5V_SYS PC92 0.3V6M VCCIO1 1 L7 2 2 PC112 0.3V6M PC94 2 1 4 PC90 22U_0603_6.1U_0402_25V6 F2 D1 VDD_1V8_GEN D2 D1 E2 @ PC100 10U_0603_6.

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