CALIFORNIA STATE POLYTECHNIC UNIVERSITY, POMONA

ECE205
GRADING:
Quizzes and Assignments: 25%
Midterm1: 25%
Midterm2: 25%
Final: 25%

Toma SACCO, Ph.D.

Room 515
telephone#: 9098692527
email: thsacco@csupomona.edu

COURSE TOPICS:
1. Verilog Modeling of Sequential Circuits
a. Structural models
b. Data flow models

c. Behavioral models
d. Test bench

e. Simulation
2. Storage Devices
a. Latches, Master/Slave and Edge Triggered Flip-Flops
b. Timing diagrams and setup and hold times
c. Metastability
3. Flip-flop characteristic equations and excitation tables
4. FPGA Architecture
a. CLB (configurable logic block), I/O Blocks
b. Mapping A Digital Design To FPGA
5. Registers and Counters
a. General Purpose Shift Registers
b. Binary up/down counters
6. Design Of Finite State Machines
a. State Diagrams
b. Next State Tables
c. Timing Diagrams
d. State assignment including one-hot state assignment
7. ASM Chart
a. Data path
b. Control design
c. Register transfer operation

d. System Design

TEXTBOOK:
Brown and Vranesic, Fundamentals of Digital Logic with Verilog Design, 2003, Mc/Graw Hill.

Toma Sacco, Ph.D.