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MAHA BARATHI ENGINEERING COLLEGE

CHINNASALEM

DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
EC6612-VLSI DESIGN
LAB MANUAL

EC6612 VLSI DESIGN LAB
1.

HDL based design entry and simulation of simple counters, state machines, adders
(min 8 bit) and multipliers (4 bit min).

2.

Synthesis, P&R and post P&R simulation of the components simulated in (I) above.
Critical paths and static timing analysis results to be identified. Identify and verify
possible conditions under which the blocks will fail to work correctly.

3.

Hardware fusing and testing of each of the blocks simulated in (I). Use of either

chipscope feature (Xilinx) or the signal tap feature (Altera) is a must. Invoke the PLL
and demonstrate the use of the PLL module for clock generation in FPGAs.
4. Design and simulation of a simple 5 transistor differential amplifier. Measure gain,
ICMR, and CMRR.
5. Layout generation, parasitic extraction and resimulation of the circuit designed in (I)
6. Synthesis and Standard cell based design of an circuits simulated in 1(I) above.
Identification of critical paths, power consumption.
7. For expt (c) above, P&R, power and clock routing, and post P&R simulation.
8.

Analysis of results of static timing analysis.

COMBINATIONAL CIRCUIT DESIGN
STUDY EXPERIMENTS
BASIC LOGIC GATES
AIM:
To study and synthesis of basic logic gates in Verilog HDL using Xilinx tools
APPARATUS REQUIRED:


PC with Windows XP.
XILINX software.

Theory:
A logic gate is a physical model of a boolean function that is, it performs a logical operation on
one or more logic inputs and produces a single logic output. Logic gates are primarily
implemented electronically using diodes or transistors, but can also be constructed using
electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even
mechanical elements.With amplification, logic gates can be cascaded in the same way that
Boolean functions can be composed, allowing the construction of a physical model of all of
Boolean logic, and therefore, all of the algorithms and mathematics that can be described with
Boolean logic Synthesis is the process of constructing a gate level netlist from a register-transfer
Level models of the circuit described in Verilog HDL ,VHDL or mixed language designs.

PROCEDURE:
1. Start the Xilinx ISE by using start→ program file → Xilinx ISE (8.1i) → Project navigator
2. File → New Project
3. Enter the project name and location then click next
4. select the Device and other category and click next twice and finish
5. Click on the symbol of FPGA device and then right click → click on new source
6. Select the Verilog Module and give the file name → click next and define ports → click
next and finish
7. Writing the behavioral verilog code in verilog Editor
8. Run the Check syntax → process window → synthesize → double click check syntax and
remove errors, if present , with proper syntax & coding.
9. synthesis your design, from the source window select, Synthesis/Implementation from the
window Now double click the synthesis →XSt
10. After the HDL synthesiss phase of the synthesis process,you can display a schematic
representation of your synthesized source file.This schematic shows a representation of the
pre-optimized design in terms of generic symbols,such as adders,multipliers,counters,Ann
gates and OR gates → double click View RTL schematic
11. Double click the schematic to internal view
12. Double click outside the schematic to move one-level back

and (out. input i1. input i2.carry logic.you can view number of Slices.13.i1.Double click the Schematic to inner view 15.I/Os are taken by your design in Device using Design Summary AND Gate: PROGRAM: AND Gate: module Andgate(i1.I/O buffers and other technology-specific components →Double click View technology Schematic 14. i2. This Schematic Shows a representation of the design in terms of logic elements optimized to the target device.Double click the LUT to inner View.This is gate lenel view of LUT . For example. out). output out.in terms of LUTs(Look Up Table).After finishing the synthesis.if you want see Truth Table and K-Map for your design just click the respective tabs 16.LUT(Look Up Table). endmodule Truth table: AND Gate -----------------------------------------------Input1 Input2 Output .i2).

-----------------------------------------------0 0 0 0 1 0 1 0 0 1 1 1 ------------------------------------------------- OUTPUT WAVE OR Gate: Program: module Orgate(i1. out). . i2. input i1.

output out.i1. endmodule Truth table: OR Gate -----------------------------------------------Input1 Input2 Output -----------------------------------------------0 0 0 0 1 1 1 0 1 1 1 1 ------------------------------------------------ Output Wave .i2). or(out.input i2.

i2). i2. endmodule .NAND Gate: Program module Nandgate(i1. output out. out). input i1.i1. nand(out. input i2.

Truth table: NAND Gate -----------------------------------------------Input1 Input2 Output -----------------------------------------------0 0 1 0 1 1 1 0 1 1 1 0 ------------------------------------------------ Output Wave: NOR Gate: .

nor(out. input i2.i1.Program module Norgate(i1. i2. out). input i1. output out.i2). endmodule Truth table: NOR Gate -----------------------------------------------Input1 Input2 Output -----------------------------------------------0 0 1 0 1 0 1 0 0 1 1 0 ------------------------------------------------ .

endmodule Truth table: . out).i1. xor(out. output out. input i2. i2.i2). input i1.Output wave XOR Gate: Program module Xorgate(i1.

. input i2.XOR Gate -----------------------------------------------Input1 Input2 Output -----------------------------------------------0 0 0 0 1 1 1 0 1 1 1 0 ------------------------------------------------Output Wave XNOR Gate: Program module Xnorgate(i1. output out. i2. input i1. out).

endmodule Truth table: XNOR Gate -----------------------------------------------Input1 Input2 Output -----------------------------------------------0 0 1 0 1 0 1 0 0 1 1 1 ------------------------------------------------ Output Wave: Not Gate: .i2).i1.xnor(out.

out). output out. endmodule Truth table: NOT Gate --------------------------Input Output --------------------------0 1 1 0 --------------------------- . input in.in). not(out.Program module Notgate(in.

Output Wave Buffer: Program module Buffer(in. output out. buf(out. endmodule Truth table : . input in.in). out).

BUFFER --------------------------Input Output --------------------------0 0 1 1 --------------------------Output Wave: RESULT: HALF ADDER AND FULL ADDER .

and Cin. incorporates an XOR gate for S and an AND gate for C. 3. often written as A. 2. A full adder adds binary numbers and accounts for values carried in as well as out. Utilization of LUTs & Slices I/O Buffers assignment RTL schematic in gate level Time delay between i/Os and path. It has two outputs. given their incapacity for a carry-in bit.AIM: To study and synthesis of half adder and full adder circuits in Verilog HDL using Xilinx tools. The simplest half-adder design. 4. pictured on the right. S and C (the value theoretically carried on to the next addition). PROCEDURE: . The circuit produces a two-bit output sum typically represented by the signals Cout and S. Theory: A half adder adds two one-bit binary numbers A and B. . Synthesis is the process of constructing a gate level netlist from a register-transfer Level models of the circuit described in Verilog HDL . XILINX SYNTHESIS TOOL enable us to study 1.VHDL or mixed language designs. A and B are the operands.The netlist files contain both logical design data and constraints . and Cin is a bit carried in (in theory from a past addition). B. APPARATUS REQUIRED:   PC with Windows XP XILINX. A one-bit full adder adds three one-bit numbers. Half adders cannot be used compositely. the final sum is 2C + S.

14. Click on the symbol of FPGA device and then right click → click on new source 6.you can display a schematic representation of your synthesized source file.I/Os are taken by your design in Device using Design Summary . Double click the schematic to internal view 12.Synthesis/Implementation from the window Now double click the synthesis →XSt 10.carry logic. Run the Check syntax → process window → synthesize → double click check syntax and remove errors.This schematic shows a representation of the pre-optimized design in terms of generic symbols.Ann gates and OR gates → double click View RTL schematic 11.This is gate lenel view of LUT . select the Device and other category and click next twice and finish 5.in terms of LUTs(Look Up Table).such as adders. 15. Double click outside the schematic to move one-level back 13.LUT(Look Up Table). 9. This Schematic Shows a representation of the design in terms of logic elements optimized to the target device.if you want see Truth Table and K-Map for your design just click the respective tabs 17.I/O buffers and other technology-specific components 14. After the HDL synthesiss phase of the synthesis process. Select the Verilog Module and give the file name → click next and define ports → click next and finish 7. Writing the behavioral verilog code in verilog Editor 8. Start the Xilinx ISE by using start→ program file → Xilinx ISE (8.Double click the LUT to inner View.1i) → Project navigator 2. from the source window select. with proper syntax & coding.multipliers.you can view number of Slices.Double click the Schematic to inner view 16.After finishing the synthesis. if present .1. 16. For example. Enter the project name and location then click next 4. synthesis your design.counters. File → New Project 3. →Double click View technology Schematic 15.

input i2. endmodule truth table: .i2). i2).i1.Half Adder: Program : module HalfAddr(sum. input i1.i2). and(c_out. output c_out. xor(sum. output sum. i1. c_out.i1.

Half Adder -----------------------------------------------------------------Input1 Input2 Carry Sum -----------------------------------------------------------------0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 ------------------------------------------------------------------ Output Wave: Full Adder: .

output c_out. endmodule Truth Table: .c_in).i2).c2).c1. or n5(c_out. and n4(c2. i2. sum).s1.s1. input i1. input i2. c_out. output sum.i1. and n2(c1. c_in.i1. xor n1(s1.Program: module FullAddr(i1. xor n3(sum. input c_in.c2.c1.i2). wire s1.c_in).

Full Adder -----------------------------------------------------------------------------------------------i1 i2 C_in C_out Sum -----------------------------------------------------------------------------------------------0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 ------------------------------------------------------------------------------------------------Output Wave: Result: HALF SUBTRACTOR & FULL SUBTRACTOR .

Easy way to write truth table D=X-Y-Z (don't bother about sign) Synthesis is the process of constructing a gate level netlist from a register-transfer Level models of the circuit described in Verilog HDL . It has three inputs. XILINX SYNTHESIS TOOL enable us to study 1. Utilization of LUTs & Slices I/O Buffers assignment RTL schematic in gate level Time delay between i/Os and path .AIM: To study and synthesis of half subtractor and full subtractor circuits in Verilog HDL using Xilinx tools. The netlist files contain both logical design data and constraints . .VHDL or mixed language designs.The Full_subtractor is a combinational circuit which is used to perform subtraction of three bits. It has two inputs. XILINX software. X (minuend) and Y (subtrahend) and Z (subtrahend) and two outputs D (difference) and B (borrow). 4. 2. APPARATUS REQUIRED:   PC with Windows XP. X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). 3. Theory: The half-subtractor is a combinational circuit which is used to perform subtraction of two bits.

Ann gates and OR gates → double click View RTL schematic 11.you can view number of Slices.carry logic. After the HDL synthesiss phase of the synthesis process.1i) → Project navigator 2. File → New Project 3. if present . Start the Xilinx ISE by using start→ program file → Xilinx ISE (8.PROCEDURE: 1. →Double click View technology Schematic 15. Select the Verilog Module and give the file name → click next and define ports → click next and finish 7. Double click the LUT to inner View.you can display a schematic representation of your synthesized source file.Synthesis/Implementation from the window Now double click the synthesis →XSt 10.counters. Run the Check syntax → process window → synthesize → double click check syntax and remove errors. Writing the behavioral verilog code in verilog Editor 8.multipliers.I/Os are taken by your design in Device using Design Summary .This schematic shows a representation of the pre-optimized design in terms of generic symbols.if you want see Truth Table and K-Map for your design just click the respective tabs 17.in terms of LUTs(Look Up Table). with proper syntax & coding. Double click the Schematic to inner view 16. Double click the schematic to internal view 12.such as adders.This is gate lenel view of LUT . After finishing the synthesis. from the source window select. For example.LUT(Look Up Table). Click on the symbol of FPGA device and then right click → click on new source 6. Enter the project name and location then click next 4. 9. This Schematic Shows a representation of the design in terms of logic elements optimized to the target device. synthesis your design. select the Device and other category and click next twice and finish 5. Double click outside the schematic to move one-level back 13.I/O buffers and other technology-specific components 14.

i1).i1). xor(dif. output bor. not(i0n. output dif.i0).Halfsubtractor: Program: module HalfSub(i0. endmodule Truth Table: Half Subtractor . and(bor. dif). bor.i0. wire i0n. input i1. input i0. i1.i0n.

-----------------------------------------------------------------------Input1 Input2 Borrow Difference ------------------------------------------------------------------------0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 ------------------------------------------------------------------------ Output Wave: .

dif}=i0-i1-b_in. dif).FULL SUBTRACTOR: Program: module FullSub(b_in. b_out. input i0. i0. input b_in. endmodule Truth Table: Full Subtractor . assign {b_out. output dif. i1. input i1. output b_out.

No: 1(A) Date : .-----------------------------------------------------------------------------------------------A B C Difference bout -----------------------------------------------------------------------------------------------0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 ------------------------------------------------------------------------------------------------Output Wave: Result: DESIGN AND SIMULATION OF 8-BIT ADDER Expt.

such as Binary-coded decimal or excess-3. In modern computers adders reside in the arithmetic logic unit (ALU) where other operations are performed. 3. Although adders can be constructed for many numerical representations. 2. it is trivial to modify an adder into an adder-subtractor. Theory: In electronics. The netlist files contain both logical design data and constraints .VHDL or mixed language designs. Synthesis is the process of constructing a gate level netlist from a register-transfer Level models of the circuit described in Verilog HDL . Other signed number representations require a more complex adder. an adder or summer is a digital circuit that performs addition of numbers. APPARATUS REQUIRED:   PC with Windows XP XILINX. 4. . XILINX SYNTHESIS TOOL enable us to study 1.1i) → Project navigator . Start the Xilinx ISE by using start→ program file → Xilinx ISE (8. the most common adders operate on binary numbers.AIM: To design an unsigned 8-bit adder in behavioral modeling of Verilog HDL using Xilinx tools. In cases where two's complement or one's complement is being used to represent negative numbers. Utilization of LUTs & Slices I/O Buffers assignment RTL schematic in gate level Time delay between i/Os and path PROCEDURE: 1.

Double click the Schematic to inner view 16. in terms of LUTs(Look Up Table). File → New Project 3.Ann gates and OR gates → double click View RTL schematic 11. Double click the LUT to inner View. I/O buffers and other technology-specific components 14. from the source window select. synthesis your design.such as adders.you can display a schematic representation of your synthesized source file.counters. Writing the behavioral verilog code in verilog Editor 8. This is gate lenel view of LUT .I/Os are taken by your design in Device using Design Summary RTL-SCHEMATIC . →Double click View technology Schematic 15. Enter the project name and location then click next 4.multipliers.if you want see Truth Table and K-Map for your design just click the respective tabs 17. with proper syntax & coding.LUT(Look Up Table). Select the Verilog Module and give the file name → click next and define ports → click next and finish 7. For example. After the HDL synthesiss phase of the synthesis process. if present . Run the Check syntax → process window → synthesize → double click check syntax and remove errors.you can view number of Slices. Click on the symbol of FPGA device and then right click → click on new source 6. This Schematic Shows a representation of the design in terms of logic elements optimized to the target device. 9.Synthesis/Implementation from the window Now double click the synthesis →XSt 10. select the Device and other category and click next twice and finish 5.This schematic shows a representation of the pre-optimized design in terms of generic symbols. Double click outside the schematic to move one-level back 13.carry logic.2. Double click the schematic to internal view 12. After finishing the synthesis.

ci. output [7:0] sum. b. assign sum = tmp [7:0].program module adder(a. assign tmp = a + b + ci. sum. assign co = tmp [8]. input [7:0] a. input [7:0] b. wire [8:0] tmp. output co. endmodule . co). input ci.

No:1(B) Date : AIM: To design of unsigned 4-bit multiplier in Verilog HDL usins Xilinx tools APPARATUS REQUIRED: .. Expt.Output Wave: Result: DESIGN OF UNSIGNED 4-BIT MULTIPLIER.

it is possible to construct a 4x4 combinational multiplier from an array of AND gates. taking what you have learned recently and extending it to a more complex circuit. 4. Theory: A combinational multiplier is a good example of how simple logic functions (gates.  PC with Windows XP XILINX. can be realized using simple logic building blocks.VHDL or mixed language designs. The netlist files contain both logical design data and constraints . Enter the project name and location then click next 4. Utilization of LUTs & Slices I/O Buffers assignment RTL schematic in gate level Time delay between i/Os and path PROCEDURE: 1. File → New Project 3. such as binary multiplication. XILINX SYNTHESIS TOOL enable us to study 1. Synthesis is the process of constructing a gate level netlist from a register-transfer Level models of the circuit described in Verilog HDL . 2. half adders and full adders) can be combined to construct a much more complex function. Start the Xilinx ISE by using start→ program file → Xilinx ISE (8. . In particular. half-adders and full-adders. The purpose of this document is to introduce how a relatively complex arithmetic function. Click on the symbol of FPGA device and then right click → click on new source . select the Device and other category and click next twice and finish 5.1i) → Project navigator 2. 3.

from the source window select.Ann gates and OR gates → double click View RTL schematic 11. Writing the behavioral verilog code in verilog Editor 8. Run the Check syntax → process window → synthesize → double click check syntax and remove errors. if present. →Double click View technology Schematic 15. with proper syntax & coding. After finishing the synthesis. Double click the LUT to inner View. For example.I/Os are taken by your design in Device using Design Summary RTL –SCHEMATIC . This schematic shows a representation of the pre-optimized design in terms of generic symbols.counters.LUT(Look Up Table). Select the Verilog Module and give the file name → click next and define ports → click next and finish 7.I/O buffers and other technology-specific components 14.carry logic. you can view number of Slices.6. such as adders. After the HDL synthesis phase of the synthesis process.if you want see Truth Table and K-Map for your design just click the respective tabs 17. 9. Synthesis/Implementation from the window Now double click the synthesis →XSt 10.multipliers. Double click outside the schematic to move one-level back 13. you can display a schematic representation of your synthesized source file. This is gate lenel view of LUT . Double click the Schematic to inner view 16. This Schematic Shows a representation of the design in terms of logic elements optimized to the target device. Double click the schematic to internal view 12.in terms of LUTs(Look Up Table). synthesis your design.

output [7:0] res. input [3:0] b. res). always @(a or b ) begin res=a * b. end endmodule OUTPUT WAVEFORM .PROGRAM: module fg(a. b. reg [7:0] res. input [3:0] a.

Result: DESIGN OF 4-BIT COUNTER Expt No:1(C) Date: AIM: .

Click on the symbol of FPGA device and then right click → click on new source 6. 9. the counter increments its value. Writing the behavioral verilog code in verilog Editor 8.Ann gates and OR gates → double click View RTL schematic . After the HDL synthesiss phase of the synthesis process. if present . the counter decrements the count. 3. with proper syntax & coding. Run the Check syntax → process window → synthesize → double click check syntax and remove errors. Start the Xilinx ISE by using start→ program file → Xilinx ISE (8. XILINX SYNTHESIS TOOL enable us to study 1. Select the Verilog Module and give the file name → click next and define ports → click next and finish 7.such as adders.This schematic shows a representation of the pre-optimized design in terms of generic symbols. under the control of an up/down selector input. 4. is known as an up/down counter. Utilization of LUTs & Slices I/O Buffers assignment RTL schematic in gate level Time delay between i/Os and path PROCEDURE: 1. 2. from the source window select.counters. File → New Project 3.multipliers.1i) → Project navigator 2.Synthesis/Implementation from the window Now double click the synthesis →XSt 10. The netlist files contain both logical design data and constraints . Enter the project name and location then click next 4.To design of 4-Bit Counter in Verilog HDL using Xilinx tools. When the selector is in the up state.VHDL or mixed language designs. Theory: A counter that can change state in either direction. When the selector is in the down state. select the Device and other category and click next twice and finish 5. Synthesis is the process of constructing a gate level netlist from a register-transfer Level models of the circuit described in Verilog HDL .you can display a schematic representation of your synthesized source file. synthesis your design.

Double click the LUT to inner View. reg [3:0] tmp. q).you can view number of Slices. This Schematic Shows a representation of the design in terms of logic elements optimized to the target device.in terms of LUTs(Look Up Table).I/Os are taken by your design in Device using Design Summary RTL-SCHEMATIC PROGRAM module counter (clk.carry logic. →Double click View technology Schematic 15. For example. output [3:0] q. s.11.This is gate lenel view of LUT . After finishing the synthesis. else tmp <= tmp . always @(posedge clk) begin if (s) tmp <= 4’b1111.LUT(Look Up Table). Double click outside the schematic to move one-level back 13. . Double click the Schematic to inner view 16.if you want see Truth Table and K-Map for your design just click the respective tabs 17.1’b1. input clk.I/O buffers and other technology-specific components 14. Double click the schematic to internal view 12. s.

VHDL or mixed language designs. Utilization of LUTs & Slices . When the selector is in the down state. the counter increments its value.end assign q = tmp. is known as an up/down counter. The netlist files contain both logical design data and constraints . endmodule Output Wave Result: DESIGN OF STATE MACHINE Expt No:1(D) Date: AIM: To design of State Machine in Verilog HDL using Xilinx tools. under the control of an up/down selector input. the counter decrements the count. XILINX SYNTHESIS TOOL enable us to study 5. Theory: A counter that can change state in either direction. When the selector is in the up state. Synthesis is the process of constructing a gate level netlist from a register-transfer Level models of the circuit described in Verilog HDL .

26. Select the Verilog Module and give the file name → click next and define ports → click next and finish 24. Time delay between i/Os and path PROCEDURE: 18. select the Device and other category and click next twice and finish 22.multipliers. if present . from the source window select.I/O buffers and other technology-specific components 31. RTL schematic in gate level 8. This Schematic Shows a representation of the design in terms of logic elements optimized to the target device. I/O Buffers assignment 7. Start the Xilinx ISE by using start→ program file → Xilinx ISE (8.Ann gates and OR gates → double click View RTL schematic 28. Click on the symbol of FPGA device and then right click → click on new source 23.carry logic.This schematic shows a representation of the pre-optimized design in terms of generic symbols.such as adders. For example.counters.6. synthesis your design. Double click outside the schematic to move one-level back 30. →Double click View technology Schematic 32.Synthesis/Implementation from the window Now double click the synthesis →XSt 27.1i) → Project navigator 19. Enter the project name and location then click next 21. Double click the Schematic to inner view . Double click the schematic to internal view 29.you can display a schematic representation of your synthesized source file.in terms of LUTs(Look Up Table). File → New Project 20. Run the Check syntax → process window → synthesize → double click check syntax and remove errors. Writing the behavioral verilog code in verilog Editor 25. After the HDL synthesiss phase of the synthesis process. with proper syntax & coding.

you can view number of Slices. b: if(x) prestate=c. reg y. input x.clk.y). else prestate=d.if you want see Truth Table and K-Map for your design just click the respective tabs 34. d=2’b11. else case (prestate) a: if(x) prestate=a. c=2’b10. After finishing the synthesis.clk. b:y=1.reset. . Double click the LUT to inner View. endcase always @ (prestate) case (prestate) a:y=0. c:y=1.I/Os are taken by your design in Device using Design Summary Program: module stmach(x. b=2’b01. else prestate=a.reset. else prestate=b. always @ (posdege clk or negedge reset) if(~reset) prestate=a. else prestate=d. output y. parameter a=2’b00.LUT(Look Up Table). c: if(x) prestate=c.33.This is gate lenel view of LUT . reg [1:0]prestate. d: if(x) prestate=d.

endcase endmodule OUTPUT FOR STATE MACHINE .d:y=0.

simulation. XILINX.a technology-mapped netlist is generated . APPARATUS REQUIRED:    PC with Windows XP. place and route results via timing analysis. .usually performed by the FPGA vendor’s proprietary place-and-route software 4. Back annotation is the translation of a routed or fitted design to a timing simulation netlist. the binary file generated is used to (re)configure the FPGA.a hardware description language(HDL)or Schematic design methods are used. To define the behavior of the FPGA. 3. the user will validate the map.Then. The netlist can then be fitted to the actual FPGA architecture using a process called place-and route. and other verification methodologies.. Once the design and validation process is complete.RESELT: SYNTHESIS OF PLACE AND ROUTE Expt No:2 Date: AIM: To Synthesis of Place and Route the Exno1. 2.Common HDLs are VHDL and verilog. Theory: 1.using an electronics design automation (EDA) tool.

1i) → Project navigator 2. Run the Check syntax → process window → synthesize → double click check syntax and remove errors. 7. Select the Verilog Module and give the file name → click next and define ports → click next and finish 7. Then. Afterr Synthesis you assign the Pin Value for your design so. Start the Xilinx ISE by using start→ program file → Xilinx ISE (8.5. In an attempt to reduce the complexity of designing in HDLs. Writing the behavioral verilog code in verilog Editor 8. from the source window select. the process of optimization of logic cells for effective utilization of FPGA area and the speed of operation. 9.Synthesis/Implementation from the window Now double click the synthesis →XST 10. → double click the Assign Package Pins 11. Click on the symbol of FPGA device and then right click → click on new source 6. If you want see your Pin assignment in FPGA zoom in Architecture View or Package View 12. if present . Enter the project name and location then click next 4. synthesis your design. 8. the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. is used to modify and infer the following: 1. Place & Route. Run time minimization PROCEDURE: 1. which have been compared to the equivalent of assembly. 6. Re-assignment of Pins 2. Save file as XST Default click ok and close the window . 9. You see the Pins in FPGA. File → New Project 3. after the synthesis engine has mapped the design to a netlist. 10. Enter the Pin value for your input and output signals. with proper syntax & coding. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist. Initially the RTL description in VHDL or verilog is simulated by creating test benches to simulate the system and observe results. Re-location of slices 3. select the Device and other category and click next twice and finish 5. In a typical design flow. an FPGA application developer will simulate the design at multiple stages throughout the design process.

input [3:0] a. else res = a . b.b. res). Click the pin to see where its placed in FPGA. . And zoom to view how Pins are plaved in FPGA. If you want to change the place of the design. res). input [3:0] b. Just double click View/Edit Routed Design to view interconnection wires and blocks 17. input [7:0] a. you get the all details about your design. click and trace to another slice. output [7:0] res. oper. You see where your IOs are placed in FPGA. After implementation you see Design Summary. input oper. b.13. You can see where your pins are placed. See!!! You changed place and route of the design. Double Click Implementation Design. Design Implementation begins with the mapping or fitting of a logical design file to a specific device and is complete when the physical design is successfully routed and a bit stream is generated. always @(a or b or oper) begin if (oper == 1’b0) res = a + b. 18. reg [7:0] res. And Zoom particular area to see Place and Routing. input [7:0] b. PROGRAM: Adder module addsub(a. end endmodule Multiplier module fg(a. 14. 16. If you want edit the place and route double click View/Edit placed design 15.

end endmodule Placed Design .output [7:0] res. always @(a or b ) begin res=a * b. reg [7:0] res.

Routed Design .

Result IMPLEMENTATION OF COUNTER AND ADDER Expt No:3 .

If you want see your Pin assignment in FPGA zoom in Architecture View or Package View 12. Afterr Synthesis you assign the Pin Value for your design so. Double Click Implementation Design . from the source window select. with proper syntax & coding. select the Device and other category and click next twice and finish 5. Start the Xilinx ISE by using start→ program file → Xilinx ISE (8. Enter the Pin value for your input and output signals.Synthesis/Implementation from the window Now double click the synthesis →XSt 10. Writing the behavioral verilog code in verilog Editor 8. You see the Pins in FPGA. Spartan 3 kit RS 232 PROCEDURE: 1.1i) → Project navigator 2. synthesis your design. → double click the Assign Package Pins 11. Run the Check syntax → process window → synthesize → double click check syntax and remove errors. Click on the symbol of FPGA device and then right click → click on new source 6. Enter the project name and location then click next 4. File → New Project 3. if present . Save file as XST Default click ok and close the window 13. 9. APPARATUS REQUIRED:     PC with Windows XP. Select the Verilog Module and give the file name → click next and define ports → click next and finish 7. Counter and Multiplier in verilog HDL using FPGA board. XILINX.Date: AIM: To Implement the Adder.

co). output [3:0] q. output co. endmodule PROGRAM: ADDER module adder(a. b. 16. 15.14. input [7:0] b. Right click the Generate Programming file→select properties and then select the start-up options→change the clock into JTAG clock. sum. always @(posedge clk) begin if (s) tmp <= 4’b1111. then click apply and ok. PROGRAM:COUNTER module counter (clk. output [7:0] sum. input clk. s. assign co = tmp [8]. end assign q = tmp. reg [3:0] tmp. Double click the Generate Programming file. Right click Xilinx Device→click Program→ok. q).1’b1. input [7:0] a. assign sum = tmp [7:0]. else tmp <= tmp . s. Double click Configure Device→click finish →select the bit file and then click ok 17. endmodule Multiplier . assign tmp = a + b. wire [8:0] tmp.

module fg(a. res). end endmodule . input [3:0] a. input [3:0] b. b. always @(a or b ) begin res=a * b. reg [7:0] res. output [7:0] res.

RESULT: .

the output voltage is low (0 V). SOFTWARE USED Tanner EDA Tools (i) S-Edit (ii) T-Edit (iii) W-Edit DESCRIPTION CMOS INVERTER The NMOS transistor and the PMOS transistor form a typical complementary MOS (CMOS) device. . 2. the top transistor (P-type) is conducting (switch closed) while the bottom transistor behaves like an open circuit. when a high voltage (5 V) is applied at the input. PROCEDURE: 1. the bottom transistor (N-type) is conducting (switch closed) while the top transistor behaves like an open circuit.STUDY EXPERIMENTS CMOS INVERTER OBJECTIVE To design and simulate the Cmos inverter circuits using tanner EDA tool. Open a schematic editor(S-Edit) from the Tanner EDA Tools. Output waveform is viewed in the waveform viewer. Select the required components from the symbol browser and design given circuit using S-Edit. When a low voltage (0 V) is applied at the input. 3. the supply voltage (5 V) appears at the output. Hence. 4. Conversely. Therefore. Write the program in T-Edit and run the simulation to simulate the given program to view the result.

CIRCUIT DIAGRAM: CMOS INVERTER .

PROGRAM
MNMOS_1 Out In Vss 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 Out In Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_2 Vdd Vss DC 5
VVoltageSource_1 In Vss PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(In)
.PRINT TRAN V(Out)
OUTPUTWAVE

RESULT:
The design and simulation of CMOS inverter has been performed using Tanner EDA Tools.

DESIGN AND SIMULATION OF DIFFERENTIAL AMPLIFIER
Expt No:4
Date:
OBJECTIVE

To design and simulate the differential amplifier circuits using tanner EDA tool.
SOFTWARE USED
Tanner EDA Tools
(iv)

S-Edit

(v)

T-Edit

(vi)

W-Edit

THEORY:
Differential amplifier:

Differential Amplifier amplifies the current with very little voltage gain. It consists of two FETs
connected so that the FET sources are connected together. The common source is connected to a
large voltage source through a large resistor Re, forming the "long tail" of the name, the long tail
providing an approximate constant current source. The higher the resistance of the current source
Re, the lower Ac is, and the better the CMRR. In more sophisticated designs, a true (active)
constant current source may be substituted for the long tail. The output from a differential
amplifier is itself often differential.

CIRCUIT DIAGRAM:

DIFFERENTIAL AMPLIFIER:

4. 2.model nmos nmos .model pmos pmos .PROCEDURE: 1. Open a schematic editor(S-Edit) from the Tanner EDA Tools. Write the program in T-Edit and run the simulation to simulate the given program to view the result. 3. Select the required components from the symbol browser and design given circuit using S-Edit. PROGRAM: DIFFERENTIAL AMPLIFIER .print in1 in2 out1 out2 . Output waveform is viewed in the waveform viewer.tran 1m 2m .

.WAVEFORM: DIFFERENTIAL AMPLIFIER: RESULT: The design and simulation of Differential Amplifier has been performed using Tanner EDA Tools.

the supply voltage (5 V) appears at the output. PROCEDURE 1. 2. Select a New file and enter the File type and enter the cell name in the new cell section. the top transistor (P-type) is conducting (switch closed) while the bottom transistor behaves like an open circuit. . Each Layer should be based on the Lambda rules. 4. the bottom transistor (N-type) is conducting (switch closed) while the top transistor behaves like an open circuit. 3. Hence. Therefore. Check for DRC for any error at each level of Layer.LAYOUT DESIGN FOR N-WELL CMOS INVERTER Expt No:5 Date: OBJECTIVE To draw the layout of an n well CMOS inverter using L-Edit of Tanner EDA tools. the output voltage is low (0 V). when a high voltage (5 V) is applied at the input. When a low voltage (0 V) is applied at the input. Open layout Editor (L-Edit) from Tanner EDA tools. SOFTWARE USED Tanner EDA Tools L-Edit DESCRIPTION CMOS INVERTER The NMOS transistor and the PMOS transistor form a typical complementary MOS (CMOS) device. Conversely. Making use of the pallets in L-edit draw the required layers for the Layout. 5.

LAYOUT DIAGRAM STICK DIAGRAM .

RESULT: DESIGN AND IMPLEMENT REDUCING POWER CONSUMPTION .

or a word. APPARATUS REQUIRED: Tanner T-spice v13. SRAM: Static random-access memory (SRAM) is a type of semiconductor memory that uses bi-stable latching circuitry to store each bit.0 PROCEDURE FOR TANNER TOOLS: STEP1: open s-edit window STEP2: go to file. THEORY: MEMORIES: A memory. or a double word. a data byte.Expt No: 6 Date: AIM: To design and implement reducing power consumption in 6T SRAM cell memories using Tanner EDA Tool. but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered. or a quad word may be accessed from or at all addressable locations with a similar process would be used to access from all locations and there is would be equal access time for a read or for a write that is independent of a memory address location.> new design STEP3: go to cell. The power consumption of SRAM varies widely depending on how frequently it is accessed. SRAM exhibits data permanence. such as in applications with moderately clocked microprocessors. draws very little power and can have nearly negligible power .> new view STEP4: add libraries file to the new cell STEP5: instance the devices by using appropriate library files STEP6: save the design & setup the simulation STEP7: run design &observe waveforms STEP8: observe the input & output waveform by given appropriate inputs.> new. Static RAM used at a somewhat slower pace.

W5=0.08 . While DRAM supports access times of about 60 nanoseconds. In addition to such six-transistor (6T) SRAM.36. Each bit in an SRAM is stored on four transistors (M1. both the signal and its inverse are typically provided in order to improve noise margins. Although it is not strictly necessary to have two bit lines. implemented in special processes with an extra layer of polysilicon. the bit lines are actively driven high and low by the inverters in the SRAM cell.36. other kinds of SRAM chips use 4T.5 W1=0. M4) that form two cross-coupled inverters. A typical SRAM cell is made up of six MOSFETs.8 READ OPERATION: Cell Ratio=W1/W5=W2/W6=2. The principal drawback of using 4T SRAM is increased static power due to the constant current flow through one of the pull-down transistors.8um. Two additional access transistors serve to control the access to a storage cell during read and write operations.08. During read accesses. or 2m × n bits.W4=0. SRAM can give access times as low as 10 nanoseconds. control whether the cell should be connected to the bit lines: BL and BL. 10T. W2=2. in turn. This storage cell has two stable states which are used to denote 0 and 1. They are used to transfer data for both read and write operations. 8T.consumption when sitting idle -in the region of a few micro-watts. W6=W3=10. M2. W6=1. or more transistors per bit Fourtransistor SRAM is quite common in stand-alone SRAM devices. M3. Access to the cell is enabled by the word line (WL in figure) which controls the two access transistors M5 and M6 which.7. W3=1. The size of an SRAM with m address lines and n data lines is 2m words. DESIGN SPECIFICATION: L=1.9. allowing for very high-resistance pull-up resistors. W=2L WRITE OPERATION: Pull-up ratio=W4/W6=W5/W3=13 W4=W5=3.6.

CIRCUIT DESCRIPTION: SRAM ARCHITECTURE: .

CIRCUIT DIAGRAM: .

WAVEFORM: For Write: .

26611e-009 For Read: Power Estimated=3.ANALYSIS: Power Results: For Write: Power Estimated = 2.47523e-009 .375677e-003 at time 5.036401e-003 at time 5.

RESULT: .