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Hochschule Darmstadt

University of Applied Sciences

Microelectronic Systems
WS14/15

Prof. Dr.-Ing. T. Schumann

ModelSim Intro
ModelSim PE Student Edition is available for free at: http://go.mentor.com/33rqn
Please follow the installation procedure I have sent out.
The following intro to ModelSim provides you a step-by-step description of how to
simulate a vhdl-model.

1.create a new directory for saving your project data on lab PC:
c:/MSE/Micro
2. double click on icon ModelSim to start ModelSim PE Student Edition,
create new project: File -> New -> Project, name:lab1, project location:c:/MSE/Micro,
default library:work, click OK
a window pops up, click on create new file, name:fulladder, file type:VHDL
close that window, double click on fulladder.vhd in the Workspace window
3. edit VHDL code and click the save button
4. compile code by command in Transcript window: vcom fulladder.vhd

5.Simulate -> Start Simulation, a Simulation window opens, click on + at work folder,
select fulladder, click ok

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Schumann 6. click ok 9. select A. Simulate -> Run -> Run 100ns 8. Simulate -> Run -> Run 100ns 10.Hochschule Darmstadt University of Applied Sciences Microelectronic Systems WS14/15 Prof.-Ing. Dr. Simulate -> End Simulation If you want to add a VHDL-testbench you need to follow step 11-18 2 . Force: value:1. T. in Instance window select fulladder. right mouse click:Add ->To wave -> All items in region 7. in Objects window. right mouse click.

File -> Save 13. click ok 15. click on + at work folder.-Ing. right mouse click: Add to Project -> New File . a new window for VHDL file opens 12. in Instance window select entity name of test bench. add file as type:VHDL Click OK. right mouse click:Add -> To wave -> All items in region 16. mouse click within Projects window. right mouse click: Compile -> Compile All 14. Simulate -> Run -> Run All 17. Simulate -> Start Simulation. Zoom out to show wave for all inputs 18. Schumann 11. mouse click within Projects window. Simulate -> End Simulation 3 . select the entity name of test bench.Hochschule Darmstadt University of Applied Sciences Microelectronic Systems WS14/15 Prof. a window opens. write VHDL code. T. File Name:testb_fulladder. Dr.