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2455 South Road, Poughkeepsie, NY 12601 March 11, 2010

Mr. Roger Bowler President TurboHercules SAS Tour Arane, 33eme etage 5, Place de la Pyramide La Defense 9 92088 PARIS LA DEFENSE FRANCE Re: TurboHercules Dear Mr. Bowler: We have received and considered your letter of November 18, 2009. The comments you provide do not lead IBM to reconsider IBM's position as set out in my letter of November 4, 2009. Your suggestion that TurboHercules was unaware that IBM has intellectual property rights in this area is surprising. IBM has spent many years and many billions of dollars developing its z-architecture and technology, and is widely known to have many intellectual property rights in this area. IBM's litigation against PSI for, among other things, patent infringement and trade secret misappropriation is a matter of public record, and well known in the industry. According to your own statements, your product emulates significant portions of IBM's proprietary instruction set architecture and IBM has many patents that would, therefore, be infringed. For illustration, I enclose with this letter a non-exhaustive list ofIBM u.S. patents that protect innovative elements ofIBM's mainframe architecture and that IBM believes will be infringed by an emulator covering those elements. For your information, the enclosed list also includes a non-exhaustive list of relevant IBM u .s . published patent applications. Apart from concerns about unauthorized use of proprietary IBM information by one or more TurboHercules contributors, IBM therefore has substantial concerns about infringement of patented IBM technology. In these circumstances, I trust you will understand that IBM cannot agree to your request to reconsider its position.

Sincerely,

Mark S. Anzani VP and Chief Technology Officer, IBM System z

Non-Exhaustive List ofmM U.S. Patents and mM U.S. Published Patent Applications
NO.

US
PATENT

FEATURE TYPE

TITLE

OR
1.

APPLlCA TIONNO. 7,624,237
7,617,410

2.

INSTRUCTION SET ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE

3. 4. 5. 6. 7.

7,600,053 7,594,094 7,587,531 7,581,074 7,543 ,095

CHANNEL SUBSYSTEM ARCHITECTURE INSTRUCTION SET ARCHITECTURE C HANNEL SUBSYSTEM ARCHITECTURE MEMORY ARCHITECTURE VIRTUALIZATION ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE VIRTUALIZATION ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE VIRTUALIZATION ARCHITECTURE CHANNEL SUBSYSTEM ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE CHANNEL SUBSYSTEM ARCHITECTURE INSTRUCTION SET ARCHITECTURE MEMORY ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE MEMORY ARCHITECTURE VIRTUALIZATION

8. 9. 10.

7,516,304 7,500,084 7,454,548

COMPARE, SWAP AND STORE FACILITY WITH NO EXTERNAL SERIALIZATION SIMULTANEOUSLY UPDATING LOGICAL TIME OF DAY (TO D) CLOCKS FOR MULTIPLE CPUS IN RESPONSE TO DETECTING A CARRY AT A PRE­ DETERM INED BIT POSlTlON OF A PHYSICAL CLOCK EMULATION OF EXTENDED INPUT/OUTPUT MEASUREMENT BLOCK FACILITIES MOVE DATA FACILITY WITH OPTIONAL SPECIFICATIONS MULTIPLE LOGICAL INPUT/OUTPUT SUBSYSTEM FACILITY FACILITATING USE OF STORAGE ACCESS KEYS TO ACCESS STORAGE MANAGING INP UT/OUTPUT INTERRUPTIONS IN NON- DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS PARSING-ENHANCEMENT FACILITY MULTIFUNCTION HEXADECIMAL INSTRUCTION FORM MANAGING INPUT/OUTPUT INTERRUPTIONS IN NON-DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS, AND METHODS THEREFOR DIRECTLY OBTAINING BY APPLICATION PROGRAMS INFORMATION USABLE IN DETERMINING CLOCK ACCURACY MANAGING INPUT/OUTPUT INTERRUPTIONS IN NON-DEDICATED INTERRUPTION HARDWARE ENV IRONMENTS EXTENDED INPUT/OUTPUT MEASUREMENT BLOCK METHOD AND APPARATUS FOR ADJUSTING A TIM E OF DAY CLOCK WITHOUT ADJUSTING THE STEPPING RATE OF AN OSCILLATOR SECURITY MESSAGE AUTHENTICATION CONTROL INSTRUCTION M ULTlPLE LOGICAL INPUT/OUTPUT SUBSYSTEM FACILITY INV ALIDATfNG STORAGE, CLEARING BUFFER ENTRIES, AND AN INSTRUCTION THEREFOR METHOD, SYSTEM AND PROGRAM PRODUCT FOR CLEARING SELECTED STORAGE TRANSLATION BUFFER ENTRIES CIPHER MESSAGE ASSIST INSTRUCTIONS MULTIFUNCTION HEXADECIMAL INSTRUCTIONS METHOD, SYSTEM AND PROGRAM PRODUCT FOR INVALIDATING A RANGE OF SELECTED STORAGE TRANSLATION TABLE ENTRIES METHOD AND APPARATUS FOR MANAGING THE

11.

7,395,448

12.

7,380,041

13. 14.

7,373,435 7,356,725

15.
16.

7,356,710 7,290,070 7,284,100 7,281,1 15

17. 18.

19. 20. 2l.

7,257,718 7,254,698 7,197,601

22.

I 7,197,585

2

NO.

US . FEATURE TYPE pAtENT i. OR APPLICA ' TIONNO. ARCHITECTURE 7,174,550
CHANNEL SUBSYSTEM ARCHITECTURE CHANNEL SUBSYSTEM ARCHITECTURE INSTRUCTION SET ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE VIRTUALIZATION ARCHITECTURE CHANNEL SUBSYSTEM ARCHITECTURE

TITLE

23.

I

24. 25. 26. 27.

7,174,274 7,159.122 7,146,523 7,130,949

I I
i

EXECUTION OF A BROADCAST INSTRUCTION ON A GUEST PROCESSOR SHARING COMMUNICATIONS ADAPTERS ACROSS A PLURALITY OF INPUT/OUTPUT SUBSYSTEM IMAGES GATHERING [f0 MEASUREMENT DATA DURING AN 110 OPERATION PROCESS MESSAGE DIGEST INSTRUCTIONS

28.

I 7.127,599

I
29. 30.
I

7,058,837 7,013,305

I

PARALLEL SYSPLEX ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE

I
31­ 32. 33.

I
7,003,700 7,000,036 6,996,638
PARALLEL SYSPLEX ARCHITECTURE CHANNEL SUBSYSTEM ARCHITECTURE CHANNEL SUBSYSTEM ARCHITECTURE

I

MONITORING PROCESSING MODES OF COUPLING FACILITY STRUCTURES . MANAGING INPUT/OUTPUT INTERRUPTIONS IN I NON-DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS MANAGING CONFIGURATIONS OF INPUT/OUTPUT SYSTEM IMAGES OF AN INPUT/OUTPUT SUBSYSTEM, WHEREIN A CONFIGURATION IS MODIFIED WITHOUT RESTARTING THE INPUT/OUTPUT SUBSYSTEM TO EFFECT A MODIFICATION METHOD AND SYSTEM FOR PROVIDING A MESSAGE-TIME-ORDERING FACILITY MANAGING THE STATE OF COUPLING FACILITY STRUCTURES, DETECTING BY ONE OR MORE I SYSTEMS COUPLED TO THE COUPLING FACILITY, THE SUSPENDED STATE OF THE DUPLEXED I COMMAND, DETECTING BEING INDEPENDENT OF MESSAGE EXCHANGE HALTING EXECUTION OF DUPLEXED COMMANDS EXTENDED INPUT/OUTPUT MEASUREMENT FACILITIES METHOD, SYSTEM AND PROGRAM PRODUCTS FOR ENHANCING INPUT/OUTPUT PROCESSING FOR OPERATING SYSTEM IMAGES OF A COMPUTING ENVIRONMENT METHOD, SYSTEM, AND PRODUCT FOR BOOTING A PARTITION USING ONE OF MULTIPLE, I DIFFERENT FIRMWARE IMAGES WITHOUT REBOOTING OTHER PARTITIONS I MEASURING UTILIZATION OF INDIVIDUAL COMPONENTS OF CHANNELS METHOD AND APP ARATUS FOR PROCESSING A LIST STRUCTURE SYSTEM-MANAGED DUPLEXING OF COUPLING FACILITY STRUCTURES METHOD AND APPARATUS FOR IMPLEMENTING A SHARED MESSAGE QUEUE USING A LIST STRUCTURE SYNCHRONIZING PROCESSING OF COMMANDS INVOKED AGAINST DUPLEXED COUPLING FACILITY STRUCTURES RESTARTING A COUPLING FACILITY COMMAND USING A TOKEN FROM ANOTHER COUPLING FACILITY COMMAND METHOD, SYSTEM AND PROGRAM PRODUCTS

i

I I

34.

6,971,002

I PARTITIONING
I
CHANNEL SUBSYSTEM ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE
I

35. 36. 37. 38.

6,963,940 6,963,882 6,944,787 6,862,595

I

39.

6,859,866

PARALLEL SYSPLEX ARCHITECTURE

40.

6,813,726

I ARCHITECTURE

1

PARALLEL SYSPLEX

41.

6,775 ,789

INSTRUCTION SET

3

NO.

US
PATENT OR APPLICA TIONNO.

FEATURE TYPE

TITLE

ARCH[TECTU RE

42. 43.

l 6,748,460
! 6,7 14,997
I
I I 6,687,853 6,681 ,238

CHANNEL SU BSYSTEM ARCHITECTURE VIRTUALIZAT[ON ARCHITECTURE

44. 45.

C HANNEL SUBSYSTEM ARCHITECTURE V IRTUALIZATION ARCHITECTURE PARTIT[ONING

46.

6,654,8 12

I

47. 48. 49. 50.

6,615 ,373 6,609,214 6,598,069 6,594,667

PARALLEL SYSPLEX ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE PARTITIONING PARALLEL SYSPLEX ARCHITECTURE PARALLEL SYSPLEX ARCH ITECTURE PARTITIONING P ARALLEL SYSPLEX ARC HITECTURE PARALLEL SYSPLEX ARCHITECTURE CHA NNEL SUBSYSTEM ARCHITECTURE CHANNEL SUBSYSTEM ARCH ITECTURE

51. 52. 53.
I

6,584,554 6,567,841 6,539,495

I

54. 55.

I 6,43 8,654
6,345,329

\ 56.

I 6,339,802 I6
1 ,336, [84

57.

INSTRUCTION SET ARCH ITECTURE CHANNEL SUBSYSTEM ARCH ITECTURE

58.

6,332,171

59. 60.

6,237 ,000 6,209,106

PARALLEL SYSPLEX A RCHITECTURE PARALLEL SYSPLEX ARCHITECTURE

FOR GENERATING SEQUENCE VALUES THAT ARE UN [Q UE ACROSS OPERATING SYSTEM IMAGES INIT[ATIVE PASSING IN AN lIO OPERATION WI T HOUT THE OVERHEAD OF AN INTERRUPT . METHOD AND MEANS FOR ENHANCED [NTERPRETIVE INSTRUCTIO N EXECUTION FOR A NEW INTEGRATED COMMUN ICATIONS ADAPTER USING A QUEUED DIRECT INPUT-OUTPUT DEVICE CHECKPOINTING FOR RECOVERY OF CHANNELS IN A DATA PROCESSING SYSTEM METHOD AND SYSTEM FOR PROVIDING A HARDWARE MAC HI NE FUNCTION [N A PROTECTED VIRTUAL MACHINE COMMUN [CATION BETWEEN MULTIPLE PARTITIONS EMPLOYING HOST-NETWORK INTERFACE METHOD, SYSTEM AND PROGRAM PRODUCTS FOR RESOLVING POTENTIAL DEADLOCKS METHOD, SYSTEM AN D PROGRAM PRODUCTS FOR COPYING COU PLING FACILITY STRUCTURES METHOD AND APPARATUS FOR ASS IGNI NG RESOURCES TO LOGICAL PARTIT[ON CLUSTERS METHOD, SYSTEM AND PROGRAM PRODUCTS FOR MODIFYING COUPLING FACILITY STRUCTURES DIRECTED ALLOCATION OF COUPLING FACILITY STRUCTURES METHOD AND APPARATUS FOR CREATING AND IDENTIFYING LOGICAL PARTITION C LUSTERS METHOD, SYSTEM AND PROGRAM PRODUCTS FOR PROVIDING USER-MANAGED DUPLEXING OF COUPLING FACILITY CACHE STRUCTURES CASTOUTPROC ESSING FOR DUPLEXED CACHE STRUCTURES METHOD AND APPARATUS FOR EXCHANGING DATA USING A QUEUED D[RECT INP UT-OUTPUT DEV ICE COMPUTER PROGRAM DEVIC E AND AN APPARATUS FOR PROCESSING OF DATA REQUESTS US ING A QUEUED DIRECT INPUT­ OUTPUT DEVICE METHOD AND APPARATUS FOR PERFORMING A TRAP OPERATION IN AN INFORMATION HANDLING SYSTEM SELF-CONTAINED QUEUES WITH ASSOCIATED CONTROL IN FORMATION FOR RECEIPT AND TRANSFER OF INCOMI NG AN D OUTGOING DATA US ING A QUEUED DIRECT INPUT-OUTPUT DEVICE MET HOD AND APPARATUS FOR PREVIEWING THE RESULTS OF A DATA STRUCTURE ALLOCATION METHOD AND APPARATUS FOR SYNCHRONIZING SELECTED LOGICAL PARTITIONS OF A PARTITJONED INFORMATION HANDLING SYSTEM TO AN EXTERNAL TIME REFERENCE

4

NO.

61.

US PATENT OR APPLICA .TIONNO. 6,189,007

FEATURE TYPE

TITLE

I
I

PARALLEL SYSPLEX ARCHITECTURE INSTRUCTIo.N SET ARCHITECTURE EMULATlo.N

I HIGH PERFORMANCE LOCKING FACILITY IN A

METHOD AND APPARATUS FOR CONDUCTING A

62. 63.

6,085,313
I

6,009,261

64.

5,987,495

INSTRUCTIo.N SET ARCHITECTURE EMULATIo.N PARALLEL SYSPLEX ARCHITECTURE

65. 66.

5,953,520 5,923 ,890

67.

5,893,157

INSTRUCTIo.N SET ARCHITECTURE

I

I
68.
I

I

5,887,135

PARALLEL SYSPLEX ARCHITECTURE

I
69. 5,875 ,484 PARALLEL SYSPLEX ARCHITECTURE EMULATIo.N

70.

5,875,336

71.

5,860,115

PARALLEL SYSPLEX ARCHITECTURE

I
72.

5,825,678 5,822,562

73.

INSTRUCTIo.N SET ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE

74.

5,76 1,739

75.

5,745,676

I ARCHITECTURE

INSTRUCTIo.N SET

76.

I 5,742,830
5,706,432 5,704,055

PARALLEL SYSPLEX ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE o.THER ARCHITECTURE

77.
78.

LOOSELY Co.UPLED ENVIRo.NMENT COMPUTER PROCESSOR SYSTEM FOR EXECUTING I RXE FORMAT FLOATING POINT INSTRUCTIONS PREPROCESSING o.F STo.RED TARGET Ro.UTINES Fo.R EMULATING INCOMPATIBLE INSTRUCTIONS o.N A TARGET PRo.CESSo.R METHOD AND APPARATUS FOR FULLY RESTORING A PROGRAM Co.NTEXT Fo.LLOWING AN INTERRUPT ADDRESS TRANSLATIo.N BUFFER FOR DATA PRo.CESSING SYSTEM EMULATIo.N Mo.DE METHOD AND APP ARA TUS Fo.R o.PTIMIZING THE 1 I HANDLING o.F SYNCHRo.NOUS REQUESTS TO A I Co.UPLING FACILITY IN A SYSPLEX I Co.NFIGURATION BLo.CKING SYMBOL Co.NTRo.L IN A COMPUTER SYSTEM TO SERIALIZE ACCESSING A DATA RESo.URCE BY SIMULTANEo.US PROCESSo.R REQUESTS I SYSTEM AND METHo.D FOR MANAGEMENT OF I o.BJECT TRANSITIONS IN AN EXTERNAL STORAGE FACILITY ACCESSED BY o.NE o.R Mo.RE PROCESSORS I 1 METHOD AND SYSTEM FOR DETERMINING AND OVERRIDING INFo.RMATION UNA V AILABILITY TIME AT A COUPLING FACILITY METHOD AND SYSTEM Fo.R TRANSLATING A NON-NATIVE BYTECo.DE TO. A SET OF Co.DES NATIVE TO A PRo.CESSo.R WITHIN A Co.MPUTER SYSTEM REQUESTING A DUMP o.F INFo.RMATlo.N STo.RED WITHIN A Co.UPLING FACILITY, IN WHICH THE DUMP INCLUDES SERVICEABILITY INFORMATIo.N FRo.M AN o.PERATING SYSTEM THAT LOST Co.MMUNICATION WITH THE Co.UPLlNG FACILITY METHOD AND APPARATUS FOR DETERMINING I FLo.ATING Po.INT DATA CLASS METHOD AND APPARATUS Fo.R EXPANSlo.N, I CONTRACTlo.N, AND REAPPo.RTIONMENT o.F STRUCTURED EXTERNAL STORAGE STRUCTURES METHODS AND SYSTEMS Fo.R CREATING A STo.RAGE DUMP WITHIN A COUPLING FACILITY o.F A MULTISYSTEM ENVIRo.MENT AUTHORITY REDUCTlo.N AND RESTo.RATIo.N METHOD PRo.VIDING SYSTEM INTEGRITY Fo.R I I SUBSPACE GRo.UPS AND SINGLE ADDRESS SPACES DURING PROGRAM LI NKAGE I METHo.D AND APPARATUS Fo.R PERFo.RMING Co.NDlTIONAL o.PERATIo.NS o.N EXTERNALLY ! SHARED DATA MECHANISM FOR RECEIVING MESSAGES AT A Co.UPLING FACILITY DYNAMIC RECo.NFIGURATION o.F MAIN I

I I
i

I

I

I
I
i

I

I

I

5

N6.

US
PATENT

FEATURE TYPE

,

TITLE

OR

I
I

APPLICA TIONNO.
STORAGE AND EXPANDED STORAGE BY MEANS OF A SERVICE CALL LOGICAL PROCESSOR PROGRAM CONTROLLED ROUNDING MODES

I I I
, IMPLEMENTATION OF BINARY FLOATING POINT
USING HEXADECIMAL FLOATING POfNT UNIT SYSTEM FOR SYNCHRONIZING LOGICAL CLOCK IN LOGICAL PARTITION OF HOST PROCESSOR WITH EXTERNAL TIME SOURCE BY COMBINING CLOCK ADJUSTMENT VALUE WITH SPECIFIC V ALUE OF PARTITION METHOD AND SYSTEM FOR CAPTURING AND CONTROLLING ACCESS TO INFORMATION IN A COUPLING FACILITY METHOD AND SYSTEM FOR LOCKING A PAGE OF REAL STORAGE USING A VIRTUAL ADDRESS METHOD AND APPARATUS FOR EXPANSION, CONTRACTION , AND REAPPORTIONMENT OF STRUCTURED EXTERNAL STORAGE STRUCTURES MULTI CHANNEL INTER-PROCESSOR COUPLING FACILITY PROCESSING RECEIVED COMMANDS STORED IN MEMORY ABSENT STATUS ERROR OF CHANNELS ALLOWED OPERATIONAL-LINK TRANSCEIVER TABLE VERIFIES THE OPERATIONAL STATUS OF TRANSCEIVERS IN A MULTIPLE CONDUCTOR DAT A TRANSMISSION LINK IN A MULTIPROCESSING SYSTEM HAVING A COUPLING FACILITY, COMMUNICATING MESSAGES BETWEEN THE PROCESSORS AND THE I COUPLING FACILITY IN EITHER A SYNCHRONOUS I OPERATION OR AN ASYNCHRONOUS OPERATION COHERENCE CONTROLS FOR STORE-MULTIPLE SHARED DATA COORDINATED BY CACHE DIRECTORY ENTRIES IN A SHARED ELECTRONIC STORAGE MULTIPLE PROCESSOR SYSTEM HAVING SOFTW ARE FOR SELECTING SHARED CACHE ENTRIES OF AN ASSOCIATED CASTOUT CLASS FOR TRANSFER TO A DASD WITH ONE I/O OPERATION ! METHOD AND SYSTEM FOR PROVIDING A PROGRAM CALL TO A DISP ATCHABLE UNIT'S BASE SPACE ! COUPLING FACILITY FOR RECEIVING COMMANDS FROM PLURALITY OF HOSTS FOR ACTIV ATING SELECTED CONNECTION PATHS TO I/O DEVICES AND MAINTAINING STATUS THEREOF ASYNCHRONOUS COMMAND SUPPORT FOR SHARED CHANNELS FOR A COMPUTER COMPLEX HAVING MULTIPLE OPERATING SYSTEMS AUTHORIZATION METHOD FOR CONDITIONAL COMMAND EXECUTION METHOD AND MEANS PROVIDING STADC DICTIONAR Y STRUCTURES FOR COMPRESSING I
I

79. 80. 8l.

5,696,709 5,687,106 . 5,636,373

INSTRUCTION SET ARCHITECTURE OTHER ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE

82.
I
I

5,630,050

I ARCHITECTURE

PARALLEL SYSPLEX

I 83.
I

5,613,086 5,581,737

84.

INSTRUCTION SET ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE

i
I
I

85 .

5,574,945

86.

5,574,938

PARALLEL SYSPLEX ARCHITECTURE

I
,
I

I

87.

5,561,809

PARALLEL SYSPLEX ARCHITECTURE

I

I I

88 .

5,544,345

PARALLEL SYSPLEX ARCHITECTURE

89.

5,493,668

I
90. 5,493,661

I ARCHITECTURE

PARALLEL SYSPLEX

I

I
91. 5,463 ,736

INSTRUCTION SET ARCHITECTURE

I

I ARCHITECTURE

PARALLEL SYSPLEX

I I

I

92.

5,452,455

CHANNEL SUBSYSTEM ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE OTHER ARCHITECTURE

93 . 94.

5,450,590

I

,

5,442,350

I

6

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----

~

1
NO.

US
PATENT OR APPLICA H ONNO.

FEATURE TYPE
.y

TITLE

I
I

I 95 . I
96.

!

I
5,416,921
I

I ! PARALLEL SYSPLEX
I ARCHITECTURE
PARTITIONING

5,414,851

97.

5,410,695

PARALLEL SYSPLEX ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE

98.

5,394,554

I
99. 5,394,542 PARALLEL SYSPLEX ARCHITECTURE

I
100. 5,392,397 PARALLEL SYSPLEX ARCHITECTURE

I
10 J. 5,381,535 102. ]03. 104. 5,361,356 5,339,405 5,331,673

I
I
VIRTUALIZATION ARCHITECTURE INSTRUCTION SET ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE PARALLEL SYSPLEX ARCHITECTURE OTHER ARCHITECTURE INSTRUCTION SET ARCHITECTURE CHANNEL SUBSYSTEM ARCHITECTURE CHANNEL SUBSYSTEM ARCHITECTURE CHANNEL SUBSYSTEM ARCHITECTURE

CHARACTER DATA AND EXPANDING COMPRESSED DATA APPARATUS AND ACCOMPANYING METHOD FOR USE IN A SYSPLEX ENVIRONMENT FOR PERFORMING ESCALATED ISOLATION OF A SYSPLEX COMPONENT IN THE EVENT OF A FAILURE . METHOD AND MEANS FOR SHARING I/O RESOURCES BY A PLURALITY OF OPERATING SYSTEMS APPARATUS AND METHOD FOR LIST MANAGEMENT IN A COUPLED DATA PROCESSING SYSTEM INTERDICTING I/O AND MESSAGING OPERATIONS FROM SENDING CENTRAL PROCESSING COMPLEX TO OTHER CENTRAL PROCESSING COMPLEXES AND TO I/O DEVICE IN MULTI-SYSTEM COMPLEX CLEARING DATA OBJECTS USED TO MAINTAIN STATE INFORMATION FOR SHARED DATA AT A LOCAL COMPLEX WHEN AT LEAST ONE MESSAGE PATH TO THE LOCAL COMPLEX CANNOT BE RECOVERED COMMAND EXECUTION SYSTEM FOR USING FIRST AND SECOND COMMANDS TO RESERVE AND STORE SECOND COMMAND RELATED STATUS INFORMATION lN MEMORY PORTION RESPECTIVELY DATA PROCESSrNG CONTROL OF SECOND-LEVEL QUEST VIRTUAL MACHINES WITHOUT HOST INTERVENTION STORAGE ISOLATION WITH SUBSPACE-GROUP FACILITY COMMAND QUIESCE FUNCTION

I
I

I

I I
I
!

I

105. 106. 107. 108.
I

5,317,739 5,220,669 App. ]2/0295 14 App. 12/030912 App. 12/030954

109. 110.

lAPP' 12/031038

I I I
I

11 l.

I
I
I

lApp. 12/03120] App. 12/036725

CHANNEL SUBSYSTEM ARCHITECTURE VIRTUALIZATION ARCHITECTURE

112.

I

INTEGRITY OF DATA OBJECTS USED TO I MAINTAIN STATE INFORMATION FOR SHARED I DATA AT A LOCAL COMPLEX ! METHOD AND APPARATUS FOR COUPLING DATA I ! PROCESSING SYSTEMS LINKAGE MECHANISM FOR PROGRAM ISOLATION SECURITY MESSAGE AUTHENTICATION INSTRUCTION DETERMINING EXTENDED CAPABILITY OF A CHANNEL PATH I Bl-DIRECTIONAL DATA TRANSFER WITHIN A . SINGLE 110 OPERATION PROVIDING INDIRECT DATA ADDRESSING IN AN INPUT/OUTPUT PROCESSING SYSTEM WHERE THE INDIRECT DATA ADDRESS LIST IS NON­ I CONTIGUOUS PROVIDING INDIRECT DATA ADDRESSING FOR A CONTROL BLOCK AT A CHANNEL SUBSYSTEM OF I AN I/O PROCESSING SYSTEM OPTIMIZATIONS OF A PERFORM FRAME MANAGEMENT FUNCTION ISSUED BY PAGEABLE GUESTS

I

i

7

NO.

US
PATENT

FEATURE TYPE

TITLE

OR
113.

APPLICA nON NO. App. 12/037177
App. 12/037268 App. 12/052675 App. 12/052683 App. 111182570 App. 111223641 App. 12/3 63825 App. 12/394579 App. 12/417943 App. 11/437220 App. 12/488670 App. 11/469573 App. 111469916 App. 111469919 App. 12/540261 App. 12/555974 App. 11/532172 App. 11/532177 App. 111551292 App. 111680894 App. 11/692382 App. 111733224 App. 111740165 App.
I

VIRTUALIZATION ARCHITECTURE VIRTUALIZATION ARCHITECTURE VIRTUALIZATION ARCHITECTURE VIRTUALIZATION ARCHITECTURE VIRTUALIZATION ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET I ARCHITECTURE INSTRUCTION SET ARCHITECTURE [NSTRUCTION SET I ARCHITECTURE CHANNEL SUBSYSTEM ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE MEMORY ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET

114. 115.

i

116.

I

117.

118. 119. 120. 121. 122. 123. 124.

SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A SHARED MEMORY TRANSLATION FACILITY DYNAMIC ADDRESS TRANSLATION WITH TRANSLATION EXCEPTION QUALIFIER MANAGING USE OF STORAGE BY MULTIPLE PAGEABLE GUESTS OF A COMPUTING ENVIRONMENT USE OF TEST PROTECTION INSTRUCTION IN COMPUTING ENVIRONMENTS THAT SUPPORT PAGEABLE GUESTS FACILITATING PROCESSING WITHIN COMPUTING ENVIRONMENTS SUPPORTING PAGEABLE GUESTS FUSED MULTIPLY ADD SPLIT FOR MULTIPLE PRECISION ARITHMETIC MULTIFUNCTION HEXADECIMAL INSTRUCTION FORM SYSTEM AND PROGRAM PRODUCT CIPHER MESSAGE ASSIST INSTRUCTION PARSING-ENHANCEMENT FACILITY EXTRACT CPU TIM E FACILITY

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1

I 125. I
126.

127.

128. 129. 130. 131. 132. 133. 134.

I

STORE CLOCK AN D STORE CLOCK FAST INSTRUCTION EXECUTION GATHERING I/O MEASUREMENT DATA DURING AN I/O OPERATION PROCESS METHOD OF EMPLOYING INSTRUCTIONS TO CONVERT UTF CHARACTERS WITH AN . ENHANCED EXTENDED TRANSLATION FACILITY METHOD OF TRANSLATING N TO N INSTRUCTIONS EMPLOYING AN EN HANCED EXTENDED TRANSLATION FACILITY PERFORMING A PERFORM TIMING FACILITY FUNCTION INSTRUCTION FOR SYCHRONIZING TODCLOCKS COMPARE, SWAP AND STORE FACILITY WITH NO EXTERNAL SERIALIZATION METHOD AND SYSTEM OF RECORDING TIME OF DAY CLOCK ENHANCED STORE FACILITY LIST SYSTEM AND OPERATION MESSAGE DIGEST INSTRUCTION

I

I

!

135.

136.

ROUND FOR REROUND MODE IN A DECIMAL FLOATING POINT INSTRUCTION I OPTIONAL FUNCTION MULTI-FUNCTION I I INSTRUCTION CLEARING SELECTED STORAGE TRANSLATION BUFFER ENTRIES BASED ON TABLE ORIG!N ADDRESS DETECTION OF POTENTIAL NEED TO USE A LARGER DATA FORMAT IN PERFORMING FLOATING POINT OPERATIONS MANAGEMENT OF EXCEPTIONS AND HARDWARE

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8

NO.

US
PATENT OR APPLICA TIONNO. 111740185 App. 111740683
lAPP. 111740701 App. 111740711 App. 111740721

FEATURE TYPE

TITLE

137. 138. 139.

ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE fNSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE VIRTUALIZATION ARCHITECTURE

140.

I
14l. 142 . 143. 144. 145. 146. 147. 148. App. 111770861 App. 11178 1574 App. 11 178 1650 App. 11 /840323 App. 111840345 App. 111840359 App. 111868605 App. 10/854990

!

149.

App. 10/855200 App. 11 /954526 App. 11/965866 App. 11 /968733 App. 11 /972666 App. 11/972675 App. 11 /972679 App. 111972682 App. 11 /972688 App. 11 /972689 App. 11 /972694 App. 11 /972697 App.

VIRTUALIZATION ARCHITECTURE INSTRUCTION SET ARCHITECTURE CHANNEL SUBSYSTEM ARCHITECTURE INSTRUCTION SET ARCHITECTURE fNSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTURE MEMORY ARCHITECTURE MEMORY ARCHITECTURE fNSTRUCTION SET ARCHITECTURE MEMORY ARCHITECTURE MEMORY ARCHITECTURE MEMORY

150. 151.

152. 153. 154. 155. 156. 157. I58. 159. 160. 161.

INTERRUPTIONS BY AN EXCEPTION SIMULATOR INSERT/EXTRACT BIASED EXPONENT OF DECIMAL FLOATING POINT DATA SHIFT SIGNIFICAND OF DECIMAL FLOATING POINT DATA COM POSITION/ DECOMPOSITION OF DEClMAL FLOATING POINT DATA CONVERT SIGN IFICAND OF DECIMAL FLOATING POINT DATA TO/FROM PACKED DECIMAL FORMAT EXTRACT BIASED EXPONENT OF DECIMAL FLOATING POINT DATA CONVERT SIGN IFICAND OF DECIMAL FLOATING POINT DATA TO PACKED DECIMAL FORMAT CONVERT SIGNIFICAND OF DECIMAL FLOATING POlNTDATA FROM PACKED DECIMAL FORMAT COMPOSITION OF DECIMAL FLOATfNG POINT DATA, AND METHODS THEREFORE DECOMPOSITION OF DECIMAL FLOATING POINT DATA DECOMPOSITION OF DECIMAL FLOATING POINT DATA, AND METHODS THEREFORE PERFORM FLOATING POINT OPERATION INSTRUCTION FACILITATING MANAGEMENT OF STORAGE OF A PAGEABLE MODE VIRTUAL ENVIRONMENT ABSENT INTERVENTION OF A HOST OF THE ENVIRONMENT INTERPRETING I/O OPERATION REQUESTS FROM PAGEABLE GUESTS W ITHOUT HOST INTERVENTION PRE-FETCH DATA AND PRE-FETCH DATA RELATIVE EXTENDED INPUT/OUTPUT MEASUREMENT WORD FACILITY, AND EM ULATION OF THAT FACILITY SYSTEM AND METHOD FOR TOO-CLOCK STEERING COMP ARE AND BRANCH FACILITY AND INSTRUCTION THEREFORE EXTRACT CACHE A TTRIB UTE FACI LITY AN 0 INSTRUCTION THEREFORE ROTATE THEN OPERATE ON SELECTED BITS FACILITY AND fNSTRUCTIONS THEREFORE DYNAMIC ADDRESS TRANSLATION WITH ACCESS CONTROL DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION ROTATE THEN INSERT SELECTED BITS FACILITY I AND INSTRUCTIONS THEREFORE DYNAM IC ADDRESS TRANSLATION WITH CHAN GE RECORDING OVERRIDE DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL DYNAMIC ADDRESS TRANSLATION WITH LOAD

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NO.

US pATENT OR APPLICA TIONNO,
11/972700 App. 111972705 lApp. 11/972706 App. 1119727 13 App. 11/972714 App. 111972715 App. 11/972718 App. 11/972725 App. 111972740 lAPP. ] 11972766 App. 11/972780 App. 111972791 App. 11 /972802

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FEATURE TYPE

TITLE

162. 163.
I

164. 165.

I

166. 167. 168.

I

169. 170.

ARCHITECTURE MEMORY A RCHITECTURE MEMORY ARCHITECTURE MEMORY ARCHITECTURE INSTRUCTION SET ARCHITECTURE MEMORY ARCHITECTURE MEMORY ARCHITECTURE MEMORY ARCHITECTURE INSTRUCTION SET ARCHITECTU RE INSTRUCTION SET ARCHITECTURE

I

171. 172. 173.

I ARCHITECTURE

IN STRUCTION SET

INSTRUCTION SET ARCHITECTURE INSTRUCTION SET ARCHITECTU RE

PAGE TABLE ENTRY ADDRESS DYNAMIC ADDRESS TRANSLATION WITH LOAD I I REAL ADDRESS I DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAG EMENT EXECUTE RELATIVE LONG FACILITY AND INSTRUCTIONS THEREFORE I DYNAMIC AD DRESS TRANSLATION WITH DAT I PROTECTION DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT LOAD RELATIVE AND STORE RELATIVE FACILITY AND INSTRUCTIONS THEREFORE I PERFORMING A CONFIGURATION VIRTUAL TOPOLOGY CHANGE AND INSTRUCTION THEREFORE COMPARE RELATIVE LONG FACILITY AND INSTRUCTIONS THEREFORE MOVE FACILITY AND INSTRUCTIONS THEREFORE COMPUTER CONFIGURATION VIRTUAL TOPOLOGY DISCOV ERY AND INSTRUCTION THEREFORE

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