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Features

High-performance, Low-power Atmel AVR 8-bit Microcontroller


Advanced RISC Architecture

131 Powerful Instructions Most Single-clock Cycle Execution


32 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
16 Kbytes of In-System Self-programmable Flash program memory
512 Bytes EEPROM
1 Kbyte Internal SRAM
Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
Data retention: 20 years at 85C/100 years at 25C(1)
Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
Real Time Counter with Separate Oscillator
Four PWM Channels
8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
Byte-oriented Two-wire Serial Interface
Programmable Serial USART
Master/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
I/O and Packages
32 Programmable I/O Lines
40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
Operating Voltages
2.7V - 5.5V for ATmega16L
4.5V - 5.5V for ATmega16
Speed Grades
0 - 8 MHz for ATmega16L
0 - 16 MHz for ATmega16
Power Consumption @ 1 MHz, 3V, and 25C for ATmega16L
Active: 1.1 mA
Idle Mode: 0.35 mA
Power-down Mode: < 1 A

8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega16
ATmega16L
Summary

Rev. 2466TSAVR07/10

Pin
Configurations

Figure 1. Pinout ATmega16


PDIP
(XCK/T0) PB0
(T1) PB1
(INT2/AIN0) PB2
(OC0/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP1) PD6

PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PC3 (TMS)
PC2 (TCK)
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)

PB4 (SS)
PB3 (AIN1/OC0)
PB2 (AIN0/INT2)
PB1 (T1)
PB0 (XCK/T0)
GND
VCC
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)

TQFP/QFN/MLF

(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2

Disclaimer

PD3
PD4
PD5
PD6
PD7
VCC
GND
(SCL) PC0
(SDA) PC1
(TCK) PC2
(TMS) PC3
(INT1)
(OC1B)
(OC1A)
(ICP1)
(OC2)

NOTE:
Bottom pad should
be soldered to ground.

PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)

Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.

ATmega16(L)
2466TSAVR07/10

ATmega16(L)
Overview

The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Block Diagram

Figure 2. Block Diagram


PA0 - PA7

PC0 - PC7

PORTA DRIVERS/BUFFERS

PORTC DRIVERS/BUFFERS

PORTA DIGITAL INTERFACE

PORTC DIGITAL INTERFACE

VCC

GND

AVCC

MUX &
ADC

ADC
INTERFACE

TWI

AREF
PROGRAM
COUNTER

STACK
POINTER

PROGRAM
FLASH

SRAM

TIMERS/
COUNTERS

OSCILLATOR

INTERNAL
OSCILLATOR
XTAL1

INSTRUCTION
REGISTER

GENERAL
PURPOSE
REGISTERS

WATCHDOG
TIMER

OSCILLATOR

XTAL2

X
INSTRUCTION
DECODER

MCU CTRL.
& TIMING

RESET

CONTROL
LINES

ALU

INTERRUPT
UNIT

AVR CPU

STATUS
REGISTER

EEPROM

PROGRAMMING
LOGIC

SPI

USART

+
-

INTERNAL
CALIBRATED
OSCILLATOR

COMP.
INTERFACE

PORTB DIGITAL INTERFACE

PORTD DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

PORTD DRIVERS/BUFFERS

PB0 - PB7

PD0 - PD7

3
2466TSAVR07/10

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega16 provides the following features: 16 Kbytes of In-System Programmable Flash
Program memory with Read-While-Write capabilities, 512 bytes EEPROM, 1 Kbyte SRAM, 32
general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundaryscan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented
Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with
programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops
the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters,
SPI port, and interrupt system to continue functioning. The Power-down mode saves the register
contents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run,
allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC
Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and
ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low-power consumption. In Extended Standby mode, both the main Oscillator
and the Asynchronous Timer continue to run.
The device is manufactured using Atmels high density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the Application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.
The ATmega16 AVR is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.

Pin Descriptions
VCC

Digital supply voltage.

GND

Ground.

Port A (PA7..PA0)

Port A serves as the analog inputs to the A/D Converter.


Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7
are used as inputs and are externally pulled low, they will source current if the internal pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

ATmega16(L)
2466TSAVR07/10

ATmega16(L)
Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega16 as listed on page
58.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins
PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs.
Port C also serves the functions of the JTAG interface and other special features of the
ATmega16 as listed on page 61.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega16 as listed on page
63.

RESET

Reset Input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page
38. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting Oscillator amplifier.

AVCC

AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.

AREF

AREF is the analog reference pin for the A/D Converter.

5
2466TSAVR07/10

Resources

A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Note:

Data Retention

1.

Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85C or 100 years at 25C.

ATmega16(L)
2466TSAVR07/10

ATmega16(L)
Register Summary
Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$3F ($5F)

SREG

$3E ($5E)

SPH

SP10

SP9

SP8

12

SP4

SP3

SP2

SP1

SP0

12

IVSEL

IVCE

48, 69

$3D ($5D)

SPL

$3C ($5C)

OCR0

$3B ($5B)

GICR

SP7
SP6
SP5
Timer/Counter0 Output Compare Register
INT1

INT0

Page

85

INT2

$3A ($5A)

GIFR

INTF1

INTF0

INTF2

70

$39 ($59)

TIMSK

OCIE2

TOIE2

TICIE1

OCIE1A

OCIE1B

TOIE1

OCIE0

TOIE0

85, 115, 133


86, 115, 133

$38 ($58)

TIFR

OCF2

TOV2

ICF1

OCF1A

OCF1B

TOV1

OCF0

TOV0

$37 ($57)

SPMCR

SPMIE

RWWSB

RWWSRE

BLBSET

PGWRT

PGERS

SPMEN

250

$36 ($56)

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

TWIE

180

$35 ($55)

MCUCR

SM2

SE

SM1

SM0

ISC11

ISC10

ISC01

ISC00

32, 68

$34 ($54)

MCUCSR

JTD

ISC2

JTRF

WDRF

BORF

EXTRF

PORF

41, 69, 231

$33 ($53)

TCCR0

FOC0

WGM00

COM01

COM00

WGM01

CS02

CS01

CS00

83

$32 ($52)

TCNT0

$31(1) ($51)(1)

OSCCAL
OCDR

Timer/Counter0 (8 Bits)

85

Oscillator Calibration Register

30

On-Chip Debug Register

227

$30 ($50)

SFIOR

ADTS2

ADTS1

ADTS0

ACME

PUD

PSR2

PSR10

57,88,134,201,221

$2F ($4F)

TCCR1A

COM1A1

COM1A0

COM1B1

COM1B0

FOC1A

FOC1B

WGM11

WGM10

110

$2E ($4E)

TCCR1B

ICNC1

ICES1

WGM13

WGM12

CS12

CS11

CS10

113

$2D ($4D)

TCNT1H

Timer/Counter1 Counter Register High Byte

114

$2C ($4C)

TCNT1L

114

$2B ($4B)

OCR1AH

Timer/Counter1 Counter Register Low Byte


Timer/Counter1 Output Compare Register A High Byte

$2A ($4A)

OCR1AL

Timer/Counter1 Output Compare Register A Low Byte

114

$29 ($49)

OCR1BH

Timer/Counter1 Output Compare Register B High Byte

114

114

$28 ($48)

OCR1BL

Timer/Counter1 Output Compare Register B Low Byte

114

$27 ($47)

ICR1H

Timer/Counter1 Input Capture Register High Byte

114

$26 ($46)

ICR1L

Timer/Counter1 Input Capture Register Low Byte

$25 ($45)

TCCR2

$24 ($44)

TCNT2

Timer/Counter2 (8 Bits)

$23 ($43)

OCR2

Timer/Counter2 Output Compare Register

$22 ($42)

ASSR

$21 ($41)
$20(2) ($40)(2)

FOC2

WGM20

COM21

114
COM20

WGM21

CS22

CS21

CS20

128
130
130

AS2

TCN2UB

OCR2UB

TCR2UB

WDTCR

WDTOE

WDE

WDP2

WDP1

WDP0

UBRRH

URSEL

UBRR[11:8]

131
43
167

UCSRC

URSEL

UMSEL

UPM1

UPM0

USBS

UCSZ1

UCSZ0

UCPOL

166

$1F ($3F)

EEARH

EEAR8

19

$1E ($3E)

EEARL

EEPROM Address Register Low Byte

$1D ($3D)

EEDR

EEPROM Data Register

$1C ($3C)

EECR

EERIE

EEMWE

EEWE

EERE

$1B ($3B)

PORTA

PORTA7

PORTA6

PORTA5

PORTA4

PORTA3

PORTA2

PORTA1

PORTA0

66

$1A ($3A)

DDRA

DDA7

DDA6

DDA5

DDA4

DDA3

DDA2

DDA1

DDA0

66
66

19
19
19

$19 ($39)

PINA

PINA7

PINA6

PINA5

PINA4

PINA3

PINA2

PINA1

PINA0

$18 ($38)

PORTB

PORTB7

PORTB6

PORTB5

PORTB4

PORTB3

PORTB2

PORTB1

PORTB0

66

$17 ($37)

DDRB

DDB7

DDB6

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0

66

$16 ($36)

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

66

$15 ($35)

PORTC

PORTC7

PORTC6

PORTC5

PORTC4

PORTC3

PORTC2

PORTC1

PORTC0

67

$14 ($34)

DDRC

DDC7

DDC6

DDC5

DDC4

DDC3

DDC2

DDC1

DDC0

67

$13 ($33)

PINC

PINC7

PINC6

PINC5

PINC4

PINC3

PINC2

PINC1

PINC0

67

$12 ($32)

PORTD

PORTD7

PORTD6

PORTD5

PORTD4

PORTD3

PORTD2

PORTD1

PORTD0

67

$11 ($31)

DDRD

DDD7

DDD6

DDD5

DDD4

DDD3

DDD2

DDD1

DDD0

67

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

$10 ($30)

PIND

$0F ($2F)

SPDR

SPI Data Register

67
142

$0E ($2E)

SPSR

SPIF

WCOL

SPI2X

142

$0D ($2D)

SPCR

SPIE

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

140

$0C ($2C)

UDR

$0B ($2B)

UCSRA

USART I/O Data Register

163

$0A ($2A)

UCSRB

$09 ($29)

UBRRL

$08 ($28)

ACSR

ACD

ACBG

$07 ($27)

ADMUX

REFS1

$06 ($26)

ADCSRA

ADEN

$05 ($25)

ADCH

ADC Data Register High Byte

220

$04 ($24)

ADCL

ADC Data Register Low Byte

220

$03 ($23)

TWDR

Two-wire Serial Interface Data Register

$02 ($22)

TWAR

RXC

TXC

UDRE

FE

DOR

PE

U2X

MPCM

164

RXCIE

TXCIE

UDRIE

RXEN

TXEN

UCSZ2

RXB8

TXB8

165

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

202

REFS0

ADLAR

MUX4

MUX3

MUX2

MUX1

MUX0

217

ADSC

ADATE

ADIF

ADIE

ADPS2

ADPS1

ADPS0

219

USART Baud Rate Register Low Byte

TWA6

TWA5

TWA4

167

182
TWA3

TWA2

TWA1

TWA0

TWGCE

182

7
2466TSAVR07/10

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$01 ($21)

TWSR

TWS7

TWS6

TWS5

TWS4

TWS3

TWPS1

TWPS0

181

$00 ($20)

TWBR

Notes:

Two-wire Serial Interface Bit Rate Register

180

1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register.
2. Refer to the USART description for details on how to access UBRRH and UCSRC.
3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
4. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.

ATmega16(L)
2466TSAVR07/10

ATmega16(L)
Instruction Set Summary
Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS


ADD

Rd, Rr

Add two Registers

Rd Rd + Rr

Z,C,N,V,H

ADC

Rd, Rr

Add with Carry two Registers

Rd Rd + Rr + C

Z,C,N,V,H

ADIW

Rdl,K

Add Immediate to Word

Rdh:Rdl Rdh:Rdl + K

Z,C,N,V,S

SUB

Rd, Rr

Subtract two Registers

Rd Rd - Rr

Z,C,N,V,H

SUBI

Rd, K

Subtract Constant from Register

Rd Rd - K

Z,C,N,V,H

SBC

Rd, Rr

Subtract with Carry two Registers

Rd Rd - Rr - C

Z,C,N,V,H

SBCI

Rd, K

Subtract with Carry Constant from Reg.

Rd Rd - K - C

Z,C,N,V,H

SBIW

Rdl,K

Subtract Immediate from Word

Rdh:Rdl Rdh:Rdl - K

Z,C,N,V,S

2
1

AND

Rd, Rr

Logical AND Registers

Rd Rd Rr

Z,N,V

ANDI

Rd, K

Logical AND Register and Constant

Rd Rd K

Z,N,V

OR

Rd, Rr

Logical OR Registers

Rd Rd v Rr

Z,N,V

ORI

Rd, K

Logical OR Register and Constant

Rd Rd v K

Z,N,V

EOR

Rd, Rr

Exclusive OR Registers

Rd Rd Rr

Z,N,V

COM

Rd

Ones Complement

Rd $FF Rd

Z,C,N,V

NEG

Rd

Twos Complement

Rd $00 Rd

Z,C,N,V,H

SBR

Rd,K

Set Bit(s) in Register

Rd Rd v K

Z,N,V

CBR

Rd,K

Clear Bit(s) in Register

Rd Rd ($FF - K)

Z,N,V

INC

Rd

Increment

Rd Rd + 1

Z,N,V

DEC

Rd

Decrement

Rd Rd 1

Z,N,V

TST

Rd

Test for Zero or Minus

Rd Rd Rd

Z,N,V

CLR

Rd

Clear Register

Rd Rd Rd

Z,N,V

SER

Rd

Set Register

Rd $FF

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 Rd x Rr

Z,C

MULS

Rd, Rr

Multiply Signed

R1:R0 Rd x Rr

Z,C

MULSU

Rd, Rr

Multiply Signed with Unsigned

R1:R0 Rd x Rr

Z,C

FMUL

Rd, Rr

Fractional Multiply Unsigned

R1:R0 (Rd x Rr) <<

Z,C

FMULS

Rd, Rr

Fractional Multiply Signed

Z,C

FMULSU

Rd, Rr

Fractional Multiply Signed with Unsigned

1
R1:R0 (Rd x Rr) << 1
R1:R0 (Rd x Rr) << 1

Z,C

Relative Jump

PC PC + k + 1

None

Indirect Jump to (Z)

PC Z

None

2
3

BRANCH INSTRUCTIONS
RJMP

IJMP
JMP

Direct Jump

PC k

None

RCALL

Relative Subroutine Call

PC PC + k + 1

None

Indirect Call to (Z)

PC Z

None

ICALL

Direct Subroutine Call

PC k

None

RET

Subroutine Return

PC STACK

None

RETI

Interrupt Return

PC STACK

if (Rd = Rr) PC PC + 2 or 3

None

CALL

CPSE

Rd,Rr

Compare, Skip if Equal

1/2/3

CP

Rd,Rr

Compare

Rd Rr

Z, N,V,C,H

CPC

Rd,Rr

Compare with Carry

Rd Rr C

Z, N,V,C,H

CPI

Rd,K

Compare Register with Immediate

Rd K

Z, N,V,C,H

SBRC

Rr, b

Skip if Bit in Register Cleared

if (Rr(b)=0) PC PC + 2 or 3

None

1
1/2/3

SBRS

Rr, b

Skip if Bit in Register is Set

if (Rr(b)=1) PC PC + 2 or 3

None

1/2/3

SBIC

P, b

Skip if Bit in I/O Register Cleared

if (P(b)=0) PC PC + 2 or 3

None

1/2/3

SBIS

P, b

Skip if Bit in I/O Register is Set

if (P(b)=1) PC PC + 2 or 3

None

1/2/3

BRBS

s, k

Branch if Status Flag Set

if (SREG(s) = 1) then PCPC+k + 1

None

1/2

BRBC

s, k

Branch if Status Flag Cleared

if (SREG(s) = 0) then PCPC+k + 1

None

1/2

BREQ

Branch if Equal

if (Z = 1) then PC PC + k + 1

None

1/2

BRNE

Branch if Not Equal

if (Z = 0) then PC PC + k + 1

None

1/2

BRCS

Branch if Carry Set

if (C = 1) then PC PC + k + 1

None

1/2

BRCC

Branch if Carry Cleared

if (C = 0) then PC PC + k + 1

None

1/2

BRSH

Branch if Same or Higher

if (C = 0) then PC PC + k + 1

None

1/2

BRLO

Branch if Lower

if (C = 1) then PC PC + k + 1

None

1/2

BRMI

Branch if Minus

if (N = 1) then PC PC + k + 1

None

1/2

BRPL

Branch if Plus

if (N = 0) then PC PC + k + 1

None

1/2

BRGE

Branch if Greater or Equal, Signed

if (N V= 0) then PC PC + k + 1

None

1/2

BRLT

Branch if Less Than Zero, Signed

if (N V= 1) then PC PC + k + 1

None

1/2

BRHS

Branch if Half Carry Flag Set

if (H = 1) then PC PC + k + 1

None

1/2

BRHC

Branch if Half Carry Flag Cleared

if (H = 0) then PC PC + k + 1

None

1/2

BRTS

Branch if T Flag Set

if (T = 1) then PC PC + k + 1

None

1/2

BRTC

Branch if T Flag Cleared

if (T = 0) then PC PC + k + 1

None

1/2

BRVS

Branch if Overflow Flag is Set

if (V = 1) then PC PC + k + 1

None

1/2

BRVC

Branch if Overflow Flag is Cleared

if (V = 0) then PC PC + k + 1

None

1/2

9
2466TSAVR07/10

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRIE

Branch if Interrupt Enabled

if ( I = 1) then PC PC + k + 1

None

1/2

BRID

Branch if Interrupt Disabled

if ( I = 0) then PC PC + k + 1

None

1/2

None

None

DATA TRANSFER INSTRUCTIONS


MOV

Rd, Rr

Move Between Registers

MOVW

Rd, Rr

Copy Register Word

Rd Rr
Rd+1:Rd Rr+1:Rr

LDI

Rd, K

Load Immediate

Rd K

None

LD

Rd, X

Load Indirect

Rd (X)

None

LD

Rd, X+

Load Indirect and Post-Inc.

Rd (X), X X + 1

None

LD

Rd, - X

Load Indirect and Pre-Dec.

X X - 1, Rd (X)

None

2
2

LD

Rd, Y

Load Indirect

Rd (Y)

None

LD

Rd, Y+

Load Indirect and Post-Inc.

Rd (Y), Y Y + 1

None

LD

Rd, - Y

Load Indirect and Pre-Dec.

Y Y - 1, Rd (Y)

None

LDD

Rd,Y+q

Load Indirect with Displacement

Rd (Y + q)

None

LD

Rd, Z

Load Indirect

Rd (Z)

None

LD

Rd, Z+

Load Indirect and Post-Inc.

Rd (Z), Z Z+1

None

LD

Rd, -Z

Load Indirect and Pre-Dec.

Z Z - 1, Rd (Z)

None

LDD

Rd, Z+q

Load Indirect with Displacement

Rd (Z + q)

None

2
2

LDS

Rd, k

Load Direct from SRAM

Rd (k)

None

ST

X, Rr

Store Indirect

(X) Rr

None

ST

X+, Rr

Store Indirect and Post-Inc.

(X) Rr, X X + 1

None

ST

- X, Rr

Store Indirect and Pre-Dec.

X X - 1, (X) Rr

None

ST

Y, Rr

Store Indirect

(Y) Rr

None

ST

Y+, Rr

Store Indirect and Post-Inc.

(Y) Rr, Y Y + 1

None

ST

- Y, Rr

Store Indirect and Pre-Dec.

Y Y - 1, (Y) Rr

None

STD

Y+q,Rr

Store Indirect with Displacement

(Y + q) Rr

None

ST

Z, Rr

Store Indirect

(Z) Rr

None

ST

Z+, Rr

Store Indirect and Post-Inc.

(Z) Rr, Z Z + 1

None

ST

-Z, Rr

Store Indirect and Pre-Dec.

Z Z - 1, (Z) Rr

None

STD

Z+q,Rr

Store Indirect with Displacement

(Z + q) Rr

None

STS

k, Rr

Store Direct to SRAM

(k) Rr

None

Load Program Memory

R0 (Z)

None

LPM
LPM

Rd, Z

Load Program Memory

Rd (Z)

None

LPM

Rd, Z+

Load Program Memory and Post-Inc

Rd (Z), Z Z+1

None

Store Program Memory

(Z) R1:R0

None

In Port

Rd P

None

SPM
IN

Rd, P

OUT

P, Rr

Out Port

P Rr

None

PUSH

Rr

Push Register on Stack

STACK Rr

None

POP

Rd

Pop Register from Stack

Rd STACK

None

BIT AND BIT-TEST INSTRUCTIONS


SBI

P,b

Set Bit in I/O Register

I/O(P,b) 1

None

CBI

P,b

Clear Bit in I/O Register

I/O(P,b) 0

None

LSL

Rd

Logical Shift Left

Rd(n+1) Rd(n), Rd(0) 0

Z,C,N,V

LSR

Rd

Logical Shift Right

Rd(n) Rd(n+1), Rd(7) 0

Z,C,N,V

ROL

Rd

Rotate Left Through Carry

Rd(0)C,Rd(n+1) Rd(n),CRd(7)

Z,C,N,V

ROR

Rd

Rotate Right Through Carry

Rd(7)C,Rd(n) Rd(n+1),CRd(0)

Z,C,N,V

ASR

Rd

Arithmetic Shift Right

Rd(n) Rd(n+1), n=0..6

Z,C,N,V

SWAP

Rd

Swap Nibbles

Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0)

None

BSET

Flag Set

SREG(s) 1

SREG(s)

BCLR

Flag Clear

SREG(s) 0

SREG(s)

BST

Rr, b

Bit Store from Register to T

T Rr(b)

BLD

Rd, b

Bit load from T to Register

Rd(b) T

None

1
1

SEC

Set Carry

C1

CLC

Clear Carry

C0

SEN

Set Negative Flag

N1

CLN

Clear Negative Flag

N0

SEZ

Set Zero Flag

Z1

CLZ

Clear Zero Flag

Z0

SEI

Global Interrupt Enable

I1

CLI

Global Interrupt Disable

I0

1
1

SES

Set Signed Test Flag

S1

CLS

Clear Signed Test Flag

S0

SEV

Set Twos Complement Overflow.

V1

CLV
SET
CLT
SEH

Clear Twos Complement Overflow


Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG

V0
T1
T0
H1

V
T
T
H

1
1
1
1

10

ATmega16(L)
2466TSAVR07/10

ATmega16(L)
Mnemonics

Operands

CLH
MCU CONTROL INSTRUCTIONS
NOP
SLEEP
WDR
BREAK

Flags

Description

Operation

Clear Half Carry Flag in SREG

H0

No Operation
Sleep
Watchdog Reset
Break

(see specific descr. for Sleep function)


(see specific descr. for WDR/timer)
For On-Chip Debug Only

None
None
None
None

#Clocks
1
1
1
1
N/A

11
2466TSAVR07/10

Ordering Information
Speed (MHz)

Note:

Power Supply

Ordering Code

Package
44A
40P6
44M1

Industrial
(-40oC to 85oC)

44A
40P6
44M1

Industrial
(-40oC to 85oC)

2.7V - 5.5V

ATmega16L-8AU(1)
ATmega16L-8PU(1)
ATmega16L-8MU(1)

16

4.5V - 5.5V

ATmega16-16AU(1)
ATmega16-16PU(1)
ATmega16-16MU(1)

Operation Range

1. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.

Package Type
44A

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40P6

40-pin, 0.600 Wide, Plastic Dual Inline Package (PDIP)

44M1

44-pad, 7 7 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

12

ATmega16(L)
2466TSAVR07/10

ATmega16(L)
Packaging Information
44A

PIN 1
B
PIN 1 IDENTIFIER

E1

D1
D
C

0~7
A1

A2

L
COMMON DIMENSIONS
(Unit of Measure = mm)

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ACB.


2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.

SYMBOL

MIN

NOM

MAX

1.20

A1

0.05

0.15

A2

0.95

1.00

1.05

11.75

12.00

12.25

D1

9.90

10.00

10.10

11.75

12.00

12.25

E1

9.90

10.00

10.10

0.30

0.45

0.09

0.20

0.45

0.75

NOTE

Note 2

Note 2

0.80 TYP

10/5/2001

2325 Orchard Parkway


San Jose, CA 95131

TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

DRAWING NO.

REV.

44A

13
2466TSAVR07/10

40P6

PIN
1

E1

SEATING PLANE

A1

L
B

B1
e
E

0 ~ 15

C
eB

Notes:

COMMON DIMENSIONS
(Unit of Measure = mm)

REF

1. This package conforms to JEDEC reference MS-011, Variation AC.


2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

SYMBOL

MIN

NOM

MAX

4.826

A1

0.381

52.070

52.578

15.240

15.875

E1

13.462

13.970

0.356

0.559

B1

1.041

1.651

3.048

3.556

0.203

0.381

eB

15.494

17.526

NOTE

Note 2

Note 2

2.540 TYP

09/28/01

14

2325 Orchard Parkway


San Jose, CA 95131

TITLE
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)

DRAWING NO.
40P6

REV.
B

ATmega16(L)
2466TSAVR07/10

ATmega16(L)
44M1

Marked Pin# 1 ID

SEATING PLANE

A1

TOP VIEW

A3
A

K
L

Pin #1 Corner

D2

1
2
3

Option A

SIDE VIEW

Pin #1
Triangle

E2
Option B

Option C

Pin #1
Chamfer
(C 0.30)

Pin #1
Notch
(0.20 R)

BOTTOM VIEW

COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL

MIN

NOM

MAX

0.80

0.90

1.00

A1

0.02

0.05

A3

0.20 REF

0.18

0.23

0.30

6.90

7.00

7.10

D2

5.00

5.20

5.40

6.90

7.00

7.10

E2

5.00

5.20

5.40

e
Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.

NOTE

0.50 BSC

0.59

0.64

0.69

0.20

0.26

0.41

9/26/08
Package Drawing Contact:
packagedrawings@atmel.com

TITLE
44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead
Pitch 0.50 mm, 5.20 mm Exposed Pad, Thermally
Enhanced Plastic Very Thin Quad Flat No
Lead Package (VQFN)

GPC
ZWS

DRAWING NO.

REV.

44M1

15
2466TSAVR07/10

Errata

The revision letter in this section refers to the revision of the ATmega16 device.

ATmega16(L) Rev.
M

First Analog Comparator conversion may be delayed


Interrupts may be lost when writing the timer registers in the asynchronous timer
IDCODE masks data from TDI input
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed


If the device is powered by a slow rising VCC, the first Analog Comparator conversion will
take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronized to the asynchronous timer
clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00.
Problem Fix / Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous
Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx).
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.
Problem Fix / Workaround

If ATmega16 is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or
by entering the Test-Logic-Reset state of the TAP controller to read out the contents
of its Device ID Register and possibly data from succeeding devices of the scan
chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID
Registers of preceding devices of the boundary scan chain.

If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega16 must be the fist device in the chain.

4. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.

ATmega16(L) Rev.
L

First Analog Comparator conversion may be delayed


Interrupts may be lost when writing the timer registers in the asynchronous timer
IDCODE masks data from TDI input
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed


If the device is powered by a slow rising VCC, the first Analog Comparator conversion will
take longer than expected on some devices.
16

ATmega16(L)
2466TSAVR07/10

ATmega16(L)
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronized to the asynchronous timer
clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00.
Problem Fix / Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous
Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx).
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.
Problem Fix / Workaround

If ATmega16 is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or
by entering the Test-Logic-Reset state of the TAP controller to read out the contents
of its Device ID Register and possibly data from succeeding devices of the scan
chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID
Registers of preceding devices of the boundary scan chain.

If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega16 must be the fist device in the chain.

4. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.

ATmega16(L) Rev.
K

First Analog Comparator conversion may be delayed


Interrupts may be lost when writing the timer registers in the asynchronous timer
IDCODE masks data from TDI input
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed


If the device is powered by a slow rising VCC, the first Analog Comparator conversion will
take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronized to the asynchronous timer
clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00.

17
2466TSAVR07/10

Problem Fix / Workaround


Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous
Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx).
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.
Problem Fix / Workaround

If ATmega16 is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or
by entering the Test-Logic-Reset state of the TAP controller to read out the contents
of its Device ID Register and possibly data from succeeding devices of the scan
chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID
Registers of preceding devices of the boundary scan chain.

If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega16 must be the fist device in the chain.

4. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.

ATmega16(L) Rev.
J

First Analog Comparator conversion may be delayed


Interrupts may be lost when writing the timer registers in the asynchronous timer
IDCODE masks data from TDI input
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed


If the device is powered by a slow rising VCC, the first Analog Comparator conversion will
take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronized to the asynchronous timer
clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00.
Problem Fix / Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous
Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx).
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.

18

ATmega16(L)
2466TSAVR07/10

ATmega16(L)
Problem Fix / Workaround

If ATmega16 is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or
by entering the Test-Logic-Reset state of the TAP controller to read out the contents
of its Device ID Register and possibly data from succeeding devices of the scan
chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID
Registers of preceding devices of the boundary scan chain.

If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega16 must be the fist device in the chain.

4. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.

ATmega16(L) Rev.
I

First Analog Comparator conversion may be delayed


Interrupts may be lost when writing the timer registers in the asynchronous timer
IDCODE masks data from TDI input
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed


If the device is powered by a slow rising VCC, the first Analog Comparator conversion will
take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronized to the asynchronous timer
clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00.
Problem Fix / Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous
Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx).
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.
Problem Fix / Workaround

If ATmega16 is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or
by entering the Test-Logic-Reset state of the TAP controller to read out the contents
of its Device ID Register and possibly data from succeeding devices of the scan
chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID
Registers of preceding devices of the boundary scan chain.

If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega16 must be the fist device in the chain.

19
2466TSAVR07/10

4. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.

ATmega16(L) Rev.
H

First Analog Comparator conversion may be delayed


Interrupts may be lost when writing the timer registers in the asynchronous timer
IDCODE masks data from TDI input
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed


If the device is powered by a slow rising VCC, the first Analog Comparator conversion will
take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronized to the asynchronous timer
clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00.
Problem Fix / Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous
Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx).
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.
Problem Fix / Workaround

If ATmega16 is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or
by entering the Test-Logic-Reset state of the TAP controller to read out the contents
of its Device ID Register and possibly data from succeeding devices of the scan
chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID
Registers of preceding devices of the boundary scan chain.

If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega16 must be the fist device in the chain.

4. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.

20

ATmega16(L)
2466TSAVR07/10

ATmega16(L)
Datasheet
Revision
History

Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.

Rev. 2466T-07/10

1.

Corrected use of comma in formula Rp in Table 120, Two-wire Serial Bus Requirements, on page 294.

2.

Updated document according to Atmels Technical Terminology

3. Note 6 and Note 7 under Table 120, Two-wire Serial Bus Requirements, on page 294
have been removed.

Rev. 2466S-05/09

1.

Updated Errata on page 340.

2.

Updated the last page with Atmels new adresses.

Rev. 2466R-06/08

1. Added Not recommended for new designs note in Figure on page 1.

Rev. 2466Q-05/08

1. Updated Fast PWM Mode on page 77 in 8-bit Timer/Counter0 with PWM on page
71:
Removed the last section describing how to achieve a frequency with 50% duty
cycle waveform output in fast PWM mode.
2. Removed note from Feature list in Analog to Digital Converter on page 204.
3. Removed note from Table 84 on page 218.
4. Updated Ordering Information on page 336:
- Commercial ordering codes removed.
- Non Pb-free package option removed.

Rev. 2466P-08/07

1. Updated Features on page 1.


2. Added Data Retention on page 6.
3. Updated Errata on page 340.
4. Updated Slave Mode on page 140.

Rev. 2466O-03/07

1. Updated Calibrated Internal RC Oscillator on page 29.


2. Updated C code example in USART Initialization on page 149.
3. Updated ATmega16 Boundary-scan Order on page 241.
4. Removed premilinary from ADC Characteristics on page 297.
5. Updated from V to mV in I/O Pin Input Hysteresis vs. VCC on page 317.
6. Updated from V to mV in Reset Input Pin Hysteresis vs. VCC on page 318.
21

2466TSAVR07/10

Rev. 2466N-10/06

1. Updated Timer/Counter Oscillator on page 31.


2. Updated Fast PWM Mode on page 102.
3. Updated Table 38 on page 83, Table 40 on page 84, Table 45 on page 111, Table 47 on
page 112, Table 50 on page 128 and Table 52 on page 129.
4. Updated C code example in USART Initialization on page 149.
5. Updated Errata on page 340.

Rev. 2466M-04/06

1. Updated typos.
2. Updated Serial Peripheral Interface SPI on page 135.
3. Updated Table 86 on page 221, Table 116 on page 276 ,Table 121 on page 295 and
Table 122 on page 297.

Rev. 2466L-06/05

1. Updated note in Bit Rate Generator Unit on page 178.


2. Updated values for VINT in ADC Characteristics on page 297.
3. Updated Serial Programming Instruction set on page 276.
4. Updated USART init C-code example in USART on page 144.

Rev. 2466K-04/05

1. Updated Ordering Information on page 336.


2. MLF-package alternative changed to Quad Flat No-Lead/Micro Lead Frame Package
QFN/MLF.
3. Updated Electrical Characteristics on page 291.

Rev. 2466J-10/04

1. Updated Ordering Information on page 336.

Rev. 2466I-10/04

1. Removed references to analog ground.


2. Updated Table 7 on page 28, Table 15 on page 38, Table 16 on page 42, Table 81 on
page 209, Table 116 on page 276, and Table 119 on page 293.
3. Updated Pinout ATmega16 on page 2.
4. Updated features in Analog to Digital Converter on page 204.
5. Updated Version on page 229.
6. Updated Calibration Byte on page 261.
7. Added Page Size on page 262.

Rev. 2466H-12/03

22

1. Updated Calibrated Internal RC Oscillator on page 29.

ATmega16(L)
2466TSAVR07/10

ATmega16(L)
Rev. 2466G-10/03

1. Removed Preliminary from the datasheet.


2. Changed ICP to ICP1 in the datasheet.
3. Updated JTAG Interface and On-chip Debug System on page 36.
4. Updated assembly and C code examples in Watchdog Timer Control Register
WDTCR on page 43.
5. Updated Figure 46 on page 103.
6. Updated Table 15 on page 38, Table 82 on page 217 and Table 115 on page 276.
7. Updated Test Access Port TAP on page 222 regarding JTAGEN.
8. Updated description for the JTD bit on page 231.
9. Added note 2 to Figure 126 on page 252.
10. Added a note regarding JTAGEN fuse to Table 105 on page 260.
11. Updated Absolute Maximum Ratings* and DC Characteristics in Electrical Characteristics on page 291.
12. Updated ATmega16 Typical Characteristics on page 299.
13. Fixed typo for 16 MHz QFN/MLF package in Ordering Information on page 336.
14. Added a proposal for solving problems regarding the JTAG instruction IDCODE in
Errata on page 340.

Rev. 2466F-02/03

1. Added note about masking out unused bits when reading the Program Counter in
Stack Pointer on page 12.
2. Added Chip Erase as a first step in Programming the Flash on page 288 and Programming the EEPROM on page 289.
3. Added the section Unconnected pins on page 55.
4. Added tips on how to disable the OCD system in On-chip Debug System on page
34.
5. Removed reference to the Multi-purpose Oscillator application note and 32 kHz
Crystal Oscillator application note, which do not exist.
6. Added information about PWM symmetry for Timer0 and Timer2.
7. Added note in Filling the Temporary Buffer (Page Loading) on page 253 about writing to the EEPROM during an SPM Page Load.
8. Removed ADHSM completely.

23
2466TSAVR07/10

9. Added Table 73, TWI Bit Rate Prescaler, on page 182 to describe the TWPS bits in
the TWI Status Register TWSR on page 181.
10. Added section Default Clock Source on page 25.
11. Added note about frequency variation when using an external clock. Note added in
External Clock on page 31. An extra row and a note added in Table 118 on page 293.
12. Various minor TWI corrections.
13. Added Power Consumption data in Features on page 1.
14. Added section EEPROM Write During Power-down Sleep Mode on page 22.
15. Added note about Differential Mode with Auto Triggering in Prescaling and Conversion Timing on page 207.
16. Added updated Packaging Information on page 337.

Rev. 2466E-10/02

1. Updated DC Characteristics on page 291.

Rev. 2466D-09/02

1. Changed all Flash write/erase cycles from 1,000 to 10,000.


2. Updated the following tables: Table 4 on page 26, Table 15 on page 38, Table 42 on
page 85, Table 45 on page 111, Table 46 on page 111, Table 59 on page 143, Table 67
on page 167, Table 90 on page 235, Table 102 on page 258, DC Characteristics on
page 291, Table 119 on page 293, Table 121 on page 295, and Table 122 on page 297.
3. Updated Errata on page 340.

Rev. 2466C-03/02

1. Updated typical EEPROM programming time, Table 1 on page 20.


2. Updated typical start-up time in the following tables:
Table 3 on page 25, Table 5 on page 27, Table 6 on page 28, Table 8 on page 29, Table 9
on page 29, and Table 10 on page 29.
3. Updated Table 17 on page 43 with typical WDT Time-out.
4. Added Some Preliminary Test Limits and Characterization Data.
Removed some of the TBD's in the following tables and pages:
Table 15 on page 38, Table 16 on page 42, Table 116 on page 272 (table removed in document review #D), Electrical Characteristics on page 291, Table 119 on page 293, Table
121 on page 295, and Table 122 on page 297.
5. Updated TWI Chapter.
Added the note at the end of the Bit Rate Generator Unit on page 178.
6. Corrected description of ADSC bit in ADC Control and Status Register A ADCSRA
on page 219.
7. Improved description on how to do a polarity check of the ADC doff results in ADC
Conversion Result on page 216.

24

ATmega16(L)
2466TSAVR07/10

ATmega16(L)
8. Added JTAG version number for rev. H in Table 87 on page 229.
9. Added not regarding OCDEN Fuse below Table 105 on page 260.
10. Updated Programming Figures:
Figure 127 on page 262 and Figure 136 on page 273 are updated to also reflect that AVCC
must be connected during Programming mode. Figure 131 on page 269 added to illustrate
how to program the fuses.
11. Added a note regarding usage of the PROG_PAGELOAD ($6) on page 280 and
PROG_PAGEREAD ($7) on page 280.
12. Removed alternative algortihm for leaving JTAG Programming mode.
See Leaving Programming Mode on page 288.
13. Added Calibrated RC Oscillator characterization curves in section ATmega16 Typical Characteristics on page 299.
14. Corrected ordering code for QFN/MLF package (16MHz) in Ordering Information on
page 336.
15. Corrected Table 90, Scan Signals for the Oscillators(1)(2)(3), on page 235.

25
2466TSAVR07/10

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2466TSAVR07/10

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