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8

6

7

REV

SCHEM,MLB,M82
PVT
11/14/2007

ZONE

ECN

ENG
APPD

DESCRIPTION OF CHANGE
DATE

DATE

546198

D

D

(.csa)

Date

Page

Contents
1

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B

1
CK
APPD

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

C

2

3

4

5

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31
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37
38
39
40
41

2
3
4
5
6
7
8
9

Sync
WFERRY-WF

Power Block Diagram

POWER

CONFIGURATION OPTIONS
Acoustic Cap BOM Config Tables
ICT Test Points
Functional Test and No-Tests

(MASTER)

Power Aliases

WFERRY

SIGNAL ALIAS /RESET

eXtended Debug Port (XDP)
NB CPU Interface

(MASTER)

NB PEG / Video Interfaces

M70

16

NB Misc Interfaces
NB DDR2 Interfaces

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

06/15/2006

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

04/26/2006

TABLE_TABLEOFCONTENTS_ITEM

01/24/2007

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

02/01/2007

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

02/01/2007

TABLE_TABLEOFCONTENTS_ITEM

M70

18

NB Power 1

M70

19

NB Power 2

M70

20

NB Grounds

31

(MASTER)

M70

17

30

TABLE_TABLEOFCONTENTS_ITEM

M75

15

29

N/A

MSARWAR

14

28

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)

CPU Decoupling & VID

27

(N/A)

(MASTER)

13

26

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)

CPU Power & Ground

25

06/30/2005

(MASTER)

12

24

TABLE_TABLEOFCONTENTS_ITEM

N/A

CPU FSB

23

05/11/2006

(N/A)

11

22

TABLE_TABLEOFCONTENTS_HEAD

N/A

System Block Diagram

M70

NB Standard Decoupling

M70

NB Graphics Decoupling

M70

SB Enet, Disk, FSB, LPC

M70

SB PCI, PCIe, DMI, USB

M70

SB Pwr Mgt, GPIO, Clink

M70

SB Power & Ground

M70

SB Decoupling

M70

SB Misc

M70

Clock (CK505)

M70

Clock Termination

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

M70

DDR2 DRAM Channel A

(MASTER)

32

DDR2 DRAM Channel B

(MASTER)

33

Memory Active Termination

M70

DDR2 BYPASSING 1

MEMORY

34

Date

Page

N/A

Table of Contents

10

21

(.csa)

42
43
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61
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64
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67
68
69
70
71
72
73

Contents
50
51
52
53
55
56
59
61
69

Sync
01/09/2007

SMC SUPPORT

M70

LPC+SPI Debug Connector

M70

SMBUS CONNECTIONS

M70

Voltage Sensors

M70

TEMPERATURE SENSORS

M70

Fan

M70

Sudden Motion Sensor (SMS)

M76_MLB

SPI ROMs

WFERRY

DC-In & Battery Connectors

M70

S0 FETS & Power Sequencing

M70

IMVP6 CPU VCore Regulator

POWER

Render VCore Supplies

(MASTER)

1.5V/1.05V Supplies

M70

1.8V/0.9V Supplies

M70

5V/3.3V Supplies

M70

3.42V/1.25V Switcher

M70

S3 FET & S3/S5 Control

M70

PBUS Supply/Battery Charger

M70

LVDS,Camera Conn. and ALS Conn.

GPU

SDVO/TMDS Tx

GRAPHIC

01/09/2007
01/09/2007
01/09/2007
01/09/2007
01/09/2007
01/12/2007
04/26/2006
01/09/2007

70

01/09/2007

71

07/13/2005

72

(MASTER)

73

01/09/2007

75

01/09/2007

76

02/01/2007

77

02/01/2007

79

01/09/2007

90

06/23/2006

92
93
94
97
99
100
101
102
103
104
105
108

C

01/09/2007

78

06/06/2005

HDCP uController
01/09/2007

DVI CONNECTIONS

M70

LED Backlight Driver

(MASTER)

(MASTER)

Additional CPU/GPU Decoupling
01/30/2007

CPU/FSB Constraints

T9

NB Constraints

T9

Memory Constraints

T9

SB Constraints (1 of 2)

T9

SB Constraints (2 of 2)

T9

Clock & SMC Constraints

T9

M82 Power and Ground Nets

(MASTER)

M82 Rule Definitions

(MASTER)

01/30/2007
01/30/2007
01/30/2007
01/30/2007
01/30/2007
(MASTER)

109

(MASTER)

B

06/20/2005

35

06/20/2005

DDR2 BYPASSING 2

MEMORY

Wireless M93 Connector

M70

Hatch and Audio Connectors

(MASTER)

PATA HDD CONNECTOR

(MASTER)

USB EXTERNAL CONNECTORS

M70

IPD Connector

M70

SMC

M70

41

01/09/2007

42

(MASTER)

44

(MASTER)

46

01/09/2007

48

01/09/2007

49

01/09/2007

TABLE_TABLEOFCONTENTS_ITEM

ALIASES RESOLVED

A

DIMENSIONS ARE IN MILLIMETERS

APPLE INC.

METRIC

XX
X.XX

DRAFTER

Schematic / PCB #’s
PART NUMBER

QTY

ENG APPD

MFG APPD

QA APPD

DESIGNER

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

RELEASE

SCALE

DESCRIPTION

REFERENCE DES

1

SCHEM,MLB,M82

SCH

CRITICAL

820-2179

1

PCBF,MLB,M82

PCB

CRITICAL

CRITICAL

BOM OPTION

SCHEM,MLB,M82

NONE

DRAWING
ABBREV=DRAWING

THIRD ANGLE PROJECTION

LAST_MODIFIED=Wed Nov 14 17:25:50 2007

7

TITLE

DO NOT SCALE DRAWING

TITLE=M82_MLB

8

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

ANGLES

051-7230

6

A

NOTICE OF PROPRIETARY PROPERTY

DESIGN CK

X.XXX

5

4

3

MATERIAL/FINISH
NOTED AS
APPLICABLE

SIZE

D

2

DRAWING NUMBER

REV.
051-7230

B.0.0
SHT

1

1

OF

73

8

6

7

2

3

4

5

1

U1000

CPU

U2900

SLG2AP101

2.0 GHz
Core ~1.2V
Pg 10

J1300

Pg 9

Clocks

TERMS

Pg 28

Pg 29

MINI XDP CONN
PG 12

D

FSB

DC/Batt

Power

Conn

Supplies

PG 55

PG 55-64

800 MHz

MEM Active
Parallel

Pg 13

U3100
U3110
U3120
U3130
U3140
U3150
U3160
U3170

SDVO

NB-GMCH

TMDS

Core
Pg 14

IPD
U5550

PG 46

U5520

PG 46

HEAT-PIPE/FIN Temp Sensor J5500

PG 46

MLB Temp Sensor

1.8V - 64 Bits

PG 40

DDR2 RAM

CPU Temp Sensor

Misc

LVDS

Pg 17,18,19

Pg 14

SMS

Pg 15

DMI

CLnk 0

Pg 15

Pg 15

PG 48

U3200
U3210
U3220
U3230
U3240
U3250
U3260
U3270

PG 67
PG 67

J9000

U5900 SUDDEN MOTION DETECT PG 48

VOLTAGE SENSORS

DDR2 RAM

U6100

PG 45

J5600
FAN CONN PG 47

SPI

LVDS Int Disp

Pg31

Boot ROM

Conn

C

PG 36

U5900

VGA

MUX
EN_L

Pg 32

DDR2 - Dual Channel

TV

DVI-I

PG 65

M93

U4100
J4800

Pg30

J4200
U9401

TOP ALS

J9050

Term

533/667 MHz

Out

PG 66

1.05 - 1.25V

Pg 15/16

PCI-E

SIL1392

Main Memory

U1400
U9200

D

J6900/50

64-Bit

x4 DMI

C

PG 48

2.5 GHz

PG 65

A

B

0

BSA

MGMT

Fan

ADC

Ser
J5100

Prt

SMC

FrankCard Conn
U4900

SPI

Pg 24

Pg 23

LPC

CLnk 0

Pg 22

DMI
Pg 23

PG 43

PG 41

U2300
J4200

SATA

J4400

Pg 24

GPIOs

Pg 22

J4800

Trackpad/Keyboard

SB-ICH8

HDD PATA

External
USB

Well Spring
PG 40

PG 39

9

Core 1.05V

8

Conn

5
0

PCI-E

B

U2900

Ln5

Core

Pg 24

Clk Gen

SMB

Ln4

Pg 23

Ln3

B

1

Ln2

2

3

4

USB

Ln1

Pg 23

6

7

IDE

Pg 22

PG 38

SLG2AP101

Pg 25

Ln6

E-NET

CLnk 1

PCI

HDA

Pg 22

Pg 24

Pg 23

Pg 22

PG 29

J9050

DIGITAL MIC
CONNECTOR

PG 60

J4260

Audio
Connector
Pg 50

J4100

M93 AirPort/BT

System Block Diagram

Pg 35

A

SYNC_MASTER=WFERRY-WF

SYNC_DATE=05/11/2006

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

DRAWING NUMBER

D
APPLE INC.

SCALE

SHT
NONE

8

7

6

5

4

3

2

REV.

051-7230

B.0.0

OF
2

1

73

A

8

6

7

AC
ADAPTER
IN

M82 POWER SYSTEM ARCHITECTURE

01

6A FUSE
PP18V5_DCIN

=PP18V5_G3H_CHGR

J6980

=PPDCIN_G3H

D6901

PPVBAT_G3H_R

D6901

PPBUSB_G3H

D6901

F6900

02

ENABLES

1

04

SMC_RESET_L

(PAGE 41)
=PPDCIN_G3H

ENABLE

03

3.425V G3HOT
LT1934
U7790

7A FUSE
PPVBAT_G3H_CHGR_REG

SMC PWRGD
RN5VD30A-F
U5000

PP3V42_G3H_SMC

SMC_BATT_CHG_EN

D

2

3

4

5

(? A MAX CURRENT)

(PAGE 62)

R7980

PPBUSB_G3H

PP3V42_G3H_REG

D

=PBUSA_G3H

VOUT

CLOCK

PBUS CONVERTER/
BATTERY

A

BATTERY CHARGER
ISL6258
U7900

2S2P

VIN

02

R7930

SLG2AP101
U2900
(PAGE 28)

VIN

(PAGE 63)

17

1V05S0_RUNSS
(S0)

17

1V5S0_RUNSS
(S0)

CHGR_SMBUS

01

CHGR_BGATE

1.05V
ENA1

PP1V05_S0_REG
(9.9 A MAX CURRENT)

VOUT1

1.5V

ENA2

18
18

LCDBKLT_PLT_RST_L

ICH8M

(3.3 A MAX CURRENT)
CK_PWRGD

TPS51124
U7300
(PAGE 58)

BATT_POS_F

TMDS_RST_L

AIRPORT_RST_L

PP1V5_S0_REG

VOUT2

NB_RESET_L

PWRGD

CLK_PWRGD

Q7950

U2803
VR_PWRGD_CK505

PGOOD_1V5S0

VR_PWRGD_CLKEN

06-1
PWRBTN*

19

PGOOD_1V05S0

U2880

29

VRMPWRGD

PLT_RST_L

PLTRST*
RSMRST*

DELAY

11

Q7860

PM_SB_PWROK

12

R-10K
C-0.002uF

24

P5VS3_EN_L

02

(S3)

(30 A MAX CURRENT)

P3V3S3_EN_L

R-10K
C-0.01uF

(S3)

12

C

U2801

26

VR_PWRGOOD_DELAY

ISL6261CRZ PGOOD
U7100
(PAGE 56)

Q7000

VR_PWRGOOD_DELAY

CPU

PP5V_S0
RESET*

08

PM_S4_STATE_L

TPS79933
VIN
U2280
(PAGE 21)
ENA

P5VS0_EN
Q7865

=PPBUSB_G3H

13

PG2
PG3

?

VOUT

PP5V_S3

U1000
(PAGE 9)

P3V3_S0_NB_TVDAC

(205mA MAX CURRENT)

08

SMC

12

02
06
P60

U4900
(PAGE 40)

07

SMC_PM_G2_EN

(S5)

P5VS3_EN_L
08

VIN

5VS5_RUNSS
(S5)

EN1

5V

VO1

3V3S5_RUNSS
(S5)

EN2

3.3V

VO2

PP5V_S5_REG
(? A MAX CURRENT)

PP5V_S5

PP3V3_S5_REG

07

CRESTLINE

PP3V3_S5

13

Q7866

PP3V3_S3

17

1V25S0_RUNSS

EN
VIN

PWROK

1.25V S0
LTC3412A
U7750

RSMRST_PWRGD

H_CPURST*

U1400
(PAGE 13)

P3V3S3_EN_L

09

U7002

B

22

PP1V25_S0_FET

16

PP5V_S0_NB_GFX_IMVP

PWRGD(P12)

PP3V3_S0

09

99ms DLY

GCORE_EN

EN

ADP3209
U7200 VOUT
(PAGE 57)

20

21

=PPVCORE_S0_NB_GFX_IMVP

P3V3S0_EN

RSMRST_IN(P13)

PWR_BUTTON(P90)

PGOOD_1V5S0
PGOOD_1V05S0

BATTERY ONLY:

PGOOD_SEQUENCER

ADAPTER IN

(13 A MAX CURRENT)

05

PM_WLAN_EN_L

:

23

SMC_LRESET_L
PM_PWRBTN_L

P17(BTN_OUT)

RST*

15

WOW_EN

PLT_RST*

SMC_ONOFF_L

15

IMVP_VR_ON

IMVP_VR_ON(P16)

RSMRST_PWRGD

VIN

B

PM_RSMRST_L

RSMRST_OUT(P15)

ALL_SYS_PWRGD_AND

VCC

10
SMC

ALL_SYS_PWRGD

Q7001

04

GFX_VR_EN

FSB_CPURST_L

18
PP1V25_S0_REG
(3 A MAX CURRENT)

VOUT

(PAGE 61)

PGOOD1,2

GPU_VCORE

30

(? A MAX CURRENT)
08

TPS51120
U7600
(PAGE 60)

SMC_ADAPTER_PRESENT

C

PWRGOOD

16

PPBUS_G3H

ICH

PM_SLP_S3_L

28

U2300
(PAGE 22)

VR_ON

23

CPU_PWRGD(GPIO49)

25

VR_PWRGD_CK505_L

CLKEN#

IMVP_VR_ON

CPU_PWRGD

PWROK

PPVCORE_S0_CPU

VOUT

VIN

DELAY

PPVCORE_S0_CPU_REG

CPUVCORE

SMC_RESET_L

10-1

19
PM_SLP_S5_L

14
=PP1V8_S0_FET

PP1V8_S3_FET

16

PM_SLP_S3_L

=PP1V8_S0_NB_DPLL

PP1V8_S3_REG

VIN

P1V8S0_EN
12
R7870

PM_SLP_S3_L
Q7006

A

Q7007

RUNSS_GATE_D

R-330
C-0.022uF

1V5S0_RUNSS
(S0)

17

15
Q7006

Q7007

S5
S3

VLDOIN

1.8V
VOUT1

0.9V

VOUT2

TPS51116
U7500
(PAGE 59)

VOUT

1V05S0_RUNSS
(S0)

U4900
(PAGE 40)

P1V25_S0_NB_DPLL

U7000
GATE A
ISL6130IRZA

PP0V9_S0_REG

RST*

18
PGOOD_1V8S3

PGOOD_1V8S3

17

Q7006

DELAY

UVLO_B

PP3V3_S0_FET

UVLO_C

R-330
C-1000PF

1V25S0_RUNSS
(S0)

PM_SLP_S3_L
17

P5VS0_EN

UVLO)D

GATE B
GATE C
GATE D

Power Block Diagram

15

SYNC_MASTER=POWER

P3V3S0_EN
UVLO_A

PP5V_S0_FET

PP1V8_S0_FET
Q7006

SLP_S3_L(P93)

18

PP1V8_S3_REG
(11 A MAX CURRENT)

DELAY
R-330
C-0.01uF

MCH DPLL
TPS731125
U2265
(PAGE 21)

SLP_S4_L(P94)

13

14

DELAY

ENA

15
VIN

1V8S3_RUNSS

SLP_S5_L(P95)

PM_S4_STATE_L

Q7004

P1V8S0_EN
RUNSS_GATE_D

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

15

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

15

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

ENABLE_1

SIZE

(PAGE 56)

14

SYNC_DATE=06/30/2005

NOTICE OF PROPRIETARY PROPERTY

15

DRAWING NUMBER

D
APPLE INC.

SCALE

SHT
NONE

8

7

6

5

4

3

2

REV.

051-7230

B.0.0

OF
3

1

73

A

MI 2GB.8GHZ.M82_TY_CAP TABLE_BOMGROUP_ITEM Module Parts PART NUMBER Bar Code Label / EEE #’s PART NUMBER C QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION QTY DESCRIPTION REFERENCE DES CRITICAL 337S3522 1 IC.SANTAYNEZ.SS CAP.M82_COMMON.8x13 U3240.8GHZ.MLB.MLB.965GM.6GHZ.6GHZ.1.M82_HYNIX.PRQ.CPU_PRQ_1_6GHZ.PAGE_BORDER=TRUE 8 6 7 BOMs 2 3 4 5 1 BOMOPTION Groups TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS M82_COMMON ALTERNATE.U3260.MEROM.28MM X 6 MM [EEE:ZUA] CRITICAL EEE_ZUA 341S2173 1 IC.DRAM.M82_HYNIX.28MM X 6 MM [EEE:ZU8] CRITICAL EEE_ZU8 826-4393 1 LBL.LP U3140.8x12.8GHZ.M82_COMMON.LPCPLUS.M82_SS_CAP TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9134 PCBA.8x13.PCB.MLB.ES.PCB.U3210.M82_MU_CAP 630-9207 PCBA.64M16.U3160.U3150.5A OC FUSE 104S0018 ALL 1206 1/4W .M82_HYNIX.DRAM_SPD_1 M82_HYNIX DRAM_HYNIX.SS CAP.8x13.ICH8M. 2.1. 32MBIT 8-PIN SERIAL FLASH.64M16.M82_COMMON.PRQ.MI 2GB.64M16.M82_MICRON.64M16.UCNTRLR.M82_MICRON.TY_CAP_10UF TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9208 PCBA.0 Y9390 CRITICAL SST8051_20MHZ B 197S0257 1 33MHZ XTAL.M82_COMMON.8GHZ. 2.SMC (NEW).MLB.PCB.CPU_PRQ_1_8GHZ.U3220.M82_MU_CAP TABLE_BOMGROUP_ITEM M82_COMMON3 TABLE_BOMGROUP_ITEM D DRAM_MICRON.M82 EEE_ZU9.SS_CAP_10UF M82_MU_CAP MU_CAP_1UF.MU CAP.U3120.CPU_PRQ_1_6GHZ.HY 2GB.DRAM.REV2.M82 U6100 CRITICAL BOOTROM_FINAL 826-4393 1 LBL.U3120.DRAM.1.U3270 CRITICAL DRAM_HYNIX 333S0415 4 HYNIX.M82_HYNIX.M82_COMMON2.M82_COMMON.MI 2GB.USFF BGA U2300 CRITICAL 826-4393 1 LBL.U3160.1.REV3.0 OF 4 1 73 A .5x2.SLG2AP101.LP U3240.XDP.M82 EEE_ZUC.CPU_PRQ_1_6GHZ.M82_SS_CAP TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9133 PCBA.PRGM.P/N LABEL.PCB.1.5 U3240.M82 EEE_Z81.DRAM_2GB TABLE_BOMGROUP_ITEM 630-7886 PCBA.CPU_PRQ_1_6GHZ.MEROM.U3270 CRITICAL DRAM_HYNIX_LP 353S1938 1 IC.M82_MICRON.COMMON.BOOTROM DEVELOPMENT (UNLOCKED).TY CAP.U3210.U3230 CRITICAL DRAM_MICRON 333S0406 4 MICRON.MU CAP.PRQ.U3130 CRITICAL DRAM_HYNIX 333S0411 4 HYNIX.M82_MICRON.U3120.1.28MM X 6 MM [EEE:YMS] CRITICAL EEE_YMS 338S0420 1 826-4393 1 LBL.28MM X 6 MM [EEE:ZUB] CRITICAL EEE_ZUB 338S0422 1 IC.REV3.1.M82 EEE_ZUA.CRESTLINE.20W.HY 2GB.956BGA U1000 CRITICAL BOM OPTION CPU_1_6GHZ 1 IC.HY 2GB.64M16.6GHZ.28MM X 6 MM [EEE:Z80] CRITICAL EEE_Z80 338S0421 1 IC.M82_TY_CAP TABLE_BOMGROUP_ITEM M82_HYNIX_LP DRAM_HYNIX_LP.U3110.U3170 CRITICAL DRAM_HYNIX 333S0411 4 HYNIX.MEROM.P/N LABEL.M82 EEE_ZU5. INC.M82 EEE_ZU6.P/N LABEL.6GHZ.64M16.USFF BGA U1400 CRITICAL NB_PRQ 338S0515 1 IC.M82_COMMON.8x13 U3200.ISL6258.20W.PCB.1.U3210.8x13 U3140.M82_COMMON1.EFI.PCB.0.5x2.CPU_PRQ_1_8GHZ.28MM X 6 MM [EEE:ZU6] CRITICAL EEE_ZU6 826-4393 1 LBL.TY CAP.LP U3100.U3220.U3260.CPU_PRQ_1_8GHZ.M82 EEE_XSC.U3220.M82 U9300 CRITICAL SST8051_PRGRM 826-4393 1 LBL.BOOTROM FINAL (LOCKED).M82_MICRON.DRAM.SMC_PRGRM M82_COMMON2 SMS_MOT_DIS.ICH8M.TY CAP.CPU_PRQ_1_8GHZ.MEROM.U3250.U3270 CRITICAL DRAM_MICRON 333S0411 4 HYNIX.M82 EEE_ZU7.U3130 CRITICAL DRAM_MICRON 333S0406 4 MICRON.SANTAYNEZ.PCB.DRAM_SPD_2 M82_SS_CAP SS_CAP_1UF.M82_COMMON.HY 2GB.6GHZ.SS_CAP_2_2UF.64M16.8GHZ. 2.002 OHM BOM OPTION CONFIGURATION OPTIONS A SYNC_MASTER=(N/A) SYNC_DATE=(N/A) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.318MHZ XTAL.8x12.1.U3250.P/N LABEL.M82_MICRON.M82_COMMON3 M82_COMMON1 ISL6258.M82 U6100 CRITICAL BOOTROM_DEVEL 341S2112 1 IC.8x13.8GHZ. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.64M16.0 Y9390 CRITICAL SST8051_14MHZ 197S0231 1 20MHZ XTAL.U3110.CPU_PRQ_1_6GHZ.28MM X 6 MM [EEE:ZU9] CRITICAL EEE_ZU9 337S3477 1 SST89V54RD MICROCONTROLLER U9300 CRITICAL SST8051_BLANK 826-4393 1 LBL.HS8/2117 U4900 CRITICAL SMC_BLANK 826-4393 1 LBL.CPU_PRQ_1_8GHZ.8GHZ.ES.U3150.MI 2GB.CPU_PRQ_1_6GHZ.64M16.DRAM.P/N LABEL.U3150.M82_TY_CAP TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9206 PCBA.U3130 CRITICAL DRAM_HYNIX_LP 333S0415 4 HYNIX.P/N LABEL. 16MBIT 8-PIN SERIAL FLASH.MLB.5x2.MI 2GB.1.965GM.DRAM_SPD_2 TABLE_BOMGROUP_ITEM 630-9205 PCBA.USFF BGA U1400 CRITICAL 826-4393 1 LBL.M82_SS_CAP TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9024 PCBA.M82_COMMON.M82_COMMON.5 U3140.6GHZ.M82_COMMON.SANTAYNEZ.8x12.8x13 U3100.28MM X 6 MM [EEE:XSC] CRITICAL EEE_XSC 337S3523 826-4393 1 LBL.P/N LABEL.SS CAP.U3250.U3110.M82_COMMON.M82 EEE_Z80.28MM X 6 MM [EEE:ZUC] CRITICAL EEE_ZUC 341S2115 1 IC.M82_HYNIX.U3230 CRITICAL DRAM_HYNIX_LP 333S0415 4 HYNIX.SS CAP.28MM X 6 MM [EEE:ZU7] CRITICAL EEE_ZU7 826-4393 1 LBL.64M16.1.PRGRM.956BGA U1000 CRITICAL CPU_PRQ_1_6GHZ 337S3564 1 IC.1.U3170 CRITICAL DRAM_MICRON 333S0406 4 MICRON.PCB.M82_TY_CAP D TABLE_BOMGROUP_ITEM M82_MICRON TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9210 PCBA.U3230 CRITICAL DRAM_HYNIX 333S0411 4 HYNIX.MLB.M82_COMMON.MLB.EFI.DRAM.VWQPN U6100 CRITICAL BOOTROM_BLANK_2MB 335S0509 1 IC.SMC.M82_SS_CAP 630-9204 PCBA.P/N LABEL.M82 EEE_YMS.64M16.1.1.1.20W.956BGA U1000 CRITICAL CPU_1_8GHZ IC.TY CAP.M82_HYNIX.DRAM.CPU_PRQ_1_8GHZ.M82_MU_CAP 630-9211 PCBA. 28P QFN U7900 CRITICAL ISL6258 197S0213 1 14.M82 U4900 CRITICAL SMC_PRGRM 333S0406 4 MICRON.M82_MU_CAP TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9209 PCBA.8x13.MLB.6GHZ.64M16.CRESTLINE.20W.MI 2GB.5 U3200.P/N LABEL.MU CAP.PCB.LP U3200.MU_CAP_10UF M82_TY_CAP TY_CAP_1UF.P/N LABEL.0 Y9390 CRITICAL SST8051_33MHZ 337S3563 1 IC.8x12.MLB.28MM X 6 MM [EEE:Z81] CRITICAL EEE_Z81 359S0130 1 LOW POWER CLOCK SYNTHESIZER.SANTAYNEZ.1.MU_CAP_2_2UF.TY_CAP_2_2UF.BOOTROM_DEVEL.PCB.28MM X 6 MM [EEE:ZU5] CRITICAL EEE_ZU5 335S0510 1 IC.U3260.HY 2GB.SST SST89V54RD.5 U3100.DRAM.MLB.PCB.BAT CHGR.8GHZ.P/N LABEL.U3160.DRAM.M82 EEE_ZU8.6GHZ.DRAM.PRQ.956BGA U1000 CRITICAL CPU_PRQ_1_8GHZ 338S0514 1 IC.68PIN U2900 CRITICAL 826-4393 1 LBL. 051-7230 B.DRAM. SCALE SHT NONE 8 7 6 5 4 3 2 REV.U3170 CRITICAL DRAM_HYNIX_LP 333S0415 4 HYNIX.USFF BGA U2300 CRITICAL SB_PRQ C B Alternate Parts 128S0093 ALTERNATE FOR PART NUMBER 128S0092 376S0466 740S0044 104S0023 PART NUMBER REFERENCE DESIGNATOR(S) DESCRIPTION ALL 33UF 20% 16V DCASE 376S0410 ALL Si4413 for Si4405 740S0028 ALL 0. WSON8 U6100 CRITICAL BOOTROM_BLANK_4MB 341S2111 1 IC.PCB.MLB.DRAM.M82 EEE_ZUB.HY 2GB.MLB.MU CAP.P/N LABEL.

C2215. 20%.C3530. 20%. 2. 6.C1241.C3501.3V. 10UF.C2600.C1252.C9994. 6. 6.C1267 CRITICAL SS_CAP_2_2UF 138S0633 6 CAP.C3412.2UF. 6.2UF.C1293. 0402 C2214.C9986.C3534. 6.8 6 7 2 3 4 5 1 1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS SAMSUNG PART NUMBER D MURATA QTY DESCRIPTION REFERENCE DES 138S0629 5 CAP.C9902.C9909 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP.C1249 REFERENCE DES CRITICAL CRITICAL MU_CAP_2_2UF 138S0634 10 CAP. 0402 C1240.3V.C9921. 10UF.C3404.C1212.C9938. 10UF.C3512.3V.C1229 138S0626 3 CAP.C3591.C9996.C3405.C9989 CRITICAL SS_CAP_2_2UF 138S0633 8 CAP.C9928.C2900.C9927.C2243 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP. 0402 C9990.3V. 0402 C9920.C3421.3V.C3510. 6.2UF.C3401.C3511.3V. 10UF.C7301.C7541.C1212.3V.C1216.C9922.C3445.C3516 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP.C1295.C9918.C1624. 6.2UF. 6.C3401.C7281.C1202. 2.C3555 BOM OPTION QTY DESCRIPTION CRITICAL MU_CAP_2_2UF PART NUMBER 138S0634 10 CAP. 6.3V.C2735.C3554. 1UF. 0402 C3542.C3535.3V. 0603 C1200.C9935.C2280.C2280.C1294.C1224.3V.2UF. 10UF.C1263.C7101 CRITICAL BOM OPTION DESCRIPTION REFERENCE DES CRITICAL CRITICAL SS_CAP_1UF 138S0628 5 CAP.C1295. 0603 C1200. 0603 C3490. 10UF. 2.C2260. 6.C9926.C3404.2UF.2UF.C1241. 2.C3441 CRITICAL SS_CAP_2_2UF 138S0633 8 CAP.C1214.C2708.C9988.C3541 CRITICAL SS_CAP_2_2UF 138S0633 8 CAP. 6.C3590.C1244.C3421.C3455 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP. 20%. 1UF. 6. 20%.C2219. 0603 C2705. 6. 2.C7650.2UF. 20%.C2215.C9931.3V.2UF.C1225.3V. 6.C1296 138S0632 3 CAP.C3431. 0402 C3442.3V.3V.C7650.3V.C9917.C3425.2UF. 10UF.C9922. 10%.3V.2UF.C1292.C1283.C7281.C9918.C2901 CRITICAL MU_CAP_10UF 138S0627 6 CAP.C2708.C9240 BOM OPTION PART NUMBER C QTY DESCRIPTION CRITICAL MU_CAP_10UF 138S0627 10 CAP.C3430. 0402 C3520. 10UF. 2.2UF.C1202.C1254.2UF.C3450.C2703. 10UF.C2151.3V. 6. 0402 C3500.3V. 6.C4400. 6.C1293.C3410.C1231. 6.C1246.C1252.C9908.C1262.C2242.C2285 138S0626 5 CAP. 2.C1213. 6.C2232.C9904. 6. 6.C3445.C2260. 2. 2. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.C1255.C2231.C1266.3V. 6. 10UF.3V.C9919 138S0632 10 CAP.2UF.C3521.C7690 CRITICAL MU_CAP_10UF 138S0627 5 CAP. 0402 C9910.C9987.C9995.C1295.C2232.C3590.C4800 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP.C7507.C9997 138S0632 12 CAP. 6. 6.C9983.C9985.3V.C1207. 10UF.C1215.C7350.C3534.C3492. 6. 20%.C9994.2UF.C9994. 6.C9988.C1223.C1216.C1208.C1205. 6. 0603 C1200. 0402 C3542.C1214.C1209 REFERENCE DES CRITICAL CRITICAL SS_CAP_10UF 138S0625 10 CAP. 0603 C1210.C3550.C9932.C1265.C3530. 6.2UF.C3545. 20%.C3441 CRITICAL MU_CAP_2_2UF 138S0634 8 CAP. 20%. 6. 20%. 10%.C9918. 20%.C1219 CRITICAL SS_CAP_10UF 138S0625 10 CAP.C9901. 6.C3521.C2805. 6.C7507.C1287. 6.2UF.C1219 138S0626 10 CAP. 2.C1252. 20%.C1258.3V. 0603 C4109. 6.C1280 138S0626 9 CAP.C9939 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP. 20%.C9921.C9928.C9981.C4400.C1259 CRITICAL SS_CAP_2_2UF 138S0633 8 CAP.C5066.C1256.C7351 CRITICAL MU_CAP_10UF 138S0627 8 CAP.C3515.C1228. 0402 C1250.C3554.C1206.2UF.2UF.3V. 2.C1218.3V.C9912.C1216.C1293.C2195.C9991.C9936. 1UF. 0402 C2265. 20%.C9919 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP.C7301.C3416 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP.C1292. 20%. 20%.C7350. 2.C9983. 0402 C3420.C1254.C2900. 0402 C9930.C9987.C1207.C9913.C1247.3V.C3450. 6.C1218. 20%.C3411.C1287.C9922.C9937.C1802.C1206.C1208.C3410. 20%. 0603 C7502. 2.C9915.C9983. 20%. 0603 C2705.C3551.C1256.2UF.C9985.C3546.C9992.C1253.C7690 CRITICAL SS_CAP_10UF 138S0625 5 CAP.2UF.C3551.C9906. 0402 C1622.2UF. 6.C1222.3V.C9908.C3531.C2219.C7508. 2.C9935. 6.C2280.C3451. 10%. 0402 C3400. 2.C1280 CRITICAL SS_CAP_10UF 138S0625 9 CAP.C3424.3V.3V. 0402 C3420.C9213. 10UF.C3412. 10%.C9904. 0402 C1240.C3516 138S0632 10 CAP.C9982. 6.C9901.C1217. 6. 051-7230 B.C3535.C1286.C9908. 2.2UF. 0603 C2190.C2240.C1224.2UF.C2805.C9907. 2.C2703. 20%.2UF. 6.3V.C3492.C3441 138S0632 8 CAP. 0402 C3520. 0402 C1622.C9917.2UF. 0402 C3542.C3435.C9911.C1264.C9924.C1249 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP.C3454.C9903.3V.C9985.C3414.C3435.3V.C3411. 0603 C1220.2UF.3V. 0603 C2190.C1802.C9987. 20%. 0402 C9920. 6.C4613.C9932. 0402 C1801.C9931.C2195.C9927. 20%.3V. 6.C3415.C1285.C1258. 20%.C1249 138S0632 10 CAP.C9993. 20%. 0402 C3400.C9986.C2240.C3510.3V.C9926. 6.C1257. 6.C3444. 0402 C9900.3V.3V. 20%.3V.C3431. 10%. 10UF.3V.C4613. 20%. 0603 C1230.C2144.C9913. 20%.2UF.C1245.3V.C3410.C2260.C7100.C7603.C3454.C9991. 0402 C1283.C1203.3V.C9989 CRITICAL MU_CAP_2_2UF 138S0634 8 CAP. 20%.3V.C3451.C1213.C7101 SAMSUNG B TAIYO YUDEN QTY BOM OPTION QTY DESCRIPTION CRITICAL MU_CAP_1UF PART NUMBER 138S0630 5 CAP. 0402 C3400.C9914. 2.C9997 CRITICAL SS_CAP_2_2UF 138S0633 12 CAP.C7000. 10UF.C3541 138S0632 8 CAP.C2242.C9916. 20%.C3524.C3516 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP. 0402 C1260. 6. 20%.C2219.3V.C9934.C3445. 20%.3V.C3544.C3504. 20%.C9995. 2.C1288. 20%.C3525.3V. 2. 0402 C1283. 0402 C9930.C3550.C1213.C7351 138S0626 8 CAP.2UF.C7604.C1251.C3515.C3531. 20%.3V.C9902.2UF.3V.3V.C3545. 0402 C9980.C1214.C2805.2UF.2UF.2UF. 20%.C3440.C1201.C7508.C2240.C1263.3V.C3546.C2215. 20%. 6. 10UF.3V. 2.C3431.C1228.3V.C1254.C1217. 0603 C3490.C1246. 20%. 0603 C7502. 2.C9906.C3450.2UF.C9982. 6. 20%.C3540.C3534.C3550. 6.C9932.2UF.C9911.C9939 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP.C1262. 0402 C3500.C2231.C3505.C3446.C3525. 20%.C3510.C3540. 0402 C2214.C1248. 6.C1255. 0402 C3442.C1241.C2266.C2243 138S0632 10 CAP.3V.C3434. 6.C1288.C9204. 6. INC.C3414.3V. 20%. 2.C1266.C9924.C1253.3V.C3425.C1248.C1231.C1253.C7604.C9996.C3444.C2735.C4400. 20%. 6. 0603 C4109. 20%. 20%.C1206.C9909 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP. 2.C9921. 0402 C9920.C1226.C1205. 10UF.C1259 CRITICAL MU_CAP_2_2UF 138S0634 8 CAP. 2.C9933.3V.C9912. 10UF.C9938. 0603 C4109.C3525.C9204.C9909 138S0632 10 CAP.C3591.C3590.C1212.C2151.C3435.3V.C1294.C3491.C3412. 20%. 6.C1296 CRITICAL SS_CAP_2_2UF 138S0633 3 CAP.C9926. 20%.C1624.C9907.3V.C3501.3V.C9931. 0402 C9990.C9912.3V.2UF. 0603 C1230.C1204.C3544.C2266.C7650.C1223. 2.C3511.C7000.C9925. 20%.C9986.C3504. 10UF.C3591. 2.C2706. 0402 C9990.C1285. 6.3V. 0402 C9980.3V. 0402 C9910. 10UF.C1227. 2.C1231. 0402 C9900.C3524.3V.C2151. 20%.C1242. 2.C1209 REFERENCE DES 138S0626 10 CAP.2UF. 0603 C1210.C3512.C9929 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP.3V.C1245.C3440. 20%.C3501.C1624.C9929 138S0632 10 CAP.C2241.C2232. 6. 6.C2223.C1207. 6.C2901 CRITICAL SS_CAP_10UF 138S0625 6 CAP.C1211.2UF.C9904.C9997 CRITICAL MU_CAP_2_2UF 138S0634 12 CAP. 20%. 20%.C2708.C5066.C3551. 2. 20%.C3531.3V.C1221. 6.C1211.C9984. 6. 6.C9915. 20%.C1208.3V.C1222.C9213. 6.0. 6. 20%.C7604.C9996.C9928.C9905. 0402 REFERENCE DES C1801.C1242. 0402 C1240.3V.C1203.3V.C1264.C3524. 0402 C1260.C3415. 20%.2UF. 0402 C2265.C9923.3V.C7101 CRITICAL BOM OPTION CRITICAL TY_CAP_1UF CRITICAL TY_CAP_1UF 2. 6. 1UF.C3505.C1244.C1215. 6. 2. 6.3V.C9927. 20%.C1258.C2901 138S0626 6 CAP.C9901. 6. 0402 C1250.C9914. 6.C1247.C9204. 2. 6. 0402 C9930.3V.C1802. 6. 2.C1251. 0603 C7502.C2266.C9905.2UF.C3515. 20%.C1248.C9981.3V. 10UF.C3521.C1201.3V. 2.C9984. 0603 C9012. 0603 C3490. 20%.3V.C3451.C1221.C1283.3V.3V.C1287. 2. 20%.C1261.C2231.C2243 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP. 6. 6. 20%.C3421.C2285 CRITICAL MU_CAP_10UF 138S0627 5 CAP.C2241.C3530. 20%.C3415. 10UF.C9981.C9988. 0603 C1210.C7000.C1229 CRITICAL MU_CAP_10UF 138S0627 3 CAP.C1222. 0402 C3500. 20%. 0402 C3442.3V.0 OF 5 1 73 A . 20%. 6. 2.C9205.C1263. 20%.C2213.C1226. 2.C3544.C1261.C7301. 2.C9916. 2.C9934.C3405.C3511.C9917. 0402 C1250.C2706.C7541.C3425.C3424.2UF. 0603 C1220.C1246. 20%. 0402 C3520.C3444.2UF. 20%.3V.C9936.C1265.C7350. 10UF.C9936.C3454.C9902.C3555 BOM OPTION PART NUMBER TAIYO YUDEN QTY DESCRIPTION REFERENCE DES CRITICAL CRITICAL SS_CAP_2_2UF 138S0633 10 CAP.C1219 CRITICAL MU_CAP_10UF 138S0627 10 CAP.C9914.C7603. 0402 C2265.C9925.3V. 20%. 2.2UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS PART NUMBER C PART NUMBER MURATA QTY DESCRIPTION REFERENCE DES CRITICAL 138S0632 10 CAP.C1217. 20%.C7541.3V. 20%. 0402 C9910.3V.C1251.C3434. 10UF.2UF.C3546.C3592 CRITICAL SS_CAP_10UF 138S0625 8 CAP.C9903.C3404.2UF.3V.C3545.C9991. 20%. 10UF.C7100.C9213.C1261.C3514.C1229 CRITICAL SS_CAP_10UF 138S0625 3 CAP.2UF.C2900.C3446.C1285. 6.C3455 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP. 2. 6.3V. 20%.2UF. 2.C9992.C2144.C9995.C3416 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP.C2600. 6.C1205.C3424.C9907. 6.C3514. 10UF. 2.C1291.3V. 20%.C4800 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP. 0402 C1801.2UF.C3430.C1226. 6.3V.C3411. 10UF.C9933. 20%.C9903.C3414.C9992.C1288. 6. 2.2UF.C9982. 20%.C3512.C1243.C1227.C1265. 6.C2285 CRITICAL SS_CAP_10UF 138S0625 5 CAP.C9929 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP. 10UF.C9923. 6. 0402 C9900.C1221. 20%.C5066. 6.C7603. 10%.C3401. 2. 2.C1266.C1243.C2195.C3434.C7351 CRITICAL SS_CAP_10UF 138S0625 8 CAP.C1296 CRITICAL MU_CAP_2_2UF 138S0634 3 CAP.3V.C3554.2UF. 6.C2703.C9913.C9905.C9911. 20%.C2223. 0603 C2190.C1264.C9906.C4800 138S0632 10 CAP.C1242.C3446.C1291. 0402 C9980. 6.C3592 CRITICAL MU_CAP_10UF 138S0627 8 CAP.C1292.C3514.C1225. 2. 20%.C2735. 10UF.3V. 0402 C2214.3V.C9993. 0603 C1230.C9240 CRITICAL BOM OPTION PART NUMBER D B TAIYO YUDEN QTY DESCRIPTION CRITICAL SS_CAP_10UF 138S0625 10 CAP.C1291.C1257.C1243.C1202.C9925. 0402 C3420. 6.C1225. 0603 C9012.C3540.C1245.C9205. SCALE SHT NONE 8 7 6 5 4 3 2 REV. 0603 C9012.C9240 BOM OPTION CRITICAL TY_CAP_10UF CRITICAL TY_CAP_10UF CRITICAL TY_CAP_10UF CRITICAL TY_CAP_10UF CRITICAL TY_CAP_10UF CRITICAL TY_CAP_10UF CRITICAL TY_CAP_10UF CRITICAL TY_CAP_10UF CRITICAL TY_CAP_10UF CRITICAL TY_CAP_10UF Acoustic Cap BOM Config Tables A SYNC_MASTER=N/A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.C2170 138S0629 9 CAP.C9989 138S0632 8 CAP. 0402 C1283. 6.2UF.C7281.C9937. 6.C1255. 20%. 1UF.3V. 0402 C1622. 0402 C1260.2UF.C1257. 20%.C9205. 2.C3535.C1247. 0603 C2705.C3504.C1283.3V. 6.C1259 138S0632 8 CAP.C4613.C9939 138S0632 10 CAP.C3555 BOM OPTION CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF CRITICAL TY_CAP_2_2UF 10UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS SAMSUNG PART NUMBER MURATA QTY DESCRIPTION 138S0626 10 CAP.C1262. 20%.C9933. 10UF.C2600.C1204.C3440.C9923.C1294.C9934.C1211.C9915.C3505.3V. 2.C9916.2UF.C3430.C2170 CRITICAL SS_CAP_1UF 138S0628 9 CAP.C2144.C7100.C1224. 2. 2.C9924.C1227.C1280 CRITICAL MU_CAP_10UF 138S0627 9 CAP. 6.C1256.C9993.C1228.C1267 138S0632 6 CAP.3V.C3592 138S0626 8 CAP. 0603 C1220.C2170 CRITICAL MU_CAP_1UF 138S0630 9 CAP.C1223. 1UF.C1204.C1201.C3491.C3455 138S0632 10 CAP.C2241.C9919 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP.C9984.C2242.C2706.C1244.C1203.C1218. 20%.C9935. 20%.C1286.C1286. 2. 6.C9937. 2. 20%.C7690 138S0626 5 CAP.C3405.C3541 CRITICAL MU_CAP_2_2UF 138S0634 8 CAP.C3492. 6. 6.C1267 CRITICAL MU_CAP_2_2UF 138S0634 6 CAP.C9938.2UF.C3491.C1209 REFERENCE DES CRITICAL CRITICAL MU_CAP_10UF 138S0627 10 CAP. 20%. 20%.C7508. 20%.2UF.C7507.C1215. 2.C3416 138S0632 10 CAP. 10UF.

0> 11 12 52 66 CRT_BLUE 15 63 67 CRT_GREEN 15 63 67 CRT_HSYNC_LS 63 CRT_HSYNC_LS_R 63 CRT_HSYNC_R 15 63 67 CRT_RED 15 63 67 CRT_TVO_IREF 15 63 67 CRT_VSYNC_LS 63 CRT_VSYNC_LS_R 63 CRT_VSYNC_R 15 63 67 DEBUG_RESET_L 28 43 DLY_OFF_A 51 DLY_OFF_B 51 DLY_OFF_C 51 DLY_OFF_D 51 DMI_IRCOMP_R 24 DMI_N2S_N<3....0> 16 22 53 GFX_VR_EN 6 9 16 53 GLAN_COMP 23 70 GND_1V51V05S0_SGND 54 GND_1V8S3_CSGND 55 GND_1V8S3_SGND 55 GND_5V3V3S5_SGND 56 GND_ALS_F GND_CHGR_SGND 59 GND_GCORE_PGND 53 GND_IMVP6_SGND 52 GND_LCDBKLT_GNDA 64 GND_P1V2S3_SGND 57 GND_SMC_AVSS 41 42 45 53 59 HDA_BIT_CLK 7 9 23 37 69 HDA_BIT_CLK_R 23 69 HDA_DOCK_EN_L 23 HDA_RST_L 9 23 37 69 HDA_RST_L_R 23 69 HDA_SDIN0 7 9 23 37 69 HDA_SDIN1 HDA_SDOUT 7 9 23 37 69 HDA_SDOUT_R 23 69 HDA_SYNC 7 9 23 37 69 HDA_SYNC_R 23 69 HDMI_HOST 7 37 63 I2C_TOP_ALS_SCL_F 60 I2C_TOP_ALS_SDA_F 60 I414 I415 I416 I417 I418 I419 I420 I421 I422 I424 I423 I425 I427 I426 I428 I429 I430 I432 I431 I433 I434 I435 I436 I437 I438 I439 I440 I441 I442 I443 I445 I444 I447 I446 I448 I450 I449 I452 I451 I453 I455 I454 I457 I456 I458 I460 I459 I462 I461 I463 I465 I464 I466 I468 I467 I470 I469 I471 I473 I472 I475 I474 I476 I477 2 3 4 5 This indicates a MUSTHAVE requirement for ICT TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE IDE_IRQ14 23 38 69 IDE_PDA<2. 051-7230 SHT NONE 3 D B. REV..0> 15 61 67 PGOOD_1V25S0 51 57 PGOOD_1V8S3 51 55 PLT_RST_BUF_L 28 PLT_RST_L 6 7 24 28 60 64 PM_BATLOW_L 25 41 PM_BMBUSY_L 16 25 PM_CLKRUN_L 25 41 43 PM_DPRSLPVR 16 25 52 66 PM_EXTTS_L<0> 16 41 PM_EXTTS_L<1> 16 41 PM_LAN_ENABLE 25 41 PM_LAN_PWRGD 41 42 PM_LATRIGGER_L 7 13 24 PM_PWRBTN_L 6 25 41 PM_RI_L 25 PM_RSMRST_L 6 25 41 PM_S4_STATE_L 6 25 36 41 58 PM_SB_PWROK 9 25 28 51 55 PM_SLP_S3_L 6 7 25 36 37 41 42 PM_SLP_S4_LS5V 39 58 PM_SLP_S5_L 6 25 41 42 PM_STPCPU_L 25 29 30 PM_STPPCI_L 25 29 30 PM_SUS_STAT_L 25 41 43 PM_SYSRST_L 6 25 28 41 PM_THRMTRIP_L 10 16 23 42 66 PM_THRM_L 25 PM_WLAN_EN_L 36 PM_WLAN_EN_L1 36 PM_WLAN_EN_L2 36 PM_WLAN_EN_L_SS 36 PP0V9_S0 6 7 8 33 55 72 PP0V9_S3 6 8 31 32 55 72 PP18V5_DCIN 6 7 50 72 I493 I492 I494 I495 I496 I498 I497 I499 I500 I501 I503 I502 59 I508 42 45 I506 I507 7 36 I505 I504 I514 I512 I513 I511 I510 I509 I515 I516 I534 I532 I533 I531 I530 I540 I538 I539 I537 I536 I535 I544 I545 I541 I543 I542 I549 I550 I546 I548 I547 I574 I575 I576 I573 I572 I582 I583 I584 I589 I586 I585 I588 I587 I594 I591 I590 I593 I592 I599 I597 I596 I595 I598 I600 I834 I832 I833 I830 I831 I844 I842 I843 I840 I841 I847 I848 I846 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PP18V5_DCIN_ONEWIRE 50 72 PP18V5_G3H 7 8 50 59 72 PP18V5_S5_CHGR_SW_R 59 72 27 30 42 54 72 PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 23 26 PP1V05_S0_NB_VCCPEG 15 19 21 72 PP1V25_S0 6 7 8 16 18 19 21 26 27 51 57 72 PP1V25_S0M_NB_VCCA_HPLL 19 21 72 PP1V25_S0_NB_DPLL 22 72 PP1V25_S0_NB_PEGPLL 19 21 72 PP1V25_S0_NB_PEGPLL_RC 21 72 PP1V25_S0_NB_VCCA_DPLLA 19 22 72 PP1V25_S0_NB_VCCA_DPLLB 19 22 72 PP1V5_S0 6 7 8 11 12 22 26 27 54 72 PP1V5_S0_NB_QDAC 22 72 PP1V5_S0_NB_VCCD_CRT 19 22 72 PP1V5_S0_NB_VCCD_QDAC 19 22 72 PP1V5_S0_SB_VCC1_5_B 23 24 26 27 72 PP1V5_S0_SB_VCCDMIPLL 26 27 72 PP1V5_S0_SB_VCCDMIPLL_F 27 72 PP1V5_S0_SB_VCCSATAPLL 26 27 72 PP1V8_S0 6 7 8 19 22 51 61 72 PP1V8_S0_ANALOG_SDVO_F 61 72 PP1V8_S0_ANALOG_TMDS_F 61 72 PP1V8_S0_NB_VCCTXLVDS 19 22 72 PP1V8_S0_PVCC1_TMDS_F 61 72 PP1V8_S0_PVCC2_TMDS_F 61 72 PP1V8_S0_TMDS_F 61 72 72 PP1V8_S3 6 7 8 16 18 21 31 32 34 35 51 55 68 PP1V8_S3M_NB_VCCSMCK 19 21 72 PP1V8_S3_NB_VCCSMCK_RC 21 72 28 29 30 42 44 46 PP3V3_A_S0 6 7 8 13 16 19 21 22 23 24 25 26 27 51 52 53 60 63 64 PP3V3_B_S0 6 8 38 47 51 61 62 PP3V3_LCDVDD_SW 60 72 PP3V3_LCDVDD_SW_F 7 60 72 PP3V3_S0_ANALOG_SDVO_F 61 72 PP3V3_S0_CK505_VDD48 72 PP3V3_S0_CK505_VDDA 72 PP3V3_S0_CK505_VDDA_R 72 PP3V3_S0_CK505_VDD_CPU_SRC 29 72 PP3V3_S0_CK505_VDD_PCI 72 PP3V3_S0_CK505_VDD_REF 72 PP3V3_S0_HDCP_F 62 PP3V3_S0_IMVP6_3V3 52 72 PP3V3_S0_LCD_F 7 60 72 PP3V3_S0_NBCORE_FOLLOW_R 21 72 PP3V3_S0_NB_CRTDAC_F 22 72 PP3V3_S0_NB_TVDAC 22 72 PP3V3_S0_NB_TVDAC_F 22 72 PP3V3_S0_NB_TVDAC_FOLLOW 22 72 PP3V3_S0_NB_VCCA_CRTDAC 19 22 72 PP3V3_S0_NB_VCCA_DAC_BG 19 22 72 PP3V3_S0_NB_VCCA_TVDACA 19 22 72 PP3V3_S0_NB_VCCA_TVDACB 19 22 72 PP3V3_S0_NB_VCCA_TVDACC 19 22 72 PP3V3_S0_SPVCC_TMDS_F 61 72 PP3V3_S3 6 7 8 36 42 44 48 51 58 60 72 PP3V3_S3_ALS_F PP3V3_S3_AP_AUX 7 36 72 PP3V3_S5_AVREF_SMC 41 42 72 PP3V3_S5_SMC_AVCC 41 72 PP3V42G3H_SW 57 72 57 59 72 PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42 43 44 PP3V42_G3H_IPD_F 7 40 PP3V42_G3H_SMCUSBMUX_R 39 72 PP5V_S0 6 7 8 22 27 40 43 47 51 52 53 63 72 PP5V_S0_DVIPORT 7 37 63 72 PP5V_S0_DVIPORT_D 63 72 PP5V_S0_IMVP6_VDD 52 72 PP5V_S0_KBDLED_F 7 40 72 PP5V_S0_SB_V5REF 26 27 72 PP5V_S0_TMDS_FUSE 63 72 PP5V_S3 6 7 8 40 58 60 72 PP5V_S3_CAMERA_F 7 60 72 PP5V_S3_TOPCASE_F 7 40 PP5V_S3_USB2_EXTA 39 72 PP5V_S3_USB2_EXTA_F 7 37 39 72 PP5V_S5 6 7 8 27 39 51 54 55 56 58 72 PP5V_S5_SB_V5REF_SUS 26 27 72 PPBUS_G3H 7 8 37 45 50 56 59 PPBUS_R_G3H 7 8 42 52 53 54 55 PPDCIN_G3H 7 8 50 57 72 PPDCIN_G3H_R 50 72 PPVBATT_G3H_R 50 72 63 C B 64 72 59 72 28 ICT Test Points A 66 NOTICE OF PROPRIETARY PROPERTY 66 66 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.0> I864 63 7 37 TMDS_TX_CONN_P<2...0> 60 LVDS_A_DATA_F_P<2. 2 SCALE . INC.0> 60 I350 I351 I352 I353 I354 I355 I356 I357 I358 I360 I359 I361 I363 I362 I364 I365 I366 I368 I367 I369 I370 I371 I372 I373 I374 I375 I376 I377 I378 I379 I381 I380 I383 I382 I384 I386 I385 I388 I387 I389 I391 I390 I393 I392 I394 I396 I395 I398 I397 I399 I401 I400 I402 I404 I403 I406 I405 I407 I409 I408 I411 I410 67 67 I412 I413 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE LVDS_A_DATA_N<2> 7 15 60 67 LVDS_A_DATA_P<2> 7 15 60 67 LVDS_DDC_CLK 7 15 60 LVDS_DDC_DATA 7 15 60 LVDS_IBG 15 60 67 LVDS_VDD_EN 15 60 MEM_ODT<3..0> 16 24 67 DVI_HOST 7 37 63 DVI_HOTPLUG_DET 24 61 62 DVI_HOTPLUG_DET_BUF 61 62 DVI_HOTPLUG_DET_DEL_L 62 DVI_HOTPLUG_DET_INT_L 62 I190 I192 I191 I193 I195 I194 I196 I198 I197 I199 I200 I201 I202 I203 I205 I204 I206 I207 I208 I210 I209 I211 I213 I212 I215 I214 I216 I218 I217 I219 I220 I221 I222 I223 I224 I225 I226 I227 I228 I229 I230 I232 I231 I233 I235 I234 I236 I237 I238 I240 I239 I241 I242 I243 I244 I245 I246 I247 I248 I249 I250 I251 I253 I252 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE DVI_HPDET_RC 62 EXCARD_OC_L 24 EXTAUSB_OC_F_L 39 EXTAUSB_OC_L 7 9 13 24 39 EXTBUSB_OC_L 7 9 13 24 EXTGPU_LVDS_EN 7 13 24 EXT_COMPVID_B 63 67 EXT_C_R 63 67 EXT_Y_G 63 67 FAN_RT_PWM 7 47 FAN_RT_TACH 7 47 FRANKCARD_GPIO 25 43 FSB_CLK_CPU_N 10 29 30 71 FSB_CLK_CPU_P 10 29 30 71 FSB_CLK_NB_N 14 29 30 71 FSB_CLK_NB_P 14 29 30 71 FSB_CPURST_L 10 13 14 66 FWH_MFG_MODE 25 GCORE_BST_D 53 GCORE_COMP_R 53 GCORE_CSFB 53 GCORE_FBRTN 53 GCORE_LLINE 53 GCORE_PMON 53 GCORE_PMONFS 53 GCORE_PWRGD 53 GCORE_RAMP 53 GCORE_RPM 53 GCORE_RT 53 GCORE_ST 53 GCORE_SW 53 GCORE_SW_R 53 GCORE_VARFREQ 53 GCORE_VCC 53 GCORE_VDC_DIV 53 GCORE_VRPM 53 GFX_VID<3.0 OF 6 1 73 ...1> 64 LCDBKLT_SSTCMP 64 LCDBKLT_SSTCMP_RC 64 LCDBKLT_VREF 64 LCDVDD_PWREN_L 60 LCDVDD_PWREN_L_R 60 LOCAL_CTRL_CLK 7 13 15 LOCAL_CTRL_DATA 7 13 15 LPC_AD<3... THE POSSESSOR AGREES TO THE FOLLOWING 66 66 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.0> I862 TV_A_DAC I866 TV_B_DAC I865 TV_C_DAC I867 TV_DCONSEL<1> I868 USB2_AIRPORT_N I869 USB2_AIRPORT_N_F I870 USB2_AIRPORT_P I871 USB2_AIRPORT_P_F I872 USB2_CAMERA_F_N I874 USB2_CAMERA_F_P I873 USB2_CAMERA_N I875 USB2_CAMERA_P I876 USB2_EXTA_F_N I877 USB2_EXTA_F_P I878 USB2_EXTA_N I879 USB2_EXTA_P I880 USB2_MUXED_EXTA_N I882 USB2_MUXED_EXTA_P I881 USB2_WSPRING_N 7 I883 9 24 40 69 USB2_WSPRING_P 7 9 24 40 69 USB_DEBUGPRT_EN_L 39 41 USB_EXTC_OC_L 24 USB_EXTD_OC_L 7 13 24 USB_IR_N 7 9 24 40 69 USB_IR_P 7 9 24 40 69 USB_RBIAS 24 69 VCCCL1_5V 26 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE VGA_B I614 67 63 VGA_G 7 I616 37 VGA_HSYNC 67 I615 63 37 VGA_R 7 I618 63 VGA_VSYNC 7 I617 37 VR_PWRGD_CK505 I619 VR_PWRGD_CK505_L I836 VR_PWRGOOD_DELAY I835 WOL_EN 25 I837 24 WOW_EN 7 I839 13 XDP_BPM_L<0> 36 I838 66 XDP_BPM_L<1> 713 I849 10 XDP_BPM_L<2> 66 I850 13 XDP_BPM_L<3> 710 I851 XDP_BPM_L<4> 6137 I853 10 XDP_BPM_L<5> 66 I852 66 29 XDP_CLK_N 7 I855 13 30 XDP_CLK_P 71 I854 XDP_CPURST_L 6667 I856 13 XDP_DBRESET_L 6 7 10 13 XDP_OBS20 7 13 XDP_PWRGD 6 7 13 XDP_TCK 6 7 10 13 XDP_TDI 6 7 10 13 XDP_TDO 6 7 10 13 XDP_TMS 6 7 10 13 XDP_TRST_L 6 7 10 13 28 52 28 52 9 16 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE P1V8S0_EN 51 P3V3S0_EN 51 P3V3S3_EN_L 58 P3V3TVDAC_EN_RC 22 P3V3TVDAC_NOISE 22 P3V42G3H5_BOOST 57 P3V42G3H_SHDN_L 57 P3V42G3H_SHDN_L1 57 P5VS0_EN 51 P5VS3_EN_L 58 PBUS_ISENSE_IN_NEG 59 PBUS_ISENSE_VREG 59 PBUS_S0_SMC_VSENSE 45 PBUS_SMC_VSENSE_EN_L PCIE_CLK100M_MINI_N PCIE_CLK100M_MINI_N_F PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_P_F 7 36 PCIE_E_D2R_N 24 36 70 PCIE_E_D2R_N_F 7 36 PCIE_E_D2R_P 24 36 70 PCIE_E_D2R_P_F 7 36 PCIE_E_R2D_C_N 24 36 70 PCIE_E_R2D_C_N_F 7 36 PCIE_E_R2D_C_P 24 36 70 PCIE_E_R2D_C_P_F 7 36 PCIE_E_R2D_N 36 PCIE_E_R2D_P 36 PCIE_WAKE_L 7 25 36 43 PCI_CLK33M_LPCPLUS 30 71 PCI_CLK33M_SB 24 30 71 PCI_CLK33M_SMC 30 41 71 PCI_DEVSEL_L 24 70 PCI_FRAME_L 24 70 PCI_FW_GNT_L 24 70 PCI_FW_REQ_L 24 70 PCI_IRDY_L 24 70 PCI_LOCK_L 24 70 PCI_PERR_L 24 70 PCI_PME_FW_L 25 PCI_REQ1_L 24 70 PCI_REQ2_L 24 70 PCI_SERR_L 24 70 PCI_STOP_L 24 70 PCI_TRDY_L 24 70 PEG_COMP 15 PEG_D2R_N<1> 15 61 67 PEG_D2R_P<1> 15 61 67 PEG_R2D_C_N<3.8 ICT_TEST I95 I96 I97 I100 I99 I101 D I102 I104 I103 I105 I107 I106 I108 I109 I110 I112 I111 I113 I115 I114 I116 I118 I117 I119 I120 I121 I122 I123 I125 I124 I292 I294 C I293 I295 I297 I296 I298 I300 I299 I301 I302 I303 I304 I305 I307 I306 I308 I309 I310 I338 I337 I339 I341 I340 I343 I342 I344 I346 B I345 I347 I348 I349 ICT Test Points PP18V5_DCIN 6 7 50 72 BATT_POS 57 58 60 72 44 49 51 56 27 28 36 43 PP3V3_S5 7 8 24 25 26 41 42 43 44 PP3V42_G3H 6 7 8 23 26 27 28 39 40 57 59 72 GND PM_SLP_S3_L 6 7 25 36 37 41 42 51 55 PM_S4_STATE_L 6 25 36 41 58 PM_SLP_S5_L 6 25 41 42 SMC_PM_G2_EN 6 41 56 58 IMVP_VR_ON 6 41 52 GFX_VR_EN 6 9 16 53 SMC_BATT_CHG_EN 6 41 42 SMC_ONOFF_L 6 7 40 41 42 ALL_SYS_PWRGD_AND 6 51 PPVBAT_G3H_CHGR_REG 6 59 72 CPU_PWRGD 6 10 13 23 66 PM_RSMRST_L 6 25 41 PM_PWRBTN_L 6 25 41 TP_PCI_RST_L 9 24 PLT_RST_L 6 7 24 28 60 64 SMC_RESET_L 6 41 42 43 41 28 PM_SYSRST_L 6 27 54 72 2511 12 22 26 8 PP1V5_S0 54672 23726 27 30 13 14 18 19 PP1V05_S0 6 7 8 10 11 12 42 61 72 21 PP1V8_S0 6 7 8 19 22 72 51 35 51 55 68 PP1V8_S3 6 7 8 16 18 21 31 32 34 PP0V9_S0 6 7 8 33 55 72 55 72 PP0V9_S3 6 8 31 32 72 26 27 51 57 PP1V25_S0 6 7 8 16 18 19 21 58 72 PP5V_S5 6 7 8 27 39 51 54 55 56 PP5V_S3 6 7 8 40 58 60 72 PP5V_S0 53 60 63 64 PP3V3_S3 44 46 51 52 28 29 30 42 24 25 26 27 PP3V3_A_S0 6 7 8 13 16 19 21 22 23 63 PP3V3_B_S0 6 8 38 47 51 61 62 PPVCORE_S0_CPU 6657728 11 12 52 65 72 PPVCORE_S0_NB_GFX 6 7 8 18 22 45 53 XDP_TCK 6 7 10 13 66 XDP_TDI 6 7 10 13 66 XDP_TDO 6 7 10 13 66 XDP_TMS 6 7 10 13 66 XDP_TRST_L 6 7 10 13 66 XDP_CPURST_L 6 7 13 66 XDP_BPM_L<4> 6 7 10 13 66 XDP_BPM_L<5> 6 7 10 13 66 XDP_DBRESET_L 6 7 10 13 28 XDP_PWRGD 6 7 13 SPI_A_SCLK_R 6 43 49 69 SMC_MANUAL_RST_L 6 42 SMC_TCK 6 41 42 43 SMC_TDI 6 41 42 43 SMC_TDO 6 41 42 43 SMC_TMS 6 41 42 43 SMC_TRST_L 6 41 43 CPU_A20M_L 6 10 23 66 CPU_DPRSTP_L 6 10 16 23 52 66 CPU_DPSLP_L 6 10 23 66 CPU_FERR_L 6 10 23 66 NB_BSEL<0> 6 7 13 16 30 66 NB_BSEL<1> 6 7 13 16 30 66 NB_BSEL<2> 6 7 13 16 30 66 NB_CFG<16> 6 16 NB_CFG<19> 6 16 NB_CFG<20> 6 16 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 6 7 I126 I128 I127 I129 I131 I130 I132 I134 I133 I135 I136 I137 I138 I139 I141 I140 I142 I143 I144 I146 I145 I147 I149 I148 I151 I150 I152 I154 I153 I155 I156 I157 I273 I274 I275 I276 I277 I278 I279 I280 I281 I283 I282 I284 I286 I285 I287 I288 I289 I291 I290 I324 I325 I326 I327 I328 I329 I330 I331 I332 I333 I334 I336 I335 NB_CFG<3> 6 7 13 16 NB_CFG<4> 6 7 13 16 NB_CFG<5> 6 7 13 16 NB_CFG<6> 6 7 13 16 NB_CFG<7> 6 7 13 16 NB_CFG<8> 6 7 13 16 NB_CFG<9> 6 16 NB_RESET_L 6 16 28 NB_SB_SYNC_L 6 16 25 NB_TEST1 6 16 NB_TEST2 6 16 1V05S0_RUNSS 51 54 1V05S0_TRIP 54 1V25S0_RUNSS 51 57 1V51V05S0_V5FILT 54 1V5S0_RUNSS 51 54 1V5S0_TRIP 54 1V8S3_CS 55 1V8S3_V5FILT 55 1V8S3_VDDQSET 55 3V3S5_CS 56 5V3V3S5_TONSEL 56 5V3V3S5_V5FILT 56 5V3V3S5_VREF 56 5V3V3S5_VREG3 56 5VS5_CS 56 5VS5_VREG 56 ADAPTER_SENSE 50 AIRPORT_RST_L 7 28 36 ALL_SYSPWRGD_DLY 51 ALL_SYS_PWRGD 28 41 51 52 ALL_SYS_PWRGD_AND 6 51 ARB_DETECT_L 25 AUD_MIC_CLK 7 37 60 AUD_MIC_CLK_F 60 AUD_MIC_DATA 7 37 60 AUD_MIC_DATA_F 60 BATT_POS 6 7 50 BATT_POS_F 50 59 BOOTROM_OVR_EN_L 23 25 43 CHGR_AGATE 59 CHGR_AMON 59 CHGR_BGATE 59 CHGR_BMON 59 CHGR_BOOT 59 CHGR_CSIN 59 CHGR_CSIP 59 CHGR_CSON 59 CHGR_CSOP 59 CHGR_DCIN 59 CHGR_LOWCURRENT_GATE 59 CHGR_LOWCURRENT_REF 59 CHGR_SGATE 59 CHGR_SGATE_DIV 59 CHGR_VCOMP_R 59 CHGR_VDD 59 CHGR_VDDP 59 CHGR_VNEG 59 CHGR_VNEG_R 59 CK505_CLK14P3M_TIMER 30 29 CK505_FSA 30 71 CK505_FSB_TEST_MODE 29 30 CK505_FSC 30 71 CK505_PCI3_CLK 29 30 71 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I158 I160 I159 I161 I163 I162 I164 I166 I165 I167 I168 I169 I170 I171 I173 I172 I174 I175 I176 I178 I177 I179 I181 I180 I183 I182 I184 I186 I185 I187 I188 I189 I254 I255 I256 I257 I258 I259 I260 I261 I262 I264 I263 I265 I267 I266 I268 I269 I270 I272 I271 I311 I312 I313 I314 I315 I316 I317 I318 I319 I320 I321 I323 I322 These nets have a ICT_TEST property TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE CK505_PCI5_FCTSEL1 29 30 CK505_PCIF0_CLK 29 30 CK505_PCIF1_CLK 29 30 71 CK505_SRC_CLKREQ6_L 7 29 36 CK505_USB48_FSA 29 30 CK505_XTAL_OUT 29 CLINK_NB_CLK 16 25 70 CLINK_NB_DATA 16 25 70 CLINK_NB_RESET_L 16 25 70 CLK_PWRGD 25 29 CPU_A20M_L 6 10 23 66 CPU_BSEL<0> 10 30 66 CPU_BSEL<1> 10 30 66 CPU_BSEL<2> 10 30 66 CPU_COMP<0> 10 66 CPU_COMP<1> 10 66 CPU_COMP<2> 10 66 CPU_COMP<3> 10 66 CPU_DPRSTP_L 6 10 16 23 52 66 CPU_DPSLP_L 6 10 23 66 CPU_FERR_L 6 10 23 66 CPU_GTLREF 10 66 CPU_IERR_L 10 66 CPU_IGNNE_L 10 23 66 CPU_INIT_L 10 23 66 CPU_INTR 10 23 66 CPU_NMI 10 23 66 CPU_PROCHOT_BUF 42 CPU_PROCHOT_L 10 42 52 66 CPU_PROCHOT_L_R 42 CPU_PWRGD 6 10 13 23 66 CPU_SMI_L 10 23 66 CPU_STPCLK_L 10 23 66 CPU_THERMD_N 10 46 66 CPU_THERMD_P 10 46 66 CPU_THERMTRIP_R 23 CPU_VCCSENSE_N 11 52 66 CPU_VCCSENSE_P 11 52 66 CPU_VID<6..0> I861 TMDS_TX_P<2.0> 23 41 43 LPC_FRAME_L 23 41 43 LSOC_H LSOC_H_R 7 LVDS_A_CLK_F_N 7 60 LVDS_A_CLK_F_P 7 60 LVDS_A_CLK_N 15 60 67 LVDS_A_CLK_P 15 60 67 LVDS_A_DATA_F_N<2.0> 16 24 67 DMI_N2S_P<3.0..0> TMDS_TX_CLK 61 TRUE 4 I761 I760 I762 I763 I764 I765 I766 I767 I768 I770 I771 I769 I772 I773 I774 I775 I776 I777 I781 I780 I779 I778 I782 I783 I784 I785 I786 I787 I788 I789 I790 I792 I791 I794 I793 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TMDS_TX_CLK_N I857 TMDS_TX_CLK_P I858 TMDS_TX_CONN_CLK_N I860 TMDS_TX_CONN_CLK_P I859 TMDS_TX_CONN_N<2.0> 16 24 67 DMI_S2N_N<3.1> 7 60 64 LCDBKLT_RTN_RC<6..0> 23 38 69 IDE_PDDACK_L 23 38 69 IDE_PDDREQ 23 38 69 IDE_PDIORDY 23 38 69 IDE_PDIOR_L 23 38 69 IDE_PDIOW_L 23 38 69 IDE_RESET_BUF_L 38 IDE_RESET_L 24 38 IMVP6_BOOT 52 IMVP6_BOOT_RC 52 IMVP6_COMP_R 52 IMVP6_DROOP 52 IMVP6_PHASE 52 IMVP6_PVCC 52 IMVP6_RBIAS 52 IMVP6_SOFT 52 IMVP6_VDIFF 52 IMVP6_VDIFF_RC 52 IMVP6_VO_R 52 IMVP6_VR_TT 52 IMVP6_VSEN_N 52 66 IMVP6_VSEN_P 52 66 IMVP6_VSUM 52 IMVP6_VW 52 IMVP_DPRSLPVR 52 66 IMVP_VR_ON 6 41 52 INT_PIRQA_L 24 70 INT_PIRQB_L 24 70 INT_PIRQC_L 24 70 INT_PIRQD_L 24 70 INT_PIRQE_L 24 70 INT_PIRQF_L 24 70 INT_SERIRQ 25 41 43 LAN_ENERGY_DET 23 LAN_PHYPC 23 25 LCDBKLT_ENA 64 LCDBKLT_ISET 64 LCDBKLT_OVP 64 LCDBKLT_PWM_UNBUF 9 15 64 LCDBKLT_PWREN 9 15 64 LCDBKLT_RT 64 LCDBKLT_RTN<6......0> 16 31 32 33 68 MEM_RCOMP 16 MEM_RCOMP_L 16 MEM_RCOMP_VOH 16 MEM_RCOMP_VOL 16 NB_BSEL<0> 6 7 13 16 30 66 NB_BSEL<1> 6 7 13 16 30 66 NB_BSEL<2> 6 7 13 16 30 66 NB_CFG<16> 6 16 NB_CFG<19> 6 16 NB_CFG<20> 6 16 NB_CFG<3> 6 7 13 16 NB_CFG<4> 6 7 13 16 NB_CFG<5> 6 7 13 16 NB_CFG<6> 6 7 13 16 NB_CFG<7> 6 7 13 16 NB_CFG<8> 6 7 13 16 NB_CFG<9> 6 16 NB_CLINK_VREF 16 70 NB_CLK100M_DPLLSS_N 9301671 29 71 NB_CLK100M_DPLLSS_P 29 9 16 30 NB_CLK100M_PCIE_N 16 29 30 71 NB_CLK100M_PCIE_P 16 29 30 71 NB_CLK96M_DOT_N 9 16 29 30 71 NB_CLK96M_DOT_P 9 16 29 30 71 NB_CLKREQ_L 16 29 NB_FSB_RCOMP 14 NB_FSB_SCOMP 14 NB_FSB_SCOMP_L 14 NB_FSB_SWING 14 NB_FSB_VREF 14 NB_RESET_L 6 16 28 NB_SB_SYNC_L 6 16 25 NB_TEST1 6 16 NB_TEST2 6 16 NB_VCCSM_LF1 18 68 NB_VCCSM_LF2 18 68 NB_VCCSM_LF3 18 68 NB_VCCSM_LF4 18 68 NB_VCCSM_LF5 18 68 NB_VCCSM_LF6 18 68 NB_VCCSM_LF7 18 68 NB_VTTLF_CAP1 19 NB_VTTLF_CAP2 19 NB_VTTLF_CAP3 19 ODD_PWR_EN_L 24 ONEWIRE_DCIN_DIV 50 ONEWIRE_EN 50 ONEWIRE_ESD 50 ONEWIRE_OV 50 ONEWIRE_PWR_EN_L 50 ONEWIRE_PWR_EN_L_DIV 50 P1V25S0NBDPLL_FB 22 P1V25S0NBDPLL_RF 22 P1V25S0_ITH 57 P1V25S0_ITH_RC 57 P1V25S0_MODE 57 P1V25S0_RT 57 I478 I480 I479 I481 I482 I483 I485 I484 I486 I487 I488 I490 I489 I517 I519 I518 I520 I521 I522 I523 I524 I525 I527 I526 I528 I529 I551 I553 I552 I554 I555 I556 I557 I558 I559 I561 I560 I562 I563 I564 I565 I566 I568 I567 I569 I571 I570 I577 I578 I579 I580 I581 I601 I603 I602 I604 I606 I605 I608 I607 I609 I611 I610 I612 I613 I639 I641 I640 I642 I644 I643 I646 I645 I647 I649 I648 I650 I651 I652 I654 I653 I656 I655 I657 I665 I664 A I667 I666 I668 I669 I677 I676 I679 I678 I680 I681 I687 I686 I685 I689 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PPVBAT_G3H_CHGR_OUT 59 72 PPVBAT_G3H_CHGR_REG 6 59 72 PPVBAT_G3H_CHRGR_REG_0 59 72 PPVBAT_G3H_CHRGR_REG_R 59 72 72 PPVCORE_S0_CPU 6 7 8 11 12 52 65 PPVCORE_S0_NB_GFX PPVDCIN_G3H_PRE 45 59 72 PPVDCIN_G3H_PRE2 59 72 PPVDCIN_G3H_PRE_0 59 72 PPVDCIN_G3H_PRE_R 59 72 PPVIN_S5_IMVP6_VIN 52 72 PPVOUT_S0_LCDBKLT 7 60 64 72 PPVOUT_S0_LCDBKLT_SW 64 72 RSMRST_PWRGD 41 42 56 RSVD_EXTGPU_LVDS_EN 25 RUNSS_GATE_D 51 RUNSS_GATE_D_L 51 S0PWRGD_1V8_DIV 51 S0PWRGD_3V3_DIV 51 S0PWRGD_5V_DIV 51 S0SEQ_BEGIN 51 SATA_B_DET_L 25 SB_A20GATE 23 SB_CLINK_VREF0 25 70 SB_CLINK_VREF1 25 70 SB_CLK100M_DMI_N 24 29 30 71 SB_CLK100M_DMI_P 24 29 30 71 SB_CLK14P3M_TIMER 25 30 71 SB_CLK48M_USBCTLR 25 30 71 SB_CRT_TVOUT_MUX_L 25 63 SB_GPIO10_CL1 23 25 SB_GPIO18 25 SB_GPIO30 7 13 24 SB_GPIO36 25 SB_GPIO40 7 13 24 8 I620 I621 I622 I627 I624 I623 I626 I625 I632 I629 I628 I631 I630 I637 I635 I634 I633 I636 I638 I658 I659 I660 I661 I662 I663 I670 I671 I672 I673 I674 I675 I684 I683 I682 I688 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE SB_INTVRMEN 23 SB_LAN100_SLP 23 SB_RCIN_L 23 SB_RTC_RST_L 23 28 SB_RTC_X1 23 28 SB_RTC_X1_R 28 SB_RTC_X2 23 28 SB_SLOAD 25 SB_SM_INTRUDER_L 23 28 SB_SPKR 25 SDVO_CTRLCLK 16 61 SDVO_CTRLDATA 16 61 SMBUS_SB_ME_SCL 25 44 69 SMBUS_SB_ME_SDA 25 44 69 SMBUS_SB_SCL 25 29 44 69 SMBUS_SB_SDA SMBUS_SMC_0_S0_SCL 77141 44 46 SMBUS_SMC_0_S0_SDA 7 41 44 46 SMBUS_SMC_A_S3_SCL 71 44 71 SMBUS_SMC_A_S3_SDA 7403641 SMBUS_SMC_BSA_SCL 7594171 44 50 SMBUS_SMC_BSA_SDA SMBUS_SMC_B_S3_SCL 7 41 44 60 SMBUS_SMC_B_S3_SDA 7 41 44 60 SMBUS_SMC_MGMT_SCL 41 44 48 71 SMBUS_SMC_MGMT_SDA 41 44 48 71 SMB_AIRPORT_CONN_CLK 7 36 SMB_AIRPORT_CONN_DATA 7 36 SMC_ACIN_VSENSE 41 45 SMC_ADAPTER_EN 9 36 41 42 SMC_BATTPACK_STAT 41 42 SMC_BATT_CHG_EN 6 41 42 SMC_BATT_ISENSE 41 59 SMC_BC_ACOK 41 42 50 59 SMC_BC_ACOK_ONEWIRE_R 50 7 I726 I725 I728 I727 I729 I731 I730 I732 I734 I733 I736 I735 I737 I739 I738 I741 I740 I742 I744 I743 I746 I745 I747 I749 I748 I750 I751 I752 I754 I753 I755 I756 I757 I759 I758 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE SMC_BS_ALRT_L SMC_CASE_OPEN SMC_DCIN_ISENSE SMC_EXTAL SMC_FAN_0_CTL SMC_FAN_0_TACH SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_KBC_MDE SMC_LID SMC_LRESET_L SMC_MANUAL_RST_L SMC_MANUAL_RST_L1 SMC_MD1 SMC_NMI SMC_ODD_DETECT SMC_ONOFF_H SMC_ONOFF_L SMC_PBUS_ISENSE SMC_PBUS_VSENSE SMC_PF3 SMC_PM_G2_EN SMC_PROCHOT SMC_PROCHOT_3_3_L SMC_RESET_L SMC_RUNTIME_SCI_L SMC_RX_L SMC_SMS_INT SMC_SUS_CLK SMC_SYS_KBDLED SMC_SYS_LED SMC_TCK SMC_TDI SMC_TDO SMC_THRMTRIP 6 7 41 42 50 I691 41 42 I690 41 59 I692 41 42 I693 41 47 I694 41 47 I695 41 53 I696 41 45 I697 41 I698 7 40 41 42 I700 28 41 I701 6 42 I699 42 I702 41 43 I703 41 43 I704 41 42 I705 40 42 57 I706 6 7 40 41 42 41 59 I707 41 45 I710 41 42 I709 I711 6 41 56 58 I708 41 42 I712 41 42 I713 6 41 42 43 I714 25 41 I715 39 41 42 43 I716 9 41 48 I717 41 42 I718 7 40 41 I719 7 40 41 I720 6 41 42 43 I722 6 41 42 43 I721 6 41 42 43 I724 41 42 I723 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 42 SMC_TMS 6 I796 41 43 SMC_TRST_L I795 42 SMC_TX_L 39 I798 41 43 SMC_VCL I797 41 25 SMC_WAKE_SCI_L 7 I799 13 SMC_XTAL 41 I801 42 SMS_MOT_EN 48 I800 SMS_ONOFF_L 41 I802 48 SMS_X_AXIS 41 I804 48 SMS_Y_AXIS 41 I803 48 SMS_Z_AXIS 41 I806 48 SPI_A_INT_CLK 49 I805 SPI_A_INT_HOLD_L 49 I807 SPI_A_INT_SI 49 I809 SPI_A_INT_WP_L 69 I808 49 43 SPI_A_SCLK_R 6 I811 69 SPI_A_SI_R 43 I810 49 SPI_A_SO_R I812 69 SPI_CE_L<0> 43 I814 49 SPI_CE_R_L<0> 24 I813 49 69 SPI_CE_R_L<1> I816 SPI_EXT_A_SCLK_R 43 I815 SPI_EXT_A_SI_R 43 I817 SPI_EXT_CE_L<0> 43 I819 SPI_INT_CE_L<0> 43 I818 49 SPI_SCLK_R 24 I820 49 69 SPI_SI_R I821 49 SPI_SO 24 I822 43 69 SST8051_DDC_CLK I824 SST8051_DDC_DATA 62 I823 SST8051_DDC_EN 62 I825 SST8051_DVI_HOTPLUG_DET I826 SST8051_EA_L 62 I827 SST8051_P25_AUDIO_CONFIG I829 SST8051_P34_AUDIO_CONFIG I828 5 62 62 62 1 SST8051_RST TRUE 62 SST8051_SW_RESET_L 25 62 TRUE SST8051_UPDATE_L TRUE 25 62 SST8051_XTAL1 TRUE 62 SST8051_XTAL2 TRUE 62 SUS_CLK_SB TRUE 25 42 SYS_ONEWIRE TRUE 7 41 42 50 TRUE SYS_ONEWIRE_BILAT 50 TRUE THRM_CPU_ALERT_L 46 THRM_CPU_DXN TRUE 46 TRUE THRM_CPU_DXP 46 TRUE THRM_CPU_THM_L 46 TRUE TMDS_DDC_SCL 7 37 61 62 63 67 TMDS_DDC_SDA TRUE 7 37 61 62 63 67 TMDS_EXT_RES TRUE 61 TRUE TMDS_EXT_SWING 61 TRUE TMDS_HTPLG 7 37 61 63 TRUE TMDS_HTPLG_R 61 TRUE TMDS_HW_RESET_L 28 61 62 TRUE TMDS_INT_N 61 67 TRUE TMDS_INT_P 61 67 TRUE TMDS_LINT_L 61 62 61 62 TRUE TMDS_LSCL TMDS_LSDA TRUE 61 62 TRUE TMDS_SDB_N 61 67 TRUE TMDS_SDB_P 61 67 TRUE TMDS_SDC_N 61 67 TMDS_SDC_P TRUE 61 67 TMDS_SDG_N 61 67 TRUE TMDS_SDG_P TRUE 61 67 TMDS_SDR_N 61 67 TRUE TMDS_SDR_P 61 67 TRUE 25 61 TRUE TMDS_SW_RESET_L 61 TRUE TMDS_TX<2.0> I863 63 7 37 TMDS_TX_N<2.0> 15 61 67 PEG_R2D_C_P<3..0> 23 38 69 IDE_PDCS1_L 23 38 69 IDE_PDCS3_L 23 38 69 IDE_PDD<15..0> 16 24 67 DMI_S2N_P<3.

TEMP SENSOR CONNECTOR SMBUS_SMC_0_S0_SCL TRUE SMBUS_SMC_0_S0_SDA TRUE PP3V3_A_S0 TRUE I691 6 41 44 46 71 41 44 46 71 I690 6 44 46 51 52 I692 24 25 26 27 6 7 8 13 16 19 21 22 23 I694 28 29 30 42 53 60 63 64 FUNC TEST ...0..0 OF 7 1 73 .DC-IN CONNECTOR PP18V5_DCIN TRUE SYS_ONEWIRE TRUE GND TRUE I718 7 16 MAKE_BASE=TRUE NC_NB_NC_12 I680 6 41 44 50 59 I681 71 7 16 MAKE_BASE=TRUE NC_CRT_DDC_CLK NC_CRT_DDC_DATA I595 I682 I740 I433 I593 MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE TRUE 6 50 MAKE_BASE=TRUE I738 I431 FUNC TEST ..8> XDP_PWRGD XDP_OBS20 TP_XDP_HOOK2 TP_XDP_HOOK3 LOCAL_CTRL_DATA LOCAL_CTRL_CLK XDP_TCK SMC_WAKE_SCI_L EXTAUSB_OC_L SB_GPIO40 USB_EXTD_OC_L WOW_EN PM_LATRIGGER_L EXTGPU_LVDS_EN SB_GPIO30 EXTBUSB_OC_L XDP_CLK_P XDP_CLK_N XDP_CPURST_L XDP_DBRESET_L XDP_TDO XDP_TRST_L XDP_TDI XDP_TMS PP3V3_A_S0 PP1V05_S0 GND I484 MAKE_BASE=TRUE Power Supply NO_TESTs TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 6 60 MAKE_BASE=TRUE NC_CRT_DDC_DATA I700 FUNC TEST .5> NB_BSEL<0..8 6 7 2 3 4 5 1 Functional Test Points NB NO_TESTS These are normally testpoints but become NC NO_TEST I236 I254 I255 I257 D I279 I280 I237 I368 I370 I372 I377 I379 I378 I380 I244 I246 I356 I358 I360 I362 I364 I366 I258 I259 I260 I262 I261 I263 I264 I265 C I329 I331 I333 I335 I337 I339 I348 I350 I349 I352 I351 I353 I354 I383 I384 I386 NC_LVDS_VBG TRUE TRUE TRUE TRUE NC_NB_RSVD_31 NC_NB_RSVD_32 NC_NB_RSVD_33 NC_LVDS_VBG 7 15 MAKE_BASE=TRUE NC_NB_RSVD_31 7 16 MAKE_BASE=TRUE NC_NB_RSVD_32 7 MAKE_BASE=TRUE NC_NB_RSVD_33 7 x3 x3 MAKE_BASE=TRUE NC_MEM_A_RCVEN_L TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NC_MEM_B_RCVEN_L NC_NB_RSVD_1 NC_NB_RSVD_2 NC_NB_RSVD_3 NC_NB_RSVD_4 NC_NB_RSVD_5 NC_NB_RSVD_6 NC_NB_RSVD_7 NC_NB_RSVD_8 NC_NB_RSVD_14 NC_NB_RSVD_21 NC_NB_RSVD_22 NC_NB_RSVD_23 NC_NB_RSVD_24 NC_NB_RSVD_25 NC_NB_RSVD_26 NC_NB_RSVD_27 NC_NB_RSVD_35 NC_NB_RSVD_36 NC_NB_CFG_10 NC_NB_CFG_11 NC_NB_CFG_14 NC_NB_CFG_15 NC_NB_CFG_17 NC_NB_NC_1 NC_NB_NC_2 NC_NB_NC_3 NC_NB_NC_4 NC_NB_NC_5 NC_NB_NC_6 NC_NB_NC_7 NC_NB_NC_8 NC_NB_NC_9 NC_NB_NC_10 NC_NB_NC_11 NC_NB_NC_12 NC_NB_NC_13 NC_NB_NC_14 NC_NB_RSVD_29 NC_NB_RSVD_28 NC_NB_RSVD_30 I647 I649 I638 NC_MEM_A_RCVEN_L I640 7 17 MAKE_BASE=TRUE NC_MEM_B_RCVEN_L I639 7 17 NC_NB_RSVD_1 6 41 42 50 NC_NB_RSVD_2 6 41 44 50 59 I683 71 I684 7 16 NC_NB_RSVD_3 7 16 MAKE_BASE=TRUE NC_NB_RSVD_4 x2 7 16 MAKE_BASE=TRUE NC_NB_RSVD_5 7 16 MAKE_BASE=TRUE NC_NB_RSVD_6 I648 I650 x2 7 16 I706 MAKE_BASE=TRUE NC_NB_RSVD_7 7 16 MAKE_BASE=TRUE NC_NB_RSVD_8 7 16 I673 7 16 I674 7 16 I675 MAKE_BASE=TRUE NC_NB_RSVD_14 MAKE_BASE=TRUE NC_NB_RSVD_21 MAKE_BASE=TRUE NC_NB_RSVD_22 7 16 MAKE_BASE=TRUE NC_NB_RSVD_23 7 16 MAKE_BASE=TRUE NC_NB_RSVD_24 I668 7 16 MAKE_BASE=TRUE NC_NB_RSVD_25 I667 7 16 MAKE_BASE=TRUE NC_NB_RSVD_26 I669 7 16 MAKE_BASE=TRUE NC_NB_RSVD_27 I714 7 16 MAKE_BASE=TRUE NC_NB_RSVD_35 7 16 MAKE_BASE=TRUE NC_NB_RSVD_36 7 16 x2 MAKE_BASE=TRUE NC_NB_CFG_10 I655 7 16 I656 MAKE_BASE=TRUE NC_NB_CFG_14 7 16 I657 7 16 I658 7 16 I659 7 16 I660 MAKE_BASE=TRUE NC_NB_CFG_15 MAKE_BASE=TRUE NC_NB_CFG_17 MAKE_BASE=TRUE NC_NB_NC_1 MAKE_BASE=TRUE NC_NB_NC_2 7 16 I661 7 16 I662 MAKE_BASE=TRUE NC_NB_NC_3 MAKE_BASE=TRUE NC_NB_NC_4 7 16 I663 7 16 I664 MAKE_BASE=TRUE NC_NB_NC_5 MAKE_BASE=TRUE NC_NB_NC_6 7 16 MAKE_BASE=TRUE NC_NB_NC_7 7 16 MAKE_BASE=TRUE NC_NB_NC_8 7 16 MAKE_BASE=TRUE NC_NB_NC_9 I666 I711 I712 7 16 x10I713 MAKE_BASE=TRUE NC_NB_NC_11 I665 x2 7 16 MAKE_BASE=TRUE NC_NB_NC_10 I654 7 16 MAKE_BASE=TRUE NC_NB_CFG_11 7 16 I645 7 16 I646 MAKE_BASE=TRUE NC_NB_NC_14 MAKE_BASE=TRUE NC_NB_RSVD_29 7 16 I735 7 16 I736 7 16 I737 MAKE_BASE=TRUE NC_NB_RSVD_28 MAKE_BASE=TRUE NC_NB_RSVD_30 I739 NC_CRT_DDC_CLK I685 6 50 72 I687 6 41 42 50 I686 I688 I689 FUNC TEST .2> TRUE USB2_EXTA_F_P TRUE USB2_EXTA_F_N TRUE PP5V_S3_USB2_EXTA_F TRUE PP5V_S0_DVIPORT TRUE VGA_B TRUE VGA_G TRUE VGA_R TRUE GND TRUE I478 I476 I477 I480 I483 I502 6 37 63 6 8 11 12 52 65 72 6 8 33 55 72 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 6 8 16 18 19 21 26 27 51 57 72 D 6 8 11 12 22 26 27 54 72 6 8 19 22 51 61 72 6 8 18 22 45 53 65 72 6 7 8 22 27 40 43 47 51 52 53 63 72 72 6 8 16 18 21 31 32 34 35 51 55 68 72 6 8 36 42 44 48 51 58 60 72 6 8 40 58 60 72 6 8 24 25 26 27 28 36 43 44 49 51 56 57 58 60 72 6 8 27 39 51 54 55 56 58 72 6 8 23 26 27 28 39 40 41 42 43 44 57 59 72 6 8 50 59 72 6 8 50 57 72 6 7 8 37 45 50 56 59 64 72 6 8 42 52 53 54 55 59 72 FUNC TEST .BATTERY CONNECTOR BATT_POS TRUE GND TRUE SMC_BS_ALRT_L TRUE SMBUS_SMC_BSA_SCL TRUE SMBUS_SMC_BSA_SDA TRUE NICE2HAVE NETS NO_TEST Functional Test and No-Tests A A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.XDP/ITP CONNECTOR FUNC TEST ..CAMERA USB. INC...M93 WIRELESS CONNECTOR I470 I501 6 41 44 60 HDA_SYNC HDA_BIT_CLK AUD_MIC_DATA HDA_SDOUT PPBUS_G3H HDA_SDIN0 AUD_MIC_CLK PM_SLP_S3_L PPVCORE_S0_CPU PP0V9_S0 PP1V05_S0 PP1V25_S0 PP1V5_S0 PP1V8_S0 PPVCORE_S0_NB_GFX PP5V_S0 PP3V3_S0 PP1V8_S3 PP3V3_S3 PP5V_S3 PP3V3_S5 PP5V_S5 PP3V42_G3H PP18V5_G3H PPDCIN_G3H PPBUS_G3H PPBUS_R_G3H I500 6 60 72 I503 6 24 28 60 64 6 7 25 36 6 7 29 36 6 36 6 36 6 36 6 36 6 7 36 C 6 7 36 6 7 28 36 6 36 6 36 6 7 36 6 7 36 6 36 72 6 37 63 6 37 61 63 6 37 61 62 63 67 6 37 61 62 63 67 6 37 63 6 37 63 6 37 63 67 6 37 63 67 6 37 63 6 37 63 6 37 39 69 6 37 39 69 6 37 39 72 6 37 63 72 6 37 63 67 6 37 63 67 6 37 63 67 6 40 41 6 40 41 6 9 24 40 69 I741 6 9 24 40 69 I742 6 7 40 41 42 I743 6 7 9 24 40 69 6 7 9 24 40 69 I744 6 7 40 72 I746 I745 FUNC TEST .AIRPORT CK505_SRC_CLKREQ6_L TRUE PCIE_WAKE_L TRUE AIRPORT_RST_L TRUE SMBUS_SMC_A_S3_SCL TRUE SMBUS_SMC_A_S3_SDA TRUE GND TRUE B 6 7 29 36 6 7 25 36 6 7 28 36 6 7 36 40 41 44 71 6 7 36 40 41 44 71 6 40 6 7 36 40 41 44 71 GND x13I522 6 7 36 40 41 44 71 6 7 40 41 42 6 7 9 24 40 69 6 7 9 24 40 69 6 7 40 72 6 REQUIRED NETS LVDS NO_TESTS 6 13 16 6 60 72 7 15 I508 I454 I499 I731 B 6 13 16 30 66 I482 x14I730 I506 I92 6 15 60 I729 NO_TEST FUNC TEST .IPD CONNECTOR SMC_LID TRUE PP3V42_G3H_IPD_F TRUE SMC_SYS_KBDLED TRUE SMC_SYS_LED TRUE USB2_WSPRING_N TRUE USB2_WSPRING_P TRUE SMC_ONOFF_L TRUE USB_IR_N TRUE USB_IR_P TRUE PP5V_S0_KBDLED_F TRUE PP5V_S3_TOPCASE_F TRUE SMBUS_SMC_A_S3_SCL TRUE SMBUS_SMC_A_S3_SDA TRUE SMC_ONOFF_L TRUE USB_IR_N TRUE USB_IR_P TRUE PP5V_S0_KBDLED_F TRUE LSOC_H_R TRUE I727 I728 I733 6 40 41 42 6 40 PLT_RST_L PCIE_WAKE_L CK505_SRC_CLKREQ6_L PCIE_CLK100M_MINI_N_F PCIE_CLK100M_MINI_P_F PCIE_E_D2R_N_F PCIE_E_D2R_P_F PCIE_E_R2D_C_N_F PCIE_E_R2D_C_P_F AIRPORT_RST_L SMB_AIRPORT_CONN_CLK SMB_AIRPORT_CONN_DATA PCIE_E_R2D_C_N_F PCIE_E_R2D_C_P_F PP3V3_S3_AP_AUX I475 I479 6 10 63 64 13 66 46 51 30 42 6 10 27 28 13 66 24 25 21 2253 6 7 8 13 16 72 19 19 21 23 2623 6 7 8 10 1126 12 13 14 1829 27 30 42 5444 52 60 I732 x14I710 FUNC TEST . LVDS.RIO HATCH CONNECTOR HDMI_HOST TRUE DVI_HOST TRUE TMDS_HTPLG TRUE TMDS_DDC_SDA TRUE TMDS_DDC_SCL TRUE VGA_VSYNC TRUE VGA_HSYNC TRUE TMDS_TX_CONN_CLK_P TRUE TMDS_TX_CONN_CLK_N TRUE TMDS_TX_CONN_P<0.6> TRUE LVDS_A_DATA_N<0. ALS PP5V_S3_CAMERA_F TRUE USB2_CAMERA_F_P TRUE USB2_CAMERA_F_N TRUE LCDBKLT_RTN<1. SCALE SHT NONE 8 7 6 5 4 3 2 .2> TRUE LVDS_A_DATA_P<0.2> TRUE TMDS_TX_CONN_N<0. REV. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. 051-7230 B.AUDIO CONNECTOR 7 16 MAKE_BASE=TRUE NC_NB_NC_13 FUNC TEST .FAN CONNECTOR PP5V_S0 TRUE FAN_RT_PWM TRUE FAN_RT_TACH TRUE GND TRUE I695 52 53 63 72 6 7 8 22 27 40 43 47 51 I696 6 47 I697 6 47 I698 I699 I701 FUNC TEST .Power Supplies 6 10 13 66 6 15 60 7 15 I507 XDP_BPM_L<0.2> NB_CFG<3.2> TRUE PPVOUT_S0_LCDBKLT TRUE LVDS_A_CLK_F_N TRUE LVDS_A_CLK_F_P TRUE LVDS_DDC_CLK TRUE LVDS_DDC_DATA TRUE PP3V3_S0_LCD_F TRUE PP3V3_LCDVDD_SW_F TRUE SMBUS_SMC_B_S3_SDA TRUE SMBUS_SMC_B_S3_SCL TRUE GND TRUE 6 60 72 I702 6 60 69 I703 6 60 69 I704 6 60 64 6 15 60 67 6 15 60 67 6 60 64 72 6 60 I705 I707 I708 x16I709 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I509 I510 I512 I511 I513 I514 I515 CLOCK NO_TESTS I517 I516 NO_TEST I518 I520 I519 I521 I676 I734 I455 6 13 I457 6 13 I460 13 I459 13 I458 6 13 15 6 13 15 6 10 13 66 I461 6 13 25 41 6 9 13 24 39 I463 6 13 24 6 13 24 6 13 24 36 I467 6 13 24 6 13 24 6 13 24 I474 6 9 13 24 6 13 29 30 66 71 6 13 29 30 66 71 I471 I466 I465 I462 I468 I469 I473 I472 6 13 66 6 10 13 28 6 10 13 66 6 10 13 66 6 41 44 60 I716 I717 I719 6 9 23 37 69 6 9 23 37 69 I720 I721 I722 6 37 60 6 9 23 37 69 72 6 7 8 37 45 50 56 59 64 6 9 23 37 69 I723 I724 I725 I726 6 37 60 6 25 36 37 41 42 51 55 FUNC TEST .

2 mm VOLTAGE=18.2mm VOLTAGE=3. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.2 mm VOLTAGE=0.5V MAKE_BASE=TRUE 6 7 8 36 42 44 48 51 58 60 72 PPBUS_R_G3H PPBUS_R_G3H PPBUS_R_G3H PPBUS_R_G3H PPBUS_R_G3H 6 7 8 36 42 44 48 51 58 60 72 6 7 8 36 42 44 48 51 58 60 72 6 7 8 36 42 44 48 51 58 60 72 6 7 8 36 42 44 48 51 58 60 72 PP5V_S3 PP5V_S3 6 7 8 22 27 40 43 47 51 52 53 63 72 6 7 8 22 27 40 43 47 51 52 53 63 72 6 7 8 22 27 40 43 47 51 52 53 63 72 6 7 8 23 26 43 44 57 59 6 7 8 23 26 43 44 57 59 6 7 8 36 42 44 48 51 58 60 72 MIN_LINE_WIDTH=0.20MM VOLTAGE=3.9V 21 68 R0801 2 14 21 27 54 0 1 5% 1/20W MF 201 PP0V9_S3M_MEM_NBVREFB 16 MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.5 mm MIN_NECK_WIDTH=0.S0M" RAILS 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 PP3V3_A_S0 65 52 12 11 8 7 6 72 PPVCORE_S0_CPU PPVCORE_S0_CPU (CPU VCOR PWRE) MIN_LINE_WIDTH=0.2 mm VOLTAGE=18.20MM VOLTAGE=3.42V MAKE_BASE=TRUE 6 8 38 47 51 61 62 63 PP3V3_S3 6 7 8 19 22 51 61 72 MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.2 MM VOLTAGE=18.90V PWR) 72 55 32 31 8 6 PP0V9_S3 PP0V9_S3 (NB MEM VREF 0.0.9V 21 68 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 6 7 8 10 11 23 26 27 30 6 7 8 10 11 23 26 27 30 6 7 8 10 11 23 26 27 30 PP1V25_S0 MIN_LINE_WIDTH=0. 051-7230 B.4 mm MIN_NECK_WIDTH=0. INC.5V MAKE_BASE=TRUE PPDCIN_G3H 72 59 55 54 53 52 42 8 7 6 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 6 7 8 36 42 44 48 51 58 60 72 PP5V_S3 6 7 8 40 58 60 72 PPBUS_R_G3H 6 7 8 36 42 44 48 51 58 60 72 6 7 8 36 42 44 48 51 58 60 72 B 6 7 8 50 57 72 PPBUS_R_G3H 6 7 8 42 52 53 54 55 59 72 MIN_LINE_WIDTH=0.9V MAKE_BASE=TRUE PPVCORE_S0_CPU D 33 8 7 6 72 55 PP0V9_S0 PP0V9_S0 (DDR2 TERMINATION 0.3V MAKE_BASE=TRUE PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 6 8 38 47 51 61 62 63 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.30 MM MIN_NECK_WIDTH=0.9V PWR) MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.3V MAKE_BASE=TRUE (REGULATOR OUTPUT CPU VCORE PWR) 2 3 4 5 PPBUS_G3H 6 7 8 42 52 53 54 55 59 72 6 7 8 42 52 53 54 55 59 72 6 7 8 42 52 53 54 55 59 72 6 7 8 42 52 53 54 55 59 72 6 7 8 42 52 53 54 55 59 72 PPBUS_G3H 6 7 8 37 45 50 56 59 64 72 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.3V MAKE_BASE=TRUE 6 7 8 11 12 22 26 27 54 72 PPVCORE_S0_NB_GFX 44 43 36 28 27 26 25 24 8 7 6 72 60 58 57 56 51 49 52 53 60 63 64 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 6 63 764 28 29 30 42 44 46 51 52 53 60 6 7 8 13 16 19 21 22 23 24 25 26 27 44 46 51 52 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 PP1V8_S3 PP1V8_S3 PP1V8_S3 PP1V8_S3 6 7 8 11 12 22 26 27 54 72 PPVCORE_S0_NB_GFX 25 42 25 52 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 53 60 63 64 52 53 60 63 64 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 6 63 764 27 28 29 30 42 44 46 51 52 53 6 7 8 13 16 19 21 22 23 24 25 26 64 60 27 28 29 30 42 44 46 51 52 13 16 19 21 22 23 24 25 26 8 53 60 63 46 651 52 53 60 63 64 16 719 21 22 23 24 25 26 27 28 29 30 42 44 8 6 52 53 60 63 64 7 26 27 28 29 30 42 44 46 51 13 7 8 13 16 19 21 22 23 24 25 6 28 29 30 42 44 46 51 52 53 60 8 13 16 19 21 22 23 24 25 26 6 63 64 7 52 53 60 63 64 27 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 6 63 764 28 29 30 42 44 46 51 52 53 60 6 7 8 13 16 19 21 22 23 24 25 26 27 44 46 51 52 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 MIN_LINE_WIDTH=0.5V MAKE_BASE=TRUE PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H 6 7 8 40 58 60 72 6 7 8 40 58 60 72 6 7 8 37 45 50 56 59 64 72 6 7 8 37 45 50 56 59 64 72 6 7 8 37 45 50 56 59 64 72 6 7 8 37 45 50 56 59 64 72 6 7 8 37 45 50 56 59 64 72 6 7 8 22 27 40 43 47 51 52 53 63 72 6 7 8 22 27 40 43 47 51 52 53 63 72 6 7 8 22 27 40 43 47 51 52 53 63 72 Power Aliases 6 7 8 22 27 40 43 47 51 52 53 63 72 6 7 8 22 27 40 43 47 51 52 53 63 72 SYNC_MASTER=WFERRY SYNC_DATE=06/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.25V MAKE_BASE=TRUE 24 30 24 51 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 PP1V8_S3 6 7 8 11 12 22 26 27 54 72 PP1V8_S0 PP1V8_S0 PP1V8_S0 64 23 29 23 46 "S3" RAILS PP1V8_S3 51 35 34 32 31 21 18 16 8 7 6 72 68 55 6 7 8 11 12 22 26 27 54 72 MIN_LINE_WIDTH=0.2mm MIN_NECK_WIDTH=0.9V MAKE_BASE=TRUE PP0V9_S3 PP0V9_S3 PP0V9_S3 72 54 42 30 12 11 10 8 7 6 27 26 23 21 19 18 14 13 PP1V05_S0 72 21 19 18 16 8 7 6 57 51 27 26 PP1V25_S0 MIN_LINE_WIDTH=0.05V MAKE_BASE=TRUE PP1V5_S0 1 12 13 6 7 8 10 11 18 19 23 26 30 42 72 PP0V9_S3M_MEM_NBVREFA 16 MIN_LINE_WIDTH=0.2 mm VOLTAGE=0.2 mm VOLTAGE=3.3 MM MIN_NECK_WIDTH=0.6 mm MIN_NECK_WIDTH=0. SCALE SHT NONE 8 7 6 5 4 3 2 REV.2 mm VOLTAGE=1.9V MAKE_BASE=TRUE PP0V9_S0 6 7 8 11 12 52 65 72 6 7 8 11 12 52 65 72 6 7 8 33 55 72 6 7 8 33 55 72 (REGULATOR OUTPUT CPU 0.2 mm VOLTAGE=18.4 mm MIN_NECK_WIDTH=0.8V MAKE_BASE=TRUE 63 22 28 22 44 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 53 60 63 64 28 29 30 42 44 46 51 52 53 60 8 13 16 19 21 22 23 24 25 26 6 63 64 7 52 53 60 63 64 27 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 6 63 764 28 29 30 42 44 46 51 52 53 60 6 7 8 13 16 19 21 22 23 24 25 26 27 44 46 51 52 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 53 60 63 64 26 27 28 29 30 42 6 7 8 13 16 19 21 22 23 24 25 44 46 51 52 53 60 63 64 PP3V3_B_S0 PP3V3_B_S0 PP3V3_B_S0 PP3V3_B_S0 PP3V3_B_S0 6 7 8 11 12 22 26 27 54 72 6 7 8 11 12 22 26 27 54 72 PP1V8_S0 60 21 27 21 42 "S5" RAILS 6 7 8 11 12 22 26 27 54 72 72 60 58 51 48 44 42 36 8 7 6 61 51 22 19 8 7 6 72 44 46 51 52 53 6 7 8 13 16 19 26 53 60 63 64 6 7 8 13 16 19 26 27 28 29 30 PP3V3_B_S0 (peninsula) B PP1V8_S0 PP3V3_B_S0 3V3_B_S0 plane on right side 6 7 8 16 18 19 21 26 27 51 57 72 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 PP3V3_A_S0 1 "G3H" RAILS 6 7 8 16 18 19 21 26 27 51 57 72 6 7 8 16 18 19 21 26 27 51 57 72 6 7 8 16 18 19 21 26 27 51 57 72 PP1V5_S0 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 6 7 8 16 18 19 21 26 27 51 57 72 6 7 8 16 18 19 21 26 27 51 57 72 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 6 7 8 11 12 22 26 27 54 72 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE 6 7 8 22 27 40 43 47 51 52 53 63 72 6 7 8 23 26 27 28 39 40 41 42 43 44 57 59 72 6 7 8 23 26 27 28 39 40 41 42 43 44 57 59 72 6 7 8 16 18 21 31 32 34 35 51 55 68 72 6 7 8 18 22 45 53 65 72 PP5V_S3 6 7 8 23 26 27 28 39 40 41 42 43 44 57 59 72 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.6 mm MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE 6 7 8 24 25 26 27 28 36 43 44 49 51 56 57 58 60 72 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 72 64 59 56 50 45 37 8 7 6 PP5V_S0 PP3V3_S5 MIN_LINE_WIDTH=0.5V MAKE_BASE=TRUE PP3V3_A_S0 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.9V PWR) MIN_LINE_WIDTH=0.2 mm VOLTAGE=3.20 MM VOLTAGE=0.0 OF 8 1 73 A .6 mm MIN_NECK_WIDTH=0.6 mm MIN_NECK_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.3 mm MIN_NECK_WIDTH=0.6 mm MIN_NECK_WIDTH=0.8 6 7 "S0.2 mm VOLTAGE=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE 6 7 8 27 39 51 54 55 56 58 72 6 7 8 27 39 51 54 55 56 58 72 6 7 8 27 39 51 54 55 56 58 72 6 7 8 27 39 51 54 55 56 58 72 6 7 8 27 39 51 54 55 56 58 72 6 7 8 27 39 51 54 55 56 58 72 C 42 41 40 39 28 27 26 23 8 7 6 72 59 57 44 43 PP3V42_G3H PP3V42_G3H 6 7 8 18 22 45 53 65 72 PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H 6 8 38 47 51 61 62 63 6 8 38 47 51 61 62 63 6 8 38 47 51 61 62 63 72 59 50 8 7 6 PP18V5_G3H 72 57 50 8 7 6 PPDCIN_G3H 6 7 8 16 18 21 31 32 34 35 51 55 68 72 6 7 8 16 18 21 31 32 34 35 51 55 68 72 6 7 8 16 18 21 31 32 34 35 51 55 68 72 6 7 8 16 18 21 31 32 34 35 51 55 68 72 27 28 39 40 41 42 72 27 28 39 40 41 42 72 6 7 8 23 26 27 28 39 40 41 42 43 44 57 59 72 6 7 8 23 26 27 28 39 40 41 42 43 44 57 59 72 6 7 8 23 26 27 28 39 40 41 42 43 44 57 59 72 6 7 8 23 26 27 28 39 40 41 42 43 44 57 59 72 PP18V5_G3H 6 7 8 50 59 72 PPDCIN_G3H 6 7 8 50 57 72 MIN_LINE_WIDTH=0.3V MAKE_BASE=TRUE 6 7 8 19 22 51 61 72 72 60 58 40 8 7 6 72 63 53 52 27 22 8 7 6 51 47 43 40 PP3V3_S5 6 8 38 47 51 61 62 63 MIN_LINE_WIDTH=0.25V MAKE_BASE=TRUE PP1V25_S0 PP1V25_S0 PP1V25_S0 PP1V25_S0 PP1V25_S0 PP1V25_S0 26 22 12 11 8 7 6 72 54 27 0 5% 1/20W MF 201 6 8 31 32 55 72 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 C R0800 6 8 31 32 55 72 2 12 42 12 42 12 42 13 54 13 54 13 54 3V3_S0 split into 2 14 18 19 21 72 14 18 19 21 72 14 18 19 21 72 for layout optimization of plane splits 63 62 61 51 47 38 8 6 6 7 8 16 18 19 21 26 27 51 57 72 6 7 8 11 12 22 26 27 54 72 53 45 22 18 8 7 6 72 65 PPVCORE_S0_NB_GFX 6 7 8 11 12 22 26 27 54 72 PP3V3_S3 72 58 56 55 54 51 39 27 8 7 6 6 7 8 19 22 51 61 72 6 7 8 19 22 51 61 72 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 A PP5V_S5 6 7 8 24 25 49 51 56 57 6 7 8 24 25 49 51 56 57 6 7 8 24 25 49 51 56 57 26 58 26 58 26 58 27 60 27 60 27 60 28 36 43 44 72 28 36 43 44 72 28 36 43 44 72 25 57 25 57 25 57 26 58 26 58 26 58 27 60 27 60 27 60 28 36 43 44 72 28 36 43 44 72 28 36 43 44 72 6 7 8 24 49 51 56 6 7 8 24 49 51 56 6 7 8 24 49 51 56 D 6 7 8 24 25 26 27 28 36 43 44 49 51 56 57 58 60 72 6 7 8 24 25 26 27 28 36 43 44 49 51 56 57 58 60 72 6 7 8 24 25 49 51 56 57 6 7 8 24 25 49 51 56 57 6 7 8 24 25 49 51 56 57 26 58 26 58 26 58 27 60 27 60 27 60 28 36 43 44 72 28 36 43 44 72 28 36 43 44 72 6 7 8 24 25 26 27 28 36 43 44 49 51 56 57 58 60 72 6 7 8 24 25 26 27 28 36 43 44 49 51 56 57 58 60 72 6 7 8 24 25 26 27 28 36 43 44 49 51 56 57 58 60 72 PP5V_S5 6 7 8 27 39 51 54 55 56 58 72 MIN_LINE_WIDTH=0.

5-THNP 41 9 69 39 9 6 USB2_MUXED_EXTA_N 6 9 39 69 NO-CONNECT UNUSED SDVO INTERFACE PORTS Z0911 Z0903 MAKE_BASE=TRUE USB2_MUXED_EXTA_N 69 23 9 9 67 6 9 24 39 69 EXTAUSB_OC_L 6 7 9 13 24 39 69 39 9 6 69 23 9 9 15 6 9 24 39 69 USB2_EXTA_N MAKE_BASE=TRUE EXTAUSB_OC_L 9 15 MAKE_BASE=TRUE USB2_EXTA_P MAKE_BASE=TRUE USB2_EXTA_N 9 15 PCI_EXPRESS GRAPHICS ALIASES 1 1 USB2_EXTA_P MAKE_BASE=TRUE MAKE_BASE=TRUE STDOFF-4.4 Z0912 STDOFF-4. 051-7230 SCALE SHT NONE 8 D USB PORT [2] = Unused MAKE_BASE=TRUE NC_SATA_C_R2D_C_P USB2_AIRPORT_P 6 9 24 36 69 MAKE_BASE=TRUE MAKE_BASE=TRUE 69 9 9 67 USB2_MUXED_EXTA_P 6 9 39 69 MAKE_BASE=TRUE MAKE_BASE=TRUE CLOCK ALIASES 15 9 15 9 NO_TEST NC_SMC_PA0 NC_SMC_PA1 NC_SMC_PB0 NC_SMC_PG0 NC_SMC_P14 NC_SMC_P20 NC_SMC_P21 NC_SMC_P22 NC_SMC_P23 NC_SMC_P26 NC_SMC_P27 NC_SMC_P41 NC_SMC_P43 NC_SMC_P44 NC_SMC_P46 NC_SMC_P62 NC_SMC_P63 NC_SMC_P64 NC_SMC_P67 NC_SMC_P81 NC_SMC_GFX_OVERTEMP_L NC_EXCARD_OC_L NC_SMC_BATT_TRICKLE_EN_L NC_SMC_EXCARD_CP NC_SMC_ENRGYSTR_LDO_EN NC_SMC_ENRGYSTR_LDO_PGOOD NC_ALS_RIGHT NC_ALS_GAIN NC_SMC_EXCARD_PWR_EN NC_SMC_FAN_1_CTL NC_SMC_FAN_2_CTL NC_SMC_FAN_3_CTL NC_SMC_FAN_1_TACH NC_SMC_FAN_2_TACH NC_SMC_FAN_3_TACH USB2_MUXED_EXTA_P USB PORT [1] = PCI-E Mini Card MAKE_BASE=TRUE NO-CONNECT UNUSED CLOCK INTERFACE PORTS 15 9 15 9 STDOFF-4.31> PCI_C_BE_L<0.8 6 7 EMI SPRING CLIPS LVDS ALIASES PLACE CLIPS PER MCO ON TOPSIDE NEAR BATTERY CONNECTOR J6900 CRITICAL SC0900 1 EMI-SPRING PS-25N CRITICAL SC0901 PS-25N 67 15 9 NC_LVDS_B_CLK_N NC_LVDS_B_CLK_N TRUE 67 15 9 NC_LVDS_B_CLK_P NC_LVDS_B_CLK_P TRUE 15 9 NC_LVDS_B_DATA_N0 NC_LVDS_B_DATA_N0 TRUE 15 9 NC_LVDS_B_DATA_N1 NC_LVDS_B_DATA_N1 TRUE 15 9 NC_LVDS_B_DATA_N2 NC_LVDS_B_DATA_N2 TRUE 67 9 NC_LVDS_B_DATA_N3 NC_LVDS_B_DATA_N3 TRUE 9 15 67 69 9 NC_SATA_A_D2R_N NC_SATA_A_D2R_N TRUE 9 69 9 15 67 69 9 NC_SATA_A_D2R_P NC_SATA_A_D2R_P TRUE 9 69 MAKE_BASE=TRUE MAKE_BASE=TRUE 69 23 9 NC_SATA_A_R2D_C_N NC_SATA_A_R2D_C_N TRUE 9 23 69 9 15 69 23 9 NC_SATA_A_R2D_C_P NC_SATA_A_R2D_C_P TRUE 9 23 69 69 9 NC_SATA_B_D2R_N NC_SATA_B_D2R_N TRUE 9 69 69 9 NC_SATA_B_D2R_P NC_SATA_B_D2R_P TRUE 9 69 MAKE_BASE=TRUE NC_LVDS_B_DATA_P0 NC_LVDS_B_DATA_P0 TRUE 15 9 NC_LVDS_B_DATA_P1 NC_LVDS_B_DATA_P1 TRUE 15 9 NC_LVDS_B_DATA_P2 NC_LVDS_B_DATA_P2 9 67 67 9 NC_LVDS_B_DATA_P3 NC_LVDS_B_DATA_P3 TRUE NC_LVDS_A_DATA_P3 NC_LVDS_A_DATA_P3 TRUE 67 9 NC_LVDS_A_DATA_N3 Z0910 1 Z0902 4.4 MAKE_BASE=TRUE MAKE_BASE=TRUE 15 9 NC_LVDS_A_DATA_N3 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE BOSSES TO CONNECT TO HEATSINK USB ALIASES USB PORT [0] = External USB2.4H-0...4 1 C SMC ALIASES NO-CONNECT UNUSED SMC INTERFACE PORTS NC_SATA_B_R2D_C_N NC_SATA_B_R2D_C_N TRUE 9 23 69 69 36 24 9 6 USB2_AIRPORT_P NC_SATA_B_R2D_C_P NC_SATA_B_R2D_C_P TRUE 9 23 69 69 36 24 9 6 USB2_AIRPORT_N 69 36 24 9 6 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 B 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 41 9 A 41 9 41 9 41 9 MAKE_BASE=TRUE NC_SMC_PA0 TRUE NC_SMC_PA1 TRUE NC_SMC_PB0 TRUE NC_SMC_PG0 TRUE NC_SMC_P14 TRUE NC_SMC_P20 TRUE NC_SMC_P21 TRUE NC_SMC_P22 TRUE NC_SMC_P23 TRUE NC_SMC_P26 TRUE NC_SMC_P27 TRUE NC_SMC_P41 TRUE NC_SMC_P43 TRUE NC_SMC_P44 TRUE NC_SMC_P46 TRUE NC_SMC_P62 TRUE NC_SMC_P63 TRUE NC_SMC_P64 TRUE NC_SMC_P67 TRUE NC_SMC_P81 TRUE NC_SMC_GFX_OVERTEMP_L TRUE NC_EXCARD_OC_L TRUE NC_SMC_BATT_TRICKLE_EN_L TRUE NC_SMC_EXCARD_CP TRUE NC_SMC_ENRGYSTR_LDO_EN TRUE NC_SMC_ENRGYSTR_LDO_PGOODTRUE NC_ALS_RIGHT TRUE NC_ALS_GAIN TRUE NC_SMC_EXCARD_PWR_EN TRUE NC_SMC_FAN_1_CTL TRUE NC_SMC_FAN_2_CTL TRUE NC_SMC_FAN_3_CTL TRUE NC_SMC_FAN_1_TACH TRUE NC_SMC_FAN_2_TACH TRUE NC_SMC_FAN_3_TACH TRUE NC_SMC_PF0 NC_SMC_PF0 NC_SMC_BATT_VSET NC_SMC_SYS_VSET NC_SMC_RSTGATE_L NC_SMC_GFX_THROTTLE_L NC_SYS_ISET NC_BATT_ISET NC_ISENSE_CAL_EN NC_SMC_FWE NC_SMC_ANALOG_ID NC_SMC_TEST_DAC1 NC_SMC_TEST_DAC2 NC_SMC_TEST_DAC3 NC_SMC_BATT_VSET NC_SMC_SYS_VSET NC_SMC_RSTGATE_L NC_SMC_GFX_THROTTLE_L NC_SYS_ISET NC_BATT_ISET NC_ISENSE_CAL_EN NC_SMC_FWE NC_SMC_ANALOG_ID NC_SMC_TEST_DAC1 NC_SMC_TEST_DAC2 NC_SMC_TEST_DAC3 MAKE_BASE=TRUE USB2_AIRPORT_P USB2_AIRPORT_N NC_SATA_C_D2R_N NC_SATA_C_D2R_N TRUE 9 69 69 9 NC_SATA_C_D2R_P NC_SATA_C_D2R_P TRUE 9 69 NC_SATA_C_R2D_C_N NC_SATA_C_R2D_C_N TRUE 9 23 69 TRUE 9 23 69 69 23 9 9 67 69 23 9 MAKE_BASE=TRUE NC_SATA_C_R2D_C_P USB2_AIRPORT_N 6 9 24 36 69 69 24 9 MAKE_BASE=TRUE 69 24 9 MAKE_BASE=TRUE TP_USB2_3G_P 69 24 9 TP_USB2_3G_P TP_USB2_3G_N 69 24 9 TP_USB2_3G_N TP_USB2_3G_P 9 24 69 TP_USB2_3G_N 9 24 69 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE USB PORT [3] = CAMERA 69 60 24 9 6 69 60 24 9 6 69 60 24 9 6 USB2_CAMERA_P 69 60 24 9 6 USB2_CAMERA_N USB2_CAMERA_P USB2_CAMERA_P 6 9 24 60 69 MAKE_BASE=TRUE USB2_CAMERA_N USB2_CAMERA_N 6 9 24 60 69 MAKE_BASE=TRUE NC_PEG_D2R_N0 NC_PEG_D2R_N0 TRUE NC_PEG_D2R_N2 NC_PEG_D2R_N2 TRUE 15 9 NC_PEG_D2R_N3 NC_PEG_D2R_N3 TRUE TRUE 15 9 NC_PEG_D2R_N6 NC_PEG_D2R_N6 TRUE 15 9 NC_PEG_D2R_N7 NC_PEG_D2R_N7 TRUE NC_PEG_D2R_N8 TRUE 15 9 NC_PEG_D2R_N9 NC_PEG_D2R_N9 TRUE 15 9 NC_PEG_D2R_N10 NC_PEG_D2R_N10 TRUE 15 9 NC_PEG_D2R_N11 NC_PEG_D2R_N11 TRUE NC_PEG_D2R_N12 NC_PEG_D2R_N12 TRUE 15 9 NC_PEG_D2R_N13 NC_PEG_D2R_N13 TRUE 15 9 NC_PEG_D2R_N14 NC_PEG_D2R_N14 TRUE 15 9 NC_PEG_D2R_N15 NC_PEG_D2R_N15 TRUE NC_PEG_D2R_P0 NC_PEG_D2R_P0 TRUE 15 9 NC_PEG_D2R_P2 NC_PEG_D2R_P2 TRUE NC_PEG_D2R_P3 NC_PEG_D2R_P3 TRUE 15 9 NC_PEG_D2R_P4 NC_PEG_D2R_P4 TRUE 15 9 NC_PEG_D2R_P5 NC_PEG_D2R_P5 TRUE 15 9 NC_PEG_D2R_P6 NC_PEG_D2R_P6 TRUE NC_PEG_D2R_P8 NC_PEG_D2R_P8 TRUE NC_PEG_D2R_P9 NC_PEG_D2R_P9 TRUE NC_PEG_D2R_P10 NC_PEG_D2R_P10 TRUE NC_PEG_D2R_P11 NC_PEG_D2R_P11 TRUE MAKE_BASE=TRUE NC_PEG_D2R_P12 NC_PEG_D2R_P12 TRUE 15 9 NC_PEG_D2R_P13 NC_PEG_D2R_P13 TRUE 15 9 NC_PEG_D2R_P14 NC_PEG_D2R_P14 TRUE 15 9 NC_PEG_D2R_P15 NC_PEG_D2R_P15 TRUE 15 9 NC_PEG_R2D_C_N4 NC_PEG_R2D_C_N4 TRUE NC_PEG_R2D_C_N5 TRUE 15 9 NC_PEG_R2D_C_N6 NC_PEG_R2D_C_N6 TRUE 15 9 NC_PEG_R2D_C_N7 NC_PEG_R2D_C_N7 TRUE 15 9 NC_PEG_R2D_C_N8 NC_PEG_R2D_C_N8 TRUE 15 9 NC_PEG_R2D_C_N9 NC_PEG_R2D_C_N9 TRUE 9 41 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE 15 9 NC_PEG_R2D_C_N10 NC_PEG_R2D_C_N10 15 9 NC_PEG_R2D_C_N11 NC_PEG_R2D_C_N11 9 41 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE NC_PEG_R2D_C_N13 TRUE NC_PEG_R2D_C_N14 NC_PEG_R2D_C_N14 TRUE 15 9 NC_PEG_R2D_C_N15 NC_PEG_R2D_C_N15 TRUE NC_PEG_R2D_C_P4 NC_PEG_R2D_C_P4 TRUE 15 9 NC_PEG_R2D_C_P5 NC_PEG_R2D_C_P5 TRUE 15 9 NC_PEG_R2D_C_P6 NC_PEG_R2D_C_P6 TRUE 15 9 NC_PEG_R2D_C_P7 NC_PEG_R2D_C_P7 TRUE 15 9 NC_PEG_R2D_C_P8 NC_PEG_R2D_C_P8 TRUE 15 9 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE MAKE_BASE=TRUE NC_PEG_R2D_C_P9 15 9 NC_PEG_R2D_C_P10 NC_PEG_R2D_C_P10 TRUE 15 9 NC_PEG_R2D_C_P11 NC_PEG_R2D_C_P11 TRUE 15 9 NC_PEG_R2D_C_P12 NC_PEG_R2D_C_P12 TRUE 15 9 NC_PEG_R2D_C_P13 NC_PEG_R2D_C_P13 TRUE 15 9 NC_PEG_R2D_C_P14 NC_PEG_R2D_C_P14 TRUE 15 9 NC_PEG_R2D_C_P15 NC_PEG_R2D_C_P15 TRUE 9 41 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE TRUE TRUE NC_CK505_SRC_CLKREQ4_LTRUE 9 15 29 9 NC_CK505_SRC7_N NC_CK505_SRC7_N TRUE 9 15 29 9 NC_CK505_SRC7_P NC_CK505_SRC7_P TRUE 9 15 29 9 NC_CK505_PGMODE NC_CK505_PGMODE TRUE 9 15 29 9 NC_CK505_SRC8_N NC_CK505_SRC8_N TRUE 9 15 29 9 NC_CK505_SRC8_P NC_CK505_SRC8_P TRUE 9 15 29 9 NC_CK505_SRC_CLKREQ8_L MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NC_CK505_SRC_CLKREQ8_LTRUE 69 40 24 9 7 6 USB_IR_P 9 29 69 40 24 9 7 6 USB_IR_N MAKE_BASE=TRUE 9 15 NC_GPU_STOP_L 29 9 NC_GPU_STOP_L USB_IR_P MAKE_BASE=TRUE 9 29 69 40 24 9 7 6 USB2_WSPRING_P 9 29 69 40 24 9 7 6 USB2_WSPRING_N MAKE_BASE=TRUE 9 15 29 9 NC_CK505_PCI1_CLK NC_CK505_PCI1_CLK TRUE 9 15 29 9 NC_CK505_PCI2_CLK NC_CK505_PCI2_CLK TRUE 9 15 29 9 NC_CK505_PCI4_CLK NC_CK505_PCI4_CLK TRUE MAKE_BASE=TRUE 69 40 24 9 7 6 USB2_WSPRING_P 6 7 9 24 40 69 USB2_WSPRING_P 6 7 9 24 40 69 MAKE_BASE=TRUE 69 40 24 9 7 6 USB2_WSPRING_N USB2_WSPRING_N 6 7 9 24 40 69 MAKE_BASE=TRUE 9 29 MAKE_BASE=TRUE USB PORT [6] = BLUETOOTH 9 29 MAKE_BASE=TRUE 9 29 MAKE_BASE=TRUE 9 29 MAKE_BASE=TRUE 69 24 9 NC_USB_BT_P 69 24 9 NC_USB_BT_P 69 24 9 NC_USB_BT_N 69 24 9 NC_USB_BT_N NC_USB_BT_P 9 24 69 MAKE_BASE=TRUE NC_USB_BT_N 9 24 69 MAKE_BASE=TRUE 9 29 MAKE_BASE=TRUE 9 29 USB PORT [7] = Unused MAKE_BASE=TRUE 9 29 MAKE_BASE=TRUE 9 29 69 24 9 NC_USB2_EXTB_P NC_USB2_EXTB_P 9 24 69 MAKE_BASE=TRUE 69 24 9 NC_USB2_EXTB_N NC_USB2_EXTB_N 9 24 69 MAKE_BASE=TRUE 9 29 24 13 9 7 6 EXTBUSB_OC_L 13 9 7 6 24 EXTBUSB_OC_L MAKE_BASE=TRUE 9 29 MAKE_BASE=TRUE 9 29 C 6 7 9 13 24 USB PORT [8] = Unused 9 29 TP_USB_EXCARD_P TP_USB_EXCARD_P 9 24 69 69 24 9 MAKE_BASE=TRUE 69 24 9 9 15 EXTBUSB_OC_L MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 6 7 9 24 40 69 USB PORT [5] = Trackpad(Wellspring) 9 29 MAKE_BASE=TRUE USB_IR_N MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE USB_IR_P USB_IR_N MAKE_BASE=TRUE TRUE 9 15 69 9 29 MAKE_BASE=TRUE MAKE_BASE=TRUE 40 24 9 7 6 TP_USB_EXCARD_N TP_USB_EXCARD_N 9 24 69 MAKE_BASE=TRUE 9 15 USB PORT [9] = Unused MAKE_BASE=TRUE SB ALIASES 9 15 MAKE_BASE=TRUE 9 15 28 25 9 6 MAKE_BASE=TRUE 9 15 VR_PWRGD_CK505 VR_PWRGD_CK505 6 9 25 28 TP_USB_EXTC_N TP_USB_EXTC_N 9 24 69 MAKE_BASE=TRUE MAKE_BASE=TRUE PM_SB_PWROK PM_SB_PWROK 70 PCI_AD<0.0OD2.4H-0. INC.3> NC_PCI_C_BE_L<0.0OD2.0OD2.20 MM MIN_LINE_WIDTH=0.0 Port A NO-CONNECT UNUSED SATA INTERFACE PORTS NO_TEST MAKE_BASE=TRUE D 1 SATA ALIASES NO-CONNECT UNUSED LVDS INTERFACE PORTS 1 EMI-SPRING 2 3 4 5 B..5-THNP 1 4.5-THNP 1 41 9 TRUE 69 MAKE_BASE=TRUE MAKE_BASE=TRUE 67 9 39 24 9 6 69 39 24 9 6 39 24 39 24 13 9 7 6 EXTAUSB_OC_L 13 9 7 6 69 39 24 9 6 USB2_EXTA_N 69 36 24 9 6 MAKE_BASE=TRUE TRUE 69 39 24 9 6 USB2_EXTA_P MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE STANDOFFS Z0900 4.0H-M2X0.0OD2.30 MM SIZE DRAWING NUMBER D APPLE INC.0H-M2X0.0.. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART GND SMC_SMS_INT 48 41 9 6 MAKE_BASE=TRUE SMC_ADAPTER_EN 42 41 36 9 6 SMC_SMS_INT 6 9 41 48 SMC_ADAPTER_EN 6 9 36 41 42 VOLTAGE=0V MIN_NECK_WIDTH=0.31> NC_PCI_AD<0.3>TRUE NC_PCI_PAR NC_PCI_PAR TP_PCI_RST_L TP_PCI_RST_L 28 25 9 6 TP_USB_EXTC_P 9 24 69 MAKE_BASE=TRUE 69 24 9 MAKE_BASE=TRUE 9 15 TP_USB_EXTC_P 69 24 9 NO-CONNECT UNUSED INTERFACE PORTS 9 15 6 9 25 28 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE 9 15 9 15 70 9 15 70 24 9 9 15 24 9 6 MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE TRUE 24 70 MAKE_BASE=TRUE 24 MAKE_BASE=TRUE 9 24 70 MAKE_BASE=TRUE 6 9 24 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE 9 15 NB ALIASES MAKE_BASE=TRUE 9 15 9 15 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE 9 15 9 15 MAKE_BASE=TRUE 9 15 9 15 GFX_VR_EN VR_PWRGOOD_DELAY 71 30 29 16 9 6 NB_CLK96M_DOT_P NB_CLK96M_DOT_N 71 30 29 16 9 6 71 30 29 16 9 6 NB_CLK100M_DPLLSS_P 71 30 29 16 9 6 NB_CLK100M_DPLLSS_N 53 16 9 6 52 28 16 9 6 GFX_VR_EN 6 9 16 53 VR_PWRGOOD_DELAY MAKE_BASE=TRUE NB_CLK96M_DOT_P NB_CLK96M_DOT_N NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N MAKE_BASE=TRUE 6 9 16 28 52 6 9 16 29 30 71 MAKE_BASE=TRUE 6 9 16 29 30 71 MAKE_BASE=TRUE 6 9 16 29 30 71 MAKE_BASE=TRUE 6 9 16 29 30 71 MAKE_BASE=TRUE MAKE_BASE=TRUE 9 15 B MAKE_BASE=TRUE 9 15 9 15 64 15 9 6 LCDBKLT_PWM_UNBUF LCDBKLT_PWM_UNBUF 9 15 64 15 9 6 LCDBKLT_PWREN LCDBKLT_PWREN MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 6 9 15 64 6 9 15 64 9 15 MAKE_BASE=TRUE NC_PEG_R2D_C_P9 9 41 MAKE_BASE=TRUE NC_CK505_SRC4_P 29 9 NC_CK505_SRC_CLKREQ4_L MAKE_BASE=TRUE 15 9 9 41 NC_CK505_SRC4_P 9 15 MAKE_BASE=TRUE 15 9 9 41 NC_CK505_SRC4_N 29 9 MAKE_BASE=TRUE NC_PEG_R2D_C_N12 9 41 MAKE_BASE=TRUE TRUE NC_PEG_R2D_C_N13 9 41 MAKE_BASE=TRUE TRUE NC_PEG_R2D_C_N12 9 41 MAKE_BASE=TRUE NC_CK505_SRC_CLKREQ3_LTRUE NC_CK505_SRC4_N 9 15 MAKE_BASE=TRUE 15 9 9 41 29 9 TRUE MAKE_BASE=TRUE 15 9 9 41 MAKE_BASE=TRUE 29 9 NC_CK505_SRC_CLKREQ3_L 9 15 MAKE_BASE=TRUE NC_PEG_R2D_C_N5 9 41 MAKE_BASE=TRUE 9 15 TRUE 9 29 MAKE_BASE=TRUE MAKE_BASE=TRUE 15 9 9 41 MAKE_BASE=TRUE NC_CK505_SRC3_P 29 9 MAKE_BASE=TRUE 15 9 9 41 NC_CK505_SRC3_P 9 15 MAKE_BASE=TRUE TRUE 15 9 9 41 MAKE_BASE=TRUE NC_CK505_SRC3_N USB PORT [4] = IR CONTROLLER 9 29 MAKE_BASE=TRUE MAKE_BASE=TRUE 15 9 9 41 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NC_CK505_SRC_CLKREQ1_LTRUE NC_CK505_SRC3_N 29 9 MAKE_BASE=TRUE 15 9 9 41 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE 15 9 9 41 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE MAKE_BASE=TRUE 15 9 15 9 TRUE MAKE_BASE=TRUE 15 9 NC_PEG_D2R_P7 TRUE NC_CK505_SRC1_P MAKE_BASE=TRUE NC_PEG_D2R_N8 NC_PEG_D2R_P7 NC_CK505_SRC1_N NC_CK505_SRC1_P MAKE_BASE=TRUE 15 9 9 41 MAKE_BASE=TRUE TRUE NC_PEG_D2R_N5 9 41 MAKE_BASE=TRUE TRUE NC_PEG_D2R_N5 9 41 MAKE_BASE=TRUE NC_PEG_D2R_N4 NC_CK505_SRC1_N 29 9 29 9 NC_CK505_SRC_CLKREQ1_L MAKE_BASE=TRUE 15 9 9 41 MAKE_BASE=TRUE NC_PEG_D2R_N4 29 9 9 15 9 15 MAKE_BASE=TRUE TRUE 9 15 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE 9 15 MAKE_BASE=TRUE MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE TRUE TRUE TRUE TRUE TRUE 9 41 MAKE_BASE=TRUE 9 41 AUDIO ALIASES MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE 9 41 69 37 23 9 7 6 HDA_BIT_CLK 9 41 69 37 23 9 7 6 HDA_SYNC HDA_SYNC 9 41 69 37 23 9 6 HDA_RST_L HDA_RST_L MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE TRUE TRUE MAKE_BASE=TRUE HDA_BIT_CLK 9 41 69 37 23 9 7 6 HDA_SDIN0 HDA_SDIN0 9 41 69 37 23 9 7 6 HDA_SDOUT HDA_SDOUT MAKE_BASE=TRUE 6 7 9 23 37 69 MAKE_BASE=TRUE 6 7 9 23 37 69 MAKE_BASE=TRUE 6 9 23 37 69 MAKE_BASE=TRUE 6 7 9 23 37 69 MAKE_BASE=TRUE TRUE TRUE SIGNAL ALIAS /RESET 6 7 9 23 37 69 MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 9 41 MAKE_BASE=TRUE SYNC_MASTER=(MASTER) 9 41 SYNC_DATE=(MASTER) MAKE_BASE=TRUE 9 41 NOTICE OF PROPRIETARY PROPERTY MAKE_BASE=TRUE TRUE 9 41 MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.0 OF 9 1 73 A .4H-0.0OD2. MAKE_BASE=TRUE 7 6 5 4 3 2 REV.0H-M2X0.0OD2.

9 1 PLACEMENT_NOTE=Place R1024 near ITP connector (if present) 1 1 DATA GRP 2 BI OMIT A3* ADS* A4* BNR* MEROM_SFF (1 OF 8) BPRI* A5* BGA A6* A7* DEFER* A8* DRDY* A9* DBSY* A10* A11* BR0* A12* A13* IERR* A14* INIT* A15* A16* LOCK* ADSTB0* DATA GRP 0 66 14 P2 V4 W1 T4 AA1 AB4 T2 AC5 AD2 AD4 AA5 AE5 AB2 AC1 Y4 DATA GRP 3 FSB_A_L<4> 2 3 4 5 DATA GRP1 FSB_A_L<3> BI CONTROL BI 66 14 ADDR GROUP0 66 14 XDP/ITP SIGNALS D 6 7 ADDR GROUP1 8 66 30 6 OUT CPU_BSEL<0> 66 30 6 OUT CPU_BSEL<1> 66 30 6 OUT CPU_BSEL<2> A37 C37 B38 BSEL0 BSEL1 BSEL2 AP44 AR43 AH40 AF40 AJ43 AG41 AF44 AH44 AM44 AN43 AM40 AK40 AG43 AP40 AN41 AL41 AK44 AL43 AJ41 D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* AV38 AT44 AV40 AU41 AW41 AR41 BA37 BB38 AY36 AT40 BC35 BC39 BA41 BB40 BA35 AU43 AY40 AY38 BC37 COMP0 COMP1 COMP2 COMP3 AE43 AD44 AE1 AF2 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI* G7 B8 C41 E7 D10 BD10 FSB_D_L<32> BI 14 66 FSB_D_L<33> BI 14 66 FSB_D_L<34> BI 14 66 FSB_D_L<35> BI 14 66 FSB_D_L<36> BI 14 66 FSB_D_L<37> BI 14 66 FSB_D_L<38> BI 14 66 FSB_D_L<39> BI 14 66 FSB_D_L<40> BI 14 66 FSB_D_L<41> BI 14 66 FSB_D_L<42> BI 14 66 FSB_D_L<43> BI 14 66 FSB_D_L<44> BI 14 66 FSB_D_L<45> BI 14 66 FSB_D_L<46> BI 14 66 FSB_D_L<47> BI 14 66 FSB_DSTB_L_N<2> BI 14 66 FSB_DSTB_L_P<2> BI 14 66 FSB_DINV_L<2> BI 14 66 FSB_D_L<48> BI 14 66 FSB_D_L<49> BI FSB_D_L<50> 14 66 LAYOUT NOTE: BI 14 66 COMP0.9 14 66 BI BI R1002 6 23 66 XDP_BPM_L<1> XDP_BPM_L<4> 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 2 201 B40 D8 BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* R1005 NC_CPU_RSVD13 1K 1% 1/20W MF 201 NC_CPU_RSVD14 2 0.3 CONNECT WITH ZO=55OHM. INC.4 2 27.FSB_A_L<5> 66 14 BI FSB_A_L<6> 66 14 BI FSB_A_L<7> 66 14 BI FSB_A_L<8> 66 14 BI FSB_A_L<9> 66 14 BI FSB_A_L<10> 66 14 BI FSB_A_L<11> 66 14 BI FSB_A_L<12> 66 14 BI FSB_A_L<13> 66 14 BI FSB_A_L<14> 66 14 BI FSB_A_L<15> 66 14 BI FSB_A_L<16> 66 14 BI FSB_ADSTB_L<0> 66 14 BI FSB_REQ_L<0> 66 14 BI FSB_REQ_L<1> 66 14 BI FSB_REQ_L<2> 66 14 BI FSB_REQ_L<3> 66 14 BI FSB_REQ_L<4> 66 14 BI FSB_A_L<17> 66 14 BI FSB_A_L<18> BI FSB_A_L<19> 66 14 BI FSB_A_L<20> 66 14 BI FSB_A_L<21> 66 14 BI FSB_A_L<22> 66 14 BI FSB_A_L<23> 66 14 BI FSB_A_L<24> 66 14 BI FSB_A_L<25> 66 14 66 14 C BI FSB_A_L<26> 66 14 BI FSB_A_L<27> 66 14 BI FSB_A_L<28> 66 14 BI FSB_A_L<29> R1 R5 U1 P4 W5 BI FSB_A_L<30> 66 14 BI FSB_A_L<31> 66 14 BI FSB_A_L<32> 66 14 BI FSB_A_L<33> 66 14 BI FSB_A_L<34> 66 14 BI FSB_A_L<35> 66 14 BI FSB_ADSTB_L<1> 66 14 66 23 6 66 23 6 66 23 6 AN1 AK4 AG1 AT4 AK2 AT2 AH2 AF4 AJ5 AH4 AM4 AP4 AR5 AJ1 AL1 AM2 AU5 AP2 AR1 AN5 C7 D4 F10 IN CPU_A20M_L OUT CPU_FERR_L IN CPU_IGNNE_L U1000 REQ0* REQ1* REQ2* REQ3* REQ4* A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* M4 J5 L5 FSB_ADS_L BI 14 66 FSB_BNR_L BI 14 66 FSB_BPRI_L BI 14 66 N5 F38 J1 FSB_DEFER_L BI 14 66 FSB_DRDY_L BI 14 66 FSB_DBSY_L BI 14 66 M2 FSB_BREQ0_L BI 14 66 PP1V05_S0 CPU_IERR_L CPU_INIT_L IN N1 FSB_LOCK_L BI RESET* RS0* RS1* RS2* TRDY* G5 K2 H4 K4 L1 FSB_CPURST_L IN 6 13 14 66 FSB_RS_L<0> IN 14 66 FSB_RS_L<1> IN 14 66 FSB_RS_L<2> IN 14 66 FSB_TRDY_L IN 14 66 HIT* HITM* H2 F2 FSB_HIT_L BI 14 66 FSB_HITM_L BI 14 66 AY8 BA7 BA5 AY2 AV10 AV2 AV4 AW7 AU1 AW5 AV8 XDP_BPM_L<0> 6 7 13 66 BI 6 7 13 66 XDP_BPM_L<2> BI 6 7 13 66 XDP_BPM_L<3> BI 6 7 13 66 IN CPU_STPCLK_L 66 23 6 IN CPU_INTR IN CPU_NMI IN CPU_SMI_L 66 23 6 66 23 6 28 13 7 6 OUT F8 C9 C5 E5 E37 D40 C43 AE41 AY10 AC43 NC_CPU_TEST1 NC_CPU_TEST2 NC_CPU_TEST3 NC_CPU_TEST4 NC_CPU_TEST5 NC_CPU_TEST6 B J7 XDP_DBRESET_L 1% 1/20W MF D OMIT PP1V05_S0 1 54. MAKE FSB_D_L<53> BI 14 66 TRACE LENGTH SHORTER THAN 0. FSB_D_L<52> BI 14 66 COMP1.2 CONNECT WITH ZO=27.5". FSB_D_L<54> BI 14 66 FSB_D_L<55> BI 14 66 FSB_D_L<56> BI 14 66 FSB_D_L<57> BI 14 66 FSB_D_L<58> BI 14 66 FSB_D_L<59> BI 14 66 FSB_D_L<60> BI 14 66 FSB_D_L<61> BI 14 66 FSB_D_L<62> BI 14 66 FSB_D_L<63> BI 14 66 FSB_DSTB_L_N<3> BI 14 66 FSB_DSTB_L_P<3> BI 14 66 FSB_DINV_L<3> BI 14 66 66 6 CPU_COMP<0> 66 6 CPU_COMP<1> 66 6 CPU_COMP<2> 66 6 C R1016 1 54.9 2 1% 1/20W MF 201 1 CPU_COMP<3> CPU_DPRSTP_L IN 6 16 23 52 66 CPU_DPSLP_L IN 6 23 66 FSB_DPWR_L IN 14 66 CPU_PWRGD IN 6 13 23 66 FSB_CPUSLP_L IN 14 66 B R1018 1 R1019 54. MAKE FSB_D_L<51> BI 14 66 TRACE LENGTH SHORTER THAN 0.9 2 1% 1/20W MF 201 R1017 1 27.9 2 1% 1/20W MF 201 1% 1/20W MF 201 CPU FSB A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.0 OF 10 1 73 A .4 2 1% 1/20W MF 201 1% 1/20W MF 201 NC_CPU_PSI_L 2 1% 1/20W MF 201 R1022 66 13 10 7 6 1 XDP_TCK R1023 66 13 10 7 6 1 XDP_TRST_L 649 2 54.4OHM.9 PP1V05_S0 2 R1024 54. 051-7230 B.0. SCALE SHT NONE 8 7 6 5 4 3 2 REV.5" MAX LENGTH FOR CPU_GTLREF 66 6 CPU_GTLREF F40 G43 E43 J43 H40 H44 G39 E41 L41 K44 N41 T40 M40 G41 M44 L43 K40 J41 P40 D0* D32* D1* D33* D2* MEROM_SFF D34* (2 OF 8) BGA D3* D35* D4* D36* D5* D37* D6* D38* D7* D39* D8* D40* D9* D41* D10* D42* D11* D43* D12* D44* D13* D45* D14* D46* D15* D47* DSTBN0* DSTBN2* DSTBP0* DSTBP2* DINV0* DINV2* U1000 P44 V40 V44 AB44 R41 W41 N43 U41 AA41 AB40 AD40 AC41 AA43 Y40 Y44 T44 U43 W43 R43 D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* AW43 GTLREF MISC 1 R1006 2K R1020 66 13 10 7 6 54.5".9 1% 1/20W MF 201 6 7 13 66 2 FSB_D_L<2> BI FSB_D_L<3> 66 14 BI FSB_D_L<4> 66 14 BI FSB_D_L<5> BI FSB_D_L<6> 66 14 FSB_D_L<8> XDP_TDI IN 6 7 10 13 66 66 14 BI FSB_D_L<9> XDP_TDO OUT 6 7 10 13 66 66 14 BI FSB_D_L<10> XDP_TMS IN 6 7 10 13 66 66 14 BI FSB_D_L<11> XDP_TRST_L IN 6 7 10 13 66 66 14 BI FSB_D_L<12> CPU_PROCHOT_L TO SMC B10 CPU_THERMD_P OUT 6 46 66 CPU_THERMD_N OUT 6 46 66 PM_THRMTRIP_L OUT 6 16 23 42 66 AND CPU VR TO INFORM 66 14 BI FSB_D_L<13> CPU IS HOT 66 14 BI FSB_D_L<14> 66 14 BI FSB_D_L<15> 66 14 BI FSB_DSTB_L_N<0> 66 14 BI FSB_DSTB_L_P<0> 66 14 BI FSB_DINV_L<0> 66 14 BI FSB_D_L<16> 66 14 BI FSB_D_L<17> 66 14 5% 1/20W MF 201 OUT 6 42 52 66 PM_THRMTRIP# ICH AND GMCH H CLK WITHOUT T-ING (NO STUB) FSB_CLK_CPU_P FSB_CLK_CPU_N BI FSB_D_L<19> 66 14 BI FSB_D_L<20> 66 14 BI FSB_D_L<21> 6 29 30 71 66 14 BI IN 6 29 30 71 66 14 BI FSB_D_L<23> 66 14 BI FSB_D_L<24> 66 14 BI FSB_D_L<25> 66 14 BI FSB_D_L<26> 66 14 BI FSB_D_L<27> 66 14 BI FSB_D_L<28> NC_CPU_RSVD9 1 NC_CPU_RSVD12 BI FSB_D_L<29> 66 14 BI FSB_D_L<30> 66 14 BI FSB_D_L<31> 66 14 BI FSB_DSTB_L_N<1> 66 14 BI FSB_DSTB_L_P<1> 66 14 BI FSB_DINV_L<1> 66 14 21 19 18 14 13 12 11 10 8 7 6 PP1V05_S0 72 54 42 30 27 26 23 NC_CPU_RSVD11 FSB_D_L<18> IN NC_CPU_RSVD7 NC_CPU_RSVD10 BI 66 14 FSB_D_L<22> DBR* TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 BI 66 14 BI CPU_PROCHOT_L J9 F4 H8 V2 Y2 AG5 AL5 66 14 BI BI SHOULD CONNECT TO RSVD7 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 FSB_D_L<1> 66 14 D38 BB34 BD34 A35 C35 BI 6 7 10 13 66 2 BCLK0 BCLK1 66 14 IN 68 STPCLK* LINT0 LINT1 SMI* FSB_D_L<0> XDP_TCK THERMAL THERMTRIP* BI FSB_D_L<7> R1004 A20M* FERR* IGNNE* 66 14 66 14 6 7 13 66 1 PROCHOT* THRMDA THRMDC 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 R1003 XDP_BPM_L<5> ICH 66 23 6 54. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.9 1 XDP_TMS 66 13 10 7 6 66 13 10 7 6 1 XDP_TDI 2 1% 1/20W MF 201 XDP_TDO 1% 1/20W MF 201 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 2 1% 1/20W MF 201 R1021 54.

0. INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.05V) 2.5 ONLY 6 7 8 12 22 26 27 54 72 CPU_VID<0> OUT 6 12 52 66 CPU_VID<1> OUT 6 12 52 66 CPU_VID<2> OUT 6 12 52 66 CPU_VID<3> OUT 6 12 52 66 CPU_VID<4> OUT 6 12 52 66 CPU_VID<5> OUT 6 12 52 66 CPU_VID<6> OUT 6 12 52 66 PPVCORE_S0_CPU (7 OF 8) OMIT U1000 BGA VCC VCC K20 M16 M18 K16 K18 V20 T20 P20 V16 V18 T16 T18 P16 P18 AD20 AB20 Y20 AD16 AD18 AB16 AB18 Y16 Y18 AK20 AK16 AK18 AH20 AF20 AH16 AH18 AF16 AF18 AP20 AM20 AP16 AP18 AM16 AM18 AY20 AV20 AT20 AY16 AY18 AV16 AV18 AT16 AT18 BD20 BB20 BD16 BD18 BB16 BB18 AP14 AM14 AY14 AV14 AT14 BD14 BB14 6 7 8 11 12 52 65 72 1 R1100 100 BD12 1% 1/20W MF AE37 AP38 AN37 AL37 C33 B32 H36 F36 G35 F34 E33 E35 D32 K36 N35 L35 J35 W35 V36 P36 U35 R35 AB36 AC35 AA35 AK36 AF36 AJ35 AG35 AE35 AP36 AN35 AL35 C13 B14 B12 H12 H14 G11 G13 F12 F14 E11 E13 D14 D12 K10 N11 N13 M14 L11 L13 K12 K14 J11 J13 V10 P10 W11 W13 V12 V14 U11 U13 T14 R11 (8 OF 8) OMIT U1000 BGA VCCP VCCP R13 P12 P14 AB10 AD14 AC11 AC13 AB12 AB14 AA11 AA13 Y14 AK10 AF10 AK12 AK14 AJ11 AJ13 AH14 AG11 AG13 AF12 AF14 AE11 AE13 AP10 AR11 AR13 AP12 AN11 AN13 AL11 AL13 AU11 AU13 N7 N9 L7 L9 W7 W9 U7 U9 R7 R9 AC7 AC9 AA7 AA9 AJ7 AJ9 AG7 AG9 AE7 AE9 AR7 AR9 AN7 AN9 AL7 AL9 A33 A13 27 30 42 54 72 6 7 8 10 11 12 13 14 18 19 21 23 26 Y6 Y8 AK6 AK8 AH6 AH8 AF6 AF8 AP6 AP8 AM6 AM8 AY6 AW9 AU7 AV6 AU9 AT6 AT8 BD6 BC9 BB6 BA9 C3 B4 G3 E3 D2 N3 L3 J3 W3 U3 R3 AC3 AA3 (6 OF 8) OMIT U1000 BGA VSS 2 201 BC13 CPU_VCCSENSE_P CPU_VCCSENSE_N OUT OUT 1 LAYOUT NOTE: R1101 PLACE R1100 AND R1101 100 LAYOUT NOTE: CPU_VCCSENSE_P/CPU_VCCSENSE_N USE ZO=27.5V) 0.130A VCCA VID VCCSENSE VSSSENSE PP1V5_S0 B34 D34 BD8 BC7 BB10 BB8 BC5 BB4 AY4 VCCA=1. 051-7230 B.D C B (3 BGA OF 8) VCC VCC 29A AD28 AD30 AB28 AB30 Y28 Y30 AK26 AH26 AF26 AK28 AK30 AH28 AH30 AF28 AF30 AP26 AM26 AP28 AP30 AM28 AM30 AY26 AV26 AT26 AY28 AY30 AV28 AV30 AT28 AT30 BD26 BB26 BD28 (CPU IO POWER 1. SCALE SHT NONE 8 7 6 5 4 3 2 REV. 2 6 52 66 6 52 66 1% 1/20W MF 201 WITHIN 1 INCH OF CPU W/ NO STUB VSS AJ3 AG3 AE3 AR3 AN3 AL3 AW3 AU3 BD4 BC3 BB2 BA3 G1 E1 AW1 BA1 A39 A41 A31 A27 A29 A21 A23 A25 A17 A19 A15 A11 A9 A5 A7 B42 H42 F42 D42 D44 F44 M42 K42 V42 T42 P42 AD42 AB42 Y42 AK42 AH42 AF42 AP42 AM42 AY42 AV42 AT42 AV44 AY44 BB42 BA43 C39 H38 G37 E39 N39 M38 L39 J39 W39 U39 T38 R39 AD38 AC39 AA39 Y38 AJ39 AH38 AG39 AE39 AR37 AR39 AN39 AM38 AL39 AW37 AW39 AU37 AU39 AT38 BD38 BD40 BC41 BA39 B36 D36 H34 M36 M34 K34 T36 V34 T34 P34 AD36 Y36 AD34 AB34 Y34 AK34 AH36 AH34 AF34 AR35 AM36 1 (4 OF 8) OMIT U1000 BGA VSS VSS AP34 AM34 AV36 AT36 AY34 AW33 AW35 AV34 AU35 BD36 BB36 BC33 BA33 C31 C29 C27 G31 E31 G27 G29 E27 E29 N31 L31 J31 N27 N29 L27 L29 J27 J29 W31 W27 W29 U31 R31 U27 U29 R27 R29 AC31 AA31 AC27 AC29 AA27 AA29 AJ31 AG31 AE31 AJ27 AJ29 AG27 AG29 AE27 AE29 AR31 AR27 AR29 AN31 AL31 AN27 AN29 AL27 AL29 AW31 AU31 AW27 AW29 AU27 AU29 BC31 BA31 BC27 BC29 BA27 BA29 C25 C23 C21 G21 G23 G25 E21 E23 E25 N21 N23 N25 L21 L23 L25 J21 J23 J25 W21 W23 W25 U21 U23 U25 R21 R23 R25 AC21 AC23 AC25 AA21 AA23 AA25 AJ21 AJ23 AJ25 AG21 AG23 AG25 AE21 AE23 AE25 AR21 AR23 AR25 AN21 AN23 AN25 AL21 AL23 AL25 AW21 AW23 AW25 AU21 AU23 AU25 BC21 BC23 BC25 BA21 BA23 BA25 C19 C17 G17 G19 E17 E19 N17 N19 L17 L19 J17 J19 W17 W19 U17 U19 R17 R19 AC17 AC19 AA17 AA19 AJ17 AJ19 AG17 AG19 LAYOUT NOTE: (5 OF 8) OMIT U1000 BGA MEROM_SFF OMIT U1000 MEROM_SFF BD30 BB28 BB30 B24 B22 H22 H24 F22 F24 D24 D22 M22 M24 K22 K24 V22 V24 T22 T24 P22 P24 AD22 AD24 AB22 AB24 Y22 Y24 AK22 AK24 AH22 AH24 AF22 AF24 AP22 AP24 AM22 AM24 AY22 AY24 AV22 AV24 AT22 AT24 BD22 BD24 BB22 BB24 B20 B18 B16 H20 F20 D20 H16 H18 F16 F18 D18 D16 M20 6 7 8 11 12 52 65 72 (CPU CORE POWER) H32 G33 F32 N33 M32 L33 K32 J33 W33 V32 U33 T32 R33 P32 AD32 AC33 AB32 AA33 Y32 AK32 AJ33 AH32 AG33 AF32 AE33 AR33 AP32 AN33 AM32 AL33 AY32 AV32 AU33 AT32 AT34 BD32 BB32 B26 B30 B28 H26 F26 D26 H28 H30 F28 F30 D30 D28 M26 K26 M28 M30 K28 K30 V26 T26 P26 V28 V30 T28 T30 P28 P30 AD26 AB26 Y26 PP1V05_S0 MEROM_SFF PPVCORE_S0_CPU 2 3 4 5 PPVCORE_S0_CPU MEROM_SFF 72 65 52 12 11 8 7 6 MEROM_SFF 6 7 MEROM_SFF 8 VSS VSS AE17 AE19 AR17 AR19 AN17 AN19 AL17 AL19 AW17 AW19 AU17 AU19 BC17 BC19 BA17 BA19 C15 C11 H10 G15 E15 M10 N15 L15 J15 M12 T10 W15 U15 R15 T12 AD10 Y10 AC15 AA15 AD12 Y12 AH10 AJ15 AG15 AE15 AH12 AM10 AR15 AN15 AL15 AM12 AT10 AW15 AU15 AY12 AW11 AW13 AV12 AT12 BC15 BA15 BC11 BB12 BA11 BA13 B6 H6 G9 F6 E9 D6 M6 M8 K6 K8 U5 V6 V8 T6 T8 P6 P8 AD6 AD8 AB6 AB8 D C B PROVIDE A TEST POINT (WITH NO STUB) TO CONNECT A DIFFERENTIAL PROBE BETWEEN VCCSENSE AND VSSSENSE CPU Power & Ground A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.5A VCCP N37 L37 K38 J37 W37 V38 U37 R37 P38 AC37 AB38 AA37 AK38 AJ37 AG37 AF38 PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 (CPU INTERNAL PLL POWER 1.4 OHM DIFFERENTIAL TRACE ROUTING.0 OF 11 1 73 A .

2UF 2.2UF 2.3V X5R 603 OMIT 20% 6.2UF 20% 6.3V X5R 603 C1225 20% 6.2UF C1280 20% 6.3V CERM 402-LF CRITICAL 2.3V CERM 402-LF 1 OMIT C1283 1 OMIT C1284 1 OMIT C1285 1 OMIT C1286 1 OMIT C1287 2.3V CERM 402-LF CRITICAL VCCP (CPU I/O) DECOUPLING 23 21 19 18 14 13 11 10 8 7 6 PP1V05_S0 72 54 42 30 27 26 1X 330UF.3V X5R 603 CRITICAL 10UF 20% 6.2UF 20% 2 6.2UF 20% 6.3V X5R 603 VCCA (CPU AVdd) DECOUPLING LAYOUT NOTE: OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT C1240 C1241 C1242 C1243 C1244 C1245 C1246 C1247 C1248 C1249 CRITICAL PLACE ON OPPOSITE SIDE OF CPU 2.3V CERM 402-LF 20% 6.3V X5R 603 CRITICAL 10UF 20% 6.3V X5R 603 OMIT OMIT PLACE ON OPPOSITE SIDE OF CPU C1230 C1231 10UF 20% 6.3V X5R 603 CRITICAL 10UF 20% 6.3V CERM 402-LF CRITICAL 2.3V X5R 603 10UF 20% 6.3V CERM 402-LF 2.3V CERM 402-LF 330UF 20% 2..3V CERM 402-LF CRITICAL 2.3V X5R 603 CRITICAL CRITICAL 10UF CRITICAL 10UF 20% 6.2UF 2.2UF 20% 6.2UF 20% 6.0V TANT D2T 20% 2.3V CERM 402-LF CRITICAL CRITICAL 2.0. 1x 0.2UF 20% 6.3V CERM 402-LF CRITICAL 2.0V TANT D2T 20% 2.2UF 20% 6.3V CERM 402-LF 20% 6.3V CERM 402-LF CRITICAL 2.3V X5R 603 OMIT OMIT CRITICAL 10UF 20% 6.2UF 20% 6.2UF 20% 6.3V CERM 402-LF CRITICAL 2. 051-7230 B.2UF 20% 6.2UF 20% 6.3V X5R 603 10% 10V X5R 201 LAYOUT NOTE: PLACE C1281 NEAR PIN B34 OF U1000 B B LAYOUT NOTE: OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT PLACE ON OPPOSITE SIDE OF CPU C1250 C1251 C1252 C1253 C1254 C1255 C1256 C1257 C1258 C1259 CRITICAL 2.2UF 20% 6.2UF 2.3V X5R 603 LAYOUT NOTE: CRITICAL C1222 20% 6.2UF 20% 6.3V CERM 402-LF 72 54 27 26 22 11 8 7 6 PP1V5_S0 1x 10uF.6> MAKE_BASE=TRUE CRITICAL CRITICAL C1220 PLACE ON OPPOSITE SIDE OF CPU CRITICAL C1229 C 20% 6.2UF 20% 6.3V CERM 402-LF CRITICAL 2. SCALE SHT NONE 8 7 6 5 4 3 2 REV.0V TANT D2T 3 2 3 2 CPU Decoupling & VID PLACE C1291-C1296 CLOSE TO FSB DATA PINS LAYOUT NOTE: SYNC_MASTER=MSARWAR PLACE ON SAME SIDE AS CPU SYNC_DATE=04/26/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.2UF 2.3V CERM 402-LF 20% 6..3V CERM 402-LF 2 20% 6.2UF CRITICAL 2.3V CERM 402-LF 1 1 2 2 10uF C1281 0.01UF 20% 6.2UF 20% 6.3V CERM 402-LF CRITICAL 2.3V X5R 603 20% 6.3V CERM 402-LF 2 1 OMIT C1288 2.2UF 20% 6.3V CERM 402-LF CRITICAL 2.3V CERM 402-LF 20% 6.2UF 20% 6.6> 66 52 11 6 LAYOUT NOTE: OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT PLACE ON OPPOSITE SIDE OF CPU C1210 C1211 C1212 C1213 C1214 C1215 C1216 C1217 C1218 C1219 CRITICAL 10UF 20% 6. 12X 2.2UF 2.2UF 2.3V X5R 603 OMIT LAYOUT NOTE: C CRITICAL 10UF CRITICAL 10UF 20% 6.3V CERM 402-LF 20% 6.2UF 20% 6.3V CERM 402-LF CRITICAL 2.2UF 20% 6. INC.3V X5R 603 OMIT CRITICAL 10UF 20% 6.3V X5R 603 CRITICAL 10UF 20% 6.3V CERM 402-LF CRITICAL 2.2UF 20% 6.3V CERM 402-LF 20% 6.3V X5R 603 C1224 20% 6.3V CERM 402-LF CRITICAL 2. 28x 1uF 0402 Intel recommends 32+28 but is evaluating 24+24 72 65 52 11 8 7 6 PPVCORE_S0_CPU D D 10UF 0603 = APN:138S0568 = MURATA.TDK.2UF 20% 6.0 OF 12 1 73 A .3V X5R 603 CPU VCORE VID CONNECTIONS CPU_VID<0.3V X5R 603 CRITICAL 10UF 20% 6.3V CERM 402-LF LAYOUT NOTE: PLACE C1290 CLOSE TO CPU PLACE C1283-C1288 CLOSE TO FSB ADDRESS PINS LAYOUT NOTE: A CRITICAL 1 PLACE ON SAME SIDE AS CPU 3 2 CRITICAL 1 C1270 CRITICAL 1 C1271 C1272 330UF 330UF 330UF 20% 2.8 6 7 2 3 4 5 1 CPU VCORE HF AND BULK DECOUPLING 3x 330uF.3V X5R 603 20% 6.TAIYO.SAMSUNG LAYOUT NOTE: OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT C1200 C1201 C1202 C1203 C1204 C1205 C1206 C1207 C1208 C1209 CRITICAL PLACE ON OPPOSITE SIDE OF CPU 10UF 20% 6. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT Intel recommends 3x220UF @ 9mOHM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.3V X5R 603 CRITICAL 10UF 20% 6.3V CERM 402-LF 2.3V X5R 603 OMIT CRITICAL 10UF 20% 6.3V X5R 603 CRITICAL 10UF 20% 6.2UF 2.2UF 20% 6.3V X5R 603 OMIT CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 20% 6.3V CERM 402-LF 20% 6.3V CERM 402-LF 2 20% 6.3V X5R 603 C1228 20% 6.3V X5R 603 C1226 20% 6.3V X5R 603 66 10UF 10UF C1221 IMVP6_VID<0.3V X5R 603 OMIT CRITICAL 10UF 20% 6.3V X5R 603 OMIT CRITICAL 10UF 20% 6.3V CERM 402-LF 20% 6.2UF 2.3V CERM 402-LF CRITICAL 2.3V X5R 603 10UF 20% 6.3V CERM 402-LF 2.3V CERM 402-LF C1290 1 1 OMIT C1291 1 OMIT C1292 1 OMIT C1293 1 OMIT C1294 1 OMIT C1295 2.5V POLY CASE-C2-SM-1 2 2 2 2 2 2 1 OMIT C1296 2.3V CERM 402-LF 2 20% 6.3V CERM 402-LF CRITICAL CRITICAL 2. 32x 10uF 0603.2UF CRITICAL 2.3V X5R 603 OMIT 20% 6.3V CERM 402-LF 20% 2 6.2UF 20% 6.3V CERM 402-LF CRITICAL CRITICAL 2.3V X5R 603 C1223 20% 6.2UF 2 LAYOUT NOTE: OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT PLACE ON OPPOSITE SIDE OF CPU C1260 C1261 C1262 C1263 C1264 C1265 C1266 C1267 CRITICAL 2.2UF 20% 6.2UF 20% 6.3V CERM 402-LF CRITICAL CRITICAL 2.2UF 20% 6.3V X5R 603 C1227 20% 6.2UF 20% 6.2UF CRITICAL 2.01uF CRITICAL OMIT 2.

1UF 2 10% 6. 051-7230 B. INC.3V X5R 201 B B Direction of XDP module to edge of board Please avoid any obstructions eXtended Debug Port (XDP) A SYNC_MASTER=M75 SYNC_DATE=01/24/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.3V X5R 201 57 998-1571 2 NB_CFG<8> SMC_WAKE_SCI_L IN 6 7 16 IN 6 7 25 41 OBSDATA_C0 OBSDATA_C1 EXTAUSB_OC_L SB_GPIO40 IN 6 7 9 24 39 IN 6 7 24 OBSDATA_C2 OBSDATA_C3 USB_EXTD_OC_L WOW_EN IN 6 7 24 IN 6 7 24 36 (OBSDATA_A2) (OBSDATA_A3) NB_BSEL<2> NB_CFG<3> IN 6 7 16 30 66 IN 6 7 16 OBSDATA_D0 OBSDATA_D1 PM_LATRIGGER_L EXTGPU_LVDS_EN IN 6 7 24 IN 6 7 24 OBSDATA_D2 OBSDATA_D3 SB_GPIO30 EXTBUSB_OC_L IN 6 7 24 IN 6 7 9 24 ITPCLK/HOOK4 ITPCLK#/HOOK5 (VCC_OBS_CD) RESET#/HOOK6 DBR#/HOOK7 XDP_CLK_P XDP_CLK_N IN 6 7 29 30 66 71 IN 6 7 29 30 66 71 TDO TRSTn TDI TMS XDP_PRESENT# XDP XDP C1300 OBSFN_C0 OBSFN_C1 1 66 7 6 XDP_CPURST_L XDP_DBRESET_L XDP_TDO XDP_TRST_L XDP_TDI XDP_TMS NB CFG[8] SB GPIO[8] SB OC[0]# SB OC[1]# SB OC[2]# SB OC[3]# SB OC[4]# SB OC[5]# SB OC[6]# SB OC[7]# XDP R1303 1 OUT 6 7 10 28 IN 6 7 10 66 OUT 6 7 10 66 OUT 6 7 10 66 OUT 6 7 10 66 C NB CFG[2] NB CFG[3] 1K 2 FSB_CPURST_L IN 6 10 14 66 5% 1/20W MF 201 C1301 0. NB & SB debugging. 64 63 26 25 24 23 22 21 19 16 8 7 53 52 51 46 44 42 30 29 28 23 21 19 18 14 12 11 10 8 7 72 54 42 30 27 60 6 27 6 26 PP3V3_A_S0 PP1V05_S0 XDP XDP R13301 R1315 1 54.9 1% 1/20W MF 201 66 10 7 6 66 10 7 6 C NB CFG[0] NB CFG[1] NB CFG[4] NB CFG[5] NB CFG[6] NB CFG[7] 66 23 10 6 IN CPU_PWRGD XDP R1399 1 1K OUT IN 66 10 7 6 BI 66 10 7 6 IN 66 10 7 6 IN 66 10 7 6 IN 66 30 16 7 6 BI 66 30 16 7 6 IN 16 7 6 BI 16 7 6 IN 16 7 6 IN 16 7 6 IN 2 10K 5% 1/20W MF 201 2 2 XDP_BPM_L<5> XDP_BPM_L<4> XDP_PWRGD BI 15 7 6 BI 66 10 7 6 OUT XDP_OBS20 PWRGD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 LOCAL_CTRL_DATA LOCAL_CTRL_CLK SDA SCL TCK1 TCK0 XDP_TCK 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 OBSDATA_B2 OBSDATA_B3 7 6 15 7 6 F-ST-SM OBSDATA_B0 OBSDATA_B1 NB_CFG<6> NB_CFG<7> TP_XDP_HOOK2 TP_XDP_HOOK3 LTH-030-01-G-D-NOPEGS (OBSDATA_A0) (OBSDATA_A1) NB_CFG<4> NB_CFG<5> 7 5% 1/20W MF 2 201 OBSDATA_A2 OBSDATA_A3 NB_BSEL<0> NB_BSEL<1> 7 J1300 10K OBSDATA_A0 OBSDATA_A1 XDP_BPM_L<1> XDP_BPM_L<0> 7 6 CRITICAL XDP_CONN R1331 OBSFN_A0 OBSFN_A1 XDP_BPM_L<3> XDP_BPM_L<2> 5% 1/20W MF 201 XDP 1 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 48 47 50 49 52 51 54 53 NC 56 58 55 60 59 1 0.8 6 7 2 3 4 5 1 D D Mini-XDP Connector NOTE: This is not the standard XDP pinout. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. SCALE SHT NONE 8 7 6 5 4 3 2 REV.1UF 10% 6.0.0 OF 13 1 73 A . Use with 920-0451 adapter board to support CPU.

8 6 7 3 4 5 2 1 OMIT U1400 FSB_D_L<0> BI FSB_D_L<1> 66 10 BI FSB_D_L<2> D 66 10 BI FSB_D_L<3> 66 10 BI FSB_D_L<4> 66 10 BI FSB_D_L<5> 66 10 BI FSB_D_L<6> BI FSB_D_L<7> 66 10 BI FSB_D_L<8> 66 10 BI FSB_D_L<9> 66 10 BI FSB_D_L<10> 66 10 BI FSB_D_L<11> 66 10 BI FSB_D_L<12> 66 10 BI FSB_D_L<13> 66 10 BI FSB_D_L<14> 66 10 BI FSB_D_L<15> 66 10 BI FSB_D_L<16> 66 10 BI FSB_D_L<17> 66 10 BI FSB_D_L<18> 66 10 BI FSB_D_L<19> 66 10 BI FSB_D_L<20> 66 10 BI FSB_D_L<21> 66 10 BI FSB_D_L<22> 66 10 BI FSB_D_L<23> 66 10 BI FSB_D_L<24> 66 10 BI FSB_D_L<25> 66 10 BI FSB_D_L<26> 66 10 BI FSB_D_L<27> 66 10 66 10 C BI FSB_D_L<28> 66 10 BI FSB_D_L<29> 66 10 BI FSB_D_L<30> 66 10 BI FSB_D_L<31> 66 10 BI FSB_D_L<32> 66 10 BI FSB_D_L<33> 66 10 BI FSB_D_L<34> 66 10 BI FSB_D_L<35> 66 10 BI FSB_D_L<36> 66 10 BI FSB_D_L<37> 66 10 BI FSB_D_L<38> 66 10 BI FSB_D_L<39> 66 10 BI FSB_D_L<40> 66 10 BI FSB_D_L<41> 66 10 BI FSB_D_L<42> 66 10 BI FSB_D_L<43> 66 10 BI FSB_D_L<44> 66 10 BI FSB_D_L<45> BI FSB_D_L<46> 66 10 BI FSB_D_L<47> 66 10 BI FSB_D_L<48> 66 10 BI FSB_D_L<49> 66 10 BI FSB_D_L<50> 66 10 BI FSB_D_L<51> 66 10 BI FSB_D_L<52> 66 10 BI FSB_D_L<53> 66 10 BI FSB_D_L<54> 66 10 BI FSB_D_L<55> 66 10 BI FSB_D_L<56> 66 10 BI FSB_D_L<57> 66 10 BI FSB_D_L<58> 66 10 BI FSB_D_L<59> 66 10 BI FSB_D_L<60> 66 10 BI FSB_D_L<61> 66 10 BI FSB_D_L<62> 66 10 BI FSB_D_L<63> 66 10 B 23 21 19 18 13 12 11 10 8 7 6 72 54 42 30 27 26 PP1V05_S0 1 R1421 1 1 R1420 R1410 54.1UF 2 2 1 10% 6.9 100 1% 1/20W MF 201 1% 1/20W MF 201 2 1 C15 G17 H14 F12 B16 B18 D14 D18 L15 C17 D16 F16 A17 F14 K20 B20 F18 F22 G19 K22 D20 J17 K18 L17 J19 C21 D22 C19 A21 L21 J21 B22 G21 H_ADS* H_ADSTB0* H_ADSTB1* H_BNR* H_BPRI* H_BREQ* H_DEFER* H_DBSY* HPLL_CLK HPLL_CLK* H_DPWR* H_DRDY* H_HIT* H_HITM* H_LOCK* H_TRDY* F10 G15 F20 B8 F8 C11 B10 D6 AG7 AJ7 H10 E3 H8 D8 G11 B12 H_DINV0* H_DINV1* H_DINV2* H_DINV3* L5 V6 AB6 AD6 FSB_DINV_L<0> BI 10 66 FSB_DINV_L<1> BI 10 66 FSB_DINV_L<2> BI 10 66 FSB_DINV_L<3> BI 10 66 H_DSTBN0* H_DSTBN1* H_DSTBN2* H_DSTBN3* L9 U7 AA11 AE9 FSB_DSTB_L_N<0> BI 10 66 FSB_DSTB_L_N<1> BI 10 66 FSB_DSTB_L_N<2> BI 10 66 FSB_DSTB_L_N<3> BI 10 66 H_DSTBP0* H_DSTBP1* H_DSTBP2* H_DSTBP3* K8 U9 AA9 AE7 FSB_DSTB_L_P<0> BI 10 66 FSB_DSTB_L_P<1> BI 10 66 FSB_DSTB_L_P<2> BI 10 66 FSB_DSTB_L_P<3> BI 10 66 H_REQ0* H_REQ1* H_REQ2* H_REQ3* H_REQ4* G13 D12 B14 A13 C13 FSB_REQ_L<0> BI 10 66 FSB_REQ_L<1> BI 10 66 FSB_REQ_L<2> BI 10 66 FSB_REQ_L<3> BI 10 66 FSB_REQ_L<4> BI 10 66 H_RS0* H_RS1* H_RS2* L19 A9 C7 FSB_RS_L<0> OUT 10 66 FSB_RS_L<1> OUT 10 66 FSB_RS_L<2> OUT 10 66 FSB_A_L<3> BI 10 66 FSB_A_L<4> BI 10 66 FSB_A_L<5> BI 10 66 FSB_A_L<6> BI 10 66 FSB_A_L<7> BI 10 66 FSB_A_L<8> BI 10 66 FSB_A_L<9> BI FSB_A_L<10> 10 66 BI 10 66 FSB_A_L<11> BI 10 66 FSB_A_L<12> BI 10 66 FSB_A_L<13> BI 10 66 FSB_A_L<14> BI 10 66 FSB_A_L<15> BI 10 66 FSB_A_L<16> BI FSB_A_L<17> 10 66 BI 10 66 FSB_A_L<18> BI 10 66 FSB_A_L<19> BI 10 66 FSB_A_L<20> BI 10 66 FSB_A_L<21> BI 10 66 FSB_A_L<22> BI 10 66 FSB_A_L<23> BI 10 66 FSB_A_L<24> BI 10 66 FSB_A_L<25> BI 10 66 FSB_A_L<26> BI 10 66 FSB_A_L<27> BI 10 66 FSB_A_L<28> BI 10 66 FSB_A_L<29> BI 10 66 FSB_A_L<30> BI 10 66 FSB_A_L<31> BI 10 66 FSB_A_L<32> BI 10 66 FSB_A_L<33> BI 10 66 FSB_A_L<34> BI 10 66 FSB_A_L<35> BI 10 66 FSB_ADS_L BI 10 66 FSB_ADSTB_L<0> BI 10 66 BI 10 66 FSB_ADSTB_L<1> FSB_BNR_L FSB_BPRI_L BI OUT FSB_BREQ0_L BI FSB_DEFER_L OUT FSB_DBSY_L BI FSB_CLK_NB_P D C 10 66 10 66 10 66 10 66 10 66 IN 6 29 30 71 FSB_CLK_NB_N IN 6 29 30 71 FSB_DPWR_L BI 10 66 FSB_DRDY_L BI 10 66 FSB_HIT_L BI 10 66 FSB_HITM_L BI FSB_LOCK_L IN 10 66 FSB_TRDY_L OUT 10 66 10 66 B NB CPU Interface C1410 0.1UF 2 2 K14 H_AVREF L13 H_DVREF NB_FSB_VREF H_A3* H_A4* H_A5* H_A6* H_A7* H_A8* H_A9* H_A10* H_A11* H_A12* H_A13* H_A14* H_A15* H_A16* H_A17* H_A18* H_A19* H_A20* H_A21* H_A22* H_A23* H_A24* H_A25* H_A26* H_A27* H_A28* H_A29* H_A30* H_A31* H_A32* H_A33* H_A34* H_A35* FCBGA (1 OF 10) HOST BI 66 10 66 10 10% 6.0.9 221 1% 1/20W MF 201 1% 1/20W MF 201 1% 1/20W MF 201 2 2 H6 H2 F4 K2 P6 H4 M2 N7 N9 G3 L3 M4 K10 N11 K4 J3 R3 R11 U3 T10 T6 T2 R9 P4 V10 T4 W9 N1 V2 P2 U11 N3 Y2 AC7 W3 W7 Y6 AB10 AB2 W11 V4 Y10 Y4 AA3 AC11 AC9 AB4 AA1 AF2 AE3 AD10 AH6 AD2 AF10 AE11 AD4 AG1 AC3 AG3 AH4 AH2 AF6 AJ3 AF4 CRESTLINE_USFF H_D0* H_D1* H_D2* H_D3* H_D4* H_D5* H_D6* H_D7* H_D8* H_D9* H_D10* H_D11* H_D12* H_D13* H_D14* H_D15* H_D16* H_D17* H_D18* H_D19* H_D20* H_D21* H_D22* H_D23* H_D24* H_D25* H_D26* H_D27* H_D28* H_D29* H_D30* H_D31* H_D32* H_D33* H_D34* H_D35* H_D36* H_D37* H_D38* H_D39* H_D40* H_D41* H_D42* H_D43* H_D44* H_D45* H_D46* H_D47* H_D48* H_D49* H_D50* H_D51* H_D52* H_D53* H_D54* H_D55* H_D56* H_D57* H_D58* H_D59* H_D60* H_D61* H_D62* H_D63* 2 6 6 NB_FSB_SWING NB_FSB_RCOMP 6 NB_FSB_SCOMP 6 NB_FSB_SCOMP_L C5 H_SWING E5 H_RCOMP J5 H_SCOMP F6 H_SCOMP* 1 R1425 1K 1% 1/20W MF 201 66 13 10 6 OUT FSB_CPURST_L 66 10 OUT FSB_CPUSLP_L 6 1 R1426 1 2K 1% 1/20W MF 201 A C9 H_CPURST* J13 H_CPUSLP* 2 C1425 0. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.0 OF 14 1 73 A .9 54. 051-7230 B. SCALE SHT NONE 8 7 6 5 4 3 2 REV.3V X5R 201 SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. INC.3V X5R 201 R1415 1 R1411 24.

OUT GND OUT GND OUT GND PEG_RX5* PEG_RX6* LVDS_VBG LVDS_VREFH PEG_RX7* PEG_RX8* PEG_RX9* LVDS_VREFL LVDSA_CLK* LVDSA_CLK LVDSA_DATA0* LVDSA_DATA1* PEG_RX10* PEG_RX14* PEG_RX15* LVDSA_DATA3* PEG_RX1 PEG_RX2 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 H44 G47 A47 G45 LVDSB_DATA0* H46 E47 C47 F46 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA1* LVDSB_DATA2* LVDSB_DATA3* LVDSB_DATA2 LVDSB_DATA3 B32 TVA_DAC D32 TVB_DAC A33 TVC_DAC B30 TVA_RTN F32 TVB_RTN F30 TVC_RTN PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 PEG_TX0* PEG_TX1* PEG_TX2* PEG_TX3* PEG_TX4* PEG_TX5* PEG_TX6* PEG_TX7* PEG_TX8* PEG_TX9* PEG_TX10* share filtering with VCCA_CRT_DAC. NOTE: Must keep VDDC_TVDAC powered and filtered at all times! 7 BI NC_CRT_DDC_CLK 7 BI NC_CRT_DDC_DATA OUT CRT_HSYNC_R 67 63 6 OUT CRT_TVO_IREF 67 63 6 OUT CRT_VSYNC_R 67 63 6 F36 G35 A35 D30 J37 CRT_DDC_CLK CRT_DDC_DATA VGA B PEG_RX13* PEG_RX0 Must power all VCCA_TVx_DAC and VCCA_DAC_BG can All CRT/TVDAC rails must be powered.0 OF 15 1 73 A . 63 OUT TV_DCONSEL<0> 63 6 OUT TV_DCONSEL<1> PEG_TX11* PEG_TX12* K36 TV_DCONSEL0 J35 TV_DCONSEL1 PEG_TX13* PEG_TX14* PEG_TX15* CRT Disable / TV-Out Enable Tie R/R#/G/G#/B/B#. L_CTRL_*. Can tie the following rails to GND: OUT CRT_BLUE OUT GND OUT CRT_GREEN OUT GND OUT CRT_RED OUT GND C35 D34 F34 G33 B34 C33 CRT_BLUE CRT_BLUE* PEG_TX1 PEG_TX2 CRT_GREEN PEG_TX3 CRT_GREEN* CRT_RED PEG_TX4 PEG_TX5 CRT_RED* PEG_TX6 VCCA_CRT_DAC. PEG_RX11* PEG_RX12* LVDSA_DATA2* Unused DAC outputs must remain powered. VCCA_TVx_DAC. Can also tie CRT_DDC_*. VCCD_QDAC and VCC_SYNC. TVDAC rails. Tie VCC_AXG and VCC_AXG_NCTF to GND. VCCD_LVDS must remain powered with proper decoupling.8 6 7 2 3 4 5 PP1V05_S0_NB_VCCPEG 1 6 19 21 72 R1510 1 24. HSYNC and VSYNC to GND. 13 7 6 If SDVO is used. VCCD_CRT. but can omit filtering components. PEG_RX3* PEG_RX4* LVDS_IBG LVDSB_CLK PEG_COMPO PEG_RX2* L_VDD_EN LVDSB_CLK* PEG_COMPI PEG_RX0* PEG_RX1* L_CTRL_DATA TV-Out Signal Usage: Composite: DACA only FCBGA (3 OF 10) LVDS 64 9 6 Can leave all signals NC if LVDS is not implemented. Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND. NB PEG / Video Interfaces A SYNC_MASTER=M70 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.0. DACB & DACC 67 63 6 Unused DAC outputs should connect to GND through 75-ohm resistors. Leave GFX_VID<3. TVx_RTN.9 OMIT 1% 1/20W MF U1400 CRESTLINE_USFF OUT LCDBKLT_PWM_UNBUF 64 9 6 OUT LCDBKLT_PWREN Tie VCC_TX_LVDS and VCCA_LVDS to GND. SDVO_CTRL_* and TV_DCONSELx to GND. Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore). THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. TV-Out Disable / CRT Enable Tie TVx_DAC and TVx_RTN to GND.0> and GFX_VR_EN as NC. TV PCI-EXPRESS GRAPHICS LVDS Disable D 2 201 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 CRT_HSYNC PEG_TX11 CRT_TVO_IREF CRT_VSYNC PEG_TX12 PEG_TX13 PEG_TX14 Internal Graphics Disable PEG_TX15 T44 P44 6 PEG_COMP D SDVO Alternate Function G55 J55 R47 U47 P50 V46 Y50 AB46 Y52 AB50 R53 AE55 AF50 U55 AC55 AD50 NC_PEG_D2R_N0 IN 9 SDVO_TVCLKIN# PEG_D2R_N<1> IN 6 61 67 SDVO_INT# NC_PEG_D2R_N2 IN 9 SDVO_FLDSTALL# NC_PEG_D2R_N3 IN 9 NC_PEG_D2R_N4 IN 9 NC_PEG_D2R_N5 IN 9 NC_PEG_D2R_N6 IN 9 NC_PEG_D2R_N7 IN 9 NC_PEG_D2R_N8 IN 9 NC_PEG_D2R_N9 IN 9 NC_PEG_D2R_N10 IN 9 NC_PEG_D2R_N11 IN 9 NC_PEG_D2R_N12 IN 9 NC_PEG_D2R_N13 IN 9 NC_PEG_D2R_N14 IN 9 NC_PEG_D2R_N15 IN 9 G53 J53 T48 U45 P52 V48 AA51 AB48 AA55 AB52 R55 AD52 AF52 T52 AC53 AE51 NC_PEG_D2R_P0 IN PEG_D2R_P<1> 9 SDVO_TVCLKIN IN 6 61 67 SDVO_INT NC_PEG_D2R_P2 IN 9 SDVO_FLDSTALL NC_PEG_D2R_P3 IN 9 NC_PEG_D2R_P4 IN 9 NC_PEG_D2R_P5 IN 9 NC_PEG_D2R_P6 IN 9 NC_PEG_D2R_P7 IN 9 NC_PEG_D2R_P8 IN 9 NC_PEG_D2R_P9 IN 9 NC_PEG_D2R_P10 IN 9 NC_PEG_D2R_P11 IN 9 NC_PEG_D2R_P12 IN 9 NC_PEG_D2R_P13 IN 9 NC_PEG_D2R_P14 IN 9 NC_PEG_D2R_P15 IN 9 F52 K54 N47 V50 T50 L53 U53 N53 M52 AA47 AE53 AG45 AD48 AG49 W53 AA53 PEG_R2D_C_N<0> OUT 6 61 67 SDVOB_RED# PEG_R2D_C_N<1> OUT 6 61 67 SDVOB_GREEN# PEG_R2D_C_N<2> F54 K52 M48 V52 U51 L55 V54 P54 N55 AA45 AF54 AF46 AE47 AF48 W55 AB54 C OUT 6 61 67 SDVOB_BLUE# PEG_R2D_C_N<3> OUT 6 61 67 SDVOB_CLKN NC_PEG_R2D_C_N4 OUT 9 SDVOC_RED# NC_PEG_R2D_C_N5 OUT 9 SDVOC_GREEN# NC_PEG_R2D_C_N6 OUT 9 SDVOC_BLUE# NC_PEG_R2D_C_N7 OUT 9 SDVOC_CLKN NC_PEG_R2D_C_N8 OUT 9 NC_PEG_R2D_C_N9 OUT 9 NC_PEG_R2D_C_N10 OUT 9 NC_PEG_R2D_C_N11 OUT 9 NC_PEG_R2D_C_N12 OUT 9 NC_PEG_R2D_C_N13 OUT 9 NC_PEG_R2D_C_N14 OUT 9 NC_PEG_R2D_C_N15 OUT 9 PEG_R2D_C_P<0> OUT 6 61 67 SDVOB_RED PEG_R2D_C_P<1> OUT 6 61 67 SDVOB_GREEN PEG_R2D_C_P<2> OUT 6 61 67 SDVOB_BLUE PEG_R2D_C_P<3> OUT 6 61 67 SDVOB_CLKP NC_PEG_R2D_C_P4 OUT 9 SDVOC_RED NC_PEG_R2D_C_P5 OUT 9 SDVOC_GREEN NC_PEG_R2D_C_P6 OUT 9 SDVOC_BLUE NC_PEG_R2D_C_P7 SDVOC_CLKP OUT 9 NC_PEG_R2D_C_P8 OUT 9 NC_PEG_R2D_C_P9 OUT 9 NC_PEG_R2D_C_P10 OUT 9 NC_PEG_R2D_C_P11 OUT 9 NC_PEG_R2D_C_P12 OUT 9 NC_PEG_R2D_C_P13 OUT 9 NC_PEG_R2D_C_P14 OUT 9 NC_PEG_R2D_C_P15 OUT 9 B Follow instructions for LVDS and CRT & TV-Out Disable above. BI LOCAL_CTRL_CLK 13 7 6 BI LOCAL_CTRL_DATA 60 7 6 BI LVDS_DDC_CLK 60 7 6 BI LVDS_DDC_DATA OUT LVDS_VDD_EN BI LVDS_IBG 60 6 67 60 6 7 NC_LVDS_VBG TP_LVDS_VREFH TP_LVDS_VREFL 67 60 6 OUT LVDS_A_CLK_N 67 60 6 OUT LVDS_A_CLK_P 67 9 OUT NC_LVDS_B_CLK_N 67 9 OUT NC_LVDS_B_CLK_P 67 60 7 OUT LVDS_A_DATA_N<0> 67 60 7 OUT LVDS_A_DATA_N<1> 67 60 7 6 OUT LVDS_A_DATA_N<2> TP_LVDS_A_DATA_N<3> OUT LVDS_A_DATA_P<0> 67 60 7 OUT LVDS_A_DATA_P<1> 67 60 7 6 OUT LVDS_A_DATA_P<2> 67 60 7 TP_LVDS_A_DATA_P<3> C 9 OUT NC_LVDS_B_DATA_N0 9 OUT NC_LVDS_B_DATA_N1 9 OUT NC_LVDS_B_DATA_N2 TP_LVDS_B_DATA_N<3> OUT NC_LVDS_B_DATA_P0 9 OUT NC_LVDS_B_DATA_P1 9 OUT NC_LVDS_B_DATA_P2 9 TP_LVDS_B_DATA_P<3> C43 G41 B40 D42 C39 D38 G43 L49 K50 L43 K42 A49 C49 D46 B46 J41 C51 F50 E53 H42 B50 E49 D52 L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_DDC_CLK L_DDC_DATA 67 63 6 OUT TV_A_DAC S-Video: 67 63 6 OUT TV_B_DAC OUT TV_C_DAC DACB & DACC only Component: DACA. Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore). VCCA_DAC_BG. HSYNC. R/R#/G/G#/B/B#. PEG_TX0 All rails must be filtered except for VCCA_CRT. L_DDC_*. 051-7230 B. 67 63 6 VSYNC and CRT_TVO_IREF to GND. SCALE SHT NONE 8 7 6 5 4 3 2 REV. 67 63 6 CRT & TV-Out Disable 67 63 6 Tie TVx_DAC. tie VCCD_LVDS to GND also. INC.. Otherwise.

2UF 10% 10V X5R 201 PP0V9_S3M_MEM_NBVREFA R1620 1K C1623 1 20% 6. PP0V9_S3M and PP0V9_S0M.01UF IN 8 21 68 PP0V9_S3M_MEM_NBVREFB IN 8 21 68 1 1 IN 6 9 29 30 71 NB_CLK96M_DOT_N IN 6 9 29 30 71 NB_CLK100M_DPLLSS_P IN 6 9 29 30 71 NB_CLK100M_DPLLSS_N IN 6 9 29 30 71 IN 6 29 30 71 IN 6 29 30 71 10% 6. INC.01K 2 1% 1/20W MF 201 C1616 0.3V X5R 201 2 2 1% 1/20W MF 201 OMIT C1622 2.02K NB_CFG<15> RESERVED 2 TP_NB_RSVD<44> 7 NB_CFG<19> NB_CFG<16> High = Enabled FSB Dynamic C TP_NB_RSVD<9> 1% 1/20W MF 201 Low ODT = Disabled 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 PP3V3_A_S0 NB_CFG<17> RESERVED NC_NB_RSVD_4 TP_NB_RSVD<20> 6 16 NBCFG_SDVO_AND_PCIE 1 7 NC_NB_RSVD_3 7 NC_NB_RSVD_14 7 NC_NB_RSVD_1 7 NC_NB_RSVD_2 A39 AG11 AG9 AH10 AJ11 AJ43 AL43 AN43 AR43 B36 B38 B55 BA33 BB22 BC33 BF22 BE23 BH18 BE27 BJ17 BK16 BK18 BK32 BL17 BL19 C37 D10 D36 G51 G9 H52 J25 M46 N45 CRESTLINE_USFF FCBGA (2 OF 10) SM_CK1* SM_CK3* SM_CK4* SM_CKE0 RSVD 31 33 68 OUT 31 33 68 MEM_CLK_P<3> OUT 32 33 68 MEM_CLK_P<4> OUT 32 33 68 BA37 BC23 BB34 BB26 MEM_CLK_N<0> OUT 31 33 68 MEM_CLK_N<1> OUT 31 33 68 MEM_CLK_N<3> OUT 32 33 68 MEM_CLK_N<4> OUT 32 33 68 BE33 BE35 BF40 BE39 MEM_CKE<0> OUT 31 33 68 MEM_CKE<1> OUT 31 33 68 MEM_CKE<3> OUT 32 33 68 MEM_CKE<4> OUT 32 33 68 BA23 BH16 BE15 BH14 MEM_CS_L<0> OUT MEM_CS_L<1> OUT 31 33 68 MEM_CS_L<2> OUT 32 33 68 MEM_CS_L<3> OUT 32 33 68 BJ15 BF20 BE13 BH12 MEM_ODT<0> OUT 6 31 33 68 MEM_ODT<1> OUT 6 31 33 68 MEM_ODT<2> OUT 6 32 33 68 MEM_ODT<3> OUT 6 32 33 68 BL13 BK14 SM_RCOMP_VOL SM_VREF0 SM_VREF1 AM54 AT12 6 MEM_RCOMP 6 MEM_RCOMP_L 6 MEM_RCOMP_VOH 6 MEM_RCOMP_VOL D 35 34 32 31 21 18 8 7 6 72 68 55 51 PP1V8_S3 R1610 6 16 PEG_CLK PEG_CLK* NB_CLK96M_DOT_P N51 M50 NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N 1 2 2 1 1 2 2 0.02K NB_CFG<18> SM_CK0 SM_CK4 1 C1640 SDVO_CTRL_CLK SDVO_CTRL_DATA CLKREQ* MISC NB_CFG<8> 1 U1400 RSVD bit ordering based on CRB numbering = DMIx2 NB_CFG<7> 2 3 4 5 DDR MUXING NB_CFG<3> NB_CFG<6> D 6 7 ICH_SYNC* TEST1 TEST2 K38 K40 G39 D40 F38 K34 SDVO_CTRLCLK BI SDVO_CTRLDATA BI OUT NB_SB_SYNC_L OUT 6 25 6 NB_TEST1 6 NB_TEST2 10% 6.8 RESERVED NB_CFG<4> RESERVED NB_CFG<5> High = DMIx4 DMI x2 Select Low OMIT NB CFG<5> chooses DMI x4 w/ TP TP_NB_RSVD<42> RESERVED RESERVED NB_CFG<9> 7 NC_NB_RSVD_8 7 NC_NB_RSVD_7 7 NC_NB_RSVD_5 7 NC_NB_RSVD_6 6 16 NBCFG_PEG_REVERSE 1 TP_NB_RSVD<12> R1659 TP_NB_RSVD<11> 4. NC DMI Lane SM_CS0* SM_CS1* SM_RCOMP* 1% 1/20W MF 201 NB_CFG<20> High = Reversed SM_CKE4 SM_ODT3 CLK 2 NB_CFG<19> SM_CKE1 SM_CKE3 SM_RCOMP R1670 RESERVED SM_CK1 SM_CK3 SM_CK0* 4.02K 7 NC_NB_RSVD_31 7 NC_NB_RSVD_24 7 NC_NB_RSVD_36 7 NC_NB_RSVD_22 7 NC_NB_RSVD_25 7 NC_NB_RSVD_27 NBCFG_DYN_ODT_DISABLE 1 2 See Below NC_NB_RSVD_21 NC_NB_RSVD_29 RESERVED NB_CFG<12> 6 16 7 1% 1/20W MF 201 TP_NB_RSVD<34> 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 PP3V3_A_S0 NBCFG_DMI_REVERSE 1 7 NC_NB_RSVD_26 7 NC_NB_RSVD_23 R1669 TP_NB_RSVD<43> 4. 051-7230 B. PP1V05_S0M.2UF 20% 6.1UF 6 61 NB_CLKREQ_L 1 2 2 1% 1/20W MF 201 NB Misc Interfaces SYNC_MASTER=M70 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY R1691 1 1 20K 5% 1/20W MF 201 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.3V CERM 402-LF 2 1% 1/20W MF 201 Clk used for PEG and DMI = Normal 66 30 13 7 6 IN NB_BSEL<0> 66 30 13 7 6 IN NB_BSEL<1> IN NB_BSEL<2> 13 7 6 OUT NB_CFG<3> 13 7 6 BI NB_CFG<4> 13 7 6 BI NB_CFG<5> 13 7 6 OUT NB_CFG<6> 66 30 13 7 6 = Only SDVO SDVO/PCIe x1 or PCIe x16 NB CFG<8:0> used for debug access NB_CFG<13:12> 00 = RESERVED 13 7 6 OUT NB_CFG<7> 01 = XOR Mode Enabled 13 7 6 OUT NB_CFG<8> 10 = All-Z Mode Enabled 16 6 11 = Normal Operation NB_CFG<9> 7 NC_NB_CFG_10 7 NC_NB_CFG_11 TP_NB_CFG<12> TP_NB_CFG<13> NB CFG<13:12> require ICT access 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 B OUT MEM_CLK_P<1> BK36 BL37 DPLL_REF_CLK DPLL_REF_CLK* PP3V3_A_S0 7 NC_NB_CFG_14 7 NC_NB_CFG_15 16 6 7 NB_CFG<16> NC_NB_CFG_17 TP_NB_CFG<18> R1630 1 1 10K 5% 1/20W MF 201 41 6 IN PM_EXTTS_L<0> 41 6 IN PM_EXTTS_L<1> R1631 10K 2 2 5% 1/20W MF 201 25 6 66 52 23 10 6 16 6 NB_CFG<19> 16 6 NB_CFG<20> OUT PM_BMBUSY_L IN CPU_DPRSTP_L 52 28 16 9 6 IN VR_PWRGOOD_DELAY 28 6 IN NB_RESET_L OUT PM_THRMTRIP_L IN PM_DPRSLPVR 66 42 23 10 6 66 52 25 6 A 7 NC_NB_NC_14 7 NC_NB_NC_13 7 NC_NB_NC_12 7 NC_NB_NC_10 7 NC_NB_NC_2 7 NC_NB_NC_9 7 NC_NB_NC_8 7 NC_NB_NC_4 7 NC_NB_NC_1 7 NC_NB_NC_7 7 NC_NB_NC_6 7 NC_NB_NC_5 7 NC_NB_NC_3 7 NC_NB_NC_11 H28 G25 C25 K24 B28 G27 B26 D26 D24 F26 A25 L23 D28 F24 C29 C27 A29 J27 G31 K30 L37 F44 C41 L39 J39 AT50 BB20 F28 F40 CFG0 DMI_RXN0 CFG1 DMI_RXN1 CFG2 CFG3 DMI_RXN2 DMI_RXN3 IPU CFG4 CFG5 IPU CFG6 IPU DMI_RXP0 IPU CFG7 CFG8 IPU CFG9 IPU IPU CFG10 IPU CFG11 IPU CFG DMI Low SM_ODT2 DPLL_REF_SSCLK DPLL_REF_SSCLK* High = Both active Concurrent SM_ODT0 SM_ODT1 MEM_CLK_P<0> C1615 CFG12 IPU CFG20 IPD PM_DPRSTP* PM_EXT_TS0* PM_EXT_TS1* PWROK RSTIN* THERMTRIP* DPRSLPVR A52 A54 B54 BH1 BH55 BK1 BK2 NC BK54 BK55 BL2 BL4 BL52 BL54 D55 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXP2 DMI_TXP3 CFG17 IPU PM_BM_BUSY* DMI_RXP3 DMI_TXP0 DMI_TXP1 CFG15 IPU CFG16 IPU CFG18 IPD CFG19 IPD DMI_RXP1 DMI_RXP2 DMI_TXN3 CFG13 IPU CFG14 IPU PM GRAPHICS VID NB_CFG<20> SM_CS3* SM_RCOMP_VOH GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VR_EN AL45 AK54 AJ55 AH52 DMI_S2N_N<0> IN 6 24 67 DMI_S2N_N<1> IN 6 24 67 DMI_S2N_N<2> IN 6 24 67 DMI_S2N_N<3> IN 6 24 67 AM46 AK52 AJ53 AH50 DMI_S2N_P<0> IN 6 24 67 DMI_S2N_P<1> IN 6 24 67 DMI_S2N_P<2> IN 6 24 67 DMI_S2N_P<3> IN 6 24 67 AH48 AK48 AG55 AL53 DMI_N2S_N<0> OUT 6 24 67 DMI_N2S_N<1> OUT 6 24 67 DMI_N2S_N<2> OUT 6 24 67 DMI_N2S_N<3> OUT 6 24 67 AJ47 AK50 AG53 AL55 DMI_N2S_P<0> OUT 6 24 67 DMI_N2S_P<1> OUT 6 24 67 DMI_N2S_P<2> OUT 6 24 67 DMI_N2S_P<3> OUT 6 24 67 GND OUT GFX_VID<0> OUT 6 22 53 GFX_VID<1> OUT 6 22 53 GFX_VID<2> OUT 6 22 53 GFX_VID<3> OUT 6 22 53 GFX_VR_EN OUT 6 9 53 G37 A45 B42 D44 F42 B PP1V25_S0 1 CL_CLK ME Low Reversal SM_CS2* BC37 BC25 BB36 BB24 CL_DATA CL_PWROK CL_RST* CL_VREF BF52 BE53 AP50 BH52 BF54 CLINK_NB_CLK BI 6 25 70 CLINK_NB_DATA BI 6 25 70 VR_PWRGOOD_DELAY IN CLINK_NB_RESET_L 70 6 OUT 6 7 8 18 19 21 26 27 51 57 72 R1640 1K 6 9 16 28 52 2 6 25 70 1% 1/20W MF 201 NB_CLINK_VREF NOTE: GMCH CL_PWROK input must be PWRGD signal for PP3V3_S0M. SCALE SHT NONE 8 7 6 5 4 3 2 REV.3V CERM 402-LF R1622 3.01UF 2 10% 10V X5R 201 1 OMIT C1624 2 2 C R1624 1K 2.0. THE POSSESSOR AGREES TO THE FOLLOWING R1690 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 0 2 2 II NOT TO REPRODUCE OR COPY IT 5% 1/20W MF 201 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.1UF C45 B44 H50 G49 1 20 1% 1/20W MF 201 0.3V X5R 201 6 61 6 29 R1641 392 0. If ME/AMT is not used.3V X5R 201 1 C1625 20 1% 1/20W MF 201 1 1 0. PP1V25_S0M. short CL_PWROK to PWROK.02K RESERVED 2 TP_NB_RSVD<13> 1% 1/20W MF 201 TP_NB_RSVD<10> TP_NB_RSVD<45> TP_NB_RSVD<41> NB_CFG<9> High = Normal PCIe Graphics Low Lane Reversal = Reversed NB_CFG<16> RESERVED NB_CFG<10> NB_CFG<11> NB_CFG<13> See Below NB_CFG<14> RESERVED 7 NC_NB_RSVD_28 7 NC_NB_RSVD_35 7 R1666 7 NC_NB_RSVD_30 4. PP3V3_S0MWOL.0 OF 16 1 73 A .1UF R1611 10% 6. PP1V8_S3M.

051-7230 B. SCALE SHT NONE 8 7 6 5 4 3 2 REV.8 6 7 D OMIT 68 31 BI MEM_A_DQ<1> 68 31 BI MEM_A_DQ<2> 68 31 BI MEM_A_DQ<3> 68 31 BI MEM_A_DQ<4> 68 31 BI MEM_A_DQ<5> 68 31 BI MEM_A_DQ<6> 68 31 BI MEM_A_DQ<7> 68 31 BI MEM_A_DQ<8> 68 31 BI MEM_A_DQ<9> BI MEM_A_DQ<10> 68 31 BI MEM_A_DQ<11> 68 31 BI MEM_A_DQ<12> 68 31 BI MEM_A_DQ<13> 68 31 BI MEM_A_DQ<14> 68 31 BI MEM_A_DQ<15> BI MEM_A_DQ<16> BI MEM_A_DQ<17> 68 31 BI MEM_A_DQ<18> 68 31 BI MEM_A_DQ<19> 68 31 BI MEM_A_DQ<20> BI MEM_A_DQ<21> 68 31 BI MEM_A_DQ<22> 68 31 BI MEM_A_DQ<23> BI MEM_A_DQ<24> 68 31 BI MEM_A_DQ<25> 68 31 BI MEM_A_DQ<26> 68 31 BI MEM_A_DQ<27> BI MEM_A_DQ<28> 68 31 BI MEM_A_DQ<29> 68 31 BI MEM_A_DQ<30> 68 31 BI MEM_A_DQ<31> 68 31 BI MEM_A_DQ<32> 68 31 BI MEM_A_DQ<33> BI MEM_A_DQ<34> BI MEM_A_DQ<35> 68 31 BI MEM_A_DQ<36> 68 31 BI MEM_A_DQ<37> BI MEM_A_DQ<38> 68 31 BI MEM_A_DQ<39> 68 31 BI MEM_A_DQ<40> 68 31 BI MEM_A_DQ<41> BI MEM_A_DQ<42> 68 31 BI MEM_A_DQ<43> 68 31 BI MEM_A_DQ<44> BI MEM_A_DQ<45> 68 31 BI MEM_A_DQ<46> 68 31 68 31 68 31 68 31 C 68 31 68 31 68 31 68 31 68 31 68 31 68 31 B 68 31 BI MEM_A_DQ<47> 68 31 BI MEM_A_DQ<48> 68 31 BI MEM_A_DQ<49> 68 31 BI MEM_A_DQ<50> 68 31 BI MEM_A_DQ<51> 68 31 BI MEM_A_DQ<52> 68 31 BI MEM_A_DQ<53> 68 31 BI MEM_A_DQ<54> 68 31 BI MEM_A_DQ<55> 68 31 BI MEM_A_DQ<56> 68 31 BI MEM_A_DQ<57> 68 31 BI MEM_A_DQ<58> 68 31 BI MEM_A_DQ<59> 68 31 BI MEM_A_DQ<60> 68 31 BI MEM_A_DQ<61> 68 31 BI MEM_A_DQ<62> BI MEM_A_DQ<63> 68 31 AN49 AL51 AV50 AT46 AM48 AM50 AU49 AU47 AY50 BB50 BC49 AW45 AW49 BA49 AU45 BB46 AV46 BF50 BA45 BE45 BD48 BE49 AY46 BF46 BF44 BA43 BA41 BB44 BC45 BE43 BC39 BB42 BA15 BB14 BE7 BC9 BC15 BB12 BC11 BF10 BB10 BA9 BD6 AW11 AY10 BD8 AW9 BB6 AV10 AT10 AT6 AR9 AW7 AY6 AR7 AP6 AM6 AM10 AL11 AN11 AN7 AN9 AP10 AR11 BC21 BA21 BF34 OUT 31 33 68 68 32 BI MEM_B_DQ<0> MEM_A_BS<1> OUT 31 33 68 68 32 BI MEM_B_DQ<1> OUT 31 33 68 68 32 BI MEM_B_DQ<2> 68 32 BI MEM_B_DQ<3> 68 32 BI MEM_B_DQ<4> 68 32 BI MEM_B_DQ<5> 68 32 BI MEM_B_DQ<6> 68 32 BI MEM_B_DQ<7> 68 32 BI MEM_B_DQ<8> 68 32 BI MEM_B_DQ<9> 68 32 BI MEM_B_DQ<10> 68 32 BI MEM_B_DQ<11> 68 32 BI MEM_B_DQ<12> 68 32 BI MEM_B_DQ<13> 68 32 BI MEM_B_DQ<14> 68 32 BI MEM_B_DQ<15> 68 32 BI MEM_B_DQ<16> 68 32 BI MEM_B_DQ<17> 68 32 BI MEM_B_DQ<18> 68 32 BI MEM_B_DQ<19> 68 32 BI MEM_B_DQ<20> 68 32 BI MEM_B_DQ<21> 68 32 BI MEM_B_DQ<22> 68 32 BI MEM_B_DQ<23> 68 32 BI MEM_B_DQ<24> 68 32 BI MEM_B_DQ<25> 68 32 BI MEM_B_DQ<26> 68 32 BI MEM_B_DQ<27> 68 32 BI MEM_B_DQ<28> 68 32 BI MEM_B_DQ<29> 68 32 BI MEM_B_DQ<30> 68 32 BI MEM_B_DQ<31> 68 32 BI MEM_B_DQ<32> 68 32 BI MEM_B_DQ<33> 68 32 BI MEM_B_DQ<34> 68 32 BI MEM_B_DQ<35> 68 32 BI MEM_B_DQ<36> 68 32 BI MEM_B_DQ<37> 68 32 BI MEM_B_DQ<38> 68 32 BI MEM_B_DQ<39> 68 32 BI MEM_B_DQ<40> 68 32 BI MEM_B_DQ<41> 68 32 BI MEM_B_DQ<42> 68 32 BI MEM_B_DQ<43> 68 32 BI MEM_B_DQ<44> 68 32 BI MEM_B_DQ<45> 68 32 BI MEM_B_DQ<46> 68 32 BI MEM_B_DQ<47> 68 32 BI MEM_B_DQ<48> 68 32 BI MEM_B_DQ<49> 68 32 BI MEM_B_DQ<50> 68 32 BI MEM_B_DQ<51> SA_DQ52 68 32 BI MEM_B_DQ<52> SA_DQ53 SA_DQ54 68 32 BI MEM_B_DQ<53> 68 32 BI MEM_B_DQ<54> SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 FCBGA (4 OF 10) BE19 MEM_A_CAS_L SA_DM0 AR49 BD50 BF48 BF42 BE11 BF4 AU7 AK6 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS0* SA_DQS1* SA_DQS2* SA_DQS3* SA_DQS4* SA_DQS5* SA_DQS6* SA_DQS7* SA_MA0 SA_MA1 SA_MA2 SA_DQ34 SA_DQ35 SA_MA3 SA_MA4 SA_DQ36 SA_DQ37 SA_MA5 SA_MA6 SA_MA7 SA_DQ38 SA_DQ39 SA_DQ40 SA_MA8 SA_MA9 SA_MA10 SA_DQ41 SA_DQ42 SA_DQ43 SA_MA11 SA_MA12 SA_MA13 SA_DQ44 SA_DQ45 SA_DQ46 SA_MA14 SA_RAS* SA_RCVEN* SA_DQ50 SA_DQ51 MEM_A_BS<2> SA_CAS* SA_DM1 SA_DQ33 SA_DQ49 SA_BS0 SA_BS1 SA_BS2 SA_DQ31 SA_DQ32 SA_DQ47 SA_DQ48 D U1400 CRESTLINE_USFF MEM_A_BS<0> SA_DQ0 SA_WE* AR45 BA47 BE47 BC41 BC13 BA7 AU11 AL9 AR47 AW47 BC47 BE41 BA13 BC7 AU9 AL7 BC19 BH22 BL23 BF24 BH24 BK24 BJ25 BH26 BF32 BK26 BB18 BE25 BF26 BC17 BH32 BE21 BJ19 BH20 OUT 31 33 68 MEM_A_DM<0> OUT 31 68 MEM_A_DM<1> OUT 31 68 OUT 31 68 MEM_A_DM<2> MEM_A_DM<3> OUT 31 68 MEM_A_DM<4> OUT 31 68 MEM_A_DM<5> OUT 31 68 OUT 31 68 MEM_A_DM<6> MEM_A_DM<7> OUT 31 68 MEM_A_DQS_P<0> BI 31 68 MEM_A_DQS_P<1> BI 31 68 MEM_A_DQS_P<2> BI 31 68 MEM_A_DQS_P<3> BI 31 68 BI 31 68 MEM_A_DQS_P<4> MEM_A_DQS_P<5> BI 31 68 MEM_A_DQS_P<6> BI 31 68 MEM_A_DQS_P<7> BI 31 68 MEM_A_DQS_N<0> BI 31 68 MEM_A_DQS_N<1> BI 31 68 MEM_A_DQS_N<2> BI 31 68 MEM_A_DQS_N<3> BI 31 68 MEM_A_DQS_N<4> BI 31 68 MEM_A_DQS_N<5> BI 31 68 MEM_A_DQS_N<6> BI 31 68 BI 31 68 MEM_A_DQS_N<7> MEM_A_A<0> OUT 31 33 68 MEM_A_A<1> OUT 31 33 68 MEM_A_A<2> OUT 31 33 68 MEM_A_A<3> OUT 31 33 68 MEM_A_A<4> OUT 31 33 68 MEM_A_A<5> OUT 31 33 68 MEM_A_A<6> OUT 31 33 68 MEM_A_A<7> OUT 31 33 68 OUT 31 33 68 MEM_A_A<8> MEM_A_A<9> OUT 31 33 68 MEM_A_A<10> OUT 31 33 68 MEM_A_A<11> OUT 31 33 68 MEM_A_A<12> OUT 31 33 68 MEM_A_A<13> OUT 31 33 68 TP_MEM_A_A<14> OUT MEM_A_RAS_L OUT NC_MEM_A_RCVEN_L 31 33 68 7 MEM_A_WE_L OUT 31 33 68 SA_DQ55 68 32 BI MEM_B_DQ<55> SA_DQ56 SA_DQ57 68 32 BI MEM_B_DQ<56> 68 32 BI MEM_B_DQ<57> SA_DQ58 SA_DQ59 68 32 BI MEM_B_DQ<58> 68 32 BI MEM_B_DQ<59> SA_DQ60 68 32 BI MEM_B_DQ<60> SA_DQ61 SA_DQ62 68 32 BI MEM_B_DQ<61> 68 32 BI MEM_B_DQ<62> SA_DQ63 68 32 BI MEM_B_DQ<63> AT52 AN53 AV52 AP54 AP52 AN55 AU53 AV54 BC53 BC55 AY52 BD52 AW55 AW53 BD54 AY54 BK50 BL47 BJ47 BG51 BJ51 BK46 BH50 BH46 BK44 BJ41 BH40 BJ45 BH44 BL43 BK40 BL39 BK8 BJ7 BK6 BH6 BJ11 BH10 BK10 BK12 BH4 BB4 BC1 BG3 BC3 BJ5 BF6 BD2 BB2 AU3 BA3 AY2 AY4 AT2 AV2 AT4 AR1 AK4 AK2 AP4 AP2 AL3 AR3 AL1 SB_DQ0 CRESTLINE_USFF FCBGA (5 OF 10) SB_DQ1 SB_DQ2 DDR SYSTEM MEMORY B MEM_A_DQ<0> DDR SYSTEM MEMORY A BI 1 OMIT U1400 68 31 2 3 4 5 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 BB16 BF16 BH38 MEM_B_BS<0> OUT 32 33 68 SB_BS1 SB_BS2 MEM_B_BS<1> OUT 32 33 68 MEM_B_BS<2> OUT 32 33 68 SB_CAS* BJ13 MEM_B_CAS_L OUT 32 33 68 SB_DM0 AR55 BA53 BJ49 BJ43 BH8 BD4 AV4 AN3 MEM_B_DM<0> OUT 32 68 MEM_B_DM<1> OUT 32 68 MEM_B_DM<2> OUT 32 68 MEM_B_DM<3> OUT 32 68 MEM_B_DM<4> OUT 32 68 MEM_B_DM<5> OUT 32 68 MEM_B_DM<6> OUT 32 68 MEM_B_DM<7> OUT 32 68 AT54 BB52 BH48 BH42 BL9 BE3 AW1 AM2 AR53 BB54 BK48 BK42 BJ9 BF2 AW3 AM4 MEM_B_DQS_P<0> BI 32 68 MEM_B_DQS_P<1> BI 32 68 MEM_B_DQS_P<2> BI 32 68 MEM_B_DQS_P<3> BI 32 68 MEM_B_DQS_P<4> BI 32 68 MEM_B_DQS_P<5> BI 32 68 MEM_B_DQS_P<6> BI 32 68 MEM_B_DQS_P<7> BI 32 68 MEM_B_DQS_N<0> BI 32 68 MEM_B_DQS_N<1> BI 32 68 MEM_B_DQS_N<2> BI 32 68 MEM_B_DQS_N<3> BI 32 68 MEM_B_DQS_N<4> BI 32 68 MEM_B_DQS_N<5> BI 32 68 MEM_B_DQS_N<6> BI 32 68 MEM_B_DQS_N<7> BI BA19 BE37 BF36 BA17 BJ37 BK38 BC35 BF38 BA35 BH34 BE17 BJ33 BH36 BF14 BJ39 MEM_B_A<0> OUT 32 33 68 MEM_B_A<1> OUT 32 33 68 MEM_B_A<2> OUT 32 33 68 MEM_B_A<3> OUT 32 33 68 MEM_B_A<4> OUT 32 33 68 MEM_B_A<5> OUT 32 33 68 MEM_B_A<6> OUT 32 33 68 MEM_B_A<7> OUT 32 33 68 MEM_B_A<8> OUT 32 33 68 MEM_B_A<9> OUT 32 33 68 MEM_B_A<10> OUT 32 33 68 MEM_B_A<11> OUT 32 33 68 MEM_B_A<12> OUT 32 33 68 MEM_B_A<13> OUT 32 33 68 TP_MEM_B_A<14> OUT BF18 BJ23 MEM_B_RAS_L SB_RCVEN* SB_WE* BF12 MEM_B_WE_L SB_BS0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 SB_DQS0* SB_DQS1* SB_DQS2* SB_DQS3* SB_DQS4* SB_DQS5* SB_DQ27 SB_DQ28 SB_DQ29 SB_DQS6* SB_DQS7* SB_DQ30 SB_DQ31 SB_DQ32 SB_MA0 SB_MA1 SB_MA2 SB_DQ33 SB_DQ34 SB_DQ35 SB_MA3 SB_MA4 SB_DQ36 SB_DQ37 SB_MA5 SB_MA6 SB_MA7 SB_DQ38 SB_DQ39 SB_DQ40 SB_MA8 SB_MA9 SB_MA10 SB_DQ41 SB_DQ42 SB_DQ43 SB_MA11 SB_MA12 SB_MA13 SB_DQ44 SB_DQ45 SB_DQ46 SB_MA14 SB_DQ47 SB_DQ48 SB_RAS* SB_DQ49 SB_DQ50 SB_DQ51 OUT NC_MEM_B_RCVEN_L C 32 68 32 33 68 B 7 OUT 32 33 68 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 NB DDR2 Interfaces A SYNC_MASTER=M70 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.0. INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.0 OF 17 1 73 A .

3V 2 X5R 402 10% 6.3V 2 CERM 402 0. 051-7230 B. 7 6 5 4 3 2 REV. 533MHz) 5 mA (standby) B BA27 BA29 BA31 BB28 BB30 BB32 BC27 BC29 BC31 BD28 BD30 BE29 BE31 BF28 BF30 BG27 BG29 BG31 BH28 BH30 BJ29 BK28 BK30 BL29 68 6 68 6 68 6 68 6 OMIT C1806 1 C1805 1 C1804 1 C1803 1 C1802 1 C1801 1 10% 6.8 6 7 2 3 4 5 1 NCTF balls are Not Critical To Function These connections can break without impacting part performance.0. INC.22UF 0.3V 2 X5R 201 10% 6.3V 2 CERM 402 10% 6.3V CERM-X5R 2 402 10% 6.22UF 0. 667MHz) 1395 mA (1 ch.3V 2 X5R 201 20% 6.1UF 0.0 OF 18 1 73 A .1UF AP46 BC43 BA39 BA25 BA11 BF8 AV6 VCC_SM_LF 68 6 NB_VCCSM_LF1 NB_VCCSM_LF2 NB_VCCSM_LF3 NB_VCCSM_LF4 NB_VCCSM_LF5 NB_VCCSM_LF6 NB_VCCSM_LF7 1uF PP1V05_S0 VCC_AXG_NCTF W29 Y19 Y21 Y25 Y27 VCC_AXG 68 6 6 7 8 18 22 45 53 65 72 VCCA_SM CRESTLINE_USFF 7700 mA (Int Graphics) AW36 AW38 VCC_SM_NCTF AW40 68 6 PPVCORE_S0_NB_GFX VCCA_SM_NCTF 2700 mA (2 ch.47UF 1uF AH22 AH24 AH25 AH27 AH28 AH29 AJ18 AJ21 AJ24 AJ27 OMIT C1807 1 0. doc #21749. 667MHz) U1400 FCBGA VCC_AXM PP1V8_S3 (6 OF 10) AE15 AE16 AG13 AG15 AG16 AH16 AJ13 AJ15 AJ16 AL13 AL15 AM15 AN13 R27 R29 R31 T27 T29 T31 U27 U29 U31 Y15 (7 OF 10) U1400 VCC_AXM_NCTF C POWER VCC_AXG 1600 mA (Int Graphics) OMIT CRESTLINE_USFF 1310 mA (Ext Graphics) 55 51 35 34 32 31 21 16 8 7 6 72 68 AA40 AA41 AC40 AC41 AD40 AE40 AE41 AE43 AG40 AG41 AG43 AH40 AH41 R35 R38 R40 R43 T35 T38 T40 U35 U38 U40 U41 U43 W40 W41 Y40 VCC_AXG_NCTF AA32 AA34 AA35 AA38 AA37 AC32 AC34 AC35 AC37 AC38 AD34 AD35 AD37 AD38 AE35 AE37 AG35 AG37 AH37 AH38 L29 W35 W38 Y32 Y34 Y35 Y37 Y38 VCC D PP1V05_S0 VCC_SM 21 19 18 14 13 12 11 10 8 7 6 72 54 42 30 27 26 23 POWER OMIT PP1V05_S0 AA13 AA15 AC13 AC16 AD15 AD16 AE13 21 19 18 14 13 12 11 10 8 7 6 72 54 42 30 27 26 23 VCC_NCTF PPVCORE_S0_NB_GFX PP1V25_S0 6 7 8 16 19 21 26 27 51 57 72 640mA AL18 AM18 AN22 AN24 AN37 AN38 D AN15 AN16 AR13 AR15 AR16 AR22 AR24 AR25 AR37 AR38 AT15 AT18 AT19 AT21 AT22 AT24 AT25 AT27 AT28 AT29 AT34 AT35 AT37 AT38 AU13 AU16 AU18 AU19 AU21 AU22 AU24 AU25 AU27 AU28 AU29 AU31 AU32 AU34 AU35 AW14 AW16 AW26 AW28 AW30 AW32 C BL55 BL1 D1 B2 A4 A55 B NB Power 1 VCC_AXG AJ28 AL22 AL24 AL25 AL27 AL28 W27 A SYNC_MASTER=M70 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.3V 2 X5R 402 20% 6. 533MHz) FCBGA 21 19 18 14 13 12 11 10 8 7 6 72 54 42 30 27 26 23 Y28 Y29 AA18 AA19 AA21 AA22 AA24 AA25 AA27 AA28 AA29 AC18 AC19 AC21 AC22 AC24 AC25 AC27 AC28 AC29 AD18 AD19 AD21 AD22 AD24 AD25 AD27 AD28 AD29 AD31 AE18 AE21 AE24 AE27 AE28 AE31 AG18 AG19 AG21 AG22 AG24 AG25 AG27 AG29 AH19 AH21 AH31 AH32 AJ31 AJ32 AJ34 AJ35 AL31 AL32 AL34 AL35 AL37 AL38 AM31 AM32 540mA 21 19 18 14 13 12 11 10 8 7 6 72 54 42 30 27 26 23 PP1V05_S0 AL40 AL41 AM40 AM41 AN40 AN41 AR41 AT40 AT41 AU41 AU43 AW42 VSS_SCB 3300 mA (2 ch. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. 6 7 8 18 22 45 53 65 72 1700 mA (1 ch. 8 SCALE SHT NONE Current numbers from Crestline EDS.

3V CERM-X5R 402 PP1V25_S0 42 30 29 0.05V) D 6 NB_VTTLF_CAP1 6 NB_VTTLF_CAP2 6 NB_VTTLF_CAP3 1 C1902 1 0.47UF 1 10% C1901 2 6.3V CERM-X5R 402 AXD 72 21 6 A PEG 100 mA C C1900 0. doc #21749. 8 SCALE SHT NONE Current numbers from Crestline EDS.47UF 2 10% 6. INC.8 6 7 2 3 4 5 1 OMIT L35 VCC_SYNC U1400 CRESTLINE_USFF 80 mA 72 22 6 PP3V3_S0_NB_VCCA_CRTDAC J33 VCCA_CRT_DAC L33 VCCA_CRT_DAC 5 mA 72 22 6 PP3V3_S0_NB_VCCA_DAC_BG J31 VCCA_DAC_BG GND H32 VSSA_DAC_BG D FCBGA (8 OF 10) VTT PP3V3_A_S0 CRT 44 42 30 29 30 mA 13 8 7 6 28 27 26 25 24 23 22 21 19 16 64 63 60 53 52 51 46 D50 VCCA_DPLLA PP1V25_S0_NB_VCCA_DPLLB J49 VCCA_DPLLB 10 mA J45 VCCA_LVDS L45 VCCA_LVDS S0 or S3M is acceptable PP1V8_S0_NB_VCCTXLVDS 72 22 19 6 PLL PP1V25_S0M_NB_VCCA_HPLL 72 21 6 A LVDS 50 mA AK10 VCCA_HPLL GND K44 VSSA_LVDS PP3V3_A_S0 Y48 VCCA_PEG_BG GND W47 VSSA_PEG_BG PP1V25_S0_NB_PEGPLL P48 VCCA_PEG_PLL G7 AA7 P12 VTT_FSB_NCTF PP1V25_S0_NB_VCCA_DPLLA 72 22 6 100 mA U13 T15 R13 R15 N14 R19 R18 R16 N16 VCC_AXD 72 22 6 VTTLF POWER PP1V05_S0 F2 B6 H12 H16 R7 L7 P10 L11 K12 N18 K16 AN29 AN28 AN27 AN35 AN34 AN19 AN18 6 7 8 10 11 12 13 14 TBD mA 18 21 23 26 27 30 42 54 72 770 mA @ 667MHz FSB (1.4 mA 13 8 7 6 28 27 26 25 24 23 22 21 19 16 64 63 60 53 52 51 46 44 @ 1067MHz FSB (1.05V) 6 7 8 16 18 19 21 26 27 51 57 72 515 mA C VCC_AXD_NCTF AR32 VCC_AXD_NCTF AR31 PP3V3_S0_NB_VCCA_TVDACA 72 22 6 PP3V3_S0_NB_VCCA_TVDACB 72 22 6 PP3V3_S0_NB_VCCA_TVDACC M25 VCCA_TVA_DAC K26 VCCA_TVB_DAC K28 VCCA_TVC_DAC 60 mA 72 22 19 6 PP1V5_S0_NB_VCCD_CRT 60 mA 72 22 19 6 PP1V5_S0_NB_VCCD_CRT L31 VCCD_CRT G29 VCCD_TVDAC PP1V5_S0_NB_VCCD_QDAC H30 VCCD_QDAC 72 22 6 250 mA 16 8 7 6 72 57 51 27 26 21 19 18 150 mA 8 7 6 72 61 51 22 J47 VCCD_LVDS1 L47 VCCD_LVDS2 PP1V8_S0 LVDS Y44 VCCD_PEG_PLL 495 mA 6 7 8 16 18 19 21 26 27 51 57 72 100 mA B 200 mA 6 21 72 VCC_SM_CK BL21 VCC_SM_CK BK22 VCC_SM_CK BJ21 VCC_HV L41 AH8 VCCD_HPLL PP1V25_S0 PP1V25_S0 PP1V8_S3M_NB_VCCSMCK VCC_TX_LVDS J43 D 5 mA TV/CRT 40 mA 6 7 8 16 18 19 21 26 27 51 57 72 N22 R22 R24 T22 T24 U16 U18 U19 U21 U22 U24 W16 VCC_DMI AK44 SM CK B 72 22 6 PEG 40 mA BK34 VCCA_SM_CK1 BL35 VCCA_SM_CK2 DMI 40 mA PP1V25_S0 A CK 16 8 7 6 72 57 51 27 26 21 19 18 CRT 35 mA VCC_AXF_NCTF AXF VCC_AXF PP1V25_S0 J23 C23 B24 W18 W22 W24 PP1V8_S0_NB_VCCTXLVDS 100 mA 6 19 22 72 PP3V3_A_S0 51 52 53 60 63 64 6 7 8 13 16 19 21 22 23 100 24 25 26 27 28 29 30 42 44 46 PP1V05_S0_NB_VCCPEG 6 15 21 72 1260 mA PP1V05_S0_NB_VCCRXRDMI 21 260 mA mA VCC_PEG AB44 VCC_PEG AC45 VCC_PEG AD46 VCC_PEG AE45 VCC_RXR_DMI AK46 VCC_RXR_DMI AH46 NB Power 2 A SYNC_MASTER=M70 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.0 OF 19 1 73 A . 051-7230 B.0.3V CERM-X5R 0. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.25V) 850 mA @ 800MHz FSB (1. 7 6 5 4 3 2 REV.47UF 2 402 10% 6.

8 6 7 5 3 4 OMIT VSS C B A FCBGA 1 VSS AN1 AN21 AN25 AN31 AN32 AN45 AN47 AN5 AN51 AP12 AP44 AP48 AP8 AR18 AR19 AR21 AR27 AR28 AR29 AR34 AR35 AR40 AR5 AR51 AT16 AT31 AT32 AT44 AT48 AT8 AU1 AU15 AU37 AU38 AU40 AU5 AU51 AU55 AV12 AV44 AV48 AV8 AW18 AW20 AW22 AW24 AW34 AW5 AW51 AY13 AY15 VSS AY17 AY19 AY21 AY23 AY25 AY27 AY29 AY31 AY33 AY35 AY37 AY39 AY41 AY43 AY48 AY8 B48 BA1 BA5 BA51 BA55 BB38 BB40 BB48 BB8 BC5 BC51 BD10 BD12 BD14 BD16 BD18 BD20 BD22 BD24 BD26 BD32 BD34 BD36 BD38 BD40 BD42 BD44 BD46 BE1 BE5 BE51 BE55 BE9 BG11 BG13 BG15 BG17 BG19 BG21 BG23 BG25 BG33 BG35 BG37 BG39 BG41 BG43 BG45 BG47 BG49 BG5 BG53 BG7 BG9 BJ27 BJ31 BJ35 BK20 BL11 BL15 BL25 BL27 BL31 BL33 BL41 BL45 BL49 BL7 C31 D4 D48 E11 E13 E15 E17 E19 E21 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E51 E7 E9 F48 G1 G23 G5 H18 H20 H22 H24 H26 H34 H36 H38 H40 H48 H54 J1 J11 J15 J29 J51 J7 J9 K32 K46 K48 K6 L1 L25 L27 L51 M10 M13 M15 M17 M19 (10 OF 10) U1400 FCBGA CRESTLINE_USFF D U1400 CRESTLINE_USFF A11 A15 A19 A23 A27 A31 A37 A41 A43 A7 AA16 AA31 AA43 AA49 AA5 AB12 AB8 AC1 AC15 AC31 AC43 AC47 AC49 AC5 AC51 AD12 AD32 AD41 AD44 AD54 AD8 AE1 AE19 AE22 AE25 AE29 AE32 AE34 AE38 AE49 AE5 AF12 AF44 AF8 AG28 AG31 AG32 AG34 AG38 AG47 AG5 VSS AG51 AH12 AH15 AH18 AH34 AH35 AH44 AH54 AJ1 AJ19 AJ22 AJ25 AJ29 AJ37 AJ38 AJ40 AJ41 AJ45 AJ49 AJ5 AJ51 AJ9 AK12 AK8 AL16 AL19 AL21 AL29 AL47 AL49 AL5 AM12 AM16 AM19 AM21 AM22 AM24 AM25 AM27 AM28 AM29 AM34 AM35 AM37 AM38 AM44 AM52 AM8 2 OMIT VSS VSS M21 M23 M27 M29 M31 M33 M35 M37 M39 M41 M43 M54 M6 M8 N20 N24 N26 N28 N30 N32 N34 N36 N38 N40 N42 N49 N5 P46 P8 R1 R21 R25 R28 R32 R34 R37 R41 R45 R49 R5 R51 T12 T16 T18 T19 T21 T25 T28 T32 T34 T37 T41 T46 T54 T8 U1 U15 U25 U28 U32 U34 U37 U49 U5 V12 V44 V8 W1 W13 W15 W19 W21 W25 W28 W31 W32 W34 W37 W43 W45 W49 W5 W51 D C B Y12 Y16 Y18 Y22 Y24 Y31 Y41 Y46 Y54 Y8 NB Grounds SYNC_MASTER=M70 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. 051-7230 B. INC.0.0 OF 20 1 73 A . THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. SCALE SHT NONE 8 7 6 5 4 3 2 REV.

3V CERM 2 805 6 19 72 50 mA C2182 0.7UF 20% 6.1UF 330UF this is "1 of 2" 1.3V 2 X5R 201 2 C2132 1 0.2 MM VOLTAGE=1.5 MM MIN_NECK_WIDTH=0.220mA.8V I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.8 6 7 1 I/O voltage Supply GMCH Core Power 21 19 18 14 13 12 11 10 8 7 6 72 54 42 30 27 26 23 2 3 4 5 57 51 27 26 21 19 18 16 8 7 6 72 PP1V05_S0 Host PLL Digital Supply PP1V25_S0 PP1V25_S0 6 7 8 16 18 19 21 26 27 51 57 72 57 51 27 26 21 19 18 16 8 7 6 72 495 mA 1600 mA C2100 1 D 1 20% 2. Place C2174 Near Pins AB44.22uF 20% 6.5V 2 POLY CASE-B2-HF MIN_LINE_WIDTH=0. Place C2177 Near Pins AH46.1 Layout Note: PLACE C2145.25 MM MIN_NECK_WIDTH=0.3V NOTE: This follower is redundant if VCORE is always 1.3V 2 X5R 201 1 0. C2133 22UF 20% 6.3V 2 CERM 805 PLACEMENT_NOTE=Place C2132.3V 2 CERM 805 PLACEMENT_NOTE=Place C2121-24 close to U1400.3A-EMI CRITICAL 1 L2173 PP1V05_S0 21 19 18 14 13 12 11 10 8 7 6 72 54 42 30 27 26 23 540 mA 1 22UF C2111 1 0.3V 2 X5R 201 C2115 0.3V 2 CERM 402 B C2145 1 22UF C2148 0. Current numbers from Crestline EDS Addendum.1UF 10% 6.3V 2 X5R 402 PP1V25_S0 450 mA OMIT CRITICAL PP1V25_S0 RX and I/O Logic for DMI PP1V05_S0_NB_VCCRXRDMI PP1V05_S0 850 mA 19 260 mA C2121 C2122 1 4..0.2 MM VOLTAGE=1..W47 1% 1/20W MF 201 2 1K PP0V9_S3M_MEM_NBVREFA NB_VTTREF_DIV 1 GND 1% 1/20W MF 201 2 8 16 68 1.3V 2 X5R 201 5 mA Layout Note: PLACE C2165 BETWEEN Y48.8V 2 0603 NB_VTTREF_DIV 1 R2112 Layout Note: PLACE C2161 NEAR PIN L41 1 200 mA PP1V8_S3 OMIT 1% 1/20W MF 201 2 C2195 1 PP1V8_S3_NB_VCCSMCK_RC THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. 051-7230 B.1UF 10% 6.7uF C C2123 1 4.5ohm GMCH ME Core Power 1 C2180 2 X5R PLACEMENT_NOTE=Place in GMCH cavity 21 19 18 14 13 12 11 10 8 7 6 72 54 42 30 27 26 23 6 7 8 16 18 19 21 26 27 51 57 72 250 mA Layout Note: PLACE C2170 NEAR J23.W24 1UF 0.1UF 10% 6.AN18 C2151 1UF 10% 6..1UF 0.3V CERM-X5R 2 402 20% 6.F2.3V 2 CERM 603 C2124 1 2.47UF 20% 6..3V 2 X5R 201 1 C2165 0.25V 10uF 20% 6. 35 mA 1 2 SOD-723 Layout Note: PLACE C2143.25V 2 0603 R2190 1 1.7uF 20% 6. 1 1 C2191 1 0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1. 8 SCALE SHT NONE 7 6 5 4 3 2 REV. PP1V25_S0 6 7 8 16 18 PP1V25_S0 675 mA 72 CRITICAL 1 100UF C2142 1 22UF 4.0 OF 21 1 73 A .1UF 6 19 72 200 mA Layout Note: PLACE C2197 AND FILTER CLOSE TO BL21.2uF 20% 6.05V 2 1210 CRITICAL 22UF 220UF Place C2113-2115 close as possible to AH31.3V 2 X5R 402 C2113 1 0.3V 2 X5R 201 10% 6.3V 2 X5R 402 1 C2104 C2170 10% 2 6.3V 2 CERM 805 20% 6.0.2 MM VOLTAGE=1.5A PP1V25_S0 1 100 mA PP1V25_S0_NB_PEGPLL MIN_LINE_WIDTH=0.3V CERM 2 805 1 C2197 0.AN38 Memory clock logic voltage.BL29 Place C2135 where LVDS taps from DDR2 plane.. 57 51 27 26 21 19 18 16 8 7 6 72 Memory I/O logic and DLL voltage.3V 2 CERM 603 1 1 0.3V 2 X5R 603 Layout Note: PLACE NEAR NB SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY MIN_LINE_WIDTH=0.3V 2 X5R-CERM 603 1 C2144 1UF 10% 6.AK46 22UF 10% 6.3V 2 POLY B2-HF C2143 10% 6.3V X5R Layout Note: Place C2182 Near Pin AK10 201 250mA.2 MM VOLTAGE=3.and Term Voltage for PCI-E Graphics PP1V05_S0_NB_VCCPEG 6 15 19 72 91NH PP1V05_S0 1520 mA C2110 D Layout Note: Place C2180 Near Pin AH8 250mA.3V CERM1 2 603 C2177 Layout Note: 22uF caps should be close to MCH on opposite side.2 MM VOLTAGE=1..3V 10% 6.. THE POSSESSOR AGREES TO THE FOLLOWING 10uF 20% 6.1 PP0V9_S3M_MEM_NBVREFB 1% 1/16W MF-LF 402 2 22UF 1 20% 6.150mohm max" PP1V8_S3 L2195 PP1V8_S3 51 35 34 32 31 21 18 16 8 7 6 72 68 55 1.25 MM MIN_NECK_WIDTH=0.1UF 10% 6.2 MM VOLTAGE=1.3V 1 2 X5R 201 201 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0..C2148 NEAR BL35.I/O logic.AE45 20% 6.0.1UF 10% 6. then GND R2195 1 R2110 1K PP1V8_S3M_NB_VCCSMCK MIN_LINE_WIDTH=0.3V 2 CERM 805 C2103 1 0.3V 201 L2181 Host PLL Analog Supply PP1V25_S0M_NB_VCCA_HPLL 120-OHM-0.5ohm These supplies are still needed even using external GPU GMCH FSB I/O Rail 21 19 18 14 13 12 11 10 8 7 6 72 54 42 30 27 26 23 0402-LF 1260 mA Layout Note: 22uF caps should be close to MCH on opposite side.3V 2 X5R 2 C2192 2 X5R 201 6 19 72 B 100 mA Layout Note: PLACE C2191 NEAR U1400.P48 PLACE C2192 NEAR U1400.3V 2 X5R 402 1 0. INC.3V 2 CERM 805 C2112 1 0.05V..1UF 20% 6.23A 51 35 34 32 31 21 18 16 8 7 6 72 68 55 72 31 21 18 16 8 7 6 68 55 51 35 34 32 NB_VTTREF_DIV1 60 53 52 51 46 44 100 mA 21 19 16 13 8 7 6 PP3V3_A_S0 42 30 29 28 27 26 25 24 23 22 64 63 PP1V25_S0 72 100 mA 6 A 1 Layout Note: PLACE C2160 NEAR PIN AK44 28 29 6 7 8 13 16 19 21 22 23 24 25 26 27 30 42 44 46 51 52 53 60 63 64 PP3V3_A_S0 57 51 27 26 21 19 18 16 8 7 C2160 1 0.1UF 20% 6.C2133 close to U1400..22uF 20% 6.3V CERM 805 20% 2.3V 2 CERM 402 need to find "1uH.BK34 1% 1/16W MF-LF 402 201 72 6 OMIT C2190 Memory voltage supply. doc .3V 2 X5R Place C2110-12 on edge near AH31.1UF 10% 6.25V 2 C2174 1 C2173 Layout Note: Place L and C close to MCH 10% 6.BJ21 10% 6.1UF C2161 0.C2144 NEAR AL18.AM32 C2114 Analog.3V 2 X5R 1 PP3V3_S0_NBCORE_FOLLOW_R 10 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 PP3V3_A_S0 2 1% 1/16W MF-LF 402 Analog PLL Voltage for PCI-E GPU L2190 57 51 27 26 21 19 18 16 8 7 6 72 6 7 8 16 18 19 21 26 27 51 57 72 FERR-220-OHM-2.4 MM MIN_NECK_WIDTH=0.3V 2 CERM 805 20% 6.3V 2 CERM 805 10% 6.1UF 20% 6.5V POLY CASE-C2-SM-1 C2101 1 22UF 330UF 2 C2102 1 0. PP1V25_S0 R2186 1SS418 PP1V05_S0 640 mA OMIT C2140 1 D2186 72 54 42 30 27 8 7 6 26 23 21 19 18 14 13 12 11 10 19 21 26 27 51 57 6 7 8 16 18 19 21 26 27 51 57 72 OMIT 1 Layout Note: PLACE C2151 NEAR AN29.3V CERM 402 10% 6.BA27.AM32 C2181 1 1 22UF 20% 6.22uF 20% 6.1UF 10% 2 6..K16 C GMCH Memory I/O Rail 51 35 34 32 31 21 18 16 8 7 6 72 68 55 PP1V8_S3 3300 mA CRITICAL C2130 1 1 20% 2.3V 2 X5R 201 NB Standard Decoupling SYNC_MASTER=M70 R2111 1K C2196 8 16 68 NB_VTTREF_DIV 1 R2113 72 6 1K 1% 1/20W MF 201 2 Layout Note: Route to caps.0UH-0..22uF 20% 6.3V 2 X5R 603 515 mA PP1V25_S0 1 MIN_LINE_WIDTH=0.0V POLY CASE-B2-HF C2135 1 22UF 10% 6.25 MM MIN_NECK_WIDTH=0.8V bulk decoupling caps..Y44 201 PP1V25_S0_NB_PEGPLL_RC MIN_LINE_WIDTH=0.

2 MM VOLTAGE=3.2 MM VOLTAGE=3.1UF 100 10% 6.5A PP3V3_S0_NB_TVDAC C2201 72 12 11 8 7 6 54 27 26 22 C2289 L2288 MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.5.3V 2 X5R 201 5 mA 2 0.1UF 10% 2 6.1UF 10% 6.01UF 2 19 6 72 22 1 MIN_LINE_WIDTH=0.3V 0603 1UF 10% 6. 78MOHM" INDUCTOR L2220 72 61 51 22 19 8 7 6 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 1.2 MM VOLTAGE=1.3V X5R 603 2 OMIT C2214 C2215 2.3V 2 X5R 603 20% 6.2 MM VOLTAGE=3.01UF 10% 10V X5R 201 C2207 PP1V5_S0_NB_VCCD_QDAC 2 6 19 72 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.1UF PP3V3_S0_NB_VCCA_TVDACC 6 19 72 MIN_LINE_WIDTH=0.2 MM VOLTAGE=3.3V CERM 402 CRITICAL 72 6 NR 2 5 NC GND 3 6 205 mA C2282 PAD 1 1 16V NFM18 PP1V5_S0_NB_VCCD_CRT 1 C2285 125 mA C2202 1 10% 10V X5R 201 2 1 0.5V) 80 mA OMIT C2265 1UF 1 TPS731125 SOT23-5 1 IN OUT 5 3 EN NR/FB 4 GND 72 6 R2261 PP1V25_S0_NB_DPLL MIN_LINE_WIDTH=0.7V .3V 2 CERM 402 A Vout = 1. doc #20127.204V * (Ra + Rb)/Rb Ra || Rb should be 19Kohms 1 PP1V25_S0_NB_VCCA_DPLLA MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1. 8 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY SCALE SHT NONE 6 5 4 3 2 REV.25V 2 5% 1/16W MF-LF 402 OMIT 6 0 1 80 mA C2266 1 1 P1V25S0NBDPLL_RF C2267 0. 051-7230 B.3V 2 X5R 201 2 OMIT 72 65 53 45 18 8 7 6 7700 mA C Layout Note: These 11 caps should be within 6.3V SOD-723 10% 10V X5R 201 PP1V5_S0_NB_VCCD_CRT PP1V5_S0_NB_VCCD_CRT MAKE_BASE=TRUE 2 C2288 C2292 22000pF-1000mA 16V NFM18 72 6 1 PP3V3_S0_NB_TVDAC_F MIN_LINE_WIDTH=0.2 MM VOLTAGE=3.35 mm of NB edge PPVCORE_S0_NB_GFX CRITICAL OMIT C2210 1 1 Layout Note: These 4 caps should be within 6.2UF 20% 6.3V CERM 402-LF 20% 2 6.2 MM MIN_NECK_WIDTH=0.300 2 5% 1/10W FF 603 1 OMIT C2260 10uF 1 20% 6. 500MA.3V X5R 603 2 X5R 80 mA Place C2261 close to Pin D50 SYNC_MASTER=M70 201 1 R2266 R2262 0.3V 2 CERM 402-LF 1 C2242 2.3V X5R 201 22000pF-1000mA 16V NFM18 1 PLACEMENT_NOTE=Place in GMCH cavity C CRITICAL 0.0 OF 22 1 73 A .3V X5R 2 201 CRITICAL 1% 1/16W MF-LF 402 2 C2206 22000pF-1000mA 16V NFM18 1 PP1V5_S0_NB_QDAC MIN_LINE_WIDTH=0.3V 2 CERM 402-LF CRITICAL C2294 22000pF-1000mA OMIT 1 16V NFM18 C2243 1 2.3V 150 mA R2250 22K C2299 PP3V3_S0_NB_VCCA_DAC_BG 3 GND 1NO STUFF R2249 1 1 1 GND PP1V8_S0 1 1 16V NFM18 Layout Note: Route to cap.25V P1V25S0NBDPLL_FB 2 10% 6.2 MM MIN_NECK_WIDTH=0.8V 2 1007 CRITICAL1 1NO STUFF 1NO STUFF R2242 R2243 22K 5% 1/20W MF 2 201 22K 5% 1/20W MF 2 201 1 NO STUFF R2244 22K 5% 1/20W MF 2 201 R2245 5% 1/20W MF 2 201 OUT 6 16 53 OUT 6 16 53 OUT 6 16 53 OUT 6 16 53 R2247 1R2248 22K 5% 1/20W MF 2 201 22K 5% 1/20W MF 2 201 2 C2297 10% 6.2 MM VOLTAGE=1.01UF 7 16V NFM18 72 6 P3V3TVDAC_NOISE THRML 22000pF-1000mA 180-OHM-1.3V 3 CRITICAL R2285 1SS418 6 19 22 72 0.2 MM VOLTAGE=1.2UF 20% 2 6.4 MM MIN_NECK_WIDTH=0.3V 2 X5R 603 1UF OMIT C2232 1 10uF 20% 6.5V 0.1UF 1 OMIT C2219 1 10uF 500 uA C2208 OMIT C2231 1 10uF 20% 6.3V CERM 402-LF 1 C2216 0.4 MM MIN_NECK_WIDTH=0.35 mm of NB edge 20% 2.01UF 6 19 72 MIN_LINE_WIDTH=0.2 MM VOLTAGE=3.2UF PP3V3_S0_NB_VCCA_TVDACB 6 19 72 MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.6MM MIN_NECK_WIDTH=0.3V X5R 201 1 C2218 C2296 10% 2 6.2 MM VOLTAGE=3.3V 40 mA 2 10% 10V X5R 201 C2291 R22051 PP3V3_S0_NB_VCCA_TVDACA 3 0. 40 mA 2 NEED TO FIND A "1#GH.0. then GND GFX_VID<0> GFX_VID<1> GFX_VID<2> GFX_VID<3> B C2298 Place C2221.8 6 7 2 3 4 5 1 PP5V_S0 63 53 52 51 47 43 40 27 8 7 6 72 205 mA 1 R2281 OMIT C2280 1 2 5% 1/20W MF 201 D 6 1 P3V3TVDAC_EN_RC 4 EN NO STUFF NC C2281 NOTE: This filter is required even if using only external graphics. THE POSSESSOR AGREES TO THE FOLLOWING 6 19 72 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT C2262 0.3V 3 Place smaller caps as close as possible to NB pins.3V 2 X5R 603 10% 10V 2 X5R 201 NO STUFF 6 19 22 72 MIN_LINE_WIDTH=0.47UF 10% 2 6.2 MM VOLTAGE=1.1UF 6 7 8 19 22 51 61 72 Layout Note: Route to caps.1UF 10% 6.3V CERM 2 402 CRITICAL CRITICAL U2280 0 1 0.675A PP1V8_S0 1 260 mA PP3V3_A_S0 PP1V8_S0_NB_VCCTXLVDS MIN_LINE_WIDTH=0.2UF 20% 6.3V PP3V3_S0_NB_VCCA_CRTDAC 1 PP3V3_S0_NB_CRTDAC_F 10UF 0.3V 0603 1% 1/16W MF-LF 402 D CRITICAL L2290 180-OHM-1.25V 2 5% 1/16W MF-LF 402 1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.5V 1 C2205 Filtering changed per SR MOW # 541194 1 0. then GND C2226 Place C2226 close to Pins J47.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3 MM MIN_NECK_WIDTH=0.5V 3 1 80 mA OMIT 22000pF-1000mA PP1V5_S0 MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.01UF 10% 2 10V X5R 201 C2261 NB Graphics Decoupling 0. VCCD_TVDAC also powers internal thermal sensors. INC.3V III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART Place C2262 close to Pin J49 2 X5R SIZE 201 Current numbers from Crestline EDS Addendum.J43 and K44 10% 16V 2 X7R 201 10% 2 16V X7R 201 20% 2.C2223 close between J45.2 MM VOLTAGE=1.3V CERM-X5R 402 1 C2217 0. 7 DRAWING NUMBER D APPLE INC.3 MM MIN_NECK_WIDTH=0.2UF 20% 2 6.2UF 20% 6.5A 2 6 19 72 80 mA Layout Note: These 2 caps should be within 6.3V 2 X5R 201 72 54 27 11 8 7 6 26 22 12 2 PP1V5_S0 60 mA 1 PP3V3_S0_NB_TVDAC_FOLLOW 10 1 MIN_LINE_WIDTH=0.1UF 10UF 6 6 19 72 10% 6.5V POLY CASE-C2-SM-1 OMIT C2213 1 10uF 330UF 1 2.3V 2 X5R 603 OMIT C2240 2.1UF 10% 6.L45.01UF PP1V5_S0_NB_VCCD_CRT 2 C2200 MIN_LINE_WIDTH=0.3V 3 20% 6.3V 2 CERM 805 22K 5% 1/20W MF 2 201 1 10% 10V X5R 201 0.5V 3 1 0.01UF 2 NO STUFF D2285 60 mA C2295 20% 6.3V 2 CERM 402-LF 40 mA 2 GMCH Graphics Core Power 10% 10V 2 X5R 402-1 10% 6.3V 2 X5R 603 0 PP1V25_S0_NB_VCCA_DPLLB MIN_LINE_WIDTH=0.0UH-0. L47 22UF 20% 6.2MM VOLTAGE=3.3V X5R 201 1 125 mA 22 6 19 72 C2293 6 19 72 MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.3V 2 CERM 402-LF 1 OMIT C2241 2.35 mm of NB edge 0.3 MM MIN_NECK_WIDTH=0.1UF 10% 2 6. TPS79933 SON OUT 1 6 IN 1UF 10% 2 6.5A-0.3 MM MIN_NECK_WIDTH=0.3V 2 X5R 201 CRITICAL U2265 WARNING VOLTAGE DROP 72 61 51 22 19 8 7 6 PP1V8_S0 (1.2 MM VOLTAGE=1.5V 2 POLY CASE-B2-SM-HF CRITICAL 22000pF-1000mA C2223 1000PF 1000PF 220UF 22K C2221 1 C2220 1 1 6 19 72 110 mA 5% 1/20W MF 2 201 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 B PP3V3_A_S0 10 mA 1 C2230 Place C2230 close to Pin L35 0.3V 20% 2 6.3 MM MIN_NECK_WIDTH=0.

9 1% 1/20W MF 201 OUT 6 10 66 OUT 6 10 66 OUT 6 10 66 NMI SMI* Y23 W22 CPU_NMI OUT 6 10 66 CPU_SMI_L OUT 6 10 66 INT PD STPCLK* W24 CPU_STPCLK_L OUT 6 10 66 THRMTRIP* W20 6 R2309 54.8 6 7 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 2 3 4 5 1 PP3V3_A_S0 1 R2310 43 42 41 40 39 28 27 26 8 7 6 72 59 57 44 8.000MHZ CLOCK W/INTERNAL WEAK PD HDA_BIT_CLK NOTICE OF PROPRIETARY PROPERTY HDA_RST# HDA_SDIN[0-2] INTEGRATED PDs HDA_SDOUT INTEGRATED PD ACZ_SYNC INTEGRATED PD THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. Disk.9 1% 1/20W MF 201 1% 1/20W MF 201 1% 1/20W MF 201 2 2 D 1 R2301 332K 2 OMIT AA23 AA24 RTCX1 RTCX2 IN SB_RTC_RST_L AB22 RTCRST* IN SB_SM_INTRUDER_L AB23 INTRUDER* AA19 Y19 INTVRMEN LAN100_SLP 6 SB_INTVRMEN 6 SB_LAN100_SLP TP_ENET_GLAN_CLK TP_LAN_RSTSYNC 6 41 43 BI 6 41 43 LPC_AD<2> BI 6 41 43 FWH4/LFRAME* B2 LPC_FRAME_L LDRQ0* LDRQ1*/GPIO23 F8 B1 TP_LPC_DRQ0_L TP_LAN_R2D<2> LAN_PHYPC W18 GLAN_DOCK*/GPIO12 TP_LAN_R2D<1> 27 27 1 HDA_SYNC R2313 R2314 1 2 HDA_RST_L R2315 27 1 2 OUT HDA_BIT_CLK 69 37 9 7 6 OUT 69 37 9 6 OUT IN HDA_SDIN0 2 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 70 6 GLAN_COMP 69 6 HDA_BIT_CLK_R 69 6 69 6 27 1 2 69 6 5% 1/20W MF AA20 W21 HDA_RST* AD12 Y11 AD11 W11 HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_DOCK_EN_L TP_HDA_DOCK_RST_L TP_SB_SATALED_L UNUSED SATA INTERFACE 9 69 9 69 9 69 B 9 69 9 69 9 69 NC_SATA_A_R2D_C_N NC_SATA_A_R2D_C_P NC_SATA_B_R2D_C_N NC_SATA_B_R2D_C_P NC_SATA_C_R2D_C_N NC_SATA_C_R2D_C_P 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 52 51 46 44 42 30 29 28 27 26 AD3 AD10 AC3 AA4 AA3 AB1 AB2 V5 V4 V1 V2 SATA2RXN SATA2RXP SATA2TXN SATA2TXP W7 W6 SATA_CLKN SATA_CLKP U4 U5 1 R2311 10K 5% 1/20W MF 201 SB_GPIO10_CL1 25 6 6 43 25 6 LAN_ENERGY_DET BOOTROM_OVR_EN_L AB15 AD18 AC24 BI SB_A20GATE PP1V05_S0 5% 1/32W 4X0201 1 1 CPU_A20M_L OUT 6 10 66 CPU_DPRSTP_L OUT 6 10 16 52 66 OUT 6 10 66 CPU_DPSLP_L 8 RP2405 10K 1 W19 Y22 CPU_PWRGD OUT 6 10 13 66 IGNNE* Y20 CPU_IGNNE_L R2305 54.2K PP1V5_S0_SB_VCC1_5_B 5% 1/20W MF 201 PP3V42_G3H D 1 R2300 IN SB_RTC_X1 OUT SB_RTC_X2 R2302 332K 24.0 OF 23 1 73 A .2K INT PD SATA 6 10 66 R2308 1 IHDA IN C CPU_THERMTRIP_R DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 TP8 INT PD 6 7 8 10 11 12 13 14 18 19 21 26 27 30 42 54 72 PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB) 1 CPU_FERR_L AA22 CPU_INIT_L AA21 CPU_INTR AD8 6 SB_RCIN_L INIT* INTR RCIN* INT PD SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP 8 RP2502 8. INC. 051-7230 B.9 1% 1/20W MF 201 2 PM_THRMTRIP_L IN 6 10 16 42 66 PLACEMENT_NOTE=Place R2308 within 50mm of U2300 2. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. SCALE SHT NONE 8 7 6 5 4 3 2 REV.2K 5% 1/32W 4X0201 FERR* HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO34 W4 W3 Y1 Y2 6 6 41 43 6 41 43 INT PD HDA_SDOUT SATALED* NC_EXTGPU_PWR_EN BI OUT CPUPWRGD/GPIO49 CPU GLAN_COMPI GLAN_COMPO AD13 AB10 DPRSTP* DPSLP* 201 6 2 LAN/GLAN HDA_RST_L_R HDA_SDOUT_R AC9 Y17 LPC_AD<3> 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 PP3V3_A_S0 INT PU HDA_SYNC_R TP_HDA_SDIN3 A20GATE A20M* INT PU HDA_BIT_CLK HDA_SYNC TP_HDA_SDIN2 R2316 INT PU AC10 AD9 TP_HDA_SDIN1 HDA_SDOUT D24 D23 INT PU LAN_RSTSYNC LAN_TXD0 LAN_TXD1 LAN_TXD2 TP_LAN_R2D<0> OUT BI LPC_AD<1> GLAN_CLK B23 C18 A23 TP_LAN_D2R<2> C C22 INT PU LAN_RXD0 LAN_RXD1 LAN_RXD2 TP_LAN_D2R<1> 25 6 C23 RTC LPC B21 D18 B20 TP_LAN_D2R<0> 69 37 9 7 6 LPC_AD<0> BGA (1 OF 6) 28 6 69 37 9 7 6 E7 D6 C6 B6 SB_ICH8M 28 6 69 37 9 7 6 FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 U2300 IDE NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S 28 6 28 6 1 2 INT PU 72 27 26 24 6 BI 6 38 69 IDE_PDD<3> BI 6 38 69 IDE_PDD<4> BI 6 38 69 IDE_PDD<5> BI 6 38 69 IDE_PDD<6> BI 6 38 69 IDE_PDD<7> BI 6 38 69 IDE_PDD<8> BI 6 38 69 IDE_PDD<9> BI 6 38 69 IDE_PDD<10> BI 6 38 69 IDE_PDD<11> BI 6 38 69 IDE_PDD<12> BI 6 38 69 IDE_PDD<13> BI 6 38 69 IDE_PDD<14> BI 6 38 69 IDE_PDD<15> BI IDE_IRQ14 5% 1/20W MF 201 2 6 38 69 IN 6 38 69 IDE_PDIORDY IN 6 38 69 IDE_PDDREQ IN 6 38 69 B ALERT*/GPIO10 ENERGY_DETECT/GPIO13 NETDETECT/GPIO14 SB Enet. LPC HDA A SYNC_MASTER=M70 SYNC_DATE=01/09/2007 24. FSB.0.9 1% 1/20W MF 2 2 201 INT PD NO STUFF 1 W23 TP_SB_TP8 M1 L5 M4 M6 N4 N3 R3 P1 L2 L3 M5 U1 N6 M3 M2 T3 IDE_PDD<0> BI 6 38 69 IDE_PDD<1> BI 6 38 69 IDE_PDD<2> DA0 DA1 DA2 R5 P5 T4 IDE_PDA<0> OUT 6 38 69 IDE_PDA<1> OUT 6 38 69 IDE_PDA<2> OUT 6 38 69 DCS1* DCS3* T1 R4 IDE_PDCS1_L OUT 6 38 69 IDE_PDCS3_L OUT 6 38 69 DIOR* DIOW* DDACK* IDEIRQ IORDY DDREQ R2 N1 P3 P4 P2 R1 IDE_PDIOR_L OUT 6 38 69 IDE_PDIOW_L OUT 6 38 69 IDE_PDDACK_L OUT 6 38 69 R2304 INT PD INT PU INT PD SATARBIAS* SATARBIAS 24.

NOTE: B GNT0# LPC 1 SPI 0 GNT0# HAS INT PU. ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H SPI_CS1# HAS INT PU (NOMINAL=20K. PCIe. SIZE DRAWING NUMBER D APPLE INC. 051-7230 B. R2414 69 6 D 6 16 67 IN R2413 1% INT PD INT PD INT PD RP2405 10K 4 IN OUT Ethernet RP2407 10K 2 70 36 6 70 36 6 70 36 6 DRAM_2GB1 R2442 5% 1/32W 4X0201 1 7 DRAM_SPD_11 RP2406 10K 5% 1/32W 4X0201 4 C 6 PCIE_E_D2R_N EHCI0 49 44 43 36 28 27 26 25 8 7 6 72 60 58 57 56 51 IN 70 36 6 IN 6 16 67 PCI_EXPRESS DIRECT MEDIA INTERFACE pull HDA_SYNC 2 1% 1/20W MF 201 2 NOTE: GNT[0-3]# have internal 20K pull-ups enabled only when PCIRST# = 0 and PWROK = 1 If used. SCALE SHT NONE 8 7 6 5 4 3 2 REV. SIMULATION=15K-35K) IDE_RESET_L 9 70 OUT 6 38 64 63 60 26 25 23 22 21 19 16 13 8 7 6 53 52 51 46 44 42 30 29 28 27 TP_PCI_RST_L OUT PCI_DEVSEL_L BI 6 24 70 PCI_PERR_L BI 6 24 70 70 24 6 PCI_FRAME_L PCI_LOCK_L BI 6 24 70 70 24 6 PCI_IRDY_L PCI_SERR_L BI 6 24 70 70 24 6 PCI_TRDY_L PCI_STOP_L BI 6 24 70 70 24 6 PCI_STOP_L PCI_TRDY_L BI 6 24 70 70 24 6 PCI_SERR_L PCI_FRAME_L BI 6 24 70 70 24 6 PCI_DEVSEL_L 70 24 6 PCI_PERR_L 70 24 6 PCI_LOCK_L RP2403 RP2402 RP2402 RP2403 RP2400 RP2403 RP2402 RP2403 70 24 6 PCI_FW_REQ_L RP2401 70 24 6 PCI_REQ1_L 70 24 6 PCI_REQ2_L 70 24 6 INT_PIRQA_L 70 24 6 INT_PIRQB_L PLT_RST_L OUT PCI_CLK33M_SB IN 6 9 6 7 28 60 64 6 30 71 TP_PCI_PME_L INT_PIRQE_L BI 6 24 70 INT_PIRQF_L BI 6 24 70 DVI_HOTPLUG_DET IN ODD_PWR_EN_L OUT 6 61 62 Provide a pull-down on this GPIO if not used. USB SYNC_MASTER=M70 4X0201 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY 4X0201 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. DMI.2K to 10K.0 OF 24 1 73 A . or PCIe ports 5 & 6 will be disabled. U2300 B 9 BI NC_PCI_AD<0> 9 BI NC_PCI_AD<1> 9 BI NC_PCI_AD<2> 9 BI NC_PCI_AD<3> 9 BI NC_PCI_AD<4> 9 BI NC_PCI_AD<5> 9 BI NC_PCI_AD<6> 9 BI NC_PCI_AD<7> BI NC_PCI_AD<8> 9 BI NC_PCI_AD<9> 9 BI NC_PCI_AD<10> 9 BI NC_PCI_AD<11> 9 BI NC_PCI_AD<12> 9 BI NC_PCI_AD<13> 9 BI NC_PCI_AD<14> 9 BI NC_PCI_AD<15> 9 BI NC_PCI_AD<16> 9 BI NC_PCI_AD<17> 9 A 9 BI NC_PCI_AD<18> 70 9 BI NC_PCI_AD<19> 70 9 BI NC_PCI_AD<20> 9 BI NC_PCI_AD<21> 9 BI NC_PCI_AD<22> 9 BI NC_PCI_AD<23> 9 BI NC_PCI_AD<24> 9 BI NC_PCI_AD<25> 9 BI NC_PCI_AD<26> 9 BI NC_PCI_AD<27> 9 BI NC_PCI_AD<28> 9 BI NC_PCI_AD<29> 9 BI NC_PCI_AD<30> 9 BI NC_PCI_AD<31> 70 24 6 BI INT_PIRQA_L 70 24 6 BI INT_PIRQB_L 70 24 6 BI INT_PIRQC_L 70 24 6 BI INT_PIRQD_L A20 A19 A16 B18 B15 A22 B17 C17 F15 A14 A13 C14 E13 F14 E14 C9 B11 F13 A11 D13 A12 B9 E8 F10 D9 C10 D10 A9 A8 D8 B3 A3 A6 B8 C7 B12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PIRQA* PIRQB* PIRQC* PIRQD* SB_ICH8M BGA (3 OF 6) OMIT INT PU INT PU INT PU REQ0* INT PU GNT0* REQ1*/GPIO50 GNT1*/GPIO51 REQ2*/GPIO52 GNT2*/GPIO53 REQ3*/GPIO54 GNT3*/GPIO55 A7 D7 E16 C16 A18 A17 C12 D11 PCI_FW_REQ_L IN 6 24 70 PCI_REQ1_L IN 6 24 70 IN 6 24 70 PCI_FW_GNT_L MAKE_BASE=TRUE PCI_REQ2_L TP_SB_GPIO53 TP_SB_GPIO55 INTERRUPT I/F C/BE0* C/BE1* C/BE2* C/BE3* BI 9 NC_PCI_C_BE_L<1> BI 9 NC_PCI_C_BE_L<2> BI 9 NC_PCI_C_BE_L<3> BI 9 IRDY* PAR PCIRST* DEVSEL* PERR* PLOCK* SERR* STOP* TRDY* FRAME* F11 C8 C5 D14 A10 F12 A5 B14 E11 A15 PCI_IRDY_L BI 6 24 70 PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5 A4 A2 E10 F9 I/F 5% 1/20W MF 201 R2415 pull-down on GNT0# NC_PCI_C_BE_L<0> AC22 C11 C3 R2415 1K D16 C13 D12 C15 PLTRST* PCICLK INT PU PME* 6 70 SB BOOT BIOS SELECT 1 2 PCI OUT TP_SB_GPIO51 NC_PCI_PAR BI selects SPI ROM by default. TP_PCIE_B_D2R_N high for x2) TP_PCIE_B_D2R_P TP_PCIE_B_R2D_C_N TP_PCIE_B_R2D_C_P D TP_PCIE_EXCARD_D2R_N TP_PCIE_EXCARD_D2R_P ExpressCard TP_PCIE_EXCARD_R2D_C_N TP_PCIE_EXCARD_R2D_C_P TP_PCIE_FW_D2R_N TP_PCIE_FW_D2R_P FireWire TP_PCIE_FW_R2D_C_N TP_PCIE_FW_R2D_C_P PCIe Mini Card (AirPort) CHOOSE 1GB or 2GB CONFIG CHOOSE DRAM VENDOR PP3V3_S5 5 8 RP2407 10K RP2406 10K 5% 1/32W 4X0201 3 5 R2440 10K 10K 5% 1/20W MF 201 5% 1/20W MF 201 6 2 PCIE_E_D2R_P PCIE_E_R2D_C_N OUT PCIE_E_R2D_C_P TP_PCIE_ENET_D2R_N Yukon-PCIE TP_PCIE_ENET_D2R_P Nineveh-GLCI TP_PCIE_ENET_R2D_C_N TP_PCIE_ENET_R2D_C_P DMI_N2S_P<1> IN 6 16 67 DMI_S2N_N<1> OUT 6 16 67 DMI_S2N_P<1> OUT 6 16 67 R20 R19 U23 U24 DMI_N2S_N<2> IN 6 16 67 DMI_N2S_P<2> IN 6 16 67 DMI_S2N_N<2> OUT 6 16 67 DMI_S2N_P<2> OUT 6 16 67 DMI3RXN DMI3RXP DMI3TXN DMI3TXP U20 U19 V22 V21 DMI_N2S_N<3> DMI_CLKN DMI_CLKP N23 N24 SB_CLK100M_DMI_N DMI_ZCOMP DMI_IRCOMP V18 V19 E20 E19 E24 E23 PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP 2 8 RP2405 10K RP2407 10K 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 3 69 49 6 BI SPI_SCLK_R C20 D21 C21 SPI_CLK SPI_CS0* SPI_CS1* 69 49 6 BI SPI_CE_R_L<0> 69 43 6 SPI_CE_R_L<1> D22 D19 SPI_MOSI SPI_MISO INT PD 69 49 6 BI SPI_SI_R 69 49 43 6 BI SPI_SO INT PU INT PU INT PD SPI INT PD INT PD INT PD INT PU INT PD INT PU INT PD 1 INT PD 13 7 6 IN EXTAUSB_OC_L OUT SB_GPIO40 IN USB_EXTD_OC_L 36 13 7 6 OUT WOW_EN 13 7 6 OUT PM_LATRIGGER_L 13 7 6 OUT EXTGPU_LVDS_EN 13 7 6 OUT SB_GPIO30 IN EXTBUSB_OC_L 13 7 6 13 9 7 6 6 6 Y13 AB12 AA12 AD14 W10 AC12 AA11 AB11 AA13 AB13 EXCARD_OC_L USB_EXTC_OC_L DRAM_SPD_2 1 R2443 10K 5% 1/20W MF 201 2 INT PD INT PD USB INT PD INT PD INT PD INT PD INT PD INT PD R2406 R2441 10K INT PD 1 DRAM_1GB1 5% 1/20W MF 201 OC0* OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43 OC5*/GPIO29 OC6*/GPIO30 OC7*/GPIO31 OC8* OC9* EHCI1 39 13 9 7 6 100K 5% 1/20W MF 201 2 IN 6 16 67 DMI_N2S_P<3> IN 6 16 67 DMI_S2N_N<3> OUT 6 16 67 DMI_S2N_P<3> OUT SB_CLK100M_DMI_P 6 DMI_IRCOMP_R 1 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P E2 E3 F3 F4 D1 D2 G3 G2 F1 F2 H3 H4 H1 H2 J2 J3 K1 K2 K4 K3 USBRBIAS* USBRBIAS C1 C2 6 29 30 71 IN 6 29 30 71 24.6 6 23 26 27 72 2 USB2_EXTA_N External A AirPort (PCIe Mini-Card) External D / WWAN Camera IR C Wellspring Trackpad/Keyboard Bluetooth External B ExpressCard External C NOTE: USBP[0-9]P/N have internal 15K pull-downs. INC. since not critical.0.9 1/20W PP1V5_S0_SB_VCC1_5_B MF 201 BI 6 9 39 69 USB2_EXTA_P BI 6 9 39 69 USB2_AIRPORT_N BI 6 9 36 69 USB2_AIRPORT_P BI 6 9 36 69 TP_USB2_3G_N BI 9 69 TP_USB2_3G_P BI 9 69 USB2_CAMERA_N BI 6 9 60 69 USB2_CAMERA_P BI 6 9 60 69 USB_IR_N BI 6 7 9 40 69 USB_IR_P BI 6 7 9 40 69 USB2_WSPRING_N BI 6 7 9 40 69 USB2_WSPRING_P BI 6 7 9 40 69 NC_USB_BT_N BI 9 69 NC_USB_BT_P BI 9 69 NC_USB2_EXTB_N BI 9 69 NC_USB2_EXTB_P BI 9 69 TP_USB_EXCARD_N BI 9 69 TP_USB_EXCARD_P BI 9 69 TP_USB_EXTC_N BI 9 69 TP_USB_EXTC_P BI 9 69 1 USB_RBIAS 22. ensure GNT2# is not low when PWROK rises.8 6 7 2 3 4 5 1 U2300 TP_PCIE_A_D2R_N TP_PCIE_A_D2R_P TP_PCIE_A_R2D_C_N Spares TP_PCIE_A_R2D_C_P M22 M21 L23 L24 PERN1 PERP1 PETN1 PETP1 L19 L20 K21 K22 PERN2 PERP2 PETN2 PETP2 J20 J19 J24 J23 PERN3 PERP3 PETN3 PETP3 G19 G20 H22 H21 PERN4 PERP4 PETN4 PETP4 F22 F21 G24 G23 PERN5 PERP5 PETN5 PETP5 SB_ICH8M BGA (2 OF 6) OMIT DMI0RXN DMI0RXP DMI0TXN DMI0TXP N20 N19 P22 P21 DMI_N2S_N<0> DMI1RXN DMI1RXP DMI1TXN DMI1TXP T21 T22 R24 R23 DMI_N2S_N<1> DMI2RXN DMI2RXP DMI2TXN DMI2TXP IN 6 16 67 DMI_N2S_P<0> IN 6 16 67 DMI_S2N_N<0> OUT 6 16 67 DMI_S2N_P<0> OUT 6 16 67 (x2-capable. 70 24 6 INT_PIRQC_L 70 24 6 INT_PIRQD_L 70 24 6 INT_PIRQE_L 70 24 6 INT_PIRQF_L 6 24 24 6 FireWire INT* ODD_PWR_EN_L R2431 R2433 RP2400 RP2401 RP2401 RP2402 RP2400 RP2400 RP2401 PP3V3_A_S0 4X0201 8 10K 10K 10K 10K 10K 10K 10K 10K 6 10K 4X0201 4 5 3 6 1 8 3 6 3 6 2 7 2 7 1 3 4X0201 4X0201 4X0201 4X0201 4X0201 4X0201 4X0201 1 2 10K 201 1 2 10K 201 4 5 4 5 2 7 4 5 2 7 1 8 1 8 10K 10K 10K 10K 10K 10K 10K SB PCI. THE POSSESSOR AGREES TO THE FOLLOWING 4X0201 4X0201 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 4X0201 II NOT TO REPRODUCE OR COPY IT 4X0201 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 4X0201 Changed pullups from 8.

1UF 10% 6.2K 6 RP2502 8. short CLPWROK to PWROK. VccLAN3_3 and VccLAN1_05 OUT have been up for at least 1ms. PP1V25_S0M. PP1V05_S0M. 3. PP3V3_S5 2 6 7 8 24 25 26 27 28 36 43 44 49 51 56 57 58 60 72 1 R2528 If ME/AMT is not used. 1 R2523 100K NOTE: ICH CLPWROK input must be PWRGD signal for 5% 1/20W MF 201 PP3V3_S0M. 051-7230 B.3V X5R 201 B 1 R2529 1 453 0.2K 5% 1/32W 4X0201 5% 1/32W 4X0201 2 5% 1/32W 4X0201 2 3 SMBUS_SB_ME_SDA AD21 AA17 AA16 AB16 AC16 SMBCLK SMBDATA LINKALERT* SMLINK0 SMLINK1 PM_RI_L AD15 RI* OUT PM_SUS_STAT_L IN PM_SYSRST_L D4 AC13 SUS_STAT*/LPCPD* SYS_RESET* IN PM_BMBUSY_L 69 44 29 6 BI SMBUS_SB_SCL 69 44 29 6 BI SMBUS_SB_SDA BI NC_CLINK_WLAN_RESET_L 69 44 6 BI SMBUS_SB_ME_SCL 69 44 6 BI IN 43 41 6 41 28 6 25 6 16 6 43 25 6 AD7 OUT PM_STPPCI_L OUT PM_STPCPU_L AD19 AC15 43 41 6 BI PM_CLKRUN_L AA7 IN PCIE_WAKE_L BI INT_SERIRQ PM_THRM_L AD17 W9 AB8 WAKE* SERIRQ THRM* VR_PWRGD_CK505 AB14 VRMPWRGD TP_SB_TP7 AC19 TP7 28 9 6 25 6 IN TP_SB_GPIO6 IN SMC_RUNTIME_SCI_L 41 13 7 6 IN SMC_WAKE_SCI_L SB_GPIO18 TP_SB_GPIO20 SST8051_UPDATE_L NC_SB_GPIO27 FWH_MFG_MODE 25 6 NC_SB_SATA_CLKREQ_L 6 62 6 OUT SST8051_SW_RESET_L 61 6 OUT TMDS_SW_RESET_L SB_SLOAD 16 6 IN AA8 NB_SB_SYNC_L AD16 TP_SB_TP3 SB_CRT_TVOUT_MUX_L OUT 6 63 6 30 71 6 30 71 SUSCLK B5 SUS_CLK_SB OUT 6 42 SLP_S3* SLP_S4* SLP_S5* AB17 AD20 W16 PM_SLP_S3_L OUT 6 7 36 37 41 42 51 55 PM_SLP_S5_L OUT 6 41 42 S4_STATE*/GPIO26 AC21 PM_S4_STATE_L OUT PWROK AB19 PM_SB_PWROK IN AA9 PM_DPRSLPVR OUT BATLOW* AB24 PM_BATLOW_L IN 6 25 41 PWRBTN* D5 PM_PWRBTN_L IN 6 41 W13 PM_LAN_ENABLE IN 6 41 AB21 PM_RSMRST_L IN 6 41 CK_PWRGD F7 CLK_PWRGD CLPWROK C4 PM_SB_PWROK INT PU INT PU TP_PM_SLP_S4_L 6 36 41 58 6 9 25 28 NOTE: DPRSLPVR HAS INT 20K PD ENABLED 6 16 52 66 INT PU SLP_M* AB18 AT BOOT/RESET FOR STRAPPING FUNCTION PM_LAN_ENABLE must remain deasseted until VccCL3_3. SCALE SHT NONE 8 7 6 5 4 3 2 REV. PP1V8_S3M. Clink SYNC_MASTER=M70 1 2 10K SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY R2598 R2546 43 23 6 8.0. PP3V3_S0MWOL.24K 1% 1/20W MF 2 201 B C2501 10% 6.0 OF 25 1 73 A . GPIO.8 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 44 43 36 28 27 26 25 24 8 7 6 72 60 58 57 56 51 49 6 7 PP3V3_S5 R2500 7 1K 2 5% 1/20W MF 201 D 5% 1/20W MF 201 7 RP2501 10K 2 5% 1/20W MF 201 2 RP2500 10K RP2501 10K 5% 1/32W 4X0201 2 3 1 5% 1/20W MF 201 OMIT 2 7 RP2502 8. INC.2K 2 1% 1/20W MF 201 SB_GPIO10_CL1 6 7 8 24 25 26 27 28 36 43 44 49 51 56 57 58 60 72 R2544 PM_BATLOW_L R2545 R2516 2 1 6 25 ARB_ONLY 1 A 10K 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. THE POSSESSOR AGREES TO THE FOLLOWING 1% 1/20W MF 201 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 1% 1/20W MF 201 SIZE DRAWING NUMBER D APPLE INC. PP0V9_S3M and PP0V9_S0M.3V X5R 201 6 25 MISC Test access required 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 PP3V3_A_S0 C19 W14 CONTOLLER LINK INT PD TP3 SB_GPIO36 IN RSMRST* MCH_SYNC* D SATA_B_DET_L 6 IN LAN_RST* SPKR RSVD_EXTGPU_LVDS_EN SB_CLK48M_USBCTLR SYS GPIO POWER MGT TACH0/GPIO17 GPIO18 GPIO20 INT PD SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ*/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 AD2 SB_SPKR 6 1 SB_CLK14P3M_TIMER INT PU 6 6 5% 1/32W 4X0201 4 Y7 E5 DPRSLPVR/GPIO16 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 4 W8 AC4 AD4 AB7 RP2500 10K 5% 1/32W 4X0201 CLK14 CLK48 CLKRUN*/GPIO32 Y6 AD6 AC7 Y8 AD22 Y14 AB9 AC5 AB6 AC6 NC_SB_GPIO17 6 OUT SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 GPIO C 62 6 SMB SATA GPIO STP_PCI*/GPIO15 STP_CPU*/GPIO25 AA5 Y5 AB5 W12 PCI_PME_FW_L IN BGA (4 OF 6) SMBALERT*/GPIO11 30 29 6 6 SB_ICH8M 8 RP2500 10K 5% 1/32W 4X0201 3 BMBUSY*/GPIO0 AA18 FRANKCARD_GPIO IN U2300 5 RP2501 10K 5% 1/32W 4X0201 CLOCKS 30 29 6 41 6 5 RP2501 10K 1K 5% 1/32W 4X0201 2 8 6 R2510 RP2405 10K 5% 1/32W 4X0201 5% 1/20W MF 201 6 5% 1/32W 4X0201 2 10K 100K NO_REBOOT_MODE 1 7 RP2500 10K R2553 R2550 1 10K 1 1 R2502 43 41 6 1 PP3V3_A_S0 1 36 7 6 2 3 4 5 1% 1/20W MF 2 2 201 WOL_EN for XOR chain testing. 6 29 1 1 R2524 See note below INT PU R2525 100K IN 6 9 25 28 TP_PM_SLP_M_L 5% 1/20W MF 201 10K 5% 1/20W MF 2 201 2 INT PU CL_CLK0 CL_CLK1 CL_DATA0 CL_DATA1 CL_VREF0 CL_VREF1 CLINK_NB_CLK BI NC_CLINK_WLAN_CLK BI D20 AA14 CLINK_NB_DATA BI NC_CLINK_WLAN_DATA BI CL_RST* MEM_LED/GPIO24 E18 70 AA15 6 6 16 70 INT PU WOL_EN/GPIO9 R2526 3.1UF 2 2 1% 1/20W MF 201 LAYOUT NOTE: PLACE R2511-16 WHERE PHYSICALLY ACCESSIBLE R2531 25 6 44 43 36 28 27 26 25 24 8 7 6 72 60 58 57 56 51 49 PCI_PME_FW_L 1 PP3V3_A_S0 2 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 1% 1/20W MF 201 PP3V3_S5 1 R2511 10K 2 5% 1/20W MF 201 1 1 R2514 R2515 2 5% 1/20W MF 201 R2536 10K 47K 2 5% 1/20W MF 201 FWH_MFG_MODE 25 6 PM_RI_L FRANKCARD_GPIO 6 25 43 ARB_DETECT_L 6 25 10K PP3V3_S5 2 1% 1/20W MF 201 41 25 6 23 6 0 5% 1/20W MF 201 23 6 LAN_PHYPC 1 1 10K BOOTROM_OVR_EN_L 1 100K 2 5% 1/20W MF 201 SB Pwr Mgt.24K 6 16 70 1% 1/20W MF 2 201 SB_CLINK_VREF0 SB_CLINK_VREF1 Y16 CLINK_NB_RESET_L AD23 ARB_DETECT_L AC18 C 1 OUT BI 6 16 70 C2500 6 1 R2527 1 453 0.

J6

72 27 26 24 23 6

PP1V5_S0_SB_VCC1_5_B

H17
H18
J17
J18
K17
K18
L17
L18
M17
M18
N17
N18
P17
P18
R17
R18
T18

1 mA S0-S5

U2300

VCCRTC

VCCCORE

K12
K13
K14
K15
L12
L15
M14
M15
N15
P14
P15
R10
R12
R15
T10
T11
T12
T13
T14
T15

VCCDMIPLL

P24

PP1V5_S0_SB_VCCDMIPLL
PP1V25_S0

VCC_DMI

U17
U18

V_CPU_IO

U15
U16

SB_ICH8M
BGA
(6 OF 6)

V5REF
V5REF_SUS

47 mA

72 27 6

11 8 7 6
72 54 27 26 22 12

11 8 7 6
72 54 27 26 22 12

11 8 7 6
72 54 27 26 22 12

10 mA

12 11 8 7 6
72 54 27 26 22

AC1

VCCSATAPLL

PP1V5_S0

G14
G15

RINGPCI

PP1V5_S0

PP1V5_S0

NC_VCCLAN1_05_INTERNAL_REG2

26 24 23 6 PP1V5_S0_SB_VCC1_5_B
72 27

80 mA

52 51 46 44 42
19 16 13 8 7 6 PP3V3_A_S0
1 mA
30 29 28 27 26 25 24 23 22 21
64 63 60 53

6

PLACE CLOSE TO F18
OMIT

C2600

1

A1
A24
AD1
AD24

10%
6.3V
CERM
402

USBCORE

M7
M8

RINGIDE

N7
P7
R7

ARX

N8
P8
R8

ATX

T6
U6

SATA

RINGCORE

W17

RINGCPU

G13
H13

VCCUSBPLL

VCCCL3_3

A21

VCCGLANPLL

F17
G17
G18

VCCGLAN1_5

C24

VCCGLAN3_3

NC_VCCCL1_05_INTERNAL_REG

E17

VCCCL1_05

VCCCL1_5V

F18

VCCCL1_5

G16

VCCLAN3_3

53 52 51 46
28 27 26 25
16 13 8 7 6 PP3V3_A_S0
24 23 22 21 19
19 mA
44 42 30 29
64 63 60

S0,

VCCPIDE

U7
U8
V8

PP3V3_A_S0

VCCPCORE

VCCSATABG

U2

PP3V3_A_S0

V24

PP3V3_A_S0

AA10

PP3V3_A_S0

Y10

PP3V3_S5

G8
V16

NC_VCCSUS1_05_INTERNAL_REG1

G7

NC_VCCSUS1_5_INTERNAL_REG1

V15

NC_VCCSUS1_5_INTERNAL_REG2

VCCAUBG

F6

PP3V3_S5
PP3V3_S5

VCCPUSB

J10
J8
J9
K10
K8
K9
L10
L9
M10
M9
N10
N9
V12
V13
V14

PP3V3_S5

USB

VCCPSUS

51 mA M1 & WOL

C

42 44 46 51 52 53 60 63 64
24 25 26
6 7 8 13 16
19 21 22 23
27 28 29 30

PP3V3_A_S0

RINGSUSEXT

23 mA

6 27 72

6 7 8 10 11 12 13114mA
18 19 21 23 26 27 30 42 54 72

J5
J7
K5
K6
K7
L6

VCCSUS1_05

VCCLAN1_05

PP1V05_S0

VCCPPCI

VCCSUSHDA

D

27 51
6 7 8 16 18 19 21 50
mA
57 72

PP3V3_A_S0

VCCHDA

1

13 14 18
6 7 8 10 11 12 1130
mA
19 21 23 26 27 30 42 54 72

G10
G11
G9
H10
H11
H12

VCC3GBG

V10
V9

H15
H16

PP3V3_A_S0

12 11 8 7 6 PP1V5_S0
72 54 27 26 22

23 mA

G6
H5
H6

G5

PP1V5_S0
NC_VCCLAN1_05_INTERNAL_REG1

51 46 44 42 30 29
2219
21 mA
19 16
13 8 7 6
S0,
25 24
23
28 27
63
mA26
& WOL
64
63 M1
60 53
52

VCCA3GP

PP1V5_S0_SB_VCCSATAPLL

72 54
11 8 7 6 PP1V5_S0
27 26 22 12

1080 mA

VCC1_05

OMIT
657 mA

PP1V05_S0

44 46
24 25
6 7 8
19 21
28 29
53 60

51
26
13
22
30
63

52
27
16
23
42
64

44 46
24 25
6 7 8
19 21
28 29
53 60

51
26
13
22
30
63

52
27
16
23
42
64

44 46
24 25
6 7 8
19 21
28 29
53 60
6 7 8
19 21
24 25
27 28
51 52
6 7 8
24 25

51
26
13
22
30
63
13
22
26
29
53
13
26

52
27
16
23
42
64
16
23

(VCC3_3 total)

72 27 6

PP5V_S5_SB_V5REF_SUS

1uF

VSS_NCTF

A

D15
R6

53 60
30 42 44 46
60 63 64
16 19 21 32
22
27 28 29 30

442 mA

63 64
51 52

NOTE:

23
mA
42 44 46

VccHDA and VccSusHDA can be 1.5V or 3.3V
depending on VIO of HD Audio interface.

28 36
44
6 7 8 24 25 26 27 11
mA43S0,
49 51 56 57 58 60 172mA S3-S5

Current figures provided assume 1.5V.

B

NC_VCCSUS1_05_INTERNAL_REG2

60 72
43 44
6 7 8
26 27
51 56
43 44
6 7 8
26 27
56 57
72

49
24
28
57
49
24
28
58

25
36
58
51
25
36
60

(VCCSUS3_3 total)

VSS

VSS

W15

PP5V_S0_SB_V5REF

1 mA

VCC3_3

OMIT

PP3V42_G3H

72 27 6

6 uA S0-G3 27 23 8 7 6
72 59 57 44 43 42 41 40 39 28

VCCSUS1_5

B

(5 OF 6)

L7
L8
M11
M12
M13
M16
M19
M20
M23
M24
N11
N12
N13
N14
N16
N2
N21
N22
N5
P10
P11
P12
P13
P16
P19
P20
P23
P6
P9
R11
R13
R14
R16
R21
R22
R9
T16
T17
T19
T2
T20
T23
T24
T5
T7
T8
T9
U10
U11
U12
U13
U14
U21
U22
U3
U9
V11
V17
V20
V23
V3
V6
V7
W1
W2
W5
Y12
Y15
Y18
Y21
Y24
Y3
Y4
Y9

VCCSUS3_3

C

U2300

SB_ICH8M
BGA

VCC1_5_B

AA1
AA2
AA6
AB20
AB3
AB4
AC11
AC14
AC17
AC2
AC20
AC23
AC8
AD5
B10
B13
B16
B19
B22
B24
B4
B7
D17
D3
E1
E12
E15
E21
E22
E4
E6
E9
F16
F19
F20
F23
F24
F5
G1
G12
G21
G22
G4
H14
H19
H20
H23
H24
H7
H8
H9
J1
J11
J12
J13
J14
J15
J16
J21
J22
J4
K11
K16
K19
K20
K23
K24
L1
L11
L13
L14
L16
L21
L22
L4

2

3

4

5

VCC1_5_A

D

6

7

(VCC1_5_A total)

8

117 mA S0,
44 mA S3-S5

72
43 44 49 51
6 7 8 24 25
26 27 28 36
56 57 58 60

SB Power & Ground

2

SYNC_MASTER=M70

SYNC_DATE=01/09/2007

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

DRAWING NUMBER

D
APPLE INC.

8

SCALE

SHT
NONE

Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.

7

6

5

4

3

2

REV.

051-7230

B.0.0

OF
26

1

73

A

8
PP3V3_A_S0
2

R2702
1/20W
MF
201
5%

1

3
2

L2702

D2702
72 54 27 26 22 12 11 8 7 6

1

1/20W
MF
201
5%

2

C2718

0.022UF

10%
2 6.3V
X5R
201

10%
2 6.3V
X5R
201

1

C2702

0.022UF

10%
2 6.3V
X5R
201

CRITICAL
1

C2716
330UF

20%
2 2.5V
POLY
CASE-C2-HF

C2704

PP3V3_S5

44 43 36 28 27 26 25 24 8 7 6
72 60 58 57 56 51 49

1

PLACEMENT NOTE:
PLACE CAP UNDER SB NEAR PIN G16

C2719
0.1UF
10%

PP1V5_S0

72 54 27 26 22 12 11 8 7 6

PP1V5_S0

220UF

OMIT

20%
2 2.5V
2
POLY
CASE-B2-HF

C2734
0.1UF

10%
6.3V
2 X5R
201

1

C2733

0.022UF

10%
6.3V
2 X5R
201

OMIT

C2705

1

10UF

1

C2721
0.1UF
10%

2 6.3V
X5R
1

6 23 24 26 27 72

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

C

C2710
0.1UF
10%
6.3V

2 X5R
201

ICH V_CPU_IO BYPASS
(ICH CPU I/O 1.05V PWR)

C2706
10UF

20%
6.3V
X5R
603

PP3V3_A_S0

201

PP1V5_S0_SB_VCC1_5_B

2

64 63 60 53
25 24 23 22 21 19 16 13 8 7 6
52 51 46 44 42 30 29 28 27 26

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN AA10

PLACEMENT NOTE:
PLACE CAP NEAR PINS
T6..U6, N7..R7, N8..R8 OF SB

0805-1

1

1

PLACEMENT NOTE:
PLACE CAPS NEAR PINS
J10..N9

ICH VCCHDA BYPASS
(ICH INTEL HDA CORE 3.3V/1.5V PWR)

PP1V5_S0

72 54 27 26 22 12 11 8 7 6

ICH VCCA3GP(VCC1_5_B BYPASS
L2700
FERR-330-OHM-1.5A (ICH IO,LOGIC 1.5V PWR)

C2700

10%
6.3V

ICH USB/VCCSUS3_3 BYPASS
(ICH SUSPEND USB 3.3V PWR)

PP3V3_A_S0

COMBINED VCC1_5_A, ARX AND ATX DECOUPLING PER INTEL RECOMMENDATIONS
ICH VCC1_5A/ARX/ATX BYPASS
(ICH LOGIC&IO/[ARX]/[ATX] 1.5V PWR)

CRITICAL

L2700 MAY HAVE CHANGE TO 0.5UH PART
CRITICAL
1

0.1UF

2 X5R

6 26 72

72 54 27 26 22 12 11 8 7 6

1

C2731

D

201

PLACEMENT NOTE:
PLACE C2704 < 2.54MM OF PIN J6 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY

10%
6.3V
2 X5R
201

1

201

6.3V
2 X5R

VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

PP3V3_S5

PLACEMENT NOTE:
PLACE CAP NEAR PINS
V12..V14 AND F6

PLACEHOLDER
FOR 270UF

5

PP1V5_S0

44 43 36 28 27 26 25 24 8 7 6
72 60 58 57 56 51 49

6 7 8 10 11 12 13 14 18 19 21
23 26 27 30 42 54 72

64 63 60 53
25 24 23 22 21 19 16 13 8 7 6
52 51 46 44 42 30 29 28 27 26

SOT-665

0.1UF

C

1

0.1UF

D2702

PP5V_S5_SB_V5REF_SUS
1

C2717

HN2S02JE

NC

1

2

1

ICH VCC3_3 BYPASS
(ICH IO BUFFER 3.3V PWR)
VCCPCORE DOES NOT REQUIRE DECOUPLING PER INTEL RECOMMENDATIONS

PP5V_S5

10

ICH VCCSUS3_3 BYPASS
(ICH SUSPEND 3.3V PWR)

ICH VCC_PAUX/VCCLAN3_3 BYPASS
(ICH LAN I/F BUFFER 3.3V PWR)

ICH V5REF_SUS BYPASS
(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)
6 PP3V3_S5

1

20%
6.3V
2 X5R
603

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN AC1

PLACEMENT NOTE:
PLACE C2703 < 2.54MM OF PINS D15,R6 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY

10%
2 6.3V
CERM
402

C2735
10UF

C2703

R2701

PP1V05_S0

PP1V5_S0_SB_VCCSATAPLL

6 26 72

VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

1UF

26 22 12 11 8 7 6
72 54 27

2

OMIT

OMIT

44 43 36 28 27 26 25 24 8 7
72 60 58 57 56 51 49
55
51
8
6
7
39
54
56
58
72

PP1V5_S0

1

ICH CORE/VCC1_05 BYPASS
(ICH CORE 1.05V PWR)

1

0805

PP5V_S0_SB_V5REF

D

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

10UH-100MA

SOT-665

4

1

PLACEMENT NOTE:
PLACE CAPS AT EDGE OF SB
PLACE C2718,C2702 NEAR SB K12..T15

L2702 MAY HAVE CHANGE TO 1.0UH PART

HN2S02JE

NC

100

2

3

4

5

ICH V5REF BYPASS
(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)

PP5V_S0

7
22
40
43
47
51
52
53
63
72

6

7

64 63 60 53 52 51
44 42 30 29 28 27 26 25 24
22 21 19 16 13 8 7 6
23
8
46
6

21 19 18 14 13 12 11 10 8 7 6
72 54 42 30 27 26 23

20%
6.3V
2 X5R
603

PP1V05_S0
ICH USB CORE/VCC1_5_A BYPASS
(ICH USB CORE 1.5V PWR)

PLACEMENT NOTE:
PLACE NEAR PINS U15,U16 OF SB

PLACEMENT NOTE:
PLACE C2700 & C2705-07 < 2.54MM OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
DISTRIBUTED BETWEEN H17..T18,
ALSO SHARE WITH F17,G17,G18

1

C2723
0.1UF

10%
6.3V
2 X5R
201

1

72 54 27 26 22 12 11 8 7 6

C2722
0.1UF

1

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PINS G6..H6

C2724
4.7UF

20%
2 6.3V
CERM
603

10%
6.3V
2 X5R
201

PP1V5_S0

1

C2712
0.1UF
10%
6.3V

2 X5R
201

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
72
54 27 26 22 12 11 8 7 6

PP1V5_S0
1

C2732

ICH IDE/VCC3_3 BYPASS
(ICH IDE I/O 3.3V PWR)

2.2uF

PLACEMENT NOTE:
PLACE CAPS < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN A21

20%
6.3V
2 CERM1
603

ICH VCCUSBPLL BYPASS
(ICH USB PLL 1.5V PWR)
72 54 27 26 22 12 11 8 7 6

B

PP1V5_S0

PLACEMENT NOTE:
PLACE C2715 NEAR PIN G5 OF SB
64 63 60 53
25 24 23 22 21 19 16 13 8 7 6
52 51 46 44 42 30 29 28 27 26

PP3V3_A_S0

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN U2

27 26 22 12 11 8 7 6
72 54

1

64 63 60 53
25 24 23 22 21 19 16 13 8 7 6
52 51 46 44 42 30 29 28 27 26

1

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PINS J5..L6

C2715
0.1UF

72 6

1

5%
1/20W
MF
201

10%
2 6.3V
X5R
201

64 63 60 53
25 24 23 22 21 19 16 13 8 7 6
52 51 46 44 42 30 29 28 27 26

L2703

ICH VCCDMIPLL BYPASS
(ICH DMI PLL 1.5V PWR)
PP1V5_S0_SB_VCCDMIPLL 6

1.0UH-0.5A-0.675A
1
2
2
PP1V5_S0_SB_VCCDMIPLL_F
1007
1

PLACEMENT NOTE:
PLACE CAPS < 2.54MM OF SB ON
SECONDARY SIDE OR 3.56MM ON PRIMARY NEAR PIN P24

B

0.1UF
10%
6.3V

2 X5R

ICH PCI/VCC3_3 BYPASS
(ICH PCI I/O 3.3V PWR)

0.1UF

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.20MM

C2725
201

C2701
0.01UF

10%
2 10V
X5R
201

OMIT

1

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

ICH VCC3_3/VCCHDA BYPASS
(ICH INTEL HDA CORE 3.3V PWR)

PP3V3_A_S0

PLACEMENT NOTE:
DISTRIBUTE IN PCI SECTION OF SB
NEAR PINS G9..H12

PP1V5_S0

1

1

10%
6.3V
2 X5R
201

C2738

R2700

VCCCL3_3 DOES NOT REQUIRE DECOUPLING PER INTEL RECOMMENDATIONS

PP3V3_A_S0

44 43 36 28 27 26 25 24 8 7 6
72 60 58 57 56 51 49

1

C2726
0.1UF

10%
6.3V
2 X5R
201

1

C2727
0.1UF

10%
6.3V
2 X5R
201

1

C2728
0.1UF

10%
6.3V
2 X5R
201

PP3V3_S5

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN Y10

1

C2741
0.1UF
10%
6.3V

2 X5R
201

26 72

C2708
10UF

20%
2 6.3V
X5R
603

A

43 42 41 40 39 28 26 23 8 7 6
72 59 57 44

ICH VCCRTC BYPASS
(ICH RTC 3.3V PWR)
PP3V42_G3H
72

SB Decoupling
27 26 24 23 6

PP1V5_S0_SB_VCC1_5_B
MAKE_BASE=TRUE

PP1V5_S0_SB_VCC1_5_B

SYNC_MASTER=M70

6 23 24 26 27 72

SYNC_DATE=02/01/2007

NOTICE OF PROPRIETARY PROPERTY
PP3V3_A_S0

64 63 60 53
25 24 23 22 21 19 16 13 8 7 6
52 51 46 44 42 30 29 28 27 26

72 57 51 26 21 19 18 16 8 7 6

PP1V25_S0

C2744
1UF

PLACEMENT NOTE:
PLACE CAP < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN V24

1

C2737
0.1UF
10%
6.3V

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN U17,U18

2 X5R

1

10%
10V 2
X5R
402-1

C2739

C2729
0.1UF

1

10%
6.3V 2
X5R
201

1

C2730

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

0.1UF
10%

2 6.3V
X5R

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

201

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1UF
10%
10V

2 X5R

402-1

201

1

SIZE

PLACEMENT NOTE:
PLACE CAPS NEAR PIN W15 OF SB

DRAWING NUMBER

D
APPLE INC.

SCALE

SHT
NONE

8

7

6

5

4

3

2

REV.

051-7230

B.0.0

OF
27

1

73

A

8

6

7

PP3V42_G3H
42 41 40 39 28 27 26 23 8 7 6
72 59 57 44 43

2

3

4

5

6 7 8 23 26 27 28 39 40 41 42
43 44 57 59 72

1

Platform Reset Connections

PP3V42_G3H

Unbuffered
64 60 28 24 7 6

IN

D

R2886

PLT_RST_L

100

1

MAKE_BASE=TRUE

5%
1/20W
MF
201

R2800
1

20K

5%
1/20W
MF
201

6 23

OUT

1

R2806
1M

5%
1/20W
MF
2 201

C2805

R2885

1UF

10%
2 6.3V
CERM
402

1

0

D

0

2

TMDS_HW_RESET_L

6 61 62

5%
1/20W
MF
201

OMIT

1

6 16

R2887
1

SB_RTC_RST_L

2

NB_RESET_L

2

AIRPORT_RST_L 6

2

7 36

5%
1/20W
MF
201

SB_SM_INTRUDER_L

PLT_RST_L

6 7 24 28 60 64

PLT_RST_L

6 7 24 28 60 64

6 23

OUT

64 63 60 53
25 24 23 22 21 19 16 13 8 7 6
52 51 46 44 42 30 29 28 27 26

PP3V3_A_S0

Buffered
CRITICAL

2
1

C2880 1

5 TC7SZ08AFEF

SOT665

A

U2880Y
B

3

6.3V 2
X5R
201

10M

2

6

SB_RTC_X1_R

5%
1/20W
MF
201

CRITICAL

Y2800 1

5%
1/20W
MF1
201 2
23 6

32.768K

3.2X1.5X.6-SM

197S0187

SB_RTC_X2

2

1

5%
25V
NPO
201

49 44 43 36 27 26 25 24 8 7 6
72 60 58 57 56 51

10PF
1

2
IN

1

100

2

DEBUG_RESET_L
6 43
Linda Card represents 3 loads
SMC_LRESET_L

6 41

5%
1/20W
MF
201

PP3V3_S5
10K

R2896
XDP_DBRESET_L

2

1K

1

PM_SYSRST_L

5%
1/20W
MF
201
I59 2

PM_SYSRST_L

OMIT

5%
1/20W
MF
201

MAKE_BASE=TRUE

OUT

6 25 28 41

1

R2898

Silk: "SYS RST"
Place R2898 pads on bottom side
near board edge

B

PP3V3_A_S0
0.1UF

64 63 60 53
25 24 23 22 21 19 16 13 8 7 6
52 51 46 44 42 30 29 28 27 26

10%
6.3V 2
X5R
201

VR_PWRGD_CK505

4

Y

U2803

A

2

SON

B

1

R2811

1

0.1UF
10%

1.8K

6.3V 2
X5R
201

5%
1/20W
MF
2 201

TC7SH00FEF
GND

R28031

VR_PWRGD_CK505_L

MAKE_BASE=TRUE

IN

TC7SZ08AFEF 5
SOT665

6 28 52

25 9 6

3

100K

5%
1/20W
MF
201 2

52 28 6

PP3V3_A_S0

C2807 1

5 CRITICAL
VCC
OUT

R2883

R28971

C2809

C2811 1

25 9 6

2

C

100K
This part is never stuffed,1/16W
5%
it provides a set of pads MF-LF
402 2
on the board to short or
to solder a reset button.

64 63 60 53 52
25 24 23 22 21 19 16 13 8 7 6
51 46 44 42 30 29 28 27 26

0

5%
1/20W
MF
201

2

5%
25V
NPO
201

B

100K

1

10PF

10 13

R28091

0

1

7

SB_RTC_X1

R2880

1

R2881

C2808

R2810
23 6

6

C

PLT_RST_BUF_L

6

5%
1/20W
MF
2 201

0.1UF
10%

SB RTC Crystal Circuit

4

OUT

PM_SB_PWROK
R2812

4

Y

CRITICAL
A

B

1

2

U2801 1

VR_PWRGOOD_DELAYIN
ALL_SYS_PWRGD

IN

6 9 16 52

6 41 51 52

3

10K

5%
1/20W
MF
201 2
OUT

VR_PWRGD_CK505_L

SB Misc
SYNC_MASTER=M70

A

SYNC_DATE=01/09/2007

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

DRAWING NUMBER

D
APPLE INC.

SCALE

SHT
NONE

8

7

6

5

4

3

2

REV.

051-7230

B.0.0

OF
28

1

73

A

GPU PCI-E 100 MHZ ) (ICH8M DMI 100 MHZ ) (PULL UP PIN 68 TO ENABLE ITP HOST CLK) (ICH SM BUS) 69 44 25 6 IN BI SMBUS_SB_SCL SMBUS_SB_SDA 47 48 SCL SDA SRC_3* SRC_3 CLKREQ_3* (INT PU) SRC_4* B 5 SRC_4 CLKREQ_4* VSS_48 (INT PU) 46 VSS_CPU 62 66 VSS_PCI SRC_5* SRC_5 52 VSS_REF 31 VSS_SRC CLKREQ_5* (INT PU) SRC_6* SRC_6 CLKREQ_6* (INT PU) SRC_7* SRC_7 69 THRM_PAD CLKREQ_7* (INT PU) SRC_8* SRC_8 CLKREQ_8* (INT PU) FCTSEL1 0 1 PIN 6 CLK_PWRGD 4 54 53 CK505_USB48_FSA CK505_CLK14P3M_TIMER NC_GPU_STOP_L DOT96C 27M NON SPREAD 27M SPREAD 100MT_SST SRCT0 9 OUT 9 IN 9 OUT OUT IN 6 16 30 71 6 16 30 71 6 16 6 30 36 71 6 30 36 71 (ICH SATA 100 MHZ) B (FROM ICH8M GPIO35) (GMCH G_CLKIN 100 MHZ ) (FROM GMCH CLK_REQ*) (WIRELESS PCI-E 100 MHZ ) 6 7 36 OUT 9 OUT 9 NC_CK505_SRC8_N OUT NC_CK505_SRC8_P OUT NC_CK505_SRC_CLKREQ8_L IN 2 DOT96T OUT (SLOT D .1UF) (PLACED 0.1UF 10% 2 6. 051-7230 B.3V X5R 201 10% 2 6.1UF 10% 2 6.2mm OMIT VOLTAGE=3.0 OF 29 1 73 A .1UF 10% 2 6.C2907.0.3V 2 X5R 201 1 1 C2906 C2912 1 0.1UF NEAR THE RELATIVE POWER PIN) VDD_SRC C2989 VDD_REF 1 4 VDD_PCI 3 2 C VDD_48 1 VDD_CPU 3 Y2901 SM-2.4 LANE PCI-E FOR EXPRESSCARD) (DB400 SRC ) 9 CKPWRGD/PD* PIN 10 9 IN NB_CLK96M_DOT_N NB_CLK96M_DOT_P PIN 7 9 IN OUT 7 6 48M/FS_A REF_0/FS_C/TEST_SEL GPU_STOP* 9 OUT OUT DOT_96*/27M_SS DOT_96/27M (INT PD) A 32 33 34 OUT OUT OUT 9 6 9 16 30 71 6 9 16 30 71 IN 6 25 OUT 6 30 OUT 6 30 BI (SLOT E ) 9 9 9 (GMCH D_REFCLKIN DISPLAY PLL A 96MHZ) (FROM ICH8M) (ICH8M USB 48MHZ) (ICH8M.3V 2 CERM 402 C2902 0.LPC REF. SCALE SHT NONE 8 7 6 5 4 3 2 REV.3V X5R 201 D D CRITICAL L2901 53 52 51 46 44 42 30 29 19 16 13 8 7 6 28 27 26 25 24 23 22 21 64 63 60 FERR-120-OHM-1.3V X5R 201 C2915 0.5A 1 2 PP3V3_S0_CK505_VDD_CPU_SRC PP3V3_A_S0 0402-LF OMIT C2900 MIN_LINE_WIDTH=0.1UF C2913 0.SIO.1UF 0.3V 2 X5R 201 1 1 C2905 0.3V 2 X5R 201 1 C2904 0.3V 1 C2901 1 1UF 1 10UF 10% 6. 14.8 6 7 PP3V3_A_S0 Silego recommend to remove L2903.1UF 10% 6.C2914 and R2902 1 2 3 4 5 1 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 C2909 0.1UF 10% 6.C2911.5X2.C2916. INC.3V X5R 201 1 C2903 0.0MM 14.1UF 10% 6.C2910 R2901.318MHZ) Clock (CK505) SYNC_MASTER=M70 PIN 11 100MC_SST SRCC0 SYNC_DATE=02/01/2007 NOTICE OF PROPRIETARY PROPERTY * FOR INT.318MHZ-35PPF-20PF 43 CRITICAL PCI 33MHZ) (TPM LPC 33MHZ) (SMC LPC 33MHZ) 71 30 (PCI SLOT) (PORT80 LPC 33MHZ) IN BI OUT CK505_PCIF1_CLK OUT 9 OUT 6 OUT 9 CK505_FSB_TEST_MODE NC_CK505_PCI1_CLK NC_CK505_PCI2_CLK CK505_PCI3_CLK NC_CK505_PCI4_CLK CK505_PCI5_FCTSEL1 9 OUT CK505_PCIF0_CLK (ICH8M PCI 33MHZ) 30 6 71 PCI_STOP* CPU_STOP* SLG2AP101 QFN VDD_A VSS_A 56 55 PM_STPPCI_L PM_STPCPU_L IN 6 25 30 IN 6 25 30 FSB_CLK_CPU_N FSB_CLK_CPU_P OUT 6 10 30 71 CPU_0 44 45 OUT 6 10 30 71 CPU_1_MCH* CPU_1_MCH 41 42 FSB_CLK_NB_N FSB_CLK_NB_P OUT 6 14 30 71 OUT 6 14 30 71 CPU_ITP*/SRC_10* FS_B/TEST_MODE CPU_ITP/SRC_10 36 37 OUT 6 7 13 30 66 71 OUT 6 7 13 30 66 71 57 PCI_1 SRC_0*/LCD_CLK* 58 PCI_2 SRC_0/LCD_CLK 63 PCI_3 SRC_1* 64 PCI_4 SRC_1 65 PCI_5/FCT_SEL (NO INT PD) CLKREQ_1* (INT PU) 68 PCIF_0/ITP_EN (NO INT PU) SRC_2* 1 11 10 NB_CLK100M_DPLLSS_N NB_CLK100M_DPLLSS_P OUT 6 9 16 30 71 OUT 6 9 16 30 71 14 13 9 NC_CK505_SRC1_N NC_CK505_SRC1_P NC_CK505_SRC_CLKREQ1_L OUT 9 16 15 SB_CLK100M_DMI_N SB_CLK100M_DMI_P 19 18 59 NC_CK505_SRC3_N NC_CK505_SRC3_P NC_CK505_SRC_CLKREQ3_L 22 21 20 NC_CK505_SRC4_N NC_CK505_SRC4_P NC_CK505_SRC_CLKREQ4_L 24 23 60 NB_CLK100M_PCIE_N NB_CLK100M_PCIE_P NB_CLKREQ_L 27 26 25 PCIE_CLK100M_MINI_N PCIE_CLK100M_MINI_P CK505_SRC_CLKREQ6_L 30 29 40 NC_CK505_SRC7_N NC_CK505_SRC7_P NC_CK505_PGMODE 51 50 8 XTAL_IN XTAL_OUT CPU_0* PCIF_1 SRC_2 XDP_CLK_N XDP_CLK_P OUT 9 IN 9 OUT 6 24 30 71 OUT 6 24 30 71 C (FROM ICH8M GPIO15 STPPCI* ) (FROM ICH8M GPIO25 STPCPU* ) (CPU HOST 133/167MHZ) (GMCH HOST 133/167MHZ) (ITP HOST 133/167MHZ) (GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ) (SLOT F .1UF 20% 6.3V X5R 201 10% 6.3V 2 X5R 603 10% 2 6.5mm MIN_NECK_WIDTH=0.3V 2 X5R 201 C2908 1 0. GRAPHIC SYSTEM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.3V X5R 201 20PF 5% 25V 2 NP0-C0G 201 1 C2990 30 6 R2903(FW 5% 1/20W MF 2 201 30 6 OUT 12 17 28 35 U2900 201 CK505_XTAL_IN CK505_XTAL_OUT PP3V3_A_S0 10K 49 5% 6 1 61 67 20PF 2 25V NP0-C0G 38 39 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 (EACH POWER PIN PLACED ONE 0.1UF 10% 2 6.L2902.R2900. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. GRAPHIC SYSTEM * FOR EXT.

318MHZ) IN CK505_PCIF1_CLK R3030 R3090 0 5% 1/20W MF 201 R30911 1K BI CK505_PCI5_FCTSEL1 B 2 71 29 6 CPU_BSEL<2> IN R3066 IN CK505_PCI3_CLK 1 33 PCI_CLK33M_LPCPLUS 2 2 5% 1/20W MF 201 71 30 6 71 29 6 33 5% 1/20W MF 201 1K R3089 29 6 6 9 16 29 30 71 R3038 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 R3088 (TO MCH FS_C) OUT MAKE_BASE=TRUE 1 PP1V05_S0 1 IN 2 MAKE_BASE=TRUE OUT 6 43 71 (PORT80 LPC 33MHZ) OUT 6 24 71 (TO ICH8M PCI 33MHZ) OUT 6 41 71 (TO SMC PCI 33MHZ) 10K 5% 1/20W MF 2 201 R3039 1 33 PCI_CLK33M_SB 2 MAKE_BASE=TRUE 5% 1/20W MF 201 PCI_CLK33M_SMC 5% 1/20W MF 201 6 10 66 (FROM CPU FS_C) 5% 1/20W MF 201 2 A * FS_C FS_B FS_A 0 0 0 0 0 1 0 1 1 CPU 266M 133M 166M 0 1 0 200M 1 1 0 400M 1 1 1 1 0 0 1 1 0 Clock Termination NOSTUFF R3082.8 6 7 IN CK505_USB48_FSA 1 33 SB_CLK48M_USBCTLR 2 1 CLK Termination R3032 29 6 2 3 4 5 OUT 6 25 71 5% 1/20W MF 201 R3033 2. 051-7230 B. THE POSSESSOR AGREES TO THE FOLLOWING CPU speed is currently set to 200MHz I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART Resrvd 100M 333M SIZE DRAWING NUMBER D APPLE INC. SCALE SHT NONE 8 7 6 5 4 3 2 REV.0 OF 30 1 73 A . R3086.0. INC.2K 1 71 30 29 10 6 CK505_FSA 2 D 29 6 IN CK505_CLK14P3M_TIMER 1 71 30 29 10 6 71 30 29 14 6 SB_CLK14P3M_TIMER 2 OUT R3035 71 66 30 29 13 7 6 CK505_FSC 2 OUT MAKE_BASE=TRUE IN FSB_CLK_CPU_N IN FSB_CLK_NB_P IN FSB_CLK_NB_N IN XDP_CLK_P FSB_CLK_CPU_N MAKE_BASE=TRUE FSB_CLK_NB_P MAKE_BASE=TRUE FSB_CLK_NB_N MAKE_BASE=TRUE XDP_CLK_P MAKE_BASE=TRUE 6 30 71 71 66 30 29 13 7 6 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 30 29 16 9 6 71 IN XDP_CLK_N XDP_CLK_N IN NB_CLK100M_DPLLSS_P MAKE_BASE=TRUE NB_CLK100M_DPLLSS_P MAKE_BASE=TRUE R3080 1K 66 16 13 7 6 OUT NB_BSEL<0> 1K 1 0 1 (TO ICH8M USB 48MHZ) 2 5% 1/20W MF 201 R30831 1K C 6 14 29 30 71 D OUT 6 14 29 30 71 OUT 6 7 13 29 30 66 71 CLKREQ Controls OUT 6 7 13 29 30 66 71 OUT 6 9 16 29 30 71 IN NB_CLK100M_DPLLSS_N NB_CLK100M_DPLLSS_N OUT MAKE_BASE=TRUE 64 63 60 25 24 23 22 21 19 16 13 8 7 6 53 52 51 46 44 42 29 28 27 26 29 25 6 71 30 29 24 6 IN SB_CLK100M_DMI_P SB_CLK100M_DMI_P 71 30 29 24 6 IN SB_CLK100M_DMI_N SB_CLK100M_DMI_N OUT MAKE_BASE=TRUE PP3V3_A_S0 10K PM_STPPCI_L R3046 1 2 1/20W 5% 201 MF 6 9 16 29 30 71 10K PM_STPCPU_L 1/20W 6 24 29 30 71 R3047 1 2 MF 5% 201 (ICH8M DMI 100MHZ) R3082 CK505_FSA OUT 29 25 6 2 5% 1/20W MF 201 71 30 6 30 29 16 9 6 71 5% 1/20W MF 2 201 R3081 6 10 29 30 71 (Int Gfx LVDS 100MHz) 1 (TO MCH FS_A) OUT (ITP HOST 133/167MHZ) 5% 1/20W MF 201 PP1V05_S0 NOSTUFF 6 10 29 30 71 (GMCH HOST 133/167MHZ) 71 30 29 14 6 10K FSB_CLK_CPU_P 6 25 71 5% 1/20W MF 201 1 FSB_CLK_CPU_P (CPU HOST 133/167MHZ) R3034 33 IN 6 30 71 5% 1/20W MF 201 CPU_BSEL<0> IN OUT MAKE_BASE=TRUE 6 24 29 30 71 6 10 66 (FROM CPU FS_A) C 5% 1/20W MF 201 2 71 30 29 16 6 IN NB_CLK100M_PCIE_P NB_CLK100M_PCIE_P OUT MAKE_BASE=TRUE 6 16 29 30 71 (GMCH PEG/DMI 100MHZ) PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 72 71 30 29 16 6 IN NB_CLK100M_PCIE_N IN PCIE_CLK100M_MINI_P NB_CLK100M_PCIE_N MAKE_BASE=TRUE OUT 6 16 29 30 71 OUT 6 29 30 36 71 1 R3084 1K (TO MCH FS_B) 66 16 13 7 6 OUT R3085 NB_BSEL<1> 1K 1 OUT PCIE_CLK100M_MINI_P MAKE_BASE=TRUE (WIRELESS PCI-E MINI 100MHZ) 71 36 30 29 6 IN PCIE_CLK100M_MINI_N IN NB_CLK96M_DOT_P PCIE_CLK100M_MINI_N MAKE_BASE=TRUE 2 5% 1/20W MF 201 29 6 71 36 30 29 6 5% 1/20W MF 2 201 OUT 6 29 30 36 71 OUT 6 9 16 29 30 71 R3086 CK505_FSB_TEST_MODE 0 1 NOSTUFF 2 5% 1/20W MF 201 1 R3087 1K CPU_BSEL<1> IN 6 10 66 (FROM CPU FS_B) 5% 1/20W MF 201 2 71 30 29 16 9 6 NB_CLK96M_DOT_P MAKE_BASE=TRUE (Int GFX DOT 96MHZ) B 71 30 29 16 9 6 NB_CLK96M_DOT_N NB_CLK96M_DOT_N NOSTUFF 29 6 IN CK505_PCIF0_CLK 1 66 16 13 7 6 OUT 5% 1/20W MF 2 201 NB_BSEL<2> 1K 1 CK505_FSC 1 (ICH8M 14. R3090 FOR MANUAL CPU FREQUENCY SYNC_MASTER=M70 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.

3V X5R 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 72 68 55 VDD 31 68 31 68 31 68 201 1 VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 MEM_A_DQ<47> LDQS LDQS* UDQS UDQS* F7 E8 B7 A8 MEM_A_DQS_P<4> 17 31 68 MEM_A_CAS_L MEM_A_DQS_N<4> 17 31 68 MEM_A_WE_L MEM_A_DQS_P<5> 17 31 68 MEM_A_DQS_N<5> 17 31 68 MEM_A_DM<7> 68 31 17 MEM_A_DM<6> 17 31 68 MEM_A_A<3> MEM_A_DQ<46> 17 31 68 MEM_A_A<2> MEM_A_DQ<45> 17 31 68 MEM_A_A<1> MEM_A_DQ<44> 17 31 68 MEM_A_A<0> MEM_A_DQ<43> 17 31 68 VDDQ MEM_A_BS<1> MEM_A_DQS_P<3> 17 31 MEM_A_DQS_N<3> 17 31 68 68 MEM_A_BS<0> MEM_CLK_P<1> J8 CK 68 33 31 16 MEM_CLK_P<1> J8 CK MEM_CLK_N<1> K8 CK* 68 33 31 16 MEM_CLK_N<1> K8 CK* 68 33 31 16 MEM_CLK_N<1> K8 CK* 68 33 31 16 MEM_CKE<1> MEM_CKE<1> MEM_CS_L<1> K2 CKE L8 CS* 68 33 31 16 68 33 31 16 68 33 31 16 MEM_CS_L<1> K2 CKE L8 CS* MEM_ODT<1> K9 ODT MEM_ODT<1> K9 ODT 68 33 31 17 MEM_A_RAS_L 68 33 31 17 MEM_A_RAS_L 68 33 31 17 MEM_A_CAS_L 68 33 31 17 MEM_A_CAS_L 68 33 31 17 MEM_A_WE_L K7 RAS* L7 CAS* K3 WE* 68 33 31 17 MEM_A_WE_L K7 RAS* L7 CAS* K3 WE* MEM_CKE<1> MEM_CS_L<1> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DM<1> MEM_A_DM<0> K2 CKE L8 CS* NC E2 NC NC A2 NC K9 ODT K7 RAS* L7 CAS* K3 WE* B3 UDM F3 LDM VSS VSSDL 68 33 31 16 6 68 31 17 MEM_A_DM<3> 68 31 17 MEM_A_DM<2> NC E2 NC NC A2 NC B3 UDM F3 LDM VSSQ VSS VSSDL VSSQ 68 33 31 16 6 68 31 17 MEM_A_DM<5> 68 31 17 MEM_A_DM<4> U3170 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per L1 NC/BA2 L3 BA1 L2 BA0 17 31 68 MEM_A_BS<2> MEM_A_DQ<41> 17 31 68 MEM_A_BS<1> MEM_A_DQ<40> 17 31 68 MEM_A_BS<0> MEM_A_DQ<39> 17 31 68 MEM_A_DQ<38> 17 31 68 MEM_CLK_P<1> J8 CK MEM_A_DQ<37> 17 31 68 MEM_CLK_N<1> K8 CK* MEM_A_DQ<36> 17 31 68 MEM_CKE<1> MEM_A_DQ<35> 17 31 68 MEM_CS_L<1> K2 CKE L8 CS* MEM_A_DQ<34> 17 31 68 MEM_A_DQ<33> 17 31 68 MEM_ODT<1> K9 ODT MEM_A_RAS_L K7 RAS* L7 CAS* K3 WE* MEM_A_DQ<32> VSSDL MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49> MEM_A_DQ<48> MEM_A_DQS_N<6> 17 31 68 68 17 31 17 31 68 17 31 68 17 31 68 31 68 MEM_A_DQS_N<7> 68 17 2 1 6.0.8 6 7 2 3 4 5 1 C3130 2 0.3V X5R 33 31 16 68 33 31 16 68 33 31 16 68 MEM_A_A<6> MEM_A_A<5> MEM_A_A<4> MEM_A_A<3> MEM_A_A<2> MEM_A_A<1> MEM_A_A<0> 33 31 17 68 33 31 17 68 33 31 17 68 FBGA MT47H64M16 (2 OF 2) Bit swizzle per L1 NC/BA2 L3 BA1 L2 BA0 MEM_A_BS<2> MEM_A_BS<1> MEM_A_BS<0> F7 E8 B7 A8 MEM_A_DQ<7> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<1> 68 31 17 MEM_A_DM<1> 68 31 17 MEM_A_DM<0> 31 17 68 33 31 17 68 33 MEM_A_DQ<0> MEM_A_A<10> MEM_A_A<9> MEM_A_A<8> MEM_A_A<7> MEM_A_A<6> MEM_A_A<5> MEM_A_A<4> MEM_A_A<3> MEM_A_A<2> MEM_A_A<1> MEM_A_A<0> MEM_A_BS<2> MEM_A_BS<1> R8 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 OMIT U3110 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per L1 NC/BA2 L3 BA1 L2 BA0 LDQS LDQS* UDQS UDQS* MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_A<13> MEM_A_DQ<28> MEM_A_A<12> MEM_A_DQ<27> MEM_A_A<11> MEM_A_DQ<26> MEM_A_A<10> MEM_A_DQ<25> MEM_A_A<9> MEM_A_DQ<24> MEM_A_A<8> MEM_A_DQ<23> MEM_A_A<7> MEM_A_DQ<22> MEM_A_A<6> MEM_A_DQ<21> MEM_A_A<5> MEM_A_DQ<20> MEM_A_A<4> MEM_A_DQ<19> MEM_A_A<3> MEM_A_DQ<18> MEM_A_A<2> MEM_A_DQ<17> MEM_A_A<1> MEM_A_DQ<16> MEM_A_A<0> MEM_A_DQS_P<2> MEM_A_BS<2> MEM_A_DQS_N<2> MEM_A_BS<1> MEM_CS_L<0> K9 ODT MEM_A_RAS_L K7 RAS* L7 CAS* K3 WE* MEM_A_CAS_L 68 33 31 17 MEM_A_WE_L 68 31 17 MEM_A_DM<3> 68 31 17 MEM_A_DM<2> NC E2 NC NC A2 NC VSSDL OMIT U3120 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per L1 NC/BA2 L3 BA1 L2 BA0 LDQS LDQS* UDQS UDQS* 68 33 31 16 MEM_CS_L<0> L8 CS* MEM_ODT<0> K9 ODT MEM_A_RAS_L K7 RAS* L7 CAS* K3 WE* 68 33 31 16 6 68 33 31 17 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 MEM_A_DQ<47> MEM_A_DQ<46> MEM_A_DQ<45> MEM_A_DQ<44> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<41> MEM_A_DQ<40> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<32> F7 E8 B7 A8 68 33 31 17 MEM_A_CAS_L 68 33 31 17 MEM_A_WE_L 68 31 17 MEM_A_DM<5> 68 31 17 MEM_A_DM<4> 68 33 31 17 31 68 68 33 31 17 31 68 68 33 31 17 31 68 68 33 31 17 31 68 68 33 31 17 31 68 68 33 31 17 31 68 68 33 31 17 31 68 68 33 31 17 31 68 68 33 31 17 31 68 68 33 31 17 31 68 68 33 31 17 31 68 68 33 31 17 31 68 68 33 31 17 31 68 17 17 MEM_A_A<11> 17 MEM_A_A<10> 17 MEM_A_A<9> 17 MEM_A_A<8> 17 MEM_A_A<7> 17 MEM_A_A<6> 17 MEM_A_A<5> 17 MEM_A_A<4> 17 MEM_A_A<3> 17 MEM_A_A<2> 17 MEM_A_A<1> 17 MEM_A_A<0> 17 31 68 68 33 31 17 17 31 68 68 33 31 17 17 31 68 68 33 31 17 31 68 68 33 31 31 68 68 33 31 17 31 68 68 33 31 17 31 68 68 33 31 MEM_A_DQS_N<5> MEM_A_BS<1> MEM_A_BS<0> MEM_CLK_N<0> K8 CK* 16 MEM_CKE<0> 16 MEM_CS_L<0> K2 CKE L8 CS* MEM_ODT<0> K9 ODT 68 33 31 17 MEM_A_RAS_L 68 33 31 17 MEM_A_CAS_L 68 33 31 17 MEM_A_WE_L K7 RAS* L7 CAS* K3 WE* MEM_A_DM<7> 68 31 17 MEM_A_DM<6> 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per VSSDL VSSDL 72 55 32 31 8 6 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 72 68 55 A1 E1 J9 M9 R1 VDDL VDDQ B 31 68 31 68 31 68 17 33 17 33 17 33 31 68 31 68 31 68 31 68 31 68 17 33 17 33 17 33 17 33 17 33 31 68 31 68 31 68 17 33 17 33 17 33 NC R3 MEM_A_A<13> R8 MEM_A_A<12> R2 MEM_A_A<11> P7 MEM_A_A<10> M2 P3 MEM_A_A<9> P8 MEM_A_A<8> P2 MEM_A_A<7> N7 MEM_A_A<6> N3 MEM_A_A<5> N8 MEM_A_A<4> N2 MEM_A_A<3> M7 MEM_A_A<2> M3 MEM_A_A<1> M8 MEM_A_A<0> RFU NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OMIT U3140 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per VDD B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 LDQS LDQS* UDQS UDQS* F7 E8 B7 A8 MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12> MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<9> MEM_A_DQ<8> MEM_A_DQ<7> 17 31 68 17 31 68 17 31 68 17 31 68 17 31 68 17 31 68 17 31 68 17 31 68 17 68 17 68 17 68 17 68 17 68 MEM_A_DQ<6> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<0> NC MEM_A_A<13> MEM_A_A<12> MEM_A_A<11> MEM_A_A<10> MEM_A_A<9> MEM_A_A<8> 31 MEM_A_A<7> 31 MEM_A_A<6> 31 MEM_A_A<5> 31 MEM_A_A<4> 31 MEM_A_A<3> 17 31 68 17 31 68 MEM_A_DQ<1> NC 17 31 68 MEM_A_A<2> MEM_A_A<1> MEM_A_A<0> R7 R3 R8 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 C3160 201 2 1 10% 6. 051-7230 SCALE SHT NONE 5 MEM_A_DQ<54> 10% SYNC_MASTER=(MASTER) APPLE INC. 6 MEM_A_DQ<55> 68 17 31 VSSQ D 7 MEM_A_DQ<56> B3 UDM F3 LDM SIZE 8 MEM_A_DQ<57> 17 31 68 17 31 68 NC E2 NC NC A2 NC VSSDL 68 17 31 MEM_A_DQ<58> NC E2 NC NC A2 NC VSS VSS 17 31 68 31 PP0V9_S3 OMIT A3 E3 J3 N1 P9 MEM_A_DQS_N<2> L1 NC/BA2 L3 BA1 L2 BA0 NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 MEM_A_BS<0> 68 17 31 68 MEM_A_BS<2> J7 31 68 68 31 A3 E3 J3 N1 P9 31 17 68 31 17 68 31 MEM_A_DQS_N<1> 17 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 31 17 68 33 MEM_A_BS<1> MEM_A_DQS_P<1> 17 L1 NC/BA2 L3 BA1 L2 BA0 J7 A 68 17 31 68 MEM_A_BS<2> 68 33 31 16 68 16 6 MEM_ODT<1> 33 31 31 17 68 33 31 17 68 33 MEM_A_DQS_N<0> 31 A3 E3 J3 N1 P9 31 16 68 33 MEM_A_DQS_P<0> 17 MEM_CLK_P<1> J8 CK A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 16 33 16 33 16 33 MEM_A_BS<0> J7 31 68 31 68 31 68 MEM_A_BS<1> L1 NC/BA2 L3 BA1 L2 BA0 A3 E3 J3 N1 P9 31 17 68 33 MEM_A_BS<2> R8 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 MEM_A_DQ<42> 68 33 31 17 31 17 68 33 31 17 68 33 MEM_A_DQ<59> 68 17 31 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 72 32 31 21 18 16 8 7 6 PP1V8_S3 68 55 51 35 34 0. INC.1UF 201 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 72 68 55 J2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A1 E1 J9 M9 R1 J1 VDDL NC R7 RFU 17 33 17 33 17 33 10% 6.1UF 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 72 68 55 J2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J1 A1 E1 J9 M9 R1 VDDL NC R7 RFU 33 31 17 68 33 31 17 68 33 31 17 68 1 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 72 68 55 VDD D 2 10% 6.1UF VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 VDD B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 MEM_A_DQ<31> LDQS LDQS* UDQS UDQS* F7 E8 B7 A8 MEM_A_DQS_P<2> 17 MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<26> MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<18> MEM_A_DQ<17> MEM_A_DQ<16> 17 31 68 VDDL VDDQ NC R7 RFU NC R3 17 31 68 R8 31 17 MEM_A_A<13> 68 33 R2 17 31 MEM_A_A<12> 68 P7 17 31 MEM_A_A<11> 68 M2 MEM_A_A<10> 17 31 68 P3 17 31 MEM_A_A<9> 68 P8 17 31 MEM_A_A<8> 68 P2 17 31 MEM_A_A<7> 68 N7 17 31 MEM_A_A<6> 68 N3 17 31 MEM_A_A<5> 68 N8 17 31 MEM_A_A<4> 68 N2 MEM_A_A<3> 17 31 68 M7 17 31 MEM_A_A<2> 68 M3 17 31 MEM_A_A<1> 68 M8 17 31 MEM_A_A<0> 68 RFU NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OMIT U3160 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per MEM_A_A<13> MEM_A_A<12> 68 33 31 17 MEM_A_A<11> 68 33 31 17 MEM_A_A<10> 68 33 31 17 MEM_A_A<9> 68 33 31 17 MEM_A_A<8> 68 33 31 17 MEM_A_A<7> 68 33 31 17 MEM_A_A<6> 68 33 31 17 MEM_A_A<5> 68 33 31 17 MEM_A_A<4> 0.1UF X5R 201 VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 MEM_A_DQ<63> 17 31 68 MEM_A_DQ<62> 17 31 68 LDQS LDQS* UDQS UDQS* F7 E8 B7 A8 MEM_A_DQS_P<6> 17 31 68 MEM_A_DQS_N<6> 17 31 68 MEM_A_DQS_P<7> 17 31 68 MEM_A_DQS_N<7> 17 31 68 MEM_A_DQ<61> 17 31 68 MEM_A_DQ<60> 17 31 68 MEM_A_DQ<59> 17 31 68 MEM_A_DQ<58> 17 31 68 MEM_A_DQ<57> 17 31 68 MEM_A_DQ<56> 17 31 68 MEM_A_DQ<55> 17 31 68 MEM_A_DQ<54> 17 31 68 MEM_A_DQ<53> 17 31 68 MEM_A_DQ<52> 17 31 68 MEM_A_DQ<51> 17 31 68 MEM_A_DQ<50> 17 31 68 MEM_A_DQ<49> 17 31 68 MEM_A_DQ<48> 17 31 68 SYNC_DATE=(MASTER) THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.0 OF 31 1 73 A .3V X5R VDDL RFU RFU NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VDDQ OMIT U3150 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per A1 E1 J9 M9 R1 J2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J1 A1 E1 J9 M9 R1 VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 0.3V X5R 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 72 68 55 J2 72 31 21 18 16 8 7 6 PP1V8_S3 68 55 51 35 34 32 C3110 201 201 PP0V9_S3 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 0.3V X5R A3 E3 J3 N1 P9 33 31 17 68 33 31 17 68 33 31 17 68 MEM_A_A<11> NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VDDQ NC R7 RFU 17 31 68 MEM_A_DQ<14> VDDL A3 E3 J3 N1 P9 33 31 17 68 33 31 17 68 33 31 17 68 MEM_A_A<12> MEM_A_DQ<15> A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 33 31 17 68 33 31 17 68 R8 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 MEM_A_A<13> J7 33 31 17 68 VDD B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 201 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 NC R3 RFU VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 J7 VDDQ C3120 0.1UF PP0V9_S3 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 1 10% 6.3V X5R C3150 J2 1 PP0V9_S3 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 2 72 55 32 31 8 6 J1 C3140 PP0V9_S3 MEM_A_DQS_P<6> 68 17 MEM_A_DQ<60> C3170 VSSQ VDD 72 55 32 31 8 6 F7 E8 B7 A8 MEM_A_DQ<61> 68 31 17 VSSQ NC R3 RFU PP0V9_S3 LDQS LDQS* UDQS UDQS* MEM_A_DQ<62> C NC R7 RFU 72 55 32 31 8 6 MEM_A_DQ<63> NC E2 NC NC A2 NC VSS VSS B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 B3 UDM F3 LDM B3 UDM F3 LDM VSSQ U3130 VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 L1 NC/BA2 L3 BA1 L2 BA0 MEM_CLK_P<0> J8 CK 68 31 17 OMIT J2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J1 NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16 68 33 31 16 6 NC E2 NC NC A2 NC MEM_A_BS<2> R8 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 16 MEM_A_DQS_N<4> 17 MEM_A_DQS_P<5> MEM_A_A<13> MEM_A_A<12> MEM_A_DQS_P<4> 17 MEM_CLK_P<0> J8 CK MEM_CLK_N<0> K8 CK* K2 CKE MEM_CKE<0> 68 33 31 17 VSS NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 68 33 31 16 B3 UDM F3 LDM VSSQ R8 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 17 31 68 68 33 31 16 L8 CS* MEM_ODT<0> 68 33 31 17 MEM_A_BS<0> MEM_A_DQS_N<3> VDDQ NC R3 RFU 17 31 68 MEM_A_DQS_P<3> VDDL NC R7 RFU 17 31 68 68 33 31 16 68 33 31 16 B3 UDM F3 LDM F7 E8 B7 A8 MEM_A_DQ<31> MEM_CLK_P<0> J8 CK MEM_CLK_N<0> K8 CK* K2 CKE MEM_CKE<0> 68 33 31 16 6 A1 E1 J9 M9 R1 J2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 68 33 31 16 68 33 31 17 A3 E3 J3 N1 P9 MEM_A_A<11> 17 MEM_A_BS<0> 68 33 31 31 68 NC E2 NC NC A2 NC VSSDL MEM_A_A<12> MEM_A_DQS_N<1> 17 68 33 31 16 VSS MEM_A_A<13> MEM_A_DQS_P<1> K7 RAS* L7 CAS* K3 WE* MEM_A_WE_L 31 17 68 33 31 17 68 33 31 17 68 33 68 33 31 16 K9 ODT MEM_A_CAS_L 31 17 68 33 31 17 68 33 31 17 68 33 MEM_A_DQ<6> L8 CS* MEM_A_RAS_L 17 33 17 33 31 17 68 33 31 17 68 33 MEM_A_DQ<8> MEM_CLK_N<0> K8 CK* K2 CKE MEM_CKE<0> MEM_CS_L<0> J1 A1 E1 J9 M9 R1 LDQS LDQS* UDQS UDQS* 68 MEM_A_DQS_P<0> 31 17 17 68 33 31 MEM_A_DQS_N<0> 17 68 33 31 MEM_A_DQ<9> MEM_CLK_P<0> J8 CK 31 16 6 MEM_ODT<0> 68 33 C 64MX16 MEM_A_DQ<10> 17 33 VDD B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 VDDQ J2 33 31 16 68 MEM_A_A<7> MEM_A_DQ<11> 31 17 68 33 31 68 31 68 31 68 VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 VDDL NC R3 RFU A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 33 31 17 68 MEM_A_A<8> U3100 MEM_A_DQ<12> VDD NC R7 RFU J7 33 31 17 68 33 31 17 68 MEM_A_A<9> MEM_A_DQ<13> 201 A3 E3 J3 N1 P9 33 31 17 68 33 31 17 68 MEM_A_A<10> OMIT NC R3 RFU 17 31 68 1 0.3V X5R J1 2 72 55 32 31 8 6 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 C3100 PP0V9_S3 J1 72 55 32 31 8 6 A1 E1 J9 M9 R1 PP0V9_S3 J7 72 55 32 31 8 6 72 55 32 31 8 6 B.1UF 2 68 33 31 17 68 33 31 17 J7 10% 6.3V 0.1UF 1 10% 6. THE POSSESSOR AGREES TO THE FOLLOWING B3 UDM F3 LDM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT VSSQ III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 3 68 17 31 MEM_A_DQS_P<7> 31 17 NOTICE OF PROPRIETARY PROPERTY 4 68 17 31 17 31 68 D B DDR2 DRAM Channel A DRAWING NUMBER 2 REV.1UF 2 10% 6.

1UF 6.3V X5R J2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J1 A1 E1 J9 M9 R1 VDDL NC R7 RFU 33 32 17 68 201 2 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 72 68 55 VDD D 72 55 32 31 8 6 C3210 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 10% 6.3V X5R 201 VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 MEM_B_DQ<31> VDD LDQS LDQS* UDQS UDQS* F7 E8 B7 A8 MEM_B_DQS_P<2> 17 MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<26> MEM_B_DQ<25> MEM_B_DQ<24> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<20> MEM_B_DQ<19> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<16> 17 32 68 17 17 68 17 68 17 68 17 68 17 68 17 68 17 68 17 68 17 68 17 68 17 68 17 68 17 68 17 68 VDDL VDDQ NC R7 RFU NC R3 32 68 R8 32 MEM_B_A<13> R2 32 MEM_B_A<12> P7 32 MEM_B_A<11> M2 MEM_B_A<10> 32 P3 32 MEM_B_A<9> P8 32 MEM_B_A<8> P2 32 MEM_B_A<7> N7 32 MEM_B_A<6> N3 32 MEM_B_A<5> N8 32 MEM_B_A<4> N2 MEM_B_A<3> 32 M7 32 MEM_B_A<2> M3 32 MEM_B_A<1> M8 32 MEM_B_A<0> RFU NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OMIT U3260 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per MEM_B_A<13> MEM_B_A<12> 68 33 32 17 MEM_B_A<11> 68 33 32 17 MEM_B_A<10> 68 33 32 17 MEM_B_A<9> 68 33 32 17 MEM_B_A<8> 68 33 32 17 MEM_B_A<7> 68 33 32 17 MEM_B_A<6> 33 32 17 68 68 33 32 17 MEM_B_A<4> 17 32 68 MEM_B_A<3> 17 32 68 MEM_B_A<2> 17 32 68 MEM_B_A<1> MEM_B_DQ<44> 17 32 68 MEM_B_A<0> MEM_B_DQ<43> 17 32 68 VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 MEM_B_DQ<47> LDQS LDQS* UDQS UDQS* F7 E8 B7 A8 MEM_B_DQS_P<4> 17 MEM_B_DQ<46> MEM_B_DQ<45> VDDL VDDQ 17 32 68 MEM_B_DQ<41> 17 32 68 MEM_B_BS<1> MEM_B_DQ<40> 17 32 68 MEM_B_BS<0> MEM_B_DQ<39> 17 32 68 MEM_B_DQ<38> 17 32 68 MEM_CLK_P<4> J8 CK MEM_B_DQ<37> 17 32 68 MEM_CLK_N<4> K8 CK* 17 32 68 MEM_CKE<4> MEM_B_DQ<35> 17 32 68 MEM_CS_L<3> K2 CKE L8 CS* MEM_B_DQ<34> 17 32 68 MEM_B_DQ<33> 17 32 68 MEM_ODT<3> K9 ODT MEM_B_RAS_L K7 RAS* L7 CAS* K3 WE* MEM_B_DQ<32> MEM_B_DQS_N<2> MEM_B_BS<1> MEM_B_DQS_P<3> 17 32 MEM_B_DQS_N<3> 17 32 68 68 MEM_B_BS<0> 68 33 32 16 MEM_CLK_P<4> J8 CK 68 33 32 16 MEM_CLK_P<4> J8 CK MEM_CLK_N<4> K8 CK* 68 33 32 16 MEM_CLK_N<4> K8 CK* 68 33 32 16 MEM_CLK_N<4> K8 CK* 68 33 32 16 MEM_CKE<4> MEM_CKE<4> MEM_CS_L<3> K2 CKE L8 CS* 68 33 32 16 68 33 32 16 68 33 32 16 MEM_CS_L<3> K2 CKE L8 CS* MEM_ODT<3> K9 ODT MEM_ODT<3> K9 ODT 68 33 32 17 MEM_B_RAS_L 68 33 32 17 MEM_B_RAS_L 68 33 32 17 MEM_B_CAS_L 68 33 32 17 MEM_B_CAS_L 68 33 32 17 MEM_B_WE_L K7 RAS* L7 CAS* K3 WE* 68 33 32 17 MEM_B_WE_L K7 RAS* L7 CAS* K3 WE* MEM_CKE<4> MEM_CS_L<3> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DM<1> MEM_B_DM<0> K2 CKE L8 CS* NC E2 NC NC A2 NC K9 ODT K7 RAS* L7 CAS* K3 WE* B3 UDM F3 LDM VSS VSSDL 68 33 32 16 6 68 32 17 MEM_B_DM<3> 68 32 17 MEM_B_DM<2> NC E2 NC NC A2 NC B3 UDM F3 LDM VSSQ VSS VSSDL VSSQ 68 33 32 16 6 68 32 17 MEM_B_DM<5> 68 32 17 MEM_B_DM<4> 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per 32 68 MEM_B_CAS_L MEM_B_DQS_N<4> 17 32 68 MEM_B_WE_L MEM_B_DQS_P<5> 17 32 68 MEM_B_DQS_N<5> 17 32 68 MEM_B_DM<7> 68 32 17 MEM_B_DM<6> VSS VSSDL MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<50> MEM_B_DQ<49> MEM_B_DQ<48> B3 UDM F3 LDM 68 32 17 17 32 68 68 17 32 32 32 MEM_B_DQS_N<7> 68 17 17 32 68 1 0.0.3V X5R 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 72 68 55 NC R7 RFU 32 17 68 33 32 17 68 33 201 2 J2 72 32 31 21 18 16 8 7 6 PP1V8_S3 68 55 51 35 34 72 55 32 31 8 6 C3250 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 10% 6.3V X5R A3 E3 J3 N1 P9 33 32 17 68 MEM_B_A<10> 17 32 68 MEM_B_DQ<14> VDDL A3 E3 J3 N1 P9 33 32 17 68 MEM_B_A<11> MEM_B_DQ<15> A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 33 32 17 68 33 32 17 68 MEM_B_A<12> NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 J7 33 32 17 68 R8 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 MEM_B_A<13> VDD B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 C3220 201 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 NC R3 RFU VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 PP0V9_S3 0.1UF 10% 6.1UF 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 72 68 55 J7 VDDQ 1 10% 6.1UF A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 33 32 17 68 MEM_B_A<8> U3200 NC R3 RFU 17 32 68 1 A3 E3 J3 N1 P9 33 32 17 68 MEM_B_A<9> OMIT NC R7 RFU 17 32 68 MEM_B_DQ<13> 2 10% 6. INC.1UF J1 1 68 33 32 17 68 33 32 17 MEM_B_DQ<60> 10% J7 72 55 32 31 8 6 2 MEM_B_DQS_P<6> 68 17 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 72 68 55 VDD C3240 F7 E8 B7 A8 MEM_B_DQ<61> 68 17 32 VSSQ NC R3 RFU PP0V9_S3 LDQS LDQS* UDQS UDQS* MEM_B_DQ<62> C NC R7 RFU 72 55 32 31 8 6 MEM_B_DQ<63> NC E2 NC NC A2 NC VSS VSS B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 B3 UDM F3 LDM B3 UDM F3 LDM VSSQ U3230 VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 L1 NC/BA2 L3 BA1 L2 BA0 16 68 32 17 OMIT J2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J1 NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 MEM_CLK_P<3> J8 CK 68 33 32 16 6 NC E2 NC NC A2 NC MEM_B_A<13> MEM_B_A<12> MEM_B_DQS_P<4> 17 MEM_CLK_P<3> J8 CK MEM_CLK_N<3> K8 CK* K2 CKE MEM_CKE<3> B3 UDM F3 LDM OMIT VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 L1 NC/BA2 L3 BA1 L2 BA0 68 33 32 16 68 33 32 16 NC E2 NC NC A2 NC NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VDDQ 17 32 68 68 33 32 16 L8 CS* R8 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 J2 A1 E1 J9 M9 R1 J2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 64MX16 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 VDDL A1 E1 J9 M9 R1 A3 E3 J3 N1 P9 VSS U3210 VDD MEM_CLK_P<3> J8 CK 68 33 32 17 B3 UDM F3 LDM OMIT VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 L1 NC/BA2 L3 BA1 L2 BA0 68 33 32 16 MEM_CS_L<2> J1 A1 E1 J9 M9 R1 LDQS LDQS* UDQS UDQS* 17 32 68 17 32 68 MEM_B_A<11> MEM_CLK_P<3> J8 CK 32 16 6 MEM_ODT<2> 68 33 C MT47H64M16 MEM_B_DQ<9> 17 32 68 17 32 68 VDDQ VDDL NC R3 RFU J2 33 32 17 68 MEM_B_A<6> FBGA MEM_B_DQ<10> NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VDD NC R7 RFU A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 33 32 17 68 64MX16 MEM_B_DQ<11> 17 32 68 MEM_B_A<12> R8 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 201 J7 33 32 17 68 MEM_B_A<7> MEM_B_DQ<12> MEM_B_A<13> 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 72 68 55 0. 6 MEM_B_DQ<55> VSSQ NC E2 NC NC A2 NC VSS D 68 17 32 B3 UDM F3 LDM D 7 MEM_B_DQ<56> 68 17 32 17 32 68 SIZE 8 MEM_B_DQ<57> NC E2 NC NC A2 NC A3 E3 J3 N1 P9 MEM_B_BS<0> L1 NC/BA2 L3 BA1 L2 BA0 U3270 L1 NC/BA2 L3 BA1 L2 BA0 MEM_B_BS<2> MEM_B_DQ<36> MEM_B_DQ<58> 17 32 68 68 17 32 32 PP0V9_S3 OMIT A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 32 68 68 68 17 32 68 MEM_B_BS<2> J7 32 17 68 32 MEM_B_DQS_N<1> 17 32 A3 E3 J3 N1 P9 32 17 68 MEM_B_BS<1> MEM_B_DQS_P<1> 17 L1 NC/BA2 L3 BA1 L2 BA0 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 32 17 68 33 68 17 32 68 MEM_B_BS<2> J7 A MEM_B_DQS_N<0> 32 MEM_CLK_P<4> J8 CK 68 16 6 MEM_ODT<3> 33 32 32 17 68 33 32 17 68 33 MEM_B_DQS_P<0> 17 A3 E3 J3 N1 P9 32 16 68 33 MEM_B_BS<0> A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 32 16 68 33 32 16 68 33 32 16 68 33 MEM_B_BS<1> J7 32 17 68 33 L1 NC/BA2 L3 BA1 L2 BA0 A3 E3 J3 N1 P9 32 17 68 33 MEM_B_BS<2> NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 MEM_B_DQ<42> 68 33 32 17 32 17 68 33 MEM_B_A<5> R8 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 MEM_B_DQ<59> 68 32 17 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VDDL C3260 201 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 72 68 55 J2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J1 A1 E1 J9 M9 R1 VDD NC R3 MEM_B_A<13> R8 MEM_B_A<12> R2 MEM_B_A<11> P7 MEM_B_A<10> M2 P3 MEM_B_A<9> P8 MEM_B_A<8> P2 MEM_B_A<7> N7 MEM_B_A<6> N3 MEM_B_A<5> N8 MEM_B_A<4> N2 MEM_B_A<3> M7 MEM_B_A<2> M3 MEM_B_A<1> M8 MEM_B_A<0> PP0V9_S3 1 0. 051-7230 SCALE SHT NONE 5 MEM_B_DQ<54> C3270 2 SYNC_MASTER=(MASTER) APPLE INC.1UF 10% 6.1UF J1 1 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 2 J1 72 55 32 31 8 6 C3200 A1 E1 J9 M9 R1 PP0V9_S3 J7 72 55 32 31 8 6 201 B. THE POSSESSOR AGREES TO THE FOLLOWING 4 68 32 17 MEM_B_DQS_N<6> 17 NOTICE OF PROPRIETARY PROPERTY VSSDL 68 17 32 B DDR2 DRAM Channel B DRAWING NUMBER 2 REV.3V X5R 72 31 21 18 16 8 7 6 PP1V8_S3 68 55 51 35 34 32 PP0V9_S3 0.1UF 10% 6.3V X5R PP0V9_S3 0.3V X5R 33 32 17 68 33 32 17 68 33 32 17 68 33 32 17 68 33 32 17 68 33 32 17 68 33 32 16 68 33 32 16 68 33 32 16 68 33 32 16 68 MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0> 33 32 17 68 33 32 17 68 33 32 17 68 (2 OF 2) Bit swizzle per L1 NC/BA2 L3 BA1 L2 BA0 MEM_B_BS<2> MEM_B_BS<1> MEM_B_BS<0> MEM_B_DQ<8> MEM_B_DQ<7> 17 32 68 17 32 68 MEM_B_DQ<6> MEM_B_DQ<5> 17 32 68 MEM_B_DQ<4> 17 32 68 MEM_B_DQ<3> 17 32 68 MEM_B_DQ<2> 17 32 68 MEM_B_DQ<1> 32 17 68 33 17 32 68 MEM_B_DQ<0> F7 E8 B7 A8 MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7> MEM_B_A<6> MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0> MEM_B_DQS_P<0> 17 32 MEM_B_BS<2> MEM_B_DQS_N<0> 17 32 MEM_B_BS<1> MEM_B_DQS_P<1> 17 32 MEM_B_BS<0> MEM_B_DQS_N<1> 17 32 68 68 68 68 MEM_CLK_N<3> K8 CK* K2 CKE MEM_CKE<3> 68 33 32 16 MEM_CLK_N<3> K8 CK* K2 CKE MEM_CKE<3> 68 33 32 16 MEM_CS_L<2> 68 33 32 16 L8 CS* NC E2 NC NC A2 NC K9 ODT K7 RAS* L7 CAS* K3 WE* MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L 68 32 17 MEM_B_DM<1> 68 32 17 MEM_B_DM<0> 68 33 32 16 6 68 33 32 17 VSSDL FBGA MT47H64M16 (2 OF 2) Bit swizzle per LDQS LDQS* UDQS UDQS* F7 E8 B7 A8 MEM_B_DQ<31> 17 32 68 NC R7 RFU MEM_B_DQ<30> 17 32 68 NC R3 RFU MEM_B_DQ<29> MEM_B_A<13> MEM_B_DQ<28> MEM_B_A<12> MEM_B_DQ<27> MEM_B_A<11> MEM_B_DQ<26> MEM_B_A<10> MEM_B_DQ<25> MEM_B_A<9> MEM_B_DQ<24> MEM_B_A<8> MEM_B_DQ<23> MEM_B_A<7> MEM_B_DQ<22> MEM_B_A<6> MEM_B_DQ<21> MEM_B_A<5> MEM_B_DQ<20> MEM_B_A<4> MEM_B_DQ<19> MEM_B_A<3> MEM_B_DQ<18> MEM_B_A<2> MEM_B_DQ<17> MEM_B_A<1> MEM_B_DQ<16> MEM_B_A<0> MEM_B_DQS_P<2> MEM_B_BS<2> MEM_B_DQS_N<2> MEM_B_BS<1> MEM_B_DQS_P<3> MEM_B_BS<0> MEM_B_DQS_N<3> MEM_ODT<2> K9 ODT MEM_B_RAS_L K7 RAS* L7 CAS* K3 WE* MEM_B_CAS_L 68 33 32 17 MEM_B_WE_L 68 32 17 MEM_B_DM<3> 68 32 17 MEM_B_DM<2> VSSQ 68 33 32 16 MEM_CS_L<2> L8 CS* MEM_ODT<2> K9 ODT MEM_B_RAS_L K7 RAS* L7 CAS* K3 WE* 68 33 32 16 6 68 33 32 17 VSS VSSDL U3220 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per LDQS LDQS* UDQS UDQS* 68 33 32 17 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 MEM_B_DQ<47> MEM_B_DQ<46> MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<41> MEM_B_DQ<40> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<33> MEM_B_DQ<32> F7 E8 B7 A8 68 33 32 17 MEM_B_CAS_L 68 33 32 17 MEM_B_WE_L 68 32 17 MEM_B_DM<5> 68 32 17 MEM_B_DM<4> 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 17 32 68 17 17 MEM_B_A<11> 17 MEM_B_A<10> 17 MEM_B_A<9> 17 MEM_B_A<8> 17 MEM_B_A<7> 17 MEM_B_A<6> 17 MEM_B_A<5> 17 MEM_B_A<4> 17 MEM_B_A<3> 17 MEM_B_A<2> 17 MEM_B_A<1> 17 MEM_B_A<0> 17 32 68 68 33 32 17 17 32 68 68 33 32 17 17 32 68 68 33 32 17 MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> 32 68 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 17 32 68 68 33 32 MEM_B_BS<2> MEM_B_BS<1> MEM_B_BS<0> R8 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 VDDQ 16 MEM_CLK_N<3> K8 CK* 16 MEM_CKE<3> 16 MEM_CS_L<2> K2 CKE L8 CS* MEM_ODT<2> K9 ODT 68 33 32 17 MEM_B_RAS_L 68 33 32 17 MEM_B_CAS_L 68 33 32 17 MEM_B_WE_L K7 RAS* L7 CAS* K3 WE* MEM_B_DM<7> 68 32 17 MEM_B_DM<6> 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per VSSDL VSSDL VSSQ 72 55 32 31 8 6 VDDQ B 32 17 68 33 32 17 68 33 32 17 68 33 32 17 68 33 32 17 68 33 32 17 68 33 32 17 68 33 32 17 68 33 32 17 68 33 32 17 68 33 32 17 68 33 32 17 68 33 RFU NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OMIT U3240 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 VDD LDQS LDQS* UDQS UDQS* F7 E8 B7 A8 MEM_B_DQ<15> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<9> 17 32 68 17 32 68 17 32 68 17 32 68 17 32 68 17 32 68 17 32 68 17 32 68 MEM_B_DQ<8> MEM_B_DQ<7> 17 68 17 68 17 68 17 68 17 68 MEM_B_DQ<6> MEM_B_DQ<5> MEM_B_DQ<4> MEM_B_DQ<3> MEM_B_DQ<2> MEM_B_DQ<0> NC MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> 32 MEM_B_A<7> 32 MEM_B_A<6> 32 MEM_B_A<5> 32 MEM_B_A<4> 32 MEM_B_A<3> 17 32 68 17 32 68 17 32 68 MEM_B_DQ<1> NC MEM_B_A<2> MEM_B_A<1> MEM_B_A<0> R7 R3 R8 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 VDDL RFU RFU NC/A13 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VDDQ OMIT U3250 64MX16 FBGA MT47H64M16 (2 OF 2) Bit swizzle per A1 E1 J9 M9 R1 J2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J1 A1 E1 J9 M9 R1 VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 2 1 0.3V X5R 201 VREF DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 byte? DQ1 DQ0 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 MEM_B_DQ<63> LDQS LDQS* UDQS UDQS* F7 E8 B7 A8 MEM_B_DQS_P<6> 17 32 68 MEM_B_DQS_N<6> 17 32 68 MEM_B_DQS_P<7> 17 32 68 MEM_B_DQS_N<7> 17 32 68 17 32 68 MEM_B_DQ<62> 17 32 68 MEM_B_DQ<61> 17 32 68 MEM_B_DQ<60> 17 32 68 MEM_B_DQ<59> 17 32 68 MEM_B_DQ<58> 17 32 68 MEM_B_DQ<57> 17 32 68 MEM_B_DQ<56> 17 32 68 MEM_B_DQ<55> 17 32 68 MEM_B_DQ<54> 17 32 68 MEM_B_DQ<53> 17 32 68 MEM_B_DQ<52> 17 32 68 MEM_B_DQ<51> 17 32 68 MEM_B_DQ<50> 17 32 68 MEM_B_DQ<49> 17 32 68 MEM_B_DQ<48> 17 32 68 SYNC_DATE=(MASTER) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT VSSQ III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 3 17 32 68 68 17 32 MEM_B_DQS_P<7> 68 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.8 6 7 2 3 4 5 1 72 55 32 31 8 6 C3230 PP0V9_S3 2 1 0.0 OF 32 1 73 A .

3V X5R B 201 0.1UF 10% 6.3V 2 X5R 2 X5R 201 201 D 8 2 7 5% 1/32W 3 6 5% 1/32W 4X0201 4 5 5% 1/32W 4X0201 5% 1/32W 4X0201 4X0201 1 C3302 1 10% 6.3V 201 1 10% 6.1UF 200 MEM_CLK_P<3> 1 68 32 16 5% 1/32W 6 R3395 68 31 17 68 32 16 7 3 1 68 31 17 C 8 2 MEM_CLK_P<1> 1 68 32 16 IN PP0V9_S0 1 MEM_CLK_N<1> 1 68 31 16 MEM_B_A<13> RP3301 RP3301 RP3301 RP3301 MEM_CLK_P<0> IN 56 56 56 56 5% 1/32W 5% 1/20W MF 2 201 68 32 17 68 31 16 RP3300 RP3300 RP3300 RP3300 MEM_ODT<3> MEM_B_RAS_L MEM_B_BS<1> MEM_B_BS<2> C C3311 0.3V X5R C3308 1 10% 6.1UF 2 56 56 56 56 1 8 2 7 5% 1/32W 4X0201 3 6 5% 1/32W 4X0201 5 5% 1/32W 4X0201 5% 1/32W 4X0201 4 IN 5% 1/20W MF 2 201 68 31 17 IN 68 31 17 IN IN IN MEM_CLK_N<4> 68 31 17 R3396 200 5% 1/20W MF 2 201 RP3303 RP3303 RP3303 RP3303 MEM_A_A<4> MEM_A_A<11> MEM_A_A<12> 56 56 56 56 1 8 2 7 5% 1/32W 4X0201 3 6 5% 1/32W 4X0201 5 5% 1/32W 4X0201 5% 1/32W 4X0201 4 1 C3303 0.3V X5R 201 6.1UF 2 X5R 201 201 A NOTICE OF PROPRIETARY PROPERTY 10% 6.3V 2 X5R THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.3V X5R 201 2 6.1UF 10% 6.1UF 10% 201 0.1UF 0.1UF 10% 6. one cap for every two discrete resistors BOMOPTION shown at the top of each group applies to every part below it MEM CLOCK TERMINATION 72 55 8 7 6 Place one resistor at each end of Y split 68 31 16 MEM_CLK_N<0> R3390 1 200 5% 1/20W MF 2 201 D 68 31 16 R3391 1 200 68 32 16 6 IN 68 32 17 IN 68 32 17 IN 68 32 17 IN 68 32 17 R3392 200 5% 1/20W MF 2 201 68 32 16 R3393 1 200 5% 1/20W MF 2 201 68 31 17 IN 68 31 17 IN 68 31 17 IN 68 31 17 IN 68 31 17 IN 68 31 17 IN 68 31 17 MEM_CLK_N<3> R3394 200 5% 1/20W MF 2 201 4X0201 5% 1/32W 4X0201 4 5 5% 1/32W 4X0201 MEM_A_BS<1> MEM_A_A<2> MEM_A_A<10> MEM_A_A<3> RP3302 RP3302 RP3302 RP3302 MEM_B_A<12> NC 56 56 56 56 1 4X0201 1 C3300 1 0.1UF 10% 6.3V X5R 201 Memory Active Termination 1 C3324 0.1UF 2 1 1 A IN 68 31 16 6 IN 68 31 16 IN 68 31 16 IN 68 31 17 IN 68 31 17 68 31 16 IN IN RP3312 RP3312 RP3312 RP3312 RP3313 RP3313 RP3313 RP3313 MEM_CS_L<0> MEM_ODT<0> MEM_CKE<1> MEM_CKE<0> MEM_A_A<1> MEM_A_BS<0> MEM_CS_L<1> 56 56 56 56 56 56 56 NC56 1 8 2 7 5% 1/32W 4X0201 3 6 5% 1/32W 4X0201 4 5 5% 1/32W 4X0201 1 8 5% 1/32W 4X0201 3 6 5% 1/32W 4X0201 4 5 5% 1/32W 4X0201 2 7 5% 1/32W 4X0201 5% 1/32W 4X0201 10% 201 2 1 10% 6.1UF 2 6.1UF 0.3V C3301 0.1UF 10% 2 6.8 7 6 3 4 5 2 1 One cap for each side of every RPAK. INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT LAYOUT NOTE:PLACE ONE CAP CLOSE TO EVERY TWO PULLUP RESISTORS TERMINATED TO PP0V9_S0_MEM_TERM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.3V X5R 201 2 X5R C3304 1 10% 6.1UF 2 C3315 0.3V X5R C3307 0.1UF 2 C3305 0.1UF 10% 6.1UF 0.3V 2 X5R C3310 1 0.1UF 2 C3317 0.3V 201 0.0.1UF 10% 2 6.3V X5R 201 2 X5R C3316 1 10% 6.3V X5R 201 2 X5R C3306 1 10% 6.1UF 2 6.1UF 0.0 OF 33 1 73 .1UF 0.3V X5R 201 2 6.3V 201 1 10% 201 10% C3309 0. 051-7230 B.3V X5R 201 2 X5R C3322 1 0.1UF 201 68 31 16 0.3V 1 C3325 0.1UF 2 C3313 C3323 0.3V 1 10% C3319 0.3V 201 0.3V X5R C3314 1 10% 6.3V X5R 201 2 X5R C3320 1 10% 6.3V 201 C3321 0.1UF 10% 6.3V X5R 201 2 X5R C3318 1 10% 6.3V X5R 201 201 MEM_CLK_P<4> 68 31 16 6 IN 68 31 17 IN 68 31 17 IN 68 31 17 IN 68 32 16 IN 68 32 17 IN 68 32 17 68 32 16 IN 68 32 17 IN 68 32 17 IN 68 32 17 B IN 68 32 17 IN IN 68 32 17 IN 68 32 17 IN 68 32 17 68 32 17 IN IN 68 32 17 IN 68 32 16 IN 68 32 16 6 68 32 17 IN IN 68 32 17 IN 68 32 17 IN 68 32 16 IN 68 32 17 IN RP3306 RP3306 RP3306 RP3306 MEM_ODT<1> MEM_A_WE_L MEM_A_RAS_L MEM_A_BS<2> RP3307 RP3307 RP3307 RP3307 MEM_CS_L<2> MEM_B_A<1> MEM_B_A<2> MEM_CS_L<3> RP3308 RP3308 RP3308 RP3308 MEM_B_A<4> MEM_B_A<8> MEM_B_A<6> MEM_B_A<3> RP3309 RP3309 RP3309 RP3309 MEM_B_A<0> MEM_B_A<9> MEM_B_A<7> MEM_B_A<11> RP3310 RP3310 RP3310 RP3310 MEM_B_A<10> MEM_CKE<4> MEM_ODT<2> MEM_B_A<5> RP3311 RP3311 RP3311 RP3311 MEM_B_CAS_L MEM_B_WE_L MEM_CKE<3> MEM_B_BS<0> 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 1 8 2 7 5% 1/32W 4X0201 3 6 5% 1/32W 4X0201 4 5 5% 1/32W 4X0201 5% 1/32W 4X0201 1 8 2 7 5% 1/32W 4X0201 3 6 5% 1/32W 4X0201 5 5% 1/32W 4X0201 5% 1/32W 4X0201 4 1 8 2 7 5% 1/32W 4X0201 3 6 5% 1/32W 4X0201 5 5% 1/32W 4X0201 5% 1/32W 4X0201 4 1 8 2 7 5% 1/32W 4X0201 3 6 5% 1/32W 4X0201 4 5 5% 1/32W 4X0201 5% 1/32W 4X0201 1 8 2 7 5% 1/32W 4X0201 3 6 5% 1/32W 4X0201 4 5 5% 1/32W 4X0201 5% 1/32W 4X0201 1 8 2 7 5% 1/32W 4X0201 3 6 5% 1/32W 4X0201 4 5 5% 1/32W 4X0201 5% 1/32W 4X0201 1 C3312 1 10% 6. SCALE SHT NONE 8 7 6 5 4 3 2 REV.1UF 2 1 2 R3397 1 200 5% 1/20W MF 2 201 IN 68 31 17 IN 68 31 17 IN 68 31 17 IN RP3304 RP3304 RP3304 RP3304 MEM_A_A<7> MEM_A_A<13> MEM_A_A<8> MEM_A_A<9> RP3305 RP3305 RP3305 RP3305 MEM_A_A<6> MEM_A_A<5> MEM_A_A<0> MEM_A_CAS_L 56 56 56 56 56 56 56 56 1 8 2 7 5% 1/32W 4X0201 3 6 5% 1/32W 4X0201 5 5% 1/32W 4X0201 5% 1/32W 4X0201 4 1 8 2 7 5% 1/32W 4X0201 3 6 5% 1/32W 4X0201 4 5 5% 1/32W 4X0201 5% 1/32W 4X0201 1 10% 6.

3V 2 CERM 402-LF 1 20% 2 6.2UF 20% 6.8 6 7 51 35 34 32 31 21 18 16 8 7 6 72 68 55 PP1V8_S3 OMIT 1 C3490 10UF 20% 2 6.3V 2 CERM 402-LF 2.2UF 1 1 1 1 1 20% 6.3V CERM 402-LF OMIT C3405 OMIT C3424 2.3V 2 CERM 402-LF COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES B B APPROXIMATE CAP ARRANGEMENT TWO 0402 CAPS ALONG PACKAGE EDGE THREE 0603 CAPS SPREAD TO COVER ALL 8 PARTS DDR2 BYPASSING 1 A SYNC_MASTER=MEMORY SYNC_DATE=06/20/2005 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.2UF 2 CAPS ALONG PACKAGE EDGE 1 OMIT C3431 OMIT 1 C3440 20% 6.2UF 20% 6.2UF C3410 1 2.2UF 20% 6.3V X5R 603 D PP1V8_S3 35 34 32 31 21 18 16 8 7 6 72 68 55 51 OMIT OMIT C3400 1 20% 6.2UF 20% 6.3V 2 CERM 402-LF 20% 6.3V CERM 402-LF OMIT 1 OMIT C3414 20% 6.0.3V CERM 402-LF 1 2.3V CERM 402-LF OMIT C3435 2.2UF 20% 6.3V 2 CERM 402-LF C3454 20% 2 6.3V 2 CERM 402-LF OMIT C3411 OMIT 2.2UF 20% 6.0 OF 34 1 73 A .3V 2 CERM 402-LF OMIT C3441 1 2.3V CERM 402-LF 20% 2 6. 051-7230 B.2UF 20% 6.2UF OMIT C3415 2.3V CERM 402-LF 2.2UF 20% 2 6.2UF 2.3V 2 CERM 402-LF C3430 20% 6.2UF OMIT C3421 2.3V 2 CERM 402-LF OMIT C3412 1 2.2UF 20% 6. SCALE SHT NONE 8 7 6 5 4 3 2 REV.2UF OMIT C3401 OMIT C3442 2.2UF 20% 2 6.3V 2 CERM 402-LF C3450 2.3V X5R 603 2 3 4 5 1 OMIT 1 C3492 10UF 20% 2 6.3V CERM 402-LF OMIT C3425 OMIT C3444 2.2UF 20% 6.3V 2 CERM 402-LF 1 20% 2 6. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART COLUMN OF THREE 0402 CAPS BETWEEN PACKAGES SIZE DRAWING NUMBER D APPLE INC.2UF 20% 2 6.3V X5R 603 D 51 35 34 32 31 21 18 16 8 7 6 72 68 55 PP1V8_S3 OMIT 1 C3491 10UF 20% 2 6.3V 2 CERM 402-LF OMIT 2.2UF 20% 6.2UF C3451 2.2UF 20% 6.3V 2 CERM 402-LF OMIT 1 2.3V 2 CERM 402-LF 20% 6.2UF C3446 2.3V CERM 402-LF 2 CAPS ALONG PACKAGE EDGE C C OMIT 1 OMIT C3404 1 2.2UF 20% 2 6.2UF OMIT 1 OMIT 1 2.3V 2 CERM 402-LF 2.2UF 1 1 1 1 OMIT C3445 1 C3455 2.3V 2 CERM 402-LF OMIT C3434 2.3V 2 CERM 402-LF OMIT C3416 1 2.3V 2 CERM 402-LF C3420 2.3V 2 CERM 402-LF 2.3V CERM 402-LF 20% 6.2UF 1 2.2UF 20% 6. INC.

2UF 20% 2 6.3V CERM 402-LF 2.2UF 20% 6.8 6 7 51 35 34 32 31 21 18 16 8 7 6 72 68 55 PP1V8_S3 OMIT 1 C3590 10UF 20% 2 6.0.3V CERM 402-LF OMIT C3505 OMIT C3524 2.2UF 20% 6.2UF 20% 2 6.2UF OMIT C3535 2.2UF OMIT C3511 2.2UF 20% 6.3V 2 CERM 402-LF 20% 6.2UF 20% 6.2UF 20% 6.3V 2 CERM 402-LF C3554 2.2UF 1 2.2UF C3592 10UF 20% 2 6.2UF 2 CAPS ALONG PACKAGE EDGE C3550 20% 6.3V 2 CERM 402-LF COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES B B APPROXIMATE CAP ARRANGEMENT TWO 0402 CAPS ALONG PACKAGE EDGE THREE 0603 CAPS SPREAD TO COVER ALL 8 PARTS DDR2 BYPASSING 2 A SYNC_MASTER=MEMORY SYNC_DATE=06/20/2005 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. 051-7230 B.3V CERM 402-LF 20% 2 6.2UF 20% 6.3V CERM 402-LF OMIT 1 OMIT C3514 20% 6.3V 2 CERM 402-LF C3540 20% 6. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D COLUMN OF THREE 0402 CAPS BETWEEN PACKAGES APPLE INC.2UF 1 1 C3530 1 1 1 20% 6.3V 2 CERM 402-LF OMIT C3512 1 2.3V CERM 402-LF 2.3V 2 CERM 402-LF OMIT C3521 OMIT 2.2UF 20% 6.3V 2 CERM 402-LF OMIT C3516 1 2.2UF 20% 6.2UF OMIT 1 1 OMIT C3531 2.3V 2 CERM 402-LF 1 OMIT 1 51 35 34 32 31 21 18 16 8 7 6 72 68 55 OMIT 2 3 4 5 C3542 2.3V 2 CERM 402-LF C3520 20% 6.3V CERM 402-LF OMIT C3525 OMIT C3544 2.3V 2 CERM 402-LF OMIT 2.3V 2 CERM 402-LF 2.3V 2 CERM 402-LF OMIT 1 D PP1V8_S3 OMIT 2.3V CERM 402-LF 2 CAPS ALONG PACKAGE EDGE C C OMIT 1 OMIT C3504 1 2.2UF 1 1 1 1 OMIT C3545 1 C3555 2.3V CERM 402-LF 1 2.3V 2 CERM 402-LF OMIT C3501 OMIT 2.3V 2 CERM 402-LF 2.2UF 20% 6. SCALE SHT NONE 8 7 6 5 4 3 2 REV.2UF 20% 6.2UF C3546 2.3V X5R 603 1 OMIT C3500 1 2.0 OF 35 1 73 A .3V 2 CERM 402-LF OMIT C3534 2.3V 2 CERM 402-LF 1 20% 2 6.3V 2 CERM 402-LF OMIT 1 20% 2 6. INC.3V 2 CERM 402-LF 20% 6.2UF 20% 6.2UF 20% 2 6.3V 2 CERM 402-LF 2.2UF 20% 6.3V X5R 603 D 51 35 34 32 31 21 18 16 8 7 6 72 68 55 PP1V8_S3 OMIT 1 C3591 10UF 20% 2 6.2UF 20% 2 6.2UF 20% 6.3V 2 CERM 402-LF 1 20% 2 6.3V X5R 603 C3510 1 1 2.2UF OMIT C3515 2.2UF OMIT C3541 1 C3551 2.

3V C4101 70 36 24 6 PCIE_E_D2R_N 70 36 24 6 PCIE_E_D2R_P 70 36 24 6 PCIE_E_R2D_C_N PCIE_E_R2D_C_P 70 36 24 6 PCIE_CLK100M_MINI_P_F PCIE_CLK100M_MINI_N_F 1210-4SM1 SYM_VER-1 69 24 9 6 S 4 69 24 9 6 70 36 24 6 7 6 PCIE_E_D2R_N_F PCIE_E_D2R_P_F CRITICAL L4103 90-OHM-100MA SOT563 58 41 25 6 4 2 SSM6N15FE 5 G 7 6 6 71 30 29 6 Q4103 7 6 SYM_VER-1 71 30 29 6 1 100K 2 R4106 L4100 NOSTUFF F-ST-SM 32 CRITICAL WOW_EN B CPB6330-0101F 31 SOT563 44 43 36 28 27 26 25 24 8 7 6 72 60 58 57 56 51 49 24 13 7 6 D 6 PCIE_E_D2R_N PCIE_E_D2R_P PCIE_E_R2D_C_N PCIE_E_R2D_C_P IN 1 PCIE_E_R2D_C_P 2 X5R 10% 6 6 PCIE_E_R2D_N 1 4 76 PCIE_E_R2D_C_N_F PCIE_E_R2D_P 2 3 76 PCIE_E_R2D_C_P_F 0.1UF 10% Q4102 D 6 D 3 2 10% 2 6.8 6 7 2 3 4 5 1 D D CRITICAL Q4101 M93 WIRELESS AIRPORT & BT CONNECTOR FDC638P SM-LF 6 44 43 36 28 27 26 25 24 8 7 6 72 60 58 57 56 51 49 PP3V3_S5 PP3V3_S5 5 4 2 44 43 36 28 27 26 25 24 8 7 6 72 60 58 57 56 51 49 Q4102 PP3V3_S3_AP_AUX 5% 1/20W MF 201 3 0.1UF 201 6.2MM MIN_NECK_WIDTH=0.3V X5R 201 C4112 1 R4105 SSM6N15FE C4111 MIN_LINE_WIDTH=0.1UF 2 6.3V X5R 201 PM_WLAN_EN_L_SS 5% 1/20W MF 201 10% 2 201 20% 6. 051-7230 B.3V X5R 201 72 60 58 51 48 44 42 8 7 6 PP3V3_S3 C 0.0 OF 36 1 73 .3V PLACE FILTERS NEAR CONNECTOR PLACE C4100. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.1UF 10% 2 6.2MM VOLTAGE=3.3V X5R 2 6 6.3V X5R 603 0.1UF 201 6.3V OMIT 1 C4108 1 C4107 1 C4109 1 C4110 33000PF 1 100K 2 R4104 1 6 PM_WLAN_EN_L 2 100K 1 C 72 7 6 1 SOT563 CRITICAL 2 G 55 51 42 41 37 25 7 6 42 41 9 6 5 G S 1 PM_SLP_S3_L SMC_ADAPTER_EN L4101 90-OHM-100MA 1210-4SM1 S 4 SYM_VER-1 PM_WLAN_EN_L2 6 70 36 24 6 OUT PCIE_E_D2R_N 1 4 PCIE_E_D2R_P 2 3 CRITICAL J4100 Q4103 70 36 24 6 SSM6N15FE PP3V3_S5 OUT 5% 1/20W MF 201 2 G 90-OHM-100MA 1210-4SM1 S 1 PM_WLAN_EN_L1 IN PCIE_CLK100M_MINI_P IN PCIE_CLK100M_MINI_N 1 7 6 D 3 3 BI BI 4 USB2_AIRPORT_P USB2_AIRPORT_N 1 3 2 PM_S4_STATE_L 69 6 69 6 USB2_AIRPORT_P_F USB2_AIRPORT_N_F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 33 34 R4101 7 6 7 6 SMB_AIRPORT_CONN_CLK SMB_AIRPORT_CONN_DATA 1 0 201 1/20W MF 5% 2 CK505_SRC_CLKREQ6_L PCIE_WAKE_L AIRPORT_RST_L OUT 6 7 29 IN 6 7 25 IN 6 7 28 SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA 1/20W R4102 201 MF 5% 1 0 2 BI 6 7 40 41 44 71 BI 6 7 40 41 44 71 B CRITICAL L4102 90-OHM-100MA 1210-4SM1 C4100 70 36 24 6 IN 1 PCIE_E_R2D_C_N 2 X5R 10% SYM_VER-1 0. SCALE SHT NONE 8 7 6 5 4 3 2 REV.01UF 10V 201 10% X5R SSM6N15FE SOT563 10UF 0.C4101 < 250 MILS FROM SB 6 24 36 70 APN:516S0580 MAKE_BASE=TRUE 6 24 36 70 MAKE_BASE=TRUE 6 24 MAKE_BASE=TRUE 6 24 36 70 MAKE_BASE=TRUE 36 70 Wireless M93 Connector A A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.0. INC.

0. SCALE SHT NONE 8 7 6 5 4 3 2 REV. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. USB. INC.0 OF 37 1 73 A . to RIO Hatch Assembly CRITICAL J4200 54102 F-ST-SM 63 7 6 C 63 7 6 HDMI_HOST DVI_HOST TMDS_TX_CONN_CLK_N TMDS_TX_CONN_CLK_P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 63 7 6 15 16 63 7 17 18 19 20 63 7 6 21 22 63 7 23 24 25 26 67 63 7 6 67 63 7 6 TMDS_TX_CONN_N<0> 6 TMDS_TX_CONN_P<0> TMDS_TX_CONN_N<1> 6 TMDS_TX_CONN_P<1> 63 7 6 63 7 6 69 39 7 6 69 39 7 6 TMDS_TX_CONN_N<2> TMDS_TX_CONN_P<2> USB2_EXTA_F_P USB2_EXTA_F_N 27 28 29 30 31 32 33 34 35 PP5V_S0_DVIPORT VGA_VSYNC VGA_HSYNC 38 39 40 6 7 63 TMDS_DDC_SDA TMDS_DDC_SCL CRITICAL PPBUS_G3H J4260 QT500166-L020 6 7 61 62 63 67 M-ST-SM 6 7 61 62 63 67 69 23 9 7 6 VGA_B 6 7 63 67 VGA_G 6 7 63 67 IN 69 23 9 7 6 IN 69 23 9 6 IN 55 51 42 41 36 25 7 6 VGA_R C 6 7 63 72 64 59 56 50 45 8 7 6 IN HDA_SYNC HDA_SDOUT HDA_RST_L PM_SLP_S3_L 6 7 63 67 TMDS_HTPLG 6 7 61 63 PP5V_S3_USB2_EXTA_F 6 7 39 72 36 37 Audio Connector 6 7 63 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HDA_SDIN0 OUT AUD_MIC_CLK AUD_MIC_DATA HDA_BIT_CLK 6 7 9 23 69 IN 6 7 60 OUT 6 7 60 IN 6 7 9 23 69 516S0350 B B 516S0632 Hatch and Audio Connectors A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.8 6 7 5 2 3 4 1 D D Micro DVI. 051-7230 B.

7K 69 38 23 6 1% 1/20W MF 2 201 IDE_PDIORDY 42 PP3V3_B_S0 1 6 8 38 47 51 61 62 63 R4402 100K B 2 24 6 IDE_RESET_L 5% 1/20W MF 201 1 2 5 B MC74VHC1G09 SC70 4 IDE_RESET_BUF_L B U4400Y 516S0594 6 38 A 3 3.3V GPIO54 is 5V tolerant. 051-7230 B. SCALE SHT NONE 8 7 6 5 4 3 2 REV. PATA HDD CONNECTOR A A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. INC.8 6 7 2 3 4 5 1 D D 63 62 61 51 47 38 8 6 PP3V3_B_S0 OMIT 1 C4400 10UF 20% 6.0.3V 2 X5R 603 CRITICAL J4400 AXK740327G F-ST-SM 41 69 38 23 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 69 23 6 15 16 69 23 6 17 18 69 23 6 19 20 69 23 21 22 23 24 25 26 27 28 29 30 NC31 32 69 23 6 33 34 69 23 35 36 NC 37 38 39 40 38 69 23 69 23 C 69 23 69 23 69 23 6 IDE_RESET_BUF_L 6 IDE_PDD<8> 6 IDE_PDD<9> 6 IDE_PDD<10> 6 IDE_PDD<11> IDE_PDD<12> IDE_PDD<13> IDE_PDD<14> 6 IDE_PDD<15> 6 IDE_PDIOW_L IDE_PDIORDY 6 IDE_IRQ14 69 38 23 6 69 38 23 IDE_PDA<2> 6 IDE_PDCS3_L IDE_PDD<7> IDE_PDD<6> IDE_PDD<5> IDE_PDD<4> IDE_PDD<3> IDE_IRQ14 R4400 1 6 23 69 10K 5% 1/20W MF 2 201 6 23 69 6 23 69 6 23 69 C 6 23 69 IDE_PDD<2> 6 23 69 IDE_PDD<1> 6 23 69 IDE_PDD<0> 6 23 69 IDE_PDDREQ 6 23 69 IDE_PDIOR_L 6 23 69 IDE_PDDACK_L 6 23 69 IDE_PDA<1> 6 23 69 IDE_PDA<0> 6 23 69 IDE_PDCS1_L 6 23 69 PP3V3_B_S0 62 61 51 47 38 8 6 63 R4401 1 4.0 OF 38 1 73 .

5A CONTINUOUS B B USB/SMC MUX USB2_MUXED_EXTA_P USB2_MUXED_EXTA_N 6 9 39 69 6 9 39 69 PP3V42_G3H 43 42 41 40 28 27 26 23 8 7 6 72 59 57 44 R4675 100 2 72 6 PP3V42_G3H_SMCUSBMUX_R 5% 1/20W MF 201 1 MIN_LINE_WIDTH=0.8 6 7 2 3 4 5 1 D D USB 2. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.3V 2 POLY B2-HF OMIT 1 ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS CRITICAL 100UF PP5V_S5 C LAYOUT NOTE:C4602 IS AN EMC BY-PASS CAP FOR J4200 6 5 GND 1 R4650 58 6 PM_SLP_S4_LS5V 6 EXTAUSB_OC_F_L 2 1K 5% 1/20W MF 201 1 EXTAUSB_OC_L 6 7 9 13 24 C4650 1 0.47UF 10% 6.1UF PLACE C4675 NEAR U4675 10K 10% 6.2 mm VOLTAGE=3.0 CONNECTOR CRITICAL PP5V_S3_USB2_EXTA_F L4602 MIN_LINE_WIDTH=0.0.3V 2 X5R 201 5% 1/20W MF 2 201 9 1 VCC SMC_RX_L 6 SMC_TX_L 43 42 41 69 24 9 6 69 24 9 6 D+ 3 D. SCALE SHT NONE 8 7 6 5 4 3 2 REV.2MM VOLTAGE=5V CONNECT TO RIO CONNECTOR J4200 6 7 37 69 10% 2 10V X5R 201 D4600 PP5V_S3_USB2_EXTA 6 67 7 37 39 72 37 39 72 6 7 37 69 RCLAMP0502B 3 2 1 CRITICAL 2 U4600 TPS2023DG4 C PP5V_S3_USB2_EXTA_F USB2_EXTA_F_N USB2_EXTA_F_P SYM_VER-1 0.3V X5R 201 2 603 69 39 9 6 USB2_MUXED_EXTA_N 1 4 69 39 9 6 USB2_MUXED_EXTA_P 2 3 1 IN_0 3 IN_1 SOI OUT_0 8 CRITICAL OUT_1 7 OUT_2 4 EN* OC* C4602 0.1UF 20% 2 6.6MM MIN_NECK_WIDTH=0.3V CERM-X5R 2 402 CURRENT LIMIT TO 1.0 OF 39 1 73 A .2 mm MIN_NECK_WIDTH=0. INC.5 1 D+A CRITICAL 7 D-A 43 42 41 6 U4675 PI3USB10LP USB2_EXTA_P USB2_EXTA_N 2 D+B 6 D-B TQFN SEL 10 8 OE* A 4 GND USB_DEBUGPRT_EN_L USB EXTERNAL CONNECTORS 6 41 SYNC_MASTER=M70 SEL=0 CHOOSE SMC SEL=1 CHOOSE USB SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. 051-7230 B.42V C4675 R4677 1 0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V FERR-120-OHM-3A CONNECT TO 5V S5 or S3 PER LAYOUT 0603 CRITICAL 72 58 56 55 54 51 27 8 7 6 C4610 1 C46131 C4612 10uF 90-OHM-100MA 1210-4SM1 10% 6.01UF SC-75 MIN_LINE_WIDTH=0.3V X5R L4600 20% 6.

051-7230 B.20 MM VOLTAGE=3.3V SM 1 B PP3V42_G3H 42 41 40 39 28 27 26 23 8 7 6 72 59 57 44 43 6 7 40 R4830 1 C4810 1M 5% 1/20W MF 201 2 0. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.2UF 10% 6.2mm VOLTAGE=3.3V 2 X5R 201 6 PP3V42_G3H_IPD_F 6 7 40 OMIT C4801 20% 6.0.01UF 42 41 40 7 6 10% 10V 2 X5R 201 G S 2 SMC_ONOFF_L CRITICAL L4813 600-OHM-300MA 42 41 40 39 28 27 26 23 8 7 72 59 57 44 6 PP3V42_G3H 43 1 PP3V42_G3H_IPD_F 6 2 MIN_LINE_WIDTH=0.20 MM VOLTAGE=5V 0402 1 7 40 72 1 C4812 0.2mm MIN_NECK_WIDTH=0.3V 2 X5R 201 516S0591 Power Button Inverter CRITICAL L4810 FERR-600-OHM-0.01UF NOTICE OF PROPRIETARY PROPERTY 10% 10V 2 X5R 201 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.1UF 40 7 72 40 7 6 PP5V_S0_KBDLED_F C4800 2.0 OF 40 1 73 .30 MM MIN_NECK_WIDTH=0.3V 2 CERM 402-LF CRITICAL J4800 51338-0249 F-ST-SM 25 26 41 7 6 C 71 44 41 36 7 6 BI 71 44 41 36 7 6 BI SMC_SYS_LED SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA R4831 LSOC_PRESS_H 57 42 2 10K 5% 1/20W MF 201 1 1 42 41 40 7 6 LSOC_PRESS_H_R SMC_ONOFF_L C4831 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 SMC_LID SMC_SYS_KBDLED 6 7 41 42 6 7 41 USB_IR_N USB_IR_P USB2_WSPRING_N USB2_WSPRING_P BI 6 7 9 24 69 BI 6 7 9 24 69 BI 6 7 9 24 69 BI 6 7 9 24 69 C 0.01UF 10% 10V 2 X5R 201 SMC_ONOFF_H 6 Q4830 SSM3K15FV CRITICAL D 3 42 57 Inverted to drive SMC_RESET logic SOD-VESM L4812 600-OHM-300MA 63 53 52 51 47 43 27 22 8 7 6 72 PP5V_S0 1 PP5V_S0_KBDLED_F 6 2 MIN_LINE_WIDTH=0.20 MM MIN_NECK_WIDTH=0.42V 0402 A 1 IPD Connector 7 40 A C4813 0. SCALE SHT NONE 8 7 6 5 4 3 2 REV.8 6 7 2 3 4 5 1 D IPD Connector D PP5V_S3_TOPCASE_F 1 1 0.1UF 10% 6. INC.5A B 72 60 58 8 7 6 PP5V_S3 1 PP5V_S3_TOPCASE_F 2 MIN_LINE_WIDTH=0.

2 3 4 5 1 Unused pins designed as outputs can be left floating.7 5% 1/20W MF 201 2 72 6 PP3V3_S5_SMC_AVCC MIN_LINE_WIDTH=0. those designated as inputs require pull-ups.1UF 10% 6.1UF 2 10% 6.3V X5R 201 PLACEMENT_NOTE=Place C4907 close to U4900 pin E1 6 SMC_VCL R4999 1 4. INC.1UF 6 7 44 46 71 P50 P51 P52 C4900 L11 52 51 28 6 B12 A13 A12 B13 D11 C13 C12 D10 E1 NC_SMC_RSTGATE_L 9 B1 M1 H10 PM_LAN_ENABLE OUT M12 25 6 B 6 42 45 53 59 6 42 NC_BATT_ISET 9 NC_SMC_BATT_VSET 9 NC_SYS_ISET 9 NC_SMC_SYS_VSET 9 NC_SMC_PG0 9 SMC_SMS_INT IN (OC) SMBUS_SMC_BSA_SDA BI 6 7 44 50 59 71 (OC) SMBUS_SMC_BSA_SCL BI 6 7 44 50 59 71 (OC) SMBUS_SMC_A_S3_SDA BI 6 7 36 40 44 71 (OC) SMBUS_SMC_A_S3_SCL BI 6 7 36 40 44 71 (OC) SMBUS_SMC_B_S3_SDA BI 6 7 44 60 (OC) SMBUS_SMC_B_S3_SCL BI SMC_PROCHOT SMC_THRMTRIP NC_SMC_FWE 9 NC_ALS_GAIN 9 NC_SMC_ENRGYSTR_LDO_PGOOD 6 7 44 60 OUT 6 42 OUT 6 42 OUT 6 48 9 SMS_ONOFF_L SMC NOTE: SMS Interrupt can be active high or low.47UF 0.3V X5R 201 2 C4905 0. SYNC_MASTER=M70 If SMS interrupt is not used.25 MM MIN_NECK_WIDTH=0.1UF 0.3V CERM-X5R 402 VCL AVREF U4900 1 E5 NC 5% 1/20W MF 201 LGA SMC_RESET_L D3 RES* 42 6 SMC_XTAL 42 6 SMC_EXTAL A3 A2 XTAL EXTAL IN MD1 MD2 D1 H1 NMI E3 ETRST H3 AVSS L9 (DEBUG_SW_1) 9 NC_SMC_PA0 (DEBUG_SW_2) 9 NC_SMC_PA1 B PM_SYSRST_L (OC) OUT USB_DEBUGPRT_EN_L (OC) 16 6 BI PM_EXTTS_L<0> (OC) 16 6 BI PM_EXTTS_L<1> (OC) 50 42 7 6 BI SYS_ONEWIRE (OC) 25 6 OUT PM_BATLOW_L 25 6 OUT SMC_RUNTIME_SCI_L 42 6 IN SMC_ODD_DETECT 28 25 6 OUT 39 6 (DEBUG_SW_3) 9 47 6 9 NC_ISENSE_CAL_EN 9 NC_SMC_EXCARD_CP 9 NC_SMC_EXCARD_PWR_EN 9 NC_EXCARD_OC_L 9 NC_SMC_GFX_OVERTEMP_L OUT 47 6 NC_SMC_PB0 SMC_FAN_0_CTL 9 NC_SMC_FAN_1_CTL 9 NC_SMC_FAN_2_CTL 9 NC_SMC_FAN_3_CTL SMC_FAN_0_TACH IN 9 NC_SMC_FAN_1_TACH 9 NC_SMC_FAN_2_TACH 9 NC_SMC_FAN_3_TACH 48 6 IN SMS_X_AXIS 48 6 IN SMS_Y_AXIS 48 6 IN SMS_Z_AXIS A 9 NC_SMC_ANALOG_ID 9 NC_SMC_TEST_DAC1 9 NC_SMC_TEST_DAC2 9 NC_SMC_TEST_DAC3 9 NC_ALS_RIGHT N3 N1 M3 M2 N2 L1 K3 L2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 B8 C9 B9 A10 C10 B10 C11 A11 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 (OC) G11 G13 F12 H13 G10 G12 H11 J13 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 M10 N9 K10 L8 M9 N8 K9 L7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 U4900 HS82117 LGA (2 OF 3) 1 K1 J3 K2 J1 K4 K5 SMC_CASE_OPEN IN 6 42 SMC_TCK IN 6 42 43 SMC_TDI IN 6 42 43 SMC_TDO OUT 6 42 43 SMC_TMS IN 6 42 43 PF1 PF2 PF3 PF4 PF5 PF6 PF7 N5 M6 L5 M5 N4 L4 M4 SMC_SYS_LED OUT 6 7 40 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 M8 N7 K8 K7 K6 N6 M7 L6 PH0 PH1 PH2 PH3 PH4 PH5 E2 F2 J2 A4 B3 C4 NC_SMC_PF0 2 R4902 IN 6 7 40 42 6 9 48 5% 1/20W MF 2 201 2 SMC_MD1 IN 6 43 SMC_NMI IN 6 43 SMC_TRST_L IN 6 43 R4998 10K 5% 1/20W MF 201 2 5% 1/20W MF 201 2 1 GND_SMC_AVSS SMC_LID 10K XW4900 SM 9 SMC_PF3 1 10K D2 L3 F10 B11 C5 PE0 PE1 PE2 PE3 PE4 PF0 R4904 6 SMC_KBC_MDE VSS OMIT 1 10K (3 OF 3) 43 42 6 C 2 R4905 NC HS82117 PLACEMENT_NOTE=Place R4999 close to U4900 pin M12 PLACEMENT_NOTE=Place C4900 close to U4900 pin M12 1 0.0.20 MM VOLTAGE=3. SCALE SHT NONE 8 7 6 5 4 3 2 REV.3V 1 C4907 2 10% 6. 051-7230 B.8 6 7 NOTE: Unused pins have "SMC_Pxx" names. rename net accordingly. pull up to SMC rail.0 OF 41 1 73 A . 56 42 6 IN ALL_SYS_PWRGD IN RSMRST_PWRGD 9 D NC_SMC_P14 25 6 OUT PM_RSMRST_L 52 6 OUT IMVP_VR_ON OUT PM_PWRBTN_L 25 6 9 42 6 9 NC_SMC_P20 9 NC_SMC_P21 9 NC_SMC_P22 9 NC_SMC_P23 OUT NC_SMC_BATT_TRICKLE_EN_L OUT SMC_BATT_CHG_EN 9 NC_SMC_P26 9 NC_SMC_P27 43 23 6 BI LPC_AD<0> 43 23 6 BI LPC_AD<1> 43 23 6 BI LPC_AD<2> 43 23 6 BI LPC_AD<3> 43 23 6 IN LPC_FRAME_L 28 6 IN SMC_LRESET_L IN PCI_CLK33M_SMC BI INT_SERIRQ 71 30 6 43 25 6 71 48 44 6 9 NC_SMC_GFX_THROTTLE_L 9 NC_SMC_P41 SMBUS_SMC_MGMT_SDA BI C 40 7 6 9 NC_SMC_P43 9 NC_SMC_P44 9 NC_SMC_ENRGYSTR_LDO_EN 9 NC_SMC_P46 SMC_SYS_KBDLED OUT 43 42 41 39 6 OUT SMC_TX_L 43 42 41 39 6 IN SMC_RX_L BI SMBUS_SMC_0_S0_SCL 71 46 44 7 6 (OC) (OC) P10 P11 P12 P13 P14 P15 P16 P17 D13 E11 D12 F11 E13 E12 F13 E10 OMIT U4900 P60 P61 P62 P63 P64 P65 P66 P67 L13 K12 K11 J12 K13 J10 J11 H12 SMC_PM_G2_EN OUT 6 56 58 SMC_ADAPTER_EN OUT 6 9 36 42 P20 P21 P22 P23 P24 P25 P26 P27 P70 P71 P72 P73 P74 P75 P76 P77 N10 M11 L10 N11 N12 M13 N13 L12 A9 D9 C8 B7 A8 D8 D7 D6 P30 P31 P32 P33 P34 P35 P36 P37 P80 P81 P82 P83 P84 P85 P86 A7 B6 C7 D5 A6 B5 C6 SMC_WAKE_SCI_L D4 A5 B4 A1 C2 B2 C1 C3 P40 P41 P42 P43 P44 P45 P46 P47 P90 P91 P92 P93 P94 P95 P96 P97 J4 G3 H2 G1 H4 G4 F4 F1 G2 F3 E4 HS82117 LGA (1 OF 3) NC_SMC_P62 9 NC_SMC_P64 9 PM_LAN_PWRGD IN 6 42 IN 6 42 SMC_BATTPACK_STAT IN 6 42 SMC_ACIN_VSENSE IN 6 45 SMC_GPU_ISENSE IN 6 53 SMC_GPU_VSENSE IN 6 45 SMC_DCIN_ISENSE IN 6 59 SMC_PBUS_VSENSE IN 6 45 SMC_BATT_ISENSE IN 6 59 SMC_PBUS_ISENSE IN 6 59 SMC_PROCHOT_3_3_L NC_SMC_P67 OUT 6 7 13 25 OUT 6 25 43 IN 6 25 43 9 PM_CLKRUN_L PM_SUS_STAT_L (OC) D 9 NC_SMC_P81 (OC) SMC 9 NC_SMC_P63 72 42 6 43 42 40 39 28 27 26 23 8 7 6 72 59 57 44 PP3V3_S5_AVREF_SMC PP3V42_G3H SMC_TX_L OUT 6 39 41 42 43 C4902 SMC_RX_L IN 6 39 41 42 43 22UF SMBUS_SMC_MGMT_SCL BI SMC_ONOFF_L IN 6 7 40 42 SMC_BC_ACOK IN 6 42 50 59 SMC_BS_ALRT_L IN 6 7 42 50 PM_SLP_S3_L IN 6 7 25 36 37 42 51 55 PM_S4_STATE_L IN 6 25 36 58 PM_SLP_S5_L IN 6 25 42 SMC_SUS_CLK IN 6 42 SMBUS_SMC_0_S0_SDA BI 20% 6.3V X5R 201 10% 6.3V X5R 201 AVCC VCC OMIT 10% 6.3V CERM 805 6 44 48 71 1 2 1 2 C4903 1 1 C4904 0. SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.

8 6 7 2 3 4 5 SMC Reset Button / Brownout Detect 1 SMC 1.05V to 3.3V to 1.0.3V 2 X5R 603 470K 2 GND_SMC_AVSS Q5002 6 41 42 45 53 59 MIN_LINE_WIDTH=0.01UF 2 SMC AVREF Supply 42 41 40 39 28 27 26 23 8 7 6 72 59 57 44 43 VR5065 REF3333 PP3V42_G3H IN OUT CRITICAL GND_SMC_AVSS PP3V3_S5_AVREF_SMC 6 SOT23-3 1 2 MIN_LINE_WIDTH=0. SMC_TMS SMC_TDO SMC_TDI SMC_TCK PM_LAN_PWRGD 50 41 7 6 S 4 R5094 1 R5095 1 R5080 1 R5081 1 41 6 SOT563 G RSMRST_PWRGD SMC_ONOFF_L SMC_TX_L SMC_RX_L 41 6 D 3 SSM6N15FE 5 PP3V42_G3H 6 41 43 PP3V3_S3 10V 2 X5R 201 PP1V05_S0 470 OUT 3 0.0MM Place on bottom side near board edge 41 6 2 4 Y5020 20MHZ Silk: "PWR BTN" 5% 25V NPO 201 3 CRITICAL R5010 5% 1/16W MF-LF 2 402 R5078 1 C5020 41 6 1 0 R5073 SMC_LID SMC Crystal Circuit C5021 1 NOSTUFF SMC_ONOFF_L OUT SMC_BC_ACOK 59 50 41 6 41 40 7 6 Debug Power Button SMC_ODD_DETECT 41 6 C R5097 1 R5085 1 R5086 1 R5087 1 R5090 1 R5091 1 R5082 1 R5083 1 R5049 1 R50841 SMC_PF3 50 42 41 7 6 Q5030 will pull down SMC_MANUAL_RST_L in the event of a keyboard SMC Reset generated when left shift.option.4 MM MIN_NECK_WIDTH=0.0 OF 42 1 73 A .2 MM VOLTAGE=3.2 MM VOLTAGE=0V SUS_CLK_SB 1 0 2 6 45 59 ENABLE VSENSE IN S0 ONLY OUT SYNC_MASTER=M70 IN THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.4 MM MIN_NECK_WIDTH=0.3V CERM-X5R 402 6 41 42 45 53 59 41 72 GND 3 10% 10V X5R 201 SCALE SHT NONE 5 4 3 2 REV. R5011 CLOSE TO SB 8 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY SOT563 55 51 41 37 36 25 7 6 SMC_SUS_CLK SMC SUPPORT D 6 SSM6N15FE 2 G R5011 25 6 PBUS_SMC_VSENSE_EN_L 1% 1/20W MF 201 10uF 20% 2 6.47UF 10% A R5075 2 10V X5R 201 72 59 55 54 53 52 8 7 6 PPBUS_R_G3H 1 6.01UF 10% PP3V3_A_S0 1K U5000 5 NOSTUFF R5000 VDD 6.05V Level Shifting 2 5% 25V NPO 201 APN: 197S0231 CPU_PROCHOT_L 6 Q5001 Q5001 D 6 SSM6N15FE B PM_THRMTRIP_L 6 10 42 52 66 10 16 23 66 D 3 SSM6N15FE SOT563 B SOT563 Battery Pack Status 2 G 41 6 S 1 5 G SMC_PROCHOT 41 6 S 4 SMC_THRMTRIP 50 42 41 7 6 SMC_BS_ALRT_L R5098 1 2 0 SMC_BATTPACK_STAT 1 6 41 C5098 0. 051-7230 B.5X2. INC.3V Level Shifting PP3V42_G3H 42 41 40 39 28 27 26 23 8 7 6 72 59 57 44 43 C5000 1 D SMC_MANUAL_RST_L NC 1 Silk: "SMC RST" Place R5001 on bottom side near board edge R5001 C5001 1 0 5% 1/16W MF-LF 2402 4 RN5VD30A-F SOT23-5 OUT CD NC GND 5% 1/20W MF 2 201 19 18 14 13 12 11 10 8 7 6 72 54 30 27 26 23 21 SMC_RESET_L 1 56 41 6 42 41 40 7 6 Q5030 43 41 39 6 D 6 43 41 39 6 SSM6N15FE SOT563 43 41 6 43 41 6 2 57 40 G S 1 LSOC_PRESS_H 43 41 6 43 41 6 SMC_MANUAL_RST_L1 6 Q5030 57 40 6 SMC_ONOFF_H SYS_ONEWIRE SMC_BS_ALRT_L D 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 5% 1/20W MF 2 201 R5070 1 6 7 8 23 26 27 28 39 40 41 42 43 44 57 59 72 3.1UF 10% 15PF SMC_EXTAL 1 SMC 3.and control and the power button is depressed.3V 2 X5R 201 64 63 60 53 52 24 23 22 21 19 16 13 8 7 6 51 46 44 30 29 28 27 26 25 1 CRITICAL2 0.3V TO PBUS LEVEL SHIFTING C5067 0.3K 2 5% 6 1/20W MF 201 2 Q5077 BC847BV-X-F SOT563 CPU_PROCHOT_L_R 1 C 100K R5006 1 2 100K R5092 1 2 R5096 1 R5093 1 PM_SLP_S5_L 6 25 41 10K SMC_CASE_OPEN 6 41 2 10K SMC_ADAPTER_EN 6 9 36 41 2 10K SMC_BATT_CHG_EN 6 41 15PF SMC_XTAL 1 2 6 7 40 41 42 SM-2.3K 5% 1/20W MF 2 201 6 7 8 36 44 48 51 58 60 72 100K 100K 10K 100K 6 41 SMC_PROCHOT_3_3_L 3 5 6 Q5077 BC847BV-X-F SOT563 CPU_PROCHOT_BUF 4 R5071 10K 10K 10K 10K 10K 10K 2. THE POSSESSOR AGREES TO THE FOLLOWING S 1 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE PM_SLP_S3_L II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 6 41 5% 1/20W MF 201 SIZE 7 6 DRAWING NUMBER D APPLE INC.01UF 10% OMIT 1 C5065 C5066 1 0.3V 1 3.0K 470K 10K 10K 1 66 52 42 10 6 CPU_PROCHOT_L 6 3.

INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. SCALE SHT NONE 8 7 6 5 4 3 2 REV.3V X5R 201 U5150 49 6 OUT SPI_INT_CE_L<0> 1 B1 6 25 41 IN LPCPLUS C5150 0.0.8 6 7 2 3 4 5 1 D D LPC+SPI Connector C SPI_CS MUX J5100 LPCPLUS 1 41 23 6 BI Place R5101 close to J5100 R5101 69 49 6 IN SPI_A_SI_R 1 47 5% 1/20W MF 201 2 LPC_AD<0> LPC_AD<1> SPI_EXT_A_SI_R SPI_SO LPC_FRAME_L IN PM_CLKRUN_L OUT SMC_TMS OUT DEBUG_RESET_L IN SMC_TDO OUT SMC_TRST_L IN SMC_MD1 OUT SMC_TX_L IN 6 69 49 24 6 41 23 6 41 25 6 42 41 6 28 6 42 41 6 41 6 41 6 42 41 39 6 OUT 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 33 34 PCI_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3> BOOTROM_OVR_EN_L SPI_EXT_A_SCLK_R SPI_EXT_CE_L<0> INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L FRANKCARD_GPIO IN BI 6 23 41 BI 6 23 41 IN R5102 6 30 71 6 23 25 43 1 47 2 SPI_A_SCLK_R 5% 1/20W MF 201 IN 6 25 41 IN 6 41 42 IN 6 41 42 OUT 6 41 42 OUT 6 41 OUT 6 39 41 42 OUT 6 25 10% 6.1UF 2 NC7SB3157P6X 3 B0 BI C VCC 6 49 69 6 6 1 5 BI 1 20K 5% 1/20W MF 201 2 Place R5102 close to J5100 6 7 8 23 26 27 28 39 40 41 42 43 44 57 59 72 MICROPAK CRITICAL LPCPLUS S 6 BOOTROM_OVR_EN_L IN 6 23 25 43 A 4 SPI_CE_L<0> IN 6 49 69 GND 2 41 23 6 R5151 M-ST-SM 31 32 PP3V42_G3H PP5V_S0 24 6 7 8 25 26 27 28 36 44 49 51 56 57 58 60 72 PP3V3_S5 55909-0374 42 41 40 39 28 27 26 23 8 7 6 72 59 57 44 43 63 53 52 51 47 40 27 22 8 7 6 72 PP3V42_G3H Pullup to internal ROM on S5 CRITICAL LPCPLUS Place halfway between SPIROM and J5100 516S0573 B B NO STUFF R5152 1 15 2 SPI_CE_R_L<1> IN 6 24 69 5% 1/20W MF 201 Place within 0.5" of SB LPC+SPI Debug Connector A SYNC_MASTER=M70 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.0 OF 43 1 73 A . 051-7230 B.

2K U4900 (MASTER) MAKE_BASE=TRUE SMBUS_SMC_0_S0_SDA 71 PP3V3_S3 SMC HEAT SPREADER 8.2K 2 5% 1/20W MF 201 Clock Chip SMC SLG2AP101: U2900 (Write: 0xD2 Read: 0xD3) U4900 (MASTER) SMBUS_SB_SCL MAKE_BASE=TRUE SMBUS_SB_SDA SMC "0" SMBus Connections PP3V3_A_S0 ICH8-M SMBUS_SB_SDA SMBUS_SB_SDA MAKE_BASE=TRUE 2 3 4 5 6 25 29 44 69 46 44 41 7 6 71 6 25 29 44 69 46 44 41 7 6 71 SMC "A" SMBus Connections NOTE: SMC RMT bus remains powered and may be active in S3 state PP3V3_A_S0 72 60 58 51 48 44 42 36 8 7 6 R5250 1 8.2K 2 2 5% 1/20W MF 201 J4800 Front ALS (Write: 0x53 Read: 0x52) TMP106 (Write: 0x93 Read: 0x92) SMBUS_SMC_A_S3_SCL 71 MAKE_BASE=TRUE 44 41 40 36 7 6 SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL 44 71 6 7 36 40 41 SMBUS_SMC_A_S3_SDA 44 71 6 7 36 40 41 MAKE_BASE=TRUE D M93 Wireless Card CPU Temp J4100 TMP401: U5520 (Write: 0x98 Read: 0x99) SMBUS_SMC_0_S0_SCL 71 6 7 41 44 46 SMBUS_SMC_0_S0_SDA 71 6 7 41 44 46 (Write: 0x90 Read: 0x91) SMBUS_SMC_A_S3_SCL 44 71 6 7 36 40 41 SMBUS_SMC_A_S3_SDA 44 71 6 7 36 40 41 Power Supply Temp TMP106: U5550 (Write: 0x98 Read: 0x99) SMBUS_SMC_0_S0_SCL 71 6 7 41 44 46 SMBUS_SMC_0_S0_SDA 71 6 7 41 44 46 SMC "Battery A" SMBus Connections 42 41 40 39 28 27 26 23 8 7 6 72 59 57 43 PP3V42_G3H R52801 SMC C SMC "B" SMBus Connections 50 44 41 7 6 71 59 72 60 58 51 48 44 42 36 8 7 6 PP3V3_S3 50 44 41 7 6 71 59 R5260 1 SMC 8.2K J9050 (Write: 0x52 Read: 0x53) 5% 1/20W MF 2 201 ICH8-M ME SMBus Connections B R5281 5% 1/20W MF 201 2 Top ALS 8.0. SCALE SHT NONE 8 7 6 5 4 3 2 REV.2K U4900 (MASTER) 100K 5% 1/20W MF 2 201 48 44 41 6 71 SMBUS_SB_ME_SCL MAKE_BASE=TRUE SMBUS_SB_ME_SDA R5230 1 SMC 1 48 44 41 6 71 SMBUS_SB_ME_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 5% 1/20W MF 201 2 1 SMS R5231 8.2K U4900 (MASTER) 5% 1/20W MF 201 2 60 44 41 7 6 SMBUS_SMC_B_S3_SCL 60 44 41 7 6 60 44 41 7 6 SMBUS_SMC_B_S3_SDA 60 44 41 7 6 1 R5261 SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_B_S3_SCL SMBUS_SMC_B_S3_SDA MAKE_BASE=TRUE SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA 71 MAKE_BASE=TRUE 59 50 44 41 7 6 MAKE_BASE=TRUE C 6 7 41 44 50 59 71 6 7 41 44 50 59 71 Charger SMBUS_SMC_B_S3_SCL 6 7 41 44 60 SMBUS_SMC_BSA_SCL SMBUS_SMC_B_S3_SDA 6 7 41 44 60 SMBUS_SMC_BSA_SDA 6 7 41 44 50 59 71 6 7 41 44 50 59 71 SMC "Management" SMBus Connections PP3V3_S3 PP3V3_S5 R52101 ICH8-M 100K U2300 (MASTER) 69 44 25 6 J6950 (Write: 0x?? Read: 0x??) 5% 1/20W MF 2 201 U7900 (Write: 0x?? Read: 0x??) 72 60 58 51 48 44 42 36 8 7 6 69 44 25 6 71 59 50 44 41 7 6 Battery 2.0 OF 44 1 73 A .2K B KXPS5-2050: U5900 (Write: 0x30 Read: 0x31) 5% 1/20W MF 2 201 SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA SMBUS_SMC_MGMT_SDA MAKE_BASE=TRUE MAKE_BASE=TRUE 48 6 41 44 71 48 6 41 44 71 MAKE_BASE=TRUE SMBUS CONNECTIONS A SYNC_MASTER=M70 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. 051-7230 B. INC.8 6 7 ICH8-M SMBus Connections 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 D 44 29 25 6 69 SMBUS_SB_SCL 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 R52001 8.2K U4900 (MASTER) 5% 1/20W MF 201 2 SMBUS_SB_ME_SCL R5211 8.2K U2300 (MASTER) 44 29 25 6 69 5% 1/20W MF 201 SMBUS_SB_SCL 2 1 R5201 8.2K 1 5% 1/20W MF 201 SMBUS_SMC_A_S3_SCL 44 SMBUS_SMC_A_S3_SDA 71 41 40 36 7 6 IPD 8.2K 5% 1/20W MF 201 SMBUS_SMC_0_S0_SCL 71 46 44 41 7 6 2 1 R5251 2 J5500 5% 1/20W MF 201 SMBUS_SMC_0_S0_SCL 46 44 41 7 6 SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA R52701 SMBUS_SMC_0_S0_SDA MAKE_BASE=TRUE 71 6 7 41 44 46 41 40 36 7 6 71 44 71 6 7 41 44 46 41 40 36 7 6 71 44 1 R5271 8.2K MAKE_BASE=TRUE 49 43 36 28 27 26 25 24 8 7 6 72 60 58 57 56 51 1 2.

INC. SCALE SHT NONE 8 7 6 5 4 3 2 REV.3V CERM-X5R 402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE GND_SMC_AVSS II NOT TO REPRODUCE OR COPY IT 6 41 42 45 53 59 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART PLACE C5350 NEAR SMC SIZE DRAWING NUMBER D APPLE INC.22UF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.C5310 NEAR SMC D 3 PPBUS_G3H S 72 64 59 56 50 37 8 7 6 2 PBUS VOLTAGE SENSE 6 NOMINAL 8.3V 2 CERM-X5R 402 GND_SMC_AVSS 6 41 42 45 53 59 PLACE C5300 NEAR SMC C C GPU VOLTAGE SENSE R5310 72 65 53 22 18 8 7 6 4.0V SMC_PBUS_VSENSE R5300 and R5301 VALUES CHOSEN FOR RC FILTER @ 4.53KOHM THEVENIN RESISTANCE R5300 1 27.0 OF 45 1 73 A .4V PBUS = 3.53K2 PPVCORE_S0_NB_GFX SMC_GPU_VSENSE 1 1% 1/20W MF 201 1 6 41 C5310 0.98K 1% 1/20W MF 2 201 1 SYNC_MASTER=M70 41 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY C5350 0.4K 1% 1/20W MF 2 201 SMC_ACIN_VSENSE 6 R5301 1 5.0V SMC_PBUS_VSENSE PBUS_S0_SMC_VSENSE Q5350 R5350 and R5351 VALUES CHOSEN FOR RC FILTER @ 4.22UF 10% 6.7K 1% 1/20W MF 2 201 Voltage Sensors PBUS_SMC_VSENSE_EN_L DRIVEN LOW IN S0 SMC_PBUS_VSENSE 6 R5351 1 6.53KOHM THEVENIN RESISTANCE SSM3J15FV G SOT-723 ON SMC SUPPORT PAGE 59 42 6 A 1 470K PULLUP R5350 1 12.22UF 10% 2 6.36K 1% 1/20W MF 2 201 1 41 C5300 0.0. 051-7230 B.3V CERM-X5R 402 B GND_SMC_AVSS B 6 41 42 45 53 59 PLACE R5310.5V + 10% ACIN = 3.8 7 6 3 4 5 2 1 ACIN VOLTAGE SENSE D D 72 59 6 PPVDCIN_G3H_PRE MAX 16. THE POSSESSOR AGREES TO THE FOLLOWING 10% 2 6.

3V 2 X5R 201 5% 1/20W MF 2 201 R5525 66 10 6 OUT CPU_THERMD_P 1 499 PLACE C5522 NEAR U5520 VDD 1 R5526 IN CPU_THERMD_N 1 C5520 8 470PF (TO CPU INTERNAL THERMAL DIODE) 66 10 6 5% 1/20W MF 2 201 2 1% 1/20W MF 201 499 10K VDD 10% 2 16V X5R-X7R 201 CRITICAL 6 2 6 THRM_CPU_DXP THRM_CPU_DXN 1 DXP 2 DXN 1% 1/20W MF 201 U5520 TMP421 SOT23-8 A0 4 THRM_CPU_ALERT_L A1 3 6 THRM_CPU_THM_L SCL 7 SDA 6 SMBUS_SMC_0_S0_SCL BI SMBUS_SMC_0_S0_SDA BI ADDR= 1001 100B 6 7 41 44 46 71 6 7 41 44 46 71 GND 1. ROUTE DXP AND DXN DIFFERENTIALLY 2. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. 5 MIL TRACE WIDTHS AND 5 MIL SPACING BETWEEN THE GAURD 5 (Write: 0x9E Read: 0x9F) B B LOCAL TEMP NEAR POWER SUPPLIES PP3V3_A_S0 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 C5550 1 0.0. INC.0 OF 46 1 73 A . SCALE SHT NONE 8 7 6 5 4 3 2 REV.1UF 10% 6. 051-7230 B.3V 2 X5R 201 5 V+ U5550 HPA00330AI SOT563 71 46 44 41 7 6 71 46 44 41 7 6 BI SMBUS_SMC_0_S0_SDA 6 SDA BI CRITICAL 3 SMBUS_SMC_0_S0_SCL 1 SCL ALERT A ADD0 4 TEMPERATURE SENSORS SYNC_MASTER=M70 GND 2 (Write: 0x90 Read: 0x91) SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR 3.1UF 10K 10% 6.8 6 7 2 3 4 5 1 REMOTE TEMP AT HEAT SPREADER D D CRITICAL J5500 SM04B-SURK-LF F-RT-SM 5 1 2 SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA PP3V3_A_S0 3 4 BI BI 4471 6 7 41 4641 44 46 71 6 7 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 6 APN:518S0354 CPU THERMAL DIODE C C 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 PP3V3_A_S0 C5522 1 R5520 1R5521 1 0.

SCALE SHT NONE 8 7 6 5 4 3 2 REV. INC.8 7 6 4 5 3 2 1 D D FAN CONNECTOR C C PP5V_S0 PP3V3_B_S0 63 53 52 51 43 40 27 22 8 7 6 72 63 62 61 51 38 8 6 R5660 1 47K 5% R5665 41 6 1 47K2 SMC_FAN_0_TACH 7 6 1/20W MF 201 CRITICAL J5600 SM04B-SURK-LF NC 2 F-RT-SM 5 1 FAN_RT_TACH 2 5% 1/20W MF 201 3 4 NC 5V DC TACH MOTOR CONTROL GND 6 R5661 1 Q5660 3 SMC_FAN_0_CTL D SOD-VESM 2 B 41 6 518S0354 SSM3K15FV G 2 S 1/20W MF 201 1 100K 5% 7 6 FAN_RT_PWM B Fan SYNC_MASTER=M70 A SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. 051-7230 B.0 OF 47 1 73 A . THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.0.

3V 2 X5R 201 R5903 100K 5% 1/20W MF 2 201 Desired orientation when placed on board bottom-side: Top-through View +Y B 1 +Y +X 6 41 OUT SMBUS_SMC_MGMT_SDA BI 10% 2 6. 0x33 Alias SCL/SDA to GND if using analog outputs only B +Z (up) 6 41 OUT 6 41 OUT 6 9 41 6 41 44 71 1 1 C5901 1 C5902 33000PF 10% 6.3V X5R 201 Package Top OUT SMC_SMS_INT FF/MOT 11 SDA/SDO 4 33000PF Desired orientation when placed on board top-side: 1 SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS X 7 Y 8 Z 9 GND 10 R5902 I2C addresses: C 10% 2 6. SCALE SHT NONE 8 7 6 5 4 3 2 REV.0 OF 48 1 73 A . INC.3V 2 X5R 201 1 C5903 33000PF 10% 6. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. 0x31 ADDR high => 0x32.8 6 7 2 3 4 5 1 D D SUDDEN MOTION SENSOR APN:338S0354 PP3V3_S3 SMS_MOT_EN R59001 C 1 1 R5901 10K 0 5% 1/20W MF 201 2 5% 1/20W MF 2 201 41 6 BI IN U5900 KXPS5-2050 SMBUS_SMC_MGMT_SCL SMS_ONOFF_L 6 SMS_MOT_EN SMS_MOT_DIS 2 3 5 6 12 1 CRITICAL CS* ADDR/SDI SCL/SCLK ENABLE MOT_ENABLE 0 5% 1/20W MF 2 201 ADDR low => 0x30.3V X5R 201 VDD LGA 71 44 41 6 C5900 0. 051-7230 B.1UF 1 13 14 72 60 58 51 44 42 36 8 7 6 +X +Z (dn) Sudden Motion Sensor (SMS) A SYNC_MASTER=M76_MLB SYNC_DATE=01/12/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.0.

THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. 051-7230 B.7mm of U2300 PLACEMENT_NOTE=Place R6191 within 12.7mm of U6100 PLACEMENT_NOTE=Place R6181 within 12.8 6 7 3 4 5 2 1 SPI ROM D D 44 43 36 28 27 26 25 24 8 7 6 PP3V3_S5 72 60 58 57 56 51 R6100 1 3.0. There is a 10K pullup on SPI_INT_CE_L<0> at the mux output. There is an option to connect SPI_INT_CE_L<0> directly to SPI_CE_L<0> B B SPI ROMs A SYNC_MASTER=WFERRY SYNC_DATE=04/26/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.0 OF 49 1 73 A .7mm of U2300 PLACEMENT_NOTE=Place R6193 within 12.3K 5% 1/20W MF 201 1 R6101 3. SCALE SHT NONE 8 7 6 5 4 3 2 REV.7mm of U6100 PLACEMENT_NOTE=Place R6190 within 12.7mm of U2300 OUT 6 43 69 OUT 6 43 69 OUT 6 43 69 TO DEBUG CONNECTOR note: mux for CE_L<0> on debug connector page.7mm of U6100 SPI_A_INT_HOLD_L 7 HOLD* VSS 4 C THM PAD 9 PLACEMENT_NOTE=Place R6180 within 12.3K 2 2 5% 1/20W MF 201 C6100 69 24 6 IN 1 15 2 R6180 1 SPI_A_SI_R 5% 1/20W MF 201 69 24 6 IN SPI_SCLK_R 1 SPI_CE_R_L<0> 1 R6181 47 1 SPI_A_SCLK_R 15 2 2 6 SPI_A_INT_SI 5D 6 SPI_A_INT_CLK 6C 5% 1/20W MF 201 SPI_CE_L<0> 43 6 IN U6100 R6114 SPI_INT_CE_L<0> 6 Q2 69 6 SPI_A_SO_R M25P32 1 15 5% 1/20W MF 201 VFQFPN 1 S* 6 5% 1/20W MF 201 C 8 VCC CRITICAL 15 2 2 2 R6190 5% 201 1/20W MF IN 47 5% 1/20W MF 201 R6191 69 24 6 10% 6.1UF R619x close to SB 2 SPI_SO OUT 6 24 43 69 SPI_SO also driven by debug card OMIT SPI_A_INT_WP_L 3 W*/VPP PLACEMENT_NOTE=Place R6114 within 12.3V X5R 201 R618x close to U6100 R6193 SPI_SI_R 1 0. INC.

3 mm MIN_NECK_WIDTH=0.2 MM 1% 1/16W MF-LF 2 402 6 402 3 72 6 G D SSM6N15FE SOT563 1 SYS_ONEWIRE_BILAT G 5 Q6920 10% 50V 2 CERM 402 ADAPTER_SENSE 6 C6907 2 5% 2 1/16W MF-LF 100K 5% 1/16W MF-LF 402 2 6 SMC_BC_ACOK_ONEWIRE_R 47K R6911 3 D SYS_ONEWIRE6 D 3 R6904 2 0. SCALE SHT NONE 8 7 6 5 4 3 2 REV.3K OneWire OVP 1 S SOT-723 6 VOLTAGE=18.0.001UF 4 S 42 41 7 6 Q6910 SSM6N15FE SOT563 1 6 ONEWIRE_PWR_EN_L1 5% 1/20W MF 2 201 ONEWIRE_DCIN_DIV V+ 1 V- ONEWIRE_ESD 3 U6990 2 LM397 2 SOT23-5 R6931 100K 6 5% 1/20W MF 201 B B BATTERY INTERFACE CRITICAL J6900 L6900 WTB-PWR-M82 FERR-50-OHM M-RT-SM 1 7 6 BATT_POS 2 2 3 BATT_POS_F 6 50 59 10% X7R 402 6 9 2 SM-LF 1 25V 5 8 C6900 0.0 OF 50 1 73 A . 051-7230 B.1UF CRITICAL G 1 5% 1/16W MF-LF 2 402 5 4 1 6 C R6933 100K 1% 1/16W MF-LF 2 402 C6930 10% 2 25V X5R 402 200K C6903 10% 2 50V CERM 402 R6901 24.8 6 7 2 3 4 5 DC-JACK INTERFACE R6905 PPBUS_G3H D CRITICAL D6901 CRITICAL 72 7 6 PP18V5_DCIN VOLTAGE=18.001UF 2 S 1 0.2 mm VOLTAGE=18.2 mm VOLTAGE=18.6 MM MIN_NECK_WIDTH=0. INC.3K 1 ONEWIRE_EN 100K ONEWIRE_PWR_EN_L_DIV 24.01UF 4 7 1 SMC_BS_ALRT_L SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SCL 6 7 41 42 6 7 41 44 59 71 DC-In & Battery Connectors 6 7 41 44 59 71 SYNC_MASTER=M70 A SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY 518S0540 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.3 mm MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.01UF 1 10% BATT_POS_F1 10 6AMP-24V 4 PPVBATT_G3H_R 2 1 5 2 4 3 PPDCIN_G3H 6 7 8 57 72 MIN_LINE_WIDTH=0.5V MIN_LINE_WIDTH=0.5V MIN_LINE_WIDTH=0. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.5V C6902 D HN2S02FU 47 5% 1/8W MF-LF 805 2 1 PP18V5_G3H 6 7 8 59 72 1 518S0507 R6902 6 1K 5% 1/16W MF-LF 402 59 42 41 6 SMC_BC_ACOK1 C S 5 G 2 Q6920 SSM6N15FE 1 SOT563 R6932 5% 1/16W MF-LF 2 402 6 SSM3K15FV 3 D SOD-VESM ONEWIRE_OV 1 R6900 1 R6903 200K Q6999 5% 1/16W MF-LF 2 402 SSM3J15FV 1 Q6940 G S 4 D PP18V5_DCIN_ONEWIRE 1 R6906 1 0.20 MM J6980 WTB-PWR-M82 1 M-RT-SM 1 SOT-363 0.5V 5% 1/8W MF-LF 805 1206-1 1 5 2 R6940 F6900 402 3 59 50 6 CRITICAL 2 25V X7R 2 6 PPDCIN_G3H_R MIN_LINE_WIDTH=0.

01UF S 4 RUNSS_GATE_D_L 1.5K 1 R7005 22.022UF 10% 2 10V X5R 201 1 Q7007 1 1V5S0_RUNSS D 3 1 10% 2 16V X7R 201 B S 4 RUNSS_GATE_D_L D 6 SOT563 2 G 47 S 1 DEASSERTED 160MS AFTER UVLO_D VALID PP3V3_A_S0 1 R7012 1 PGOOD_SEQUENCER 54 54 6 PGOOD_1V5S0 ALL_SYS_PWRGD_AND MAKEBASE=TRUE VDD 1 RESET*CRITICAL SENSE 5 U7002 TPS3808-1.05V S0 RUN/SS CONTROL CRITICAL Q7001 FDM6296 3.01UF 10% C7023 Q7006 0.3V X5R 201 S 1 RUNSS_GATE_D_L 6 7 8 19 22 51 61 72 CRITICAL 1 ENABLE_1 1 SOT563 GATE_A 2 GATE_B 5 6 6 54 D 6 Q7007 FDC655BN N-TYPE 33 mOhm @4. INC.7K 1% 72 61 51 22 19 8 7 6 PP1V8_S0 2 1/20W MF 201 6 4 10% 6 2 G 19 NC NC NC NC 11 ENABLE_2* NC 22 R7006 1 13. 6 5 4 3 2 REV.063 A 46 44 42 30 29 28 21 19 16 13 8 7 6 27 26 25 24 23 22 64 63 60 53 52 51 1UF 72 60 58 48 44 42 36 8 7 6 PP3V3_A_S0 53 6 8 38 47 61 62 63 MOSFET CHANNEL RDS(ON) LOADING C7006 C R7031 1/20W MF 201 3.01UF 10% 10V 2 X5R 201 THML PAD NOSTUFF 1 C7021 0.5V 4.25V S0 RUN/SS CONTROL R7041 R7040 1/20W MF 201 1/20W MF 201 100K 5% PP3V3_A_S0 2 1 330 5% 1V25S0_RUNSS_BUF2 1V25S0_RUNSS 6 1 1 P1V8S0_EN CERM 402 1 2 5 G FDC655BN N-TYPE 33 mOhm @4.3V X5R 201 R7007 2 330 5% 1V5S0_RUNSS_BUF2 5 G 51 6 6 RESET0* 24 RESET1* 9 C7040 10% 2 10V X5R 201 1/20W MF 201 DLY_OFF_A6 18 DLY_OFF_B6 13 C 57 D 3 Q7006 SOT563 R7050 DLY_ON_C 16 DLY_ON_D 15 SYSRST* 0.3V 10% CERM 402 72 55 34 31 18 8 6 7 16 21 32 35 68 C7000 PP3V3_S3 P3V3S0_EN 30.5V 1.0022UF U7000 S0SEQ_BEGIN 1V05S0_RUNSS 1 SSM6N15FE 1.1K 1% R7004 1% 1/20W MF 2 201 1/20W MF 201 B 6 1 2 C7005 R7000 2 D 1 4.0 OF 51 1 73 A .5V S0 RUN/SS CONTROL R7051 1/20W MF 201 10K 5% RUNSS_GATE_D 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 TP_DLY_ON_A TP_DLY_ON_B TP_DLY_ON_C TP_DLY_ON_D DLY_OFF_C 3 DLY_OFF_D 4 PP3V3_A_S0 PP5V_S5 56 55 54 51 39 27 8 7 6 72 58 R7061 1 470K 5% 1/20W MF 2 201 DLY_OFF_A DLY_OFF_B DLY_OFF_C 6 DLY_OFF_D NOSTUFF 1 C7024 0.01UF 10% 2 10V X5R 201 NOSTUFF 1 C7022 1 0.3V X5R 201 6 5% 1/20W MF 2 201 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 C7001 0.0022UF 10% 50V CERM 402 1 P5VS0_EN 6 7 8 22 27 40 43 47 51 52 53 63 72 44 43 36 28 27 26 25 24 8 7 6 72 60 58 57 56 51 49 2 FDC655BN 1 PP3V3_S5 SOT6 PP3V3_A_S0 D 2 5V S0 FET 1 D 1.3 has int 90K pull-up PGOOD_1V05S0 NO STUFF NO STUFF R7013 R7014 1/20W MF 201 1/20W MF 201 0 5% 57 6 PGOOD_1V25S0 2 1 0 5% 2 10% 2 6.022UF GATE_C 6 GATE_D 7 DLY_ON_A 21 DLY_ON_B 8 C7030 10% 2 6.87K 1 FDC655BN 2 1 R7001 64 63 60 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 330 5% CRITICAL 23 2 25 PP5V_S0 10% 50V CERM 402 Q7004 1 PP1V8_S3 S 53 52 51 47 43 40 27 22 8 7 6 72 63 FDC655BN N-TYPE 33 mOhm @4. 051-7230 SCALE SHT NONE 7 C7050 1000PF SSM6N15FE SOT563 ~26MS 5% 1/20W MF 201 8 6 54 SSM6N15FE 2 6.061 A 4 MOSFET CHANNEL RDS(ON) LOADING C7004 0.C7002 TO USE WIRE-AND OF ALL PGOODs INSTEAD OF TPS3808 APPLE INC.0.9K 1% 1/20W MF 201 R7002 1 SOT6 100K 1% 1/20W MF 2 201 5% 1/20W MF 2 201 55 6 PGOOD_1V8S3 6 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 PP3V3_A_S0 2 1 6 R7003 28.7K 1% 1/20W MF 2 201 1 10 GND PM_SLP_S3_L 2 1.C7001.776 A MOSFET CHANNEL RDS(ON) LOADING 0.3V S0 FET 5 6 3 G S FDM6296 N-TYPE 15 mOhm @4.120 A 51 6 0.0022UF 6 PP5V_S5 1 OMIT 2 6.8 6 7 2 3 4 5 1 S0 FETS & POWER SEQUENCING & PGOOD D D CRITICAL Q7000 PP5V_S0 MICROFET3X3 3 2 72 58 56 55 54 51 39 27 8 7 6 PP5V_S5 5 S G 4 6 MOSFET CHANNEL RDS(ON) LOADING C7003 0.5V 1.0022UF 10% 50V CERM 402 1 CRITICAL 2 Q7002 44 43 36 28 27 26 25 24 8 7 6 72 60 58 57 56 51 49 FDC655BN 1 PP3V3_S5 SOT6 PP3V3_B_S0 D 2 6 S 4 0.8V S0 FET 3 G 50V QFN 1/20W MF 201 1V05S0_RUNSS_BUF2 1 SSM6N15FE ISL6130IRZA 20 UVLO_A S0PWRGD_5V_DIV 12 UVLO_B S0PWRGD_3V3_DIV 17 UVLO_C S0PWRGD_1V8_DIV 14 UVLO_D 6 55 42 41 37 36 25 7 6 PP1V8_S0 5 VDD 7.3V S0 FET 3 G R7030 100K 5% 51 6 5 72 58 56 55 54 51 39 27 8 7 6 53 60 63 64 6 7 8 13 16 19 21 22 23 24 25 26 27 28 29 30 42 44 46 51 52 B.1UF 100K CT 4 PP1V25_S0 6 7 8 16 18 19 21 26 27 57 72 S0 FETS & Power Sequencing ALL_SYSPWRGD_DLY 6 1 SYNC_MASTER=M70 C7002 1000PF 10% ALL_SYS_PWRGD SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY 2 16V X7R 201 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.R7014 and UNSTUFF U7002.25V 3 MR* SOT23-6 GND 2 A U7002. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 6 28 41 52 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 1 SIZE DRAWING NUMBER D STUFF R7013.5V .

25 MM MIN_NECK_WIDTH=0.25 MM 0. 1 (IMVP6_VSUM) R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED 2 C7133 1 10% 6.20 MM 0.3V X5R 201 1 R7131 R7132 0 2 0 5% 1/20W MF 201 5% 1/20W MF 2 201 CPU_VCCSENSE_P 6 11 66 CPU_VCCSENSE_N 6 11 66 MIN_LINE_WIDTH 52 52 A 52 6 52 6 52 CRITICAL 0603-LF 52 6 52 B 6 1 ERT-J1VR103J 72 65 52 12 11 8 7 6 MIN_LINE_WIDTH 1% 1/16W MF-LF 402 2 52 6 IMVP6_PHASE IMVP6_BOOT IMVP6_UGATE IMVP6_LGATE IMVP6_VO_R 2 10KOHM-5% 52 6 52 6 1% 1/20W MF 201 R7144 1% 1/20W MF 2 201 0.2M-OHM FB 1% 1/20W MF 201 2 C7153 1UF 10% 25V X5R 603 RJK0305DPB IMVP6_VSEN_P VW 2 1 CRITICAL 1 IMVP6_VSEN_N COMP 8 20% 2 10.3V PP3V3_S0_IMVP6_3V3 R7103 C7103 1 1UF 0 5% 1/20W MF 201 GND_IMVP6_SGND 52 6 2 1 PLACE R7110 WITH NO STUB ON PM_DPRSLPVR R7111 499 1% 1/20W MF 2 201 1 1% 1/20W MF VDD VCCP CPU_VID<6> 34 VID6 CPU_VID<5> 33 VID5 66 12 11 6 CPU_VID<4> 66 12 11 6 32 VID4 CPU_VID<3> 31 VID3 30 VID2 29 VID1 CPU_VID<0> 28 VID0 37 DPRSTP* 36 DPRSLPVR 2 201 66 6 NO STUFF R7115 51 41 28 6 CPU_DPRSTP_L IN IMVP_DPRSLPVR ALL_SYS_PWRGD IN 1 FDE 2 PGD_IN 66 42 10 6 CPU_PROCHOT_L 1 28 6 2 OUT VR_PWRGD_CK505_L 41 6 FROM SMC 1 IN 28 16 9 6 2 IMVP_VR_ON OUT VR_PWRGOOD_DELAY 6 IMVP6_VR_TT R7116 C7111 NC 147K 0.8 6 7 1 IMVP6_PVCC 2 63 53 51 47 43 40 27 22 8 7 6 72 1 2 72 6 OMIT R7101 5% 1/16W MF-LF 402 72 59 55 54 53 52 42 8 7 6 1UF 2 PPBUS_R_G3H 1 2 R7102 5% 1/16W MF-LF 402 PM_DPRSLPVR IN PP5V_S0_IMVP6_VDD 5% 1/16W MF-LF 402 2 IMVP6 CPU VCORE REGULATOR 10% 6.0V POLY CASE-B2-1 C7152 1UF 10% 25V X5R 603 4 IMVP6_PHASE PHASE 24 1 2.25 MM 0.25 MM 0.5V 0. = 300kHz MAX CURRENT = 30A 5 Q7150 4 IMVP6_OCSET PPVCORE_S0_CPU VO 16 100 1% 1/20W MF 201 1 CRITICAL R7130 1 PPVCORE_S0_CPU SM-IHLP (IMVP6_PHASE) IMVP6_VSUM VSUM 17 VSS 52 6 CRITICAL IMVP6_UGATE 5 C7124 10% 10V X5R 201 LFPAK 2 3 0.20 MM 0.20 MM 0. 051-7230 SCALE SHT NONE 8 C 52 65 6 7 8 11 12 72 C7141 1000PF R7121 IMVP6_FB_RC NO STUFF IMVP6_DROOP 374K 2 2 PWM FREQ.20 MM 52 6 1.0.5 MM 0.36UH-30A-1.20 MM 52 6 52 6 52 52 6 IMVP6_OCSET IMVP6_VSUM GND_IMVP6_SGND PPVCORE_S0_CPU IMVP6_DROOP IMVP6_DFB IMVP6_SOFT IMVP6_RBIAS IMVP6_VDIFF IMVP6_FB IMVP6_COMP IMVP6_VW IMVP6_PVCC IMVP6_COMP_R IMVP6_COMP_RC IMVP6_FB_RC IMVP6_VDIFF_RC MIN_NECK_WIDTH 0.22UF 0 66 25 16 6 1UF 10% 6.12UF 1 2 C7143 1 0.20 MM 0.2 MM C7102 1 VOLTAGE=18.34K C7140 330PF 1% 1/20W MF 201 1% 1/20W MF 201 2 1 R7142 16V 20K X7R 201 2 270PF C7122 1 56PF 5% 25V NP0-C0G 201 2 C7123 1 1000PF R7123 6.5 MM 0.20 MM 0.20 MM 0. INC.25 MM 0.5 MM 0.0V CERM-X5R 402 0.015uF 1% 1/20W MF 201 10% 16V X7R 402 1 2 39 3V3 38 CLK_EN* 35 VR_ON 40 PGOOD 4 VR_TT* 5 NTC 52 6 IMVP6_SOFT 6 SOFT 52 6 IMVP6_RBIAS 3 RBIAS IMVP6_VDIFF 11 2 R7104 LGATE 26 52 IMVP6_LGATE 52 2 2 R7124 21 1K 6 IMVP6_COMP_R 1 52 6 52 1 R7122 15K 1% 1/20W MF 201 2 1 1% 1/20W MF 201 L7100 2 (IMVP6_FB) OCSET 7 52 (IMVP6_VO) 52 IMVP6_DFB 1 NC 41 TPAD 2 66 6 2 C7130 1000PF 10% 16V X7R 201 66 6 2 1 2 (IMVP6_VW) R7141 C7121 1 6.3V CERM 402 MIN_LINE_WIDTH=0.25 MM 0.25 MM 0. 7 6 5 4 3 2 REV.0V POLY CASE-B2-1 PPBUS_R_G3H CRITICAL 5 6 25 (GND) VSSP DFB 15 10 IMVP6_BOOT_RC 0 DROOP 14 52 6 1 QFN 0 5% 1/20W MF 201 IMVP6_BOOT BOOT 22 U7100 C7150 47UF CRITICAL 12 11 6 CPU_VID<2> 66 66 12 11 6 CPU_VID<1> 66 12 11 6 1 VIN 66 12 11 6 66 23 16 10 6 C CRITICAL 66 12 11 6 R7110 499 72 59 55 54 53 52 42 8 7 6 10% 10V X5R 402-1 27 72 6 2 20 1 ISL6261CRZ PP3V3_A_S0 18 64 63 60 25 24 23 22 21 19 16 13 8 7 6 53 51 46 44 42 30 29 28 27 26 B.25 MM MIN_NECK_WIDTH=0.01UF R7140 806 RTN 13 1 RJK0303DPB 1 16V VSEN 12 1 52 52 6 MIN_NECK_WIDTH 52 1.50 MM 0.2 MM VOLTAGE=5V C7101 1 0 D C7100 1 0 PP5V_S0 1 OMIT VOLTAGE=5V R7100 2 3 4 5 10% 16V X7R 603 2 MIN_LINE_WIDTH=0.4 OHM FOR VALIDATING CPU ONLY.20 MM 0.25 MM MIN_NECK_WIDTH=0.20 MM 0.1UF XW7100 52 6 2 R7146 7.25 MM 0.20 MM 0.20 MM 0.25 MM 0.20 MM 0.57K 1 C7142 2 10% 10.25 MM 0.25 MM 0.22UF 10% 16V X7R 603 VDIFF 52 1 C7104 1 5% 1/16W MF-LF 402 1 C7120 20% 2 10.0 OF 52 1 73 A .53K 10% 10V X5R 201 2 1% 1/20W MF 201 OMIT SM NOTE 1: C7132.20 MM 0.C7133 = 27.25 MM 0.3V CERM 402 72 6 D PPVIN_S5_IMVP6_VIN MIN_LINE_WIDTH=0.25 MM 0.04K 10% 16V X7R 201 2 1% 1/20W MF 201 1% 1/20W MF 201 10% 50V X7R-CERM 402 3.25 MM 0.25 MM 0.20 MM IMVP6 CPU VCore Regulator SYNC_MASTER=POWER SYNC_DATE=07/13/2005 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.20 MM 0.01UF R7145 4.25 MM 0. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.25 MM 0.20 MM 0.20 MM 0.20 MM 0.21K B 9 IMVP6_VW 180PF IMVP6_VDIFF_RC R7120 IMVP6_COMP 5% 50V CERM 402 2 1 52 52 6 1 47UF Q7100 UGATE 23 19 1 IMVP6_FB C7151 0.68K R7143 (IMVP6_VO) 1 2 1 2 3 1% 1/20W MF 201 10% 16V X7R 201 R7134 100 2 1 LFPAK 1 330PF 1 RJK0303DPB 2 1 2 3 10% 1 1 C7132 Q7151 4 LFPAK (IMVP6_VO) 1000PF 2 CRITICAL X7R 201 2 10% 16V X7R 201 GND_IMVP6_SGND 10% 2 2 C7131 0.25 MM 0.20 MM 0.2 MM VOLTAGE=3.20 MM 52 1.

250V 1.20 MM 0.8A.3V CERM 2 603-1 20 30K 5% 1/20W MF 201 NO STUFF 53 6 C7202 0. I236 SCALE SHT NONE 2 REV.20 MM 0.0V POLY CASE-B2-1 PWM FREQ.3 MM 0.025V 1.20 MM 0.01UF R7212 64 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 53 16 9 6 1 1K R7210 10 5 GCORE_CSCOMP GCORE_CSFB GCORE_LLINE GCORE_RT GFX_VR_EN GCORE_COMP GCORE_FB GCORE_FBRTN GCORE_PMON GCORE_PMONFS GCORE_RPM GCORE_VRPM GCORE_FB_R 4 MIN_LINE_WIDTH 0.20 MM 0.20 MM 0.3V X5R 2 402 1 200K 1% 1/20W MF 201 R7218 187K 113K 1% 1/20W MF 201 GND_SMC_AVSS 1 R7219 2 1% 1/20W MF 201 53 1 R7219 sets maximum current measured by PMON 1% 1/20W MF 201 6 NO STUFF R7250 Imax = 12.20 MM 0.1uA GCORE_ST 4 1 2 CRITICAL D 2 5% 1/16W MF-LF 402 1% 1/4W MF-LF 1206 5 309K 2 2 72 63 53 52 51 47 43 40 27 22 8 7 6 0 1 2 2 1% 1/20W MF 201 22 GCORE_DRVH 53 DRVH 19 GCORE_DRVL 53 DRVL CRITICAL 6 PMON 7 PMONFS GCORE_PMON GCORE_PMONFS 53 6 R7290 1 0.3 MM 0.7UF 1 1 10% 1 R7217 R7213 6.20 MM 0.3 MM 0.925V 0.100V 1.20 MM 2 5% 1/20W MF 201 PPVCORE_S0_NB_GFX 6 7 8 18 22 45 53 65 72 ROUTE AS DIFF PAIR TO NB GFX VCC AND GND FOR REMOTE SENSING 2 I103 I104 Render VCore Supplies I105 I106 I107 53 I108 53 6 I110 53 6 I111 53 6 I112 53 16 9 6 I113 53 I114 53 I235 53 6 53 6 53 6 53 6 53 6 C7280 20% 2 2.3 MM 0.20 MM 0.000V 0.900V 0.3 MM 0.3 MM 0.20 MM 0. INC.20 MM 0.20 MM 3 SYNC_MASTER=(MASTER) I115 I117 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY I118 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.5V POLY CASE-C2-SM-1 5% 1/20W MF 201 53 6 7 0 100 CRITICAL 1 330UF 20% 6.3 MM 0.20 MM 0.1KOhms 25 26 27 28 29 R7251 B 2 5% 1/20W MF 201 22 16 6 22 16 6 22 16 6 22 16 6 A 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOLTAGE 1. =400kHz MAX CURRENT = 13A (inductor limit) R7200 L7200 0.3V X5R-CERM 603 2 1 2 1/20W MF 201 63 60 53 44 42 30 25 24 23 13 8 7 6 22 21 19 16 29 28 27 26 46 2 52 51 64 PP3V3_A_S0 R7216 6 GCORE_PWRGD 31 PWRGD 53 6 9 LLINE GCORE_LLINE 1 53 1.0.20 MM 0.3 MM 0.20 MM 0. Rpmonfs = 93.008 Ohm)/1.200V 1.20 MM 0.6 MM C7281 10UF GCORE_COMP_R 6 2 201 10% 16V X7R 2 201 B C7234 10% 25V X7R-CERM 1000PF 2 5% 1/20W MF 201 (GCORE_ST) GND_GCORE_PGND 100 1 (GCORE_FBRTN) 53 6 2 5% 1/20W MF 201 5% 1/20W MF 201 (GCORE_CSFB) 0 1 10% 50V CERM 5% 25V 2 NP0-C0G 201 0 R7230 1% 1/20W MF 201 NO STUFF 1 1 1K (GCORE_FB) THRM_PAD 1 GCORE_SW_R 2 5% 1/20W MF 201 C7230 2 10% 16V X7R 201 2 3 1% 1/16W MF-LF 402 R7225 33.875V 1 110K (GCORE_CSCOMP) 470PF VID4 VID3 VID2 VID1 VID0 1 FB 2 53 GCORE_FB 2 1 10% 50V CERM 402 GND PGND (GCORE_CSCOMP) R7232 C7231 100PF 1% 1/20W MF 201 5% 25V 2 CERM 201 1 C7232 1 100PF 5% 25V 2 CERM 2 C7233 1 22PF NO STUFF (GCORE_COMP) 201 R7231 1 R7226 2 (GCORE_LLINE) R7228 53 GCORE_FB_R 1 C7241 1000PF 1 C7242 OMIT XW7200 10% 16V X7R 201 2 1 2 0.050V 1.950V 0.20 MM 0.20 MM 0.3 MM 0.3 MM 0.175V 1.6 MM 0.3 MM 0.20 MM 0.150V 1.3 MM 0.3 MM 0.225V 1.3 MM MIN_NECK_WIDTH 0.6 MM 0.20 MM 0.3 MM 0.3V X5R 603 R7229 1 R7292 MIN_LINE_WIDTH 0.20 MM 0.2K 53 6 8 2 R7222 2 CSREF 11 (GCORE_CSREF) GND GFX_VID<3> GFX_VID<2> GFX_VID<1> GFX_VID<0> 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 215K 1% 1/16W MF-LF 402 10 GCORE_CSCOMP 53 CSCOMP 2 1000PF VID VID VID VID VID VID VID VID VID VID VID VID VID VID VID VID R7224 SS 4 GCORE_SS C7240 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 10% 6.3V 1 1 NOTE: VID<4> is tied to GND 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWRPK-1212-8 1UF 53 10K C SI7108DNS 2 CERM 603-1 GCORE_VARFREQ 32 VARFREQ 1 Q7201 G C7214 1 FBRTN GCORE_VRPM 14 VRPM 10K 5% 1/20W MF 201 6 7 8 18 22 45 53 65 72 53 6 21 GCORE_SW SW GCORE_RPM 15 RPM 53 6 PPVCORE_S0_NB_GFX S 3 COMP GCORE_COMP R7220 GCORE_FBRTN PP5V_S0 Rpmonfs = (Imax x 0.3 MM 0.012UF 1 (GCORE_CSREF) 10% 25V X7R 402 2 SM Each step is 0.20 MM 0.6 MM 0.025V 1 1 C7243 470PF 20K 2 OMIT 1 2 402 2 C7244 220PF R7291 1 0 2 5% 1/20W MF 201 1 53 6 53 53 53 53 6 53 6 53 6 53 6 53 53 53 6 GCORE_SW GCORE_BST GCORE_DRVH GCORE_DRVL GCORE_BST_D GND_GCORE_PGND GCORE_VDC_DIV GCORE_RAMP GCORE_CLIM GCORE_SS GCORE_ST GCORE_SW_R MIN_NECK_WIDTH 0.975V 0.3 MM 0.0 OF 53 1 73 A .8 6 7 2 3 4 5 1 RENDER VCORE POWER SUPPLY D D 72 59 55 54 52 42 8 7 6 PPBUS_R_G3H R72111 PP5V_S0 5% 1/16W MF-LF 402 1 53 52 51 47 43 40 27 22 8 7 6 72 63 1% 1/20W MF 201 2 2GCORE_VCC PP3V3_A_S0 C7212 4.3 MM 0.22UF 59 45 42 41 6 2 18 C7290 ST 5 LFCSP 0.8K 5% 1/20W MF 201 GFX_VR_EN30 EN 53 6 PVCC 2 ( 2 OF 2 ) 53 6 20% 6.6 MM 0.3 MM 0.002 1 R7214 649K 20% 10.82UH 1 C7200 47UF CRITICAL CRITICAL 2 3 IHLP2525CZ-SM 23 GCORE_BST 1 53 BST ADP3209 17 41 6 1 1 (GCORE_SW) R7215 GCORE_CLIM 8 CLIM GCORE_CSFB 12 CSFB 2 PWRPK-1212-8 2 53 6 16 GCORE_RT RT U7200 2 SI7110DN 5% 25V CERM 2 201 53 6 13 GCORE_RAMP RAMP PLACE RC CLOSE TO SMC SMC_GPU_ISENSE VCC 1 S 2GCORE_BST_D 33 C 53 16 9 6 C7201 10% 16V X5R 603-1 Q7200 G 100PF B0530WS-X-F 24 2 4 C7211 1 CRITICAL D D7210 SOD-323 1 1 100K 5% 1 CRITICAL 1 1UF GCORE_VDC_DIV 1% 1/20W MF 201 1UF 10K 1% 1/20W MF 201 GFX_VR_EN R7209 C7213 5 10% 25V 2 X7R 402 340K 10% 6.20 MM 0.3 MM 0.20 MM 0.075V 1.125V 1. 051-7230 B.20 MM 0. THE POSSESSOR AGREES TO THE FOLLOWING I119 I120 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE I121 II NOT TO REPRODUCE OR COPY IT I122 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART I123 I124 SIZE I125 I230 DRAWING NUMBER D I229 APPLE INC.

C7305 close to U7300 pin 15.6 mm MIN_NECK_WIDTH=0. separate from the output voltage sensing trace.6 MIN_NECK_WIDTH=0.2 mm 5 V5FILT 1V05S0_VBST 1V05S0_VH 1V05S0_LL 1V05S0_VL 6 1V05S0_TRIP 1V05S0_VFB D CRITICAL C7352 G 330UF 20% 2 2. separate from the output voltage sensing trace. 051-7230 B.05V POWER SUPPLY State PM_SLP_S3_L PP1V5_S0 PP1V05_S0 HIGH 1.758V * (1 + Rc / Rd) C7381 4.5A mm mm mm mm mm mm 141V5S0_TRIP 5 1V5S0_VFB 7 4 1 D C7364 0 V5IN 1 22 21 20 19 20K 1% 1/20W MF 2 201 R7364 PWRPK-1212-8 3 Q7320 C7340 47UF 16V X5R 603-1 5 CRITICAL 6 2 14 13 12 11 10 8 7 6 PP1V05_S0 72 42 30 27 26 23 21 1UF 10% CRITICAL 1 1 (OCP setting limited) C7341 CRITICAL Q7360 25 1 PPBUS_R_G3H 6 7 8 42 52 53 54 55 59 72 16 PWM FREQ.81K S 1% 1/20W MF 2 201 3 2 1 51 6 51 VO1 SYM(1 OF 2) VO2 CRITICAL VBST1 VBST2 DR_VH1 DR_VH2 LL1 LL2 QFN DR_VL1 DR_VL2 17 2 24 TRIP1 VFB1 PGOOD1 U7300 TPS51124 TRIP2 VFB2 PGOOD2 1V05S0_RUNSS23 EN1 6 1V5S0_RUNSS8 EN2 GND 1 6 9 1V5S0_VBST 101V5S0_VH 111V5S0_LL 121V5S0_VL TONSEL 6 5% 1/16W MF-LF 402 1 2 0.0.3V X5R 603 PPBUS_R_G3H 5 SI7110DN 20% 2 10.5V/1.3 mm Routing Note: put 6 vias under the thermal pad (pin 25) PGOOD_1V05S0 PWM FREQ.6 MIN_NECK_WIDTH=0.2 MIN_LINE_WIDTH=0.0 OF 54 1 73 A . THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. C7301 close to U7600 pin 16.7UH-5.5K 1% 1/20W MF 2 201 2 54 6 GND_1V51V05S0_SGND MIN_NECK_WIDTH=0. 6 7 8 27 39 51 55 56 58 72 OMIT 1 1UF Placement Note: R7361.05V Supplies SYNC_MASTER=M70 A SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.5V POLY CASE-C2-SM-1 SI7212DN 1 CRITICAL 1 C7392 330UF OMIT 1 C7350 10UF 20% 6.0UH-22A-10M-OHM NO STUFF 1 2 C7329 100PF 5% 25V CERM 201 <Rc> 1 R7327 Q7321 <Rd> 1 R7328 SI7108DNS PWRPK-1212-8 1 0 5% 16V 1/16W X5R MF-LF 402 402 2 1 1V05S0_VBST_RC 1 2 3 2 1 MIN_LINE_WIDTH=0.3 5% 1/16W MF-LF 402 6 C7301 2 20% 6.00V S0 S3/S5/G3Hot C C R7361 3.68K 1% 1/20W MF 2 201 4 S L7320 B SI7212DN 1 4 R7325 6.1UF 10% 16V X5R 402 1 1V5S0_VBST_RC 2 MIN_LINE_WIDTH=0.2 mm MIN_LINE_WIDTH=0.0V POLY CASE-B2-1 C7324 D PWRPK-1212-8 G CRITICAL 1.5V/1.4K PGND THRM_PAD CRITICAL 1% 1/20W MF 2 201 47UF (OCP setting limited) 20% 10. 1 1V51V05S0_V5FILT Vout = 0.1UF 10% SM-IHLP CRITICAL 7. 72 59 55 54 53 52 42 8 7 6 20% 2 6.6 MIN_NECK_WIDTH=0.8 6 7 2 3 4 5 1 D D 1.5V 1.3V 2 X5R 603 6 7 8 11 12 22 26 27 72 C7369 100PF 20K 1 B NO STUFF <Ra> R7367 1 2 1% 1/20W MF 201 S 5% 25V CERM 201 2 <Rb> R7368 20.2 mm MIN_LINE_WIDTH=0. = 360 kHz MAX CURRENT = 3.0V 0.2 MIN_LINE_WIDTH=0.5V POLY CASE-C2-SM-1 R7324 0.2 4 G S CRITICAL L7360 1 1 R7365 2 G 15.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.758V * (1 + Ra / Rb) PGOOD_1V5S0 51 Note: pu on PGOOD page Note: pu on PGOOD page 1.6 mm MIN_NECK_WIDTH=0. = 300 kHz MAX CURRENT = 9.0V POLY CASE-B2-1 PWRPK-1212-8 20% 2 2. INC.3A C7380 PP1V5_S0 Q7360 D NC 1UF 10% 2 IHLP-2525 XW7300 51 2 16V X5R 603-1 CRITICAL SM Vout = 0. SCALE SHT NONE 8 7 6 5 4 3 2 REV.9A 19 18 PP5V_S5 2 13 10UF 10% 10V X5R 402-1 15 C7351 C7305 2 3 1 1 18 OMIT Routing Note: The discharge path (VO1) should have a dedicated trace to the output cap.05V LOW 0.3V X5R 603 10UF 54 6 GND_1V51V05S0_SGND Routing Note: The discharge path (VO2) should have a dedicated trace to the output cap.

75V * (1 + Ra / Rb) NO <Rb> 1 2 6 R7522 20K C 1 72 55 32 31 8 6 2 28K S0 HIGH HIGH 1.9V Supplies 2 XW7501 SM SYNC_MASTER=M70 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. = 400 kHz MAX CURRENT = 11A CRITICAL G S MIN_LINE_WIDTH=0.0V 0.2 mm 2 PP1V8_S3 MIN_LINE_WIDTH=0.3V X5R 603 330UF 2 OMIT 1 1 2 3 B 6 7 8 16 18 21 31 32 34 35 51 68 72 SM-IHLP 5 S OMIT 1 C7530 47UF SI7110DN D NC NC 1 Q7520 D 4 PPBUS_R_G3H CRITICAL CRITICAL C7543 330UF 20% 2. SCALE SHT NONE 8 7 6 5 4 3 2 REV.2.2 mm (inductor limited) L7520 1 2 3 1.3V X5R 603 OMIT 8. 1 7 12 C7511 2.8V 1 MIN_LINE_WIDTH=0.033UF 10% 16V X5R 402 1 2 6 1V8S3_V5FILT 1 72 33 8 7 6 C7502 10UF 5% 1/16W MF-LF 402 10% 10V X5R 402-1 PP0V9_S3 PP0V9_S0 OMIT 1 4.1uF 10% CRITICAL 5 VTTGND 1 10UF PGND 18 C7508 20% 2 6.8V/0.9V POWER SUPPLY D State Vout = 0.8V 0. 051-7230 B.25K 1% 1/20W MF 2 201 VDDQSET VTTREF VLDOIN VTT V5FILT R7500 2 8 15 22 14 24 23 5 9 R7510 1 0 5% 1/16W MF-LF 402 VBST V5IN VDDQSNS VTTSNS Routing Note: 51 42 41 37 36 25 7 6 58 PM_SLP_S3_L 1V8S3_RUNSS 10 11 S3 S5 PGOOD CRITICAL DRVH LL U7500 SYM (1 OF 2) 6 6 1V8S3_CS 16 13 21 1V8S3_DRVH 20 1V8S3_LL TPS51116 COMP QFN CS Routing Note: DRVL 19 1V8S3_DRVL MODE 4 NC0 NC1 Connect CS_GND to Q7521 PIN1.8V/0.0. NEAR C7542 PIN 2 6 GND_1V8S3_CSGND MIN_NECK_WIDTH=0.2 mm 4 CRITICAL CRITICAL 1 Q7521 SI7108DNS G PWRPK-1212-8 1 10UF 2 C7541 C7542 20% 2. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.3V X5R 603 PLACE C7507.0UH-22A-10M-OHM VOLTAGE=1.8 6 7 2 3 4 5 1 D 1.3 mm Placement Note: 1 PGOOD_1V8S3 6 2 51 XW7500 SM PLACE XW7500.C7508 GND NEAR PIN 1 THRM_PAD 25 Placement Note: OMIT 1 CRITICAL 1 C7532 47UF 20% 2 10.3V 2 CERM 402-LF 0.3 using Kelvin connection.0V POLY CASE-B2-1 1 C7531 1UF 10% 2 25V X5R 603 PWM FREQ.3 mm A 1 1.9V S3 HIGH LOW 1.2 mm MIN_LINE_WIDTH=0.0V S5/G3Hot LOW LOW 0.2 mm MIN_LINE_WIDTH=0.5V POLY CASE-C2-HF Placement Note: PLACE C7543 NEAR NB (GND) 6 Routing Note: put 6 vias under the thermal pad GND_1V8S3_SGND MIN_NECK_WIDTH=0.0V POLY CASE-B2-1 PWRPK-1212-8 20% 2 10.0 OF 55 1 73 A .2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.0V Routing Note: 25V CERM 201 1% 1/20W MF 201 1 2 PP0V9_S0 2 <Ra> C7503 100PF R7521 5% 1% 1/20W MF 201 PM_SLP_S3_L PP1V8_S3 STUFF 1 1V8S3_VDDQSET PM_S4_STATE_L C CONNECT VDDQSNS TO C7542 PIN1 using separate trace.3V X5R 603 GND 3 10UF CS_GND 17 C7507 20% 2 6.5V POLY CASE-C2-HF 20% 2 6.6 mm MIN_NECK_WIDTH=0.7 1UF 72 56 51 27 6 7 8 39 54 58 PP5V_S5 R7507 C7500 72 55 32 31 8 6 2 2 20% 6. PP0V9_S3 C7540 0.6 mm MIN_NECK_WIDTH=0.8V 0.2UF 20% C7509 2 16V X5R 402 1 CONNECT VTTSNS TO C7507 PIN1 using separate trace. INC.6 mm MIN_NECK_WIDTH=0. B 2 1V8S3_VBST_RC 1V8S3_VBST1 72 59 54 53 52 42 8 7 6 6.

8 6 7 2 3 4 5 1 5V/3.3V PWRPK-1212-8 POLY CASE-B2-HF G 5 6 7 8 GND COMP2 VO2 3 VREF2 VFB2 2 VFB1 4 1 VO1 4 S 6 1% 1/20W MF 201 CS2 PGND2 18 17 V5FILT 1 R7605 5.3UH-6. 10% 50V CERM 402 GND_5V3V3S5_SGND 5V3V3S5_TONSEL PPBUS_G3H C7600 0. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 6 56 MIN_NECK_WIDTH=0.3V 0.6 LL2 153V3S5_LL MIN_NECK_WIDTH=0.6 MIN_NECK_WIDTH=0.90K 6 BOM OPTION 128S0093 128S0092 ? REF DES 5 16V X5R 402 3V3S5_VBST_RC2 CRITICAL C7640 47UF 20% 10.2 U7600 5VS5_VREG 3 2 1 R7660 0 72 64 59 56 50 45 37 8 7 6 TPS51120 VIN S VOLTAGE=5V MIN_LINE_WIDTH=0.0A PWPD 56 42 41 6 603-1 C 6 56 CRITICAL 33 PGND1 1UF 10% 2 16V X5R COMP1 Routing Note: put 6 vias under the thermal pad (pin 33) C7681 23 47UF 20% 2 10.2 mm MIN_LINE_WIDTH=0. pin 21.001UF 1 5V3V3S5_V5FILT 56 6 1 6 56 1% 1/20W MF 201 5VS5_CS C GND_5V3V3S5_SGND 4.6 MIN_NECK_WIDTH=0.3V X5R 603 GND_5V3V3S5_SGND 5V/3.2 MIN_LINE_WIDTH=0.3V 3.8A CRITICAL mm mm mm mm mm mm 4 Q7620 G SI7110DN S 1 2 PWRPK-1212-8 (OCP setting limited) 3 5 D 4 G S PP3V3_S5 2 CRITICAL 6 7 8 24 25 26 27 28 36 43 44 49 51 57 58 60 72 VOLTAGE=3. INC.3V POLY SI7110DN C7652 150UF 20% CASE-B2-HF 1 C7651 150UF OMIT C7650 10UF 20% 20% 2 6.3 mm II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.6 mm MIN_NECK_WIDTH=0.3V POLY 1 CASE-B2-HF 2 6. 1 CRITICAL 20% 2 6.0V 3.3V X5R 603 2 1 10% 2 10V X5R 402-1 2 XW7601 SM 20% 2 6.6 MIN_NECK_WIDTH=0.3V X5R 603 R7603 7.6 DRVH2 MIN_NECK_WIDTH=0.R7603 close to to U7600 to U7600 TO U7600 close to U7600 pin 20. U7600.6 DRVL2 163V3S5_DRVL MIN_NECK_WIDTH=0.C7680 KEMET T520V336M016ATE0457650 1 TABLE_ALT_ITEM 128S0093 A 128S0092 ? C7640 C7602 1UF 10% 2 16V X5R 603-1 KEMET T520V336M016ATE0457650 1 OMIT OMIT 1 C7605 1 C7603 C7604 10UF 1UF 10UF 20% 6.0V POLY CASE-B2-1 1 2 25V3V3S5_VREF 24 CRITICAL C7680 Routing Note: The discharge path (VO2) should have a dedicated trace to the output cap.3V Supplies Placement Note: R7601.2 mm PGOOD1 6 22 B 2 4 G PWRPK-1212-8 1 30 5% 1/16W 6 SMC_PM_G2_EN29 MF-LF 41 402 58 56 1 5VS5_VBST_RC 1 2 28 5VS5_VBST 16V X5R 402 D Q7660 PP5V_S5 TONSEL 0. SYNC_MASTER=M70 SYNC_DATE=02/01/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.5A CRITICAL C7692 Q7661 150UF PGOOD2 NC NC 3V3S5_CS OMIT 1 C7690 C7691 10UF 150UF 10 EN2 21 L7660 9 EN3 SYM (2 OF 3) VBST1 mm 27 DRVH1 5VS5_DRVH mm mm 26 LL1 mm5VS5_LL mm 5VS5_DRVL 25 DRVL1 mm 5 IHLP EN5 LLP EN1 2 CRITICAL 1 MIN_LINE_WIDTH=0. pin 22.87K2 1 1% 1/20W MF 201 NO STUFF C7667 1 20K COMMENTS: 1 2 TABLE_ALT_ITEM C7682.0V 0. SCALE SHT NONE 8 7 6 5 4 3 2 REV. separate from the output voltage sensing trace. PIN 19. = 430 kHz MAX CURRENT = 7.0V POLY CASE-B2-1 D 1 PWM FREQ.2 MIN_LINE_WIDTH=0.C7605 C7602 close C7604 close C7603 CLOSE R7605.3V MIN_LINE_WIDTH=0.2 MIN_LINE_WIDTH=0.3V POLY CASE-B2-HF 1 20% SI7110DN 2 6.6 mm MIN_NECK_WIDTH=0.1UF 10% SI7110DN (inductor limited) SKIPSEL 31 RSMRST_PWRGD CS1 CRITICAL 72 58 55 54 51 39 27 8 7 6 32 C7660 5 PWM FREQ.3V POWER SUPPLY D D State G3H SMC_PM_G2_EN PP3V3_G3H PP5V_S5 PP3V3_S5 LOW HIGH 3.106V = 1V * (1 + 20K / 4. = 280 kHz MAX CURRENT = 6.1UF 10% C7641 1UF 1 R7601 4.2UH-14A B IHLP2525CZ-SM1 CRITICAL 1 2 3 1 CRITICAL CRITICAL Q7621 1 PWRPK-1212-8 2 6.7 PART NUMBER 1 R7620 0 5% 12 SMC_PM_G2_EN 1/16W MF-LF 402 13 3V3S5_VBST 1 2 PPBUS_G3H 6 41 42 56 MIN_LINE_WIDTH=0.0 OF 56 1 73 A .0V 5.87K) <Ra> <Rb> R7667 R7668 1 100PF 2 2 5VS5_FB R7610 0 5% 25V CERM 201 5% 1/16W MF-LF 402 Routing Note: The discharge path (VO1) should have a dedicated trace to the output cap.3V X5R 603 20% 2 6.2 VREG3 VREG5 6 3 2 1 8 7 6 72 64 59 56 50 45 37 RSMRST_PWRGD 143V3S5_DRVH 19 D CRITICAL 11 VBST2 20 3.2 MIN_LINE_WIDTH=0.3V S0/S3/S5 Vout = 1V * (1 + Ra / Rb) 5. 051-7230 B.2 mm L7620 2.0.15K 1% 1/20W MF 2 201 2 5V3V3S5_V5FILT 6 PPBUS_G3H 56 5V3V3S5_VREG3 5% 1/16W MF-LF 402 TABLE_ALT_HEAD ALTERNATE FOR PART NUMBER 10% 16V 2 X5R 603-1 C7620 0.

0A max output (Switcher limit) IHLP1616BZ-SM 309K 22PF PP1V25_S0 P1V25S0_SW MIN_LINE_WIDTH=0. = ??? MAX CURRENT = 0.0 OF 57 1 73 A .option. D7790 SOD-323 PPDCIN_G3H 1 R7792 2 383K 1% 1/20W MF 2 201 B0530WS-X-F 1 SSM6N15FE C C SOT563 5 42 40 6 SMC_ONOFF_H G S 4 C7730 Vout = 1.2 mm FB 6 SHDN 5 Q7730 33UH-0. INC.3V CERM-X5R 402 1.25V Switcher P1V25S0_VFB_DIV <Rc> R7752 1 A SYNC_MASTER=M70 1% 1/20W MF 201 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY 23.2516V 3.8V * (1 + Ra / (Rb + Rc)) III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. 051-7230 B.2 mm 1 C7750 2.2K THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.425V G3H SUPPLY D Supply needs to guarantee 3.8 6 7 2 3 4 5 1 3.25V * (1 + Ra / Rb) 1 0.and control and the power button is depressed.3 mm MIN_NECK_WIDTH=0.22uF 3 100K 5% 1/20W MF 201 2 B0530WS-X-F R77951 Q7730 will pull down P3V42G3H_SHDN_L in the event of a keyboard SMC Reset generated when left shift.25V S0 REGULATOR PP3V3_S5 B 51 6 1V25S0_RUNSS R7755 0 C7751 3 11 1 10 CRITICAL NO STUFF Continuous 44 43 36 28 27 26 25 24 8 7 6 72 60 58 56 51 49 20% 4V CERM-X5R 0805-1 SVIN PVIN 5% 1/20W MF 2 201 U7750 LTC3412A 6 P1V25S0_RT 15 1 QFN RT RUN/SS 1 47UF 2 PGOOD 12 PGOOD_1V25S0 B 6 51 CRITICAL 6 6 6 C7753 2.6 mm MIN_NECK_WIDTH=0.3A CRITICAL 10% 2 6.31V delivered to SMC VRef generator D 72 50 8 7 6 6 P3V42G3H5_BOOST C7791 DFN SW 2 72 6 CRITICAL P3V42G3H_SHDN_L 4 S1024AS-SM D 6 SSM6N15FE PP3V42_G3H 1 VOLTAGE=3.2UH-3.22UF 10% 2 6.42V THRML SOT563 C7792 1R7791 10PF 665K 2 G C7790 S 1 Q7730 D7791 SOD-323 5.2NF C7754 10% 10V 2 X5R 201 6 SW 1 5% 25V NP0-C0G 201 <Ra> R7750 1 47K R7754 1% 1/20W MF 201 2 2 2 1% 1/20W MF 201 XW7750 SM GND_P1V2S3_SGND 1 VOLTAGE=0V MIN_LINE_WIDTH=0.0. THE POSSESSOR AGREES TO THE FOLLOWING 2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT Vout = 0.3V CERM-X5R 402 VIN 2 1 BOOST 6 1 1 0.2 mm MIN_NECK_WIDTH=0.42V/1.6UF 20% 25V POSCAP CASE-B2-SM-HF D 3 1 C7793 100UF 20% 2 6. SCALE SHT NONE 8 7 6 5 4 3 2 REV.3V POLY B2-HF <Rb> P3V42G3H_FB P3V42G3H_SHDN_L1 6 LSOC_PRESS_H CRITICAL 1% 1/20W MF 2 201 CRITICAL 42 40 6 7 8 23 26 27 28 39 40 41 42 43 44 59 72 <Ra> 5% 2 25V NPO 201 PAD 7 GND L7790 MIN_LINE_WIDTH=0.4K 1% 1/20W MF 201 2 3.25 mm 17 5% 1/20W MF 2 201 CRITICAL L7750 2.39A PP3V42G3H_SW U7790 LT1934 PWM FREQ.2NF 2 10% 10V X5R 201 CRITICAL C7755 1 47UF 20% 4V CERM-X5R 0805-1 6 7 8 16 18 19 21 26 27 51 72 Vout = 1.25K 1% 1/20W MF 201 13 16 2 R7753 P1V25S0_ITH P1V25S0_MODE CRITICAL 1 C7756 47UF 2 20% 4V 2 CERM-X5R 0805-1 2 P1V25S0_VFB <Rb> 1 R7751 60.25A 8 9 VFB THERM SGND PGND PAD 0 7 Burst 2 P1V25S0_ITH_RC 14 R7756 6 1 1 1 4 5 ITH SYNC/MODE 1 8.

0022uF 10% 50V CERM 402 1 2 6 7 8 40 60 72 5V S3 FET MOSFET CHANNEL RDS(ON) LOADING B FDC638P P-TYPE 48 mOhm @4.051 A R7806 10K 5% 1/20W MF 201 D 6 Q7860 CRITICAL Q7866 FDC638P SSM6N15FE 58 41 36 25 6 IN PM_S4_STATE_L R7807 2 G 72 60 43 36 8 7 6 28 27 26 25 24 57 56 51 49 44 S 1 PP3V3_S5 6 5 2 1 4 1 100K 5% 1/20W MF 201 PP3V3_S3 SM-LF SOT563 3 R7808 2 5% 1/20W MF 201 1 2 C7802 0. SCALE SHT NONE 8 7 6 5 4 3 2 REV.3V S5 RUN/SS CONTROL 1.47UF 10% 6.0.5V 0. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.0 OF 58 1 73 A .8 6 7 D 2 3 4 5 1 D S3 FETS & S3/S5 CONTROL 5V/3. 051-7230 B.3V 402 2 CERM-X5R 1 10K 5% 1/20W MF 201 2 CRITICAL Q7865 FDC638P SM-LF B 72 58 56 55 54 51 39 27 8 7 6 PP5V_S5 4 R7805 3 100K 5% 1/20W MF 201 72 58 56 55 54 51 39 27 8 7 6 PP5V_S5 1 2 PM_SLP_S4_LS5V 1 PP5V_S3 6 5 2 1 2 6 P5VS3_EN_L C7801 0.3V S3 FET MOSFET CHANNEL RDS(ON) LOADING FDC638P P-TYPE 65 mOhm @2. INC.098 A S3 FET & S3/S5 Control 2 SYNC_MASTER=M70 SYNC_DATE=02/01/2007 A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.5V 0.8V S3 RUN/SS CONTROL R7870 100K 5% 1/20W MF 201 58 41 36 25 6 C 58 56 41 6 SMC_PM_G2_EN IN SMC_PM_G2_EN MAKE_BASE=TRUE 6 41 56 58 OUT 6 41 56 58 PM_S4_STATE_L 1 MAKE_BASE=TRUE 1V8S3_RUNSS 2 OUT 55 C 1 SMC_PM_G2_EN R7856 OUT IN C7870 0.01UF 10K 6 P3V3S3_EN_L 10% 10V X5R 201 1 6 7 8 36 42 44 48 51 60 72 3.

7UH-7.3V X5R 402 KELVIN CONNECTION MIN_LINE_WIDTH=0.2MM VDDP 4 VREF 3 ACIN CHGR_ICOMP 5 CHGR_VCOMP 7 CHGR_VNEG 8 CHGR_CSOP 18 CHGR_CSON 17 6 4 5 NC 1 6 MIN_LINE_WIDTH=0.0V POLY POLY CASE-B2-1 CASE-B2-1 MIN_LINE_WIDTH=0.1UF 402 DFN TL331 1. 051-7230 B.5% 1W MF 0612 C7931 3 C7926 2 1 6 7 8 37 45 50 56 59 64 72 CRITICAL 20% 20% 10.0 OF 59 1 73 A .6 MM MIN_NECK_WIDTH=0.6 MM MIN_NECK_WIDTH=0. SCALE SHT NONE 8 7 6 5 4 3 2 REV.22UF 4. = 400 kHz MAX CURRENT = ??A 1000PF 0.2K SMC_PBUS_ISENSE 1 1 CRITICAL PPVDCIN_G3H_PRE_0 D 1 6 R79451 ICOMP VCOMP VNEG CSOP CSON 2 G 6 10% 6.2 MM MIN_NECK_WIDTH=0.2MM R79311 10 5% 1/20W MF 201 2 (??? limited) (CHGR_CSOP) B XW7931 SM PPVBAT_G3H_CHRGR_REG_0 6 72 C7946 1 44 41 7 6 71 59 50 PPBUS_G3H CRITICAL CRITICAL C7930 6 7 8 42 52 53 54 55 59 72 TO SYSTEM 2 PPVBAT_G3H_CHGR_REG MICROFET3X3 PPBUS_R_G3H 1% 1/4W MF-LF 1206 7AMP-24V CRITICAL GND_CHGR_SGND CHGR_VNEG_R 6 7 41 44 50 59 71 0.1UF 1 1% 1/16W MF-LF 402 R7999 2 MIN_LINE_WIDTH=0.1UF 1 PPVDCIN_G3H_PRE_R CHGR_BGATE CHGR_DCIN 6 59 BOOT 6 25 UGATE 24 PHASE 23 CHGR_BOOT CHGR_UGATE CHGR_PHASE LGATE 21 CHGR_LGATE 26 6 AGND AMON 9 BMON 15 ACOK 14 2 10% 25V X5R 402 C7996 1 2 1 2 10% 25V X5R 402 1 GND_CHGR_SGND 6 59 C7921 2 20% 25V 2 POLY CASE-D2-LF 22UF 1 C7922 1 1UF 10% 25V X5R 603 2 C7925 0.6 MM MIN_NECK_WIDTH=0.1K -INS U7960 2 R7910 -INF 1 V- CHGR_SGATE 1 PPBUS_R_G3H 2 CHGR_LOWCURRENT_GATE R7901 6 6 PBUS_ISENSE_IN_NEG SOT23-5 1% 1/20W MF 201 2 0.53K R7920 XW7921 1 2 5% 1/20W MF 201 D 6 1 R7989 THM PAD 6 41 C7989 1 S 0.2 MM MIN_LINE_WIDTH=0.2 MM 62K C7960 1 57.1UF 10% 25V X5R 402 1 1 2 1 IHLP4040CZ-SM 72 6 1 47UF FDM6296 470PF 10% 50V CERM 2 402 SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA 6 7 41 44 50 59 71 R7930 0.82K 1 46 10% 16V LTC6102AP 1 5% 1/20W MF 201 5 GND 3 CHGR_LOWCURRENT_REF 0.68UF 2 10% 6.76K 1% 1/20W MF 201 2 VDD 71 59 50 44 41 7 6 C7995 0.2 MM 4 D 1 1 CRITICAL PBUS CURRENT SENSOR AO4409 SOI PPVDCIN_G3H_PRE2 3 2 72 50 8 7 6 PP18V5_G3H 7 CRITICAL 1 MIN_NECK_WIDTH=0.047UF 1 1UF 5% 1/16W MF-LF 402 1UF 1 1 72 6 C7924 1 5% 1/20W MF 201 CHGR_VDDP R7940 4.0.2 MM L7900 4. INC.1UF 2 X5R U7980 2 D C7980 1 V+ 402 VCC R79611 CHGR_DCIN 10% 2 25V X5R 5 100K 5% 1/20W MF 201 2 0.6K 10% 25V 2 X5R 402 R7981 21 CHGR_SGATE_DIV R79621 57 44 43 42 26 23 8 7 6 41 40 39 28 27 72 59 R7960 C7910 D 6 1 59 6 2 6 7 100K 5% 1/20W MF 201 2 PPBUS_G3H 9 R79001 0.2 MM 3 59 6 16 BGATE DCIN 2 TRKL* 13 29 THRM_PAD 2 0.2 MM PPVBAT_G3H_CHGR_OUT 2 1 6 59 72 C7935 1UF 10% 2 25V X5R 603 47UF 2 XW7930 2 SM 1 PWM FREQ.01UF G 10% 2 10V X5R 201 S 1 1 C7951 0.2 MM MIN_LINE_WIDTH=0.68UF R7974 1 10% 6. THE POSSESSOR AGREES TO THE FOLLOWING D 3 CHGR_VDD_L I TO MAINTAIN THE DOCUMENT IN CONFIDENCE SOT563 5 CHGR_VDD_R G SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY SSM6N15FE 5% 1/20W MF 201 2 6 41 42 45 53 59 Q7970 SSM6N15FE D 2 6 41 C7971 AO4409 SOI 1M 7 8 C7972 GND_SMC_AVSS R7975 D 1 Q7950 1NO STUFF PP3V42_G3H 72 39 28 27 26 23 8 7 6 59 57 44 43 42 41 40 5 6 5% 1/20W MF 201 CRITICAL 6 41 S SMC_BATT_ISENSE 2 R7971 0 G 1 BATTERY CHARGING 6 59 PLACE RC CLOSE TO SMC 4 59 CHGR_BMON 6 3 MAKE_BASE=TRUE 1 2 SMC_BC_ACOK 50 42 41 6 59 CHGR_BGATE 6 II NOT TO REPRODUCE OR COPY IT 59 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART S 4 SIZE DRAWING NUMBER D APPLE INC.001UF 59 6 2 0.2MM 1/20W MIN_NECK_WIDTH=0.2 MM 41 42 50 59 C7923 1UF 10% 25V X5R 603 S 1 6 1 CRITICAL G B C7920 20% 25V POLY CASE-D2-LF Q7920 4 MIN_NECK_WIDTH=0.3V CERM 402 GND_SMC_AVSS 6 CHGR_VDD 1M Q7970 6 SOT563 5% 1/20W MF 2 201 72 59 6 PPVBAT_G3H_CHGR_OUT 1 C7950 0.2 MM 30.01UF 10% 10V 201 0.1UF 10% 2 16V X5R 402 TO BATTERY MIN_LINE_WIDTH=0.0022 1206 MIN_LINE_WIDTH=0.0V 2 10.3 MM GND_SMC_AVSS 6 TO CURRENT SENSOR U7980 72 6 PP18V5_S5_CHGR_SW_R CRITICAL CRITICAL 22UF 2 NC CHGR_AMON 59 6 CHGR_BMON SMC_BC_ACOK 6 0.6 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.3V X5R 2 201 3 PLACE C CLOSE TO SMC LTC6102 DISABLED WHEN SHDN=1 LTC6102 ENABLED WHEN SHDN=0 SM 4 33000PF SHDN PBUS_ISENSE_VREG MIN_NECK_WIDTH=0.01K SMBUS_SMC_BSA_SCL CRITICAL CRITICAL FDM6296 Q7921 XW7900 SM R79461 44 41 7 6 71 59 50 41 42 45 53 59 C 1 MICROFET3X3 MIN_LINE_WIDTH=0.1UF 10% 50V CERM 2 402 GND_CHGR_SGND 20% 6.02 SM 5 10% 16V X5R 402 CHGR_VCOMP_R 0.2MM MF 201 10% 2 10V X5R 402-1 PGND C7947 (CHGR_ACIN) 10% 10V X5R 402-1 0.1UF 1% 1/16W MF-LF 402 2 C7944 2 X5R C7943 56.2MM CRITICAL OMIT C7942 1 12 VHST AGATE 1 6 CHGR_AGATE U7900 CSIP 6 28 CHGR_CSIP 11 SCL SMBUS_SMC_BSA_SCL QFN 10 SDA SMBUS_SMC_BSA_SDA CSIN 6 27 CHGR_CSIN 71 59 50 7 6 pullups offpage 44 41 +IN 6 OUT PBUS_SMC_VSENSE_EN_L 45 42 6 XW7920 1 R7921 10 2 C7940 20 1UF R79111 10% 16V CERM 402 1 5% MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.5% 1W MF 2 0612 2 C7945 1 1% 1/20W MF 2 201 0.3V 2 CERM 1M 402 A 59 6 CHGR_AMON 5% 1/20W MF 201 2 6 41 42 45 53 59 PLACE RC CLOSE TO SMC 1 SMC_DCIN_ISENSE 2 R7970 0 5% 1/20W MF 201 1 59 R79731 0.6 MM MIN_NECK_WIDTH=0.1UF 72 64 59 56 50 45 37 8 7 6 PPVDCIN_G3H_PRE MIN_LINE_WIDTH=0.7 C7941 PP3V42_G3H 62 ISL6258 72 59 57 23 8 7 6 44 43 42 41 40 39 28 27 26 1 62K 10 2 22 C 2CHGR_VDD 1 19 1% 1/20W MF 201 2 8 VREG CRITICAL CRITICAL MIN_NECK_WIDTH=0.5A 1 1% 1/16W MF-LF 402 2 SMBUS_SMC_BSA_SCL R7980 F7900 CRITICAL 2 2 3.2 MM 4 C7900 1 2 72 45 6 5 6 7 5 D S 8 8 B0530WS-X-F G D7910 SOD-323 MIN_LINE_WIDTH=0.2MM R79471 10 5% 1/20W MF 201 2 (CHGR_CSOP) (CHGR_CSON) ACOK pullup/down on SMC page SMC_BC_ACOK AMON PULLDOWN LOGIC 6 41 42 50 59 CHGR_AMON 0.01 1 10% 16V 2 X7R 201 MIN_LINE_WIDTH=0.8 6 7 2 3 4 5 1 PBUS SUPPLY / BATTERY CHARGER CRITICAL Q7900 Q7901 AO4409 SOI 10% 25V X5R 402 2 3 1 S G PP3V42_G3H 1% 1/20W MF 201 2 6 CHGR_AMON 1 2 72 59 55 54 53 52 42 8 7 6 R7923 10% 10V 2 X5R 402-1 9.2 MM BATT_POS_F 6 50 PBUS Supply/Battery Charger SYNC_MASTER=M70 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.2MM MIN_NECK_WIDTH=0.2MM 72 6 PPVBAT_G3H_CHRGR_REG_R MIN_LINE_WIDTH=0.

8-OHM 1 2 SMBUS_SMC_B_S3_SDA 6 I2C_TOP_ALS_SDA_F 44 41 7 6 240-OHM-0.2A-0.20MM MIN_NECK_WIDTH=0.1UF 5% 1/20W MF 201 Q9004 0.2A-0.0.3V 2 X5R 201 SSM3K15FV D 4 3 SOD-VESM 72 6 1 C9011 10% 2 6. SYNC_MASTER=GPU 6 7 37 0201 240-OHM-0.8-OHM 1 2 AUD_MIC_CLK 1 2 90-OHM-100MA 1210-4SM1 SYM_VER-2 4 3 LVDS.Camera Conn.8-OHM MIN_LINE_WIDTH=0.8-OHM 1 2 AUD_MIC_DATA 6 AUD_MIC_DATA_F AUD_MIC_CLK_F 8 L9053 1 BI 67 15 6 BI LVDS_A_CLK_N LVDS_A_CLK_P 0201 240-OHM-0. DRAWING NUMBER 7 6 5 4 3 2 REV.01UF APN:518S0356 2 1 C9053 0.20MM MIN_NECK_WIDTH=0.01UF 10% 2 10V X5R 201 NO STUFF 1 C9030 10PF 5% 25V NPO 201 2 II NOT TO REPRODUCE OR COPY IT 1 NO STUFF C9031 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 10PF 5% 25V SIZE 201 D 2 NPO APPLE INC.3V MIN_LINE_WIDTH=0. INC.3V MIN_LINE_WIDTH=0.3V 1 PP3V3_S3_MIC_F 2 NC NC 3 A 67 15 7 6 BI LVDS_A_DATA_N<2> LVDS_A_DATA_P<2> L9012 2 1 6 7 8 36 42 44 48 51 58 72 3 SYM_VER-2 1210-4SM1 90-OHM-100MA 4 CRITICAL L9006 6 240-OHM-0.2.2MM 0402-LF LVDS REFERENCE CURRENT.20MM 7 37 67 15 6 L9031 GND_MIC_F C9050 BI 0201 6 5 6 67 15 7 6 L9030 4 4 CRITICAL CRITICAL F-RT-SM 7 10% 10V X5R 201 SYNC_DATE=06/23/2006 NOTICE OF PROPRIETARY PROPERTY 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.37K2 1 1% 1/20W MF 201 PLACE NEAR NB 7 6 64 7 6 64 1 R9008 R9009 10K 1 10K 15 7 6 BI 15 7 6 BI LVDS_DDC_CLK LVDS_DDC_DATA 7 6 64 7 6 64 5% 1/20W MF 2 201 5% 1/20W MF 2 201 7 6 64 7 6 64 7 6 72 64 LCDBKLT_RTN<1> LCDBKLT_RTN<2> LCDBKLT_RTN<3> LCDBKLT_RTN<4> LCDBKLT_RTN<5> LCDBKLT_RTN<6> PPVOUT_S0_LCDBKLT B BI 67 15 7 BI LVDS_A_DATA_N<0> LVDS_A_DATA_P<0> L9010 2 1 3 SYM_VER-2 1210-4SM1 90-OHM-100MA 4 BI 67 15 7 BI LVDS_A_DATA_N<1> LVDS_A_DATA_P<1> L9011 2 1 MIC CONNECTOR L9050 240-OHM-0.0 OF 60 1 73 A .3A-EMI C PP3V3_A_S0 1 2 MIN_NECK_WIDTH=0.2MM 72 7 6 PP3V3_S0_LCD_F 72 7 6 (LVDS DDC POWER) C9010 1 10% 16V X7R 201 2 LVDS_A_DATA_F_N<0> 67 6 LVDS_A_DATA_F_P<0> 67 6 LVDS_A_DATA_F_N<1> 67 6 LVDS_A_DATA_F_P<1> 67 6 LVDS_A_DATA_F_N<2> 67 6 LVDS_A_DATA_F_P<2> 7 6 LVDS_A_CLK_F_N 7 6 LVDS_A_CLK_F_P 1000PF R9013 LVDS_IBG MIN_LINE_WIDTH=0.20MM VOLTAGE=3.5A 1 CRITICAL J9000 1 10PF 25V 20347-130E-11 F-RT-SM 38 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2 0402-LF C9015 1 10% 16V X7R 201 2 1000PF PLACE FILTERS AND CAPS NEAR PINS ON CONNECTOR 120-OHM-0.2A-0.37K OHM PULL DOWN RESISTOR NEEDED 67 15 6 VOLTAGE=3.2MM 0.3V X5R 201 3 6 PP3V3_LCDVDD_SW VOLTAGE=3.3MM MIN_NECK_WIDTH=0.2MM 72 7 6 PP3V3_LCDVDD_SW_F VOLTAGE=3.3V MIN_LINE_WIDTH=0.3MM 69 7 6 L9008 64 63 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 69 7 6 PP5V_S3_CAMERA_F USB2_CAMERA_F_P USB2_CAMERA_F_N VOLTAGE=5V 67 6 2.8 72 58 28 27 26 25 24 8 7 6 57 56 51 49 44 43 36 6 7 PP3V3_S5 CRITICAL R9002 FDC638P 100K 5% 1/20W MF 2 201 R9023 10% 6. and ALS Conn.3MM MIN_NECK_WIDTH=0.8-OHM 1 2 SMBUS_SMC_B_S3_SCL 6 I2C_TOP_ALS_SCL_F 0201 L9051 FERR-120-OHM-1.2A-0.8-OHM 1 2 PP3V3_S3 J9050 GS03067-11131-7F MIN_LINE_WIDTH=0.0033UF PLT_RST_L LCD + CAMERA CONNECTOR SM-LF 1 C9040 1 Q9003 1 D 2 3 4 5 2 0201 0402-LF 3 C9016 1 1 10% 16V X7R 201 2 2 NPO 1000PF 100K 1% 1/20W MF 2 201 CRITICAL L9004 C9052 10PF C9051 5% 5% 25V NPO 201 201 FERR-120-OHM-1.5A 1 PP5V_S3 58 40 8 7 6 72 B 1 USB2_CAMERA_N L9005 10% 50V CERM 402 A 1 D L9007 C9012 C9013 2 LVDS_VDD_EN CRITICAL OMIT 1 0.2A-0. THE POSSESSOR AGREES TO THE FOLLOWING 0201 1 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 0. 051-7230 SCALE SHT NONE 8 B 518S0433 3 SYM_VER-2 1210-4SM1 90-OHM-100MA C 39 CRITICAL 67 15 7 LCD I/F 31 32 33 34 35 36 37 CRITICAL 67 15 7 CAMERA I/F B.3V X5R 603 69 24 9 6 BI 69 24 9 6 BI U9040Y 2 4 LVDS_VDD_GATED_EN R9014 1 USB2_CAMERA_P CRITICAL 2 L9052 4 3 44 41 7 6 240-OHM-0.2A-0.3MM MIN_NECK_WIDTH=0.1UF 10K 6 5 2 1 2 LCDVDD_PWREN_L 6 1 LCDVDD_PWREN_L_R 24 7 6 64 28 15 6 IN IN 5 TC7SZ08AFEF SOT665 1 1 G S 2 90-OHM-100MA 10UF 1210-4SM1 SYM_VER-1 20% 2 6.

9 6 61 63 67 TMDS_TX_N<2> 6 61 63 67 D 2 1% 1/20W MF 201 C9223 1000PF 1C9233 1000PF 0.1UF TMDS_SDC_N 67 6 TMDS_SDC_P R9200 5.3V X5R 201 R9239 6 2 16V X7R 0.3V ACTIVE OUTPUT NC 1 R9200 INSURES ESD DIODE U9201 SOT-553 4 2 2TMDS_HTPLG_R 5% 1/20W MF 201 55 54 201 0 2 10% 6.5V TOL INPUT CURRENT IS SMALL R9213 270K 5% 1/20W MF 201 74LVC1G17DRL SDGSDG+ 58 57 SDBSDB+ 61 60 SDCSDC+ 47 46 SDISDI+ 49 EXT_RES 44 TEST DVI_HOTPLUG_DET_BUF BI 1% 1/20W MF 201 2 SDVO_CTRLCLK SDVO_CTRLDATA BI 7 SDVO_CTRLCLK BI 6 16 61 SDSDA 6 SDVO_CTRLDATA BI 6 16 61 A1 8 SDADDC 12 SCLDDC 11 TMDS_DDC_SCL (int pullup) SCLROM 14 NC LSCL/DCEN 4 LSDA/PREEMP 3 LINT* NC NC NC NC SGND BI 6 7 37 62 63 67 TO TMDS CONNECTOR BI 6 7 37 62 63 67 5% 1/20W MF 201 2 TMDS_LSCL MAKE_BASE=TRUE TMDS_LSDA TMDS_LSDA MAKE_BASE=TRUE 6 61 62 0 2 6 62 1NO STUFF R9252 0 5% 1/20W MF 2 201 SDVO/TMDS Tx THRM_PAD SYNC_MASTER=GRAPHIC SYNC_DATE=06/06/2005 NOTICE OF PROPRIETARY PROPERTY BI 1 2 R9212 9. 7 6 61 62 TMDS_LINT_L 15 6 5 4 3 2 REV.1UF 2 X5R 2 201 20% 6.U9201 CLOSE TO 6 7 37 63 TMDS_SDB_P 10% 6.1UF AND 1000PF FOR EACH PIN CRITICAL TMDS_TX<0> 62 OMIT C9212 R9237 49.1UF (int pulldown) 53 59 A TMDS_HTPLG 52 51 HOST SERIAL DATA RECEIVER CORE 5 10 41 45 1 1% 1/20W MF 201 RIO CONN J4200 IN TMDS_EXT_RES QFN R9254 2 X5R RESET* SIL1392 PP3V3_B_S0 PLACE R9200.1UF 1000PF 10% 6.3V I2C MASTER 63 CRITICAL 5 1 SDRSDR+ 0.1UF 10% 6.1UF 10% X5R 67 15 6 67 15 6 6.1UF 10% 16V 1 R9209 67 63 61 6 TMDS_TX_P<2> C9204 10% 6.F12" 1 R9250 100K 67 6 TMDS_SDR_N 67 6 TMDS_SDR_P 67 6 TMDS_SDG_N 67 6 TMDS_SDG_P 2 67 6 5% 1/20W MF 201 67 6 C9219 0.3V 2 X5R 201 C9244 1 2 C9245 1 0.1UF 1000PF 10% 16V X7R 201 2 2 10% 6.9 2 1% 1/20W MF 201 C9224 1000PF 201 ONE 1000PF FOR EACH PIN R9210 10% 2 6.0 OF 61 1 73 A .3V 10% 6.3V X5R 603 ONE 0.5A 47 38 8 6 63 62 61 51 PP3V3_B_S0 1 1 0. INC.3V 2 X5R 201 1 C9248 0.3V X5R 201 2 10% 16V X7R 201 1C9261 1 1C9207 C9240 10UF 2 TMDS_TX_P<0> 67 63 61 6 6 61 72 20% 6.1UF 0.3V PP1V8_S0_PVCC1_TMDS_F C9205 10UF 0.B. 051-7230 SCALE SHT NONE 8 6 8 38 47 51 61 62 63 TMDS_LSCL 6 62 1% 1/20W MF 201 1 B 6 24 61 62 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.94K 62 64 37 32 21 27 31 CONFIGURATION /PROGRAMMING CRITICAL TC7SZ08AFEF 5 SOT665 3.3V X5R 49.9 2 TMDS_TX_CLK_N 6 61 63 67 1% 1/20W MF 201 C9225 1000PF C 10% TWO 0.1UF AND 1000PF FOR EACH PIN L9203 1 10UF ONE 0.3V 2 201 0.1UF 10% 6.1UF 10% 2 16V X7R 2 16V X7R 201 201 10% 2 6.1UF 10% 6.2MM 0402-LF 1 1C9231 C9230 1000PF 0.3V X5R 201 0.1UF AND 1000PF FOR EACH PIN CRITICAL C 2 16V X7R L9205 201 FERR-120-OHM-1.9 1 201 R9240 2 6 TMDS_TX_CLK 1% 1/20W MF 201 1 1 49.8V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.5A 72 61 51 22 19 8 7 6 PP1V8_S0 1 PP1V8_S0_PVCC2_TMDS_F 2 6 61 72 VOLTAGE=1.9 1 VOLTAGE=1.0.3V X5R 72 61 6 201 TWO 0.1UF 10% 6.2MM 17 PP3V3_S0_SPVCC_TMDS_F PVCC1 2 50 56 1 PP3V3_B_S0 51 47 38 8 6 63 62 61 2 9 33 38 43 48 FERR-120-OHM-1.8V MIN_LINE_WIDTH=0.3V X5R 201 10% 16V X7R 201 10% 6.8V MIN_LINE_WIDTH=0.8 6 7 CRITICAL PP1V8_S0 1 L9201 R9207 FERR-120-OHM-1.3V X5R 2 1000PF 1000PF 10% 2 16V X7R 49.3V X5R 201 1 0402-LF C9208 1C9209 C9210 1C9211 0.1UF 1000PF 0.5A PP1V8_S0_ANALOG_TMDS_F 2 PP1V8_S0 72 61 51 22 19 8 7 6 1 VOLTAGE=1.3V 2 X5R 201 C9246 1 C9247 0. THE POSSESSOR AGREES TO THE FOLLOWING R9211 9.3V X5R 201 0.3V MIN_LINE_WIDTH=0.1UF 10% 6.5A 10% FERR-120-OHM-1.1UF 1000PF 0.3MM MIN_NECK_WIDTH=0.1UF 10% 10% 2 16V X7R 2 6.3V X5R 201 0.CLK SIGNAL TO TMDS CHIP 10% 2 6.3V X5R 201 2 1 C9253 0.3V X5R 603 2 1 2 2 1 2 2 1 1 1% 1/20W MF 201 C9213 2 1C9250 FERR-120-OHM-1.09K 3 6 25 4.1UF PP3V3_S0_ANALOG_SDVO_F 2 2 6 61 72 VOLTAGE=3.3V 1 2 X5R 201 67 6 TMDS_INT_N OUT PEG_D2R_N<1> 1 2 67 6 TMDS_INT_P OUT PEG_D2R_P<1> TMDS CHIP SDVO INPUT INTERRUPT SIGNAL TO MCH R9201 2.3V X5R 201 2 10% 6.1UF 0.3V X5R 603 PP1V8_S0_ANALOG_TMDS_F PP1V8_S0_TMDS_F PP3V3_S0_SPVCC_TMDS_F 6 61 72 PP3V3_B_S0 10% 1C9259 1C9260 1000PF 0.3V MIN_LINE_WIDTH=0.3V X5R 201 201 1 1C9252 C9251 1000PF 10% 6.3V 2 X7R 2 X7R 2 X5R 2 X5R 201 201 201 201 72 61 6 PP3V3_S0_ANALOG_SDVO_F 72 61 6 PP1V8_S0_ANALOG_SDVO_F 72 61 6 PP1V8_S0_PVCC2_TMDS_F 72 61 6 TWO 0.1UF 10% 201 201 72 61 51 22 19 8 7 6 201 PP1V8_S0 1 C9200 10% 16V 1 C9254 1000PF 10% 2 16V X7R 201 201 49.1UF 10% 2 1% 1/20W MF 201 1C9206 2 6.1UF 10% 6.9 1% 1/20W MF 201 R9208 1000PF 10% 2 6.1UF AND 1000PF FOR EACH PIN B 67 15 6 IN 67 15 6 IN 67 15 6 IN 67 15 6 IN 67 15 6 IN 67 15 6 IN 67 15 6 IN 67 15 6 IN 5% 1/20W MF 67 63 61 6 67 63 61 6 OUT PEG_R2D_C_N<2> PEG_R2D_C_P<2> 67 63 61 6 OUT 67 63 61 6 OUT PEG_R2D_C_N<3> PEG_R2D_C_P<3> 67 63 61 6 OUT 67 63 61 6 OUT 67 63 61 6 OUT 2 C9241 1 0.3V X5R 201 10% 16V X7R 201 10% 6.2MM 10% 1 1 10% PP1V8_S0_PVCC1_TMDS_F 0402-LF C9201 1C9202 2 X7R 201 1000PF 1% 1/20W MF 201 PP1V8_S0_ANALOG_SDVO_F 2 2 X7R C9232 TMDS_TX<1> 201 L9204 2 16V X7R TMDS_TX_N<1> R9238 6 FERR-120-OHM-1.5A 61 51 22 19 8 7 6 72 2 3 4 5 67 63 61 6 TMDS_TX_CLK_P 49.8V MIN_LINE_WIDTH=0.1UF 10% 16V 10% 6.5MM MIN_NECK_WIDTH=0.2MM 0402-LF 1 1 C9234 1000PF 10% 16V C9235 1C9255 1C9256 1000PF 0.3MM MIN_NECK_WIDTH=0.1UF 0.1UF 10% 6.3V 201 C9220 0.5A 1 2 L9200 1000PF 2 16V X7R 1000PF 1 49.3V 2 X5R 201 67 63 61 6 OUT OUT 6 22 23 TX0TX0+ TMDS_TX_N<1> TMDS_TX_P<1> 25 26 TX1TX1+ TMDS_TX_N<2> TMDS_TX_P<2> 28 29 TX2TX2+ TMDS_TX_CLK_N TMDS_TX_CLK_P 19 20 TXCTXC+ 16 EXT_SWING TMDS_EXT_SWING "Place R9250 near U2300.2MM 6 61 72 VOLTAGE=1.G.9 1 10UF 2 X5R 201 6 61 72 VOLTAGE=1.3MM MIN_NECK_WIDTH=0.2MM 0402-LF PP1V8_S0_TMDS_F 2 1 C9236 C9237 1000PF 10% 16V X7R 201 2 1C9238 1C9239 0.1UF AND 1000PF FOR EACH PIN 72 61 6 CRITICAL L9207 72 61 6 PP3V3_B_S0 6 8 38 47 51 61 62 63 OMIT 1C9221 1 10% 6.7K TMDS_HDARST_L 5% 1/20W MF 201 AGND 6 28 62 R92511 R9253 GND TMDS_SW_RESET_L PP3V3_B_S0 NO STUFF1 FACTORY TEST MODE 1 ADDRESS=0X70 ADDRESS=0X72 IF A1 IS PULLED HIGH TMDS_DDC_SDA 34 40 39 36 35 Y B DVI_HOTPLUG_DET SPDIF/HDASDO HDASYNC HDABCLK HDASDI HDARST* A U9290 1 5% 1/20W MF 201 2 TMDS_HW_RESET_L 3 42 HTPLG LOCAL I2C 1K 2 4 SDSCL 13 NC DIFFERENTIAL SIGNAL DATA SPGND R92031 TMDS_RST_L 65 BI 61 16 6 1% 1/20W MF 201 2 1 1 (int pullup) SDAROM AUDIO 18 24 30 61 16 6 R9202 2.3V 2 X5R 201 C9242 1 2 C9243 1 0.3V X5R 1 2 16V X7R 20% 6.1UF 20% 6.3V X5R 201 1 R9204 MCH SDVO CHANNEL R.1UF 10% 6.1UF 10% 16V X7R 201 0.8V MIN_LINE_WIDTH=0.09K 1% 1/20W MF 201 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 1 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE 2 DRAWING NUMBER D 2 APPLE INC.3V X5R 603 TMDS_TX<2> 1 1 49.5A B.94K 10K TMDS_SDB_N 67 6 6 63 62 61 51 47 38 8 6 U9200 TMDS_TX_N<0> TMDS_TX_P<0> DVI_HOTPLUG_DET 62 61 24 6 AVCC1_8 CRITICAL 2 201 PEG_R2D_C_N<1> PEG_R2D_C_P<1> 1 SVCC 360 PLACE THESE CAPS NEAR NB PEG_R2D_C_N<0> PEG_R2D_C_P<0> VCC 6 8 38 47 51 61 62 63 NO STUFF 1C9290 SPVCC 1000PF C9258 OVCC 1 C9257 HDAVCC 1 AVCC3_3 0402-LF PP1V8_S0_ANALOG_SDVO_F PVCC2 6 61 72 VOLTAGE=3.3MM MIN_NECK_WIDTH=0.9 1 10% C9214 CRITICAL 2 TMDS_TX_P<1> 201 OMIT 1 C9222 2 16V X7R 1 PP1V8_S0 67 63 61 6 C9262 CRITICAL 0402-LF 61 51 22 19 8 7 6 72 6 61 63 67 201 2 16V X7R 201 TMDS_TX_N<0> 10% 10% 2 6.2MM OMIT 1 D 1 CRITICAL L9206 FERR-120-OHM-1.5MM MIN_NECK_WIDTH=0.

INC.7K 1% 1/20W MF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 2 201 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.0 OF 62 1 73 A .20MM VOLTAGE=3.0) 16 A9(P2.2K 5% 1/20W MF 2 201 SST8051 2 6 VDD OMIT CRITICAL R9303 SST8051 G 4 2 61 28 6 5% 1/20W MF 201 2 1 SST8051 S 1UF B 1 6 8 A 2 5 5 4.5 (CEX3/MISO)P1.8 6 7 2 3 4 5 1 SST8051 microcontroller for HDCP support D PP3V3_B_S0 D 6 8 38 47 51 61 62 63 SST8051 CRITICAL L9300 FERR-120-OHM-1.3) 19 A12(P2.1(AD1) P0.5(AD5) P0.5A SST8051 6 SST8051 1 C9302 10% 10V 2 X5R DVI_HOTPLUG_DET_BUF 201 8 1 5% 1/20W MF 201 2 A 10UF 20% 6.3 (RXD)P3.4) 20 P2.0(AD0) P0.7 (WR#)P3. SCALE SHT NONE 8 7 6 5 4 3 2 REV.6 (CEX4/SCK)P1.2K 36 SST8051_UPDATE_L 6 25 62 37 DVI_HOTPLUG_DET_BUF 6 61 62 38 SST8051_DVI_HOTPLUG_DET 39 NC 40 6 SST8051_DDC_CLK 1 6 SST8051_DDC_DATA 2 3 A8(P2.7 SM-2.2K B 61 6 62 6 10MS RC GENERATES ONE-SHOT LOW PULSE ON INT0# TO ALLOW PART TO WAKE UP AND XTAL TO START SST8051 C9390 TP_SST8051_TXD 22PF 2 SST8051 C9391 22PF 1 1 4 WQFN 14.7(AD7) P1.1UF 2 0402-LF SST8051 6 10% 6.1) 17 A10(P2.318MHZ-35PPF-20PF 6 SST8051_XTAL1 SST8051_XTAL2 6 SST8051_RST 6 2 62 6 C9326 14 XTAL1 13 XTAL2 62 25 6 SST8051_EA_L SST8051_UPDATE_L 24 PSEN* 5 25 6 SST8051_SW_RESET_L 1 B 4 SON GND R9305 1 2.30MM MIN_NECK_WIDTH=0. THE POSSESSOR AGREES TO THE FOLLOWING 4.0(T2) P1.2) 18 A11(P2.7K G 1 US8 35 6 DVI_HPDET_RC R9306 1 74LVC2G132 SST8051 7 132 Y CRITICAL U9340 SST8051 C C9300 CRITICAL 10K 10% 6.5X2.2(AD2) P0.1UF 2 U9300 SST89V54RD Y9390 2 SST8051 1 (INT0#)P3.5 (RD#)P3.5(A13) 21 P2.3(CEX0) P1.1(T2_EX) P1.1 OMIT 5% 25V NP0-C0G 201 PP3V3_B_S0 7 8 5 9 NC 10 NC 12 NC 11 6 1 5% 25V NP0-C0G 201 63 62 61 51 47 38 8 6 DVI_HOTPLUG_DET_INT_L TMDS_LINT_L TP_SST8051_RXD SST8051_P34_AUDIO_CONFIG 2.3V D 1 1 3 C9341 PP3V3_S0_HDCP_F 4 PP3V3_B_S0 61 51 47 38 8 6 63 62 B 10K 1% 1/20W MF 2 201 NO STUFF R9350 62 6 SST8051_DVI_HOTPLUG_DET 1 0 2 DVI_HOTPLUG_DET 6 24 61 5% 1/20W MF 201 PP3V3_B_S0 62 25 6 SST8051_UPDATE_L MAKE_BASE=TRUE SST8051_UPDATE_L 6 25 62 R9351 6 8 38 47 51 61 62 63 62 61 6 DVI_HOTPLUG_DET_BUF SST8051 R9330 4.4(CEX1/SS*) (CEX2/MOSI)P1.3V X5R 201 TMDS_HW_RESET_L P0.3V X5R 201 MIN_LINE_WIDTH=0.2(ECI) P1.7K 1% 1/20W MF PP3V3_B_S0 AUDIO CONFIG OPTIONS SST8051 R93011 62 6 SST8051_P25_AUDIO_CONFIG P25 P34 OPTION 10K 1% 1/20W MF 201 2 A 62 6 62 6 2 STUFFING OPTION CHOOSES RAW OR CONTROLLER OUTPUT OF DVI_HOTPLUG_DET 2 201 63 62 61 51 47 38 8 6 0 5% 1/20W MF 201 1 SST8051_UPDATE_L pulled up to 10K at SB 1 0 0 1 1 SST8051_P34_AUDIO_CONFIG SST8051_EA_L 0 1 0 1 HD AUDIO SPDIF NO AUDIO RESERVED HDCP uController SYNC_MASTER= SYNC_DATE= NOTICE OF PROPRIETARY PROPERTY SST8051 R9333 1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.0 (T0)P3.7(A15) 23 26 EA* CRITICAL SST8051 VCC 2 A TC7SH00FEF 34 33 32 31 30 29 28 27 R93041 5% 1/20W MF 2 201 4 RST NC 25 ALE/PROG* 10% 6.6(AD6) P0.01UF D 2 0.3V CERM 603-1 1 0. 051-7230 B.1UF U9340 SST8051 R93401 C9340 CRITICAL C9301 S 62 61 6 SST8051 1 0.6 (TXD)P3.2 (INT1#)P3.2K 5% 1/20W MF 2 201 6 SST8051_DDC_EN NC TMDS_DDC_SCL SST8051 BI 6 7 37 61 63 67 BI 6 7 37 61 63 67 C Q9300 SSM6N15FE SOT563 TMDS_DDC_SDA SST8051 Q9300 SSM6N15FE SOT563 NC NC NC NC NC TMDS_LSCL SST8051_P25_AUDIO_CONFIG BI 6 61 BI 6 61 6 62 NC NC TMDS_LSDA VSS SST8051 R9325 1 3 B 5% 1/20W MF 201 2 15 Y THRM_PAD 41 U9325 2.3V 2 X5R 201 SST8051 74LVC2G132 US8 SST8051 1 R9302 4 SST8051 3 132 6 Y DVI_HOTPLUG_DET_DEL_L 2.3(AD3) P0.6(A14) 22 P2.3V 2 X5R 603 10% 6.0.0MM 3 0.4 (T1)P3.4(AD4) P0.

3V X5R 201 CRITICAL PP3V3_A_S0 D9401 R9466 R9467 2.30 MM MIN_NECK_WIDTH=0.2V 1 VOLTAGE=5V MIN_LINE_WIDTH=0. VOLTAGE=0V SCALE SHT NONE 8 7 6 5 4 3 2 .1UF 10% 2 6. REV.3K OHM 1% RESISTOR IS REQUIRED BETWEEN CRT_IREF AND GROUND R9469 CRT_TVO_IREF 67 63 15 6 1 53 52 51 47 43 40 27 22 8 7 6 72 1.0.2 MM MIN_NECK_WIDTH=0.25 MM PP3V3_B_S0 0.5 MM MIN_NECK_WIDTH=0.2K 5% 1/20W MF 2 201 67 63 15 6 SOD-723 1 2 1 5% 1/20W MF 2 201 U9404 8 SN74LVC2G125DCU R9460 1SS418 1 PP5V_S0_DVIPORT_D 6 8 38 47 51 61 62 63 C9460 CRT_HSYNC_R 1 39 2 6 CRT_HSYNC_LS_R A 5% 1/20W MF 201 6 72 VOLTAGE=5V MIN_LINE_WIDTH=0.1UF 10% 2 6.5 MM MIN_NECK_WIDTH=0.3K 2 L9444 600-OHM-300MA 0.20 MM 1% 1/20W MF 201 53 52 51 46 44 42 30 29 19 16 13 8 7 6 28 27 26 25 24 23 22 21 64 63 60 CRITICAL F9404 PP5V_S0 2 D MAKE_BASE=TRUE 72 6 PP5V_S0_TMDS_FUSE 1 PP5V_S0_DVIPORT 2 VOLTAGE=5V MIN_LINE_WIDTH=0. 051-7230 B.0 OF 63 1 73 A .2K 2.5AMP-13.2 MM R9470 US VCC 5 125 Y 3 CRT_HSYNC_LS 6 1 7 4 39 VGA_HSYNC 2 5% 1/20W MF 201 GND 6 7 37 NOSTUFF 1 C9442 33PF 5% 2 25V NP0-C0G 201 C 15 R94621 TV_DCONSEL<0> 1K 15 6 5% 1/20W MF 2012 TV_DCONSEL<1> 61 37 7 6 PP3V3_B_S0 63 62 61 51 47 38 8 6 37 7 6 R9463 1K 5% 1/20W MF 2 201 U9404 8 SN74LVC2G125DCU US R9461 67 63 15 6 CRT_VSYNC_R 1 39 2 6 CRT_VSYNC_LS_R 5% 1/20W MF 201 TMDS_HTPLG A 125 Y R9480 1 4 6 7 37 NOSTUFF 1 C9443 33PF 2 25V NP0-C0G 5% 1/20W MF 2 201 201 16V 2 X7R 201 67 62 61 37 7 6 DVI_HOST BI TMDS_DDC_SDA NOSTUFF C9411 CRITICAL 100PF 5% L9405 2 25V CERM 90-OHM-100MA 1210-4SM1 201 SB_CRT_TVOUT_MUX_L 67 62 61 37 7 6 BI 2 TMDS_DDC_SCL NOSTUFF 1 PLACE U9401 NEAR NB PLACE R9450 R9451 CLOSE TO NB TV_A_DAC CRT_BLUE 67 63 15 6 53 52 51 46 44 42 30 22 21 19 16 13 8 7 6 29 28 27 26 25 24 23 64 63 60 67 63 15 6 150 1% 1/20W MF 2 201 25V 2 CERM 37 7 6 1% 1/20W MF 2 201 These nets connect to RIO connector J4200 37 7 6 0. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 150 1% 1/20W MF 2 201 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE GND DRAWING NUMBER D VOLTAGE=0V GND APPLE INC.3V X5R 201 VCC U9401 VGA_B 6 7 37 67 FSAV430 GND 37 7 6 DQFN VOLTAGE=0V 1 S GND VOLTAGE=0V 2 1B1 OE* 15 CRITICAL 3 1B2 TV_B_DAC CRT_GREEN 5 2B1 3B1 11 6 2B2 3B2 10 R9453 GND 1 150 1% 1/20W MF 2 201 8 150 3A 9 1% 1/20W MF 2 201 FL9400 210MHZ MEA2010P-SM VGA_G 67 37 7 6 8 67 6 EXT_C_R 2 7 67 6 EXT_Y_G 3 6 EXT_COMPVID_B 4 5 6 61 67 L9407 90-OHM-100MA 1210-4SM1 VGA_R TMDS_TX_CONN_N<2> 2 TMDS_TX_CONN_P<1> 1 TMDS_TX_CONN_N<1> TMDS_TX_N<1> 6 61 67 B 4 CRITICAL L9406 90-OHM-100MA 1210-4SM1 TMDS_TX_P<0> 6 61 67 TMDS_TX_N<0> 6 61 67 3 TMDS_TX_CONN_CLK_P TMDS_TX_CONN_CLK_N 6 61 67 SYM_VER-1 TMDS_TX_CONN_P<0> TMDS_TX_CONN_N<0> TMDS_TX_P<1> 3 2 6 7 37 67 67 37 7 6 1 4 SYM_VER-1 6 7 37 67 CRITICAL L9404 300-OHM-100MA 1210-4SM 2 3 THMPAD 1 17 R9452 1 4A 12 NC 7 2A 1 37 7 6 4B1 14 NC 4B2 13 NC 4 1A PLACE R9452 R9453 CLOSE TO NB TMDS_TX_CONN_P<2> 201 1 150 TMDS_TX_N<2> 4 CRITICAL C9439 R9451 1 16 R9450 1 6 61 67 SYM_VER-1 100PF 5% PP3V3_A_S0 TMDS_TX_P<2> 3 1 C9412 37 7 6 67 63 15 6 VGA_VSYNC 2 5% 1/20W MF 201 1 C9410 1 67 63 15 6 1 GND 1000PF 10% 100K 5% 1/20W MF 2 201 B CRT_VSYNC_LS 6 39 5% R9481 1 10K 25 6 6 C R9471 VCC 2 HDMI_HOST 1 37 7 6 BI PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR THE CONNECTOR CRITICAL 1 CRITICAL 4 TMDS_TX_CLK_P 6 61 67 TMDS_TX_CLK_N 6 61 67 SYM_VER-1 GND VOLTAGE=0V GND DVI CONNECTIONS VOLTAGE=0V A SYNC_MASTER=M70 PLACE R9454 R9455 CLOSE TO NB 67 63 15 6 TV_C_DAC 67 63 15 6 CRT_RED R9454 1 150 1% 1/20W MF 2 201 Place components near J4200 unless otherwise noted R9455 1 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.8 6 7 2 3 4 5 1 NB VIDEO ALIASES 67 63 15 6 67 63 15 6 67 63 15 6 67 63 15 6 CRT_TVO_IREF TV_A_DAC TV_B_DAC TV_C_DAC CRT_TVO_IREF TV_A_DAC TV_B_DAC TV_C_DAC 676 63 15 6 MAKE_BASE=TRUE 15 63 67 6 15 63 67 MAKE_BASE=TRUE 67 63 15 6 15 63 6 MAKE_BASE=TRUE 67 6 15 63 67 MAKE_BASE=TRUE 67 63 15 6 CRT_BLUE CRT_BLUE CRT_GREEN CRT_GREEN CRT_RED CRT_RED CRT_HSYNC_R CRT_VSYNC_R CRT_HSYNC_R CRT_VSYNC_R 6 15 63 67 MAKE_BASE=TRUE 6 15 63 67 MAKE_BASE=TRUE Video Connectors 6 15 63 67 MAKE_BASE=TRUE 67 63 15 6 D 67 63 15 6 6 15 63 67 6 15 63 67 MAKE_BASE=TRUE TMDS(MICRO DVI) INTERFACE EXTERNAL VIDEO (VGA) INTERFACE Isolation required for DVI power switch A 1.1UF 10% 2 16V X5R 402 1 0. INC.2 MM SM-LF 0402 1 C9404 PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR CONNECTOR 6 7 37 72 VOLTAGE=5V MIN_LINE_WIDTH=0.

25 mm MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0. SCALE SHT NONE 8 7 6 5 4 3 2 REV.2 mm R9772 MIN_LINE_WIDTH=0.2 mm 5% 1/20W MF 201 LCDBKLT_RTN_RC<2> MIN_LINE_WIDTH=0.2 mm VOLTAGE=0V 2 LCDBKLT_RTN_RC<3> LCDBKLT_RTN<1> 6 7 60 LCDBKLT_RTN<2> 6 7 60 LCDBKLT_RTN<3> 6 7 60 LCDBKLT_RTN<4> 6 7 60 LCDBKLT_RTN<5> 6 7 60 MIN_LINE_WIDTH=0.2 mm 5% 1/20W MF 201 OVP Threshold: 37.3V X5R 2 201 C9750 10% 25V X5R 1206-1 VIN CRITICAL 10UF 10% 25V 2 X5R 603 0.25 mm MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.7UF 10% 50V X7R-CERM 1206 R97551 >2V = ON.9V R97561 78.2 mm 1 1 LCDBKLT_OVP 2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.0.2 mm 5% 1/20W MF 201 XW9750 SM 1 1 1 MIN_LINE_WIDTH=0.20KHz R97661 C9756 4.2 mm 6 C R9771 LCDBKLT_RTN_RC<1> 21 6 75K 1 10% 50V X7R-CERM 1206 1% 1/20W MF 201 2 SW 18 100Hz .5 mm MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.1UF 2 U9750 f=500KHz OZ9956ALN C 6 IN 1 LCDBKLT_ENA QFN 1 ENA LCDBKLT_PWM_UNBUF 20 PWM 6 ISEN1 10 6 LCDBKLT_ISET 8 ISET ISEN2 11 6 5 RT ISEN3 12 6 9 SSTCMP ISEN4 14 6 3 VREF ISEN5 15 6 2 NC1 ISEN6 16 6 ILED[A] = 1500/R9766 6 LCDBKLT_RT FOP[Mhz] = 50000/R9764 1 R9762 10K 1% 1/20W MF 2 201 6 C9763 1 6 LCDBKLT_SSTCMP LCDBKLT_VREF 0.2 mm 6 7 60 1 1000PF 10% 16V X7R 2 201 Place R9771-R9776.2 mm 5% 1/20W MF 201 MIN_LINE_WIDTH=0.7K R9774 1% 1/20W MF 201 2 1 1 2 MIN_LINE_WIDTH=0.001UF 10% 50V CERM 402 NC NC NC NC 2 LCDBKLT_SSTCMP_RC 1 R9764 100K 1% 1/20W MF 2 201 C9762 1 1 0.7UF 2 10% 50V X7R-CERM 1206 1M 10% 10V X5R 402-1 GND_LCDBKLT_GNDA MIN_LINE_WIDTH=0.8 6 7 2 3 4 5 1 D D LED Backlight Driver CRITICAL CRITICAL L9750 72 59 56 50 45 37 8 7 6 PPBUS_G3H 1 63 60 53 25 24 23 22 21 19 16 13 8 7 6 52 51 46 44 42 30 29 28 27 26 D9750 22UH-2. INC. 051-7230 B.2 mm 1 1 LCDBKLT_RTN_RC<4> 2 MIN_LINE_WIDTH=0.5A 1 MIN_LINE_WIDTH=0.2 mm R9773 LCDBKLT_RTN_RC<6> MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.01UF 20% 16V CERM 402 2 6 OVP 6 19 NC4 THRML PAD GNDA C9760 1UF 2 7 NC2 17 NC3 13 1% 1/20W MF 201 2 2 C9757 1 4.25 mm MIN_NECK_WIDTH=0.7UF 2 10% 50V X7R-CERM 1206 C9758 4. <1V = OFF 15 9 6 C9755 4 B 4 60 28 24 7 6 1 4.2 mm 5% 1/20W MF 201 B B R9776 1 1 2 5% 1/20W MF 201 C9771 1000PF 1 10% 16V X7R 2 201 C9772 1 1000PF 10% 16V X7R 2 201 C9773 1000PF 1 10% 16V X7R 2 201 C9774 1000PF 1 10% 16V X7R 2 201 C9775 1 1000PF 10% 16V X7R 2 201 C9776 LCDBKLT_RTN<6> MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm LCDBKLT_RTN_RC<5> MIN_LINE_WIDTH=0.2 mm SWITCH_NODE=TRUE IHLP2525CZ-SM PP3V3_A_S0 PD3S140XF 2 IN LCDBKLT_PWREN 2 IN PLT_RST_L 1 C9740 SOT665 A U9740Y 1 3 1 C9751 1 1UF 10% 6.5 mm MIN_NECK_WIDTH=0.7UF 5 TC7SZ08AFEF 6 7 60 72 MIN_LINE_WIDTH=0.2 mm VOLTAGE=35V 2 PLT_RST_L input ensures backlight ENA does not glitch during RESET.0 OF 64 1 73 A .25 mm MIN_NECK_WIDTH=0. 15 9 6 PPVOUT_S0_LCDBKLT SM PPVOUT_S0_LCDBKLT_SW 2 2 R9775 1 1 2 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.C9771-C9776 close to J9000 LED Backlight Driver A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.

2UF 20% 6.3V CERM 402-LF C9931 20% 6.2UF CRITICAL PLACE ON OPPOSITE SIDE OF CPU 20% 6.2UF 20% 6.3V 2 CERM 402-LF C9982 OMIT 1 2.3V CERM 402-LF CRITICAL 2.3V 2 CERM 402-LF 20% 6.2UF 20% 6. SCALE SHT NONE 8 7 6 5 4 3 2 REV.2UF 20% 6.3V CERM 402-LF OMIT CRITICAL C9906 2. 051-7230 B.3V 2 CERM 402-LF 1 C9986 2.3V 2 CERM 402-LF OMIT 1 OMIT C9985 OMIT 1 2.3V CERM 402-LF OMIT CRITICAL C9909 2.2UF 2.3V 2 CERM 402-LF OMIT C9995 1 2.2UF 20% 6.2UF 20% 6.2UF 20% 6.2UF 20% 6.3V CERM 402-LF OMIT CRITICAL C9904 2.2UF 20% 6.2UF 20% 6.2UF 20% 6.3V CERM 402-LF C9932 20% 6.3V CERM 402-LF CRITICAL 2.3V CERM 402-LF OMIT CRITICAL C9907 2.3V CERM 402-LF OMIT CRITICAL C9905 2.3V 2 CERM 402-LF 2.2UF 2.2UF 20% 6.2UF 20% 6.2UF 20% 6.2UF 2.2UF 20% 6.3V CERM 402-LF 2.3V CERM 402-LF 20% 6.3V CERM 402-LF C9938 20% 6.3V CERM 402-LF C9935 20% 6.2UF CRITICAL 20% 6.2UF 20% 6.2UF 20% 6.2UF 2.2UF 20% 6.2UF C9996 2.2UF 20% 6.3V CERM 402-LF 2.3V 2 CERM 402-LF OMIT 1 C9991 2.2UF CRITICAL OMIT 20% 6.3V CERM 402-LF CRITICAL 2.2UF CRITICAL C9920 CRITICAL 20% 6.3V CERM 402-LF 2.3V 2 CERM 402-LF D C9989 2. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.3V CERM 402-LF OMIT CRITICAL C9908 2.3V CERM 402-LF C9937 20% 6.2UF 20% 6.3V CERM 402-LF C9939 20% 6.2UF 2.2UF 20% 6.2UF 20% 6.2UF 20% 6.3V CERM 402-LF OMIT CRITICAL C9902 2.2UF CRITICAL OMIT 20% 6.2UF 20% 6.3V CERM 402-LF 2.3V CERM 402-LF CRITICAL 2.2UF CRITICAL 2.3V 2 CERM 402-LF OMIT C9987 1 OMIT C9988 1 2.2UF 20% 6.2UF 20% 6.2UF 20% 6.3V 2 CERM 402-LF OMIT 1 C9992 2.3V CERM 402-LF CRITICAL 2.3V CERM 402-LF 2. INC.3V CERM 402-LF B B Additional CPU/GPU Decoupling A SYNC_MASTER= SYNC_DATE= NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.2UF 20% 6.3V CERM 402-LF C9936 20% 6.3V 2 CERM 402-LF OMIT 1 C9993 2.2UF 20% 6.3V CERM 402-LF 2.2UF CRITICAL PLACE ON OPPOSITE SIDE OF CPU 20% 6.2UF 20% 6.2UF 20% 6.3V CERM 402-LF CRITICAL 2.3V 2 CERM 402-LF OMIT C9984 1 1 2.2UF 20% 6.2UF CRITICAL LAYOUT NOTE: 20% 6.3V CERM 402-LF C C OMIT LAYOUT NOTE: OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 2.3V 2 CERM 402-LF OMIT C9994 2.2UF 20% 6.2UF 20% 6.0 OF 65 1 73 A .3V CERM 402-LF CRITICAL 2.3V CERM 402-LF 2.2UF OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT LAYOUT NOTE: C9910 C9911 C9912 C9913 C9914 C9915 C9916 C9917 C9918 C9919 CRITICAL OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT C9921 C9922 C9923 C9924 C9925 C9926 C9927 C9928 C9929 2.2UF 20% 6.3V CERM 402-LF CRITICAL 2.3V 2 CERM 402-LF C9983 OMIT 1 2.2UF 2.2UF C9930 PLACE ON OPPOSITE SIDE OF CPU 20% 6.8 6 7 ADDITIONAL CPU VCORE HF DECOUPLING 18x 1uF 0402 PPVCORE_S0_CPU 72 53 45 22 18 8 7 6 PPVCORE_S0_NB_GFX OMIT D 1 LAYOUT NOTE: OMIT CRITICAL PLACE ON OPPOSITE SIDE OF CPU C9900 2.3V CERM 402-LF OMIT CRITICAL C9901 2.3V 2 CERM 402-LF OMIT 1 CRITICAL 1 ADDITIONAL GPU VCORE HF DECOUPLING 40x 1uF 0402 72 52 12 11 8 7 6 2 3 4 5 OMIT 1 2.3V CERM 402-LF 2.2UF 2.0.3V CERM 402-LF C9933 20% 6.3V CERM 402-LF C9934 20% 6.2UF 20% 6.3V 2 CERM 402-LF OMIT 1 C9990 2.3V CERM 402-LF CRITICAL 2.3V CERM 402-LF 20% 6.3V CERM 402-LF OMIT CRITICAL C9903 2.2UF 20% 6.3V CERM 402-LF C9980 2.2UF 2.3V 2 CERM 402-LF C9981 2.2UF 2.3V 2 CERM 402-LF OMIT 1 C9997 2.2UF 20% 6.

NOTE: Design Guide allows closer spacing if signal lengths can be shortened... Rev 0.0> FSB_DINV_L<0> FSB_DSTB_L_P<0> FSB_DSTB_L_N<0> FSB_D_L<31.ISL10 Y =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD FSB_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM PHYSICAL SPACING FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON TABLE_PHYSICAL_RULE_ITEM FSB_DSTB_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_SPACING_RULE_HEAD D SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FSB_4MIL * ? 0.0 OF 66 1 73 A . (FSB_CPURST_L) SOURCE: Santa Rosa Platform DG.9 (#20517). with 3:1 spacing to the ADSTBs. Design Guide recommends each strobe/signal group is routed on the same layer.8...0> XDP_BPM_L<5> XDP_CLK_P XDP_CLK_N XDP_CPURST_L CPU_VID<6.2 & 4.4 & 5.. Sections 4.0> CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N CPU_THERMD_P CPU_THERMD_N 6 7 10 13 6 7 10 13 6 7 10 13 6 7 10 13 6 7 10 13 6 7 10 13 6 7 10 13 6 7 13 29 30 71 6 7 13 29 30 71 6 7 13 6 11 12 52 12 6 11 52 6 11 52 6 52 6 52 CPU/FSB Constraints 6 10 46 6 10 46 A SYNC_MASTER=T9 SYNC_DATE=01/30/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. >50 mils preferred ? TABLE_SPACING_RULE_ITEM CPU_VCCSENSE * 25 MIL ? TABLE_SPACING_RULE_ITEM CPU_THERMD * ? 25 MIL Most CPU signals with impedance requirements are 55-ohm single-ended.4 FSB_A_L<16. TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CPU_2TO1 * =2:1_SPACING ? CPU_COMP * 25 MIL ? TABLE_SPACING_RULE_ITEM CPU_COMP CPU_27P4S CPU_COMP CPU_COMP CPU_55S CPU_COMP CPU_COMP CPU_27P4S CPU_COMP XDP_TDI CPU_55S CPU_ITP XDP_TDO CPU_55S CPU_ITP XDP_TMS CPU_55S CPU_ITP XDP_TCK CPU_55S CPU_ITP XDP_TRST_L CPU_55S CPU_ITP XDP_BPM_L CPU_55S CPU_ITP XDP_BPM_L5 CPU_55S CPU_ITP CLK_FSB_100D CLK_FSB CLK_FSB_100D CLK_FSB CPU_55S CPU_ITP CPU_55S CPU_2TO1 CPU_55S CPU_2TO1 CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_70D CPU_THERMD CPU_70D CPU_THERMD TABLE_SPACING_RULE_ITEM CPU_GTLREF * 25 MIL ? TABLE_SPACING_RULE_ITEM CPU_ITP * =2:1_SPACING DG recommends at least 25 mils. SCALE SHT NONE 8 7 6 5 4 3 2 REV.32> FSB_DINV_L<2> FSB_DSTB_L_P<2> FSB_DSTB_L_N<2> 10 14 10 14 10 14 10 14 10 14 10 14 10 14 D 10 14 10 14 10 14 10 14 10 14 10 14 6 10 13 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 TABLE_SPACING_ASSIGNMENT_ITEM FSB_ADDR FSB_ADDR * FSB_ADDR2ADDR FSB_ADDR FSB_ADSTB * FSB_ADDR2ADSTB TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM FSB_DATA FSB_DATA * FSB_DATA2DATA FSB_D_L<63..3> FSB_REQ_L<4.0..17> FSB_ADSTB_L<1> CPU_IERR_L CPU_FERR_L CPU_PROCHOT_L CPU_PWRGD CPU_INTR CPU_NMI CPU_A20M_L CPU_DPSLP_L CPU_IGNNE_L CPU_INIT_L CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L PM_DPRSLPVR IMVP_DPRSLPVR CPU_BSEL<0> NB_BSEL<0> CPU_BSEL<1> NB_BSEL<1> CPU_BSEL<2> NB_BSEL<2> CPU_DPRSTP_L CPU_GTLREF CPU_COMP<3> CPU_COMP<2> CPU_COMP<1> CPU_COMP<0> 10 14 10 14 C 10 14 10 14 10 14 6 10 6 10 23 6 10 42 52 6 10 13 23 6 10 23 6 10 23 6 10 23 6 10 23 6 10 23 6 10 23 6 10 23 6 10 23 6 10 16 23 42 10 14 6 16 25 52 6 52 6 10 30 6 7 13 16 30 6 10 30 6 7 13 16 30 6 10 30 6 7 13 16 30 B 6 10 16 23 52 6 10 6 10 6 10 6 10 6 10 XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L<4. Design Guide recommends FSB signals be routed only on internal layers.4-ohm single-ended impedance. Worst-case spacing is 2:1 within Data bus..100 MM TABLE_SPACING_RULE_ITEM FSB_9MIL * 0.16> FSB_DINV_L<1> FSB_DSTB_L_P<1> FSB_DSTB_L_N<1> FSB_D_L<47.0> FSB_ADSTB_L<0> FSB_A_L<35. 051-7230 B.0> IMVP6_VID<6. which Intel says to route with 7 mil spacing without specifying a target differential impedance. DSTB complementary pairs are spaced 1:1 and routed as differential pairs. Worst-case spacing is 2:1 within Addr bus.9 (#20517).8 6 7 LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NET_TYPE ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM FSB_55S ISL3. Sections 4.0> FSB_TRDY_L FSB_CPURST_L FSB_D_L<15. NOTE: Design Guide does not indicate FSB spacing to other signals. Some signals require 27. with 3:1 spacing to the DSTBs.. INC.. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. Rev 0.228 MM ? FSB_DATA * =FSB_4MIL ? FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON TABLE_SPACING_RULE_ITEM FSB_CPURST_L FSB_55S FSB_COMMON TABLE_SPACING_RULE_ITEM FSB_DATA_GROUP0 FSB_55S FSB_DATA FSB_DATA_GROUP0 FSB_55S FSB_DATA FSB_DSTB0 FSB_DSTB_55S FSB_DSTB FSB_DSTB_55S FSB_DSTB FSB_DATA_GROUP1 FSB_55S FSB_DATA FSB_DATA_GROUP1 FSB_55S FSB_DATA FSB_DSTB1 FSB_DSTB_55S FSB_DSTB FSB_DSTB_55S FSB_DSTB FSB_DATA_GROUP2 FSB_55S FSB_DATA FSB_DATA_GROUP2 FSB_55S FSB_DATA FSB_DSTB2 FSB_DSTB_55S FSB_DSTB FSB_DSTB_55S FSB_DSTB FSB_DATA_GROUP3 FSB_55S FSB_DATA FSB_DATA_GROUP3 FSB_55S FSB_DATA FSB_DSTB3 FSB_DSTB_55S FSB_DSTB FSB_DSTB_55S FSB_DSTB FSB_ADDR_GROUP0 FSB_55S FSB_ADDR FSB_ADDR_GROUP0 FSB_55S FSB_ADDR FSB_ADSTB0 FSB_55S FSB_ADSTB FSB_ADDR_GROUP1 FSB_55S FSB_ADDR FSB_ADSTB1 FSB_55S FSB_ADSTB CPU_IERR_L CPU_55S CPU_FERR_L CPU_55S CPU_PROCHOT_L CPU_55S CPU_PWRGD CPU_55S CPU_FROM_SB CPU_55S CPU_FROM_SB CPU_55S CPU_FROM_SB CPU_55S CPU_FROM_SB CPU_55S CPU_FROM_SB CPU_55S CPU_INIT_L CPU_55S CPU_FROM_SB CPU_55S CPU_FROM_SB CPU_55S PM_THRMTRIP_L CPU_55S FSB_CPUSLP_L CPU_55S PM_DPRSLPVR CPU_55S CPU_2TO1 (See above) CPU_55S CPU_2TO1 CPU_BSEL0 CPU_55S CPU_2TO1 (See above) CPU_55S CPU_2TO1 CPU_BSEL1 CPU_55S CPU_2TO1 (See above) CPU_55S CPU_2TO1 CPU_BSEL2 CPU_55S CPU_2TO1 (See above) CPU_55S CPU_2TO1 TABLE_PHYSICAL_RULE_ITEM CPU_DPRSTP_L CPU_55S CPU_2TO1 TABLE_PHYSICAL_RULE_ITEM CPU_GTLREF CPU_55S CPU_GTLREF CPU_55S CPU_COMP TABLE_SPACING_RULE_ITEM FSB_DATA2DATA * =FSB_4MIL ? FSB_DSTB * =FSB_9MIL ? TABLE_SPACING_RULE_ITEM FSB_DATA2DSTB * =FSB_9MIL ? TABLE_SPACING_RULE_ITEM FSB_ADDR * =FSB_4MIL ? TABLE_SPACING_RULE_ITEM FSB_ADDR2ADDR * =FSB_4MIL ? FSB_ADSTB * =FSB_9MIL ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM FSB_ADDR2ADSTB * =FSB_9MIL ? TABLE_SPACING_RULE_ITEM FSB_COMMON * =FSB_4MIL ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE 1 CPU / FSB Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET 2 3 4 5 FSB (Front-Side Bus) Constraints SPACING_RULE_SET FSB_ADS_L FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_RS_L<2.3 CPU Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? CPU_27P4S * Y MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE 7 MIL 7 MIL CPU_2TO1 CPU_2TO1 TABLE_PHYSICAL_RULE_ITEM B CPU_55S * CPU_70D * SPACING_RULE_SET LAYER Y =55_OHM_SE Y =55_OHM_SE =70_OHM_DIFF =70_OHM_DIFF =55_OHM_SE =70_OHM_DIFF =STANDARD =70_OHM_DIFF =STANDARD =70_OHM_DIFF CPU_COMP NOTE: 7 mil gap is for VCCSense pair. SOURCE: Santa Rosa Platform DG..48> FSB_DINV_L<3> FSB_DSTB_L_P<3> FSB_DSTB_L_N<3> 10 14 10 14 10 14 10 14 TABLE_SPACING_ASSIGNMENT_ITEM FSB_DATA C FSB_DSTB * FSB_DATA2DSTB All FSB signals with impedance requirements are 55-ohm single-ended.2. assumed 3:1.

.0> PEG_R2D_N<15.0> DMI_S2N_N<3.0> TMDS_CONN_N<3.0> TMDS_TX_P<3.228 MM ? PCIE_D2R_2_PCIE_D2R * 0. CRT & TVDAC signal single-ended impedence varies by location: .. NB Constraints SYNC_MASTER=T9 SOURCE: Santa Rosa Platform DG..0> PEG_D2R_N<15..3.0> D 6 16 24 6 16 24 6 16 24 6 16 24 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PCIE_R2D 6 15 61 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM PCIE_R2D_2_PCIE_D2R PEG_R2D_P<15.0> BUS2PWR_GND LVDS_IBG LVDS CRT_TVO_IREF CRT LVDS_A_CLK_P LVDS_A_CLK_N LVDS_A_DATA_P<2.0 OF 67 1 73 A .0> LVDS_A_DATA_F_P<2.0> NC_LVDS_B_DATA_P3 NC_LVDS_B_DATA_N3 LVDS_IBG 6 15 60 6 15 60 6 7 15 60 6 7 15 60 6 60 6 60 9 9 9 15 9 15 9 9 6 15 60 TABLE_SPACING_ASSIGNMENT_ITEM DMI_S2N PWR * BUS2PWR_GND DMI_S2N GND * BUS2PWR_GND LVDS PWR * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM CRT_RED CRT_50S CRT CRT_GREEN CRT_50S CRT CRT_BLUE CRT_50S CRT CRT_SYNC CRT_55S CRT_SYNC CRT_SYNC CRT_55S CRT_SYNC TV_A_DAC CRT_50S TVDAC TV_B_DAC CRT_50S TVDAC TV_C_DAC CRT_50S TVDAC TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM LVDS C GND * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM TMDS PWR * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM TMDS GND * BUS2PWR_GND EXT_COMPVID_B CRT_50S CRT EXT_Y_G CRT_50S CRT EXT_C_R CRT_50S CRT VGA_R CRT_50S CRT VGA_G CRT_50S CRT VGA_B CRT_50S CRT PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D TMDS_100D TMDS TMDS_100D TMDS PCIE_100D PCIE_D2R PCIE_100D PCIE_D2R TMDS_100D TMDS TMDS_100D TMDS TMDS_100D TMDS TMDS_100D TMDS TMDS_100D TMDS TMDS_100D TMDS SMB_55S SMB SMB_55S SMB Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CRT_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD CRT_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TMDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM LVDS * 20 MIL ? CRT * 25 MIL ? TABLE_SPACING_RULE_ITEM B DG Says 40 mil spacing minimum TABLE_SPACING_RULE_ITEM CRT_2CRT * 20 MIL ? TABLE_SPACING_RULE_ITEM CRT_SYNC * 25 MIL ? CRT_SYNC2SYNC * 20 MIL ? DG Says 30 mil spacing minimum CRT_TVO_IREF CRT_RED CRT_GREEN CRT_BLUE CRT_HSYNC_R CRT_VSYNC_R TV_A_DAC TV_B_DAC TV_C_DAC EXT_COMPVID_B EXT_Y_G EXT_C_R VGA_R VGA_G VGA_B TMDS_SDB_P TMDS_SDB_N TMDS_SDC_P TMDS_SDC_N TMDS_SDG_P TMDS_SDG_N TMDS_SDR_P TMDS_SDR_N TMDS_TX_CLK_P TMDS_TX_CLK_N TMDS_INT_P TMDS_INT_N TMDS_TX_CONN_CLK_P TMDS_TX_CONN_CLK_N TMDS_CONN_P<3. 051-7230 B.37.0> LVDS_A_DATA_F_N<2..0> PEG_R2D_C_N<15.300 MM DMI_S2N TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_ASSIGNMENT_HEAD SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM PCIE_R2D PCIE_R2D * PCIE_R2D_2_PCIE_R2D PCIE_D2R PCIE_D2R * PCIE_D2R_2_PCIE_D2R DMI_N2S DMI_N2S * DMI_N2S_2_DMI_N2S DMI_S2N DMI_S2N * DMI_S2N_2_DMI_S2N TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PCIE_D2R * TABLE_SPACING_ASSIGNMENT_ITEM DMI_N2S PCIE_R2D_2_PCIE_D2R DMI_S2N * DMI_N2S_2_DMI_S2N TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET PCIE_R2D PWR * BUS2PWR_GND PCIE_R2D GND * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PCIE_D2R PWR * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM PCIE_D2R GND * BUS2PWR_GND DMI_N2S PWR * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM DMI_N2S GND * 6 15 61 6 15 61 6 15 61 DMI_N2S_P<3.15% from first to second termination resistor.228 MM ? DMI_N2S_2_DMI_S2N * 0.15% from second termination resistor to connector.0> PEG_D2R_C_P<15. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.0> NC_LVDS_A_DATA_P3 NC_LVDS_A_DATA_N3 NC_LVDS_B_CLK_P NC_LVDS_B_CLK_N LVDS_B_DATA_P<2.0> TMDS_DDC_SCL TMDS_DDC_SDA 6 15 63 6 15 63 6 15 63 6 15 63 6 15 63 6 15 63 C 6 15 63 6 15 63 6 15 63 6 63 6 63 6 63 6 7 37 63 6 7 37 63 6 7 37 63 6 61 6 61 6 61 6 61 6 61 6 61 6 61 6 61 6 61 63 6 61 63 6 61 6 61 6 7 37 63 6 7 37 63 6 61 63 B 6 61 63 6 7 37 61 62 63 6 7 37 61 62 63 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TVDAC * 25 MIL ? TVDAC_2TVDAC * 20 MIL ? LVDS2LVDS * 0. Rev 1.0> PEG_R2D_C_P<15...0> PEG_D2R_C_N<15.15% single-ended impedence..0 (#21112). Sections 8..0> DMI_S2N_P<3..8...50-ohm +/.8 6 7 2 3 4 5 1 PCI-Express / DMI Bus Constraints NET_TYPE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM PEG_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_D2R PCIE_100D PCIE_D2R PCIE_100D PCIE_D2R PCIE_100D PCIE_D2R TABLE_PHYSICAL_RULE_ITEM DMI_100D * SPACING_RULE_SET LAYER =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCIE * 20 MIL TABLE_SPACING_RULE_ITEM ? DMI_N2S_2_DMI_N2S * ? 0..0> PEG_D2R_P<15.20% differential impedence.300 MM ? TABLE_SPACING_RULE_ITEM * DMI_N2S DMI_100D DMI_N2S DMI_100D DMI_N2S DMI_100D DMI_S2N DMI_100D DMI_S2N LVDS_A_CLK LVDS_100D LVDS LVDS_A_CLK LVDS_100D LVDS LVDS_A_DATA LVDS_100D LVDS LVDS_A_DATA LVDS_100D LVDS LVDS_A_DATA LVDS_100D LVDS LVDS_A_DATA LVDS_100D LVDS LVDS_A_DATA3 LVDS_100D LVDS LVDS_A_DATA3 LVDS_100D LVDS LVDS_B_CLK LVDS_100D LVDS LVDS_B_CLK LVDS_100D LVDS LVDS_B_DATA LVDS_100D LVDS LVDS_B_DATA LVDS_100D LVDS LVDS_B_DATA3 LVDS_100D LVDS LVDS_B_DATA3 LVDS_100D LVDS ? 0. SYNC_DATE=01/30/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. SCALE SHT NONE 8 7 6 5 4 3 2 REV. CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/.0....0> DMI_N2S_N<3....5-ohm +/.1 .300 MM ? TMDS * 20 MIL ? DG Says 40 mil spacing minimum TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CRT CRT * CRT_2CRT CRT_SYNC CRT_SYNC * CRT_SYNC2SYNC TVDAC TVDAC * TVDAC_2TVDAC LVDS LVDS * LVDS2LVDS TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM A LVDS signals are 100-ohm +/.0> TMDS_TX_N<3.228 MM TABLE_SPACING_RULE_ITEM D PCIE_R2D_2_PCIE_R2D * 0..... .228 MM ? PEG_D2R TABLE_SPACING_RULE_ITEM DMI_S2N_2_DMI_S2N * 0.55-ohm +/.0> LVDS_B_DATA_N<2.0> LVDS_A_DATA_N<2.15% from GMCH to first termination resistor. INC.

ISL10 =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD MEM_CLK_P<2..16> MEM_A_DQ<31.28:1_SPACING ? MEM_CLK PP1V8_MEM * * =2.0> 16 31 33 16 31 33 6 16 31 33 TABLE_PHYSICAL_RULE_ITEM MEM_85D * =85_OHM_DIFF SPACING_RULE_SET LAYER =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_SPACING_RULE_HEAD D LINE-TO-LINE SPACING TABLE_SPACING_ASSIGNMENT_HEAD WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * =2. 051-7230 B.24> MEM_A_DQ<39...0....0> 16 31 33 16 31 33 TABLE_PHYSICAL_RULE_ITEM MEM_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MEM_87D * =87_OHM_DIFF =87_OHM_DIFF =87_OHM_DIFF =87_OHM_DIFF =87_OHM_DIFF =87_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM MEM_CKE<1..0> MEM_A_DQ<15...24> MEM_B_DQ<39..16> MEM_B_DQ<31.48> MEM_B_DQ<63.0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM MEM_2OTHER PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM MEM_DQS2MEM GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM MEM_DATA2MEM GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM MEM_CMD2MEM SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM ? MEM_CTRL2CTRL =85_OHM_DIFF SCALE SHT NONE 6 5 4 3 2 REV..0> MEM_A_BS<2...0> MEM_CLK_N<2.56> 17 31 33 17 31 33 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_A_A<13. NET_SPACING_TYPE=GND 7 17 32 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART I101 GND 17 31 33 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL D 17 31 33 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DQS2MEM MEM_A_DQS7 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_A_DQ<7..48> MEM_A_DQ<63..3> MEM_CS_L<3.0> MEM_B_BS<2.0> MEM_ODT<1...0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L 16 32 33 16 32 33 6 16 32 33 17 32 33 17 32 33 17 32 33 17 32 33 MEM_B_DQS7 MEM_B_DQ<7.28:1_SPACING TABLE_SPACING_ASSIGNMENT_ITEM ? MEM_DQS GND * TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * =1:1_SPACING * =2.2> MEM_ODT<3.3> MEM_CLK_N<5...3> 17 31 17 31 17 31 17 31 17 31 17 31 C 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 16 32 33 16 32 33 MEM_CKE<4. INC.28:1_SPACING ? MEM_CTRL PP1V8_MEM * * 25 MIL PWR_P2MM ? MEM_DATA PP1V8_MEM * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM ? MEM_DQS PP1V8_MEM * PWR_P2MM MEM_CMD PP1V8_MEM * PWR_P2MM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK * * MEM_2OTHER MEM_CTRL * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK NB_STATIC * PWR_P2MM MEM_CTRL NB_STATIC * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * * MEM_2OTHER MEM_DATA * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA NB_STATIC * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM * * MEM_2OTHER NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK MEM_CLK * MEM_CLK2MEM MEM_CLK MEM_CTRL * MEM_CLK2MEM MEM_A_DQS1 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS NB_STATIC * TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD NB_STATIC * PWR_P2MM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM C TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_A_DQS4 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CLK MEM_DATA * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CTRL * MEM_DQS2MEM MEM_DQS MEM_CMD * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS5 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_DQS * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_A_DQS6 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK * MEM_CMD2MEM MEM_CMD MEM_CTRL * MEM_CMD2MEM MEM_DQS MEM_DQS * Need to support MEM_*-style wildcards! TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_CMD MEM_DATA * MEM_CMD2MEM * MEM_CMD2MEM SPACING_RULE_SET MEM_CLK PWR * BUS2PWR_GND MEM_CLK GND * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL PWR * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL GND * BUS2PWR_GND MEM_CMD PWR * BUS2PWR_GND MEM_CMD GND * BUS2PWR_GND MEM_DATA PWR * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CLK * MEM_CTRL2MEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA GND * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS PWR * BUS2PWR_GND MEM_DQS GND * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM B MEM_CTRL MEM_DQS * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CTRL * MEM_DATA2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DATA * MEM_DATA2DATA MEM_DATA MEM_DQS * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS4 A I93 PP0V9_S3M_MEM_NBVREFB NET_SPACING_TYPE=NB_STATIC 8 16 21 I95 PP0V9_S3M_MEM_NBVREFA NET_SPACING_TYPE=NB_STATIC 8 16 21 MEM_B_DQS5 MEM_B_DQS6 I94 NB_VCCSM_LF1 NET_SPACING_TYPE=NB_STATIC 6 18 I96 NB_VCCSM_LF2 NET_SPACING_TYPE=NB_STATIC 6 18 I97 NB_VCCSM_LF3 NET_SPACING_TYPE=NB_STATIC 6 18 I98 NB_VCCSM_LF4 NET_SPACING_TYPE=NB_STATIC 6 18 I99 NB_VCCSM_LF5 NET_SPACING_TYPE=NB_STATIC 6 18 NB_VCCSM_LF6 NET_SPACING_TYPE=NB_STATIC 6 18 I103 NB_VCCSM_LF7 NET_SPACING_TYPE=NB_STATIC 6 18 I102 PP1V8_S3 NET_SPACING_TYPE=PP1V8_MEM 8 17 31 33 17 31 17 31 17 31 17 31 17 31 17 31 17 31 MEM_A_DM<0> MEM_A_DM<1> MEM_A_DM<2> MEM_A_DM<3> MEM_A_DM<4> MEM_A_DM<5> MEM_A_DM<6> MEM_A_DM<7> 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7> 17 31 MEM_CLK_P<5.32> MEM_B_DQ<47..56> 17 32 33 MEM_B_DM<0> MEM_B_DM<1> MEM_B_DM<2> MEM_B_DM<3> MEM_B_DM<4> MEM_B_DM<5> MEM_B_DM<6> MEM_B_DM<7> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7> 17 32 17 32 17 32 B 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 Memory Constraints 17 32 17 32 SYNC_MASTER=T9 SYNC_DATE=01/30/2007 17 32 NOTICE OF PROPRIETARY PROPERTY 17 32 17 32 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER....0> MEM_CS_L<1..28:1_SPACING ? MEM_CMD2CMD * =1:1_SPACING ? MEM_CMD GND * GND_P2MM MEM_CTRL GND * GND_P2MM MEM_DATA GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM * =2.8> MEM_B_DQ<23...8 6 7 DDR2 Memory Bus Constraints 2 3 4 5 1 Memory Net Properties NET_TYPE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MEM_87D MEM_CLK MEM_87D MEM_CLK MEM_45S MEM_CTRL MEM_45S MEM_CTRL MEM_45S MEM_CTRL MEM_A_CMD MEM_55S MEM_CMD MEM_A_CMD MEM_55S MEM_CMD MEM_A_CMD MEM_55S MEM_CMD MEM_A_CMD MEM_55S MEM_CMD MEM_A_CMD MEM_55S MEM_CMD MEM_A_DQ_BYTE0 MEM_55S MEM_DATA MEM_A_DQ_BYTE1 MEM_55S MEM_DATA MEM_A_DQ_BYTE2 MEM_55S MEM_DATA MEM_A_DQ_BYTE3 MEM_55S MEM_DATA MEM_A_DQ_BYTE4 MEM_55S MEM_DATA MEM_A_DQ_BYTE5 MEM_55S MEM_DATA MEM_A_DQ_BYTE6 MEM_55S MEM_DATA MEM_A_DQ_BYTE7 MEM_55S MEM_DATA MEM_A_DM0 MEM_55S MEM_DATA MEM_A_DM1 MEM_55S MEM_DATA MEM_A_DM2 MEM_55S MEM_DATA MEM_A_DM3 MEM_55S MEM_DATA MEM_A_DM4 MEM_55S MEM_DATA MEM_A_DM5 MEM_55S MEM_DATA MEM_A_DM6 MEM_55S MEM_DATA MEM_A_DM7 MEM_55S MEM_DATA MEM_A_DQS0 MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_A_DQS2 MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_A_DQS3 MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_87D MEM_CLK MEM_87D MEM_CLK MEM_45S MEM_CTRL MEM_45S MEM_CTRL MEM_45S MEM_CTRL MEM_B_CMD MEM_55S MEM_CMD MEM_B_CMD MEM_55S MEM_CMD MEM_B_CMD MEM_55S MEM_CMD MEM_B_CMD MEM_55S MEM_CMD MEM_B_CMD MEM_55S MEM_CMD MEM_B_DQ_BYTE0 MEM_55S MEM_DATA MEM_B_DQ_BYTE1 MEM_55S MEM_DATA MEM_B_DQ_BYTE2 MEM_55S MEM_DATA MEM_B_DQ_BYTE3 MEM_55S MEM_DATA MEM_B_DQ_BYTE4 MEM_55S MEM_DATA MEM_B_DQ_BYTE5 MEM_55S MEM_DATA MEM_B_DQ_BYTE6 MEM_55S MEM_DATA MEM_B_DQ_BYTE7 MEM_55S MEM_DATA MEM_B_DM0 MEM_55S MEM_DATA MEM_B_DM1 MEM_55S MEM_DATA MEM_B_DM2 MEM_55S MEM_DATA MEM_B_DM3 MEM_55S MEM_DATA MEM_B_DM4 MEM_55S MEM_DATA MEM_B_DM5 MEM_55S MEM_DATA MEM_B_DM6 MEM_55S MEM_DATA MEM_B_DM7 MEM_55S MEM_DATA MEM_B_DQS0 MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS TABLE_PHYSICAL_RULE_ITEM MEM_55S ISL3.8> MEM_A_DQ<23.. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT SIZE DRAWING NUMBER D 6 7 8 16 18 21 31 32 34 35 51 55 72 APPLE INC...0 OF 68 1 73 A .0> MEM_B_DQ<15.32> MEM_A_DQ<47.28:1_SPACING MEM_CLK GND * TABLE_SPACING_RULE_ITEM * =1:1_SPACING ? MEM_CTRL2MEM * =2..40> MEM_B_DQ<55.2> MEM_B_A<13.40> MEM_A_DQ<55.

9 HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SATA_A_D2R TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =1. 051-7230 B.9 (#17978).7 & 10.0 (#21112).. THE POSSESSOR AGREES TO THE FOLLOWING 6 24 43 49 6 49 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 6 24 49 SIZE 6 43 49 DRAWING NUMBER D 6 24 43 APPLE INC. Section 10.8:1_SPACING ? TABLE_SPACING_RULE_ITEM IDE D * TABLE_SPACING_RULE_ITEM SATA * 20 MIL ? SOURCE: Santa Rosa Platform DG. Section 10.9..8 6 7 Disk Interface Constraints 2 3 4 5 1 NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP IDE_PDD IDE_55S IDE IDE_PDA IDE_55S IDE IDE_PDCS IDE_55S IDE IDE_PDCS IDE_55S IDE IDE_CNTL IDE_55S IDE IDE_PDIOR_L IDE_55S IDE IDE_CNTL IDE_55S IDE IDE_CNTL IDE_55S IDE IDE_PDIORDY IDE_55S IDE IDE_IRQ14 IDE_55S IDE IDE_RST_L IDE_55S IDE SATA_A_R2D SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D GND SATA_100D GND SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D GND SATA_100D GND SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D GND SATA_100D GND SATA_100D SATA SATA_100D SATA TABLE_PHYSICAL_RULE_ITEM IDE_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM SATA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =1.0> IDE_PDCS1_L IDE_PDCS3_L IDE_PDIOW_L IDE_PDIOR_L IDE_PDDACK_L IDE_PDDREQ IDE_PDIORDY IDE_IRQ14 ODD_RST_5VTOL_L NC_SATA_A_R2D_C_P NC_SATA_A_R2D_C_N SATA_A_R2D_P SATA_A_R2D_N NC_SATA_A_D2R_P NC_SATA_A_D2R_N SATA_A_D2R_C_P SATA_A_D2R_C_N NC_SATA_B_R2D_C_P NC_SATA_B_R2D_C_N SATA_B_R2D_P SATA_B_R2D_N NC_SATA_B_D2R_P NC_SATA_B_D2R_N SATA_B_D2R_C_P SATA_B_D2R_C_N NC_SATA_C_R2D_C_P NC_SATA_C_R2D_C_N SATA_C_R2D_P SATA_C_R2D_N NC_SATA_C_D2R_P NC_SATA_C_D2R_N SATA_C_D2R_C_P SATA_C_D2R_C_N SATA_RBIAS HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_L HDA_RST_L_R HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R USB2_EXTA_P USB2_EXTA_N USB2_MUXED_EXTA_N USB2_MUXED_EXTA_P USB2_AIRPORT_P USB2_AIRPORT_N TP_USB2_3G_P TP_USB2_3G_N USB2_CAMERA_P USB2_CAMERA_N NC_USB_BT_P NC_USB_BT_N USB2_WSPRING_P USB2_WSPRING_N USB_IR_P USB_IR_N NC_USB2_EXTB_P NC_USB2_EXTB_N TP_USB_EXCARD_P TP_USB_EXCARD_N TP_USB_EXTC_P TP_USB_EXTC_N USB2_AIRPORT_P_F USB2_AIRPORT_N_F USB2_CAMERA_F_P USB2_CAMERA_F_N USB2_EXTA_F_P USB2_EXTA_F_N USB2_3G_F_P USB2_3G_F_N USB_RBIAS SMBUS_SB_SCL SMBUS_SB_SDA SMBUS_SB_ME_SCL SMBUS_SB_ME_SDA SPI_SCLK_R SPI_SCLK SPI_A_SCLK_R SPI_B_SCLK_R SPI_SI_R SPI_SI SPI_A_SI_R SPI_B_SI_R SPI_SO SPI_A_SO_R SPI_B_SO SPI_B_SO_R SPI_CE_R_L<0> SPI_CE_L<0> SPI_CE_R_L<1> SPI_CE_L<1> 6 23 38 6 23 38 6 23 38 6 23 38 6 23 38 6 23 38 6 23 38 6 23 38 6 23 38 D 6 23 38 9 23 9 23 9 9 9 23 9 23 9 9 9 23 9 23 9 9 C 6 7 9 23 37 6 23 6 7 9 23 37 6 23 6 9 23 37 6 23 6 7 9 23 37 6 7 9 23 37 6 23 6 9 24 39 6 9 24 39 6 9 39 6 9 39 6 9 24 36 6 9 24 36 9 24 9 24 6 9 24 60 6 9 24 60 9 24 9 24 6 7 9 24 40 6 7 9 24 40 B 6 7 9 24 40 6 7 9 24 40 9 24 9 24 9 24 9 24 9 24 9 24 6 36 6 36 6 7 60 6 7 60 6 7 37 39 6 7 37 39 6 24 6 25 29 44 6 25 29 44 6 25 44 6 25 44 6 24 49 6 43 49 SB Constraints (1 of 2) 6 24 49 SYNC_MASTER=T9 SYNC_DATE=01/30/2007 NOTICE OF PROPRIETARY PROPERTY 6 43 49 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. Sections 10. Rev 1. INC. Rev 1.17 B USB_IR USB_EXTB USB_EXCARD USB_EXTC USB_RBIAS USB_60S SMB_SB_SCL SMB_55S SMB SMB_SB_SDA SMB_55S SMB SMB_SB_ME_SCL SMB_55S SMB SMB_SB_ME_SDA SMB_55S SMB SPI_SCLK SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_SI A SPI_SO SPI_CE_L0 SPI_CE_L1 IDE_PDD<15. Rev 0.0 OF 69 1 73 A .0.8:1_SPACING ? SATA_B_R2D TABLE_SPACING_RULE_ITEM HDA * SOURCE: Napa Platform DG.8:1_SPACING ? USB_TPAD SOURCE: Santa Platform DG.0 (#21112). SCALE SHT NONE 8 7 6 5 4 3 2 REV.0> IDE_PDA<2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? USB_60S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_C_R2D TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM SATA_A_D2R TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 20 MIL ? TABLE_SPACING_RULE_ITEM USB * TABLE_SPACING_RULE_ITEM C USB_2CLK * 25 MIL ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET SATA_RBIAS SATA_55S HDA_BIT_CLK HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB TABLE_SPACING_ASSIGNMENT_ITEM USB PWR * BUS2PWR_GND USB GND * BUS2PWR_GND HDA_SYNC TABLE_SPACING_ASSIGNMENT_ITEM HDA_RST_L HDA_SDIN0 HDA_SDOUT Internal Interface Constraints USB_EXTA TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_MINI TABLE_PHYSICAL_RULE_ITEM SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_EXTD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_CAMERA TABLE_SPACING_RULE_ITEM SMB * =3:1_SPACING ? USB_BT TABLE_SPACING_RULE_ITEM SPI * =1.1 SATA_A_D2R USB 2.

10.29 & 10.1.5-7. Sections 10. SCALE SHT NONE 8 7 6 5 4 3 2 REV....1 & 10. Sections 10.21> NC_PCI_PAR PCI_C_BE_L<3.0> LAN_D2R<2.30 GLAN_COMP ENET_KBIAS ENET_RBIAS (PCIE_ENET_R2D) (PCIE_ENET_D2R) B GLAN_100D ENET_GLAN GLAN_100D ENET_GLAN GLAN_100D ENET_GLAN GLAN_100D ENET_GLAN ENET_LAN LAN_55S ENET_LAN ENET_LAN LAN_55S ENET_LAN ENET_LAN LAN_55S ENET_LAN ENET_GLAN_CLK LAN_55S ENET_CLK LAN_55S ENET_CLK ENET_MDI0 ENET_100D ENET_MDI ENET_100D ENET_MDI ENET_100D ENET_MDI ENET_100D ENET_MDI ENET_100D ENET_MDI ENET_100D ENET_MDI ENET_100D ENET_MDI ENET_100D ENET_MDI CLINK_NB CLINK_55S CLINK CLINK_NB CLINK_55S CLINK CLINK_NB_RESET_L CLINK_55S CLINK CLINK_WLAN CLINK_55S CLINK CLINK_WLAN CLINK_55S CLINK CLINK_WLAN_RESET_L CLINK_55S CLINK NB_CLINK_VREF CLINK_12MIL CLINK_VREF SB_CLINK_VREF0 CLINK_12MIL CLINK_VREF SB_CLINK_VREF1 CLINK_12MIL CLINK_VREF ENET_MDI1 ENET_MDI2 ENET_MDI3 PCIE_A_R2D_C_P PCIE_A_R2D_C_N PCIE_A_D2R_P PCIE_A_D2R_N PCIE_B_R2D_C_P PCIE_B_R2D_C_N PCIE_B_D2R_P PCIE_B_D2R_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_E_R2D_C_P PCIE_E_R2D_C_N PCIE_E_D2R_P PCIE_E_D2R_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N GLAN_COMP NINEVEH_KBIAS_P NINEVEH_RBIAS ENET_GLAN_R2D_P ENET_GLAN_R2D_N ENET_GLAN_D2R_C_P ENET_GLAN_D2R_C_N LAN_RSTSYNC LAN_R2D<2. 10.5:1_SPACING ? ENET_GLAN * 20 MILS ? PCIE_B_R2D TABLE_SPACING_RULE_ITEM PCIE_B_D2R TABLE_SPACING_RULE_ITEM ENET_LAN C * =1.19 Platform LAN (Nineveh) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM LAN_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM ENET_100D * =100_OHM_DIFF GLAN_100D * =100_OHM_DIFF SPACING_RULE_SET LAYER =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCI_AD<18.5-7.27.8 6 7 2 3 4 5 1 PCI Bus Constraints NET_TYPE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM PCI_AD PCI_55S PCI PCI_AD19 PCI_55S PCI PCI_AD20 PCI_55S PCI PCI_AD PCI_55S PCI PCI_AD PCI_55S PCI PCI_C_BE_L PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_LOCK_L PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_FW_REQ_L PCI_55S PCI PCI_FW_GNT_L PCI_55S PCI PCI_REQ1_L PCI_55S PCI PCI_GNT1_L PCI_55S PCI PCI_REQ2_L PCI_55S PCI PCI_GNT2_L PCI_55S PCI INT_PIRQA_L PCI_55S PCI INT_PIRQB_L PCI_55S PCI INT_PIRQC_L PCI_55S PCI INT_PIRQD_L PCI_55S PCI INT_PIRQE_L PCI_55S PCI INT_PIRQF_L PCI_55S PCI PCIE_A_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_D2R PCIE_100D PCIE_D2R PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_D2R PCIE_100D PCIE_D2R PCIE_100D PCIE_R2D PCIE_100D PCIE_R2D PCIE_100D PCIE_D2R PCIE_100D PCIE_D2R TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCI * =2:1_SPACING ? TABLE_SPACING_RULE_ITEM PCIE_R2D * ? =PCIE TABLE_SPACING_RULE_ITEM D PCIE_D2R * =PCIE ? PCIE_9MIL * 0..30 Controller Link (AMT) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CLINK_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLINK_12MIL * =STANDARD 12 MILS 5 MILS 300 MILS =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM PCIE_MINI_R2D TABLE_PHYSICAL_RULE_ITEM PCIE_MINI_D2R TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLINK * =1.0.0> NC_PCI_AD<19> NC_PCI_AD<20> PCI_AD<31. Rev 1.18.0 (#21112).29 & 10. Rev 1. INC. ? SOURCE: Santa Rosa Platform DG.0 (#21112).0> PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_LOCK_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_FW_REQ_L PCI_FW_GNT_L PCI_REQ1_L PCI_GNT1_L PCI_REQ2_L PCI_GNT2_L INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L INT_PIRQE_L INT_PIRQF_L 9 9 24 9 24 9 9 24 9 6 24 D 6 24 6 24 6 24 6 24 6 24 6 24 6 24 6 24 6 24 6 24 6 24 6 24 6 24 6 24 6 24 6 24 6 24 TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT PCIE_A_D2R TABLE_SPACING_RULE_ITEM ENET_CLK * =2.228 MM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM PCIE_12MIL * ? 0.0> ENET_GLAN_CLK_R ENET_GLAN_CLK ENET_MDI_P<0> ENET_MDI_N<0> ENET_MDI_P<1> ENET_MDI_N<1> ENET_MDI_P<2> ENET_MDI_N<2> ENET_MDI_P<3> ENET_MDI_N<3> CLINK_NB_CLK CLINK_NB_DATA CLINK_NB_RESET_L CLINK_WLAN_CLK CLINK_WLAN_DATA CLINK_WLAN_RESET_L NB_CLINK_VREF SB_CLINK_VREF0 SB_CLINK_VREF1 C 6 24 36 6 24 36 6 24 36 6 24 36 6 23 B 6 16 25 6 16 25 6 16 25 6 16 6 25 6 25 SB Constraints (2 of 2) A SYNC_MASTER=T9 SYNC_DATE=01/30/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.5:1_SPACING ? TABLE_SPACING_RULE_ITEM ENET_MDI * 25 MILS DG says 30 mils min separation. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC. Sections 10.8:1_SPACING ? CLINK_VREF * 12 MILS ? TABLE_SPACING_RULE_ITEM SOURCE: Santa Rosa Platform DG.1.27. Rev 1. 051-7230 B.0 OF 70 1 73 A .300 MM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM PCIE_R2D PCIE_R2D * PCIE_9MIL PCIE_D2R PCIE_D2R * PCIE_9MIL TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PCIE_D2R PCIE_R2D * PCIE_12MIL SOURCE: Santa Rosa Platform DG.0 (#21112)..

0.8 6 7 Clock Signal Constraints 2 3 4 5 1 Clock Net Properties NET_TYPE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM CK505_CPU CLK_FSB_100D CLK_FSB CK505_CPU CLK_FSB_100D CLK_FSB CK505_NB CLK_FSB_100D CLK_FSB CK505_NB CLK_FSB_100D CLK_FSB CK505_ITP CLK_FSB_100D CLK_FSB CK505_ITP CLK_FSB_100D CLK_FSB CK505_PCIF0 CLK_MED_55S CLK_MED CK505_PCIF1 CLK_MED_55S CLK_MED CK505_PCI1 CLK_MED_55S CLK_MED CK505_PCI2 CLK_MED_55S CLK_MED CK505_PCI3 CLK_MED_55S CLK_MED CK505_PCI4 CLK_MED_55S CLK_MED CK505_PCI5 CLK_MED_55S CLK_MED (CPU_BSEL0) (CPU_BSEL2) CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED CK505_DOT96 CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE (CK505_CPU) (CK505_CPU) (CK505_NB) (CK505_NB) (CK505_ITP) (CK505_ITP) CLK_FSB_100D CLK_FSB CLK_FSB_100D CLK_FSB CLK_FSB_100D CLK_FSB CLK_FSB_100D CLK_FSB CLK_FSB_100D CLK_FSB CLK_FSB_100D CLK_FSB (CK505_PCIF0) (CK505_PCIF1) (CK505_PCI1) (CK505_PCI2) (CK505_PCI3) CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED TABLE_PHYSICAL_RULE_ITEM CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM CLK_MED_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_NB_P FSB_CLK_NB_N XDP_CLK_P XDP_CLK_N 6 10 29 30 71 6 10 29 30 71 6 14 29 30 71 6 14 29 30 71 6 7 13 29 30 66 71 6 7 13 29 30 66 71 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER LINE-TO-LINE SPACING WEIGHT 25 MIL ? TABLE_SPACING_RULE_ITEM CLK_FSB * TABLE_SPACING_RULE_ITEM CLK_PCIE * 20 MIL ? CLK_MED * 20 MIL ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CLK_SLOW * 10 MIL ? SOURCE: Santa Rosa Platform DG. THE POSSESSOR AGREES TO THE FOLLOWING 6 41 44 48 6 41 44 48 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.6 CK505_PCIF0_CLK_ITPEN CK505_PCIF1_CLK CK505_PCI1_CLK CK505_PCI2_CLK CK505_PCI3_CLK CK505_PCI4_CLK CK505_PCI5_CLK_FCTSEL D 6 29 30 6 29 30 CK505_48M_FSA CK505_REF0_FSC TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA BGA_P1MM TABLE_SPACING_ASSIGNMENT_ITEM CK505_LVDS TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK * BGA BGA_P2MM CK505_SRC1 TABLE_SPACING_ASSIGNMENT_ITEM CLK_FSB * BGA BGA_P2MM CLK_PCIE * BGA BGA_P2MM CLK_MED * BGA BGA_P2MM FSB_DSTB FSB_DSTB BGA BGA_P3MM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM CK505_SRC2 TABLE_SPACING_ASSIGNMENT_ITEM CK505_SRC3 TABLE_SPACING_ASSIGNMENT_ITEM CK505_SRC4 TABLE_SPACING_ASSIGNMENT_HEAD CK505_SRC5 TABLE_SPACING_ASSIGNMENT_ITEM CLK_FSB PWR * BUS2PWR_GND CLK_FSB GND * BUS2PWR_GND CK505_SRC6 TABLE_SPACING_ASSIGNMENT_ITEM CK505_SRC7 TABLE_SPACING_ASSIGNMENT_ITEM C CLK_PCIE PWR * BUS2PWR_GND CLK_PCIE GND * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM CK505_SRC8 TABLE_SPACING_ASSIGNMENT_ITEM CLK_MED PWR * BUS2PWR_GND NB_CLK96M_DOT_P NB_CLK96M_DOT_N NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N CK505_SRC1_P CK505_SRC1_N SB_CLK100M_DMI_P SB_CLK100M_DMI_N CK505_SRC3_P CK505_SRC3_N CK505_SRC4_P CK505_SRC4_N NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N CK505_SRC7_P CK505_SRC7_N CK505_SRC8_P CK505_SRC8_N 6 9 16 29 30 71 6 9 16 29 30 71 6 9 16 29 30 71 6 9 16 29 30 71 6 24 29 30 71 6 24 29 30 71 6 16 29 30 71 6 16 29 30 71 6 29 30 36 71 6 29 30 36 71 C TABLE_SPACING_ASSIGNMENT_ITEM CLK_MED GND * BUS2PWR_GND FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_NB_P FSB_CLK_NB_N XDP_CLK_P XDP_CLK_N PCI_CLK33M_LPCPLUS PCI_CLK33M_SB PCI_CLK33M_FW PCI_CLK33M_TPM PCI_CLK33M_SMC 6 10 29 30 71 6 10 29 30 71 6 14 29 30 71 6 14 29 30 71 6 7 13 29 30 66 71 6 7 13 29 30 66 71 6 30 43 6 24 30 6 30 41 CK505 PCI4 is project-specific CK505 PCI5 is project-specific B (CPU_BSEL0) (CPU_BSEL2) CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED (CPU_BSEL0) (CPU_BSEL2) CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED (CK505_DOT96) (CK505_DOT96) (CK505_LVDS) (CK505_LVDS) (CK505_SRC1) (CK505_SRC1) (CK505_SRC2) (CK505_SRC2) (CK505_SRC3) (CK505_SRC3) (CK505_SRC4) (CK505_SRC4) (CK505_SRC5) (CK505_SRC5) (CK505_SRC6) (CK505_SRC6) CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE SATA_100D GND SATA_100D GND CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE SB_CLK48M_USBCTLR SB_CLK14P3M_TIMER CK505_FSA CK505_FSC 6 25 30 6 25 30 6 30 6 30 NB_CLK96M_DOT_P NB_CLK96M_DOT_N NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N PEG_CLK100M_P PEG_CLK100M_N SB_CLK100M_DMI_P SB_CLK100M_DMI_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N SB_CLK100M_SATA_P SB_CLK100M_SATA_N NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N 6 9 16 29 30 71 6 9 16 29 30 71 6 9 16 29 30 71 6 9 16 29 30 71 B 6 24 29 30 71 6 24 29 30 71 6 16 29 30 71 6 16 29 30 71 6 29 30 36 71 6 29 30 36 71 CK505 SRC7 is project-specific (CK505_SRC8) (CK505_SRC8) CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N SMC SMBus Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET A PHYSICAL SPACING SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SDA SMB_55S SMB SMBUS_SMC_BSA_SCL SMB_55S SMB SMBUS_SMC_BSA_SDA SMB_55S SMB SMBUS_SMC_MGMT_SCL SMB_55S SMB SMBUS_SMC_MGMT_SDA SMB_55S SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 6 7 36 40 41 44 6 7 36 40 41 44 Clock & SMC Constraints 6 7 41 44 46 SYNC_MASTER=T9 SYNC_DATE=01/30/2007 6 7 41 44 46 NOTICE OF PROPRIETARY PROPERTY 6 7 41 44 50 59 6 7 41 44 50 59 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. Rev 1.0 (#21112).1 . SCALE SHT NONE 8 7 6 5 4 3 2 REV. INC.0 OF 71 1 73 A .14. 051-7230 B. Sections 14.

0 OF 1 73 A .228 MM ? 6 7 8 11 12 22 26 27 54 TABLE_SPACING_RULE_ITEM 6 22 TABLE_SPACING_RULE_ITEM 6 19 22 6 19 22 6 26 27 6 27 6 26 27 6 23 24 26 27 6 7 8 19 22 51 61 6 61 6 61 6 19 22 6 61 6 61 6 61 6 7 8 16 18 21 31 32 34 35 51 55 68 C 6 19 21 6 21 6 7 8 10 11 12 13 14 18 19 21 23 26 27 30 42 54 6 15 19 21 6 7 8 16 18 19 21 26 27 51 57 6 19 21 6 22 6 19 21 6 21 6 19 22 6 19 22 6 60 6 7 60 7 6 61 6 6 6 29 6 6 6 6 52 6 7 60 6 21 6 22 6 22 B 6 22 6 22 6 19 22 6 19 22 6 19 22 6 19 22 6 19 22 6 61 6 7 8 36 42 44 48 51 58 60 6 7 36 6 7 8 24 25 26 27 28 36 43 44 49 51 56 57 58 60 6 41 42 6 41 6 57 6 7 8 23 26 27 28 39 40 41 42 43 44 57 59 6 39 6 7 8 22 27 40 43 47 51 52 53 63 6 7 37 63 6 63 M82 Power and Ground Nets 6 52 6 7 40 SYNC_MASTER=(MASTER) 6 26 27 6 63 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER. 051-7230 SCALE SHT NONE 72 6 59 7 6 5 4 3 2 B. 6 50 6 7 8 50 59 REV.0. INC.8 I1 I2 I3 I4 I5 I6 I7 I8 I10 I9 I12 D I11 I13 I14 I16 I15 I18 I17 I19 I21 I20 I23 I100 I101 I22 I24 I25 I26 I28 I27 I30 I29 I31 I33 I32 I35 I34 I36 C I38 I37 I39 I41 I40 I43 I42 I44 I46 I45 I48 I47 I49 I50 I52 I51 I54 I53 I55 I57 I56 I59 I58 I60 I62 I61 B I63 I65 I64 I67 I66 I68 I70 I69 I72 I71 I73 I74 I76 I75 I78 I77 I79 I81 I80 I83 I82 I84 I86 I85 I87 I89 A I88 I91 I90 I92 I94 I93 I96 I95 I97 I98 I99 I102 I103 I104 PPBUS_G3H PPBUS_R_G3H PPDCIN_G3H PPDCIN_G3H_R PPVBATT_G3H_R PPVBAT_G3H_CHGR_OUT PPVBAT_G3H_CHGR_REG PPVBAT_G3H_CHRGR_REG_R PPVBAT_G3H_CHRGR_REG_0 PPVCORE_S0_CPU PPVCORE_S0_NB_GFX PPVDCIN_G3H_PRE PPVDCIN_G3H_PRE_R PPVDCIN_G3H_PRE_0 PPVDCIN_G3H_PRE2 PPVIN_S5_IMVP6_VIN PPVOUT_S0_LCDBKLT PPVOUT_S0_LCDBKLT_SW PP0V9_S0 PP0V9_S3 PP1V5_S0 PP1V5_S0_NB_QDAC PP1V5_S0_NB_VCCD_CRT PP1V5_S0_NB_VCCD_QDAC PP1V5_S0_NB_VCCDMIPLL PP1V5_S0_NB_VCCDMIPLL_F PP1V5_S0_SB_VCCDMIPLL PP1V5_S0_SB_VCCDMIPLL_F PP1V5_S0_SB_VCCSATAPLL PP1V5_S0_SB_VCC1_5_B PP1V8_S0 PP1V8_S0_ANALOG_SDVO_F PP1V8_S0_ANALOG_TMDS_F PP1V8_S0_NB_VCCTXLVDS PP1V8_S0_PVCC1_TMDS_F PP1V8_S0_PVCC2_TMDS_F PP1V8_S0_TMDS_F PP1V8_S3 PP1V8_S3M_NB_VCCSMCK PP1V8_S3_NB_VCCSMCK_RC PP1V05_S0 PP1V05_S0_NB_VCCPEG PP1V25_S0 PP1V25_S0M_NB_VCCA_HPLL PP1V25_S0_NB_DPLL PP1V25_S0_NB_PEGPLL PP1V25_S0_NB_PEGPLL_RC PP1V25_S0_NB_VCCA_DPLLA PP1V25_S0_NB_VCCA_DPLLB PP3V3_LCDVDD_SW PP3V3_LCDVDD_SW_F PP3V3_S0 PP3V3_S0_ANALOG_SDVO_F PP3V3_S0_CK505_VDDA PP3V3_S0_CK505_VDDA_R PP3V3_S0_CK505_VDD_CPU_SRC PP3V3_S0_CK505_VDD_PCI PP3V3_S0_CK505_VDD_REF PP3V3_S0_CK505_VDD48 PP3V3_S0_IMVP6_3V3 PP3V3_S0_LCD_F PP3V3_S0_NBCORE_FOLLOW_R PP3V3_S0_NB_CRTDAC_F PP3V3_S0_NB_TVDAC PP3V3_S0_NB_TVDAC_F PP3V3_S0_NB_TVDAC_FOLLOW PP3V3_S0_NB_VCCA_CRTDAC PP3V3_S0_NB_VCCA_DAC_BG PP3V3_S0_NB_VCCA_TVDACA PP3V3_S0_NB_VCCA_TVDACB PP3V3_S0_NB_VCCA_TVDACC PP3V3_S0_SPVCC_TMDS_F PP3V3_S3 PP3V3_S3_AP_AUX PP3V3_S3_TOPCASE_F PP3V3_S5 PP3V3_S5_AVREF_SMC PP3V3_S5_SMC_AVCC PP3V42G3H_SW PP3V42_G3H PP3V42_G3H_SMC_F PP3V42_G3H_SMCUSBMUX_R PP4V5_AUDIO_ANALOG PP5V_S0 PP5V_S0_AUDIO PP5V_S0_AUDIO_AMP PP5V_S0_DVIPORT PP5V_S0_DVIPORT_D PP5V_S0_IMVP6_VDD PP5V_S0_KBDLED_F PP5V_S0_SB_V5REF PP5V_S0_TMDS_FUSE PP5V_S0_3G_F PP5V_S3 PP5V_S3_CAMERA_F PP5V_S3_IR_F PP5V_S3_USB2_EXTA PP5V_S3_USB2_EXTA_F PP5V_S5 PP5V_S5_SB_V5REF_SUS PP18V5_DCIN PP18V5_DCIN_ONEWIRE PP18V5_G3H PP18V5_S5_CHGR_SW_R 8 7 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 6 4 5 3 2 1 6 7 8 37 45 50 56 59 64 6 7 8 42 52 53 54 55 59 6 7 8 50 57 6 50 6 50 6 59 6 59 6 59 6 59 6 7 8 11 12 52 65 6 7 8 18 22 45 53 65 D 6 45 59 6 59 6 59 6 59 6 52 6 7 60 64 6 64 6 7 8 33 55 6 8 31 32 55 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT PWR LAYER * =STANDARD ? BUS2PWR_GND * 0. THE POSSESSOR AGREES TO THE FOLLOWING 6 7 8 40 58 60 6 7 60 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 6 39 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 6 7 37 39 6 7 8 27 39 51 54 55 56 58 SIZE 6 26 27 DRAWING NUMBER D 6 7 50 APPLE INC.

INC.ISL5 Y 0.310 MM 0.ISL9.091 MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_SPACING_RULE_ITEM 1:1_SPACING * 0.132 MM 0.235 MM 0.280 MM LAYER ALLOW ROUTE ON LAYER? TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM A M82 Rule Definitions SYNC_MASTER=(MASTER) TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.200 MM 87_OHM_DIFF ISL10.065 MM 0.15 MM ? 1. SCALE SHT NONE 8 7 6 5 4 3 2 REV.250 MM 90_OHM_DIFF ISL10.085 MM 0.228 MM ? 2.190 MM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM GND * =STANDARD ? PP1V8_MEM * =STANDARD ? TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD C TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT GND_P2MM LAYER * 0.ISL13 Y 0.200 MM 85_OHM_DIFF ISL10.ISL11.7 MM =DEFAULT =DEFAULT PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM DEFAULT * 0.205 MM 100_OHM_DIFF ISL2.1 MM ? STANDARD * =DEFAULT ? BGA_P1MM * 0.25 MM ? 3:1_SPACING * 0.8:1_SPACING * 0.ISL12.ISL4.280 MM 0.ISL5 Y 0.ISL13 Y 0.ISL8.082 MM 0.5:1_SPACING * 0.082 MM 0.ISL5 Y 0.215 MM =STANDARD =STANDARD =STANDARD 27P4_OHM_SE ISL10.085 MM 0.250 MM 0.190 MM 0.ISL11.0 OF 73 1 73 A .065 MM 0.170 MM 0.280 MM 100_OHM_DIFF ISL10.ISL11. 051-7230 B.BOTTOM Y 0.8 6 7 3 4 5 2 1 M82 Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP.ISL4.ISL4.1 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_SPACING_RULE_HEAD DIFFPAIR NECK GAP SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM DEFAULT * Y 0.190 MM 0.ISL13 Y 0.0.1 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER.ISL13 Y 0.ISL4.180 MM 0.ISL4.ISL11.ISL11.200 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 85_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 85_OHM_DIFF TOP.3 MM ? LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM D TABLE_SPACING_RULE_ITEM D TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 27P4_OHM_SE * Y =STANDARD =STANDARD 27P4_OHM_SE ISL2.200 MM 0.070 MM 50_OHM_SE ISL10.BOTTOM Y 0.ISL4.ISL4.070 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 55_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 55_OHM_SE TOP.070 MM 0.132 MM 0.310 MM 0.ISL11.4 MM ? LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 50_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE TOP.2 MM ? BGA_P3MM * 0.BOTTOM Y 0.215 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 45_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 45_OHM_SE TOP.18 MM ? TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM 2:1_SPACING * 0.170 MM 0.200 MM 70_OHM_DIFF ISL10.180 MM 87_OHM_DIFF ISL2.132 MM 0.200 MM 0.ISL5 Y 0.220 MM 0.091 MM 0.3 MM ? 4:1_SPACING * 0.090 MM 0.090 MM 0.ISL11.070 MM 0.200 MM 0.200 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 87_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 87_OHM_DIFF TOP.ISL13 Y 0.250 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM B B TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD 100_OHM_DIFF TOP.2 MM 1000 PWR_P2MM * 0.ISL5.5:1_SPACING * 0.ISL11.280 MM 0.180 MM 90_OHM_DIFF ISL2.070 MM 0.130 MM 70_OHM_DIFF ISL2.BGA MM 15.215 MM 0.ISL3.200 MM 0.200 MM 0.ISL5 Y 0.ISL13. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC.ISL11.132 MM 0.082 MM 0.091 MM 45_OHM_SE ISL10.2 MM 1000 LINE-TO-LINE SPACING WEIGHT =STANDARD ? C TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE ISL2.082 MM 0.290 MM 0.ISL4.ISL11.ISL6.070 MM 55_OHM_SE ISL10.065 MM 0.180 MM 0.ISL10.ISL4.BOTTOM NO_TYPE.220 MM 0.090 MM 0.200 MM 0.BOTTOM Y 0.130 MM 0.ISL5 Y 0.ISL5 Y 0.180 MM 0.290 MM 45_OHM_SE ISL2.070 MM TABLE_SPACING_RULE_ITEM 55OHM SE ON INTERNAL LAYERS NOT ACHIEVABLE IN M82 STACKUP USING 50OHM SE TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_SPACING_RULE_ITEM NB_STATIC * TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 70_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 70_OHM_DIFF TOP.ISL13 Y 0.250 MM 0.ISL13 Y 0.1 MM ? BGA_P2MM * 0.235 MM 50_OHM_SE ISL2.070 MM 0.215 MM 0.ISL5 Y 0.ISL5 Y 0.200 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 90_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 90_OHM_DIFF TOP.BOTTOM Y 0.BOTTOM Y 0.BOTTOM Y 0.ISL2.ISL4.ISL13 Y 0.100 MM 0.ISL7.BOTTOM Y 0.205 MM 0.2 MM ? 2.091 MM 0.065 MM 0.1 MM SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY TABLE_PHYSICAL_RULE_ITEM 0.090 MM 0.ISL13 Y 0.180 MM 85_OHM_DIFF ISL2.076 MM 30 MM 0 MM 0 MM STANDARD * Y =DEFAULT =DEFAULT 12.190 MM 0.5.1 MM ? 1.28:1_SPACING * 0.085 MM 0.230 MM 0.085 MM 0.230 MM 0.