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CABINET (CASE)
Size
TMR = Triple Modular Redundant cabinet size
(54"w x 20"d x 90"h).
Simplex = cabinet size (36"w x 20"d x 90"h).
Grounding
The cabinet is equipped with a ground bar and
lug which must be connected to the plant's
ground grid system or earth ground with a
minimum #4 AWG cable size. This cable is for
electrical grounding and noise interference
reduction. The cable resistance should be no
greater than 1/2 ohm.
E-stop
The E-Stop (emergency stop) push-button is
located below the back up panel on the right
front door (Figure 1). This push-button is used
to trip the turbine in an emergency situation
only and should not be used as a normal
turbine stop. (Note: Steam turbine applications
use this as the last step of a normal shutdown)
Radio transmitters
Operation of a 5 watt or less radio transmitter
at 27 MHz, 150 MHz and 480 MHz with panel
doors closed will not disrupt control operation.
If at all practical, try not to key radio
transmitters near the control panel.
Power requirements
100 - 144 VDC at a minimum of 7 amps. Add
0.5 amps for each solenoid used.
Cores
There are at usually 8 different cores used in
the gas turbine and steam turbine control
system for TMR panels (6 for a simplex
panel.) Additional cores are added as required
by the application.
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LOW LEVEL
SHIELD BUS
BAR
CCOM
<S>
Core
<R>
Core
<C>
Core
TB for LVDT/R
Servo's etc.
TB for LVDT/R
Servo's etc.
TB for mA
inputs/outputs
Not Used
Vibration,
PR, Vdc etc.
Not Used
Not Used
TB for
Themopcouples
TB for
Themopcouples
Not Used
LVDT feedback,
mA inputs
TB for RTD
<T>
Core
<P>
Core
HIGH LEVEL
SHIELD BUS
BAR
Backup
Operator
Interface
<BOI>
<PD>
Core
Emergency Stop PB
TB for LVDT/R
Servo's etc.
<D>
Core
or
<QD2>
Core
or
Rectfiers
LEFT
FRONT DOOR
LEFT
SIDE
WALL
Overspeed, flame
Synch & trip
AC & DC power
supply inputs
<QD1>
Core
<CD>
Core
Contact Input
Terminal Board
Contact Input
Terminal Board
Contact Input
Terminal Board
Contact Input
Terminal Board
Contact Output
Terminal Board
Contact Output
Terminal Board
Contact Output
Terminal Board
Contact Output
Terminal Board
BACK PANEL
RIGHT
SIDE
WALL
Ground Lug
NOTES:
1 - High level wiring on right side of case, low level on left side.
2 - Cable support rails provided on both side walls.
3 - Refer to case outline drawings for additional site specific details.
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LOW LEVEL
SHIELD BUS
BAR
CCOM
<S>
Core
1 - DCC
/LCC
2 - TCQA
3 - TCQB*
4 - TCQC
5 - TCPS
<R>
Core
1 - DCC
/LCC
2 - TCQA
3 - TCQB*
4 - TCQC
5 - TCPS
<C>
Core
1 - DCC
/LCC
2 - TCCA
3 - TCCB*
4 - TCCC
5 - TCPS
6 - QTBA
6 - QTBA
6 - CTBA
7 - TBQB
Not Used
Not Used
8 - TBQA
8 - TBQA
Not Used
9 - TBQC (*4)
9 - TBCA
<T>
Core
1 - DCC
/LCC
2 - TCQA
3 - TCQB*
4 - TCQC
5 - TCPS
<P>
Core
1 - TCEA
2 - TCEB
3 - TCEA
4 - TCTn
5 - TCEA
<PD>
Core
1 - TCPD
HIGH LEVEL
SHIELD BUS
BAR
Backup
Operator
Interface
<BOI>
Emergency Stop PB
6 - QTBA
<D>
Core
or
<QD2>
Core
or
Rectfiers
LEFT
FRONT DOOR
LEFT
SIDE
WALL
6 - PTBA
<QD1>
Core
1 - TCDA
2 - TCDA
3 - TCDA
4 - TCRA
5 - TCRA
<CD1>
Core
1 - TCDA
2 - OPEN
3 - OPEN
4 - TCRA
5 - TCRA
6 - DTBA
6 - DTBA
7 - DTBB
7 - DTBB
8 - DTBC
8 - DTBC
9 - DTBD
9 - DTBD
BACK PANEL
RIGHT
SIDE
WALL
Ground Lug
NOTES:
1 - High level wiring on right side of case, low level on left side.
2 - Cable support rails provided on both side walls.
("B" type panels have shield termination bars located adjacent to the terminal boards).
3 - Refer to case outline drawings for additional site specific details.
4 - Location 9 of <R> could be used for extended I/O, eg. a TBQF card installed on a large steam turbine application.
5 - Location 7 of <S> could be used for extended I/O, eg. proximeter inputs terminated on a TBQE card.
Figure 2 Descriptive Layout of a typical SPEEDTRONIC Mark V Cabinet
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Core Types
<R,S,T> -Redundant control Cores
<C> - Common or communication Core
<P> - Protective Core
<PD> - Power Distribution Core
<CD> - Digital I/O Core for <C>
<QD1> - Digital I/O #1 Core for <RST>
Optional cores:
<QD2> - Digital I/O #2 Core for <RST>.
<CD2> - Digital I/O #2 Core for <C>.
<D> - Redundant communications core.
<PLU> Power Load Unbalance (Large Steam Applications)
F11
F12
DSP
F1
F2
PROC
F16
F17
F6
F7
ALARM
ACK
NORMAL
ALARM
RESET
ALARMS
F13
F3
F18
F8
F14
F4
F19
F9
ALLP
SCROLL
UP
PREV
DSP
ESC
F15
F20
SET
B
1
F10
FORCE
RAISE
F5
E
4
SCROLL
DOWN
NEXT
DSP
HELP
<
>
CLEAR
DELETE
T
8
9
E
N
T
E
R
DZ
LOWER
DEM
SHIFT
C
2
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Loc. 2
Loc. 1
Loc. 3
Loc. 4
Loc. 5
Indicates Board
Orientation
(Top Left Hand
Corner of Card)
Loc. 6
Loc. 7
Loc. 8
Shield Termination
Strips (B Panels)
Loc. 9
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Strip Insulation
Back Approx. 1/4"
INSULATION SLEEVE
Slide sleeve over aluminum
shield
SIGNAL WIRES
INSULATION SLEEVE
Slide sleeve over
Drain Wire
DRAIN WIRE
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Note:
Color Trace
Indicates Pin
Number One
Color Trace
1
1
Connector
Ribbon Cable
1 2
View A
Connector
Pin Numbering
Arrangement
Figure 6 SpeedtronicTM Mark V Ribbon Cables
Rev. 1 2/3/2016
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Pin (Male/Female)
TOP VIEW
Polarized
(Keyed)
TYPE 1
Wires
Polarized
(Keyed)
PIN
CIRCUIT
BOARD
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Circuit boards
DCCA -<RST or C> - CPU or control
processor board contains the 80186
microprocessor which is the heart of the
system. The CPU board also contains the
80196 microprocessor, 32010 math coprocessor used for auto sync functions,
EEPROM and dual ported RAM. There is a
small push-button switch mounted on the
board for re-booting the processor after
down loading new software into the
EEPROM.
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Termination boards
CTBA - Termination for <C> core. The
termination signals are as follows:
1. Ma. input and Ma. output.
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5. LVDT excitation.
3. Bus volts.
4. Generator volts and current.
5. Synchronizing.
6. Protective inputs.
7. Alarm horn enable and disable hardware
jumper location.
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1. Proximitors.
2. LVDT input signals.
3. Milliamp outputs.
24
<R>
T
B
Q
A
8
<S>
<T>
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HEWLETT
PACKARD
Vectra
Office
Track Ball
Emergency Stop
SPEEDTRONIC
MARK V PANEL
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MARK V PANEL
JAI
93 R
HEWLETT
PACKARD
93 Termination
Resistor
<C>
Vectra
Off ice
"T" Connector
JAJ
HEWLETT
PACKARD
MARK V PANEL
Vectra
Off ice
JAI
<I> Processors
Maximum of 6
<C>
JAJ
HEWLETT
PACKARD
Vectra
Off ice
Additional
Mark V Panels
and/or <I>'s
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<C>
CONTROL PROCESSOR
LCC
LCC
RS232
ANALOG I/O
EEPROM
80196
D
P
M
D
P
M
DPM
<I>
TCCn
80196
A
R
C
TO DCS
(MODBUS LINK)
80196
A
R
C
32010
DPM
STAGE LINK
A
R
C
RG 62/A-U COAX
2.5 MEGA BAUD
93Termination
Resistor
486 DX
32 BIT
I/O
ADDRESS BUS
<CD>
DE NET
(DATA EXCHANGE NETWORK)
(2.5 MEGA BAUD)
DIGITAL I/O
(DUAL PORTED
MEMORY)
TCDn
I/O NET
760K BAUD
TCRn
TCRn
80196
<I>
<R>
CONTROL PROCESSOR
RS232
80186
80196
A
R
C
TCQn
A
R
C
EEPROM
80196
D
P
M
D
P
M
DPM
A
R
C
ANALOG I/O
LCC
80196
E
T
H
A
R
C
TO DCS
32010
DPM
<QDn>
<P>
BUNET
9600 BAUD
TCEn
I/O NET
760K BAUD
<S>
80196
A
R
C
80186
RS232
TCDn
80196
ANALOG I/O
TCQn
EEPROM
80196
D
P
M
D
P
M
DPM
(ETHERNET LINK)
RG 58 C/U Cable
10 Mega Baud
50Termination
Resistor
<X>
Loc. 1
LCC
DIGITAL I/O
80196
SYNC CHECK
ONLY
CONTROL PROCESSOR
<G>
80196
TCT(L,S,G)
A
R
C
32010
DPM
<QDn>
<P>
BUNET
9600 BAUD
TCDn
<Y>
Loc. 3
<T>
CONTROL PROCESSOR
RS232
80196
TCRn
ANALOG I/O
EEPROM
80186
D
P
M
D
P
M
DPM
TCRn
80196
TCQn
LCC
A
R
C
DIGITAL I/O
TCEn
80196
I/O NET
760K BAUD
80196
80196
A
R
C
32010
DPM
<P>
BUNET
9600 BAUD
TCEn
I/O NET
760K BAUD
80196
<Z>
Loc. 5
RS422
<BOI>
<QDn>
DIGITAL I/O
TCDn
80196
Rev 1.0
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TM
SPEEDTRONIC MARK V
CONTROL PANEL HARDWARE
The typical SPEEDTRONICTM Mark V
control panel consists of a communicator
core <C>, control core(s) (<R>, in a
Simplex configuration), <R>, <S>, & <T>,
in a TMR panel, a protective core <P>, a
power distribution core <PD>, and Digital
I/O cores <CD> and <QD1>. Additional
cores; <QD2>, <D>, and <PLU> are added
as needed. These additional cores allow
extended digital I/O and Power Load
Unbalance (Large Steam Applications.)
The basic function of each core (the
assembly containing printed circuit cards,
fuses, etc.) in the SPEEDTRONICTM Mark
V control panel is described as follows:
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<I>
Stage Link
Primary
Operator
Interface
<C>
DENET
<R>
<S>
<T>
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<C>
LCC_
<D>
LCC_
<C>
DCC_
<R>
TCQC
<S>
TCQC
<T>
TCQC
<R>
LCC_
<S>
LCC_
<T>
LCC_
<R>
DCC_
<S>
DCC_
<T>
DCC_
----- DENET
___ CORE WIRING HARNESS
<D>
DCC_
DENET (TMR Control Panel shown with optional <D> Redundant Communications Processor)
<C>
LCC_
TCDA
<C>
DCC_
TCCA
TCCB
NOT
USED
TCPS
*
Loc. 1
Loc. 2
Loc. 3
CTBA
TBCB
TBQA
Loc. 1
Loc. 4
<CD> Digital
I/O Core
Loc. 5
TBCA
Loc. 6
Loc. 7
Loc. 8
Indicates Optional
Card
Loc. 9
<C> IONET
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<R>
LCC_
TCEA
<R>
DCC_
TCQA
TCDA
TCDA
TCPS
<X>
Loc. 1
Loc. 1
Loc. 1
Loc. 5
<P> Protective
Core
<QD1> Digital
I/O Core
<QD2> Digital
I/O Core *
TCQB
TCQC
Loc. 1
Loc. 2
Loc. 3
Loc. 4
QTBA
TBQB
TBQA
TBQC
Indicates Optional
Cards
<Q> IONET
Loc. 6
Loc. 7
Loc. 8
Loc. 9
Figure 15 <R> Core (Critical I/O) Shown for a TMR configuration with optional extended I/O
TCEA
TCEA
TCEA
<X>
<Y>
<Z>
TCDA
TCDA
Loc. 1
Loc. 3
Loc. 5
Loc. 1
Loc. 1
<P> Protective
Core
<P> Protective
Core
<P> Protective
Core
<QD1> Digital
I/O Core
<QD2> Digital
I/O Core *
Indicates Optional
Cards
<Q> IONET
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<S>
LCC_
TCEA
<S>
DCC_
TCQA
TCQB
TCQC
TCPS
*
Loc. 1
QTBA
Loc. 2
Loc. 3
Loc. 4
Not
Used
*
Not
Used
*
Not
Used
*
TCDA
TCDA
Loc. 3
Loc. 2
Loc. 2
<P> Protective
Core
<QD1> Digital
I/O Core
<QD2> Digital
I/O Core *
<Y>
Loc. 5
* Indicates Optional
Cards
<Q> IONET
Loc. 6
Loc. 7
Loc. 8
Loc. 9
<T>
LCC_
TCEA
<T>
DCC_
Loc. 1
TCQA
Loc. 2
TCQB
TCQC
TCDA
TCDA
<Z>
TCPS
Loc. 5
Loc. 3
Loc. 3
Loc. 3
<P> Protective
Core
<QD1> Digital
I/O Core
<QD2> Digital
I/O Core *
Loc. 4
Loc. 5
QTBA
* Indicates Optional
Cards
<Q> IONET
Loc. 6
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TCEA
<X>
TCEB
TCEA
<X>
TCT_
TCEA
<X>
Loc. 1
Loc. 2
Loc. 3
Loc. 4
Loc. 5
PTBA
Loc. 6
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TCDA
TCDA
TCDA
TCRA
TCRA
Loc. 1
Loc. 2
Loc. 3
Loc. 4
Loc. 5
DTBA
DTBB
DTBC
DTBD
Loc. 6
Loc. 7
Loc. 8
Loc. 9
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TCDA
Not
Used
Not
Used
TCRA
TCRA
Loc. 1
Loc. 2
Loc. 3
Loc. 4
Loc. 5
DTBA
DTBB
DTBC
DTBD
Loc. 6
Loc. 7
Loc. 8
Loc. 9
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<BOI>
<BOI>
TCQC
TCQC
TCQC
TCQC
<R>
<S>
<T>
<R>
SIMPLEX
BUNET
TMR
BUNET
LCC
LCC
LCC
LCC
<R>
<R>
<R>
<R>
Figure 22
<BOI> Communications Layout for a TMR and SIMPLEX Configuration
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