ELECTRONICS ENGINEERING DEPARTMENT

COLLEGE OF ENGINEERING
XAVIER UNIVERSITY- ATENEO DE CAGAYAN

Title of Experiment: JFET Frequency Response

Experiment #: 2

Names of Members:
Leo Marcelo P. Villalba
Joeune B. Merencillo
Arnel Charles Ed Go
Aira Jean Damasing
Primo B. Revilla III
Group Number: 3
Subject and Section: ECE 32- EC

Date Performed:
November 24, 2015
Date of Report Submitted:
November 21, 2015

Name of Intsructor:
Engr. McAlvin Neri

Rating:
Introduction, Objective & Theory (20%)
Methods/Laboratory Performance (20%)
Data and Results (20%)
Discussions & Conclusions (20%)
Organization (20%)
Total (100%)

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Remarks:
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INTRODUCTION
Field-effect transistor amplifiers provide an excellent voltage gain with the
added feature of a high input impedance. They are also low-power-consumption
configurations with good frequency range and minimal size and weight. As an
amplifier, the JFET also uses coupling capacitors and bypass capacitors in order to
separate dc signal to ac signal. The coupling and bypass capacitors are placed at the
gate, drain and source. In the analysis of frequency response, we look at the reactance
as a behavior of this capacitors, see (Eqn. 1).

1
2

(Eqn. 1)

In figure 1, a common source self biased JFET configuration is used in order to

observe the frequency response of the JFET caused by CS, CD, and CG. In figure 2, a
common drain amplifier is used. The voltage gain is less than 1 and on the other hand,
it has a large current gain.

Figure 1. JFET self bias common source amplifier configuration.

Figure 2. JFET common drain or source follower configuration.

PROCEDURE
The following experiment was simulated in NI Multisim 14.0 program. The JFET
used was 2n5485 in absence of 2n5457. The saturation current of the JFET is 6.2 mA
while the pinch off voltage is equal to 2.5 V. The source voltage is set to 15 Volts
while the input voltage at 100 mVrms.
The JFET is then biased in 3 mA IDQ, 0.8 VGS equivalent, and VDSQ of 12 V.
After knowing the operating points, the drain and source resistance is then calculated
using Equations 2 and 3. RS = 267 while RD = 733 .
RS =
RD =

(Eqn. 2)

VDD IDQ Rs VDS

IDQ

(Eqn. 3)

In calculating the voltage gain, MatLab with the equation 4 was used. Where
the logarithm of the output and input ratio is used.
AV = 20 log |

VOUT
VIN

(MatLab code in getting gain and plot)

(Eqn. 4)

In the common drain configuration, the output is from the voltage across R1 in
figure 2. In DC biasing, in order to get R1 and RS, we set open all the capacitors. Then
solve for the resistor values where VGSQ is 0.8 V, IDQ = 3 mA, VDSQ = 12 V, and VDD
equal to 15 V.
DATA AND RESULTS
The following data was gathered through NI Multisim 14.0 simulations.
Individual data gathering was used so as the AC sweep simulation to compare results.
MatLab log-log plot tool is then used to plot the data gathered.

f (Hz)
50
75
100
200
500
800
1k
2k
5k
10k
20k
50k
100k
200k
500k
1M
10M
20M
50M
100M
200M
500M
1G

Table 1. Common source amplifier frequency response.

VIN (mVrms)
VOUT (mVrms)
Deg
AV (dB)
100
220
-165
6.8485
100
231
-169
7.2722
100
235
-172
7.4214
100
240
-175
7.6042
100
241
-178
7.6403
100
241
-178
7.6403
100
241
-179
7.6403
100
241
-179
7.6403
100
241
-179
7.6403
100
241
-179
7.6403
100
241
-179
7.6403
100
241
-180
7.6403
100
241
-180
7.6403
100
241
-180
7.6403
100
241
-180
7.6403
100
241
-180
7.6403
100
242
-182
7.6763
100
241
-183
7.6403
100
240
-190
7.6042
100
236
-199
7.4582
100
223
-217
6.9661
100
175
-257
4.8608
100
135
-293
2.6067

Common Source Clipping Level

Vertical Scale: 2V / div
Vi = 900 mV, start of clipping

Vo = 1.888 V

Figure 3. Green (Vout), Red (Vin), clipping level.

Figure 4. Common source JFET frequency response using MatLab with values
from gathered individually.

Figure 5. Frequency response of common source JFET using Multisim AC

Sweep simulation.

f (Hz)
50
75
100
200
500
800
1k
2k
5k
10k
20k
50k
100k
200k
500k
1M
10M
20M
50M
100M
200M
500M
1G

Table 2. Common Drain amplifier frequency response.

VIN (mVrms)
VOUT (mVrms)
Deg
AV (dB)
100
69
5.1
-3.22
100
70
3.8
-3.09
100
70
2.7
-3.09
100
71
1.4
-2.97
100
71
0.546
-2.97
100
71
0.345
-2.97
100
71
0.274
-2.97
100
71
0.137
-2.97
100
71
0.054
-2.97
100
71
0.027
-2.97
100
71
0.015
-2.97
100
71
0.008
-2.97
100
71
0.00775
-2.97
100
71
0.0114
-2.97
100
71
0.0257
-2.97
100
71
0.05
-2.97
100
71
0.5
-2.97
100
71
1
-2.97
100
71
2.5
-2.97
100
72
4.7
-2.85
100
76
7.8
-2.38
100
87
9.3
-1.20
100
95
6.5
-0.44

Common Drain Clipping Level

Vertical Scale: 2V / div
Vi = 2.5 V, start of clipping Vo = 1.65 V

Figure 6. Common drain clipping level.

Figure 7. Common drain JFET frequency response using MatLab with values
from gathered individually.

Figure 8. Frequency response of common drain JFET using Multisim AC

Sweep simulation.

ANALYSIS AND CONCLUSION

Leo Marcelo Villalba:
The unavailability of JFET 2n5457 transistor leads us to use 2n5485.
In the common source frequency response, we will notice the output voltage is
amplified however not that large compared to BJT. We can see in table 1 that the
output voltage trend is increasing, steady, then decreasing. Just like the one seen on
bode plots. In figures 4 and 5 shows the bode plot of the common source amplifier.
We can see that this JFET 2n5485 has wide bandwidth ranging from few Hertz until 1
Gigahertz. In this simulation, we chose to increase the frequency until 1 Gigahertz in
order to see its high frequency cut-off. Another very interesting trend that we can
observe from the bode plots is the phase. As we can see in figures 4 and 5, the phase
is already negative starting at 50 Hz. It is true to the fact that Av = - gmRD. We can see
that as frequency goes higher, the phase goes more negative, and when the gain is
steady at 7.64 equivalent to approximately -180 degrees phase shift.
In the common drain frequency response, we will notice that the output voltage
is lower than the input voltage and at very high frequency only then it is approximately
equal to the input voltage, see figure 7 and 8, and columns 2 and 3 table 2. Also, we
will notice that the phase difference, see column 4 at table 2, is very small, which is
ideal to be a buffer, where it copies the input signal without changing the phase. Also,
we can see that we can utilize the 2n5485 transistor in 500 to 20 MHz range where
phase difference is less than 1.
CONCLUSION
The common source amplifier circuit amplifies the signal depending on the
values of resistors used to bias and the input is out of phase with the input signal.
Meanwhile, common drain or source follower configuration has gain approximately

equal to one and phase difference absolutely equal to zero at certain ranges ideal to
be used for buffer applications.
ANSWERS TO QUESTIONS
Common Source and Common Drain:
8 & 6. Plot the obtained data on top of your simulations. Do they agree? If there is a
difference, explain what could be the reason for it.
There are many factors affecting the inaccuracy of the data gathered. From
tolerance of the resistors to the effects of temperature. So there is no absolute reason
to why the data does not fit exactly.
Common Drain:
8. Note the phase shift between output and input, is your amplifier inverting or noninverting?
Non-inverting since the phase difference is positive and almost equal to zero.
9. Comment on the following questions:
a.) Comment on both the DC and AC values. Explain any discrepancies.
Without proper DC biasing, the amplified signal could be chopped off like the
one seen on figures 3 and 6 where the input signal is boosted. So when designing
amplifiers, the ranges of AC input should be remembered in order for DC biasing to
be effective.
b.) Is your CD amplifier suitable for an audio amplifier?
Common drain is best suited as a buffer in pre-amplification stage.
c.) What is a suitable application for the source follower?
It is best for the source follower to be connected in cascade with common drain
and into another common source to amplify voltage signals. It could be used in sensors
or amplification mainly.