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Computer Engineering Dept

Engineering

Term 081

Dr. Ashraf S. Hasan Mahmoud

Rm 22-148-3

Ext. 1724

Email: ashraf@kfupm.edu.sa

1/25/2009 Dr. Ashraf S. Hasan Mahmoud 1

Definitions

• Memory: A collection of cells capable of storing binary

information (1s or 0s) – in addition to electronic circuit

for storing (writing) and retrieving (reading)

information

• Two Types of Memory:

1. Random Access Memory (RAM):

• Accepts new information for storage to be available later for use

• Write/Read operations

2. Read Only Memory (ROM): is a programmable logic device

(PLD)

• Programming: specifying information and embedding it within

hardware

• Read operation (no write)

1

Definitions (2)

• Programmable Logic Devices (PLDs):

• ROM

• Programmable Logic Array (PLA)

• Programmable Array Logic (PAL) device

• Complex Programmable Logic Device (CPLD)

• Field-Programmable Gate Array (FPGA)

• PLD is an integrated circuit with internal logic gates

and/or connections that can in some way be changed

by a programming process

• Example: connections can be made with fuses

• Intact fuse – connection Î symbol = “X”

• Blown fuse - no connection Î symbol = “+”

Used symbol

Multi-input OR gate

There is a connection

There is no connection

• Fuse map: graphic representation of the selected

connections

2

Read-Only Memory (ROM)

• Def: A device in which “permanent” binary information

is stored

• Block diagram of ROM:

k inputs n outputs

(address)

2k x n ROM

(data)

• Each word is of size n bits

• ROM DOES NOT have a write operation Î ROM DOES

NOT have data inputs

Word: group of bits stored in one location

1/25/2009 Dr. Ashraf S. Hasan Mahmoud 5

• Note: The decoder stage produces ALL possible

minterms

0

I0 1

2

I1 3

5-to-32 .

I2

decoder .

.

I3 28

29

I4 30

31

A7 A6 A5 A4 A3 A2 A1 A0

3

Internal Binary Storage of ROM

Inputs Outputs

I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 1 0 1 1 0 1 1 0 0 x x x x x

I0 1 x x x x

0 0 0 0 1 0 0 0 1 1 1 0 1 2 x x x x

0 0 0 1 0 1 1 0 0 0 1 0 1 I1

3 x x x x

0 0 0 1 1 1 0 1 1 0 0 1 0 I2 5-to-32 .

. . decoder .

I3 .

. . 28 x x

I4 29 x x x x

. .

30 x x x

1 1 1 0 0 0 0 0 0 1 0 0 1 31 x x x x

1 1 1 0 1 1 1 1 0 0 0 1 0

1 1 1 1 0 0 1 0 0 1 0 1 0

1 1 1 1 1 0 0 1 1 0 0 1 1

A7 A6 A5 A4 A3 A2 A1 A0

• Every ONE in truth table specifies a closed circuit

• Example: At address 00011 Æ The word 10110010 is

stored

1. Mask Technology Î ROM

2. Fuses Î Programmable ROM or PROM

• User can blow/connect fuses employing some equipment

3. Erasable floating-gate technology Î EPROM

4. Electrically erasable technology Î Electrically erasable

programmable ROM or EEPROM or E2PROM

4

Combinational Circuit

Implementation with ROM

• Problem: Design a combinational circuit using ROM.

The circuit accepts a 3-bit number and generates an

output binary number equal to the square of the

number.

• Solution: Derive truth table:

Inputs Outputs

A2 A1 A0 B5 B4 B3 B2 B1 B0 No

0 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1 1

0 1 0 0 0 0 1 0 0 4

0 1 1 0 0 1 0 0 1 9

1 0 0 0 1 0 0 0 0 16

1 0 1 0 1 1 0 0 1 25

1 1 0 1 0 0 1 0 0 36

1 1 1 1 1 0 0 0 1 49

Combinational Circuit

Implementation with ROM – cont’d

• Note that B1 is ALWAYS 0 Î no need to generate it using the

ROM

• Note that B0 is equal to A0 Î no need to generate it using the

ROM

• Therefore: The minimum size of ROM needed is 23X4 or 8X4

B0

Inputs Outputs

A2 A1 A0 B5 B4 B3 B2

0 0 0 0 0 0 0

0 B1

0 0 1 0 0 0 0 A0 8 X 4 ROM B2

0 1 0 0 0 0 1

0 1 1 0 0 1 0

1 0 0 0 1 0 0

B3

A1

1 0 1 0 1 1 0

B4

1 1 0 1 0 0 1

1 1 1 1 1 0 0 A2 B5

ROM truth table – specifies the required connections

5

Problem

• Problem: Specify the size of a ROM (number of words

and number of bits per word) that will accommodate

the truth table for the following combinational circuit

components:

(a) An 8-bit adder subtractor with Cin and Cout – assume

output is 16-bit wide

(b) A binary multiplier that multiplies two 8-bit numbers

(c) A code converter from a 4-digit BCD number to a

binary number

Problem - Solution

• Solution:

(a) An 8-bit adder subtractor with Cin and Cout

Inputs to the ROM (address lines):

8 (first number) + (8 second number) + 1 (Cin) + 1

(Add/Subtract) Î 18 lines

Hence number of words in ROM is 218 = 256K

Size of each word = number of possible functions

= 16 (addition/subtraction) + 1 (Cout)

= 17

1/25/2009 Dr. Ashraf S. Hasan Mahmoud 12

6

Problem - Solution

• Solution:

(b) A binary multiplier that multiplies two 8-bit numbers

Inputs to the ROM (address lines):

8 (first number) + (8 second number) Î 16 lines

Hence number of words in ROM is 216 = 64K

Size of each word = number of possible functions

= 16 (result is 16-bit wide)

Problem - Solution

• Solution:

(c) A code converter from a 4-digit BCD number to a

binary number

Inputs to the ROM (address lines):

4 (number of BCD digits) X (4 bits/digit) Î 16 lines

Hence number of words in ROM is 216 = 64K

Size of each word = number of possible functions to

represent all 4-digits BCD number

= number of bits required to represent 9999

= 14 (remember 213 ≤ 9999 ≤ 214)

Hence ROM size = 64K X 14

1/25/2009 Dr. Ashraf S. Hasan Mahmoud 14

7

Problem

• Problem: Tabulate the truth for an 8 X 4 ROM that

implements the following four Boolean functions:

A(X,Y,Z) = Σm(3,6,7); B(X,Y,Z) = Σm(0,1,4,5,6)

C(X,Y,Z) = Σm(2,3,4); D(X,Y,Z) = Σm(2,3,4,7)

• Solution:

Inputs Outputs

X Y Z A B C D

0 0 0 0 1 0 0

0 0 1 0 1 0 0

0 1 0 0 0 1 1

0 1 1 1 0 1 1

1 0 0 0 1 1 1

1 0 1 0 1 0 0

1 1 0 1 1 0 0

1 1 1 1 0 0 1

Fixed

Programmable Programmable

Inputs AND array Outputs

connections OR array

(decoder)

Programmable read-only memory (PROM)

Inputs Outputs

connections AND array OR array

Inputs Outputs

connections AND array connections OR array

8

Programmable Logic Array (PLA)

• Unlike PROM, PLA does NOT provide full decoding of

the variables; i.e. it does not generate all the minterms

• The decoder is replaced with an array of AND gates

that can be programmed to generate product terms of

the input variables

• The terms are then selectively (programmable

connections) connected to OR gates to provide the sum

products for the required Boolean functions

Example 1:

• Problem: Implement the following functions using a

PLA

F1 = AB’ + AC + A’BC’; F2 = (AC + BC)’

9

F1 = AB’ + AC + A’BC’; F2 = (AC + BC)’

Specifying the function form:

PLA programming table: T: function does not require inverting

C: function requires inverting

Inputs Outputs

Product A B C (T) (C)

Term F1 F2

AB’ 1 1 0 - 1 -

AC 2 1 - 1 1 1

BC 3 - 1 1 - 1

A’BC’ 4 0 1 0 1 -

1 2 3

The fuse map of a PLA can be specified in this tabular form

Section 1: product terms

Section 2: required path between inputs and AND gates

Section 3: required path between AND and OR gates

1/25/2009 Dr. Ashraf S. Hasan Mahmoud 19

Product Terms, and 2 Outputs

A

PLA programming table: Inputs Outputs

B Product A B C (T) (C)

Term F1 F2

C

AB’ 1 1 0 - 1 -

XX X AB’ AC 2 1 - 1 1 1

BC 3 - 1 1 - 1

X X X X AC A’BC’ 4 0 1 0 1 -

The fuse map of a PLA can be specified in this tabular form

X X X BC Section 1: product terms

Section 2: required path between inputs and AND gates

Section 3: required path between AND and OR gates

X X X X A’BC’

X 0

C C’ B B’ A A’ X 1

F1 = AB’+AC+A’BC’

F2 = (AC+BC)’

1/25/2009 Dr. Ashraf S. Hasan Mahmoud 20

10

PLA Internal Logic

• Notes:

• The size of the PLA is specified by:

no of inputs X no of products X no of outputs

• In general: for an n inputs, k products, and m outputs PLA:

• n buffer inverter gates

• k AND gates

• m OR gates

• m XOR gates

• 2n X k programmable connections (inputs ÅÆ AND gates)

• k X m programmable connections (AND gates ÅÆ OR gates)

• m programmable connections (for the XOR gates)

Implementing Combinational

Circuits Using PLA

• Reduce number of distinct products (i.e. save by

reducing number of AND gates):

• Simplify Boolean function (and its complement) to obtain the

least number of products

• Reducing number of literals in the product is not a saving –

since all inputs are already available; However, less is better

11

Example 2: Implementing a

Combinational Circuit Using a PLA

• Problem: Implement the following two Boolean

functions with a PLA:

F1(A,B,C) = Σm(0,1,2,4); F2(A,B,C) = Σm(0,5,6,7)

• Solution:

BC 00 01 11 10

The combination that gives a minimum no of

A product terms is: F1 = (AB + AC + BC)’

0 1 1 0 1 F2 = (AB + AC + A’B’C’)

1 1 0 0 0

F1 = A’B’ + A’C’ + B’C’

F1’= AB + AC + BC

Inputs Outputs

BC 00 01 11 10

Product A B C (C) (T)

A Term F1 F2

0 1 0 0 0 AB 1 1 1 - 1 1

1 0 1 1 1

AC 2 1 - 1 1 1

F2 = AB + AC + A’B’C’

F2’= A’C + A’B + AB’C’ BC 3 - 1 1 1 -

A’B’C’ 4 0 0 0 - 1

1/25/2009 Dr. Ashraf S. Hasan Mahmoud 23

Problem:

• Problem: Derive the PLA programming table for the

combinational circuit that squares a 3-bit number.

Minimize the number of product terms.

• Solution:

Inputs Outputs

Inputs Outputs

A2 A1 A0 B5 B4 B3 B2 B1 B0 No

A2 A1 A0 B5 B4 B3 B2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0

0 1 0 0 0 0 1 0 0 4 0 1 0 0 0 0 1

B0 = Z 0 1 1 0 0 1 0

0 1 1 0 0 1 0 0 1 9 B1 = 0

1 0 0 0 1 0 0

1 0 0 0 1 0 0 0 0 16 1 0 1 0 1 1 0

1 0 1 0 1 1 0 0 1 25 1 1 0 1 0 0 1

1 1 0 1 0 0 1 0 0 36 1 1 1 1 1 0 0

1 1 1 1 1 0 0 0 1 49

12

Problem: Solution

• Solution: A1A0 00 01 11 10

A2

Inputs Outputs 0 0 0 0 0

A2 A1 A0 B5 B4 B3 B2 1 0 0 1 1

0 0 0 0 0 0 0 B5 = A2A1

0 0 1 0 0 0 0 B5’= A2’ + A1’

0 1 0 0 0 0 1

0 1 1 0 0 1 0 A1A0 00 01 11 10

1 0 0 0 1 0 0 A2

1 0 1 0 1 1 0 0 0 0 0 0

1 1 0 1 0 0 1 1 1 1 1 0

1 1 1 1 1 0 0

B4 = A2A1’+A2A0

B4’= A2’ + A1A0’

A1A0 00 01 11 10

A1A0 00 01 11 10

A2

A2

0 0 0 0 1

0 0 0 1 0

1 0 0 0 1

1 0 1 0 0

B2 = A1A0’

B3 = A2A1’A0+A2’A1A0

B2’= A1’ + A0’

B3’= A0’+ A2’A1’ + A2A1

1/25/2009 Dr. Ashraf S. Hasan Mahmoud 25

Problem: Solution

• Solution: Minimum number of products = 5

B0 = A0

B2 = A1A0’

B2’= A1’ + A0’

B1 = 0

B3 = A2A1’A0+A2’A1A0

B3’= A0’+ A2’A1’ + A2A1

B4’= A2’ + A1A0’ Inputs Outputs

B5 = A2A1 Product A2 A1 A0 (T) (C) (T) (T)

B5’= A2’ + A1’ Term B5 B4 B3 B2

A2’A1A0 1 0 1 1 - - 1 -

A2A1’A0 2 1 0 1 - - 1 -

A2A1 3 1 1 - 1 - - -

A1A0’ 4 - 1 0 - 1 - 1

A2’ 5 0 - - - 1 - -

13

Random Access Memory (RAM)

• Def: A device in which binary information is stored and

can be transferred to and from any location - with the

access taking the same time regardless of the location

• To compare:

• Serial Memory: the access time depends on the location of the

info – e.g. magnetic disk, tape, etc

• Binary info is stored in words – group of bits in one

location

• A group of size eight is called BYTE

k address lines

Memory Unit

2k words

Read n bits per word

Write

14

Read/Write Operation of RAM

• Write Operation:

1. Apply the binary address of the desired word to the address

lines

2. Apply the data bits that must be stored in memory to the data

input lines

3. Activate the Write input

• Read Operation:

1. Apply the binary address of the desired word to the address

lines

2. Activate the Read input

Chip

• Chip select (CS): to enable the particular RAM chip or

chips containing the word to be accessed Î Memory

Enable

Inputs

Chip Select Read/Write’ Operation

(CS) (R/W’)

0 x None

1/25/2009 Dr. Ashraf S. Hasan Mahmoud 30

15

Properties of RAM

• Statistic RAM (SRAM):

• Internal latches that store the binary information. The stored

information remains valid as long as power is applied

• Dynamic RAM (DRAM):

• Stores the binary information in the form of an electric charge

on capacitors

• Must be periodically recharged – refreshing ; ALL words are

read and re-writting to restore the decaying charge

• Less power consumption compared to SRAM

• SRAM is easier to use

• Volatile Memory: info is lost when power is off (e.g.

RAM)

• Nonvolatile Memory: info is retained even if power is

off (e.g. magnetic disk, ROM, etc)

1/25/2009 Dr. Ashraf S. Hasan Mahmoud 31

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