.

VHDL

ISBN 978-974-13-3479-6

VHDL

VHDL
6

1 VHDL
2
3
4
5
6

2552
Email: wutichai@rmuti.ac.th


1 VHDL ................................................................................................................................. 1
1.1 VHDL ...................................................................................................... 1
1.1.1 VHDL LIBRARY ........................................................... 1
1.1.2 VHDL ENTITY ............................................................... 2
1.1.3 VHDL ARCHITECTURE ............................................... 3
1.2 VHDL ............................................................................................... 4
1.3 ............................................................................................................................................. 6
2 ......................................................................................................................................... 7
2.1 .................................................................................................... 7
2.2 ........................................................................................................ 11
2.2.1 INTEGER ................................................................... 11
2.2.2 ENUMERATED 12
2.3 ................................................................................................................................................. 12
2.4 ............................................................................................................................................. 12
2.5 ........................................................................................................................................... 14
2.6 .......................................................................... 14
2.7 ................................................................................................................................... 16
2.8 VHDL ................................................................................................ 17
2.9 ............................................................................................................................................. 19
3 .................................................................................. 20
3.1 ............................................................................................................................. 20
3.1.1 .......................................................................................................... 20
3.1.2 ................................................................................................................. 21
3.1.3 ....................................................................................................... 22
3.1.4 ....................................................................................................... 23
3.1.5 .................................................................................................... 23
3.2 ............................................................................................................... 24
3.3 .................................................................................................... 25
3.4 GENERIC ......................................................................................................................26
3.5 VHDL ................................................................................................ 26
3.6 ............................................................................................................................................. 29

 ()
4 ................................................................................................................................. 30
4.1 WHEN .................................................................................................................................... 30
4.1.1 WHEN/ELSE ................................................................................................................... 30
4.1.2 WITH/SELECT/WHEN .................................................................................................. 33
4.2 GENERATE ............................................................................................................................. 39
4.2.1 FOR/GENERATE ............................................................................................................ 39
4.2.2 IF/GENERATE ................................................................................................................ 40
4.3 ............................................................................................................................................. 41
5 ................................................................................................................................. 42
5.1 PROCESS ................................................................................................................................. 42
5.2 VARIABLE SIGNAL........................................................................................... 43
5.3 IF PROCESS ................................................................................................... 44
5.4 WAIT PROCESS ............................................................................................ 47
5.4.1 WAIT ON ......................................................................................................................... 47
5.4.2 WAIT UNTIL .................................................................................................................. 47
5.4.3 WAIT FOR....................................................................................................................... 47
5.5 CASE PROCESS ............................................................................................ 49
5.6 ............................................................................................................................................. 55
6 ...................................................................................................................................... 56
6.1 VHDL ....................................................................................... 57
6.2 VHDL...................................................................................... 64
6.3 ............................................................................................................................................. 68
. VHDL ............................................. 70
. VHDL ................................................................................................................... 73
. Standard Package STD_LOGIC_1164 ....................................................................................... 74
. Quartus-II VHDL................................. 77
.............................................................................................................................................................. 85

 VHDL

: 1

VHDL

VHDL


VHDL
VHDL 3
o LIBRARY
o ENTITY
o ARCHITECTURE
1.1 VHDL

1.1

LIBRARY Declaration
ENTITY
ARCHITECTURE

1.1 VHDL
VHDL LIBRARY
LIBRARY package package
(subprogram) package ENTITY
ARCHITECTURE package 1.2
1.1.1

LIBRARY
PACKAGE
FUNCTIONS
PROCEDURES
COMPONENTS
CONSTANTS
TYPES

1.2 LIBRARY

VHDL

 VHDL

: 2

LIBRARY
o
LIBRARY
o
package LIBRARY
USE 1.3
1
2

LIBRARY library_name;
USE library_name.package_name.package_parts;

1.3 LIBRARY
USE package
TYPES CONSTANT SIGNAL FUNCTION PROCEDURE
USE (;) 1.3

VHDL

package

package

LIBRARY std
LIBRARY ieee

standard
std_logic_1164

package LIBRARY
1.4
1
2

LIBRARY std;
USE std.standard.all;
()

1.4 () package
() package

1
2

LIBRARY ieee;
USE ieee.std_logic_1164.all;

()
standard LIBRARY std
std_logic_1164 LIBRARY

ieee

package std
package
VHDL ENTITY

ENTITY 1.5
1.1.2

1
2
3
4
5
6
7

ENTITY entity_name IS
PORT (
port_name : signal_mode signal_type ;
port_name : signal_mode signal_type ;
...
);
END entity_name;

1.5

ENTITY

VHDL

 VHDL

signal_mode

INOUT

BUFFER

1.6

: 3
4

IN OUT

signal_type BIT BOOLEAN
STD_LOGIC INTEGER 2
signal_type

entity_name port_name VHDL

.

OUT
INOUT
BUFFER
IN

1.6 ENTITY
1.7() VHDL ENTITY
2 a b
y ENTITY 1.7()
1
2
3
4

()
1.7

ENTITY nand_gate IS
PORT( a,b : IN BIT ;
x
: OUT BIT );
END nand_gate;

()
() 2
()

VHDL ARCHITECTURE
ARCHITECTURE

(signal_mode) ENTITY ARCHITECTURE
1.8
1.1.3

1
2
3
4
5

ARCHITECTURE architecture_name OF entity_name IS

[declarations option]
BEGIN
[ code ]
END architecture_name;

1.8 ARCHITURE

VHDL

 VHDL

: 4

1.8 ARCHITECTURE BEGIN declarations option

ARCHITURE (
ENTITY) SIGNAL CONSTANT COMPONENT
BEGIN END code

1.7()

ARCHITECTURE
1
2
3
4

1.9

ARCHITECTURE behav OF nand_gate IS

BEGIN
y <= a nand b;
END behav;

1.9
1.9 3 a b
( <=) y
( 1.7() a b
y BIT )
1.2

1.1

VHDL

y = abc + ac

VHDL

1
2
3
4
5
6
7
8
9
10
11
12

3 a b c
y ENTITY
4 7 ARCHITECTURE
9 12 1 2 package
std_logic_1164 LIBRARY ieee
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------ENTITY ex1 IS
PORT ( a,b,c : IN BIT ;
y
: OUT BIT );
END ex1;
-------------------------------ARCHITECTURE behav OF ex1 IS
BEGIN
y <= (a and not(b) and c) or (a and not(c));
END behav;

VHDL

 VHDL

entity_name .vhd
ex1.vhd
Quartus-II ModelSim
Quartus-II 1.10
a (MSB) c (LSB)

1.10 1.1
1.2 y = ab + ab z = (ab+bc)
VHDL

2 3 a b c
y z VHDL
1
2
3
4
5
6
7
8
9
10
11
12
13

LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------ENTITY ex2a IS
PORT ( a,b,c : IN BIT ;
y,z
: OUT BIT );
END ex2a;
--------------------------------ARCHITECTURE behav OF ex2a IS
BEGIN
y <= (a and not(b)) or (not(a) and b);
z <= not ((a and b) or (b and c));
END behav;

y
1
2
3
4
5
6
7
8
9
10
11
12
13

LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------ENTITY ex2b IS
PORT ( a,b,c : IN BIT ;
y,z
: OUT BIT );
END ex2b;
--------------------------------ARCHITECTURE behav OF ex2b IS
BEGIN
y <= a xor b;
z <= not ((a and b) or (b and c));
END behav;

VHDL

: 5

 VHDL

: 6

1.11

1.11 1.2

1. VHDL
1.1)
Z = A + BC
Y = A1A2(A1 + A3)
1.2)
OUT = AB + BC + AC + ABC
1.3)
1.4).
S = (W + W )(W + W )
2. VHDL

1.3

2.1).

A
B

C
2.2).

A
0
A
1
A2
A
3

ON

3.

0 1
- 1 () 0
- 1
VHDL
4. Z = f(A, B,C) = m(0,2,6,7) VHDL
5. X = f(A, B,C, D) = m(1,5,8,10) VHDL
6. Y = f(A, B,C) = M(0,1,3,4) VHDL
-

VHDL

: 7

VHDL

(Pre-Defined Data Type)

.
package package LIBRARY
2.1
2.1

2.1 package
LIBRARY Package

ieee
std_logic_1164
package VHDL

o STD_LOGIC
o STD_LOGIC_VECTOR
std_logic_arith

package
o SIGNED
o UNSIGNED
o

conv_integer(p)
conv_unsinged(p,b)
conv_signed(p,b)
conv_std_logic_vector(p,b)

SIGNED
UNSIGNED

std_logic_unsigned

package
o STD_LOGIC_VECTOR

std_logic_signed

UNSIGNED
package
o STD_LOGIC_VECTOR

VHDL

SIGNED

: 8

2.1 package ()
LIBRARY Package

ieee
numeric_std
package
package
std_logic_arith std_logic_unsigned
std_logic_signed

work

package

1. BOOLEAN

FALSE

TRUE

1
2
3
4
5
6
7
8
9
10
11
o

resetn 0
6 8
1
2
3
4
5
6
7
8
9
10
11
12

ARCHITECTURE behav OF ex_boolean IS

BEGIN
PROCESS(...)
BEGIN
IF resetn = 0 THEN
...
ELSE
...
END IF;
END PROCESS;
END behav;

ARCHITECTURE behav OF ex_boolean2 IS

...
BEGIN
PROCESS(...)
BEGIN
IF a >= b THEN
...
ELSE
...
END IF;
END PROCESS;
END behav;

a b a b
7 9
a b

VHDL


2. BIT

: 9

1
2
3
4
5
6
7
8
9
10
11
12
o

ARCHITECTURE behav OF ex_bit IS

SIGNAL a,b : BIT;
BEGIN
PROCESS(...)
BEGIN
IF a >= b THEN
...
ELSE
...
END IF;
END PROCESS;
END behav;

3. BIT_VECTOR

b BIT 1

BIT

1
2
3
4
5
6
7
8
o

ARCHITECTURE behav OF ex_bit_vector IS

SIGNAL a : BIT_VECTOR(3 DOWNTO 0);
SIGNAL b : BIT_VECTOR(0 TO 7);
BEGIN
a <= 0110;
b <= 01110000;
...
END behav;

a BIT_VECTOR 4
b
BIT_VECTOR 8 5 a
01102 6 b 000011102

1 (0)
1 (0)

32
-2,147,483,647 +2,147,483,647

4. INTEGER

1
2
3
4
5
6
7

ARCHITECTURE behav OF ex_integer IS

SIGNAL a,b : INTEGER;
BEGIN
a <= 200;
b <= -100;
...
END behav;

VHDL

: 10

a 200 b -100
a b -2,147,483,647
+2,147,483,647

a_vect <= 1100_0011_0011_1100;

a_vect <= 1100001100111100;

a_vect <= XC33C;

a_vect <= 49980;

a_vect <= X141474;

5. NATURAL
0

--

--
--
--
--

2,147,483,647
c <= 1234;

c
NATURAL

6. REAL

1234
INTEGER

-1.0E38 +1.0E38
y <= 1.25E-5;

y
1.25E-5

7. STD_LOGIC

(X

STD_LOGIC_VECTOR 8

0 1 Z W L H -)

1
2
3
4
5
6
o

ARCHITECTURE behav OF ex_std_logic IS

SIGNAL x : STD_LOGIC;
SIGNAL y : STD_LOGIC_VECTOR(3 DOWNTO 0):= 0101;
BEGIN
...
END behav;

x STD_LOGIC
y 4 0101
STD_LOGIC_VECTOR

VHDL


8. STD_ULOGIC

(U

: 11

STD_ULOGIC_VECTOR 9

X 0 1 Z W L H -)

1
2
3
4
5
6
o

ARCHITECTURE behav OF ex_std_logic IS

SIGNAL x : STD_ULOGIC;
SIGNAL y : STD_ULOGIC_VECTOR(3 DOWNTO 0):= 0101;
BEGIN
...
END behav;

x STD_ULOGIC
y 4 STD_ULOGIC
0101

9. TIME

1
2
3
4
5
6
o

ARCHITECTURE behav OF ex_time IS

...
BEGIN
c <= a AFTER 10 ns WHEN sel_0 = 0 ELSE
b AFTER 10 ns;
END behav;

c a 10 sel_0
0 b 10
sel_0 1

10.CHARACTER

(User-Defined Data Type)

2 integer enumerated
TYPE
2.2

integer

+2147483647
2.2.1

1
2
3
4
5
6

ARCHITECTURE behav OF ex_integer IS

TYPE my_integer IS RANGE 0 to 255;
SIGNAL q : my_integer;
BEGIN
...
END behav;

VHDL

-2147483647

my_integer 0 255
q ( subtype) my_integer

enumerated

2.2.2

1
2
3
4
5
6
o

ARCHITECTURE behav OF ex_enum IS

TYPE state IS (idle,forward,backward,start,stop);
SIGNAL id : state;
BEGIN
...
END behav;

state

idle forward backward start stop

(Subtypes)

Subtype
2.3

1
2
3
4
5
6
7
o

ARCHITECTURE behav OF ex_sub IS

TYPE color IS (red,green,blue,white);
SUBTYPE my_color IS color RANGE red TO blue;
SIGNAL shirt_id : my_color;
BEGIN
...
END behav;

my_color color
red green blue white my_color
red green blue

(Array)

()
() 2.1 ()
scalar () ()
()
scalar
2.4

VHDL

: 12

()

()

()

: 13

()

2.1
2.1 (scalar)

BIT
STD_LOGIC
STD_ULOGIC
BOOLEAN

(vector)

BIT_VECTOR
STD_LOGIC_VECTOR
STD_ULOGIC
SIGNED
UNSIGNED
INTEGER

TYPE

SIGNAL VARIABLE ( 5.2)

1
2
3
4
5
6

ARCHITECTURE behav OF ex_array IS

TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;
TYPE matrix IS ARRAY (0 TO 3) OF row;
SIGNAL x: matrix;
BEGIN
...

row
matrix
x
SIGNAL

1
2
3
4

ARCHITECTURE behav OF ex_array2 IS

TYPE mat IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR
(7 DOWNTO 0);
BEGIN
...

VHDL

mat
2.1

:=
1
2
3
4
5
o

ARCHITECTURE behav OF ex_array3 IS

TYPE row1 IS ARRAY(3 DOWNTO 0)OF STD_LOGIC := 0001;
TYPE row2 IS ARRAY(3 DOWNTO 0)OF STD_LOGIC :=
(0,0,0,1);
BEGIN
...

row1 row2
0001

(Record)

2.5

1
2
3
4
5
6
7
o

ARCHITECTURE behav OF ex_rec IS

TYPE birthday IS RECORD
day: INTEGER RANGE 1 TO 31;
month: month_name;
END RECORD;
BEGIN
...

birthday day
INTEGER month month_name
()

(signed) (unsigned)


1
0

2.6

"0101" 5(10)
"1101" -3(10) (
) 13(10)

VHDL

: 14



package std_logic_arith
LIBRARY ieee

1
2
3
4
5
6
7
8
9
10
11

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
...
ARCHITECTURE behav OF ex_sig1 IS
SIGNAL a: SIGNED (7 DOWNTO 0);
SIGNAL b: SIGNED (7 DOWNTO 0);
SIGNAL x: SIGNED (7 DOWNTO 0);
...
BEGIN
v <= a + b;
--

12
13

w <= a AND b;
END behav;

--

a b

1
2
3
4
5
6
7
8
9
10

LIBRARY ieee;
USE ieee.std_logic_1164.all;
...
ARCHITECTURE behav OF ex_sig2 IS
SIGNAL a: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL x: STD_LOGIC_VECTOR (7 DOWNTO 0);
...
BEGIN
v <= a + b;
--

11
12

w <= a AND b;
END behav;

--

a b

package
1
2
3
4
5
6
7
8
9
10
11

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
...
ARCHITECTURE behav OF ex_sig3 IS
SIGNAL a: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL x: STD_LOGIC_VECTOR (7 DOWNTO 0);
...
BEGIN
v <= a + b;
--

12
13

w <= a AND b;
END behav;

--

VHDL

: 15

a b
package

(data conversion)
VHDL


2.7

conv_integer(p)
conv_unsigned(p,b)
conv_signed(p,b)
conv_std_logic_vector(p,b)

2.2

conv_integer(p)

conv_unsigned(p,b)

conv_signed(p,b)

conv_std_logic_vector(p,b)

p
SIGNED UNSIGNED STD_ULOGIC
INTEGER
p
INTEGER SIGNED SIGNED
STD_ULOGIC UNSIGNED
b
p
INTEGER UNSIGNED STD_ULOGIC
SIGNED b
p
INTEGER UNSIGNED SIGNED
STD_LOGIC_VECTOR b

1
2
3
4
5
6
7
8
9
10
11
12
13

LIBRARY ieee;
USE ieee.std_logic_1164.all;
...
ARCHITECTURE behav OF ex_conv IS
TYPE long IS INTEGER RANGE -100 TO 100;
TYPE short IS INTEGER RANGE -10 TO 10;
SIGNAL x : short;
SIGNAL y : long;
BEGIN
...
y <= 2*x + 5;
--
...
END behav;

VHDL

: 16

x y 2*x
x y
1
2
3
4
5
6
7
8
9
10
11
12
13
12
13

2.8

: 17
+

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
...
ARCHITECTURE behav OF ex_conv2 IS
SIGNAL a: UNSIGNED (7 DOWNTO 0);
SIGNAL b: UNSIGNED (7 DOWNTO 0);
SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
...
y <= CONV_STD_LOGIC_VECTOR ((a+b), 8);
...
END behav;
...
END behav;

a b UNSIGNED 8
y
CONV_STD_LOGIC_VECTOR

VHDL

2.1 4 SIGNED

4 2 a b 4
x 4
SIGNED
1
2
3
4
5
6
7
8
9
10
11
12
13

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
-----------------------------------------ENTITY adder1 IS
PORT ( a, b : IN SIGNED (3 DOWNTO 0);
x : OUT SIGNED (3 DOWNTO 0));
END adder1;
-----------------------------------------ARCHITECTURE behav OF adder1 IS
BEGIN
x <= a + b;
END behav;

2.2

VHDL

2.2 2.1
2.2 4 SIGNED
INTEGER CONV_INTEGER

4 2 a b 4
SIGNED sum 4
INTEGER
1
2
3
4
5
6
7
8
9
10
11
12
13

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
-----------------------------------------ENTITY adder2 IS
PORT ( a, b : IN SIGNED (3 DOWNTO 0);
sum : OUT INTEGER RANGE -16 TO 15);
END adder2;
-----------------------------------------ARCHITECTURE behav OF adder2 IS
BEGIN
sum <= CONV_INTEGER(a + b);
END behav;

2.2

2.2 2.2

VHDL

: 18

: 19

2.9

TYPE array1 IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;

TYPE array2 IS ARRAY (3 DOWNTO 0, 7 DOWNTO 0) OF STD_LOGIC;
TYPE array3 IS ARRAY (3 DOWNTO 0) OF array1;
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
1.

2.

a
b
x
y
w
z

:
:
:
:
:
:

BIT;
STD_LOGIC;:
array1;
array2;
array3;
STD_LOGIC_VECTOR (7 DOWNTO 0);

( 1 2
1x1)

a <= x(2);
b <= x(2);
b <= y(3,5);
b <= w(5)(3);
y(1)(0) <= z(7);
x(0) <= y(0,0);
x <= "1110000";
a <= "0000000";
y(1) <= x;
w(0) <= y;
w(1) <= (7=>'1', OTHERS=>'0');
y(1) <= (0=>'0', OTHERS=>'1');
w(2)(7 DOWNTO 0) <= x;
w(0)(7 DOWNTO 6) <= z(5 DOWNTO 4);
x(3) <= x(5 DOWNTO 5);
b <= x(5 DOWNTO 5);
y <= ((OTHERS=>'0'), (OTHERS=>'0'),
(OTHERS=>'0'), "10000001");
z(6) <= x(5);
z(6 DOWNTO 4) <= x(5 DOWNTO 3);
z(6 DOWNTO 4) <= y(5 DOWNTO 3);
y(6 DOWNTO 4) <= z(3 TO 5);
y(0, 7 DOWNTO 0) <= z;
w(2,2) <= '1';

VHDL

VHDL

(Operators)
VHDL 5

3.1

(assignment)

3.1.1

SIGNAL
VARIABLE
CONSTANT

<=

:=

=>

SIGNAL
VARIABLE
CONSTANT GENERIC

VHDL

: 20


1
2
3
4
5
6
7
8
9
10
11

ARCHITECTURE behav OF ex_41 IS

SIGNAL x : STD_LOGIC;
VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL w: STD_LOGIC_VECTOR(0 TO 7);
...
x <= '1';
y := "0000";
w <= "10000000";
w <= (0 =>'1', OTHERS =>'0');
...
END behav;

x <= '1';

1 x SIGNAL
x 1

y := "0000";

"0000" y
STD_LOGIC_VECTOR

w <= "10000000";

"10000000" w
STD_LOGIC_VECTOR

w <= (0 =>'1', OTHERS =>'0');

'1' w

0
( 1 7)

(Logic)

3.1.2

BIT
STD_LOGIC
STD_ULOGIC
BIT_VECTOR
STD_LOGIC_VECTOR
STD_ULOGIC_VECTOR

AND
OR
NOT
NAND
NOR
XOR
XNOR

Z <= (A AND B)
Z <= (A OR B)
Z <= NOT(A)
Z <= (A NAND B)
Z <= (A NOR B)
Z <= (A XOR B)
Z <= (A XNOR B)

VHDL

: 21


AND OR NAND NOR XOR VHDL
NOT

1
2
3
4
5

ARCHITECTURE behav OF ex_bit_vector IS

SIGNAL a,b,z
: BIT;
SIGNAL va,vb,vx : BIT_VECTOR(0 TO 2);
BEGIN
z <= NOT a AND b;
-- a.b

6
7
8

vx <= va NOR vb;

...
END behav;

--

(va+vb)

(Arithmetic)

3.1.3

INTEGER
SIGNED
UNSIGNED

STD_LOGIC_VECTOR
STD_LOGIC_VECTOR

package
std_logic_singed std_logic_unsinged LIBRARY ieee
STD_LOGIC_VECTOR
( 2.6)

+
*
/
**
MOD
REM
ABS

Z <= A+B
Z <= A-B
Z <= A*B
Z <= A/B
Z <= 4**2
Z <= A MOD B
Z <= A REM B
Z <= ABS(A)

1
2
3
4
5
6

ARCHITECTURE behav OF ex_bit_vector IS

SIGNAL a,b : INTEGER RANGE 0 TO 7;
SIGNAL z : INTEGER RANGE 0 TO 15;
BEGIN
z <= a + b;
END behav;

VHDL

: 22


(Comparison)


3.1.4

=
/=
<
>
<=
>=

IF (a = b) THEN
IF (a /= b) THEN
IF (a < b) THEN
IF (a > b) THEN
IF (a <= b) THEN
IF (a >= b) THEN

1
2
3
4
5
6
7
8
9
10
11

ARCHITECTURE behav OF ex_comp IS

SIGNAL a,b,z
: BIT;
BEGIN
...
IF A = B THEN
z <= 0;
ELSE
z <= 1;
END IF;
...
END behav;

(Concatenation)
&
3.1.5

&

Z <= A & B

1
2
3
4
5
6

ARCHITECTURE behav OF ex_conc IS

SIGNAL a,b,c
: BIT;
SIGNAL a_bus,b_bus : BIT_VECTOR(2 DOWNTO 0);
SIGNAL t_bus
: BIT_VECTOR(5 DOWNTO 0);
BEGIN
a_bus <= a & b & c;
--

7
8
9

t_bus <= a_bus & b_bus;

...
END behav;

--

VHDL

: 23


3.1
(operator)

NOT AND NAND OR NOR

XOR

XNOR

+ (mod,
=
>

&

* / **
rem, abs)
/=
<
<=
>=

(,,,)

: 24

(data
BIT
BIT_VECTOR
STD_LOGIC_VECTOR
STD_ULOGIC_VECTOR
INTEGER

SIGNED

type)

STD_LOGIC,
STD_ULOGIC

UNSIGNED

SIGNED UNSIGNED

(Data Attributes)


3.2

dLOW
dHigh
dLEFT
dRIGHT
dLENGTH
dRANGE
dREVERSE_RANGE

dLOW
dHIGH
dLEFT
dRIGHT
dLENGTH
dRANGE
dREVERSE_RANGE

dRANGE

1
2
3
4

ARCHITECTURE behav OF ex_att IS

SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);
...
END behav;

d'LOW 0
d'HIGH 7
d'LEFT 7
d'RIGHT 0
d'LENGTH 8
VHDL


d'RANGE 7 DOWNTO 0
d'REVERSE_RANGE 0 TO

LOOP
1
2
3
4
5
6
7
8
9
o

ARCHITECTURE behav OF ex_att2 IS

SIGNAL x : STD_LOGIC_VECTOR (7 DOWNTO 0);
...
FOR i IN RANGE(0 TO 7) LOOP ...
FOR i IN xRANGE LOOP ...
FOR i IN RANGE (xLOW TO xHIGH) LOOP ...
FOR i IN RANGE (0 TO xLENGTH-1) LOOP ...
...
END behav;

4 LOOP
5 7 LOOP

(Signal Attributes)


3.3

sEVENT
sSTABLE
sACTIVE
sQUIET<time>
sLAST_EVENT
sLAST_ACTIVE
sLAST_VALUE

sEVENT
sSTABLE
sACTIVE
sQUIET<time>
SLAST_EVENT
SLAST_ACTIVE
sLAST_VALUE

s
s
s
s 1


s 1
s

IF WAIT

VHDL

: 25


1
2
3
4
5
6
7

ARCHITECTURE behav OF ex_att3 IS

...
IF (clkEVENT AND clk = 1 THEN ...
IF (NOT clkSTABLE AND clk = 1 THEN ...
WAIT UNTIL (clkEVENT AND clk = 1) ;
...
END behav;

3 clk
4 clk
5 clk
o

Generic

ARCHITECTURE GENERIC

3.4

ENTITY ...
GENERIC (parameter_name : parameter_type := parameter_value;
PORT ...
END ... ;

3.5

VHDL

3.1 Decoder 3 8

Decoder sel 3 x 8
ena 1 decoder

3.1

Decoder

3 8

1 --------------------------------------------2 LIBRARY ieee;

3 USE ieee.std_logic_1164.all;
4 --------------------------------------------5 ENTITY decoder IS
6
PORT ( ena : IN STD_LOGIC;
7
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
8
x : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
9 END decoder;
10 --------------------------------------------11 ARCHITECTURE generic_decoder OF decoder IS

VHDL

: 26


12 BEGIN
13
PROCESS (ena, sel)
14
VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH DOWNTO 0);
15
VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH;
16
BEGIN
17
temp1 := (OTHERS => '1');
18
temp2 := 0;
19
IF (ena='1') THEN
20
FOR i IN sel'RANGE LOOP -- sel range is 2 downto 0
21
IF (sel(i)='1') THEN -- Bin-to-Integer conv.
22
temp2:=2*temp2+1;
23
ELSE
24
temp2 := 2*temp2;
25
END IF;
26
END LOOP;
27
temp1(temp2):='0';
28
END IF;
29
x <= temp1;
30
END PROCESS;
31 END generic_decoder;
32 --------------------------------------------o

+ 22
* 22 24

:= 17 18 22 24 27
<= 29
=> 17

xHIGH 14 15

3.2 3.1
VHDL 3.2 sel =
000 ( 0 ) x = 11111110 ( 254 )
sel = 010 ( 2 ) x = 11111011 (
251 )

VHDL

: 27


3.2 parityy

parity
n-1 n
GENERIC
n n

3.3 parity
1 ----------------------------------------------2 ENTITY parity_ge
en IS
3
GENE
ERIC (n : INTEGER := 7);
4
PORT
T ( input: IN BIT_V
VECTOR (n-1 DOWNTO 0);
5
output: OUT BIT_
_VECTOR (n
n DOWNTO 0
0));
6 END par
rity_gen;
7 ----------------------------------------------8 ARCHITE
ECTURE Beh
havior OF parity_ge
en IS
9 BEGIN
10
PROC
CESS (inpu
ut)
11
VARIABLE temp
p1: BIT;
12
VARIABLE temp
p2: BIT_VE
ECTOR (out
tput'RANGE
E);
13
BEGIN
14
temp1 := '0';
15
FOR i IN
I input'R
RANGE LOOP
P
16
t
temp1
:= temp1
t
XOR input(i);
17
t
temp2(i)
:= input(i
i);
18
END LOO
OP;
19
temp2(o
output'HIG
GH) := tem
mp1;
20
output <= temp2;
21
END PROCESS;
22 END Beh
havior;

3.4 3.2
VHDL
3.4
input = 0000000 ( 0 )) outpu
ut = 0000
00000 (

0 ))
input = 0000001 ( 1 )

output = 10000001 ( 81 )

VHDL

: 28


3.6

: 29

1 3
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL

a
b
c
d
e
f

:
:
:
:
:
:

BIT := '1';
BIT_VECTOR (3
BIT_VECTOR (3
BIT_VECTOR (7
INTEGER RANGE
INTEGER RANGE

DOWNTO 0) := "1100";
DOWNTO 0) := "0010";
DOWNTO 0);
0 TO 255;
-128 TO 127;

1.
x1 <= a & c;
x2 <= c & b;
x3 <= b XOR c;

x1 ________
x2 ________
x3 ________
x4 ________

x4 <= a NOR b(3);

x5 <= a AND NOT b(0) AND NOT c(1);
x5 ________
d <= (5=>'0', OTHERS=>'1');

2.
c'LOW
d'HIGH
c'LEFT
d'RIGHT
c'RANGE
d'LENGTH
c'REVERSE_RANGE

________

______
______
______
______
______
______
______

3.
b(0) AND a
a + d(7)
NOT b XNOR c
c + d
e - f
IF (b<c) ...
IF (b>=a) ...
IF (f/=e) ...
IF (e>d) ...
e*3
5**5
f/4
e/3
d <= c
d(6 DOWNTO 3) := b
e <= d
f := 100
4. 3.1

GENERIC m n

VHDL

= 2m

: 30

(concurrent code) VHDL

(combination logic)


VHDL
o WHEN
o GENERATE


WHEN
2

WHEN/ELSE
WITH/SELECT/WHEN
4.1

WHEN/ELSE
WHEN
4.1.1

assignment WHEN condition ELSE

assignment WHEN condition ELSE
...;

assignment (<=)

1
2
3
4
5
6
7

ARCHITECTURE behav OF ex_when1 IS

BEGIN
outp <= "000" WHEN (inp='0' OR resetn='1') ELSE
"001" WHEN ctl ='1' ELSE
"010";
...
END behav;

VHDL

: 31

outp 000 inp

0 resetn 1
outp 001 ctl
1 outp 010

WITH/ELSE condition

ELSE

4.1 Multiplexer
a
b

s1

s0

0
0
1
1

0
1
0
1

a
b
c
d

c
d

s1 s0

()

4.1 () Multiplexer

()
()

4.1 Multiplexer 4 1
4 a b c d (select) 2
s1 s0 1 y ENITY
5 8
y = a.s1.s0+ b.s1.s0 + c.s1.s0+ d.s1.s0
multiplexer y
10 16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

--------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------ENTITY mux41 IS
PORT (a,b,c,d,s0,s1 : IN STD_LOGIC;
y : OUT STD_LOGIC);
END mux41;
--------------------------------------ARCHITECTURE behave OF mux41 IS
BEGIN
y <= (a AND NOT s1 AND NOT s0) OR
(b AND NOT s1 AND s0) OR
(c AND s1 AND NOT s0) OR
(d AND s1 AND s0);
END behave;
---------------------------------------

VHDL

: 32

4.2 4.1
4.2 Multiplexer 2 WHEN/ELSE
Multiplexer
() 4.3()
a
b
y

c
d

s[1..0]

00
01
10
11

a
b
c
d

4.1

S[1..0]

()

4.3 () Multiplexer

()
()

4.3 5 a b c d (select)
2 s[1..0] 1 y ENITY
5 9 WHEN
y
11
1 ------------ with WHEN/ELSE --------------2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ------------------------------------------5 ENTITY mux41 IS
6
PORT ( a, b, c, d: IN STD_LOGIC;
7
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
8
y: OUT STD_LOGIC);
9 END mux41;
10 ------------------------------------------11 ARCHITECTURE behave1 OF mux41 IS
12 BEGIN
13
y <= a WHEN sel="00" ELSE
14
b WHEN sel="01" ELSE
15
c WHEN sel="10" ELSE
16
d;
17 END behave1;
18 -------------------------------------------

VHDL

: 33

WITH/SELECT/WHEN
WHEN WITH/SELECT
4.1.2

WITH identifier SELECT

assignment WHEN value,
assignment WHEN value,
...;

identifier value
assignment

1
2
3
4
5
6
7
8

ARCHITECTURE behav OF ex_when2 IS

BEGIN
WITH cont SELECT
outp <= "000" WHEN 00,
"111" WHEN 01,
"ZZZ" WHEN OTHERS;
...
END behav;

outp 000 cont

00 outp 111 cont
01 outp ZZZ cont

WHEN "...

WHEN value"

WHEN value

WHEN value1 to value2

WHEN value1 | value2

value
value1 value2
value1 value2

WITH/SELECT
value

WHEN value

VHDL


4.3

Multiplexer

WITH/SELECT/WHEN

1 ------------- with WITH/SELECT/WHEN ----2 LIBRARY ieee;

3 USE ieee.std_logic_1164.all;
4 ------------------------------------------5 ENTITY mux41 IS
6
PORT ( a, b, c, d: IN STD_LOGIC;
7
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
8
y: OUT STD_LOGIC);
9 END mux41;
10 ------------------------------------------11 ARCHITECTURE beahve2 OF mux41 IS
12 BEGIN
13
WITH sel SELECT
14
y <= a WHEN "00", -- notice "," instead of ";"
15
b WHEN "01",
16
c WHEN "10",
17
d WHEN OTHERS; -- cannot be "d WHEN "11" "
18 END behave2;
19 --------------------------------------------

7 sel STD_LOGIC_VECTOR 2
INTEGER WHEN/ELSE VHDL

1 ---------------------------------------------2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ---------------------------------------------5 ENTITY mux41 IS
6
PORT ( a, b, c, d: IN STD_LOGIC;
7
sel: IN INTEGER RANGE 0 TO 3;
8
y: OUT STD_LOGIC);
9 END mux41;
10 ---- Solution 1: with WHEN/ELSE --------------11 ARCHITECTURE behave1 OF mux41 IS
12 BEGIN
13
y <= a WHEN sel=0 ELSE
14
b WHEN sel=1 ELSE
15
c WHEN sel=2 ELSE
16
d;
17 END behave1;

WHEN/ELSE WITH/SELECT/WHEN
1 ---------------------------------------------2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ---------------------------------------------5 ENTITY mux41 IS
6
PORT ( a, b, c, d: IN STD_LOGIC;
7
sel: IN INTEGER RANGE 0 TO 3;
8
y: OUT STD_LOGIC);
9 END mux41;
10 ---- Solution 2: with WITH/SELECT/WHEN ---------------

VHDL

: 34

: 35

11 ARCHITE
ECTURE beh
have2 OF mux41
m
IS
12 BEGIN
13
y <=
= a WHEN 0,
14
b WHEN 1,
15
c WHEN 2,
16
d WHEN 3; -- her
re, 3 or OTHERS
O
are
e equivale
ent,
17 END beh
have2; -- for all options
o
ar
re tested anyway

4..4 Tri--state

Buf
ffer

4.4
Tri-state
T

Buffer

4.4 Tri-statte Buffer 8

ena
0

ena 1

(high
(
impe
edance)

VHDL
Z

VHDL


1 LIBRARY ieee;
2 USE ieee
e.std_logi
ic_1164.al
ll;
3 ---------------------------------------------4 ENTITY tri_state
t
IS
5
PORT
T ( ena: IN
I STD_LOG
GIC;
6
input: IN STD_LO
OGIC_VECTO
OR (7 DOWN
NTO 0);
7
output: OUT STD_
_LOGIC_VEC
CTOR (7 DO
OWNTO 0));
8 END tri_
_state;
9 ---------------------------------------------10 ARCHITE
ECTURE beh
have OF tr
ri_state IS
I
11 BEGIN
12
outp
put <= inp
put WHEN (ena='0') ELSE
13
(OT
THERS => 'Z');
14 END beh
have;
15 ----------------------------------------------

4..5 4.4
4

VHDL

: 36

4.5 Encoder
x[7..0]
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000

()

y[2..0]
000
001
010
011
100
101
110
111
()

4.6 () Encoder ()

Encoder 2n m
4.6 Encoder 8
3 Encoder

VHDL
o

WHEN/ELSE

1 ---- Solution 1: with WHEN/ELSE ------------2 LIBRARY ieee;

3 USE ieee.std_logic_1164.all;
4 --------------------------------------------5 ENTITY encoder IS
6
PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
7
y: OUT STD_LOGIC_VECTOR (2 DOWNTO 0));
8 END encoder;
9 --------------------------------------------10 ARCHITECTURE encoder1 OF encoder IS
11 BEGIN
12
y <= "000" WHEN x="00000001" ELSE
13
"001" WHEN x="00000010" ELSE
14
"010" WHEN x="00000100" ELSE
15
"011" WHEN x="00001000" ELSE
16
"100" WHEN x="00010000" ELSE
17
"101" WHEN x="00100000" ELSE
18
"110" WHEN x="01000000" ELSE
19
"111" WHEN x="10000000" ELSE
20
"ZZZ";
21 END encoder1;
22 ---------------------------------------------

VHDL

WITH/SELECT/WHEN

1 ---- Solution 2: with WITH/SELECT/WHEN -----2 LIBRARY ieee;

3 USE ieee.std_logic_1164.all;
4 --------------------------------------------5 ENTITY encoder IS
6
PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
7
y: OUT STD_LOGIC_VECTOR (2 DOWNTO 0));
8 END encoder;
9 --------------------------------------------10 ARCHITECTURE encoder2 OF encoder IS
11 BEGIN
12
WITH x SELECT
13
y <= "000" WHEN "00000001",
14
"001" WHEN "00000010",
15
"010" WHEN "00000100",
16
"011" WHEN "00001000",
17
"100" WHEN "00010000",
18
"101" WHEN "00100000",
19
"110" WHEN "01000000",
20
"111" WHEN "10000000",
21
"ZZZ" WHEN OTHERS;
22 END encoder2;
23 ---------------------------------------------

4.5 (ALU)

4.8 () ALU

4.8() 8

5 .8()

package std_logic_unsigned LIBRARY
ieee

VHDL

: 37

()
4.8 ()
1 ---------------------------------------------2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 USE ieee.std_logic_unsigned.all;
5 ---------------------------------------------6 ENTITY ALU IS
7
PORT (a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
8
sel: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
9
cin: IN STD_LOGIC;
10
y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
11 END ALU;
12 ---------------------------------------------13 ARCHITECTURE dataflow OF ALU IS
14 SIGNAL arith, logic: STD_LOGIC_VECTOR (7 DOWNTO 0);
15 BEGIN
16 ----- Arithmetic unit: -----17
WITH sel(2 DOWNTO 0) SELECT
18
arith <= a
WHEN "000",
19
a+1 WHEN "001",
20
a-1 WHEN "010",
21
b
WHEN "011",
22
b+1 WHEN "100",
23
b-1 WHEN "101",
24
a+b WHEN "110",
25
a+b+cin WHEN OTHERS;
26 ----- Logic unit: ----------27
WITH sel(2 DOWNTO 0) SELECT
28
logic <= NOT a WHEN "000",
29
NOT b WHEN "001",
30
a AND b WHEN "010",
31
a OR b WHEN "011",
32
a NAND b WHEN "100",
33
a NOR b WHEN "101",
34
a XOR b WHEN "110",
35
NOT (a XOR b) WHEN OTHERS;

VHDL

: 38



36 -------- Mux: --------------37
WITH
H sel(3) SELECT
S
38
y <= ar
rith WHEN '0',
39
lo
ogic WHEN OTHERS;
40 END dat
taflow;
41 ----------------------------------------------

4.9
5.5
GENERRATE

2
4.2

FOR
R/GENERATE
E
IF/GENERATE

FOR/GENNERATE

FOR

4.2.1

[label] : FOR ident

tifier IN range GEN
NERATE
(concur
rrent assi
ignment)
END GENER
RATE;

iddentifier
(raange)

identifieer
label
FOR//GENERATE (

FORR/GENERATEE
o

1
2
3
4
5
6
7
8
9
10
11
12
13
14

ARCHIT
TECTURE be
ehav OF ex
x_U IS
SIGNAL
L x: BIT_V
VECTOR (7 DOWNTO 0)
);
SIGNAL
L y: BIT_V
VECTOR (15
5 DOWNTO 0);
0
SIGNAL
L z: BIT_V
VECTOR (7 DOWNTO 0)
);
...
G1: FOR
F
i IN x'RANGE
x
GE
ENERATE
z
z(i)
<= x(i) AND y(i+8);
E
END
GENERA
ATE;
...
OK: FOR i IN 0 TO 7 GE
ENERATE
output(i)<='1' WHE
EN (z(i) AND
A
y(i+1))='1' ELS
SE '0';
END GENER
RATE;
...
END behave;

VHDL

: 39

IF/GENEERATE
IF

FOR/GENER
RATE

4.2.2

[label_1] : FOR ide

entifier IN
I range GENERATE
G
...
[label_2] : IF con
ndition GE
ENERATE
(concurr
rent assig
gnment)
END GENE
ERATE labe
el_2;
...
END GENE
ERATE labe
el_1;

4..6 (vector shifter) GENERRATE

1111

row(0
0)
row(1
1)
row(2
2)
row(3
3)
row(4
4)

=
=
=
=
=

0000
01111
0001
11110
0011
11100
0111
11000
1111
10000

VHDL
4

8
5
( 0 4)

4.10
4.5
1 LIBRARY ieee;
2 USE ieee
e.std_logi
ic_1164.al
ll;
3 ENTITY shifter IS
S
4
PORT
T ( inp: IN
I STD_LOG
GIC_VECTOR
R (3 DOWNT
TO 0);
5
sel: IN
I INTEGER
R RANGE 0 TO 4;
6
outp: OUT STD_L
LOGIC_VECT
TOR (7 DOW
WNTO 0));
7 END shif
fter;
8 -----------------------------------------------9 ARCHITEC
CTURE shif
fter OF sh
hifter IS
10 SUBTYPE
E vector IS
I STD_LOG
GIC_VECTOR
R (7 DOWNT
TO 0);
11 TYPE ma
atrix IS ARRAY
A
(4 DOWNTO
D
0) OF vector
r;
12 SIGNAL row: matr
rix;
13 BEGIN
13
row(0) <= "00
000" & inp
p;
14
G1: FOR i IN 1 TO 4 GE
ENERATE
15
row(i) <= row(i-1)(6 DOWN
NTO 0) & '0';
16
END GENERATE;
17
outp
p <= row(s
sel);
18 END shi
ifter;

VHDL

: 40


4.3

Multiplexer 8 1 2
2. Priority Encoder

1.

A[7..0]

W[3..0]

0000000
00000001
0000001X
000001XX
00001XXX
0001XXXX
001XXXXX
01XXXXXX
1XXXXXXX

XXX0
0001
0011
0101
0111
1001
1011
1101
1111

X=dont care
3. Binary decoder

A[2..0]

Y[7..0]

000
001
010
011
100
101
110
111

00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000

4.

5.

VHDL

: 41

: 42

(sequential
code)
(sequential circuit) (
)
(present state)

5.1

()

()
5.1() ()
VHDL

o
o
o

PROCESS
FUNCTION
PROCEDURE

IF WAIT CASE LOOP

PROCESS
PROCESS

5.1

[label:] PROCESS (sensitivity list)

[VARIABLE variable_name : type [range] [:= initial_value;]]
BEGIN
(sequential code)
END PROCESS [label];

VHDL

: 43

PROCESS (sensitivity list)

( )
PROCESS sequential code
label PROCESS
VARIABLE ( 5.3)
PROCESS END PROCESS label (
)
PROCESS IF
BEGIN END PROCESS sequential code

WAIT CASE

LOOP

VARIABLE SIGNAL
SIGNAL
()

<=
5.2

[SIGNAL signal_name : type [range] [:= initial_value;]]

VARIABLE

PROCESS
sequential code
:=

[VARIABLE variable_name : type [range] [:= initial_value;]]

VARIABLE SIGNAL variable_name

signal_name VARIABLE SIGNAL type
initial_value

VHDL


1
2
3
4
5
6
7
8
9
10
11
12
13
14

----------EXAMPLE SIGNAL---------------------------SIGNAL sel : BIT_VECTOR (2 DOWNTO 0) := 000;

SIGNAL count,temp : INTEGER RANGE 0 TO 59;
...
count <= count + 1 AFTER 5 ns;
temp <= temp 1 AFTER 10 ns;
...
-----------EXAMPLE VARIABLE-------------------------VARIABLE opcode : BIT_VECTOR (3 DOWNTO 0) := 0000;
VARIABLE freq,direction : INTEGER;
...
freq := clk + direction;
...
----------------------------------------------------

IF PROCESS
IF ( WHEN)

5.3

IF conditions THEN assignments;

ELSIF conditions THEN assignments;
...
ELSE assignments;
END IF;

IF 2 ELSIF
1
2
3
4
5
6
7
8
9
10
11

------- IF/THEN/ELSE---------------VARIABLE count1,count2 : STD_LOGIC_VECTOR( 3 DOWNTO 0);

... PROCESS(clk)
...
IF (clk = 1) then
count1 := count1 + 1;
ELSE
count2 := count2 1;
END IF;
...
-----------------------------------

IF 2 ELSIF
1
2
3
4
5
6
7
8
9
10
11
12

------- IF/THEN/ELSIF/ELSE---------------VARIABLE cnt1,cnt2 : STD_LOGIC_VECTOR( 3 DOWNTO 0);

VARIABLE sel : STD_LOGIC_VECTOR( 1 DOWNTO 0);
... PROCESS(clk,sel)
...
IF sel = 00 then count1 := count1 + 1;
ELSIF sel = 01 then count1 := count1 1;
ELSIF sel = 10 then count2 := count2 + 1;
ELSE count2 := count2 1;
END IF;
...
-----------------------------------

VHDL

: 44



5..1

)

PROCESS IF

PROCCESS clkk rst

5.11

1 -------------------------------------2 LIBRARY ieee;

3 USE ieee
e.std_logi
ic_1164.al
ll;
4 -------------------------------------5 ENTITY dff
d
IS
6
PORT
T (d, clk, rst: IN STD_LOGIC
C;
7
q: OUT STD_LOGIC
C);
8 END dff;
9 -------------------------------------10 ARCHITE
ECTURE beh
havior OF dff IS
11 BEGIN
12 PROCESS
S (clk, rs
st)
13
BEGIN
14
IF (rst
t='1') THE
EN
15
q <=
< '0';
16
ELSIF (clk'EVENT
T AND clk=
='1') THEN
N
17
q <=
< d;
18
END IF;
19 END PROCESS;
20 END beh
havior;
21 --------------------------------------

5.2 5.1

VHDL

: 45


5.2 0 9 1
1 0 9
4 (910 = 10012)
( 5 8)
PROCESS temp
VARIABLE 20
temp PROCESS
digit

5.3 1
1 --------------------------------------------2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 --------------------------------------------5 ENTITY counter IS
6
PORT (clk : IN STD_LOGIC;
7
digit : OUT INTEGER RANGE 0 TO 9);
8 END counter;
9 --------------------------------------------10 ARCHITECTURE counter OF counter IS
11 BEGIN
12
count: PROCESS(clk)
13
VARIABLE temp : INTEGER RANGE 0 TO 10;
14
BEGIN
15
IF (clk'EVENT AND clk='1') THEN
16
temp := temp + 1;
17
IF (temp=10) THEN temp := 0;
18
END IF;
19
END IF;
20
digit <= temp;
21
END PROCESS count;
22 END counter;
23 ---------------------------------------------

VHDL

: 46


WAIT PROCESS
WAIT PROCESS
PROCESS

PROCESS

PROCESS
WAIT

5.4

WAIT

5.4.1

WAIT ON

WAIT ON signal1,[signal2,...];

1
2
3
4
5
6
7
8
9
10

5.4.2

-------------------------------------------PROCESS (clk,rst,sel)
BEGIN
WAIT ON clk, rst;
IF (rst='1') THEN
output <= "00000000";
ELSIF (clk'EVENT AND clk='1') THEN
output <= input;
END IF;
END PROCESS;
11 ---------------------------------------------

WAIT UNTIL

WAIT UNTIL condition;

5.4.3

WAIT FOR

WAIT FOR time;

VHDL

: 47


1
2
3
4
5
6
7
8
9
10
11
12
13

: 48

-------------------------------------------------PROCESS
-- no sensitivity list
BEGIN
WAIT UNTIL (clk'EVENT AND clk='1');
IF (rst='1') THEN
WAIT FOR 10 ns;
output <= "00000000";
ELSIF (clk'EVENT AND clk='1') THEN
WAIT FOR 10 ns;
output <= input;
END IF;
END PROCESS;
--------------------------------------------------

5.4 2

5.1 WAIT ON

1 -------------------------------------2 LIBRARY ieee;

3 USE ieee.std_logic_1164.all;
4 -------------------------------------5 ENTITY dff IS
6
PORT (d, clk, rst: IN STD_LOGIC;
7
q: OUT STD_LOGIC);
8 END dff;
9 -------------------------------------10 ARCHITECTURE dff OF dff IS
11 BEGIN
12
PROCESS
13
BEGIN
14
WAIT ON rst, clk;
15
IF (rst='1') THEN
16
q <= '0';
17
ELSIF (clk'EVENT AND clk='1') THEN
18
q <= d;
19
END IF;
20
END PROCESS;
21 END dff;
22 --------------------------------------

5.5 0 9 1 2

5.2 WAIT

1
2
3
4
5
6
7
8
9

--------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------------ENTITY counter IS
PORT (clk : IN STD_LOGIC;
digit : OUT INTEGER RANGE 0 TO 9);
END counter;
---------------------------------------------

VHDL

UTIL


10
11
12
13
14
15
16
17
18
19
20
21
22

ARCHITECTURE counter OF counter IS

BEGIN
PROCESS -- no sensitivity list
VARIABLE temp : INTEGER RANGE 0 TO 10;
BEGIN
WAIT UNTIL (clk'EVENT AND clk='1');
temp := temp + 1;
IF (temp=10) THEN temp := 0;
END IF;
digit <= temp;
END PROCESS;
END counter;
---------------------------------------------

WAIT ON WAIT

o

: 49

FOR

ON UTIL

ON FOR

UTIL FOR

CASE PROCESS
CASE WHEN
WITH/SELECT/WHEN ( 4.3) CASE

5.5

CASE identifier IS
WHEN value => assignment1, assignment2;
WHEN value => assignment1, assignment2;
...
END CASE;

CASE identifier
value (assignment)
CASE
PROCESS
1 --- sequential code -------2 ----CASE/WHEN--------------3 CASE control IS
4
WHEN "00" => x<=a; y<=b;
5
WHEN "01" => x<=b; y<=c;
6
WHEN OTHERS => x<="0000";
7
y<="ZZZZ";
8 END CASE;
------------------------------

VHDL

: 50

1------ concurrent code --------2----------WITH/SELECT/WHEN------3 WITH control SELECT

4
x <= a WHEN "00",
5
b WHEN "01",
6
"0000" WHEN OTHERS;
7 ...

CASE/WHEN WITH/SELECT/WHEN
5.1
5.1 CASE/WHEN WITH/SELECT/WHEN
WITH/SELECT/WHEN
-
-
-
-

PROCESS
FUNCTION PROCEDURE

CASE/WHEN

PROCESS
FUNCTION PROCEDURE

5.6 (7-segment display)

0 9
BCD to seven segment display 5.4
(Decoder)
(common)
(common anode) (common cathode)

1
(segment)a g 5.4

VHDL 4 7 (
dot) ENTITY
0
1 a f 111 1110
16
26

5.4

VHDL



1 -------------------------------------------------2 LIBRARY
Y ieee;
3 USE iee
ee.std_log
gic_1164.a
all;
4 -------------------------------------------------5 ENTITY bcd_ssd IS
I
6
PORT
T (bcd_dat
ta : IN ST
TD_LOGIC_V
VECTOR(3 D
DOWNTO 0);
7
digit1 : OUT STD
D_LOGIC_VE
ECTOR (6 D
DOWNTO 0));
8 END bcd
d_ssd;
9 -------------------------------------------------10 ARCHITE
ECTURE beh
have OF bc
cd_sssd IS
S
11 BEGIN
12
PROC
CESS(bcd_d
data)
13
BEGIN
14 ---- BC
CD to seve
en segment
t display conversio
on: -------15
CASE bc
cd_data IS
S
16
W
WHEN
"0000
0" => digi
it1 <= "11
111110"; --7E
17
W
WHEN
"0001
1" => digi
it1 <= "01
110000"; --30
18
W
WHEN
"0010
0" => digi
it1 <= "11
101101"; --6D
19
W
WHEN
"0011
1" => digi
it1 <= "11
111001"; --79
20
W
WHEN
"0100
0" => digi
it1 <= "01
110011"; --33
21
W
WHEN
"0101
1" => digi
it1 <= "10
011011"; --5B
22
W
WHEN
"0110
0" => digi
it1 <= "10
011111"; --5F
23
W
WHEN
"0111
1" => digi
it1 <= "11
110000"; --70
24
W
WHEN
"1000
0" => digi
it1 <= "11
111111"; --7F
25
W
WHEN
"1001
1" => digi
it1 <= "11
111011"; --7B
26
W
WHEN
OTHER
RS => NULL
L;
27
END CAS
SE;
28
END PROCESS;
29 END beh
have;
30 --------------------------------------------------

5.5 5.6
5..7 0 7

0 7 3

1 ------ Solution
S
1 With a VARIABLE -------1:
2 ENTITY counter
c
IS
S
3
PORT
T ( clk, rst:
r
IN BI
IT;
4
count: OUT INTEG
GER RANGE 0 TO 7);
5 END coun
nter;
6 -------------------------------------------7 ARCHITEC
CTURE coun
nter OF co
ounter IS
8 BEGIN
9 PROCESS (clk, rst
t)
10
VARIABLE temp
p: INTEGER
R RANGE 0 TO 7;
11
BEGIN
12
IF (rst
t='1') THE
EN
13
t
temp:=0;
14
ELSIF (clk'EVENT
T AND clk=
='1') THEN
N
15
t
temp
:= te
emp+1;

VHDL

: 51



16
END IF;
17
count <=
< temp;
18
END PROCESS;
19 END cou
unter;
20 --------------------------------------------

1 ------ Solution
S
2 With SI
2:
IGNALS onl
ly ------2 ENTITY counter
c
IS
S
3
PORT
T ( clk, rst:
r
IN BI
IT;
4
count: BUFFER INTEGER
I
RA
ANGE 0 TO 7);
5 END coun
nter;
6 -------------------------------------------7 ARCHITEC
CTURE coun
nter OF co
ounter IS
8 BEGIN
9
PROC
CESS (clk, rst)
10
BEGIN
11
IF (rst
t='1') THE
EN
12
c
count
<= 0;
0
13
ELSIF (clk'EVENT
T AND clk=
='1') THEN
N
14
c
count
<= count
c
+ 1;
15
END IF;
16
END PROCESS;
17 END cou
unter;
18 --------------------------------------------

5.6 5.7
5..8
(PIISO)

(load)
( )
0

1 --------------------------------------------------2 LIBRARY
Y ieee;
3 USE iee
e.std_logi
ic_1164.al
ll;
4 --------------------------------------------------5 ENTITY piso IS
6 PORT(cl
lk,resetn,ld_shf : in std_lo
ogic; -c
clock,rese
etn,load/s
shift
7
da
ata_in
: in std_l
logic_vect
tor(4 down
nto 1); --Data
input
8
da
ata_out : out std_
_logic
--Data
o
output
9
);
10 END piso;
11 ----------------------------------------------------

VHDL

: 52



12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

ARCHITE
ECTURE beh
havioral of
o piso IS
S
CONSTAN
NT reset_a
active : std_logic
s
:= '0';
BEGIN
PROC
CESS(
c
clk,
reset
tn)
VARIABLE temp
p_a,temp_b
b : std_lo
ogic_vecto
or(4 downt
to 1);
BEGIN
-------clear out
tput regis
ster----------------------IF(rese
etn = rese
et_active) THEN
t
temp_a
:= (OTHERS =>
= '0');
------ On rising
g edge of clock, lo
oad/shift in data
ELSIF (clk'EVENT
T and clk = '1') TH
HEN
-------load data
a ---------------------------------I
IF(ld_shf
= '1') TH
HEN
temp
p_a := dat
ta_in;
----------shift data------------------------------E
ELSE
temp
p_b := tem
mp_a;
temp
p_a (4) :=
= temp_b (
(3);
temp
p_a (3) :=
= temp_b (
(2);
temp
p_a (2) :=
= temp_b (
(1);
temp
p_a (1) :=
= '0';
E
END
IF;
END IF;
data_ou
ut <= temp
p_a(4);
END PROCESS;
END beh
havioral;
-----------------------------------------------------

5.7 5.8

VHDL

: 53

: 54

5.9 (Frequency divider) 1Mhz 100 khz

(Osillator)

n = 1,000,000/100,000

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

= 10

LIBRARY ieee;
USE ieee.std_logic_1164.All;
USE ieee.std_logic_unsigned.All;
ENTITY freq_div IS
PORT(clk,resetn : IN STD_LOGIC;
clk_out : OUT STD_LOGIC;
q : OUT INTEGER RANGE 0 TO (10-1)
END freq_div;

);

ARCHITECTURE Behav OF freq_div IS

SIGNAL count : INTEGER RANGE 0 TO (10-1) := 0;
SIGNAL temp : STD_LOGIC;
BEGIN
PROCESS (clk,resetn)
BEGIN
IF (resetn = '0' OR count > (10-1)) THEN
count <= 0;
ELSIF (clk'EVENT AND clk = '1') THEN
count <= count + 1;
IF count > ((10/2)-1) THEN
temp <= '1';
ELSE temp <= '0';
END IF;
END IF;
q <= count;
clk_out <= temp;
END PROCESS;
END Behav;

5.8 5.9

VHDL


5.6

: 55

1. Carry Ripple Adder

sj = aj XOR bj XOR cj
cj+1 = (aj AND bj)OR(aj AND cj)OR(bj AND cj)
GENERIC FOR/LOOP

5.5 00 99 2
3. 5.6
0 F 1
4. 5.9 50hz
2.

1hz
5.

12 50
)

hz

VHDL

: 56

(state)
-

( 6.1)
1.
2 (
) (pr_state) 2
(nx_state)
2.

3
1

nx_state

pr_state

6.1

VHDL


1.

(Mealy
state machine)

2.

(Moore state machine)

6.1 VHDL

VHDL

1 :
2 :
1:

(4) (5)
PROCESS CASE/WHEN

1
2
3
4
5
6
7
8
9

---------- part 1 : combinational ---------------PROCESS (pr_state)

BEGIN
CASE pr_state IS
WHEN state0 => output <= <value>;
WHEN state1 => output <= <value>;
...
END CASE;
END PROCESS;

PROCESS pr_state
PROCESS
4 pr_state

2:

PROCESS

PROCESS ()

PROCESS
(state0)
1

VHDL

: 57


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

---------- part 2 : sequential -----------------PROCESS(input,pr_state)

BEGIN
CASE pr_state IS
WHEN state0 =>
IF (input = ...) THEN
nx_state <= state1;
END IF;
WHEN state1 =>
IF (input = ...) THEN
nx_state <= state2;
END IF;
...
END CASE;
END IF;
END PROCESS;
------------ Update state ----------------------PROCESS(reset,clock)
BEGIN
IF (reset='1') THEN
pr_state <= state0;
ELSIF (clock'EVENT AND clock='1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;

1 2
VHDL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------------------------ENTITY <entity_name> IS
PORT ( input: IN <data_type>;
reset, clock: IN STD_LOGIC;
output: OUT <data_type>);
END <entity_name>;
----------------------------------------------------ARCHITECTURE <arch_name> OF <entity_name> IS
TYPE state IS (state0, state1, state2, state3, ...);
SIGNAL pr_state,nx_state : state;
BEGIN
---------- part 2 section: -----------------------PROCESS(input,pr_state)
BEGIN
CASE pr_state IS
WHEN state0 =>
IF (input = ...) THEN
nx_state <= state1;
END IF;
WHEN state1 =>
IF (input = ...) THEN
nx_state <= state2;
END IF;
...
END CASE;
END IF;

VHDL

: 58


29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

END PROCESS;
-------------- Update state --------------------PROCESS(reset,clock)
BEGIN
IF (reset='1') THEN
pr_state <= state0;
ELSIF (clock'EVENT AND clock='1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;
---------- part 1 section: -----------------------PROCESS (pr_state)
BEGIN
CASE pr_state IS
WHEN state0 => output <= <value>;
WHEN state1 => output <= <value>;
...
END CASE;
END PROCESS;
END <arch_name>;

6.1 6.2

S0 S1 S2 S3
x 1
0000 1011 1100 1010
S0 S1 S2 S3
S0

6.2 6.1

6.3 6.1

VHDL

: 59

6.4 6.1
VHDL
11 15 44
46 54
6.3 6.4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------------------------ENTITY exam_fsm_moore1 IS
PORT ( x: IN STD_LOGIC;
reset, clock: IN STD_LOGIC;
z: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
END exam_fsm_moore1;
----------------------------------------------------ARCHITECTURE fsm OF exam_fsm_moore1 IS
TYPE state IS (S0, S1, S2, S3);
SIGNAL pr_state,nx_state : state;
BEGIN
---------- part 2 section: -----------------------PROCESS (reset, clock)
BEGIN
IF (reset='1') THEN
pr_state <= S0;
ELSIF (clock'EVENT AND clock='1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;
--------------------------------------------------PROCESS (x,pr_state)
BEGIN
CASE pr_state IS
WHEN S0 =>

VHDL

: 60


28
IF (x = '1') THEN
29
nx_state <= S1;
30
END IF;
31
WHEN S1 =>
32
IF (x = '1') THEN
33
nx_state <= S2;
34
END IF;
35
WHEN S2 =>
36
IF (x = '1') THEN
37
nx_state <= S3;
38
END IF;
39
WHEN S3 =>
40
IF (x = '1') THEN
41
nx_state <= S0;
42
END IF;
43
END CASE;
44
END PROCESS;
45 ---------- part 1 section: -----------------------46
PROCESS (pr_state)
47
BEGIN
48
CASE pr_state IS
49
WHEN S0 => z <= "0000";
50
WHEN S1 => z <= "1011";
51
WHEN S2 => z <= "1100";
52
WHEN S3 => z <= "1010";
53
END CASE;
54
END PROCESS;
55 END fsm;
56 ----------------------------------------------

6.2 13140

5 S0 S1 S2 S3 S4
1 3 1 4 0 6.5
x 1 reset
1 S0
S4 S0

6.5 13140

VHDL

: 61


VHDL
11 15 48
50 59
6.6
6.7

6.6 6.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------------------------ENTITY exam_fsm_moore_13140 IS
PORT ( x: IN STD_LOGIC;
reset, clock: IN STD_LOGIC;
z: OUT INTEGER RANGE 0 TO 9 );
END exam_fsm_moore_13140;
----------------------------------------------------ARCHITECTURE fsm OF exam_fsm_moore_13140 IS
TYPE state IS (S0, S1, S2, S3, S4);
SIGNAL pr_state,nx_state : state;
BEGIN
---------- part 2 section: -----------------------PROCESS (reset, clock)
BEGIN
IF (reset='1') THEN
pr_state <= S0;
ELSIF (clock'EVENT AND clock='1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;
--------------------------------------------------PROCESS (x,pr_state)
BEGIN
CASE pr_state IS
WHEN S0 =>
IF (x = '1') THEN
nx_state <= S1;
END IF;
WHEN S1 =>
IF (x = '1') THEN
nx_state <= S2;
END IF;
WHEN S2 =>
IF (x = '1') THEN
nx_state <= S3;
END IF;
WHEN S3 =>
IF (x = '1') THEN
nx_state <= S4;
END IF;
WHEN S4 =>

VHDL

: 62

: 63

44
IF (x = '1') THEN
45
nx_state <= S0;
46
END IF;
47
END CASE;
48
END PROCESS;
49 ---------- part 1 section: -----------------------50
PROCESS (pr_state)
51
BEGIN
52
CASE pr_state IS
53
WHEN S0 => z <= 1;
54
WHEN S1 => z <= 3;
55
WHEN S2 => z <= 1;
56
WHEN S3 => z <= 4;
57
WHEN S4 => z <= 0;
58
END CASE;
59
END PROCESS;
60 END fsm;

pr_state
nx_state.S0_160
clk

PRE
D

ENA
CLR

nx_state.S1_147
PRE
D

nx_state.S0_160

S0

nx_state.S1_147

S1

nx_state.S2_134

S2

nx_state.S3_121

S3

nx_state.S4_108

S4

z~0

reset

ENA
CLR

nx_state.S2_134
PRE
D

ENA
CLR

nx_state.S3_121
PRE
D

ENA
CLR

nx_state.S4_108
PRE
D

ENA
CLR

reset
clock

6.7 6.2

VHDL

1' h0 --

z[3..0]


6.2 VHDL

VHDL
1
1
LIBRARY ieee;
2
USE ieee.std_logic_1164.all;
3
---------------------------------------------------4
ENTITY <entity_name> IS
5
PORT ( input: IN <data_type>;
6
reset, clock: IN STD_LOGIC;
7
output: OUT <data_type>);
8
END <entity_name>;
9
---------------------------------------------------10
ARCHITECTURE <arch_name> OF <entity_name> IS
11
TYPE state IS (state0, state1, state2, state3, ...);
12
SIGNAL pr_state,nx_state : state;
13
BEGIN
14
---------- part 2 section: -----------------------15
PROCESS(input,pr_state)
16
BEGIN
17
CASE pr_state IS
18
WHEN state0 =>
19
IF (input = ...) THEN
20
nx_state <= state1;
21
END IF;
22
WHEN state1 =>
23
IF (input = ...) THEN
24
nx_state <= state2;
25
END IF;
26
...
27
END CASE;
28
END IF;
29
END PROCESS;
30
-------------- Update state -------------------31
PROCESS(reset,clock)
32
BEGIN
33
IF (reset='1') THEN
34
pr_state <= state0;
35
ELSIF (clock'EVENT AND clock='1') THEN
36
pr_state <= nx_state;
37
END IF;
38
END PROCESS;
39 ---------- part 1 section: ---------------------40
PROCESS (input,pr_state)
41
BEGIN
42
CASE pr_state IS
43
WHEN state0 =>
44
IF (input = ...) THEN
45
output <= <value>;
46
ELSE
47
output <= <value>;
48
END IF;
49
WHEN state1 =>
50
IF (input = ...) THEN
51
output <= <value>;
52
ELSE

VHDL

: 64


53
output <= <value>;
54
END IF;
55
...
56
END CASE;
57
END PROCESS;
58 END <arch_name>;

6.3 6.8

S0 S1 S2 S3
11 2

6.8 6.3
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.all;
3 ----------------------------------------------------4 ENTITY exam_fsm_mealy_1 IS
5 PORT ( x: IN STD_LOGIC;
6
reset, clock: IN STD_LOGIC;
7
z: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
8 END exam_fsm_mealy_1;
9 ----------------------------------------------------10 ARCHITECTURE fsm OF exam_fsm_mealy_1 IS
11 TYPE state IS (S0, S1, S2, S3);
12 SIGNAL pr_state,nx_state : state;
13 BEGIN
14 ---------- part 2 section: -----------------------15
PROCESS (reset, clock)
16
BEGIN
17
IF (reset='1') THEN
18
pr_state <= S0;
19
ELSIF (clock'EVENT AND clock='1') THEN
20
pr_state <= nx_state;
21
END IF;
22
END PROCESS;
23 --------------------------------------------------24
PROCESS (x,pr_state)
25
BEGIN
26
CASE pr_state IS

VHDL

: 65


27
WHEN S0 =>
28
IF (x = '1') THEN
29
nx_state <= S1;
30
END IF;
31
WHEN S1 =>
32
IF (x = '1') THEN
33
nx_state <= S2;
34
END IF;
35
WHEN S2 =>
36
IF (x = '1') THEN
37
nx_state <= S3;
38
END IF;
39
WHEN S3 =>
40
IF (x = '1') THEN
41
nx_state <= S0;
42
END IF;
43
WHEN S4 =>
44
IF (x = '1') THEN
45
nx_state <= S0;
46
END IF;
47
END CASE;
48
END PROCESS;
49 ---------- part 1 section: ---------------------50
PROCESS (x,pr_state)
51
BEGIN
52
CASE pr_state IS
53
WHEN S0 =>
54
IF (x='1') THEN
55
Z <= "1011";
56
ELSE
57
Z <= "1111";
58
END IF;
59
WHEN S1 =>
60
IF (x='1') THEN
61
Z <= "1100";
62
ELSE
63
Z <= "1111";
64
END IF;
65
WHEN S2 =>
66
IF (x='1') THEN
67
Z <= "1010";
68
ELSE
69
Z <= "1111";
70
END IF;
71
WHEN S3 =>
72
IF (x='1') THEN
73
Z <= "0000";
74
ELSE
75
Z <= "1111";
76
END IF;
77
END CASE;
78
END PROCESS;
79 END fsm;

6.9
6.10
6.1

VHDL

: 66

: 67

6.9 6.3
pr_state

Selector5

nx_state.S0_130
D

z~1

clk

PRE
Q

ENA
CLR

nx_state.S1_118

nx_state.S0_130

S0

nx_state.S1_118

S1

nx_state.S2_106

S2

nx_state.S3_94

S3

SEL[1..0]
OUT

1' h1 --

Selector6

DATA[1..0]

reset

PRE
D

ENA
CLR

SEL[1..0]

SELECTOR
OUT

1' h1 --

DATA[1..0]

nx_state.S2_106
PRE
D

SELECTOR

ENA
CLR

Selector4

nx_state.S3_94
SEL[1..0]

PRE
D
ENA
CLR

OUT

1' h1 --

DATA[1..0]

SELECTOR

reset
clock

0
1

z~0

6.10 6.3

VHDL

z[3..0]

: 68

6.3
1.

6.1

VHDL

6.1
2.

6.2 BCD

counter

6.2
3.

6.3

VHDL

6.3

VHDL

VHDL


4.

6.4

VHDL

6.4

VHDL

: 69

: 70

VHDL
VHDL
VHDL VHSIC Hardware Description Language (VHIC : Very High speed Integrated Circuit)
(High Level Language)
- VHDL .. 1981
.. 1985 VHDL
IEEE .. 1987
VHDL IEEE 1076-1987 ..1993
IEEE 1076-1993
VHDL
IEEE
VHDL

VHDL IEEE VHDL

VHDL
VHDL VHDL

VHDL Electronic boxes

VHDL

VHDL

VHDL


CPLD FPGA .1

.1

VHDL

: 71

 .
VHDL
VHDL

(Object Name)
() A-Z , a-z , 0-9,
_ (underscore)


(_)

(case insensitive)

entity_name
VHDL 87 VHDL
VHDL 87 93 2002
. XNOR
VHDL 87 VHDL 93

VHDL

: 72

: 73

VHDL
From VHDL 87:
ABS
ACCESS
AFTER
ALIAS
ALL
AND
ARCHITECTURE
ARRAY
ASSERT
ATTRIBUTE
BEGIN
BLOCK
BODY
BUFFER
BUS
CASE
COMPONENT
CONFIGURATION
CONSTANT
DISCONNECT
DOWNTO
ELSE
ELSIF
END

ENTITY
EXIT
FILE
FOR
FUNCTION
GENERATE
GENERIC
GUARDED
IF
IN
INOUT
IS
LABEL
LIBRARY
LINKAGE
LOOP
MAP
MOD
NAND
NEW
NEXT
NOR
NOT
NULL
OF
ON

OPEN
OR
OTHERS
OUT
PACKAGE
PORT
PROCEDURE
PROCESS
RANGE
RECORD
REGISTER
REM
REPORT
RETURN
SELECT
SEVERITY
SIGNAL
SUBTYPE
THEN
TO
TRANSPORT
TYPE
UNITS
UNTIL
USE
VARIABLE

VHDL

WAIT
WHEN
WHILE
WITH
XOR

From VHDL 93:

GROUP
IMPURE
INERTIAL
LITERAL
POSTPONED
PURE
REJECT
ROL
ROR
SHARED
SLA
SLL
SRA
SRL
UNAFFECTED
XNOR

: 74

Standard Package STD_LOGIC_1164

-- This package shall be compiled into a design library
-- symbolically named IEEE.

package STD_LOGIC_1164 is
------------------------------------------------------------------------------------ logic State System (unresolved)
----------------------------------------------------------------------------------type STD_ LOGIC is (
U,
-- Uninitialized
X,
-- Forcing Unknown
0,
-- Forcing
0
1,
-- Forcing
1
Z
-- High Impedance
W,
-- Weak Unknown
L,
-- Weak 0
H,
-- Weak 1
-
-- dont care
);
------------------------------------------------------------------------------------ Unconstrained array of std_ulogic for use with the
-- resolution function
----------------------------------------------------------------------------------type STD_ULOGIC_VECTOR is array ( NATURAL range <> ) of STD-ULOGIC;
------------------------------------------------------------------------------------ resolution function
------------------------------------------------------------------------------------ function RESOLVED ( S : STD_ULOGIC_VECTOR ) return STD_ULOGIC;
------------------------------------------------------------------------------------ *** industry standard logic type ***
----------------------------------------------------------------------------------subtype STD-LOGIC is RESOLVED STD_ULOGIC;
------------------------------------------------------------------------------------ Unconstrained array of std_logic for use in declaring
-- signal arrays
----------------------------------------------------------------------------------type STD_LOGIC_VECTOR is array ( NATURAL range <> )of STD_LOGIC;
------------------------------------------------------------------------------------ common subtypes
----------------------------------------------------------------------------------subtype X01 is RESOLVED STD_ULOGIC range X to 1;
-- (X, 0, 1)
subtype X01Z is RESOLVED STD_ULOGIC range X to Z; -- (X, 0, 1, Z;)
subtype UX01 is RESOLVED STD_ULOGIC range U to 1; -- (U, X, 0, 1)
subtype UX01Z is RESOLVED STD_ULOGIC range U to Z; -- (U, X, 0, 1, Z)
------------------------------------------------------------------------------------ overloaded logical operators

VHDL

: 75

----------------------------------------------------------------------------------function and ( L : STD_ULOGIC; R : STD_ULOGIC ) return UX01;

function nand (L : STD_ULOGIC; R : STD_ULOGIC ) return UX01;
function or (L : STD_ULOGIC; R : STD_ULOGIC ) return UX01;
function xor (L : STD_ULOGIC; R : STD_ULOGIC ) return UX01;
function xnor (L : STD_ULOGIC; R : STD_ULOGIC ) return UX01;
function not (L : STD_ULOGIC ) return UX01;
------------------------------------------------------------------------------------ vectorized overloaded logical operators
----------------------------------------------------------------------------------function and ( L, R : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR;
function and ( L, R : STD_ULOGIC_VECTOR ) return STD_ULOGIC_VECTOR;
function nand ( L, R : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR;
function nand ( L, R : STD_ULOGIC_VECTOR ) return STD_ULOGIC_VECTOR;
function or ( L, R : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR;
function or ( L, R : STD_ULOGIC_VECTOR ) return STD_ULOGIC_VECTOR;
function nor ( L, R : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR;
function nor ( L, R : STD_ULOGIC_VECTOR ) return STD_ULOGIC_VECTOR;
function xor ( L, R : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR;
function xor ( L, R : STD_ULOGIC_VECTOR ) return STD_ULOGIC_VECTOR;
function xnor ( L, R : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR;
function xnor ( L, R : STD_ULOGIC_VECTOR ) return STD_ULOGIC_VECTOR;
function not ( L : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR;
function not ( L : STD_ULOGIC_VECTOR ) return STD_ULOGIC_VECTOR;
------------------------------------------------------------------------------------ conversion functions
----------------------------------------------------------------------------------function TO_BIT ( S : STD_ULOGIC; XMAP : BIT :=0) return BIT;
function TO_BITVECTOR (S : STD_LOGIC_VECTOR; XMAP : BIT :=0) return BIT_VECTOR
function TO_BITVECTOR (S : STD_ULOGIC_VECTOR;XMAP : BIT :=0) return BIT_VECTOR
function TO_STDULOGIC( B : BIT ) return STD_ULOGIC;
function TO_STDLOGICVECTOR(B : BIT_VECTOR) return STD_LOGIC_VECTOR;
function TO_STDLOGICVECTOR(S : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function TO_STDULOGICVECTOR(B : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function TO_STDULOGICVECTOR(S : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
------------------------------------------------------------------------------------ strength strippers and type converters
----------------------------------------------------------------------------------function TO_X01 ( S : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR;
function TO_X01 ( S : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function TO_X01 ( S : STD_ULOGIC ) return X01;
function TO_X01 ( B : BIT_VECTOR ) return STD_LOGIC_VECTOR;
function TO_X01 ( B : BIT_VECTOR ) return STD_ULOGIC_VECTOR;
function TO_X01 ( B : BIT ) return X01;
function TO_X01Z ( S : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR;
function TO_X01Z ( S : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function TO_X01Z ( S : STD_ULOGIC ) return X01Z;
function TO_X01Z ( B : BIT_VECTOR ) return STD_LOGIC_VECTOR;
function TO_X01Z ( B : BIT_VECTOR ) return STD_ULOGIC_VECTOR;
function TO_X01Z (B : BIT ) return X01Z;
function TO_UX01 ( S : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR;
function TO_UX01 ( S : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function TO_UX01 ( S : STD_ULOGIC ) return UX01;
function TO_UX01 ( B : BIT_VECTOR ) return STD_LOGIC_VECTOR;
function TO_UX01 ( B : BIT_VECTOR ) return STD_ULOGIC_VECTOR;
function TO_UX01 ( B : BIT ) return UX01;
------------------------------------------------------------------------------------ edge detection
----------------------------------------------------------------------------------function RISING_EDGE (signal S : STD_ULOGIC) return BOOLEAN;

VHDL

 .
function FALLING_EDGE (signal S : STD_ULOGIC) return BOOLEAN;
------------------------------------------------------------------------------------ object contains an unknown
----------------------------------------------------------------------------------function IS_X ( S : STD_ULOGIC_VECTOR ) return BOOLEAN;
function IS_X ( S : STD_LOGIC_VECTOR ) return BOOLEAN;
function IS_X ( S : STD_ULOGIC ) return BOOLEAN;
end STD_LOGIC_1164;

VHDL

: 76

: 77

Quartus II
VHDL

Quartus II Altera
(CPLD) (FPGA)
2
o Schemetic Block diagam
Library
o Text
(VHDL) (Verilog)
VHDL
1.

Quartus II

VHDL

: 78

2.
Quartus II File / New Project Wizard
Wizard

2
1

(1) Next
(3)
(5) Next

(2) Folders Directory

(4) Directory

4
6

(6)
(7)

VHDL

: 79

(8) Next

(9) Finish

3. File / New VHDL

File

1
3

(1) New
(3) OK

(2) VHDL File

VHDL1.vhd

VHDL

VHDL

4.
F = ab c + b c + ad

VHDL
library ieee;
use ieee.std_logic_1164.all;
entity lab1 is
port ( a,b,c,d : in
std_logic;
f
: out std_logic);
end lab1;
architecture behavior of lab1 is
begin
f <= (a and b and not c) or (b and not c)
or (not a and d);
end behavior;

File / Save as lab1.vhd

( )

VHDL

: 80

 .
5. Processing / Complier Tool Start
error warning
error

6.
simulate
File / New Other Files
Vector Waveform File

7.
Node Edit / Insert / Insert Node or Bus
Node Fider Node Finder Filter :
Pins : all List

VHDL

: 81

() Node
Simulate () >>

Simulate

8.
Edit / End Time
1.0 us
9.
Edit / Grid size 100 ns
Node b a
Edit /
Value / Clock Period 100 200 ( Period
2n Grid size )

VHDL

: 82

1
Group
Group

Group ( )
Edit / Grouping / Group
Group name Radix

10.
11.

Waveform File / Save as

Lab1.vwf
Process / Simulator Tool Start
-

VHDL

: 83

 .
Simulation Report Waveform
Processing / Simulation Debug / Overwrite Vector Inputs with Simulation Outputs

VHDL

: 84

: 85

. , VHDL,
Armstrong J. R. and F. G. Gray, VHDL Design Representation and
Synthesis, Englewood Clis, NJ: Prentice Hall, 2nd Edition, 2000.
3. Bhasker J., VHDL Primer, Englewood Clis, NJ: Prentice Hall,3rd
Edition, 1999.
4. Chang K. C., Digital Systems Design with VHDL and SynthesisAn
Integrated Approach, Los Alamitos,CA: IEEE Computer Society
Press, 1999.
5. Hamblen J. and M. Furman, Rapid Prototyping of Digital Systems,
Boston: Kluwer Academic Publisher,2nd Edition, 2001.
6. Naylor D. and S. Jones, VHDL: A Logic Synthesis Approach,
London: Chapman & Hall, 1997.
7. Navabi Z., VHDL Analysis and Modeling of Digital Systems, New
York: McGraw-Hill, 1993.
8. Pellerin D. and D. Taylor, VHDL Made Easy, Englewood Cliffs, NJ:
Prentice Hall, 1997.
9. Perry D. L., VHDL, New York: McGraw-Hill, 2nd Edition, 1994.
10. Yalamanchili S., Introductory VHDL from Simulation to Synthesis,
Englewood Clis, NJ: Prentice Hall,2001.
11. Yalamanchili S., VHDL Starters Guide, Englewood Cliffs, NJ:
Prentice Hall, 1998.
12. Volnei A. Pedroni.,Circuit Design with VHDL,Massachusetts,MIT
Press,2004.
1.
2.

VHDL