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Digital Principles
Switching Theory
THIS PAGE IS
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DIGITAL PRINCIPLES
SWITCHING
THEORY
A.K. Singh
Manish Tiwari
Arun Prakash
Department of Electronics
& Instrumentation Engineering
Northern India Engineering College
Lucknow.
Copyright © 2006, New Age International (P) Ltd., Publishers
Published by New Age International (P) Ltd., Publishers
All rights reserved.
No part of this ebook may be reproduced in any form, by photostat, microfilm,
xerography, or any other means, or incorporated into any information retrieval
system, electronic or mechanical, without the written permission of the
publisher. All inquiries should be emailed to rights@newagepublishers.com
ISBN (10) : 81-224-2306-X
ISBN (13) : 978-81-224-2306-8
PUBLISHING FOR ONE WORLD
NEW AGE INTERNATIONAL (P) LIMITED, PUBLISHERS
4835/24, Ansari Road, Daryaganj, New Delhi - 110002
Visit us at www.newagepublishers.com
Dedicat ed t o
Our Parents
Though no one can go back and make a brand new st ar t,
any one can st ar t from now and make a brand new end.
THIS PAGE IS
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PREFACE
Digit al Elect r onic is int ended as a compr ehensive t ext for t he cour ses in digit al elect r onic
cir cuit s. The object ive of t his book is t o develop in t he r eader t he abilit y t o analyze and design
t he digit al cir cuit s. The incr eased uses of digit al t echnology in object s used for day-t o-day life
necessit at e an in-dept h knowledge of t he subject for t he pr ofessionals and engineer s.
Ther e ar e lot s of r efer ences available on Swit ching Theor y and Basic Digit al Cir cuit s,
which discuss var ious t opics separ at ely. But t hr ough t his t ext our not ion was t o discover t he
t opics r at her t han t o cover t hem. This compr ehensive t ext fulfills t he cour se r equir ement on
t he subject of digit al cir cuit design for B. Tech degr ee cour se in Elect r onics, Elect r onics and
Communicat ion, Elect r onics and Elect r ical, Elect r onics and Inst r ument at ion, Elect r onics
Inst r ument at ion and Cont r ol, Inst r ument at ion and Cont r ol Engineer ing of differ ent t echnical
Univer sit ies. This t ext is also bound t o ser ve as a useful r efer ence book for var ious compet it ive
examinat ions.
Ther e is no special pr e-r equisit e befor e st ar t ing t his book. Each chapt er of t he book
st ar t s wit h simple fact s and concept s, and t r aver se t hr ough t he examples & figur es it uncover s
t he advanced t opics.
The book st ar t s fr om chapt er 0. It is ver y obvious because in t he wor ld of digit al
elect r onics t he ver y fir st level is 0 and t hen comes t he last level called 1. This is t he r eason
why all t he chapt er s of t his book have subsect ions number ed st ar t ing fr om 0.The book has
11 well-or ganized chapt er s and 2 appendices.
Chapt er 0 is int r oduct ion and is a must for all t he beginner s as it int r oduces t he concept
of digit al signals and digit al syst ems. It at t empt s t o answer why and wher e t he digit al cir cuit s
are used what are t heir advant ages. Chapt er 1 deals wit h number syst ems and t heir arit hmet ic.
It includes an exhaust ive set of solved examples and exer cise t o clar ify t he concept s. Chapt er
2 int r oduces t he basic building blocks of digit al elect r onics. It st ar t s wit h basic post ulat es,
Boolean algebr a and t hen int r oduces logic gat es. It also deals wit h sever al t ypes of t ypes of
implement at ion using logic gat es. For beginner s we st r ongly r ecommend t o wor k out t his
chapt er t wice befor e pr oceeding fur t her.
Chapt er 3 deals wit h t he Boolean funct ion minimizat ion t echniques using Post ulat es and
Boolean Algebr a, K-Map and Quine-McCluskey met hods. Chapt er 4 pr esent s var ious
combinat ional logic design using t he discr et e logic gat es and LSI & MSI cir cuit s. This chapt er
also deals wit h hazar ds and fault det ect ion. Chapt er 5 int r oduces t he Pr ogr ammable Logic
(vi i)
Devices. It also deals wit h basics of ROM, and t hen moves t owar ds PLAs, PALs, CPLDs and
FPGA.
Chapt er 6 int r oduces t he clocked (synchr onous) sequent ial cir cuit s. It st ar t s wit h
discussions on var ious flip-flops t heir t r igger ing and flip-flop t imings. It t hen deals wit h
analysis and design of synchr onous cir cuit s and concludes wit h sequence det ect or cir cuit s.
Chapt er 7 deals wit h shift r egist er s and count er s. It int r oduces t he basic idea of shift r egist er s
and t hen discusses var ious modes and applicat ion of shift r egist er s. It t hen int r oduces t he
var ious t ypes and modes of count er s and concludes wit h applicat ions. Chapt er 8 deals wit h
asynchronous sequent ial circuit s. It elaborat es t he analysis and design procedures wit h different
consider at ions. Chapt er 9 int r oduces t he Algor it hmic St at e Machine. It st ar t s wit h basic
concept s, design t ools and concludes wit h design using mult iplexer s.
Chapt er 10 int r oduces t he fundament als of digit al int egr at ed cir cuit s- The Digit al Logic
Families. The chapt er has an indept h analysis of semiconduct or swit ching devices and var ious
logic families wit h det ailed qualit at ive and quant it at ive descr ipt ions. Cir cuit s ar e simplified
t opologically and equivalent cir cuit s ar e dr awn separ at ely t o clar ify t he concept s. Chapt er 11
deals wit h t he semiconduct or memor y devices t o be used wit h comput er syst em. It also
includes memor y syst em designs and int r oduces Magnet ic and Opt ical memor ies also.
The t ext also includes t wo r ich appendices giving infor mat ion about ICs fabr icat ion,
var ious digit al ICs, and list s var ious digit al ICs.
All t he t opics ar e illust r at ed wit h clear diagr am and simple language is used t hr oughout
t he t ext t o facilit at e easy under st anding of t he concept s. The aut hor s welcome const r uct ive
s u gges t ion a n d commen t s fr om t h e r ea der s for t h e impr ovemen t of t h is book a t
singh_a_k@r ediffmail.com or at manisht iwar i_me@r ediffmail.com
A.K. SINGH
MANISH TIWARI
ARUN PRAKASH
(viii )
ACKNOWLEDGEMENT
This book is t he r esult of t he dedicat ion and encour agement of many individuals. We ar e
also t hankful t o our Dir ect or s and all our colleagues at BBD Gr oup of Educat ional Inst it ut ions.
We would like t o t hank our family member s especially wife and daught er for t heir
pat ience and cont inuing suppor t and our par ent s for t heir blessings.
We ar e indebt ed t o our fr iend and colleague Ar un Pr akash, for his invaluable cont r ibut ion
and involvement in t he pr oject .
We t hankfully acknowledge t he cont r ibut ions of var ious aut hor s, dat a manuals, jour nals,
r efer ence manuals et c. fr om wher e mat er ials have been collect ed t o enr ich t he cont ent s of
t he book.
Finally, We would like t o t hank t he people at New Age Int er nat ional (P) Limit ed,
especially Mr. L.N. Mishr a, who cont inues suppor t and encour ages wr it ing and who made t he
book a r ealit y. Thanks ar e also due t o Mr. Soumya Gupt a, M.D. New Age Int er nat ional (P)
Limit ed for his involvement in t he pr oject .
In last but not t he least by t he blessing of almight y and good for t une we get such a
suppor t ing and cooper at ive people ar ound us who in one way or ot her help us t o complet e
t his pr oject in t ime.
A.K. SINGH
MANISH TIWARI
ARUN PRAKASH
(ix)
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CONTENTS
Preface (v)
Acknowledgement (vii)
CHAPTER 0: INTRODUCTION TO DIGITAL ELECTRONICS 1
CHAPTER 1: NUMBERING SYSTEMS 12
1.0 Int r oduct ion 12
1.1 Number ing Syst ems 12
1.1.1 A Review of t he Decimal Syst em 12
1.1.2 Binar y Number ing Syst em 12
1.1.3 Binar y For mat s 14
1.2 Dat a Or ganizat ion 15
1.2.1 Bits 15
1.2.2 Nibbles 15
1.2.3 Byt es 16
1.2.4 Wor ds 17
1.2.5 Double Words 17
1.3 Oct al Number ing Syst em 18
1.3.1 Oct al t o Decimal, Decimal t o Oct al Conver sion 19
1.3.2 Oct al t o Binar y, Binar y t o Oct al Conver sion 19
1.4 Hexadecimal Number ing Syst em 20
1.4.1 Hex t o Decimal, Decimal t o Hex Conver sion 21
1.4.2 Hex t o Binar y, Binar y t o Hex Conver sion 21
1.4.3 Hex t o Oct al, Oct al t o Hex Conver sion 21
1.5 Range of Number Repr esenat ion 22
1.6 Binary Arit hmat ic 24
1.7 Negat ive Number & Their Ar it hmat ic 26
1.7.1 1’s & 2’s Complement 27
1.7.2 Subt r act ion Using 1’s & 2’s Complement 29
1.7.3 Signed Binar y Repr esent at ion 31
1.7.4 Ar it hmat ic Over flow 33
1.7.5 9’s & 10’s Complement 34
(xi)
1.7.6 r’s Complement and (r–1)’s Complement 35
1.7.7 Rules for Subt r act ion using r ’s and (r–1)’s Complement 35
1.8 Binar y Coded Decimal (BCD) & It s Ar it hmat ic 37
1.9 Codes 40
1.9.1 Weight ed Binar y Codes 40
1.9.2 Non-Weighbt ed Codes 43
1.9.3 Er r or Det ect ing Codes 45
1.9.4 Er r or Cor r ect ing Codes 47
1.9.5 Hamming Code 49
1.9.6 Cyclic Codes 52
1.10 Solved Examples 54
1.11 Exer cises 62
CHAPTER 2: DIGITAL DESIGN FUNDAMENTALS–BOOLEAN
ALGEBRA & LOGIC GATES 63
2.0 Int r oduct or y Concept s of Digit al Design 63
2.1 Truth Table 63
2.2 Axiomat ic Syst ems and Boolean Algebr a 65
2.2.1 Hunt ingt on’s Post ulat e 66
2.2.2 Basic Theorems and Propert ies of Boolean Algebra 67
2.3 Boolean Funct ions 69
2.3.1 Tr ansfor mat ion of a Boolean Funct ions int o Logic Diagr am 71
2.3.2 Complement of a Funct ion 71
2.4 Repr esent at ion of a Boolean Funct ion 72
2.4.1 Mint er m & Maxt er m Realizat ion 73
2.4.2 St andar d For ms—SOP & POS 75
2.4.3 Conver sion bet ween St andar d For ms 77
2.5 Digit al Logic Gat es 77
2.5.1 Posit ive & Negat ive Logic Designat ion 77
2.5.2 Gat e Definit ion 78
2.5.3 The and Gat e 79
2.5.4 The or Gat e 80
2.5.5 The Inver t er & Buffer 82
2.5.6 Ot her Gat es & Their Funct ion 84
2.5.7 Univer sal Gat es 84
2.5.8 The Exclusive OR (Ex-OR) Gat e 88
2.5.9 The Exclusive NOR (Ex-NOR) Gat e 91
(xi i )
2.5.10 Ext ension t o Mult iple Input s in Logic Gat es 92
2.6 NAND-NOR Implement at ion (Two Level) 97
2.6.1 Implement at ion of a Mult ist age (Or Mult ilevel) Digit al Cir cuit
Using NAND Gat es Only 97
2.6.2 Implement at ion of a Mult ist age (Or Mult ilevel) Digit al Cir cuit s
Using NOR Gat es Only 99
2.7 Exer cises 101
CHAPTER 3: BOOLEAN FUNCTION MINIMIZATION TECHNIQUES 112
3.0 Int r oduct ion 112
3.1 Minimizat ion using Post ulat es & Theorems of Boolean Algebr a 112
3.2 Minizat ion using Kar naugh Map (K-Map) Met hod 113
3.2.1 Two and Three Var iable K-Map 114
3.2.2 Boolean Expr esion Minizat ion Using K-Map 116
3.2.3 Minimizat ion in Pr oduct s of Sums For m 119
3.2.4 Four Var iable K-Map 120
3.2.5 Pr ime and Essent ial Implicant s 123
3.2.6 Don’t Car e Map Ent r ies 124
3.2.7 Five Var ibale K-Map 125
3.2.8 Six Var ibale K-Map 127
3.2.9 Mult i Out put Minimizat ion 129
3.3 Minimizat ion Using Quine-McCluskey (Tabular ) Met hod 130
3.4 Exer cises 136
CHAPTER 4: COMBINATIONAL LOGIC 141
4.0 Int r oduct ion 141
4.1 Ar it hmat ic Cir cuit s 143
4.1.1 Addres 143
4.1.2. Subt r act or s 146
4.1.3 Code Conver t er s 149
4.1.4 Par it y Gener at or s & Checker s 153
4.2 MSI & LSI Cir cuit s 155
4.2.1 Mult iplexer s 156
4.2.2 Decoder s (DeMult iplexer s) 159
4.2.3 Encoder s 167
4.2.4 Ser ial & Parallel Adders 169
4.2.5 Decimal Adder 174
4.2.6 Magnit ude Compar at or s 177
(xi i i )
4.3 Hazards 179
4.3.1 Hazar ds in Combinat ional Cir cuit s 179
4.3.2 Types of Hazar ds 181
4.3.3 Hazar d Fr ee Realizat ions 182
4.3.4 Essent ial Hazar ds 184
4.3.5 Significance of Hazar ds 185
4.4 Fault Det ect ion and Locat ion 185
4.4.1 Classical Met hod 185
4.4.2 The Fault Table Met hod 186
4.4.3 Fault Dir ect ion by Pat h Sensit izing 189
4.5 Exer cises 192
CHAPTER 5: PROGRAMMABLE LOGIC DEVICES 196
5.0 Int r oduct ion 196
5.1 Read Only Memor y (ROM) 196
5.1.1 Realizing Logical Funct ions wit h ROM 198
5.2 PLAs : Programmable Logical Arrays 199
5.2.1 Realizing Logical Funct ions wit h PLAs 201
5.3 PALs : Programmable Ar r ay Logic 202
5.3.1 Commercially Available SPLDS 204
5.3.2 Generic Ar r ay Logic 204
5.3.3 Applicat ions of PLDs 205
5.4 Complex Pr ogr ammable Logic Devices (CPLD) 206
5.4.1 Applicat ions of CPLDs 207
5.5 FPGA : Field Programmable Gat e Arrays 207
5.5.1 Applicat ions of FPGAs 209
5.6 User-Pr ogr ammable Swit ch Technologies 210
5.7 Exer cises 211
CHAPTER 6: SYNCHRONOUS (CLOCKED) SEQUENTIAL LOGIC 213
6.0 Int r oduct ion 213
6.1 Flip Flops 214
6.1.1 RS Flip Flop 216
6.1.2 D-Flip Flop 220
6.1.3 Clocked of Flip Flop 222
6.1.4 Tr igger ing of Flip Flops 231
6.1.5 J K & T Flip Flop 232
6.1.6 Race Ar ound Condit ion & Solut ion 235
(xi v)
6.1.7 Oper at ing Char act er ist ics of Flip-Flop 236
6.1.8 Flip-Flop Applicat ions 237
6.2 Flip-Flop Excit at ion Table 238
6.3 Flip Flop Conver sions 239
6.4 Analysis of Clocked Sequent ial Cir cuit s 241
6.5 Designing of Clocked Sequent ial Cir cuit s 246
6.6 Finit e St at e Machine 250
6.7 Solved Examples 256
6.7 Exer cises 262
CHAPTER 7: SHIFT REGISTERS AND COUNTERS 265
7.0 Int r oduct ion 265
7.1 Shift Regist er s 265
7.2 Modes of Oper at ion 268
7.2.1 Ser ial IN – Ser ial Out Shift Regist er s (SISO) 268
7.2.2 Ser ial IN – Par allel Out Shift Regist er s (SIPO) 269
7.2.3 Par allel IN – Ser ial Out Shift Regist er s (PISO) 270
7.2.4 Par allel IN – Par allel Out Shift Regist er s (PIPO) 270
7.2.5 Bidir ect ional Shift Regist er s 270
7.3 Applicat ions of Shift Regist er s 271
7.3.1 To Produce Time Delay 271
7.3.2 To Simplify Combinat ional Logic 271
7.3.3 To Conver t Ser ial Dat a t o Par allel Dat a 272
7.4 Count er s 272
7.4.1 Int r oduct ion 272
7.4.2 Binar y Ripple Up-Count er 272
7.4.3 4-Bit Binar y Ripple Up-Count er 275
7.4.4 3-Bit Binar y Ripple Down Count er 277
7.4.5 Up-Down Count er s 278
7.4.6 Reset and Pr eset Funct ions 279
7.4.7 Univer sal Synchr onous count er St age 280
7.4.8 Synchr onous Count er ICs 282
7.4.9 Modulus Count er s 287
7.4.10 Count er Reset Met hod (Asynchr onous Count er ) 288
7.4.11 Logic Gat ing Met hod 295
7.4.12 Design of Synchr ous Count er s 299
7.4.13 Lockout 305
(xv)
7.4.14 MSI Count er IC 7490 A 307
7.4.15 MSI Count er IC 7492 A 313
7.4.16 Ring Count er 316
7.4.17 J ohnson Count er 318
7.4.18 Ring Count er Applicat ions 322
7.5 Exer cises 328
CHAPTER 8: ASYNCHRONOUS SEQUENTIAL LOGIC 331
8.0 Int r oduct ion 331
8.1 Differ ence Bet ween Synchronous and Asynchr onous 333
8.2 Modes of Oper at ion 334
8.3 Analysis of Asynchr onous Sequent ial Machines 335
8.3.1 Fundament al Mode Cir cuit s 335
8.3.2 Cir cuit s Wit hout Lat ches 335
8.3.3 Transit ion Table 338
8.3.4 Flow Table 339
8.3.5 Cir cuit s wit h Lat ches 340
8.3.6 Races and Cycles 345
8.3.7 Pulse-Mode Cir cuit s 346
8.4 Asynchr onous Sequent ial Cir cuit Design 349
8.4.1 Design St eps 349
8.4.2 Reduct ion of St at es 351
8.4.3 Mer ger Diagr am 352
8.5 Essent ial Hazar ds 353
8.6 Hazar d-Fr ee Realizat ion Using S-R Flip-Flops 354
8.7 Solved Examples 357
8.8 Exer cises 361
CHAPTER 9: ALGORITHMIC STATE MACHINE 362
9.0 Int r oduct ion 362
9.1 Design of Digit al Syst em 362
9.2 The Element s and St ruct ure of t he ASM Chart 363
9.2.1 ASM Block 365
9.2.2 Regist er Oper at ion 365
9.2.3 ASM Char t s 366
9.2.4 MOD-5 Count er 368
9.2.5 Sequence Det ect or 369
(xvi )
9.3 Timing Consider at ion 371
9.4 Dat a Pr ocessing Unit 375
9.5 Cont r ol Design 376
9.5.1 Mult iplexer Cont r ol 377
9.5.2 PLA Cont r ol 379
9.6 Exer cises 379
CHAPTER 10: SWITCHING ELEMENTS & IMPLEMENTATION OF LOGIC
GATES 382
10.0 Int r oduct ion 382
10.1 Fundament als of Semiconduct or s and Semiconduct or Swit ching Devicer 382
10.1.1 Semiconduct or s 382
10.1.2 Semiconduct or Diode or PN J unct ion 385
10.1.3 Bipolar J unct ion Tr ansist or (BJ Ts) 391
10.2 Char act er ist ics of Logic Families 403
10.2.1 Classificat ions of Logic Families 403
10.2.2 Char act er ist ics of Digit al ICs and Familier 404
10.3 Implement at ion of Logic Families 407
10.3.1 Basic Diode Logic 407
10.3.2 Resistor Tr ansist or Logic (RTL) 410
10.3.3 Direct Coupled Tr ansist or Logic (DCTL) 415
10.3.4 Diode Tr ansist or Logic (DTL) 415
10.3.5 High Thr eshold Logic (HTL) 422
10.3.6 Tr ansist or-Tr ansist or Logic (TTL) 423
10.3.7 Emit t er Coupled Logic (ECL) 431
10.3.8 MOS Logic 438
10.3.9 Thr ee St at e Logic (TSL) 444
10.4 Int er facing of Logic Gat es 446
10.4.1 TTL t o CMOS Int er facing 446
10.4.2 CMOS t o TTL Int er facing 447
10.5 Compar ison of Logic Families 448
10.8 Exer cises 448
CHAPTER 11: MEMORY FUNDAMENTALS 452
11.0 Int r oduct ion 452
11.1 Memor y Basics 452
11.2 Memor y Char act er ist ics 453
(xvi i )
11.3 Mass St or age Devices 455
11.3.1 Magnat ic Memor y 455
11.3.2 Opical Memor y 457
11.4 Semiconduct or Memor y 458
11.4.1 Basic Memor y Unit 458
11.4.2 Basic Memor y Or ganizat ion 459
11.4.3 Cell Or ganizat ion (Memor y Addr essing) 460
11.4.3.1 Mat r ix Addr essing 461
11.4.3.2 Addr ess Decoding 461
11.4.4 Organizing Wor d Lengt hs (Differ ent Memor y Or ganizat ion) 464
11.4.5 Classificat ion of Semiconduct or Memor y 468
11.4.6 Semiconduct or Memor y Timing 469
11.4.6.1 Memory Wr it e Oper at ion 470
11.4.6.2 Memor y Read Oper at ion 471
11.4.7 Read Only Memor y 472
11.4.7.1 Some Simple ROM Or ganizat ions 473
11.4.7.2 Mask Pr ogr ammed ROMs 475
11.4.8 Pr ogammable Read Only Memor y (PROM) 476
11.4.8.1 Bi-Polar PROMS 477
11.4.8.2 MOS PROMS 478
11.4.8.3 PROM Pr ogr amming 478
11.4.9 Pr ogammable Read Only Memor y (EPROM) 479
11.4.9.1 EPROM Pr ogr amming 480
11.4.9.2 The 27XXX EPROM Ser ies 480
11.4.10 Elect r ically Er asable Pr ogammable Read Only Memor y
(EEPROM) 481
11.4.11 Random Access Memor y (RAM) 482
11.4.12 St at ic Random Access Memory (SRAM) 482
11.4.12.1 The Bi-Polar SRAM Cell 483
11.4.12.2 The MOS SRAM Cell 484
11.4.12.3 SRAM ICs 485
11.4.13 Dynamic Random Access Memory (DRAM) 486
11.4.13.1 Basic DRAM Cell 486
11.4.13.2 One MOS Tr ansist or DRAM Cell 487
11.4.13.3 DRAM Or ganizat ion 488
11.4.14.4 DRAM St r uct ur e 489
11.4.14 SRAMS and DRAMS 491
(xvi i i )
11.4.15 Memor y Syst em Design 492
11.4.15.1 Det ermining Address Lines and Addr ess Range 492
11.4.15.2 Par allel and Ser ies Connect ions of Memor y 493
11.4.15.3 Address Space Allocat ion 494
11.4.15.4 For mat ion of Memor y Syst em 495
11.5 Exer cises 505
APPENDICES 517
A: Int egr at ed Cir cuit s Fabr icat ion Fundament als
B: Digit al ICs
REFERENCES 517
INDEX 518
(xi x)
THIS PAGE IS
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0.1 INTRODUC TION
Engineer s gener ally classify elect r onic cir cuit s as being eit her analog or digit al in nat ur e.
Hist or ically, most elect r onic pr oduct s cont ained elect r onic cir cuit r y. Most newly designed
elect r onic devices cont ain at least some digit al cir cuit r y. This chapt er int r oduces you t o t he
wor ld of digit al elect r onics.
What ar e t he clues t hat an elect r onic pr oduct cont ains digit al cir cuit r y? Signs t hat a
device cont ains digit al cir cuit r y include:
1. Does it have an alphanumer ic (shows let t er s and number s) display?
2. Does it have a memor y or can it st or e infor mat ion?
3. Can t he device be pr ogr ammed?
If t he answer t o any one of t he t hr ee quest ions is yes, t hen t he pr oduct pr obably cont ains
digit al cir cuit r y.
Digit al cir cuit r y is quickly becoming per vasive because of it s advant ages over analog
including:
1. Generally, digit al circuit s are easier t o design using modern int egrat ed circuit s (ICs).
2. Infor mat ion st or age is easy t o implement wit h digit al.
3. Devices can be made pr ogr ammable wit h digit al.
4. Mor e accur acy and pr ecision is possible.
5. Digit al cir cuit r y is less affect ed by unwant ed elect r ical int er fer ences called noise.
The ver y basic digit al design can be defined as t he science of or ganizing ar r ays of simple
swit ches int o what is called a discr et e syst em t hat per for m t r ansfor mat ions on t wo-level
(binar y) infor mat ion in a meaningful and pr edict able way. Cer t ainly t his is t r ue, but digit al
design as we know it t oday is much mor e excit ing t han t his definit ion pr ot ends. Digit al design
has mat ur ed since 1938 when Claude Shannon syst emized t he ear lier t heor et ical wor k of
Geor ge Boole (1854). Since t hen, design met hods and devices have been developed, t r ied and
pr oven, leading t he way int o one of t he most fascinat ing and challenging fields of st udy.
Keep in mind t hat seldom will you find a field of st udy as vast as t hat of digit al design
and it s r elat ed applicat ions, yet seldom will you find a field in which you can become mor e
pr oduct ive in as shor t a per iod of t ime.
In shor t , wit h a limit ed backgr ound in ot her basic sciences and a desir e t o cr eat e, you
can st ar t designing digit al cir cuit s in a limit ed per iod of t ime.
1
0
CHAPTER
INTRODUCTION TO DIGITAL ELECTRONICS
2 S witching Theory
Digit al design is cont r ast ing yet complement ar y t o yet anot her development al science we
call ANALOG DESIGN, which over t he year s has pr oduced syst ems such as r adio, analog
comput er s, st er eo, and all sor t s of ot her conveniences t hat we classify as ANALOG or CON-
TINUOUS syst ems. However, it is int er est ing t o not e t hat it is becoming incr easingly difficult
t o delinat e t he t wo t echnologies because of t he inevit able int egr at ion of t he t wo. For example,
you can now pur chase a DIGITAL STEREO POWER AMPLIFIER, capable of deliver ing some
250 wat t s per channel. Unt il r ecent ly linear amplifier design has been one of t he st r ongest
bast ions of t he analog wor ld, but now we have t his component t hat incor por at es t he advan-
t ages of t wo t echnologies, r esult ing in a super ior pr oduct . This same sor t of mix is wit nessed
each day in all ar eas of measur ement inst r ument design wher e we see digit al volt met er s,
digit al oscilloscopes, swit ching power supplies et c.
The next five sect ions ar e int ended t o familiar ize you wit h some of t he basics of bot h
sciences so t hat you can bet t er appr eciat e t he applicat ions of bot h and how t hey r elat e t o each
ot her. The r est of t he t ext is devot ed t o helping you develop an in-dept h under st anding of
digit al design. The met hodology of t he t ext is st ep by st ep lear ning. We pr oceed using a r at her
poignant st at ement made by Rudyar d Kipling as a guide t o r est of our st udies:
I had six honest ser ving men
Who t aught me all t hey knew.
Their names were WHERE, and WHAT, and WHEN, and WHY, and HOW, and WHO.
Whe re a re Dig ita l C irc uits Use d ?
Digit al elect r onics is a fast gr owing field, as wit nessed by t he widespr ead use of micr o-
comput ers. Microcomput ers are designed around complex ICs called microprocessors. In addit ion
many IC semiconduct or memor ies makes up t he micr ocomput er. Micr ocomput er s wit h micr o-
pr ocessor s, int er face chips and semiconduct or memor ies have st ar t ed t he PC r evolut ion.
Small comput er s t hat used t o cost t ens of t housands of dollar s now cost only hundr eds. Digit al
cir cuit s housed in ICs ar e used in bot h lar ge and small comput er s.
Ot her examples include:
Calculat or
Per ipher al devices
Robot ics
Digit al t imepiece
Digit al capacit ance met er
Fr equency count er s
Funct ion gener at or
Wha t a nd Whe n Dig ita l?
A syst em can be defined mat hemat ically as a unique t r ansfor mat ion or oper at or t hat
maps or t r ansfor ms a given input condit ion int o a specific out put .
We classify syst ems in one of t he t wo ways:
(i) Analog or cont inuous
(ii) Digit al or discr et e
An analog syst em oper at es wit h an analog or cont inuous signal and a digit al syst em
oper at es wit h a digit al or discr et e signal. A signal can be defined as useful infor mat ion
t r ansmit t ed wit hin, t o or fr om elect r onic cir cuit s.
Introduction to Digital Electronics 3
Ana log or C ontinuous Sig na l
The cir cuit of Fig. 1 put s out an analog signal or volt age.
+

V
( ) Analog output from
a potentiometer
a
6
5
4
3
2
1
V
O
L
T
S
TIME
Wiper
moving
up
Wiper
moving
down
( ) Analog signal
waveform
b
A
B
O
Fig. 1
As t he wiper on t he pot ent iomet er is moved upwar d, t he volt age, from point s A t o B
gr adually incr eases. When t he wiper is moved downwar d, t he volt age gr adually decr eases
fr om 5 t o 0 volt s (V). The wavefor m diagr am in (b) is a gr aph of t he analog out put . On t he
left side t he volt age fr om A t o B is gr adually incr easing fr om 0 t o 5 V; on t he r ight side t he
volt age is gr adually decr easing fr om 5 t o 0 V. By st opping t he pot ent iomet er wiper at any mid-
point we can get an out put volt age any wher e bet ween 0 t o 5 V.
As analog syst em, t hen, is one t hat has a signal which var ies cont inuously in st ep wit h
t he input .
Cont inuous is defined in many sophist icat ed ways for a wide var iet y of r easons and
pur poses. However, for t he pur pose her e, ‘cont inuous signals or event s or pr ocesses which
change fr om one condit ion t o yet anot her condit ion in such a manner t hat no det ect or can
per cieve any disjoint or quant ized behaviour br ought about by t his change.’ For example t he
t emper at ur e of t he air ar ound us changes fr om t ime t o t ime, and at t imes it changes quit e
r apidly, but never does it change so r apidly t hat some specialized elect r onic t her momet er
cannot t r ack it s change.
Dig ita l or Disc re te Sig na l
Fig. 2(a) pict ur es a squar e wave gener at or. The gener at or pr oduces a squar e wavefor m
t hat is displayed on oscilloscope. The digit al signal is only at +5 V or at 0 V as diagr ammed
in 2(b). The volt age at point A moves from 0 t o +5 V. The volt age t hen st ays at +5 V for a
t ime. At point B t he volt age dr ops immediat ely fr om +5 V to 0 V. The volt age t hen st ays at
0 V for a t ime. Only t wo volt ages ar e pr esent in a digit al elect r onic cir cuit . In t he wavefor m
diagr am in Fig. 2(b). These volt ages ar e labled HIGH and LOW. The HIGH volt age is +5 V
and t he LOW volt age is 0V. Lat t er we shall call t he HIGH volt age (+5 V) a logical 1 and t he
LOW volt age (0 V) a logical 0.
Square
wave
generator
+5
0
B
LOW
HIGH
V
O
L
T
S
( ) Digital signal displayed on scope a ( ) Digital signal waveform b
A TIME
Fig. 2
4 S witching Theory
Syst ems, t hat handle only HIGH and LOW signals ar e called digit al syst ems.
Discr et e signals or pr ocesses ar e defined as t hose pr ocesses t hat change fr om one con-
dit ion t o yet anot her condit ion in a per cieved disjoint or quant ized manner. Two explanat ions
could be t hat :
(i) t her e exist s no det ect or t hat can t r ace t he quant um t r ansit ions in a cont inuous
fashion or, may be,
(ii) it is best descr ibed t o be discont inuous for specific r easons.
What is implied her e is t hat t her e ar e pr ocesses t hat ar e cont inuous in ever y sense of
t he wor d; however t heir changes ar e dominat ed by r apid t r ansit ions fr om one condit ion t o t he
next . Thus, it makes mor e sense t o define it as a discr et e pr ocess. For example, consider t he
signal wavefor ms shown in Fig. 3. In Fig. 3(a) we have a sinusoidal wavefor m t hat is defined
by t he cont inuous mat hemat ical expr ession.
V(t) = A sin 2π ft .
( ) Sinusoidal waveform a ( ) An ideal square waveform b
Time
+A
–A
Rise
time
Fall
time
Fig. 3
While in Fig. 3(b) we have an ideal discr et e signal, called a squar e wave signal, t hat is
defined by an infinit e ser ies of sinusoidal expr essions called a Four ier ser ies. This ideal
squar e wave is char act er ized by it s squar e cor ner s and infinit ely shor t r ise and fall t imes, and
t hus is classified dist inct ly as discr et e.
It s changes fr om one condit ion (HIGH volt age level) t o t he ot her (LOW volt age level) ar e
dominat ed by a ser ies of r apid t r ansit ions.
Thus, it is supposed t hat some r easonable cr it er ia could be developed for classifying
pr ocesses and signals as cont inuous or discr et e by det er mining t he t ime it t akes t o move fr om
one condit ion in r elat ion t o t he t ime spent in t he new condit ion befor e t he next condit ion
must be moved t o.
0.2 CLASSIFICATION OF SIGNALS
Ther e ar e sever al classes of signals. Her e we ar e consider ing only t he following classes,
which ar e suit able for t he scope of t his book:
1. Cont inuous t ime and discr et e t ime signals.
2. Analog and digit al signals.
1. C ontinuous Time a nd Disc re te Time Sig na ls
A signal t hat is specified for ever y value of t ime t is a cont inuous t ime signal (Fig. 4(a)
and (b) and a signal t hat is specified only at discr et e values of t (Fig. 4(d) is a discr et e t ime
signal. Telephone and video camer a out put s ar e cont inuous t ime signals, wher eas t he mont hly
sales of a cor por at ion, and st ock mar ket daily aver ages ar e discr et e t ime signals.
Introduction to Digital Electronics 5
2. Ana log a nd Dig ita l Sig na ls
The concept of cont inuous t ime is oft en confused wit h t hat of analog. The t wo ar e not
t he same. The same is t r ue of t he concept s of discr et e and digit al. A signal whose amplit ude
can t ake on any value in cont inuous r ange is an analog signal. This means t hat an analog
signal amplit ude can t ake on an infinit e number of values. A digit al signal, on t he ot her hand,
is one whose amplit ude can t ake on only a finit e number of values. Signals associat ed wit h
a digit al comput er ar e digit al because t hey t ake on only t wo values (binar y signals). For a
signal t o qualify as digit al, t he no. of values need not be r est r ict ed t o t wo. It can be any finit e
number. A digit al signal whose amplit udes can t ake on M values is an M-ar y signal of which
binar y (M = 2) is a special case.
The t er m cont inuous t ime and discr et e t ime qualify t he nat ur e of a signal along t he t ime
(hor izont al) axis. The t er ms analog and digit al on t he ot her hand qualify t he nat ur e of t he
signal amplit ude (ver t ical axis). Figur es 4(a, b, c, d) shows examples of var ious t ype of signals.
It is clear t hat analog is not necessar y cont inuous t ime and digit al need not be discr et e t ime.
Fig. 4(c) shows an example of an analog but discr et e t ime signal.
( ) a
t →
g(t)
( ) b
t →
g(t)
( ) c
t →
g(t)
( ) d
t →
g(t)
Fi g. 4. Examples of signals
(a) analog, cont inuous t ime
(b) digit al, cont inuous t ime
(c) analog, discr et e t ime
(d) digit al, discr et e t ime.
6 S witching Theory
Why Use Dig ita l C irc uits ?
Ther e ar e sever al advant ages t hat digit al (t wo-valued discr et e) syst ems have over t he
analog (cont inuous) syst ems. Some commonly named ar e:
1. Inexpensive ICs can be used wit h few ext er nal component s.
2. Infor mat ion can be st or ed for shor t per iods or indefinit ely.
3. Syst ems can be pr ogr ammed and show some manner of “int elligence”.
4. Alphanumer ic infor mat ion can be viewed using a var iet y of elect r onic displays.
5. Digit al cir cuit s ar e less affect ed by unwant ed elect r ical int er fer ence called ‘noise’.
Bot h digit al and analog appr oaches have pit falls. However, t he pit falls of digit al ar e at
t imes easier t o ident ify and r esolve t han t he associat ed pit falls in t he analog wor ld. This
advant age as well as t hose ment ioned above, answer much of t he quest ion, “why digit al?”
How Dig ita l
The r est of t he t ext is devot ed t o t he fift h of t he Kipling’s honest men–How digit al.
However at t his int r oduct or y st age, we ar e giving some idea t hat how do you gener at e a
digit al signal.
Digit al signals ar e composed of t wo well defined volt age levels. Most of t he volt age level
used in t his class will be about +3 V to +5 V for HIGH and near 0 V (GND) for LOW.
A digit al signal could be made manually by using a mechanical swit ch. Consider t he
simple cir cuit shown in Fig. 5.
+5V
0V (GND)
5V
+

t
1
t
2
t
3
t
4
Fig. 5
As t he swit ch is moved up and down, it pr oduces t he digit al wavefor m shown at r ight .
At t ime period t
1
, t he volt age is 0V, or LOW. At t
2
t he volt age is +5V, or HIGH. At t
3
, t he
volt age is again 0 V, or LOW, and at t
4
, it is again +5 V, or HIGH. The act ion of t he swit ch
causing t he LOW, HIGH, LOW, HIGH wavefor m is called t oggling. By definit ion, t o t oggle
means t o swit ch over t o an opposit e st at e. As an example, in figur e, if t he swit ch moves fr om
LOW t o HIGH we say t he out put has t oggled. Again if t he swit ch moves fr om HIGH t o LOW
we say t he out put has again t oggled.
Dig ita l a nd the Re a l World
The use of digit al pr act ices can be a viable met hod for solving design pr oblems in t he
r eal wor ld. The r eason t hat design pr oblems ar e emphasized st ems fr om t he fact t hat t he
major ar eas of involvement for elect r ical and digit al engineer s ar e:
1. Measur ement
2. Cont r ol and,
3. Tr ansmission of infor mat ion and ener gy.
Thus, if we look at t he “what we do”, we find t hat we ar e cont inually t r ying t o find
solut ions t o pr oblems r elat ed t o t he measur ement , cont r ol, and t r ansmission of infor mat ion
Introduction to Digital Electronics 7
or ener gy in t he domain of t he r eal wor ld. However, t he r eal wor ld t ends t o have a cont inuous
nat ur e. Because of t his, t he discr et e domain needs t o be buffer ed in some way.
As a r esult of t his buffer ing r equir ement , we should view t he digit al domain in t he
per spect ive shown in Fig. 6.
Interdomain
The Domain of
the Digital System
Conversion
The Domain of
the “real world”
(for the most
part analog)
Fig. 6
However, figur e does not complet ely descr ibe t he r elat ion bet ween t he t wo domains
because t her e ar e sever al impor t ant pr ocesses in t he r eal wor ld t hat ar e at least modelled
as discr et e pr ocesses. For example t he elect r ical signals gover ning t he human ner vous sys-
t em which is, most definit ely discr et e phenomena. But for t he most par t , figur e does depict
t he t ypical r elat ion bet ween t he out side wor ld and t he digit al domain.
The int er domain conver t er depict ed in figur e is a specialized syst em t hat conver t s or
t r anslat es infor mat ion of one domain int o infor mat ion of anot her domain. For example, you
will ser ve as a special int er domain conver t er shor t ly when you ar e asked t o conver t a decimal
number int o it s binar y equivalent . This oper at ion we define as an ANALOG-TO-DIGITAL
CONVERSION.
The pur e digit al syst ems ar e made up of ar r ays of simple and r eliable swit ches wit h only
t wo posit ions, t hat ar e eit her open or closed. (These swit ches can exist as eit her mechanical,
elect r omechanical, or elect r onic devices.)
A numer ical syst em t hat alr eady exist ed was adopt ed t o ser ve as t he “t ool” needed for
ut ilizing t he basic concept . This numer ical mat h syst em, called t he binar y syst em, is based
on t he t wo symbols “0” and “1” in cont r ast t o t he decimal syst em which has t en symbols:
0, 1, 2, . . . . , 9.
We should now see t hat in or der t o use a digit al syst em, such as a digit al comput er for
mat hemat ical comput at ions, we must fir st conver t our mat hemat ical symbolisms (decimal in
t his case) int o binar y symbolisms t o allow t he comput er t o per for m t he mat hemat ical oper a-
t ion. Once t his is done, t he inver se pr ocess must be per for med t o conver t t he binar y r esult
int o a r eadable decimal r epr esent at ion.
The obvious quest ion: “Is digit al wor t h all of t he conver sion? The answer can not be
simply st at ed in Yes/No t er ms, but must be left t o t he individual and t he par t icular sit uat ion.
In cer t ain inst ances, it may not infact be wor t h t he bot her. Such would be t he case if we wer e
able t o cr eat e and use mult iple valued logic syst ems t o cr eat e a “t ot ally decimal machine”.
Obviously if t her e wer e t en unique discr ipt or s usable for our “decimal comput er ”, t her e would
be no need t o conver t any infor mat ion int o t he now r equir ed t wo valued binar y syst em.
However, pr act ically speaking, binar y syst ems pr esent ly dominat e and will cont inue t o be t he
dominant syst em for some year s t o come.
8 S witching Theory
Since, such is t he case, and man must lear n how t o communicat e wit h his machine, it
is necessar y t hat we st udy t he pr ocesses involved in number conver sion and t he differ ent
codes used t o r epr esent and convey infor mat ion.
Bina ry Lo g ic
Binar y logic deals wit h var iables t hat t ake on t wo discr et e values and wit h oper at ions
t hat assume logical meaning. The t wo values t he var iables t ake may be called by differ ent
names (e.g., t r ue and false, high and low, asser t ed and not asser t ed, yes and no et c.), but for
our pur pose it is convenient t o t hink in t er ms of numer ical values and using t he values of
1 and 0. The var iables ar e designat ed by let t er s of t he alphabet such as A, B, C, x, y, z, et c.,
wit h each var iable having t wo and only t wo dist inct possible values: 1 and 0. Ther e ar e t hr ee
basic logical oper at ions: AND, OR and NOT.
1. AND: This oper at ion is r epr esent ed by a dot or by t he absence of an oper at or. For
example x.y = z or xy = z is read “x AND y is equal t o z”. The logical
operation AND mean that z = 1 if and only if x = 1 if and y = 1; ot herwise
z = 0.
2. OR: This oper at ion is r epr esent ed by a plus sign. For example x + y = z is r ead
“x OR y is equal t o z” meaning t hat z = 1, x = 1. or if y = 1 or if bot h
x = 1 and y = 1. If bot h x = 0, and y = 0, t hen z = 0.
3. NOT: This oper at ion is r epr esent ed by a pr ime (somet imes by a bar ). For example
x' = z (or x z = ) is r ead “x not is equal t o z” meaning t hat z is what x is not .
In ot her words, if x = 1, t hen z = 0; but if x = 0, t hen z = 1.
Binar y logic should not confused wit h binar y ar it hmet ic. (Binar y ar it hmat ic will be
discussed in Chapt er 2). One should r ealize t hat an ar it hmet ic var iable designat es a number
t hat may consist of many digit s. A logic var iable is always eit her a 1 or 0. For example, in
binar y ar it hmet ic we have 1 + 1 = 10 (r ead: “one plus one is equal t o 2”), while in binar y logic,
we have 1 + 1 = 1 (r ead: “one OR one is equal t o one”).
For each combinat ion of t he values of x and y, t here is a value of z specified by t he
definit ion of t he logical oper at ion. These definit ions may be list ed in a compact fr om using
‘t r ut h t ables’. A t r ut h t able is a t able of all possible combinat ions of t he var iables showing t he
r elat ion bet ween t he values t hat t he var iables may t ake and t he r esult of t he oper at ion. For
example, t he t r ut h t ables for t he oper at ions AND and OR wit h, var iables x and y ar e obt ained
by list ing all possible values t hat t he var iables may have when combined in pair s. The r esult
of t he oper at ion for each combinat ion is t hen list ed in a separ at e r ow.
Lo g ic G a te s
Logic cir cuit s t hat per for m t he logical oper at ions of AND, OR and NOT ar e shown wit h
t heir symbols in Fig. 7. These cir cuit s, called gat es, ar e blocks of har dwar e t hat pr oduce a
logic 1 or logic 0. Out put signal if input logic r equir ement s ar e sat isfied. Not t hat four
differ ent names have been used for t he same t ype of cir cuit s. Digit al cir cuit s, swit ching
cir cuit s, logic cir cuit s, and gat es. We shall r efer t o t he cir cuit s as AND, OR and NOT gat es.
The NOT gat e is somet imes called an inver t er cir cuit since it inver t s a binar y signal.
x
y
z = x.y x
y
z = x + y
Two Input ( ) AND gate ( ) OR gate a b
x x′
( ) NOT gate or inverter c
Fig. 7
Introduction to Digital Electronics 9
The input signals x and y in t he t wo-input gat es of Fig. 8 may exist is one of four possible
st at es: 00, 01, 10, or 11. These input signals ar e shown in Fig. 8 t oget her wit h t he out put
signals for t he AND and OR gat es. The t iming diagr ams of Fig. 8 illust r at e t he r esponse of
each cir cuit t o each of t he four possible input binar y combinat ions.
0 1 1 0 0
0 0 1 1 0
0 0 1 0 0
0 1 1 1 0
1 0 0 1 1
x
y
AND : x.y
OR : x + y
NOT : x′
Fig. 8
The mat hemat ic syst em of binar y logic is known as Boolean, or swit ching algebr a. This
algebr a is used t o descr ibe t he oper at ion of net wor ks of digit al cir cuit s. Boolean algebr a is
used t o t r ansfor m cir cuit diagr ams t o algebr aic expr essions and vice ver sa. Chapt er 3 is
devot ed t o t he st udy a Boolean algebr a wher e we will see t hat t hese funct ion (AND, OR, NOT)
Make up a sufficient set t o define a t wo valued Boolean algebr a.
The t rut h t ables for AND, OR and NOT are list ed in following Table.
AND OR NOT
x y x.y x y x + y x x'
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1
These t ables clear ly demonst r at e t he definit ions of t he oper at ions.
Switc hing C irc uits a nd Bina ry Sig na ls
The use of binar y var iables and t he applicat ion of binar y logic ar e demonst r at ed by t he
simple swit ching cir cuit s of Fig. 9(a) and (b).
A B
( ) Switches in series
logic AND
a
B
( ) Switches in Parallel
logic OR
b
L
A
L
Voltage
source
Fig. 9
Let t he manual swit ches A and B r epr esent t wo binar y var iables wit h values equal t o 0
when t he swit ch is open and 1 when swit ch is closed. Similar ly, let t he lamp L r epr esent a
10 S witching Theory
t hir d binar y var iable equal t o 1 when t he light is on and 0 when off. For t he swit ches in
ser ies, t he light t ur ns on if A and B ar e closed. For t he swit ches in par allel, t his light t ur ns
on if A or B is closed.
Thus L = A.B for t he cir cuit of Fig. 9(a)
L = A + B for t he cir cuit of Fig. 9(b)
Elect r onic digit al cir cuit s ar e somet imes called swit ching cir cuit s because t hey behave
like a swit ch, wit h t he act ive element such as a t r ansist or eit her conduct ing (swit ch closed)
or not conduct ing (swit ch open). Inst ead of changing t he swit ch manually, an elect r onic
swit ching cir cuit uses binar y signals t o cont r ol t he conduct ion or non-conduct ion st at e of t he
act ive element .
0.3 INTEGRATED CIRCUITS
An int egr at ed cir cuit (IC) is a small silicon semiconduct or cr yst al, called a chip, cont ain-
ing elect r ical component s such as t r ansist or s, diodes, r esist or s and capacit or s. The var ious
component s ar e int er connect ed inside t he chip t o for m an elect r onic cir cuit . The chip is
mount ed on a met al or plast ic package, and connect ions ar e welded t o ext er nal pins t o for m
t he IC.
The individual component s in t he IC cannot be separ at ed or disconnect ed and t he cir cuit
inside t he package is accessible only t hr ough t he ext er nal pins.
Besides a subst ant ial r educt ion in size, ICs offer sever al ot her advant ages and benefit s
compar ed t o elect r onic cir cuit s wit h discr et e component s. These ar e:
1. The cost of ICs is ver y low, which makes t hem economical t o use.
2. Their r educed power consumpt ion makes t he digit al syst em mor e economical t o
oper at e.
3. They have a high r eliabilit y against failur e, so t he digit al syst em needs less r epair s.
4. The oper at ing speed is higher, which makes t hem suit able for high-speed oper at ions.
Small scale int egr at ion (SSI) r efer s t o ICs wit h fewer t han t o gat es on t he same chip.
Medium scale int egr at ion (MSI) includes 12 t o 100 gat es per chip. Lar ge scale int egr at ion
(LSI) r efer s t o mor e t han 100 upt o 5000 gat es per chip. Ver y lar ge scale int egr at ion (VLSI)
devices cont ain sever al t housand gat es per chip.
Int egr at ed chips cir cuit s ar e classified int o t wo gener al cat egor ies: (i) Linear and (ii) Digit al.
0.4 CLASSIFICATION OF DIGITAL CIRCUITS
Digit al cir cuit s can be br oadly classified int o t wo gener al cat egor ies:
1. Combinat ion logic cir cuit s
2. Sequent ial logic cir cuit s.
1. C omb ina tion Log ic C irc uits
A combinat ional cir cuit consist s of logic gat es whose out put s at any t ime ar e det er mined
dir ect ly fr om t he pr esent combinat ion of input s wit hout r egar d t o pr evious input s. A combi-
nat ional cir cuit consist of input var iables, logic gat es and out put var iables. A block diagr am
of combinat ional logic cir cuit is shown in Fig. 10.
Introduction to Digital Electronics 11
Combinational
circuit
Input
variables
Output
variables
Consisting
of a network of
logic gates
Fig. 10
2. Se q ue ntia l Log ic C irc uits
Many syst ems encount er ed inpr act ice also include memor y element s which r equir e t hat
t he syst em be descr ibed in t er ms of sequent ial logic. A block diagr am of sequent ial logic
cir cuit is shown in Fig. 11.
Combinational
logic circuit
Memory
elements
Inputs
Outputs
Fig. 11
It consist s of a combinat ional cir cuit t o which memor y element s ar e connect ed t o for m
a feedback pat h. The memor y element s ar e devices capable of st or ing binar y infor mat ion
wit hin t hem. Thus t he ext er nal out put s in a sequent ial cir cuit ar e a funct ion of not only
ext er nals input s but also of t he pr esent st at s of memor y element s. This is why, t her e cir cuit s
ar e also known as Hist or y sensit ive cir cuit s.
Ther e ar e t wo t ypes of sequent ial cir cuit s depending upon t he t iming of t heir input
signals of t he memor y element s used.
(i) Synchronous sequenti al ci rcui t. If t he t r ansit ion of sequent ial cir cuit fr om one
st at e t o anot her ar e cont r olled by a clock (i.e., depending upon t ime), t he cir cuit is
known as synchr onous. The memor y element s ar e clocked flip flops.
(ii) Asynchronous sequenti al ci rcui t. When t he cir cuit is not cont r olled by clock,
(i.e., independent of t ime) t he t r ansit ion fr om one st at e t o anot her occur whenever
t her e is a change in t he input of cir cuit . The memor y element s ar e eit her unclocked
FFs (lat ches) or t ime delay element s.
12 S witching Theory
1.0 INTRO DUC TIO N
This chapt er discusses sever al impor t ant concept s including t he binar y, oct al and hexadeci-
mal number ing syst ems, binar y dat a or ganizat ion (bit s, nibbles, byt es, wor ds, and double
wor ds), signed and unsigned number ing syst ems. If one is alr eady familiar wit h t hese t er ms
he should at least skim t his mat er ial.
1.1 NUM BERING SYSTEM S
Inside t oday’s comput er s, dat a is r epr esent ed as 1’s and 0’s. These 1’s and 0’s might be
st or ed magnet ically on a disk, or as a st at e in a t r ansist or, cor e, or vacuum t ube. To per for m
useful oper at ions on t hese 1’s and 0’s one have t o or ganize t hem t oget her int o pat t er ns t hat
make up codes. Moder n digit al syst ems do not r epr esent numer ic values using t he decimal
syst em. Inst ead, t hey t ypically use a binar y or t wo’s complement number ing syst em. To
under st and t he digit al syst em ar it hmet ic, one must under st and how digit al syst ems r epr esent
number s.
1.1.1 A Re vie w of the De c ima l Syste m
People have been using t he decimal (base 10) number ing syst em for so long t hat t hey
pr obably t ake it for gr ant ed. When one see a number like “123”, he don’t t hink about t he
value 123; r at her, he gener at e a ment al image of how many it ems t his value r epr esent s. In
r ealit y, however, t he number 123 r epr esent s:
1*10
2
+ 2*10
1
+ 3*10
0
OR 100 + 20 + 3
Each digit appear ing t o t he left of t he decimal point r epr esent s a value bet ween zer o and
nine t imes an incr easing power of t en. Digit s appear ing t o t he r ight of t he decimal point
r epr esent a value bet ween zer o and nine t imes an incr easing negat ive power of t en. For
example, t he value 123.456 means:
1*10
2
+ 2*10
1
+ 3*10
0
+ 4*10
–1
+ 5*10
–2
+ 6*10
–3
OR 100 + 20 + 3 + 0.4 + 0.05 + 0.006
Note: Hexadecimal is oft en abbr eviat ed as hex even t hough, t echnically speaking, hex means base
six, not base sixt een.
1.1.2 Bina ry Numb e ring Syste m
Most moder n digit al syst ems oper at e using binar y logic. The digit al syst ems r epr esent s
values using t wo volt age levels (usually 0 v and +5 v). Wit h t wo such levels one can r epr esent
12
1
CHAPTER
NUMBERING SYSTEMS
Numbering S ystems 13
exact ly t wo differ ent values. These could be any t wo differ ent values, but by convent ion we
use t he values zer o and one. These t wo values, coincident ally, cor r espond t o t he t wo digit s
used by t he binar y number ing syst em.
The binar y number ing syst em wor ks just like t he decimal number ing syst em, wit h t wo
except ions: binar y only allows t he digit s 0 and 1 (r at her t han 0–9), and binar y uses power s
of t wo r at her t han power s of t en. Ther efor e, it is ver y easy t o conver t a binar y number t o
decimal. For each “1” in t he binar y st r ing, add 2
n
wher e “n” is t he bit posit ion in t he binar y
st ring (0 t o n–1 for n bit binar y st r ing).
For example, t he binar y value 1010
2
r epr esent s t he decimal 10 which can be obt ained
t hr ough t he pr ocedur e shown in t he below t able:
Binar y No. 1 0 1 0
Bit Posit ion (n) 3rd 2nd 1st 0th
Weight Fact or (2
n
) 2
3
2
2
2
1
2
0
bit * 2
n
1*2
3
0*2
2
1*2
1
0*2
0
Decimal Value 8 0 2 0
Decimal Number 8 + 0 + 2 + 0 = 10
All t he st eps in above pr ocedur e can be summar ized in shor t as
1*2
3
+ 0*2
2
+ 1*2
1
+ 0*2
0
= 8 + 0 + 2 + 0 = 10
10
The inver se pr oblem would be t o find out t he binar y equivalent of given decimal number
for inst ance let us find out binar y of 19
10
(decimal 19)

Division Dividend Remainder
19 / 2 9
1

9 / 2 4
1

4 / 2 2
0
2 / 2 1 0
1 / 2 0
1

1 0 0 1 1

Dividend is 0, st op t he pr ocedur e.
Our final number is 10011.
To conver t decimal t o binar y is slight ly mor e difficult . One must find t hose power s
of t wo which, when added t oget her, pr oduce t he decimal r esult . The easiest met hod is t o
wor k fr om t he a lar ge power of t wo down t o 2
0
. For example consider t he decimal value
1359:
14 S witching Theory
• 2
10
= 1024, 2
11
= 2048. So 1024 is t he lar gest power of t wo less t han 1359. Subt r act
1024 fr om 1359 and begin t he binar y value on t he left wit h a “1” digit . Binar y = “1”,
Decimal r esult is 1359 – 1024 = 335.
• The next lower power of t wo (2
9
= 512) is gr eat er t han t he r esult fr om above, so
add a “0” t o t he end of t he binar y st r ing. Binar y = “10”, Decimal r esult is st ill 335.
• The next lower power of t wo is 256 (2
8
). Subt r act t his fr om 335 and add a “1” digit
t o t he end of t he binar y number. Binary = “101”, Decimal r esult is 79.
• 128 (2
7
) is gr eat er t han 79, so t ake a “0” t o t he end of t he binar y st r ing. Binar y =
“1010”, Decimal r esult r emains 79.
• The next lower power of t wo (2
6
= 64) is less t han 79, so subt r act 64 and append
a “1” t o t he end of t he binar y st r ing. Binar y = “10101”, Decimal r esult is 15.
• 15 is less t han t he next power of t wo (2
5
= 32) so simply add a “0” t o t he end of
t he binar y st r ing. Binar y = “101010”, Decimal r esult is st ill 15.
• 16 (2
4
) is gr eat er t han t he r emainder so far, so append a “0” t o t he end of t he binar y
st r ing. Binar y = “1010100”, Decimal r esult is 15.
• 2
3
(eight ) is less t han 15, so st ick anot her “1” digit on t he end of t he binar y st r ing.
Binar y = “10101001”, Decimal r esult is 7.
• 2
2
is less t han seven, so subt r act four fr om seven and append anot her one t o t he
binar y st r ing. Binary = “101010011”, decimal r esult is 3.
• 2
1
is less t han t hr ee, so append a one t o t he end of t he binar y st r ing and subt r act
t wo fr om t he decimal value. Binary = “1010100111”, Decimal r esult is now 1.
• Finally, t he decimal r esult is one, which is 2
0
, so add a final “1” t o t he end of t he
binar y st r ing. The final binar y r esult is “10101001111”.
1.1.3 Bina ry Forma ts
In t he pur est sense, ever y binar y number cont ains an infinit e number of digit s (or bits
which is shor t for binar y digit s). Because any number of leading zer o bit s may pr ecede t he
binar y number wit hout changing it s value. For example, one can r epr esent t he number
seven by:
111 00000111 ..0000000000111 000000000000111
Note: This book adopt t he convent ion ignor ing any leading zer os. For example, 101
2
r epr esent s
t he number five. Since t he 80 × 86 wor ks wit h gr oups of eight bit s, one will find it much easier t o zer o
ext end all binar y number s t o some mult iple of four or eight bit s. Ther efor e, following t his convent ion,
number five is r epr esent ed as 0101
2
or 00000101
2
.
Oft en sever al values ar e packed t oget her int o t he same binar y number. For convenience,
a numer ic value is assign t o each bit posit ion. Each bit is number ed as follows:
1. The r ight most bit in a binar y number is bit posit ion zer o.
2. Each bit t o t he left is given t he next successive bit number.
An eight -bit binar y value uses bit s zer o t hr ough seven:
X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
Numbering S ystems 15
A 16-bit binar y value uses bit posit ions zer o t hr ough fift een:
X
15
X
14
X
13
X
12
X
11
X
10
X
9
X
8
X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
Bit zer o is usually r efer r ed t o as t he low order bit . The left -most bit is t ypically called
the high order bit . The int er mediat e bit s ar e r efer r ed by t heir r espect ive bit number s. The
low or der bit which is X
0
is called LEAST SIGNIFICANT BIT (LSB). The high or der bit or
left most bit . i.e., X
15
is called MOST SIGNIFICANT BIT (MSB).
1.2 DATA ORGANIZATION
In pure mat hemat ics a value may t ake an arbit rary number of bit s. Digit al syst ems, on t he
ot her hand, generally work wit h some specific number of bit s. Common collect ions are single bit s,
groups of four bits (called nibbles), groups of eight bits (called bytes), groups of 16 bit s (called
words), and more. The sizes are not arbit rary. There is a good reason for t hese part icular values.
1.2.1 Bits
The smallest “unit ” of dat a on a binar y comput er or digit al syst em is a single bit. Bi t,
an abbreviat ion for Binar y Digit , can hold eit her a 0 or a 1. A bit is t he smallest unit of
infor mat ion a comput er can under st and. Since a single bit is capable of r epr esent ing only t wo
differ ent values (t ypically zer o or one) one may get t he impr ession t hat t her e ar e a ver y small
number of it ems one can r epr esent wit h a single bit . That ’s not t r ue! Ther e ar e an infinit e
number of it ems one can r epr esent wit h a single bit .
Wit h a single bit , one can r epr esent any t wo dist inct it ems. Examples include zer o or
one, t r ue or false, on or off, male or female, and r ight or wr ong. However, one are not limit ed
t o r epr esent ing binar y dat a t ypes (t hat is, t hose object s which have only t wo dist inct values).
One could use a single bit t o r epr esent t he number s 321 and 1234. Or per haps 6251 and 2.
One could also use a single bit t o r epr esent t he color s gr een and blue. One could even
r epr esent t wo unr elat ed object s wit h a single bit . For example, one could r epr esent t he color
r ed and t he number 3256 wit h a single bit . One can r epr esent any t wo differ ent values wit h
a single bit . However, one can represent only t wo differ ent values wit h a single bit .
To confuse t hings even more, different bit s can represent different t hings. For example,
one bit might be used t o represent t he values zero and one, while an adjacent bit might be used
t o represent t he values t rue and false. How can one t ell by looking at t he bit s? The answer,
of course, is t hat one can’t . But t his illust rat es t he whole idea behind comput er dat a st ruct ures:
data is what one define it to be. If one uses a bit t o represent a boolean (t rue/false) value t hen
t hat bit (by definit ion) represent s t rue or false. For t he bit t o have any t rue meaning, one must
be consist ent . That is, if one is using a bit t o represent t rue or false at one point in his program,
he shouldn’t use t he t rue/false value st ored in t hat bit t o represent green or blue lat er.
Since most it ems one will be t r ying t o model r equir e mor e t han t wo differ ent values,
single bit values ar en’t t he most popular dat a t ype used. However, since ever yt hing else
consist s of gr oups of bit s, bit s will play an impor t ant r ole in pr ogr ams. Of cour se, t her e ar e
sever al dat a t ypes t hat r equir e t wo dist inct values, so it would seem t hat bit s ar e impor t ant
by t hemselves. However, individual bit s ar e difficult t o manipulat e, so ot her dat a t ypes ar e
oft en used t o r epr esent boolean values.
1.2.2 Nib b le s
A nibble is a collect ion of four bit s. It wouldn’t be a par t icular ly int er est ing dat a st r uct ur e
except for t wo it ems: BCD (binary coded decimal) number s and hexadecimal number s. It
16 S witching Theory
t akes four bit s t o r epr esent a single BCD or hexadecimal digit . Wit h a nibble, one can
r epr esent up t o 16 dist inct values. In t he case of hexadecimal number s, t he values 0, 1,
2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F ar e r epr esent ed wit h four bit s (see “The
Hexadecimal Number ing Syst em”). BCD uses t en differ ent digit s (0, 1, 2, 3, 4, 5, 6, 7, 8, 9)
and r equir es four bit s. In fact , any sixt een dist inct values can be r epr esent ed wit h a
nibble, but hexadecimal and BCD digit s ar e t he pr imar y it ems we can r epr esent wit h a
single nibble.
1.2.3 Byte s
Comput er memor y must be able t o st or e let t er s, number s, and symbols. A single bit by
it self cannot be of much use. Bit s ar e combined t o r epr esent some meaningful dat a. A gr oup
of eight bit s is called a byt e. It can r epr esent a char act er and is t he smallest addr essable
dat um (dat a it em) on t he most of t he digit al syst ems (e.g. 80 × 86 micr opr ocessor ). The most
impor t ant dat a t ype is t he byt e. Main memor y and input /out put addr esses on t he 80 × 86 ar e
all byt e addr esses. This means t hat t he smallest it em t hat can be individually accessed by an
80 × 86 pr ogr am is an eight -bit value. To access anyt hing smaller r equir es t hat you r ead t he
byt e cont aining t he dat a and mask out t he unwant ed bit s. The bit s in a byt e ar e nor mally
number ed fr om zer o t o seven using t he convent ion in Fig. 1.1.
Bit 0 is t he low order bit or least significant bit, bit 7 is t he high order bit or most
significant bit of t he byt e. All ot her bit s ar e r efer r ed by t heir number.
7 6 5 4 3 2 1 0
Fi g. 1.1 Bit number ing in a byt e
Note: That a byt e also cont ains exact ly t wo nibbles (see Fig. 1.2).
7 6 5 4 3 2 1 0
High Nibble Low Nibble
Fi g. 1.2 The t wo nibbles in a byt e
Bit s 0–3 compr ise t he low order nibble, bit s 4–7 for m t he high order nibble. Since a byt e
cont ains exact ly t wo nibbles, byt e values r equir e t wo hexadecimal digit s.
Since a byt e cont ains eight bit s, it can r epr esent 2
8
, or 256, differ ent values. Gener ally,
a byt e is used t o r epr esent numer ic values in t he r ange 0.255, signed number s in t he r ange
–128.. + 127 (r efer “Signed and Unsigned Number s”). Many dat a t ypes have fewer t han 256
it ems so eight bit s is usually sufficient .
For a byt e addr essable machine, it t ur ns out t o be mor e efficient t o manipulat e a whole
byt e t han an individual bit or nibble. For t his r eason, most pr ogr ammer s use a whole byt e
t o r epr esent dat a t ypes t hat r equir e no mor e t han 256 it ems, even if fewer t han eight bit s
would suffice. For example, we’ll oft en r epr esent t he boolean values t r ue and false by 00000001
2
and 00000000
2
(r espect ively).
Numbering S ystems 17
Pr obably t he most impor t ant use for a byt e is holding a char act er code. Char act er s t yped
at t he keyboar d, displayed on t he scr een, and pr int ed on t he pr int er all have numer ic values.
1.2.4 Words
A wor d is a gr oup of 16 bit s. Bit s in a wor d ar e number ed st ar t ing fr om zer o on up t o
fift een. The bit number ing appear s in Fig. 1.3.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fi g. 1.3 Bit number s in a wor d
Like t he byt e, bit 0 is t he low or der bit and bit 15 is t he high or der bit . When r efer encing
t he ot her bit s in a wor d use t heir bit posit ion number.
Not ice t hat a wor d cont ains exact ly t wo byt es. Bit s 0 t hr ough 7 for m t he low or der byt e,
bit s 8 t hr ough 15 for m t he high or der byt e (see Fig. 1.4).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
High Byt e Low Byt e
Fig. 1.4 The t wo byt es in a wor d
Nat ur ally, a wor d may be fur t her br oken down int o four nibbles as shown in Fig. 1.5.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nibble 3 Nibble 2 Nibble 1 Nibble 0
Higher Nibble Lower Nibble
Fig. 1.5 Nibbles in a wor d
Nibble zer o is t he low or der nibble in t he wor d and nibble t hr ee is t he high or der nibble
of t he wor d. The ot her t wo nibbles ar e “nibble one” or “nibble t wo”.
Wit h 16 bit s, 2
16
(65,536) differ ent values can be r epr esent ed. These could be t he values
in t he r ange 0 t o 65,535 (or –32,768 t o +32,767) or any ot her dat a t ype wit h no mor e t han
65,536 values. The t hr ee major uses for wor ds ar e int eger values, offset s, and segment
values.
Wor ds can r epr esent int eger values in t he r ange 0 t o 65,535 or –32,768 t o 32,767.
Unsigned numer ic values ar e r epr esent ed by t he binar y value cor r esponding t o t he bit s in t he
wor d. Signed numer ic values use t he t wo’s complement for m for numer ic values (r efer
“Signed and Unsigned Number s”). Segment values, which ar e always 16 bit s long, const it ut e
the paragraph address of a code, dat a, ext r a, or st ack segment in memor y.
1.2.5 Double Words
A double wor d is exact ly what it s name implies, a pair of wor ds. Ther efor e, a double wor d
quant it y is 32 bit s long as shown in Fig. 1.6.
18 S witching Theory
31 23 15 7 0
Fi g. 1.6 Bit number s in a double wor d
This double wor d can be divided int o a high or der wor d and a low or der wor d, or four
differ ent byt es, or eight differ ent nibbles (see Fig. 1.7).
Double wor ds can r epr esent all kinds of differ ent t hings. Fir st and for emost on t he list
is a segment ed addr ess. Anot her common it em r epr esent ed wit h a double wor d is a 32-bit
int eger value (which allows unsigned number s in t he r ange 0 t o 4,294,967,295 or signed
number s in t he r ange –2,147,483,648 t o 2,147,483,647). 32-bit float ing point values also fit int o
a double wor d. Most of t he t ime, double wor ds ar e used t o hold segment ed addr esses.
Fi g. 1.7 Nibbles, byt es, and wor ds in a double wor d
1.3 O C TAL NUM BERING SYSTEM
The oct al number syst em uses base 8 inst ead of base 10 or base 2. This is somet imes
convenient since many comput er oper at ions ar e based on byt es (8 bit s). In oct al, we have 8
digit s at our disposal, 0–7.
Decimal Octal
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 10
31 23 15 7 0
31 23 15 7 0
High Wor ld Wor d
31 23 15 7 0
Higher Byt e Byt e 2 Byt e 1 Lower Byt e
Nibble 7 6 5 4 3 2 1 0
Hihger Lower
Numbering S ystems 19
Decimal Octal
9 11
10 12
11 13
12 14
13 15
14 16
15 17
16 20
1.3.1 O c ta l to De c ima l, De c ima l to O c ta l C onve rsion
Conver t ing oct al t o decimal is just like conver t ing binar y t o decimal, except inst ead of
power s of 2, we use power s of 8. That is, t he LSB is 8
0
, t he next is 8
1
, t hen 8
2
, et c.
To conver t 172 in oct al t o decimal:
1 7 2
8
2
8
1
8
0
Weight = 1*8
2
+ 7*8
1
+ 2*8
0
= 1*64 + 7*8 + 2*1
= 122
10
Conver t ing decimal t o oct al is just like conver t ing decimal t o binar y, except inst ead of
dividing by 2, we divide by 8. To conver t 122 t o oct al:
122/8 = 15 r emainder 2
15/8 = 1 r emainder 7
1/8 = 0 r emainder 1
= 172
8
If using a calculat or t o per for m t he divisions, t he r esult will include a decimal fr act ion
inst ead of a r emainder. The r emainder can be obt ained by mult iplying t he decimal fr act ion
by 8. For example, 122/8 = 15.25. Then mult iply 0.25 * 8 t o get a r emainder of 2.
1.3.2 O c ta l to Bina ry, Bina ry to O c ta l C onve rsion
Oct al becomes ver y useful in conver t ing t o binar y, because it is quit e simple. The
conver sion can be done by looking at 3 bit combinat ions, and t hen concat enat ing t hem
t oget her. Her e is t he equivalent for each individual oct al digit and binar y r epr esent at ion:
Octal Binary
1 001
2 010
3 011
4 100
5 101
6 110
7 111
20 S witching Theory
To conver t back and for t h bet ween oct al and binar y, simply subst it ut e t he pr oper pat t er n
for each oct al digit wit h t he cor r esponding t hr ee binar y digit s.
For example, 372 in oct al becomes 010 111 010 or 010111010 in binar y.
777 in oct al becomes 111 111 111 or 111111111 in binar y.
The same applies in t he ot her dir ect ion:
100111010 in binar y becomes 100 111 010 or 472 in oct al.
Since it is so easy t o conver t back and for t h bet ween oct al and binar y, oct al is somet imes
used t o r epr esent binar y codes. Oct al is most useful if t he binar y code happens t o be a
mult iple of 3 bit s long. Somet imes it is quicker t o conver t decimal t o binar y by fir st conver t -
ing decimal t o oct al, and t hen oct al t o binar y.
1.4 HEXADEC IM AL NUM BERING SYSTEM
The hexadecimal number ing syst em is t he most common syst em seen t oday in r epr e-
sent ing r aw comput er dat a. This is because it is ver y convenient t o r epr esent gr oups of 4 bit s.
Consequent ly, one byt e (8 bit s) can be r epr esent ed by t wo gr oups of four bit s easily in
hexadecimal.
Hexadecimal uses a base 16 number ing syst em. This means t hat we have 16 symbols t o
use for digit s. Consequent ly, we must invent new digit s beyond 9. The digit s used in hex ar e
t he let t ers A, B, C, D, E, and F. If we st ar t count ing, we get t he t able below:
Decimal Hexadecimal Binary
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
10 A 1010
11 B 1011
12 C 1100
13 D 1101
14 E 1110
15 F 1111
16 10 10000
17 11 10001
18 …
Numbering S ystems 21
1.4.1 He x to De c ima l a nd De c ima l to He x C onve rsion
Conver t ing hex t o decimal is just like conver t ing binar y t o decimal, except inst ead of
power s of 2, we use power s of 16. That is, t he LSB is 16
0
, t he next is 16
1
, t hen 16
2
, et c.
To conver t 15E in hex t o decimal:
1 5 E
16
2
16
1
16
0
Weight = 1*16
2
+ 5*16
1
+ 14*16
0
= 1*256 + 5*16 + 14*1
= 350
10
Conver t ing decimal t o hex is just like conver t ing decimal t o binar y, except inst ead of
dividing by 2, we divide by 16. To conver t 350 t o hex:
350/16 = 21 r emainder 14 = E
21/16 = 1 r emainder 5
1/16 = 0 r emainder 1
So we get 15E for 350.
Again, not e t hat if a calculat or is being used, you may mult iple t he fr act ion r emainder by
16 t o pr oduce t he r emainder. 350/16 = 21.875. Then t o get t he r emainder, 0.875 * 16 = 14.
1.4.2 He x to Bina ry a nd Bina ry to He x Conve rsion
Going fr om hex t o binar y is similar t o t he pr ocess of conver t ing fr om oct al t o binar y. One
must simply look up or comput e t he binar y pat t er n of 4 bit s for each hex code, and concat enat e
t he codes t oget her.
To convert AE t o binar y:
A = 1010
E = 1110
So AE in binar y is 1010 1110
The same pr ocess applies in r ever se by gr ouping t oget her 4 bit s at a t ime and t hen look
up t he hex digit for each gr oup.
Binar y 11000100101 br oken up int o gr oups of 4:
0110 0010 0101 (not e t he 0 added as padding on t he MSB t o get up t o 4 bit s)
6 2 5
= 625
16
1.4.3 He x to Oc ta l a nd Oc ta l to He x Conve rsion
These conver sions ar e done t hr ough t he binar y conver sion. Recall t hat , a gr oup of 4-bit s
r epr esent a hexadecimal digit and a gr oup of 3-bit s r epr esent an oct al digit .
He x to O c ta l C onve rsion
1. Conver t t he given hexadecimal number int o binar y.
2. St ar t ing fr om r ight make gr oups of 3-bit s and designat e each gr oup an oct al digit .
22 S witching Theory
Example. Convert (1A3)
16
into octal.
Soluti on.
1. Conver t ing hex t o binar y
(1 A 3)
16
=
0001
1
1010
A
0011
3
2. Gr ouping of 3-bit s
(1A3)
16
=
000 110 100
0 6 4
011
3
so (1A3)
16
= (0643)
8
≡ (643)
8
O c ta l to He x C onve rsion
1. Conver t t he given oct al number int o binar y.
2. St ar t ing fr om r ight make gr oups of 4-bit s and designat e each gr oup as a Hexadeci-
mal digit .
Example. Convert (76)
8
into hexadecimal.
Solution. 1. Conver t ing oct al t o binar y
(76)
8
=
111 110
7 6
2. Gr ouping of 4-bit s
(76)
8
=
11 1110 0011
3 E 3
1110
E
so (76)
8
= (3E)
16
1.5 RANG E O F NUM BER REPRESENTATIO N
The r ange of number s t hat can be r epr esent ed is det er mined by t he number of digit s (or
bit s in binar y) used t o r epr esent a number. Let us consider decimal number syst em t o
under st and t he idea.
Highest decimal number r epr esent ed by 2 digit s = 99
But 99 = 100 – 1 = 10
2
– 1. The power of 10 (in 10
2
– 1)
indicat es t hat it is 2 digit r epr esent at ion.
So highest 2-digit decimal number = 10
2
– 1
and lowest 2-digit decimal number = 00
Thus r ange of 2-digit decimal number = 00 t o 10
2
– 1
It is evident t hat a t ot al of 100 or 10
2
number s (00 t o 99) can be r epr esent ed by 2-digit s.
So we conclude t hat for n-digit r epr esent at ion
r ange of decimal number s = 0 t o 10
n
– 1
Numbering S ystems 23
highest decimal number = 10
n
– 1
t ot al number s t hat can be r epr esent ed = 10
n
Not e t hat highest n-digit decimal number can be r epr esent ed by n 9s (i.e., 10 – 1) e.g.,
highest 2 digit decimal number is r epr esent ed by 2 9s which is 99.
The above discussion can be gener alized by t aking base-r number syst em inst ead of base-
10 (or decimal) number syst em. Thus wit h n-digit r epr esent at ion–
Tot al dist inct number s t hat can be r epr esent ed = r
n
Highest decimal Number = r
n – 1
Range of Number s = 0 to r
n – 1
wher e r = base or r adix of Number syst em
n = Number of digit s used for r epr esent at ion
It is wor t h not ing t hat highest decimal number can be r epr esent ed by n (r – 1)s in base-
r syst em.
Let us consider t he base-2 or binar y number syst em. Thus 2
n
dist inct quant it ies, in t he
r ange 0 t o 2
n
– 1, can be r epr esent ed wit h n-bit . If n = 4-bit s, t ot al dist inct quant it ies (i.e.,
number s) t hat can be r epr esent ed
= N = 2
4
= 16
t he r ange of number s = 0 t o 2
4
– 1 = 0 t o 15
and Highest decimal number = 2
4
– 1 = 15
The highest decimal number 15, is r epr esent ed by our 1s i.e., 1111. The r ange 0 t o 15
cor r esponds t o 0000 t o 1111 in binar y.
If we want t o r epr esent a decimal number M using n-bit s, t hen t he number M should
lie in t he r ange 0 t o 2
n
–1 i.e.,
0 < M < 2
n
– 1
or 2
n
– 1 > M
or 2
n
> M + 1
or n > log
2
(M + 1)
where M and n ar e int eger s.
In t he similar way if we want t o r epr esent N dist inct quant it ies in binar y t hen N should
not exceed 2
n
.
2n > N
or n > log
2
N Both n and N ar e int eger
Example. How many bits are required to represent
(i) 16-distinct levels
(ii) 10 distinct levels
(iii) 32 distinct levels
Solution. (i) we have 2
n
> N
or 2
n
> 16 ⇒ 2
n
> 2
4
or n > 4 ⇒ n = 4
24 S witching Theory
Thus, at least 4-bit s ar e r equir ed t o r epr esent 16 dist inct levels, r anging fr om 0 t o 15.
(ii) We have n > log
2
N
or n > log
2
10 ⇒ n > 3.32
but n should be int eger, so t ake next higher int eger value
i.e., n = 4 bit s
So, minimum 4-bit s ar e r equir ed t o r epr esent 10 dist inct levels, r anging fr om 0 t o 9.
(iii) n > log
2
N
or n > log
2
32 ⇒ n > log
2
2
5
or n > 5 ⇒ n = 5
So, minimum 5-bit s ar e r equir ed t o r epr esent 32 levels, r anging fr om 0 t o 31.
Example. Calculate the minimum no. of bits required to represent decimal numbers
(i) 16 (ii) 63
Solution. (i) We have n > log
2
(M + 1) wher e M = given number
so n > log
2
(16 + 1) ⇒ n > log
2
(17)
or n > 4.09
t aking next higher int eger i.e., n = 5 bit s.
Thus, at least 5-bit s ar e r equir ed t o r epr esent decimal number 16.
(ii) n > log
2
(M + 1)
n > log
2
(63 + 1) ⇒ n > log
2
64
or n > log
2
2
6
or n > 6 bit s
So, minimum 6-bit s ar e needed t o r epr esent decimal 63.
Example. In a base-5 number system, 3 digit representation is used. Find out
(i) Number of distinct quantities that can be represented.
(ii) Representation of highest decimal number in base-5.
Solution. Given radix of number syst em r = 5
digit s of represent at ion n = 3
digit s in base-5 would be – 0, 1, 2, 3, 4
(i) we have r elat ion
no of dist inct quant it ies = r
n
= 5
3
= 125
So, 125 dist inct levels (quant it ies) can be r epr esent ed.
(ii) Highest decimal Number can be r epr esent ed by n(r – 1)s i.e., by t hr ee 4s.
So, highest decimal Number = 444
1.6 BINARY ARITHMETIC
The binar y ar it hmet ic oper at ions such as addit ion, subt r act ion, mult iplicat ion and divi-
sion ar e similar t o t he decimal number syst em. Binar y ar it hmet ics ar e simpler t han decimal
because t hey involve only t wo digit s (bit s) 1 and 0.
Numbering S ystems 25
Bina ry Ad d ition
Rules for binar y addit ion ar e summar ized in t he t able shown in Fig. 1.8.
Augend Addend S um Carry Result
0 0 0 0 0
0 1 1 0 1
1 0 1 0 1
1 1 0 1 10
Fig. 1.8 Rules for binar y addit ion
As shown in 4t h r ow adding 1 t o 1 gives 9 car r y which, is given t o next binar y posit ion,
similar t o decimal syst em. This is explained in examples below:
Example. (i) Add 1010 and 0011 (ii) Add 0101 and 1111
Soluti on.
Bina ry Sub tra c tio n
The r ules for binar y subt r act ion is summar ized in t he t able shown in Fig. 1.9.
Minuend S ubtrahend Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Fig. 1.9 Rules for binar y subt r act ion
The pr ocess of subt r act ion is ver y similar t o decimal syst em in which if a bor r ow is
needed it is t aken fr om next higher binar y posit ion, as shown in r ow 2.
Example. S ubtract 0100 from 1011
Soluti on.
1 Bor r ow
Minuend
Subt r a hend
0 1 1 1 Differ ence
C C
3 2
C
1
C
0


− ←

1 0 1 1
0 1 0 0
↑ ↑ ↑ ↑
Ther e is no pr oblem in column C
0
and C
1
. In column C
2
we made 0 –1, so r esult = 1 and
bor r ow = 1. Then t his bor r ow = 1 is mar ked in column C
3
. So r esult in column C
2
is 1. Then
in column C
3
we fir st made 1 – 0 t o get r esult = 1 and t hen we subt r act ed bor r ow fr om r esult ,
t hus we get 0 in column C
3
.
26 S witching Theory
“Thus in subt r act ion, fir st subt r act t he subt r ahend bit fr om minuend and t hen subt r act
bor r ow fr om t he r esult .”
Wat ch out t he next example t o fur t her clar ify t he concept .
Example. S ubtract 0110 from 1001
Soluti on.
1 Bor r ow
Minuend
Subt r a hend
0 0 1 1 Differ ence
C C
3 2
C
1
C
0


− ←

1 0 0 1
0 1 1 0
↑ ↑ ↑ ↑
1
Her e, in column C
1
we get differ ence = 1 and bor r ow = 1. This bor r ow is mar ked in
column C
2
, and differ ence = 1 is shown in t he column C
1
. We now come t o column C
2
. Her e
by 0–1 we get differ ence = 1 and bor r ow = 1. Now t his bor r ow is mar ked in column C
3
. But
in column C
2
alr eady we have 9 bor r ow so t his bor r ow = 1 is subt r act ed fr om differ ence
= 1 which r esult s in 0. Thus t he differ ence = 0 is mar ked in column C
2
.
In t he similar way we pr ocess column C
3
and we get differ ence = 0 in column C
3
.
Bina ry M ultip lic a tio n
Binar y mult iplicat ion is also similar t o decimal mult iplicat ion. In binar y mult iplicat ion if
mult iplier bit is 0 t hen par t ial pr oduct is all 0 and if mult iplier bit is 1 t hen par t ial pr oduct
is 1. The same is illust r at ed in example below:
Example.
Bina ry Divisio n
Binar y division is also similar t o decimal division as illust r at ed in example below:
Example.
1 0 1 1 0 1
1 0 0 1
× × 1 0 0 1
1 0 0 1
× × × ×
1 0 0 1 Divisor Dividend
1 0 1
1.7 NEG ATIVE NUMBERS AND THEIR ARITHM ETIC
So far we have discussed st r aight for war d number r epr esent at ion which ar e not hing but
posit ive number. The negat ive number s have got t wo r epr esent at ion
Numbering S ystems 27
(i) complement r epr esent at ion.
(ii) sign magnit ude r epr esent at ion.
We will discuss bot h t he r epr esent at ion in following subsect ions.
1.7.1 1’s a nd 2’s Comple me nt
These ar e t he complement s used for binar y number s. Their r epr esent at ion ar e ver y
impor t ant as digit al syst ems wor k on binar y number s only.
1’s C omp le me nt
1’s complement of a binary number is obt ained simply by replacing each 1 by 0 and each 0
by 1. Alt ernat ely, 1’s complement of a binary can be obt ained by subt ract ing each bit from 1.
Example. Find 1’s complement of (i) 011001 (ii) 00100111
Solution. (i) Replace each 1 by 0 and each 0 by 1
0 1 1 0 0 1
↓ ↓ ↓ ↓ ↓ ↓
1 0 0 1 1 0
So, 1’s complement of 011001 is 100110.
(ii) Subt r act each binar y bit fr om 1.
1 1 1 1 1 1 1 1
– 0 0 1 0 0 1 1 1
1 1 0 1 1 0 0 0 ← 1’s complement
one can see t hat bot h t he met hod gives same r esult .
2’s C omp le me nt
2’s complement of a binar y number can be obt ained by adding 1 t o it s 1’s complement .
Example. Find 2’s complement of (i) 011001 (ii) 0101100
Solution. (i) 0 1 1 0 0 1 ← Number
1 0 0 1 1 0 ← 1’s complement
+ 1 ← Add 1 t o 1’s complement
1 0 0 1 1 1 ← 2’s complement
(ii) 0 1 0 1 1 0 0 ← Number
1 0 1 0 0 1 1 ← 1’s complement
+ 1 ← Add 1 t o 1’s complement
1 0 1 0 1 0 0 ← 2’s complement
There is an efficient met hod t o find 2’s complement based upon t he observat ion made on t he
above 2 examples. Consider t he number and it s 2’s complement of example (ii) as shown below:
0 1 0 1 1 0 0
1 0 1 0 1 0 0
1’s
complement
Same as
number
Number
2’s Complement
Fig. 1.10 Number and it s 2’s complement
28 S witching Theory
The above figur e clear ly shows t hat t o find 2’s complement of a binar y number st ar t fr om
r ight t owar ds left t ill t he fir st 1 appear s in t he number. Take t hese bit s (including fir st 1) as
it is and t ake 1’s complement of r est of t he bit s. Wor kout below examples t o enhance your
underst anding.
Example. Find 2’s complement of (i) 101100 (ii) 10010 (iii) 01001
Solution. (i) Number = 101100
1 0 1 1 0 0
0 1 0 1 0 0
1’s complement
NUMBER
2’s complement
Fir st 1 fr om r ight
(ii) Number = 10010
1 0 0 1 0
0 1 1 1 0
1’s complement
NUMBER
2’s complement
Fir st 1 fr om r ight
(iii) Number = 01001
0 1 0 0 1
1 0 1 1 1
Take 1’s
complement
NUMBER
2’s complement
Fir st 1 fr om r ight
As it is
It is int er est ing t o not e t hat t aking complement t wice leaves t he number as it is. This
is illust r at ed in below Fig. 1.11.
1001 2’s
complement
0111 2’s
complement
1001
Fig. 1.11 Effect of t aking complement t wice
To r epr esent a negat ive number using complement s t he pr ocess involves t wo st eps.
(1) obt ain t he binar y r epr esent at ion of equivalent posit ive number for given negat ive
number. e.g., if given number is –2 t hen obt ain binar y r epr esent at ion of +2.
(2) Take t he appr opr iat e complement of r epr esent at ion obt ained in st ep 1.
Example. Obtain 1’s and 2’s complement representation of –5 and –7.
Solution. (i) –5
1. binar y of +5 = (0101)
2
2. 1’s complement of (0101)
2
= (1010)
2
← Repr esent s (–5)
10
Numbering S ystems 29
2’s complement of (0101)
2
= (1011)
2
← Repr esent s (–5)
10
(ii) –7
1. binar y of +7 = (0111)
2
2. 1’s complement of (0111)
2
= (1000)
2
Repr esent s (–7)
10
2’s complement of (0111)
2
= (1001)
2
Repr esent s (–7)
10
Not e t hat in above t wo examples, for posit ive number s we obt ained such a binar y
r epr esent at ion in which MSB is 0. e.g., for +7 we obt ained (0111)
2
not just (111)
2
. It is because
for all posit ive number s MSB must be 0 and for negat ive number s MSB should be 1. This will
be mor e clear in subsect ion 1.7.3.
1.7.2 Sub tra c tion Using 1’s a nd 2’s C omp le me nt
Befor e using any complement met hod for subt r act ion equat e t he lengt h of bot h minuend
and subt r ahend by int r oducing leading zer os.
1’s complement subt r act ion following ar e t he r ules for subt r act ion using 1’s complement .
1. Take 1’s complement of subt r ahend.
2. Add 1’s complement of subt r ahend t o minuend.
3. If a car r y is pr oduced by addit ion t hen add t his car r y t o t he LSB of r esult . This is
called as end ar ound car r y (EAC).
4. If car r y is gener at ed fr om MSB in st ep 2 t hen r esult is posit ive. If no car r y
gener at ed r esult is negat ive, and is in 1’s complement for m.
Example. Perform following subtraction using 1’s complement.
(i) 7 – 3 (ii) 3 – 7
Solution. (i) 7 – 3: binar y of 7 = (0111)
2
binar y of 3 = (0011)
2
bot h number s have equal lengt h.
Step 1. 1’s complement of (0011)
2
= (1100)
2
Step 2. Per for m addit ion of minuend and 1’s complement of subt r ahend
Step 3. EAC
0 1 1 1
+ 1 1 0 0
1 0 0 1 1
+ 1
0 1 0 0
Fina l
Car r y
(7)
(–3 or 1’s complement of + 3)
(EAC)
Step 4. Since car r y is gener at ed in st ep 2 t he r esult is posit ive.
since (0100)
2
= (4)
10
so r esult = +4 which is cor r ect answer
(ii) 3 – 7:
binar y of 3 = 0011
binar y of 7 = 0111
30 S witching Theory
Step 1. 1’s complement of 0111 = 1000
Step 2. Per for m addit ion of minuend and 1’s complement of subt r ahend
Step 3. No car r y pr oduced so no EAC oper at ion.
Step 4. Since no car r y pr oduced in st ep 2, r esult is negat ive and is in complement ed
for m. So we must t ake 1’s complement of r esult t o find cor r ect magnit ude of r esult .
1’s complement of r esult (1011)
2
= (0100)
2
so final r esult = –(0100)
2
or –(4)
10
Not e t hat when (in example (ii) t he r esult was negat ive (st ep 2), MSB of t he r esult was
1. When (in example (i)) t he r esult was posit ive t he MSB was 0. The same can be obser ved
in 2’s complement subt r act ion.
2’s complement Subtracti on Met hod of 2’s complement is similar t o 1’s complement
subt r act ion except t he end ar ound car r y (EAC). The r ules ar e list ed below:
1. Take 2’s complement of subt r ahend.
2. Add 2’s complement of subt r ahend t o minuend.
3. If a car r y is pr oduced, t hen discar d t he car r y and t he r esult is posit ive. If no car r y
is pr oduced r esult is negat ive and is in 2’s compliment for m.
Example. Perform following subtraction using 2’s complement.
(i) 7 – 5 (ii) 5 – 7
Solution. (i) 7 – 5: binar y of 7 = (0111)
2
binar y of 5 = (0101)
2
Step 1. 2’s complement of subt r ahend (=0101)
2
= (1011)
2
Step 2. Per for m addit ion of minuend and 2’s complement of subt r ahend
Step 3. Since a final car r y is pr oduced in st ep 2 (which is discar ded) t he r esult is posit ive.
So,
r esult = (0010)
2
= (2)
10
(ii) 5 – 7:
binar y of 5 = (0101)
2
binar y of 7 = (0111)
2
Step 1. 2’s complement of subt r ahend (= 0111) = 1001
Step 2. Addit ion of minuend and 2’s complement of subt r ahend
O
Q
P
bot h t he number s should
have equal lengt h.
Numbering S ystems 31
Step 3. Since final car r y is not gener at ed in st ep 2, t he r esult is negat ive and is in 2’s
complement for m. So we must t ake 2’s complement of r esult obt ained in st ep 2 t o find cor r ect
magnit ude of r esult .
2’s complement of r esult (1110)
2
= (0010)
2
so, final r esult = – (0010)
2
= – (2)
10
1.7.3 Sig ne d Bina ry Re p re se nta tion
Unt ill now we have discussed r epr esent at ion of unsigned (or posit ive) number s, except
one or t wo places. In comput er syst ems sign (+ve or –ve) of a number should also be
r epr esent ed by binar y bit s.
The accept ed convent ion is t o use 1 for negat ive sign and 0 for posit ive sign. In signed
r epr esent at ion MSB of t he given binar y st r ing r epr esent s t he sign of t he number, in all t ypes
of r epr esent at ion. We have t wo t ypes of signed r epr esent at ion:
1. Signed Magnit ude Repr esent at ion
2. Signed Complement Repr esent at ion
In a signed-Magnitude r epr esent at ion, t he MSB r epr esent t he sign and r est of t he bit s
represent t he magnit ude. e.g.,
Not e t hat posit ive number is r epr esent ed similar t o unsigned number. Fr om t he example
it is also evident t hat out of 4-bit s, only 3-bit s ar e used t o r epr esent t he magnit ude. Thus in
general, n – 1 bit s ar e used t o denot e t he magnit ude. So t he r ange of signed r epr esent at ion
becomes –(2
n–1
– 1) t o (2
n–1
– 1).
In a signed-complement r epr esent at ion t he posit ive number s ar e r epr esent ed in t r ue
binar y for m wit h MSB as 0. Wher e as t he negat ive number s ar e r epr esent ed by t aking
appr opr iat e complement of equivalent posit ive number, including t he sign bit . Bot h 1’s and
2’s complement s can be used for t his pur pose e.g.,
+5 = (0101)
2
–5 = (1010)
2
←in 1’s complement
= (1011)
2
←in 2’s complement
Not e t hat in signed complement r epr esent at ion t he fact r emains same t hat n – 1 bit s ar e
used for magnit ude. The r ange of number s
In 1’s complement 0 t o (2
n–1
– 1) Posit ive Number s
– 0 t o –(2
n–1
– 1) Negat ive Number s
In 2’s complement 0 t o (2
n–1
– 1) Posit ive Number s
– 1 t o –2
n–1
Negat ive Number s
32 S witching Theory
To illust r at e t he effect of t hese 3 r epr esent at ions, we consider 4-bit binar y r epr esent at ion
and dr aw t he below t able. Car efully obser ve t he differ ences in t hr ee met hods.
Decimal Signed 1’s complement 2’s complement
Magnit ude
+0 0 0 0 0 0 0 0 0 0 0 0 0
+1 0 0 0 1 0 0 0 1 0 0 0 1
+2 0 0 1 0 0 0 1 0 0 0 1 0
+3 0 0 1 1 0 0 1 1 0 0 1 1
+4 0 1 0 0 0 1 0 0 0 1 0 0
+5 0 1 0 1 0 1 0 1 0 1 0 1
+6 0 1 1 0 0 1 1 0 0 1 1 0
+7 0 1 1 1 0 1 1 1 0 1 1 1
–8 — — 1 0 0 0
–7 1 1 1 1 1 0 0 0 1 0 0 1
–6 1 1 1 0 1 0 0 1 1 0 1 0
–5 1 1 0 1 1 0 1 0 1 0 1 1
–4 1 1 0 0 1 0 1 1 1 1 0 0
–3 1 0 1 1 1 1 0 0 1 1 0 1
–2 1 0 1 0 1 1 0 1 1 1 1 0
–1 1 0 0 1 1 1 1 0 1 1 1 1
–0 1 0 0 0 1 1 1 1 —
Fig. 1.12 Differ ent signed r epr esent at ion
Fr om t he t able it is evident t hat bot h signed Magnit ude and 1’s complement met hods
int r oduce t wo zer os +0 and – 0 which is awkwar d. This is not t he case wit h 2’s complement .
This is one among t he r easons t hat why all t he moder n digit al syst ems use 2’s complement
met hod for t he pur pose of signed r epr esent at ion. Fr om t he above t able it is also evident t hat
in signed represent at ion
2
2
n
posit ive numbers and
2
2
n
negat ive number s can be r epr esent ed
with n-bit s. Out of 2
n
combinat ions of n-bit s, first
2
2
n
combinat ions ar e used t o denot e t he
posit ive numbers and next
2
2
n
combinat ions r epr esent t he negat ive number s.
Example. In a signed representation given binary string is (11101)
2
. What will be the sign
and magnitude of the number represented by this string in signed magnitude, 1’s complement
and 2’s complement representation.
Soluti on.
The number N = (11101)
2
since MSB = 1 t he given number is negat ive.
Numbering S ystems 33
(i) In signed Magnit ude MSB denot es sign and r est of t he bit s r epr esent magnit ude. So,
(ii) In 1’s complement if number is negat ive (i.e., MSB = 1) t hen t he magnit ude is
obt ained by t aking 1’s complement of given number.
1’s complement of (11101)
2
= (00010)
2
so (11101)
2
= –2 in 1’s complement .
(iii) In 2’s complement if number is negat ive (i.e., MSB = 1) t hen magnit ude is obt ained
by t aking 2’s complement of given number.
2’s complement of (11101)
2
= (00011)
2
= 3
so (11101)
2
= –3 in 2’s complement .
Example. Obtain an 8-bit representation of –9 in signed Magnitude, 1’s complement and
2’s complement representation.
Solution. We first find binary of 9 i.e., (9)
10
= (1001)
2
Next we r epr esent 9 using 8-bit s. So N = (00001001)
2
= (9)
10
(i) In signed Magnit ude, MSB shows sign and r est of t he bit s shows t r ue magnit ude. So,
(–9)
10
= (10001001)
2
(ii) In 1’s complement , negat ive number is r epr esent ed by t aking 1’s complement of
posit ive number. So,
(–9)
10
= 1’s complement of (00001001)
2
= (11110110)
2
(iii) In 2’s complement
(–9)
10
= 2’s complement of (00001001)
2
= (11110111)
2
1.7.4 Arithme tic O ve rflow
When t he r esult of an ar it hmet ic oper at ion r equir es n+1 bit s, upon operat ing on n-bit s
number, an over flow occur s. Alt er nat ely, if r esult exceeds t he r ange 0 t o 2
n
– 1, an over flow
occur s.
Let us consider t he addit ion of t wo 4-bit number s
Thus addit ion of t wo 4-bit s number s r equir es 5-bit s (n+1 bit s) t o r epr esent t he sum.
Alt er nat ely, t he r esult of addit ion of 4-bit s, falls out side t he r ange 0 t o 15 (i.e., 0 t o 2
4
–1).
Thus, over flow has occur ed.
34 S witching Theory
In case of si gned ari thmeti c t he over flow causes t he sign bit of t he answer t o change.
In t his case an over flow occur s if t he r esult does not lie in t he r ange –2
n–1
t o 2
n–1
– 1. In
signed ar it hmet ic over flow can occur only when t wo posit ive number s or t wo negat ive num-
ber s ar e added.
Let us consider 4-bit signed 2’s complement r epr esent at ion.
1. Addit ion of t wo posit ive number s +6 and +5
Since MSB of r esult is 1, if r eflect s a negat ive r esult which is incor r ect . It happened
because over flow has changed t he sign of r esult .
2. Addit ion of t wo negat ive number s –6 and –5
In 2’s complement if a car r y is gener at ed aft er t he addit ion t hen car r y is discar ded and
r esult is declar ed posit ive. Thus, r esult = (0101)
2
= +5 which is wr ong, because addit ion of
t wo negat ive number s should give a negat ive r esult . This happened due t o over flow.
Not e t hat over flow is a pr oblem t hat occur s when r esult of an oper at ion exceeds t he
capacit y of st or age device. In a comput er syst em t he pr ogr ammer must check t he over flow
aft er each ar it hmet ic oper at ion.
1.7.5 9’s a nd 10’s Comple me nt
9’s and 10’s complement s ar e t he met hods used for t he r epr esent at ion of decimal num-
ber s. They ar e ident ical t o t he 1’s and 2’s complement s used for binar y number s.
9’s complement : 9’s complement of a decimal number is defined as (10
n
– 1) – N, where n
is no. of digit s and N is given decimal numbers. Alt ernat ely, 9’s complement of a decimal number
can be obtained by subtracting each digit from 9. 9’s complement of N = (10
n
–1) – N.
Example. Find out the 9’s complement of following decimal numbers.
(i) 459 (ii) 36 (iii) 1697
Solution. (i) By using (10
n
–1) – N; But , n = 3 in t his case
So, (10
n
–1) – N = (10
3
– 1) – 459 = 540
Thus 9’s complement of 459 = 540
(ii) By subt r act ing each digit fr om 9
9 9
–3 6
6 3
So, 9’s complement of 36 is 63.
Numbering S ystems 35
(iii) We have N = 1697, so n = 4
Thus, 10
n
–1 = 10
4
– 1 = 9999
So, (10
n
–1) – N = (10
4
–1) – 1697 = 9999 – 1697
= 8302
Thus, 9’s complement of 1697 = 8302
10’s complement: 10’s complement of a decimal number is defined as 10
n
– N.
10’s complement of N = 10
n
– N
but 10
n
– N = (10
n
– 1) – N + 1
= 9’s complement of N + 1
Thus, 10’s complement of a decimal number can also be obt ained by adding 1 t o it s 9’s
complement .
Example. Find out the 10’s complement of following decimal numbers. (i) 459 (ii) 36.
Solution. (i) By using 10
n
– N; We have N = 459 so n = 3
So, 10
n
– N = 10
3
– 459 = 541
So, 10’s i s complement of 459 = 541
(ii) By adding 1 t o 9’s complement
9’s complement of 36 = 99 – 36
= 63
Hence, 10’s complement of 36 = 63 + 1
= 64
1.7.6 r’s C omple me nt a nd ( r – 1) ’s C omple me nt
The r ’s and (r – 1)’s complement s ar e gener alized r epr esent at ion of t he complement s, we
have st udied in pr evious subsect ions. r st ands for r adix or base of t he number syst em, t hus
r’s complement is referred as radix complement and (r – 1)’s complement is r efer r ed as
diminished radix complement. Examples of r ’s complement s ar e 2’s complement and 10’s
complement . Examples of (r – 1)’s complement ar e 1’s complement and 9’s complement .
In a base-r syst em, the r’s and (r – 1)’s complement of t he number N having n digit s,
can be defined as:
(r – 1)’s complement of N = (r
n
– 1) – N
and r ’s complement of N = r
n
– N
= (r – 1)’s complement of N + 1
The (r – 1)’s complement can also be obt ained by subt r act ing each digit of N fr om
r–1. Using t he above met hodology we can also define t he 7’s and 8’s complement for oct al
syst em and 15’s and 16’s complement for hexadecimal syst em.
1.7.7 Rule s for Sub tra c tion Using r’s a nd ( r–1) ’s C omp le me nt
Let M (minuend) and S (subt r ahend) be t he t wo number s t o be used t o evaluat e t he
differ ence D = M – S, by using r’s complement and (r – 1)’s complement s, and eit her or bot h
t he number s may be signed or unsigned.
36 S witching Theory
Unt ill and unless specified t he given r ules ar e equally applied t o bot h t he complement s
for bot h signed and unsigned and ar it hmet ic. For t he clar it y of pr ocess let us assume t hat
t wo dat a set s ar e:
Unsigned dat a— M
u
= 1025, S
u
= 50 and D
u
= M
u
– S
u
Signed dat a— M
s
= –370, S
s
= 4312 and D
s
= M
s
– S
s
For illust r at ion pur pose (r – 1)’s complement is used for unsigned and r’s complement
for signed ar it hmet ic.
Ste p 1. Eq ua te the Le ng th
Find out t he lengt h of bot h t he number s (no. of digit ) and see if bot h ar e equal. If not ,
t hen make t he bot h t he number s equal by placing leading zer oes.
M
u
= 1025, S
u
= 50 → So S
u
= 0050
M
s
= –370, S
s
= 4312 → M
s
= –0370
Ste p 2. Re p re se nt Ne g a tive O p e ra nd s ( for Ne g a tive Numb e rs only)
If eit her or bot h of oper ands ar e negat ive t hen t ake t he appr opr iat e complement of t he
number as obt ained in st ep 1.
M
s
= –370, → r’s of M
s
= 9999 – 0370 + 1 → M
s
= 9630 and S
s
= 4312
Ste p 3. C omp le me nt the Sub tra he nd
In or der t o evaluat e differ ence t ake t he appr opr iat e complement of t he r epr esent at ion
obt ained for t he SUBTRAEND S
U
in st ep 1 and S
S
in st ep 2.
S
u
= 0050, (r – 1)’s of S
u
= 9999 – 0050 → S
u
= 9949 and we’ve M
u
= 1025
S
s
= 4312, r’s of S
s
= 9999 – 4312 + 1 → S
s
= 5688 and we’ve M
s
= 9630
Ste p 4. Addition a nd The Ca rry ( CY)
Add t he t wo number s in t he st ep 3 and check weat her or not car r y gener at ed fr om MSD
(Most Significant Digit ) due t o addit ion.
M
u
= 1025, S
u
= 9949 → So D
u
= M
u
– S
u
= 10974

CY
M
s
= 9630, S
s
= 5688 → So D
s
= M
s
– S
s
= 15318

CY
Ste p 5. Proc e ss the C a rry ( C Y)
In st ep 4, we obt ained r esult as CY, D. The CY fr om MSD cont ains some useful
infor mat ion especially in some unsigned ar it hmet ic. Pr ocessing is differ ent for t wo comple-
ment .
• For r’s complement . In t he case of r’s complement if t her e is car r y fr om MSD in
st ep 4 t hen simply discar d it . We ar e using r ’s complement t o per for m signed
oper at ion. In st ep 4 we get CY = 1, D
s
= 5318 aft er discar ding t he CY.
• For (r – 1)’s complement . In t his case if a car r y is gener at ed fr om MSD in st ep 4,
add t his car r y t o t he LSD of t he r esult . (We are using r – 1’s complement for
Numbering S ystems 37
unsigned) In st ep 4 we got CY = 1, D
u
= 0974 aft er adding car r y t o t he LSD (fr om
MSD in st ep 4 we get D
u
= 0974 + 1 → 0975. In t his case car r y is called “end-ar ound
car r y”.
Ste p 6. Re sult M a nip ula tion
The manipulat ion of r esult is same for bot h t he complement s. The way r esult is manipu-
lat ed is differ ent for signed and unsigned ar it hmet ic.
(a) UNSIGNED
(1) If a car r y was gener at ed in st ep 4 t hen t he r esult is posit ive(+) and t he digit s in
t he r esult shows t he cor r ect magnit ude of r esult .
(2) If t her e is no car r y fr om MSD in st ep 4 t hen t he r esult is negat ive (–) and t he digit s
in r esult is not showing t he cor r ect magnit ude. So must go for a post pr ocessing
(St ep 7) of r esult t o det er mine t he cor r ect magnit ude of t he r esult .
(b) SIGNED
(1) If t he MSD of r esult obt ained in st ep 5 is lesser t han t he half r adix (i.e., MSD <
r/2) t hen t he r esult is +ve and r epr esent ing t he cor r ect magnit ude. Thus no post
pr ocessing is r equir ed.
(2) If t he MSD of r esult obt ained in st ep 5 is not lesser t han t he half r adix (i.e., MSD
> r/2) = t hen t he r esult is –ve and cor r ect magnit ude of which must be obt ained
by post pr ocessing (St ep 7).
Ste p 7. Post Proc e ssing a nd Re sult De c la ra tion
By t he st ep 6 (a) – 1 and t he st ep 6 (b) – 1 we know t hat if t he r esult is +ve (posit ive)
it r epr esent s t he cor r ect magnit ude weat her it is signed or unsigned ar it hmet ic. However for
t he negat ive r esult s ar e not showing cor r ect magnit udes so post processing in principle is
needed for declaration of negative results.
(a) Declar e posit ive r esult s. As per t he r ules t he r esult of t he unsigned ar it hmet ic is
posit ive.
D
u
= +0975 (Ans.)
(b) Pr ocess and declar e negat ive r esult s. As per t he r ules r esult of signed ar it hmet ic
is negat ive and is in complement ed for m. Take t he appr opr iat e complement t o find
t he complement and declar e t he r esult .
r’s of D
s
= 5318 = 9999 – 5318 + 1 = –4682 (Ans.)
1.8 BINARY C O DED DEC IM AL ( BC D) AND ITS ARITHM ETIC
The BCD is a gr oup of four binar y bit s t hat r epr esent a decimal digit . In t his r epr e-
sent at ion each digit of a decimal number is r eplaced by a 4-bit binar y number (i.e., a
nibble). Since a decimal digit is a number fr om 0 t o 9, a nibble r epr esent ing a number
gr eat er t han 9 is invalid BCD. For example (1010)
2
is invalid BCD as it r epr esent s a
number gr eat er t han 9. The t able shown in Fig. 1.13 list s t he binar y and BCD r epr esen-
t at ion of decimal number s 0 t o 15. Car efully obser ve t he differ ence bet ween binar y and
BCD r epr esent at ion.
38 S witching Theory
Decimal Binary Representation BCD Representation
Number
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 0
3 0 0 1 1 0 0 1 1
4 0 1 0 0 0 1 0 0
5 0 1 0 1 0 1 0 1
6 0 1 1 0 0 1 1 0
7 0 1 1 1 0 1 1 1
8 1 0 0 0 1 0 0 0
9 1 0 0 1 1 0 0 1
10 1 0 1 0 0 0 0 1 0 0 0 0
11 1 0 1 1 0 0 0 1 0 0 0 1
12 1 1 0 0 0 0 0 1 0 0 1 0
13 1 1 0 1 0 0 0 1 0 0 1 1
14 1 1 1 0 0 0 0 1 0 1 0 0
15 1 1 1 1 0 0 0 1 0 1 0 1
Fig. 1.13 Binar y and BCD r epr esent at ion of decimal number s
BCD Addition: In many applicat ion it is r equir ed t o add t wo BCD number s. But t he
adder cir cuit s used ar e simple binar y adder s, which does not t ake car e of peculiar it y of BCD
r epr esent at ion. Thus one must ver ify t he r esult for valid BCD by using following r ules:
1. If Nibble (i.e., gr oup of 4-bit s) is less t han or equal t o 9, it is a valid BCD Number.
2. If Nibble is gr eat er t han 9, it is invalid. Add 6 (0110) t o t he nibble, t o make it valid.
OR
If a car r y was gener at ed fr om t he nibble dur ing t he addit ion, it is invalid. Add 6
(0110) t o t he nibble, t o make it valid.
3. If a car r y is gener at ed when 6 is added, add t his car r y t o next nibble.
Example. Add the following BCD numbers. (i) 1000 and 0101 (ii) 00011001 and 00011000
Solution. (i)
Since, (1101)
2
> (9)
10
add 6 (0110) t o it
So,
So, r esult = 00010011
Numbering S ystems 39
(ii)
1
0 0 0 1
0 0 0 1
0 0 1 1
1 0 0 1
1 0 0 0
0 0 0 1
19
+18
37
Car r y gener at ed fr om nibble
Since, a car r y is gener at ed fr om r ight most nibble we must add 6 (0110) t o it .
So,
So, r esult = 00110111
BCD Subtracti on. The best way t o car y out t he BCD subt r act ion is t o use comple-
ment s. The 9’s and 10’s complement , st udied in subsect ion 1.7.5, ar e exclusively used for t his
pur pose. Alt hough any of t he t wo complement s can be used, we pr efer 10’s complement for
subt r act ion. Following ar e t he st eps t o be followed for BCD subt r act ion using 10’s comple-
ment :
1. Add t he 10’s complement of subt r ahend t o minuend.
2. Apply t he r ules of BCD addit ion t o ver ify t hat r esult of addit ion is valid BCD.
3. Apply t he r ules of 10’s complement on t he r esult obt ained in st ep 2, t o declar e t he
final result i.e., t o declar e t he r esult of subt r act ion.
Example. S ubtract 61 from 68 using BCD.
Solution. To illust r at e t he pr ocess fir st we per for m t he subt r act ion using 10’s comple-
ment in decimal syst em. Aft er t hat we go for BCD subt r act ion.
we have D = 68 – 61
So, 10’s complement of 61 = 99 – 61 + 1 = 39
So, 6 8
+ 3 9
1 0 7

Carry
In 10’s complement if an end car r y is pr oduced t hen it is discar ded and r esult is declar ed
posit ive. So,
D = +07
by using BCD
1.
2. Check for valid BCD– since a car r y is gener at ed fr om r ight most nibble, we must add
6 (0110) t o it . Since t he left most nibble is gr eat er t han 9, we must add 6(0110) t o it .
40 S witching Theory
Thus,
3. Declar at ion of r esult – We got end car r y is st ep 2. In 10’s complement ar it hmet ic, end
car r y is discar ded and r esult is declar ed posit ive. Hence,
D = (00000111)
2
= (7)
10
1.9 C O DES
Coding and encoding is t he pr ocess of assigning a gr oup of binar y digit s, commonly
r efer r ed t o as ‘bit s’, t o r epr esent , ident ify, or r elat e t o a mult ivalued it ems of infor mat ion. By
assigning each it em of infor mat ion a unique combinat ion of bit s (1’s and o’s), we t r ansfor m
some given infor mat ion int o anot her for m. In shor t , a code is a symbolic r epr esent at ion of
an infor mat ion t r ansfor m. The bit combinat ion ar e r efer r ed t o as ‘CODEWORDS’.
Ther e ar e many differ ent coding schemes, each having some par t icular advant ages and
char act er ist ics. One of t he main effor t s in coding is t o st andar dize a set of univer sal codes
t hat can be used by all.
In a br oad sense we can classify t he codes int o five gr oups:
(i) Weight ed Binar y codes
(ii) Non-weight ed codes
(iii) Er r or –det ect ing codes
(iv) Er r or –cor r ect ing codes
(v) Alphanumer ic codes.
1.9.1 We ig hte d Bina ry C od e s
In weight ed binar y codes, each posit ion of a number r epr esent s a specific weight . The
bit s ar e mult iplied by t he weight s indicat ed; and t he sum of t hese weight ed bit s gives t he
equivalent decimal digit . We have been familiar wit h t he binar y number syst em, so we shall
st ar t wit h st r aight binar y codes.
(a) Strai ght Bi nary codi ng is a met hod of r epr esent ing a decimal number by it s binar y
equivalent . A st r aight binar y code r epr esent ing decimal 0 t hr ough 7 is given in t able below:
Decimal Three bit straight Weights MOI S um
Binary Code 2
2
2
1
2
0
0 000 0 0 0 0
1 001 0 0 1 1
2 010 0 2 0 2
3 011 0 2 1 3
4 100 4 0 0 4
5 101 4 0 1 5
6 110 4 2 0 6
7 111 4 2 1 7
Numbering S ystems 41
In t his par t icular example, we have used t hr ee bit s t o r epr esent 8 dist inct element s of
informat ion i.e., 0 t hr ough 7 in decimal for m.
Now t he quest ion arises, if n element s of infor mat ion ar e t o be coded wit h binar y (t wo
valued bit s), t hen how many bit s ar e r equir ed t o assign each element of infor mat ion a unique
code wor d (bit combinat ion). Unique is impor t ant , ot her wise t he code would be ambiguous.
The best appr oach is t o evaluat e how many code wor ds can be der ived fr om a combina-
tion of n bit s.
For example: Let n = no. of bit s in t he codeword and x = no. of unique wor ds
Now, if n = 1, then x = 2 (0, 1)
n = 2, then x = 4 (00, 01, 10, 11)
n = 3, then x = 8 (000, 001, ..., 111)
and in gener al, n = j, then x = 2
j
t hat is, if we have available j no. of bit s in t he code wor d, we can uniquely encode max 2
j
dist inct element s of infor mat ion.
Inversely, if we are given x element s of infor mat ion t o code int o binar y coded for mat ,
t he following condit ion must hold:
x < 2
j
or j > log
2
x
or j > 3.32 log
10
x
wher e j = number of bit s in code wor d.
Example. How many bits would be required to code the 26 alphabetic characters plus the
10 decimal digits.
Solution. Her e we have t ot al 36 discr et e element s of infor mat ion.
⇒ x = 36
Now j > log
2
x
⇒ j > log
2
36 or j > 3.32 log
10
36
or j > 5.16 bit s
Since bit s ar e not defined in fr act ional par t s, we know j > 6.
In ot her wor ds, a minimum of 6 bit code is r equir ed t hat leaves 28 unused code wor ds
out of t he 64 which ar e possible (2
6
= 64 and 64 – 36 = 28).
This syst em of st r aight binar y coding has t he disadvant age t hat t he lar ge number s
r equir e a gr eat deal of har dwar e t o handle wit h. For example if we have t o conver t decimal
2869594 t o st r aight binar y code a r egr ous division of t his number by 2 is r equir ed unt ill we
get r emainder 0 or 1.
The above difficult y is over comed by using anot her coding scheme called as BCD codes.
(b) Bi nary Codes Deci mal Codes (BCD codes). In BCD codes, individual decimal
digit s ar e coded in binar y not at ion and ar e oper at ed upon singly. Thus binar y codes r epr esent -
42 S witching Theory
ing 0 t o 9 decimal digit s ar e allowed. Ther efor e all BCD codes have at least four bit s (
Q
min.
no. of bit s r equir ed t o encode t o decimal digit s = 4)
For example, decimal 364 in BCD
3 → 0011
6 → 0110
4 → 0100
364 → 0011 0110 0100
However, we should r ealize t hat wit h 4 bit s, t ot al 16 combinat ions ar e possible (0000,
0001, ..., 11 11) but only 10 ar e used (0 t o 9). The r emaining 6 combinat ions ar e unvalid and
commonly r efer r ed t o as ‘UNUSED CODES’.
Ther e ar e many binar y coded decimal codes (BCD) all of which ar e used t o r epr esent
decimal digit s. Ther efor e all BCD codes have at least 4 bit s and at least 6 unassigned or
unused code wor ds.
Some example of BCD codes ar e:
(a) 8421 BCD code, somet imes r efer r ed t o as t he Nat ur al Binar y Coded Decimal Code
(NBCD);
(b)* Excess-3 code (XS3);
(c)** 84 –2 –1 code (+8, +4, –2, –1);
(d) 2 4 2 1 code
Example. Lowest [643]
10
int o XS3 code
Decimal 6 4 3
Add 3 t o each 3 3 3
Sum 9 7 6
Conver t ing t he sum int o BCD code we have
0 7 6
↓ ↓ ↓
1001 0111 0110
Hence, XS3 for [643]
10
= 1001 0111 0110
*–XS3 is an example of nonweight ed code but is a t ype of BCD code. It is obt ained by adding 3 t o a
decimal number. For example t o encode t he decimal number 7 int o an excess 3 code. We must fir st add
3 t o obt ain 10. The 10 is t hen encoded in it s equivalent 4 bit binar y code 1010. Thus as t he name
indicat es, t he XS3 r epr esent s a decimal number in binar y for m, as a number gr eat er t han 3.
** – Dashes (–) ar e minus signs.
Numbering S ystems 43
Table : BCD codes
Decimal 8421 Excess-3 84–2–1 2421
Digit (NBCD) code (XS 3) code code
0 0000 0011 0000 0000
1 0001 0100 0111 0001
2 0010 0101 0110 0010
3 0011 0110 0101 0011
4 0100 0111 0100 0100
5 0101 1000 1011 1011
6 0110 1001 1010 1100
7 0111 1010 1001 1101
8 1000 1011 1000 1110
9 1001 1100 1111 1111
Ther e ar e many BCD codes t hat one can develop by assigning each column or bit posit ion
in t he code, some weight ing fact or in such a manner t hat all of t he decimal digit s can be coded
by simply adding t he assigned weight s of t he 1 bit s in t he code wor d.
For example: 7 is coded 0111 in NBCD, which is int er pr et ed as
0 × 8 + 1 × 4 + 1 × 2 + 1 × 1 = 7
The NBCD code is most widely used code for t he r epr esent at ion of decimal quant it ies in
a binar y coded for met .
For example: (26.98) would be r epr esent ed in NBCD as
2 6 9 8
(26.98)
10
= (0010 0110. 1001 1000) NBCD
It should be not ed t hat on t he per digit basis t he NBCD code is t he binar y numer al
equivalent of t he decimal digit it r epr esent s.
Se lf c omp le me nting BC D c od e s
The excess 3, 8 4–2–1 and 2421 BCD codes ar e also known as self complement ing codes.
Self complement ing pr oper t y– 9’s complement of t he decimal number is easily obt ained
by changing 1’0 t o 0’s and 0’s t o 1’s in cor r esponding codewor d or t he 9’s complement of self
complement ing code wor d is t he same as it s logical complement .
When ar it hmet ic is t o be per for med, oft en an ar it hmet ic “complement ” of t he number s
will be used in t he comput at ions. So t hese codes have a par t icular advant age in machines t hat
use decimal ar it hmet ic.
Example. The decimal digit 3 in 8.4–2–1 code is coded as 0101. The 9’s complement of
3 is 6. The decimal digit 6 is coded as 1010 that is 1’s complement of the code for 3. This is
termed as self complementing property.
1.9.2 Non We ig hte d C od e s
These codes ar e not posit ionally weight ed. This means t hat each posit ion wit hin a binar y
number is not assigned a fixed value. Excess-3 codes and Gr ay codes ar e examples of non-
weight ed codes.
We have alr eady discussed XS3 code.
44 S witching Theory
G ra y c od e ( Unit Dista nc e c od e or Re fle c tive c od e )
Ther e ar e applicat ions in which it is desir able t o r epr esent numer ical as well as ot her
infor mat ion wit h a code t hat changes in only one bit posit ion fr om one code wor d t o t he next
adjacent wor d. This class of code is called a unit dist ance code (UDC). These ar e somet imes
also called as ‘cyclic’, ‘r eflect ive’ or ‘gr ay’ code. These codes finds gr eat applicat ions in Boolean
funct ion minimizat ion using Kar naugh map.
The gray code shown in Table below is bot h r eflect ive and unit dist ance.
Table : Gray codes *
Decimal Three bit Four bit
Digit Gray code Gray code
0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1
2 0 1 1 0 0 1 1
3 0 1 0 0 0 1 0
4 1 1 0 0 1 1 0
5 1 1 1 0 1 1 1
6 1 0 1 0 1 0 1
7 1 0 0 0 1 0 0
8 – 1 1 0 0
9 – 1 1 0 1
10 – 1 1 1 1
11 – 1 1 1 0
12 – 1 0 1 0
13 – 1 0 1 1
14 – 1 0 0 1
15 – 1 0 0 0
0
1
1
0
0
1
2
3
0
0
1
1
00
01
11
10
10
11
01
00
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
*Gr ay codes ar e for med by r eflect ion. The t echnique is as follows:
In binar y we have t wo digit s 0 and 1.
Step I. Wr it e 0 and 1 and put a mir r or, we fir st see 1 and
t hen 0. Place 0’s above mir r or and 1’s below mir r or
We have got gr ay code for decimal digit s 0 t hr ough 4.
Step II. Wr it e t hese 4 codes and again put a mir r or. The code
will look in t he or der 10, 11, 01 and 00. Then place 0’s above
mir r or and 1’s below mir r or.
Pr oceeding int act ively in t he same manner. We can for m Gr ay
code for any decimal digit .
Numbering S ystems 45
Bina ry to G ra y c onve rsion
(1) Place a leading zer o befor e t he most significant bit (MSB) in t he binar y number.
(2) Exclusive-OR (EXOR) adjacent bit s t oget her st ar t ing fr om t he left of t his number
will r esult in t he Gr ay code equivalent of t he binar y number.
Exclusive–OR– If t he t wo bit s EX–OR’d ar e ident ical, t he r esult is 0; if t he t wo bit s differ,
t he r esult is 1.
Example. Convert binary 1010010 to Gray code word.
0 1 0 1 0 0 1 0
1 1 1 1 0 1 1
⇒ (1010010) = (1111011)
2 Gr a y
.
G ra y to Bina ry c onve rsion
Scan t he gr ay code wor d fr om left t o r ight . The fir st 1 encount er ed is copied exact ly as
it st ands. Fr om t hen on, 1’s will be wr it t en unt ill t he next 1 is encount er ed, in which case
a 0 is wr it t en. Then 0’s ar e wr it t en unt ill t he next 1 is encount er ed, in which case a 1 is
wr it t en, and so on.
Example 1. Convert Gray code word 1111011 into binary.
1 1 1 1 0 1 1
↓ ↓ ↓ ↓ ↓ ↓ ↓ ⇒ (1111011)
Gray
= (1010010)
2
.
1 0 1 0 0 1 0
Example 2. Convert Gray code word 10001011 into binary.
1 0 0 0 1 0 1 1
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
1 1 1 1 0 0 1 0
⇒ (10001011)
Gray
= (11110010)
2
.
1.9.3 Error De te c ting C od e s
Binar y infor mat ion is t r ansmit t ed fr om one device t o anot her by elect r ic wir es or ot her
communicat ion medium. A syst em t hat can not guar ant ee t hat t he dat a r eceived by one
device ar e ident ical t o t he dat a t r ansmit t ed by anot her device is essent ially useless. Yet
anyt ime dat a ar e t r ansmit t ed fr om sour ce t o dest inat ion, t hey can become cor r upt ed in
passage. Many fact or s, including ext er nal noise, may change some of t he bit s fr om 0 t o 1 or
vicever sa. Reliable syst ems must have a mechanism for det ect ing and cor r ect ing such er r or s.
Binar y infor mat ion or dat a is t r ansmit t ed in t he for m of elect r o magnet ic signal over a
channel whenever an elect r omagnet ic signal flows fr om one point t o anot her, it is subject t o
unpr edict able int er fer ence fr om heat , magnet ism, and ot her for ms of elect r icit y. This int er-
fer ence can change t he shape or t iming of signal. If t he signal is car r ying encoded binar y dat a,
such changes can alt er t he meaning of dat a.
In a single bit er r or, a 0 is changed t o a 1 or a 1 is changed t o a 0.
In a bur st er r or, mult iple (t wo or mor e) bit s ar e changed.
The pur pose of er r or det ect ion code is t o det ect such bit r ever sal er r or s. Er r or det ect ion
uses t he concept of redundancy which means adding ext r a bit s for det ect ing er r or s at t he
dest inat ion.
46 S witching Theory
For a single bit er r or det ect ion, t he most common way t o achieve er r or det ect ion is by
means of a pari ty bi t.
A par it y bit is an ext r a bit (r edundant bit ) included wit h a message t o make t he t ot al
number of 1’s t r ansmit t ed eit her odd or even.
Table below shows a message of t hr ee bit s and it s cor r esponding odd and even par it y bit s.
If an odd par it y is adopt ed, P bit is choosen such t hat t he t ot al no. of 1’s is odd in four
bit t hat const it ut e message bit s and P.
If an even parit y is adopt ed, t he P bit is choosen such t hat t he t ot al number of 1’s is even.
Table: Pari ty bi t generati on
Message Odd Even Parity
x y z Parity (P) bit (P)
bit
0 0 0 1 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 0 1
The message wit h t he parit y bit (eit her odd or even) is t ransmit t ed t o it s dest inat ion. The
parit y of t he received dat a is checked at t he receiving end. If t he parit y of t he received dat a is
changed (from t hat of t ransmit t ed parit y), it means t hat at least one bit has changed t heir value
during t ransmission. Though t he parit y code is meant for single error det ect ion, it can det ect any
odd number of errors. However, in bot h t he cases t he original codeword can not be found.
If t her e is even combinat ion of er r or s (means some bit s ar e changed but par it y r emains
same) it r emains undet ect ed.
Checksums–The checksum met hod is used t o det ect double er r or s in bit s. Since t he
double er r or will not change t he par it y of t he bit s, t he par it y checker will not indicat e any
er r or.
In t he checksums met hod, Init ially a wor d A (let 11001010) is t r ansmit t ed, next wor d B
(let 00101101) is t r ansmit t ed. The sum of t hese t wo wor ds is r et ained in t he t r ansmit t er. Then
a wor d C is t r ansmit t ed and added t o t he pr evious sum; and t he new sum is r et ained.
Similar ly, each wor d is added t o t he pr evious sum; aft er t r ansmission of all t he wor ds, t he
final sum called t he checksum is also t r ansmit t ed. The same oper at ion is done at t he r eceiv-
ing end and t he final sum obt ained her e is checked against t he t r ansmit t ed checksum. If t he
t wo sums ar e equal t her e is no er r or.
Burst Erro r De te c tio n
So far we have consider ed det ect ing or cor r ect ing er r or s t hat occur independent ly or
r andomly in digit posit ions. But dist ur bances can wipe out an ent ir e block of digit s. For
example, a st r oke of light enning or a human made elect r ical dist ur bance can affect sever al
t r ansmit t ed digit s. Bur st er r or s ar e t hose er r or s t hat wipe out some or all of a sequent ial set
of digit s.
Numbering S ystems 47
A burst of lengt h b is defined as a sequence of digit s in which t he fir st digit and b for
Ball digit ar e in er r or, wit h t he b-2 digit s in bet ween eit her in er r or or r eceived cor r ect ly. For
Example l and m r epr esent er r or s t hen a sequence 10Ml 10 m00 l10l01mM10 has a bur st
lengt h 13.
It can be shown t hat for det ect ing all bur st er r or s of lengt h b or less; b par it y check bit s
ar e necessar y and sufficient .
To const r uct such a code, let s group k dat a digit s int o segment of b digit s in lengt h as
shown below:
1101 0101 1110 0100 0010
b digit s
Par it y check bit s
k dat a bit s
Bur st er r or det ect ion
To t his we add a last segment of b par it y check digit s, which ar e det er mined as follows:
‘The modulo-2 sum* of t he it h digit in each segment (including t he par it y check segment )
must be zer o.”
It is easy t o see t hat if a single sequence of lengt h b or less is in er r or, par it y will be
violat ed and t he er r or will be det ect ed and t he r eciever can r equest r et r ansmission of code.
1.9.4 Error C orre c ting C od e s
The mechanism t hat we have cover ed upt o t his point det ect er r or s but do not cor r ect
t hem. Er r or cor r ect ion can be handled in t wo ways. In one, when an er r or is encount er ed
t he r eceiver can r equest t he sender t o r et r ansmit ent ir e dat a unit . In t he ot her, a r eceiver
can use an er r or cor r ect ing code, which aut omat ically cor r ect s cer t ain er r or s.
In t heor y, it is possible t o cor r ect any binar y code er r or s aut omat ically using er r or
cor r ect ing codes, however t hey r equir e mor e r educt ant bit s t han er r or det ect ing codes.
The number of bit s r equir ed t o cor r ect a mult iple-bit or bur st er r or is so high t hat in most
cases, it is inefficient t o do so. For this r eason, most er r or cor r ect ion is limit ed t o one,
t wo, or t hr ee-bit er r or s. However, we shall confine our discussion t o only single bit er r or
cor r ect ion.
As we saw ear lier, single bit er r or s can be det ect ed by t he addit ion of a r edundant (par it y)
bit t o t he dat a (infor mat ion) unit . This pr ovides sufficient base t o int r oduce a ver y popular
er r or det ect ion as well cor r ect ion codes, known as Block codes.
Block codes: [(n, k) codes] In block codes, each block of k message bit s is encoded int o
a larger block of n bit s (n > k), as shown. These ar e also known as (n, k) codes.
Modulo–2 sum denot ed by symbol

wit h t he r ules of addit ion as follows:
0 0 0
0 1 1
1 0 1
1 1 0
⊕ =
⊕ =
⊕ =
⊕ =
R
S
|
|
T
|
|
U
V
|
|
W
|
|
48 S witching Theory
The r educt ant * (par it y) bit s ‘r’ ar e der ived fr om message bit s ‘k’ and ar e added t o t hem.
The ‘n’ bit block of encoder out put is called a codewor d.
Message
block
Message
k bits
ENCODER
Code
block
Message Redundant bits
k bits r bits
Code n bits = (k + r) bits
The simplest possible block code is when t he number of r educt ant or par it y bit s is one.
This is known as par it y check code. It is ver y clear t hat what we have st udied in single bit
er r or det ect ion is not hing but a class of ‘Block codes’.
R.W. Hamming developed a syst em t hat pr ovides a met hodical way t o add one or mor e
par it y bit t o dat a unit t o det ect and cor r ect er r or s weight of a code.
Ha mming d ista nc e a nd minimum d ista nc e
The weight of a code wor d is defined as t he number of nonzer o component s in it . For
example,
Code word Weight
010110 3
101000 2
000000 0
The ‘Hamming dist ance’ bet ween t wo code wor ds is defined as t he number of component s
in which t hey differ.
For example, Let U = 1010
V = 0111
W = 1001
Then, D (U, V) = dist ance bet ween U and V = 3
Similar ly, D (V, W) = 3
and D (U, W) = 2
The ‘minimum dist ance’ (D
min
) of a block code is defined is t he smallest dist ance bet ween
any pair of codewor ds in t he code.
Fr om Hamming’s analysis of code dist ances, t he following impor t ant pr oper t ies have
been der ived. If D
min
is t he minimum dist ance of a block code t hen
(i) ‘t’ number of er r or s can be det ect ed if
D
min
= t + 1
(ii) ‘t’ number of er r or s can be cor r ect ed if
D
min
= 2t + 1
It means, we need a minimum dist ance (D
min
) of at least 3 t o cor r ect single er r or and
wit h t his minimum. dist ance we can det ect upt o 2 er r or s.
*The ‘r’ bit ar e not necessar ily appear aft er ‘k’ bit s. They may appear at t he st ar t ing, end or in bet ween
‘k’ dat a bit s.
Numbering S ystems 49
Now coming t o our main object ive i.e., er r or cor r ect ion, we can say t hat an er r or occur s
when t he r eceiver r eads 1 bit as a 0 or a 0 bit as a 1. To cor r ect t he er r or, t he r eciever simply
r ever ses t he value of t he alt er ed bit . To do so, however, it must know which bit is in er r or.
The secr et of er r or cor r ect ion, t her efor e, is t o locat e t he invalid bit or bit s.
For example, t o cor r ect a single bit er r or in a seven bit dat a unit , t he er r or cor r ect ion code
must det er mine, which of t he seven dat a bit s has changed. In t he case we have t o dist inguish
bet ween eight differ ent st at es: no er r or, er r or in posit ion 1, er r or in posit ion 2, and so on, upt o
er r or in posit ion 7. To do so r equir es enough r edudant bit s t o show all eight st at es.
At fir st glance, it appear s t hat a 3-bit r edundant code should be adequat e because t hr ee
bit s can show eight differ ent st at es (000 t o 111) and can t hus indicat e t he locat ions of eight
differ ent possibilit ies. But what if an er r or occur s in t he r edundant bit s t hemselves. Seven
bit s of dat a plus t hr ee bit s of r edundancy equals 10 bit s. Thr ee bit s, however, can ident ify only
eight possibilit ies. Addit ional bit s ar e necessar y t o cover all possible er r or locat ions.
Re d und a nt Bits
To calculat e t he number of r edundant bit s (r) r equir ed t o cor r ect a given no. of dat a bit s
(k), we must find a r elat ionship bet ween k and r. Figure shows k bit s of dat a wit h r bit s of
r edundancy added t o t hem. The lengt h of t he r esult ing code is t hus n = k + r.
If t he t ot al no. of bit s in code is k + r, then r must be able t o indicat e at least k + r + 1
differ ent st at es. Of t hese, one st at e means no er r or and k + r st at es indicat e t he locat ion of
an error in each of t he k + r posit ions.
Data ( ) bits k
Redundant
( ) bits r
Total + = bits k r n
Alt er nat ively, we can say the k + r + 1 st at us must be discover able by r bit s; and r bit s
can indicat e 2
r
differ ent st at es. Ther efor e, 2
r
must be equal t o or great er t han k + r + 1:
2
r
> k + r + 1
The value of r can be det er mined by plugging in t he value of k (t he lengt h of dat a unit ).
For example, if t he value of k is 7 (⇒ seven bit dat a), t he smallest r value t hat can sat isfy
t his equat ion is 4:
2
4
> 7 + 4 + 1
and 2
3
> 7 + 4 +1
1.9.5 Ha mming C ode
So far, we have examined t he number of bit s required t o cover all of t he possible single
bit error st at es in a t ransmission. But how do we manipulat e t hose bit s t o discover which st at e
has occured ? A t echnique developed by R.W. Hamming provides a pract ical solut ion, Hamming
code is a class of block code (n, k) and we are going t o discuss (11, 7) Hamming code.
Positioning the Re d und a nt b its
The ‘Hamming code’ can be applied t o dat a unit s of any lengt h and uses t he r elat ionship
bet ween dat a and r edundant bit s as discussed above. As we have seen, a 7 bit dat a unit (⇒
k = 7) r equir es 4 r edundant bit s (⇒ r = 4) t hat can be added t o t he end of dat a unit (or
int er sper sed wit h dat a bit s). Such t hat a code wor d of lengt h 11 bit s (n = 11) is for med.
50 S witching Theory
In figur e t hese bit s ar e placed in posit ions 1, 2, 4 and 8 (t he posit ions in an 11-bit
sequence t hat ar e power s of 2). We r efer t hese bit s as r
1
, r
2
, r
4
and r
8
.
9 8 7 6 5 4 3 2 1 10 11 Bits ( ) n
d
7
d
6
d
5
r
4
d
4
d
3
d
2
r
3
d
1
r
2
r
1
Redundant bits
In t he Hamming code, each r bit is t he r edundant bit for one combinat ion* of dat a bit s.
The combinat ions (modulo-2 addit ions) used t o calculat e each of four r values (viz, r
1
, r
2
, r
4
and r
8
) for a 7 bit dat a sequence d
1
through d
7
ar e as follows:
r
1
: bit s 1, 3, 5, 7, 9, 11
r
2
: bit s 2, 3, 6, 7, 10, 11
r
4
: bit s 4, 5, 6, 7
r
8
: bit s 8, 9, 10, 11
Each dat a bit may be included in mor e t han one r edundant bit calculat ion. In t he sequences
above, for example, each of t he or iginal dat a bit s is included in at least t wo set s, while t he
r bit s ar e included in only one.
To see t he pat t er n behind t his st r at egy, look at t he binar y r epr esent at ion of each bit
posit ion. The r
1
bit is calculat ed using all bit posit ions whose binar y r epr esent at ion includes
a 1 in t he r ight most posit ion. The r
2
bit is calculat ed using all bit posit ions wit h a 1 in t he
second posit ion, and so on. (see Fig.)
11
d
7
d
6
d
5
r
8
d
4
d
3
d
2
r
4
d
1
r
2
r
1
9 7 5 3 1
1011 1001 0111 0101 0011 0001
r will take care
of these bits
1
11
d
7
d
6
d
5
r
8
d
4
d
3
d
2
r
4
d
1
r
2
r
1
10 7 6 3 2
1011 1010 0111 0110 0011 0010
r will take care
of these bits
2
*In codes combinat ion of bit s means modulo 2 addit ion t he dat a bit s. Modulo-2 addit ion applies
in binar y field wit h following r ules.
0 0 ⊕ = 0 Modulo 2 →

0 1 ⊕ = 1
1 0 ⊕ = 1
1 1 ⊕ = 0
Numbering S ystems 51
d
7
d
6
d
5
r
8
d
4
d
3
d
2
r
4
d
1
r
2
r
1
7 5 4
0111 0101 0100
r will take care
of these bits
4
11
d
7
d
6
d
5
r
8
d
4
d
3
d
2
r
4
d
1
r
2
r
1
10 9 8
1011 1010 1001 1000
r will take care
of these bits
8
6
0110
C a lc ula ting the r va lue s
Figur e shows a Hamming code implement at ion for a 7 bit dat a unit . In t he fir st st ep;
we place each bit of or iginal dat a unit in it s appr opr iat e posit ion in t he 11-bit unit . For
example, let t he dat a unit be 1001101.
In t he subsequent st eps; we calculat e t he EVEN par it ies for t he var ious bit combina-
t ions. The even par it y value for each combinat ion is t he value of cor r esponding r bit . For
example, t he value of r
1
is calculat ed t o pr ovide even par it y for a combinat ion of bit s 3, 5,
7, 9 and 11.
⇒ 1011 1001 0111 0101 0011 0001
Her e t he t ot al no. of 1’s ar e 13. Thus t o pr ovide even par it y r
1
= 1.
Similar ly t he value of r
2
is calculat ed t o pr ovide even par it y wit h bit s 3, 6, 7, 10, r
4
wit h
bit s 5, 6, 7 and r wit h bit s 9, 10, 11. The final 11-bit code is sent .
1 0 0 r
8
1 1 0 r
4
1 r
2
r
1
9 8 7 6 5 4 3 2 1 11 10
Data 1001101 →
Data
1 0 0 r
8
1 1 0 r
4
1 r
2
1
9 8 7 6 5 4 3 2 1 11 10
Adding
r
1
1 0 0 r
8
1 1 0 r
4
1 0 1
9 8 7 6 5 4 3 2 1 11 10
Adding
r
2
1 0 0 r
8
1 1 0 0 1 0 1
9 8 7 6 5 4 3 2 1 11 10
Adding
r
4
1 0 0 1 1 1 0 0 1 0 1
9 8 7 6 5 4 3 2 1 11 10
Adding
r
8
Code : 1001 110 0101
r = 1
r

= 0
r

= 0
r

= 1
Thus
r r r r = 1 0 0 1
1
2
4
8
8 4 2 1
Sender ’s
parity
52 S witching Theory
Error detection and correction – Suppose above gener at ed code is r eceived wit h t he
error at bit number 7 ⇒ bit has changed fr om 1 t o 0 see figur e below:
1 0 0 1 0 1 0 0 1 0 1 1 0 0 1 1 1 0 0 1 0 1
Received Sent
Error
The r eceiver r eceives t he code and r ecalculat e four new r edundant bit s (r
1
, r
2
, r
4
and
r
8
) using t he same set of bit s used by sender plus t he r elevant par it y bit for each set shown
below
1 0 0 1 0 1 0 0 1 0 1
9 8 7 6 5 4 3 2 1 11 10
1 0 0 1 0 1 0 0 1 0 1
9 8 7 6 5 4 3 2 1 11 10
1 0 0 1 0 1 0 0 1 0 1
9 8 7 6 5 4 3 2 1 11 10
1 0 0 1 0 1 0 0 1 0 1
9 8 7 6 5 4 3 2 1 11 10
0 1 1 1
The bit in position 7 is in Error 7 in decimal ←
r
8
r
4
r
2
r
1
Then it assembles t he new par it y values int o a binar y number in or der of r posit ion (r
8
,
r
4
, r
2
, r
1
). In our example, t his st ep gives us t he binar y number 0111 (7 in decimal), which
is t he pr ecise locat ion of t he bit in er r or.
Once t he bit is ident ified, t he r eciever can r ever se it s value and cor r ect t he er r or.
Note: If t he new par it y assembled is same as t he par it y at sender ’s end mean no er r or.
1.9.6 C yc lic C od e s
Binar y cyclic codes for m a subclass of linear block codes.
An (n, k) linear block code is called t he cyclic code if it sat isfies t he following pr oper t y:
If an n t uple (a row vect or of n element s), V = (V
0
, V
1
, V
2
, . . ., V
n–1
)
is a code vect or or C, t hen t he n t uple
V
1
= (V
n–1
, V
0
, V
1
, . . ., V
n–2
)
obt ained by shift ing V cyclically one place t o t he r ight (it may be left also) is also a code vect or
of C. Fr om above definit ion it is clear t hat
Numbering S ystems 53
V
(i)
= (V
n–i
, V
n–i+1
, . . ., V
0
, V
1
, . . . V
n–i–1
).
An example of cyclic code:
1 1 0 1
1 1 1 0
0 1 1 1
1 0 1 1
1 1 0 1
It can be seen t hat 1101, 1110, 0111, 1011 is obt ained by a cyclic shift of n-t uple 1101
(n = 4). The code obt ained by r ear r anging t he four wor ds is also a cyclic code. Thus 1110, 0111,
1011 ar e also cyclic codes.
This pr oper t y of cyclic code allows t o t r eat t he codewor ds as a polynomial for m. A
pr ocedur e for gener at ing an (n, k ) cyclic code is as follows:
The bit s of uncoded wor d (message) Let D = [d
0
, d
1
, d
2
... d
k–1
] ar e wr it t en as t he
coefficient s of polynomial of degr ee k – 1.
D(x) = d
0
x
0


d
1
x
1


d
2
x
2


...

d
k–1
x
k–1
Similar ly, t he coded wor d, let V = [v
0
, v
1
, v
2
, ..., v
n–1
) ar e wr it t en as t he coefficient s of
polynomial of degree n – 1.
V(x) = v
0
x
0


v
1
x
1


v
2
x
2


. . .

v
n–1
x
n–1
The coefficient s of t he polynomials ar e 0’s and 1’s and t hey belong t o t he binar y field wit h
t he modulo-2 r ules for addit ion as descr ibed in Hamming codes.
Now, we will st at e a t heor em* which is used for cyclic code gener at ion.
Theorem. If g(x) is a polynomial of degr ee (n–k) and is a fact or of x
n+1
, then g(x)
gener at es an (n, k) cyclic code in which t he code polynomial V(x) for a dat a polynomial D(x)
is given by
V(x) = D(x). g(x)
wher e V(x) – Code wor d polynomial of degr ee (n – 1)
D(x) – Dat a wor d polynomial of degr ee (k – 1)
g(x) – Gener at or polynomial of degr ee (n – k)
Example. Consider a (7, 4) cyclic code. The generator polynomial for this code is given
as g(x) = 1 + x + x
3
. Find all the code words of this code.
Solution. It is a (7, 4) cyclic code
⇒ n = No. of bit s in coded wor d = 7
and k = No. of bit s in dat a wor d = 4.
(n – k) = No. of r edundant bit s in code wor d = 3
It implies t hat , t her e ar e 16 differ ent messages t hat ar e possible (10000, 0001, 0010
. . . 1110, 1111). Cor r espondingly, t her e will be 16 differ ent codes (of 7 bit s).
Now, accor ding t o above t heor em, t he generat or polynomial g(x) must be a fact or of
(x
n
+ 1)** and of degr ee (n – k).
x
n
+ 1 = x
7
+ 1
If we fact or ize t his polynomial we get
x
7
+1 = (x + 1) (x
3
+ x + 1) (x
3
+ x
2
+ 1)
I II III
*Wit hout giving pr oof t hat is beyond t he scope of t his book.
**+ means modulo-2 operat ion ⊕ in binar y codes.
54 S witching Theory
⇒ I Fact or →x + 1
II Fact or →x
3
+ x + 1
III Fact or →x
3
+ x
2
+ 1
The I fact or does not sat isfy t he r equir ement t hat it must be of degr ee (n – k) but t he
II and III do sat isfy.
Ther efor e, we can eit her choose II Fact or or III Fact or as gener at or polynomial g(x).
However, t he set of codewor ds will nat ur ally be differ ent for t hese t wo polynomial.
In t his example, we have t aken g(x) as 1 + x + x
3
.
i.e., we have t o encode t he 16 messages using gener at or polynomial.
g(x) = 1 + x + x
3
.
Consider, for example, a dat a wor d 1010.
⇒ D = (d
0
, d
1
, d
2
, d
3
) = (1010)
Because t he lengt h is four, t he dat a polynomial D(x)
will be of t he form d
0
+ d
1
x + d
2
x
2
+ d
3
x
3
⇒ D(x) = 1 + 0.x + 1.x
2
+ 0.x
3
= 1 + x
2
The code polynomial V(x) = D(x) . g(x)
= (1 + x
2
) . (1 + x + x
3
)
= 1 + x + x
2
+
x x
3 3
+
0
+ x
5
⇒ V(x) = 1 + x + x
2
+ x
5
Q
if x = 1 t hen x
3
= 1
or if x = 0 t hen x
3
= 0
0 ⊕ 0 = 1 ⊕ 1 = 0
Because t he lengt h of codewor d and (n) is 7.
So t he st andar d polynomial will be of t he for m.
V(x) = V
0
+ V
1
x + V
2
x
2
+ V
3
x
3
+ V
4
x
4
+V
5
x
5
+ V
6
x
6
Compar ing t his st andar d polynomial wit h above poly. for V(x)
we get V = [1110010]
In a similar way, all code vect or s can be found out .
1.10 SO LVED EXAM PLES
Example. 1. Convert each binary number to the decimal:
(a) (11)
2
(b) (.11)
2
(1011)
2
(.111)
2
(10111)
2
(.1011)
2
(1111)
2
(.10101)
2
(11010111)
2
(.0101)
2
(1001)
2
(.110)
2
(c) (11.11)
2
(1011.1011)
2
(1111.0101)
2
(11010111.110)
2
(1001.10101)
2
Numbering S ystems 55
Solution. (a) (11)
2
= 1 × 2
1
+ 1 × 2
0
= 2 + 1 = 3
(1011)
2
= 1 × 2
3
+ 0 × 2
2
+ 1 × 2
1
+ 1 × 2
0
= 8 + 0 + 2 + 1 = 11
(10111)
2
= 1 × 2
4
+ 0 × 2
3
+ 1 × 2
2
+ 1 × 2
1
+ 1 × 2
0
= 16 + 0 + 4 + 2 + 1 = 23
(1111)
2
= 1 × 2
3
+ 1 × 2
2
+ 1 × 2
1
+ 1 × 2
0
= 8 + 4 + 2 + 1 = 15
(11010111)
2
= 1 × 2
7
+ 1 × 2
6
+ 0 × 2
5
+ 1 × 2
4
+ 0 × 2
3
+ 1 × 2
2
+
1 × 2
1
+ 1 × 2
0
= 128 + 64 + 0 + 16 + 0 + 4 + 2 + 1 = 215
(1001)
2
= 1 × 2
3
+ 0 × 2
2
+ 0 × 2
1
+ 1 × 2
0
= 8 + 0 + 0 + 1 = 9
(b) (.11)
2
= 1 × 2
–1
+ 1 × 2
–2
= .5 + .25 = (.75)
10
(.111)
2
= 1 × 2
–1
+ 1 × 2
–2
+ 1 × 2
–3
= .5 + .25 + .125 = (.875)
10
(.1011)
2
= 1 × 2
–1
+ 0 × 2
–2
+ 1 × 2
–3
+ 1 × 2
–4
= .5 + 0 + .125 + .0625 = (.6875)
10
(.10101)
2
= 1 × 2
–1
+ 0 × 2
–2
+ 1 × 2
–3
+ 0 × 2
–4
+ 1 × 2
–5
= .5 + 0 + .125 + 0 + .03125 = (.65625)
10
(.0101)
2
= 0 × 2
–1
+ 1 × 2
–2
+ 0 × 2
–3
+ 1 × 2
–4
= 0 + .25 + 0 + .0625 = (.3125)
10
(.110)
2
= 1 × 2
–1
+ 1 × 2
–2
+ 0 × 2
–3
= .5 + .25 + 0 = (.75)
10
(c) 11.11 = ?
Fr om par t (a) and par t (b), we see t hat
11 = 3
11 = .75
Ther efor e, (11.11)
2
= (3.75)
10
1011.1011 = ?
(1011)
2
= 11
(.1011)
2
= .6875
Ther efor e, (1011.1011)
2
= (.6875)
10
1111.0101 = ?
(1111)
2
= 15
(.0101)
2
= .3125
Ther efor e, (1111.0101)
2
= (15.3125)
10
11010111.110 = ?
11010111 = 215
.110 = .75
56 S witching Theory
(11010111.110)
2
= (215.75)
10
1001.10101 = ?
1001 = 9
.10101 = .65625
(1001.10101)
2
= (9.65625)
10
Example 2. How many bits are required to represent the following decimal numbers,
represent them in binary.
(I) (17)
10
(II) (27)
10
(III) (81)
10
(IV) (112)
10
(V) (215)
10
Solution. (I) Let n bit s r equir ed
n should be such t hat
2
n
> Given Number (N)
Ther efor e, 2
n
> 17
i.e., n > 5
Ther efor e minimum number of bit s r equir ed = 5.
(II) (27)
10
The minimum number of bit s r equir ed is given by
2
n
> N (given number )
2
n
> 27
i.e., n > 5
(III) (81)
10
The minimum number of bit s r equir ed is given by
2
n
> N
2
n
> 81
i.e., n = 7
(IV) (112)
10
The minimum number of r equir ed is given by
2
n
> N
2
n
> 112
i.e., n = 7
Numbering S ystems 57
(V) (215)
10
The minimum number of bit s r equir ed is given by
2
n
> 215
i.e., n = 8
Example 3. Convert the following numbers as indicated:
(a) decimal 225.225 to binary, octal and hexadecimal.
(b) binary 11010111.110 to decimal, octal and hexadecimal.
(c) octal 623.77 to decimal, binary and hexadecimal.
(d) hexadecimal 2AC5.D to decimal, octal and binary.
Solution. (a) 225.225 = (?)
2
(.225)
10
= (?)
2
.225 × 2 = 0.450
.450 × 2 = 0.900
.900 × 2 = 1.800
.800 × 2 = 1.600
.600 × 2 = 1.200
.200 × 2 = 0.400
.400 × 2 = 0.800
.800 × 2 = 1.600
.600 × 2 = 1.200
Fr act ion par t = 001110011
58 S witching Theory
Ther efor e,
(225.225)
10
= 11100001.001110011
(225.225)
10
= (?)
8
From t he previous st ep we know t he binary equivalent of decimal no. as 11100001.001110011.
For oct al number, binar y number is par t it ioned int o gr oup of t hr ee digit each st ar t ing
fr om r ight t o left and r eplacing decimal equivalent of each gr oup.
(225.225)
10
= (341.163)
8
(225.225)
10
= (?)
16
For hexadecimal number, inst ead of t hr ee four digit s ar e gr ouped.
(225.225)
10
= E1.398
(b) (11010111.110)
2
= (?)
10
Fr om example 1.6.1
(11010111.110)
2
= (215.75)
10
(11010111.110)
2
= (?)
8
= 327
= 6
(11010111.110)
2
= (327.6)
8
(11010111.110)
2
= (?)
16
= D7
= C
(11010111.110)
2
= (D7.C)
16
(c) (623.77)
8
= (?)
2
623 = 110010011
.77 = 111111
Numbering S ystems 59
(623.77)
8
= (110010011.111111)
2
(623.77)
8
= (?)
16
= 193
= FC
(623.77)
8
= (193.FC)
16
(623.77)
8
= (?)
10
623 = 6 × 8
2
+ 2 × 8
1
+ 3 × 8
0
= 384 + 16 + 3
= 403
.77 = 7 × 8
–1
+ 7 × 8
–2
= 7 × .125 + 7 × .015625
= .875 + .109375
= 0.9843
(623.77)
8
= (403.9843)
10
(d) (2AC5.D)
16
= (?)
2
2AC5 = 0010101011000101
D = 1101
(2AC5.D)
16
= (10101011000101.1101)
2
(2AC5.D)
16
= (?)
8

(2AC5.D)
16
= (25305.64)
8
(2AC5.D)
16
= (?)
10
2AC5 = 2 × 16
3
+ 10 × 16
2
+ 12 × 16
1
+ 5 × 16
0
= 2 × 4096 + 10 × 256 + 12 × 16 + 5 × 1
= 8192 + 2560 + 192 + 5
= 10949
D = 13 × 16
–1
= 13 × .0625
= .8125
(2AC5.D)
16
= (10949.8125)
10
60 S witching Theory
Example 4. Obtain the 9’s and 10’s complement of the following decimal numbers.
(i) 10000, (ii) 00000, (iii) 13469, (iv) 90099, (v) 09900
Solution. 9’s complement
10’s complement = 9’s complement + 1 (LSB)
Example 5. Perform the subtraction with the decimal numbers given using
(1) 10’s complement.
(2) 9’s complement.
Check the answer by straight subtraction
(a) 5249 – 320 (b) 3571 – 2101.
Solution. (a) Usi ng 10’s complement. 10’s complement of 320
Ther efor e, 5249 – 320 = 5249
+9680
CY →
discarded
Result = 4929
Usi ng 9’s complement. 9’s complement of 320
Ther efor e, 5249 – 320 = 5249
+ 9679
CY →
Result = 4929
By strai ght subtracti on
Hence, r esult s ar e same by each met hod.
Numbering S ystems 61
(b) Usi ng 10’s complement
10’s complement of 2101 =
Ther efor e, 3571 – 2101 = 3571
+7899
CY →
discarded
Result = 470
Usi ng 9’s complement
9’s complement of 2101 = 7898
Ther efor e, 3571 – 2101 = 3571
+7898
CY →
By strai ght subtracti on
Hence, r esult s ar e same by each met hod.
Example 6. Obtain the 1’s and 2’s complement of the following binary numbers
(I) 11100101 (II) 0111000 (III) 1010101 (IV) 10000 (V) 00000.
Soluti on.
(I) 1’s complement = 00011010
2’s complement = 1’s complement + 1 = 00011011
(II) 1’s complement = 1000111
2’s complement = 1000111
1
(III) 1’s complement = 0101010
2’s complement = 0101011
(IV) 1’s complement = 01111
2’s complement = 10000
(V) 1’s complement = 11111
2’s complement = 00000
62 S witching Theory
1.11 EXERC ISES
1. Wr it e 9’s and 10’s complement of t he following number s:
+9090
–3578
+136.8
–136.28
2. (a) Conver t t he decimal int eger ’s +21 and –21 int o 10’s complement and 9’s comple-
ment .
(b) Conver t t he above t wo number s in binar y and expr ess t hem in six bit (t ot al)
signed magnit ude and 2’s complement .
3. (a) Find t he decimal equivalent of t he following binar y number s assuming signed
magnit ude r epr esent at ion of t he binar y number :
(I) 001000 (II) 1111
(b) Wr it e t he pr ocedur e for t he subt r act ion of t wo number s wit h (r – 1)’s comple-
ment .
(c) Per for m t he subt r act ion wit h t he following binar y number s using
2’s complement and 1’s complement r espect ively.
(I) 11010 – 1101 (II) 10010 – 10011
(d) Per for m t he subt r act ion wit h following decimal number s using
10’s complement and 9’s complement r espect ively.
(I) 5294 – 749 (II) 27 – 289
4. Conver t :
(I) (225.225)
12
t o Hexadecimal number.
(II) (2AC5.15)
16
t o Oct al number.
5. Per for m t he following using 6’s complement :
(I) (126)
7
+ (42)
7
(II) (126)
7
– (42)
7
6. Repr esent t he following decimal number s in t wo’s complement for mat :
(I) +5 (II) +25 (III) –5 (IV) –25 (V) –9
7. Repr esent t he decimal number s of quest ion 6 in ones complement for mat .
8. Find t he decimal equivalent of each of t he following number s assuming t hem t o be
in t wo’s complement for mat .
(a) 1000 (b) 0110 (c) 10010 (d) 00110111
9. Conver t t he following oct al number s int o equivalent decimal number s:
(a) 237 (b) 0.75 (c) 237.75
10. Repr esent t he following decimal number s in sign-magnit ude for mat :
(a) –11 (b) –7 (c) +12 (d) +25
2.0 INTRO DUC TO RY C O NC EPTS O F DIG ITAL DESIG N
Geor ge Boole, in his wor k ent it led ‘An Invest igat ion of t he Laws of Thought ’, on which
are founded t he Mat hemat ical Theories of Logic and Probabilit y (1854), int roduced t he fundamen-
t al concept s of a t wo-values (binary) syst em called Boolean Algebra. This work was lat er
organized and syst emized by Claude Shannon in ‘Symbolic Analysis of Relay and Swit ching
Circuit s (1938)’. Digit al design since t hat t ime has been pret t y much st andard and advanced,
following Boole’s and Shannon’s fundament als, wit h added refinement s here and t here as new
knowledge has been uneart hed and more exot ic logic devices have been developed.
Digit al design is t he field of st udy r elat ing t he adopt at ion of Logic concept s t o t he design
of r ecognizable, r ealizable, and r eliable degit al har dwar e.
When we begin st udy of logic, digit al logic, binar y syst ems, swit ching cir cuit s, or any
ot her field of st udy t hat can be classified as being r elat ed t o digit al design, we must concer n
our selves wit h lear ning some philosophical pr emises fr om which we must launch our st udies.
In or der t o r each a desir able t heor et ical, as well as concept ual, under st anding of digit al
design, you must gr asp some fundament al definit ions and insight giving concept s.
Gener ally speaking, being involved in digit al design is dealing in “LOGIC” a t er m t hat
cer t ainly needs some definit ion. LOGIC, by definit ion, is a process of classifying information.
Information is intelligence related to ideas, meanings, and actions which can be processed or
transformed into other forms. For example, NEWS is infor mat ion by vir t ue of t he fact t hat
it is int elligence r elat ed t o ACTIONS, be it good news or bad news. News can be hear d, r ead,
seen or even felt or any combinat ion of all four, indicat ing t he possibilit y of it s t r ansfor mat ion
int o differ ent for ms.
“BINARY LOGIC,” or t wo-valued logic, is a process of classifying information into two
classes. Tr adit ionally, binar y ar gument s, or t hat infor mat ion which can be definit ely classified
as t wo valued, has been deliver ed eit her TRUE or FALSE. Thus, t he Boolean var iable is
unlike t he algebr aic var iables of t he field of r eal number s in t hat any Boolean var iable can
t ake on only t wo values, the TRUE or t he FALSE. Tr adit ionally, (High or Low-Asser t ed or
Not Asser t ed) it is st andar d t o use t he shor t hand symbols 1 for TRUE and 0 for t he FALSE.
2.1 TRUTH TABLE
A Boolean var iable can t ake on only t wo values, not an infinit e number as, t he var iable
of t he r eal number syst em, can. This basic differ ence allows us t o illust r at e all possible logic
condit ions of a Boolean var iable or a collect ion of Boolean var iables using a finit e t abuler
63
2
CHAPTER
DIGITAL DESIGN FUNDAMENTALS—
BOOLEAN ALGEBRA AND LOGIC GATES
64 S witching Theory
format called a ‘t rut h-t able’. Furt her, t he nont r ivial decisions in digit al design ar e based on
mor e t han one-t wo valued var iable. Thus, if an out put is t o be complet ely specified as a
funct ion of t wo input s, t her e ar e four input combinat ions t hat must be consider ed. If t her e
ar e t hr ee input s, t hen eight combinat ions must be consider ed and fr om t his we see t hat n
input s will r equir e 2
n
combinat ions t o be consider ed.
A TRUTH-TABLE as suggest ed is a t abular or gr aphical t echnique for list ing all possible
combinat ions of input var iables, ar gument s, or what ever t hey may be called, in a ver t ical
or der, list ing each input combinat ion one r ow at a t ime (Table 2.1). When ever y possible
combinat ion is r ecor ded, each combinat ion can be st udied t o det er mine whet her t he ‘out put ’
or ‘combined int er act ion’ of t hat combinat ion should be ASSERTED or NOT-ASSERTED. Of
cour se t he infor mat ion used t o det er mine t he combined int er act ion or out put must come fr om
st udying ar gument s of t he logic pr oblem. For example
(i) Let we have a TV t hat oper at es wit h a swit ch. The TV, becomes on or off wit h t he
swit ch on or off r espect ively.
Table 2.1(a)
True
High ASSERTED
Low NOT ASSERTED
I/P
Switch
O/P
TV
Off
On
0
1
Off
On
0
1
False
(ii) Let we have a TV t hat oper at es wit h t wo swit ches. When bot h t he swit ches ar e
‘ON’ t hen only TV becomes ‘ON’ and in all ot her cases TV is ‘Off ’.
Table 2.1(b)
S .1 S .2 TV
0 0 0 OFF
0 1 0 OFF
1 0 0 OFF
1 1 1 ON
(iii) Let t he TV oper at e wit h t hr ee swit ches. The condit ion now is t hat when at least
t wo swit ches ar e ‘ON’ t he TV becomes ‘ON’ and in all ot her condit ions ‘TV’ is ‘OFF’.
Table 2.1(c)
S .1 S .2 S .3 TV
0 0 0 0 OFF
0 1 0 0 OFF
0 1 0 0 OFF
0 1 0 1 ON
1 0 0 0 OFF
1 0 1 1 ON
1 1 0 1 ON
1 1 1 0 OFF
Table 2.1(a) illust r at es t he use of a one var iable T.T. and how t he out put or combined
int er act ion is manually list ed t o t he r ight of each possible combinat ion. Table 2.1(b) and Table
2.1(c) show t he st andar d for m for t wo and t hr ee var iable t r ut h-t ables. In r eview, what is
Digital Design Fundamentals–Boolean Algebra and Logic Gates 65
suggest ed her e is t hat aft er all t he input var iables have been ident ified, and all t he possible
combinat ions of t hese var iables have been list ed in t he t r ut h-t able on t he left , t hen each r ow
should be st udied t o det er mine what out put or combined int er act ion is desir ed for t hat input
combinat ion. Fur ht er, not e t hat t he input combinat ions ar e list ed in ascending or der, st ar t ing
wit h t he binar y equivalent of zer o. The TRUTH-TABLE also allows us t o est ablish or pr ove
Boolean ident it ies wit hout det ailed mat hemat ical pr oofs, as will be shown lat t er.
2.2 AXIOMATIC SYSTEMS AND BOOLEAN ALG EBRA
In chapt er 1 we have discussed t he AND, OR, and INVERTER funct ions and st at ed t hat
it can be pr oven t hat t hese funct ions make up a sufficient set t o define a t wo valued Boolean
Algebr a. Now we int r oduce some for mal t r eat ment t o t his t wo-valued Boolean algebr a.
Axio m a tic Sy ste m s
Axiomat ic syst ems are founded on some fundament al st at ement s reffered t o as ‘axioms’
and ‘post ulat es.’ As you delve deeper into the origin of axioms and postualtes, you find t hese
t o be predict ed on a set of undefined object s t hat are accept ed on fait h.
Axioms or post ulat es ar e st at ement s t hat make up t he fr amewor k fr om which new
syst ems can be developed. They ar e t he basis fr om which t heor ems and t he pr oofs of t hese
t heor ems ar e der ived. For example, proofs are justified on the basis of a more primitive proof.
Thus, we use t he st at ement —‘From this we justify this’. Again, we find a pr ocess t hat is based
on some point for which t her e exist no fur ht er pr imit ive pr oofs. Hence, we need a st ar t ing
point and t hat st ar t ing point is a set of axioms or post ulat es.
Axioms ar e for mulat ed by combining int elligence and empir ical evidence and should have
some basic pr oper t ies. These ar e:
1. They ar e st at ement s about a set of undefined object s.
2. They must be consist ent , t hat is, t hey must not be self-cont r adict or y.
3. They should be simple but useful, t hat is, not lengt hy or complex.
4. They should be independent , t hat is, t hese st at ement s should not be int er dependent .
The st udy of axiomat ic syst ems r elat ed t o logic mot ivat ed t he cr eat ion of t he set of
post ulat es known as t he ‘HUNTINGTON POSTULATES’. E.V. Hunt igt on (1904) for mulat ed
t his set of post ulat es t hat have t he basic pr oper t ies descr ibed desir able, consist ant , simple and
independent . These post ulat es as set for t h can be used t o evaluat e pr oposed syst ems and
t hose syst ems t hat meet t he cr it er ia set for t h by t hese posut lat es become known as Hunt igt on
Syst em. Fur t her, once a pr oposed syst em meet s t he cr it er ia set for t h by t he Hunt ingt on
Post ulat es, aut omat ically all t heor ems and pr oper t ies r elat ed t o ot her Hunt igt on syst ems
become immediat ely applicable t o t he new syst em.
Thus, we pr opose a Boolean algebr a and t est it wit h t he Hunt igt on post ulat es t o det er -
mine it s st r uct ur e. We do t his so t hat we can ut ilize t he t heor ems and pr oper it ies of ot her
Hunt igt on syst em for a new syst em t hat is defined over a set of volt ge levels and har dwar e
oper at or s. Boolean algebr a, like ot her axiomat ic syst ems, is based on sever al oper at or s de-
fined over a set of undefined element s. A SET is any collect ion of element s having some
common pr oper t y; and t hese element s need not be defined. The set of element s we will be
dealing wit h is {0, 1}. The 0 and 1, as far as we ar e concer ned, ar e some special symbols and
have no numer ical cannot at ion what soever. They ar e simply some object s we ar e going t o
make some st at ement s about . An oper at ion (., +) is defined as a r ule defining t he r esult s of
an oper at ion on t wo element s of t he set . Becuase t hese oper at or s oper at e on t wo element s,
t hey ar e commonly r eflect ed t o as “binar y oper at or s”.
66 S witching Theory
2.2.1 Hunting ton’s Postula te s
1. A set of element s S is closed wit h respect t o an operat or if for every pair of element s
in S t he operat or specifies a unique result (element ) which is also in t he set S.
or
For the operator + the result of A + B must be found in S if A and B are in S; and for
the operator t he result of A. B must also be found in S if A and B are elements in S.
2(a) Ther e exist s an element 0 in S such t hat for every A in S, A + 0 = A.
2(b) Ther e exist s an element 1 in S such t hat for every A in S, A.1 = A.
3(a) A + B = B + A
3(b) A. B = B . A
4(a) A + (B . C) = (A + B) . (A + C)
4(b) A . (B + C) = (A . B) + (A . C)
5. For every element A in S, there exists an element A′ such that
A. A = 0 and A + A = 1
6. Ther e exist at least t wo element s A and B in S such t hat A is not equivalent t o B.
Ther efor e, if we pr opose t he following t wo values. Boolean algebr a syst em, t hat is, if we
define t he set S = {0, 1} and pr escr ibe t he r ules for
.
, + and INVERTER as follows:
Rules for “ . ” Rules for “+”
. 0 1 A B A.B + 0 1 A B A + B
0 0 0 or 0 0 0 0 0 1 or 0 0 0
1 0 1 0 1 0 1 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1
INVERT FUNCTION (COMPLEMENT)
A A′
0 1
1 0
and t est our syst em wit h post ulat es, we find
1. Closur e is obvious—no r esult s ot her t han t he 0 and 1 ar e defined.
2. Fr om t he t ables (a) 0 + 0 = 0 0 + 1 = 1 + 0 = 1
(b) 1.1 = 1 1.0 = 0.1 = 0
3. The commut at ive laws ar e obvious by t he symmet r y of t he oper at or t ables.
4(a) The dist r ibut ive law can be pr oven by a TRUTH-TABLE.
A B C B + C A.(B + C) A.B A.C (A.B) + (A.C)
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1
U
V
W
Commut at ive Law
U
V
W
Dist r ibut ive Law
Digital Design Fundamentals–Boolean Algebra and Logic Gates 67
4(b) Can be shown by a similar t able.
5. Fr om t he INVERTER funct ion t able
(COMPLEMENT)
1. 1 = 1.0 = 0,
0. 0 = 0.1 = 0
1 + 1 = 1 + 0 = 1,
0 + 0 = 0 + 1 = 1
6. It is obvious t hat t he set S = {0, 1} fulfills t he minimum r equir ement s of having at
least t wo element s where 0 1. ≠
Fr om t his st udy t he following post ulat es can be list ed below:
Table 2.2.1
Post ulat e 2 (a) A + 0 = A (b) A.1 = A Int er sect ion Law
Post ulat e 3 (a) A + B = B + A (b) A.B = B.A Commut at ing Law
Post ulat e 4 (a) A(B + C) = AB + AC (b) A + BC = (A + B) (A + C) Dist r ibut ive Law
Post ulat e 5 (a) A +
A
= 1 (b) A.A′ = 0 Complement s Law
We have just est ablished a t wo valued Boolean algebr a having a set of t wo element s, 1
and 0, t wo binar y oper at or s wit h oper at ion r ules equivalent t o t he AND or OR oper at ions, and
a complement oper at or equivalent t o t he NOT oper at or. Thus, Boolean algebr a has been
defined in a for mal mat hemat ical manner and has been shown t o be equivalent t o t he binar y
logic pr esent ed in Chapt er 1. The pr esent at ion is helpful in under st anding t he applicat ion of
Boolean algebr a in gat e t ype cir cuit s. The for mal pr esent at ion is necessar y for developing t he
t heor ems and pr oper t ies of t he algebr aic syst em.
2.2.2 Ba sic The ore ms a nd Prop e rtie s of Boole a n Alg e b ra
Duality. The Hunt ingt on post ulat es have been list ed in pair s and designat ed by par t (a)
and (b) in Table 2.2.2. One part may be obtained from other if the binary operators (+ and .)
and ident it y element s (0 and 1) ar e int er changed. This impor t ant pr oper t y of Boolean algebr a
is called t he dualit y pr inciple. It st at es t hat ever y algebr aic expr ession deducible fr om t he
post ulat es of Boolean algebr a r emain valid if t he oper at or s and ident it y element s ar e int er -
changed. In a t wo valued Boolean algebr a, t he ident it y element s and t he element s of t he set
ar e same: 1 and 0.
Basic Theorems. Table 2.2.2 list s six t heor ems of Boolean algebr a. The t heor ems, like t he
post ulat es, ar e list ed in pair s; each r elat ion is t he dual of t he one pair ed wit h it . The
post ulat es ar e basic axioms of t he algebr aic st r uct ur e and need no pr oof. The t heor ems must
be pr oven fr om t he post ulat es.
Table 2.2.2 Theorems of Boolean Algebra
Theor em
1. (a) A + A = A (b) A.A = A Taut ology Law
2. (a) A + 1 = 1 (b) A.0 = 0 Union Law
3. (A′)′ = A Involut ion Law
4. (a) A + (B + C) = (A + B) + C (b) A.(B.C) = (A.B).C Associat ive Law
5. (a) (A + B)′ = A′B′ (b) (A.B)′ = A′ + B′ De Mor gan’s Law
68 S witching Theory
6. (a) A + AB = A (b) A(A + B) = A Absorpt ion Law
7. (a) A + A′B = A + B (b) A(A′ + B) = AB
8. (a) AB + AB′ = A (b) (A + B) (A + B′) = A Logical adjancy
9. (a) AB + A′C + BC = AB + A′C (b) (A + B) (A′ + C) (B + C) = (A + B)
Consensus Law
The pr oofs of t he t heor em ar e pr esent ed below. At t he r ight is list ed t he number of
post ulat e which just ifies each st ep of pr oof.
Theor em 1(a) A + A = A
A + A = (A + A).1 by post ulat e 2(b)
= (A + A) (A + A′) 5(a)
= A + AA′ 4(b)
= A + 0 5(b)
= A 2(a)
Theor em 1(b) A.A = A.
A.A = A.A + 0 by post ulat e 2(a)
= A.A + A.A′ 5(b)
= A(A + A′) 4(a)
= A.1 5(a)
= A 2(b)
Not e t hat t heor em 1(b) is t he dual of t heor em 1(a) and t hat each st ep t he pr oof in par t
(b) is t he dual of par t (a). Any dual t heor em can be similar ly der ived fr om t he pr oof of it s
cor r esponding pair.
Theor em 2(a) A + A = 1
A + 1 = 1.(A + 1) by post ulat e 2(b)
= (A + A′) (A + 1) 5(a)
= A + A′.1 4(b)
= A + A′ 2(b)
= 1 5(a)
Theor em 2(b) A.0 = 0 by dualit y.
Theor em 3. (A′)′ = A Fr om post ulat e 5, we have
A + A′ = 1 and A.A′ = 0, which defines t he complement of A. The complement of A′ is
A and is also (A′)′. Ther efor e, since t he complement is unique, we have t hat (A′)′ = A.
Theor em 4(a) A + (B + C) = (A + B) + C
We can pr ove t his by per fect induct ion met hod shown in t able below:
A B C (B + C) A + (B + C) (A + B) (A + B) + C
0 0 0 0 0 0 0
0 0 1 1 1 0 1
0 1 0 1 1 1 1
0 1 1 1 1 1 1
(Contd.)...
Digital Design Fundamentals–Boolean Algebra and Logic Gates 69
A B C (B + C) A + (B + C) (A + B) (A + B) + C
1 0 0 0 1 1 1
1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1
We can obser ve t hat A + (B + C) = (A + B) + C
*Theor em 4(b)—can be pr oved in similar fashion.
*Theor em 5(a) and 5(b)—can also be pr oved by per fect induct ion met hod.
Theor em 6(a) A + AB = A
A + AB = A (1 + B)
= A (1)
= A
6(b) A.(A + B) = A By dualit y.
Theor em 7(a) A + A′B = A + B
A + A′B = A.1 + A′B
= A (B + B′) + A′B
= AB + AB′ + A′B
= AB + AB + AB′ + A′B
= A(B + B′) + B(A + A′)
= A + B.
7(b) A.(A′ + B) = A.B By dualit y.
Theor em 8(a) AB + AB′ = A
AB + AB′ = A(B +B′)
= A
8(b) (A + B) . (A + B′) = A By dualit y.
Theor em 9(a) AB + A′C + BC = AB + A′C
AB + A′C + BC = AB + A′C + BC(A + A′)
= AB + A′C + ABC + A′BC
= AB (1 + C) + A′C (1 + B)
= AB + A′C
9(b) (A + B) (A′ + C) (B + C) = (A + B) (A′ + C) By dualit y.
2.3 BO O LEAN FUNC TIO NS
A binar y var iable can t ake t he value of 0 or 1. A Boolean funct ion is an expr ession for med
wit h binar y var iable, t he t wo binar y oper at or s OR and AND, t he unar y oper at or NOT,
par ant heses and an equal sign. For a given value of t he var iables, t he funct ion can be eit her
0 or 1. Consider, for example, t he Boolean funct ion
F
1
= xy′z
*The pr oof of 4(b), 5(a) and 5(b) is left as an exer cise for t he r eader.
70 S witching Theory
The function F is equal to 1 when x = 1, y = 0 and z = 1; ot herwise F = 0. This is an example
of a Boolean funct ion represent ed as an algebraic expression. A Boolean funct ion may also be
represent ed in a t rut h t able. To represent a funct ion in a t rut h t able, we need a list of t he 2
n
combinations of 1’s and 0’s of n binary variables, and a column showing t he combinat ions for
which t he funct ion is equal t o 1 or 0 as discussed previously. As shown in Table 2.3, there
are eight possible dist inct combinat ion for assigning bit s t o t hree variables. The t able shows
that the function F is euqal to 1 only when x = 1, y = 0 and z = 1 and equal t o 0 ot herwise.
Consider now t he funct ion
F
2
= x′y′z + x′yz + xy′
F
2
= 1 if x = 0, y = 0, z = 1 or
x = 0, y = 1, z = 1 or
x = 1, y = 0, z = 0 or
x = 1, y = 0, z = 1
F
2
= 0, ot her wise.
Table 2.3
x y z F
1
F
2
F
3
0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 0 0 0
0 1 1 0 1 1
1 0 0 0 1 1
1 0 1 1 1 1
1 1 0 0 0 0
1 1 1 0 0 0
The number of r ows in t he t able is 2
n
, where n is t he number of binar y var iables in t he
funct ion.
The quest ion now ar ises, Is an algebr aic expr ession of a given Boolean funct ion unique?
Or, is it possible t o find t wo algebr aic expr essions t hat specify t he same funct ion? The answer
is yes. Consider for example a t hir d funct ion.
F
3
= xy′ + x′z
F
3
= 1 if x = 1, y = 0, z = 0 or
x = 1, y = 0, z = 1 or
x = 0, y = 0, z = 1 or
x = 0, y = 1, z = 1
F
3
= 0, ot her wise.
Fr om t able, we find t hat F
3
is same as F
2
since bot h have ident ical 1’s and 0’s for each
combinat ion of values of t he t hr ee binar y var iables. In gener al, t wo funct ions of n binar y
var iables ar e said t o be equal if t hey have t he same value for all possible 2
n
combinat ions of
the n var iables.
As a mat t er of fact , t he manipulat ion of Boolean algebr a is applied most ly t o t he pr oblem
of finding simpler expr essions for t he same funct ion.
Digital Design Fundamentals–Boolean Algebra and Logic Gates 71
2.3.1 Tra nsforma tion of Boole a n Func tion into Log ic Dia g ra m
A Boolean funct ion may be t r ansfor med fr om an algebr aic expr esion int o a logic diagr am
composed of AND, OR and NOT gat es. Now we shall implement t he t hr ee funct ions discussed
above as shown in Fig. 2.3.1.
• Her e we ar e using inver t er s (NOT gat es) for complement ing a single var iable. In
gener al however, it is assumed t hat we have bot h t he nor mal and complement
for ms available.
• There is an AND gat e for each pr oduct t er m in t he expr ession.
• An OR gat e is used t o combine (seen) t wo or mor e t er ms.
F
1
x
z
y
x
z
y
x
z
y
F
2
F
3
( ) a
( ) b
( ) c
Fi g. 2.3.1 (a, b, c)
Fr om t he diagr ams, it is obvious t hat t he implement at ion of F
3
r equir es fewer gat es and
fewer input s t han F
2
. Since F
3
and F
2
ar e equal Boolean funct ions, it is mor e economical t o
implement F
3
for m t han t he F
2
for m. To find simpler cir cuit s, we must know how t o manipu-
lat e Boolean funct ions t o obt ain equal and simpler expr ession. These simplificat ion (or mini-
mizat ion) t echniques will be r elat ed in det ail in next chapt er.
2.3.2 C omp le me nt of a Func tion
The complement of a funct ion F is F′ and is obt ained fr om an int er change of 0’s for 1’s
... and 1’s for 0’s in t he value of F. The complement of a funct ion may be der ived algebr aically
t hr ough De Mor gan’s t heor em. De Mor gan’s t heor em can be ext ended t o t hr ee or mor e
var iables. The t hr ee-var iable for m of t he De Mor gan’s t heor em is der ived below:
(A + B + C)′ = (A + X)′ Let B + C = X
= A′X′ by t heor em 5(a)
= A′.(B + C)′ subst it ut ing B + C = X
= A′.(B′C′) t heor em 5(a)
= A′B′C′ t heor em 4(a)
72 S witching Theory
This t heor em can be gener alized as
(A + B + C + D + ... F)′ = A′B′C′D′....F′
and it s DUAL
(ABCD .... F)′ = A′ + B′ + C′ + D′ + ... + F′
The gener alized for m of De Mor gan’s t heor em st at es t hat t he complement of a funct ion
is obt ained by int er chaning AND and OR oper at or s and complement ing each lit er al.
Example. Determine the complements of the following function:
F
1
= AB′ + C′D
Soluti on. F
1
= AB′ + C′D
F
1
′ = (AB′ + C′D)′
= (AB′)′ . (C′D)′
= (A′ + B) . (C + D′)
2.4 REPRESENTATIO N O F BO O LEAN FUNC TIO NS
Boolean funct ions (logical funct ions) ar e gener ally expr essed in t er ms of logical var i-
ables. Values t aken on by t he logical funct ions and logical var iables ar e in t he binar y for m.
Any logical var iable can t ake on only one of t he t wo values 0 and 1 or any logical var iable
(binar y var iable) may appear eit her in it s nor mal for m (A) or in it s complement ed for m (A′).
As we will see shor t ly lat t er t hat an ar bit r ar y logic funct ion can be expr essed in t he
following for ms:
(i) Sum of Pr oduct s (SOP)
(ii) Pr oduct of Sums (POS)
Produc t Te rm
The AND funct ion is r effer ed t o as pr oduct . The logical pr oduct of sever al var iables on
which a funct ion depends is consider ed t o be a pr oduct t er m. The var iables in a pr oduct t er m
can appear eit her in complement ed or uncomplement ed (nor mal) for m. For example AB′C is
a pr oduct for m.
Sum Te rm
The OR funct ion is gener ally used t o r efer a sum. The logical sum of sever al var iables
on which a funct ion depends is consider ed t o be a sum t er m. Var iables in a sum t er m also
can appear eit her in nor mal or complement ed for m. For example A + B + C′, is a sum
t er m.
Sum of Prod uc ts ( SO P)
The logic sum of t wo or mor e pr oduct t er ms is called a ‘sum of pr oduct ’ expr ession. It
is basically on OR oper at ion of AND oper at ed var iables such as F = A′B + B′C + A′BC.
Prod uc t of Sums ( PO S)
The logical product of two or more sum terms is called a ‘product of sum’ expression. It is
basically an AND operation of OR operated variables such as F = (A′ + B). (B′ + C) . (A′ + B + C).
Digital Design Fundamentals–Boolean Algebra and Logic Gates 73
2.4.1 M inte rm a nd M a xte rm Re a liza tion
Consider t wo binary variables A and B combined wit h an AND operat ion. Since each
var iable may appear in eit her for m (nor mal or complement ed), t her e ar e four combinat ions,
t hat ar e possible—AB, A′B, AB′, A′B′.
Each of t hese four AND t er ms r epr esent one of t he four dist inct combinat ions and is
called a mint er m, or a st andar d pr oduct or fundament al pr oduct .
Now consider t hr ee var iable—A, B and C. For a t hr ee var iable funct ion t her e ar e 8
mint er ms as shown in Table 2.4.1. (Since t her e ar e 8 combinat ions possible). The binar y
number s fr om 0 t o 7 ar e list ed under t hr ee var ibles. Each mint er m is obt ained fr om an AND
t er m of t he t hr ee var iables, wit h each var iable being pr imed (complement ed for m) if t he
cor r esponding bit of t he binar y number is a 0 and unpr imed (nor mal for m) if a 1. The
symbol is m
j
, where j denot es t he decimal equivalent of t he binar y number of t he mint er m
disignat ed.
In a similar manner, n variables can be combined t o form 2
n
mint erms. The 2
n
different
mint erms may be det ermined by a met hod similar t o t he one shown in t able for t hree variables.
Similar ly n var iables for ming an OR t er m, wit h each var iable being pr imed or unpr imed,
pr ovide 2
n
possible combinat ions, called maxt er ms or st andar d sums.
Each maxt er m is obt ained fr om an OR t er m of t he n var iables, wit h each var iable being
unpr imed if t he cor r esponding bit is a 0 and pr imed if a 1.
It is int er st ing t o not e t hat each maxt er m is t he complement of it s cor r esponding
mint er m and vice ver sa.
Now we have r eached t o a level wher e we ar e able t o under st and t wo ver y impor t ant
pr oper t ies of Boolean algebr a t hr ough an example. The example is same as we have alr eady
discussed in Sect ion (2.1) Truth Table.
Table 2.4.1 Mi nterm and Maxterm for three bi nary vari ables
MINTERMS MAXTERMS
Decimal Eqt. A B C Term Designation Term Designation
0 0 0 0 A′B′C′ m
0
A + B + C M
0
1 0 0 1 A′B′C m
1
A + B + C′ M
1
2 0 1 0 A′BC′ m
2
A + B′ + C M
2
3 0 1 1 A′BC m
3
A + B′ + C′ M
3
4 1 0 0 AB′C′ m
4
A′ + B + C M
4
5 1 0 1 AB′C m
5
A′ + B + C′ M
5
6 1 1 0 ABC′ m
6
A′ + B′ + C M
6
7 1 1 1 ABC m
7
A′ + B′ + C M
7
Let we have a TV t hat is connect ed wit h t hr ee swit ches. TV becomes ‘ON’ only when
at least t wo of t he t hr ee swit ches ar e ‘ON’ (or high) and in all ot her condit ions TV is ‘OFF’
(or low).
Let t he t hr ee swit ches ar e r epr esent ed by t hr ee var iable A, B and C. The out put of TV
is r epr esent ed by F. Since t her e ar e t hr ee swit ches (t hr ee var iables), t her e ar e 8 dist inct
combinat ions possible t hat is shown in TT.
74 S witching Theory
SWITCHES TV (o/ p) HIGH (ON) → 1
A B C F LOW (OFF) → 0.
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
The TV becomes ‘ON’ at four combinat ions. These ar e 011, 101, 110 and 111. We can say
t hat F is det er mined by expr essing t he combinat ions A′BC, ABC′ and ABC. Since each of t hese
mint er ms r esult in F = 1, we should have
F = A′BC + AB′C + ABC′ + ABC
= m
3
+ m
5
+ m
6
+ m
7
.
This demonst r at es an impor t ant pr oper t y of Boolean algebr a t hat ‘Any Boolean funct ion
can be expr essed as sum of mint er ms or as ‘Sum of pr oduct ’. However, t her e is no guar ant ee
t hat t his SOP expr ession will be a minimal expr ession. In ot her wor ds, SOP expr essions ar e
likely t o have r eduandancies t hat lead t o syst ems which r equir es mor e har dwar e t hat is
necessar y. This is wher e t he r ole of t heor ems and ot her r educt ion t echniques come int o play
as will be shown in next chapt er.
As ment ioned, any TRUTH-TABLE INPUT/OUTPUT specificat ions can be expr essed in
a SOP expr ession. To facilit at e t his a shor t hand symbology has been developed t o specify such
expr essions. This is done by giving each r ow (MINTERM) in t he TRUTH-TABLE a decimal
number t hat is equivalent t o t he binar y code of t hat r ow, and specifying t he expr ession t hus:
F = Σ(m
3
, m
5
, m
6
, m
7
)
which r eads: F = t he sum-of-pr oduct s of MINTERMS 3, 5, 6 and 7. This shor t hand not at ion
can be fur ht er shor t end by t he following accept able symbology:
F = Σ(3, 5, 6, 7)
Expr ession such as t hese ser ve as gr eat aids t o t he simplificat ion pr ocess, as shown in
next chapt er.
Now, cont inuing wit h t he same example, consider t he complement of Boolean funct ion
t hat can be r ead fr om Tr ut h-t able by for ming a mint er m for each combinat ion t hat pr oduces
0 in t he funct ion and by 0Ring
F ′ = A′B′C′ + A′B′C + A′BC′ + AB′C
Now, if we t ake t he complement of F′, we get F.
⇒ F = (A + B + C) . (A + B + C′) . (A + B′ + C) (A′ + B + C)
= M
0
M
1
M
2
M
4
This demonst r at es a second impor t ant pr oper t y of t he Boolean algebr a t hat ‘Any Boolean
funct ion can be expr essed as pr oduct -of-maxt er ms or as pr oduct of sums’. The pr ocedur e for
Digital Design Fundamentals–Boolean Algebra and Logic Gates 75
obt aining t he pr oduct of maxt er ms dir ect ly fr om Tr ut h-t able is as; For m a maxt er m for
each combinat ion of t he var iables t hat pr oduces a 0 in t he funct ion, and t hen for m t he AND
of all t hose funct ions. Out put will be equal t o F because in case of maxt er ms 0 is unpr imed.
The shor t end symbology for POS expr essions is as follows—
F = II(M
0
, M
1
, M
2
, M
4
)
or F = II(0, 1, 2, 4)
Boolean funct ions expr essed as sum of mint er ms (sum of pr oduct t er ms) SOP or pr oduct
of maxt er ms, (Pr oduct of sum t er ms) POS ar e said t o be in CANONICAL for m or STANDARD
for m.
2.4.2 Sta nd a rd Forms
We have seen t hat for n binar y var iables, we can obt ain 2
n
dist inct mint er sms, and t hat
any Boolean funct ion can be expr essed as a sum of mint er ms or pr oduct of maxt er ms. It is
somet imes convenient t o expr ess t he Boolean funct ion in one of it s st andar d for m (SOP or
POS). If not in t his for m, it can me made as follows:
1. Sum of Product. Fir st we expand t he expr ession int o a sum of AND t er ms. Each
t er m is t hen inspect ed t o see if it cont ains all t he var iable. If it misses one or mor e
var iables, it is ANDed wit h an expr ession such as A + A′, where A is one of t he missing
var iables.
Example. Express the Boolean function F = x + y′z in a sum of product (sum of minterms)
form.
Solution. The funct ion has t hr ee var iables x, y and z. The first t erm x is missing t wo
var iables; t her efor e
x = x (y + y′) = xy + xy
This is st ill missing one var iable:
x = xy (z + z′) + xy′ (z + z′)
= xyz + xyz′ + xy′z + xy′z′
The second t erm y′z is missing one var iable:
y′z = y′z (x + x′) = xy′z + x′y′z
Combining all t er ms, we have
F = x + y′z = xyz + xyz′ + xy′z + xy′z′ + xy′z + x′y′z
But xy′z appear s t wice, and accor ding t o t heor em 1 (A + A = A), it is possible t o r emove
one of t hem. Rear r anging t he min t er ms in ascending or der, we have:
F = x′y′z + xy′z′ + xy′z + xyz′ + xyz
= m
1
+ m
4
+ m
5
+ m
6
+ m
7
.
⇒ F(x, y, z) = Σ(1, 4, 5, 6, 7)
An alt er nat ive met hod for dr iving pr oduct t er ms (mint er ms) is t o make a T.T. dir ect ly
fr om funct ion. F = x + y′z from T.T., we can see dir ect ly five mint er ms wher e t he value of
funct ion is equal t o 1. Thus,
76 S witching Theory
F(x, y, z) = Σ(1, 4, 5, 6, 7)
x y z F = x + y′z
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
2. Product of Sums. To expr ess t he Boolean funct ion as pr oduct of sums, it must fir st
be br ought int o a for m of OR t er ms. This may be done by using t he dist r ibut ive law A + BC
= (A + B) . (A + C). Then any missing variable A in each OR t erm is 0Red wit h AA′.
Example. Express the Boolean function F = AB + A′C in a product of sum (product of
mixterm) form.
Solution. Fir st conver t t he funct ion int o OR t er ms using dist r ibut ive law.
F = AB + A′C = (AB + A′) (AB + C)
= (A + A′) (B + A′) (A + C) (B + C)
= (A′ + B) (A + C) (B + C)
The funct ion has t hr ee var iables A, B and C. Each OR t er m is missing one var iable
t her efor e:
A′ + B = A′ + B + CC′ = (A′ + B + C) (A′ + B + C′)
A + C = A + C + BB′ = (A + B + C) (A + B′ + C)
B + C = B + C + AA′ = (A + B + C) (A′ + B + C)
Combining all t hese t er ms and r emoving t hose t hat appear mor e t han once.
F = (A + B + C) (A + B′ + C) (A′ + B + C) (A′ + B + C′)
M
0
M
2
M
4
M
5
⇒ F(x, y, z) = II(0, 2, 4, 5)
An alt er nat ive met hod for der iving sum t er ms (maxt er ms) again is t o make a TT dir ect ly
fr om funct ion.
F = AB + A′C
From TT, we can see dir ect ly four maxt er ms wher e t he value of funct ion is equal t o 0.
Thus, F(A, B, C) = II(0, 2, 4, 5)
A B C F = AB + A′C
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
(Contd.)...
Digital Design Fundamentals–Boolean Algebra and Logic Gates 77
A B C F = AB + A′C
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
2.4.3 C onve rsion b e twe e n Sta nd a rd Forms
Consider t he t able shown in sect ion 2.4.1(b) t o help you est ablish t he r elat ionship be-
t ween t he MAXTERM and MINTERM number s.
Fr om t able we see t hat m
j
= M
j
or m
j
= m
j
An int erest ing point can be made in relat ionship bet ween MAXTERM list s and MINTERMS
list s. The subscr ipt number of t he t er ms in t he MAXTERM list cor r espond t o t he same
subscr ipt number s for MINTERMS t hat ar e not included in t he MINTERM list . Fr om t his we
can say t he following:
Give : II (Set of MAXTERM number s)
We know t hat t he funct ion der ived fr om t his list will yield pr ecisely t he same r esult as
t he following:
Σ(set of MINTERMS number s t hat ar e not included in t he MAXTERM list )
For example,
Given, F(A, B, C) = II(0, 1, 4, 6)
We know immediat ely t hat
F(A, B, C) = Σ(2, 3, 5, 7)
2.5 LOGIC GATES
I ntro d uc tio n
We have seen t hat t he foundat ion of logic design is seat ed in a well defined axiomat ic
syst em called Boolean algebra, which was shown t o be what is known as a “Hunt ingt on syst em”.
In t his axiomat ic syst em t he definit ion of AND and OR operat ors or funct ions was set fort h and
t hese were found t o be well defined operat ors having cert ain propert ies t hat allow us t o ext end
t heir definit ion t o Hardware applicat ions. These AND and OR operat ors, somet imes reffered t o
as connect ives, act ually suggest a funct ion t hat can be emulat ed by some H/w logic device. The
logic Hardware devices just ment ioned are commonly reffered t o as “gat es”.
Keep in mind t hat t he usage of “gat e” r efer s t o an act ual piece of Har dwar e wher e
“funct ion” or “oper at ion” r efer s t o a logic oper at or AND. On t he ot her hand, when we r efer
t o a “gat e” we ar e r effer ing dir ect ly t o a piece of har dwar e called a gat e. The main point t o
r emember is ‘Don’t confuse gat es wit h logic oper at or s’.
2.5.1 Positive a nd Ne g a tive Log ic De sig na tion
The binary signals at t he input s or out put s of any gat e can have one of t he t wo values except
during transistion. One signal levels represents logic 1 and the other logic 0. Since two signal
values are assigned t wo t o logic values, t here exist t wo different assignment s of signals t o logic.
78 S witching Theory
Logics 1 and 0 ar e gener ally r epr esent ed by differ ent volt age levels. Consider t he t wo
values of a binar y signal as shown in Fig. 2.5.1. One value must be higher t han t he ot her
since t he t wo values must be differ ent in or der t o dist inguish bet ween t hem. We designat e
t he higher volt age level by H and lower volt age level by L. Ther e ar e t wo choices for logic
values assignment . Choosing t he high-level (H) t o r epr esent logic 1 as shown in (a) defines
a posit ive logic syst em. Choosing t he low level L t o r epr esent logic-1 as shown in (b), defines
a negat ive logic syst em.
Logic
value
Signal
value
Logic
value
Signal
value
1
0
H
L
0
1
H
L
(a) Positive logic (b) Negative logic
Fi g. 2.5.1
The t er ms posit ive and negat ive ar e somewhat misleading since bot h signal values may
be posit ive or bot h may be negat ive. Ther efor e, it is not signal polar it y t hat det er mines t he
t ype of logic, but r at her t he assignment of logic values accor ding t o t he r elat ive amplit udes
of t he signals.
The effect of changing fr om one logic designat ion t o t he ot her equivalent t o complement -
ing t he logic funct ion because of t he pr inciple of dualit y of Boolean algebr a.
2.5.2 G a te De finition
A ‘gat e’ is defined as a mult i-input (> 2) har dwar e device t hat has a t wo-level out put . The
out put level (1–H/0–L) of t he gat e is a st r ict and r epeat able funct ion of t he t wo-level
(1–H/0–L) combinat ions applied t o it s input s. Fig. 2.5.2 shows a gener al model of a gat e.
n inputs, each of
which can take on
one of two levels
(HIGH/LOW)
Two level output that
is a strict function of
two-level input
combinations
Gate
(Hardware)
Fi g. 2.5.2 The gener al model of a gat e.
The t erm “logic” is usually used t o r efer t o a decision making pr ocess. A logic gat e, t hen,
is a cir cuit t hat can decide t o say yes or no at t he out put based upon input s.
We apply volt age as t he input t o any gat e, t her efor e t he Boolean (logic) 0 and 1 do not
r epr esent act ual number but inst ead r epr esent t he st at e of a volt age var iable or what is called
it s logic level. Somet imes logic 0 and logic 1 may be called as shown in t able below:
Table 2.5.2
Logic 0 Logic 1
False Tr ue
Off On
Low High
No Yes
Open swit ch Close swit ch
Digital Design Fundamentals–Boolean Algebra and Logic Gates 79
2.5.3 The AND Ga te
The AND gat e is somet imes called t he “all or not hing gat e”. To show t he AND gat e we
use t he logic symbol in Fig. 2.5.3(a). This is t he st andar d symbol t o memor ize and use fr om
now on for AND gat es.
Y output
A
B
Inputs
A
B
B A
SWITCHES
INPUTS
Y
OUTPUT
( ) a
( ) b
Fig. 2.5.3 (a) AND Gat e logic symbol. (b) Pract ical AND gat e cir cuit .
Now, let us consider Fig. 2.5.3(b). The AND gat e in t his figur e is connnect ed t o input
swit ches A and B. The out put indicat or is an LED. If a low volt age (Gr ound, GND) appear s
at input s, A and B, t hen t he out put LED is not bit . This sit uat ion is illust r at ed in t able ().
Line 1 indicat es t hat if t he input s ar e binar y 0 and 0, t hen t he out put will be binar y 0. Notice
that only binary 1s at bot h A and B will pr oduce a binar y 1 at t he out put .
Table 2.5.3 AND Truth Table
INPUTS OUTPUTS
A B Y
S witch Binary S witch Binary Light Binary
Voltage Voltage
Low 0 Low 0 No 0
Low 0 High 1 No 0
High 1 Low 0 No 0
High 1 High 1 Yes 1
It is a +5V compar ed t o GND appear ing at
A, B, or Y t hat is called a binar y 1 or a HIGH
volt age. A binar y 0, or Low volt age, is defined
as a GND volt age (near 0V compar ed t o GND)
appearing at A, B or Y. We are using positive
logic because it takes a positive +5V to produce
what we call a binary 1.
The t r ut h t able is said t o discr ibe t he AND
funct ion. The unique out put fr om t he AND gat e
is a HIGH only when all input s ar e HIGH.
Fig. 2.5.3 (c) shows t he ways t o expr ess
t hat input A is ANDed wit h input B t o pr oduce
output Y.
Boolean
Expression
Logic
Symbol
Truth
Table
A
B
Y
AND Symbol
A.B = Y

A
0
0
1
1
B
0
1
0
1
Y
0
0
0
1
Fig. 2.5.3 (c)
80 S witching Theory
Pulse d O p e ra tio n
In many applicat ions, t he input s t o a gat e may be volt age t hat change wit h t ime bet ween
t he t wo logic levels and ar e called as pulsed wavefor ms. In st udying t he pulsed oper at ion of
an AND gat e, we consider t he input s wit h r espect t o each ot her in or der t o det er mine t he
out put level at any given t ime. Following example illust r at es t his oper at ion:
Example. Determine the output Y from the AND gate for the given input waveform
shown in Fig. 2.5.3(d).
A
B
0 0 1 1
t
1
t
2
t
3
t
4
INPUTS
Y ? →
Fig. 2.5.3 (d)
Solution. The out put of an AND gat e is det er mined by r ealizing t hat it will be high only
when bot h input s ar e high at t he same t ime. For t he input s t he out put s is high only dur ing
t
3
per iod. In r emaining t imes, t he out put s is 0 as shown in Fig. 2.5.3(e).
0 0 1 0
t
1
t
2
t
3
t
4
OUTPUT Y →
Fig. 2.5.3 (e)
2.5.4 The OR Ga te
The OR gat e is somet imes called t he “any or all gat e”. To show t he OR gat e we use t he
logical symbol in Fig. 2.5.4(a).
Y output
A
B
INPUTS
A
B
B A
SWITCHES
INPUTS
Y
OUTPUT
( ) a
( ) b
Fig. 2.5.4 (a) OR gat e logic symbol. (b) Pr act ical OR gat e cir cuit .
A t r ut h-t able for t he ‘OR’ gat e is shown below accor ding t o Fig. 2.5.4(b). The t r ut h-t able
list s t he swit ch and light condit ions for t he OR gat e. The unique out put fr om t he OR gat e
is a LOW only when all input s ar e low. The out put column in Table (2.5.4) shows t hat only
t he fir st line gener at es a 0 while all ot her s ar e 1.
Digital Design Fundamentals–Boolean Algebra and Logic Gates 81
Table 2.5.4
INPUTS OUTPUTS
A B Y
S witch Binary S witch Binary Light Binary
Low 0 Low 0 No 0
Low 0 High 1 No 0
High 1 Low 0 No 0
High 1 High 1 Yes 1
Fig. 2.5.4(c) shows t he ways t o expr ess t hat input A is ORed wit h input B t o pr oduce
output Y.
Boolean
Expression
Logic
Symbol
Truth
Table
A
B
Y
OR Symbol

A + B = Y

A
0
0
1
1
B
0
1
0
1
Y
0
1
1
1
Fig. 2.5.4 (c)
Example. Determine the output Y from the OR gate for the given input waveform shown
in Fig. 2.5.4(d).
A
B
0 0 1
t
1
t
2
t
3
INPUTS
Y ? →
1 0 1
Fig. 2.5.4 (d)
Solution. The out put of an OR gat e is det er mined by r ealizing t hat it will be low only
when bot h input s ar e low at t he same t ime. For t he input s t he out put s is low only dur ing
period t
2
. In r emaining t ime out put is 1 as shown in Fig. 2.5.4(e).
1 0 1
t
1
t
2
t
3
OUTPUT Y →
Fig. 2.5.4 (e)
82 S witching Theory
We ar e now familiar wit h AND and OR gat es. At t his st age, t o illust r at e at least in par t
how a wor d st at ement can be for mulat ed int o a mat hemat ical st at ement (Boolean expr ession)
and t hen t o har dwar e net wor k, consider t he following example:
Example. Utkarsha will go to school if Anand and S awan go to school, or Anand and
Ayush go to school.
Solution. → This st at ement can be symbolized as a Boolean expr ession as follows:
U IF AAND S
U = (A . S)
AND
Symbol


+
OR
Symbol

(A . AY)
AND
Symbol

or
Utkarsha - U
Anand - A
Sawan - S
Ayush - AY
The next st ep is t o t r ansfor m t his Boolean expr ession int o a Har dwar e net wor k and t his
is where AND and OR gat es ar e used.
A
AY
S
U
1
2
A.S
A.AY
3
(A.S) + (A.AY)
The out put of gat e 1 is high only if bot h t he input s A and S ar e high (mean bot h Anand
and Sawan go t o school). This is t he fir st condit ion for Ut kar sha t o go t o school.
The out put of gat e 2 is high only if bot h t he input s A and A.Y ar e high (means bot h Anand
and Ayush go t o school). This is t he second condit ion for Ut kar sha t o go t o school.
Accor ding t o example at least one condit ion must be fullfilled in or der t hat Ut kar sha goes
t o school. The out put of gat e 3 is high when any of t he input t o gat e 3 is high means at least
one condit ion is fulfilled or bot h t he input s t o gat e 3 ar e high means bot h t he condit ions ar e
fulfilled.
The example also demonst r at es t hat Anand has t o go t o school in any condit ion ot her wise
Ut kar sha will not go t o school.
2.5.5 The Inve rte r a nd Buffe r
Since an Inver t er is a single input device, it per for ms no logic int er act ion funct ion
bet ween t wo var iables, and t o say t hat mer ely changing a volt age level const it ut e a logic
oper at ion would be misleading. Ther efor e we define it as an Inver t er funct ion r at her t han a
logic oper at or like t he AND and OR oper at or s. The NOT cir cuit per for ms t he basic logical
funct ion called inver sion or complement at ion. That is why, it is also known as Inver t er. The
NOT cir cuit has only input and one ouput . The pur pose of t his gat e is t o give an out put t hat
is not t he same as t he input . When a HIGH level is applied t o an inver t er, a LOW level appear s
at it s out put and vice ver sa. The logic symbol for t he inver t er is shown in Fig. 2.5.5(a).
If we wer e t o put in a logic at 1 and input
A in Fig. 2.5.5(a), we would get out t he oppo-
sit e, or a logical 0, at out put Y.
Y OUTPUT INPUT A
Y = A or A ′
Fig. 2.5.5 (a) A logic symbol and Boolean
expr ession for an inver t er.
Digital Design Fundamentals–Boolean Algebra and Logic Gates 83
The t r ut h-t able for t he inver t er is shown in Fig. 2.5.5(b). If t he volt age at t he input of
t he inver t er is LOW, t hen t he out put volt age is HIGH, if t he input volt age is HIGH, t hen t he
out put is LOW. We can say t hat out put is always negat ed. The terms “negat ed”, “comple-
ment ed” and “inver t ed”, t hen mean t he same t hings.
INPUT OUTPUT
A B
Voltages Binary Voltages Binary
LOW 0 HIGH 1
HIGH 1 LOW 0
Fig. 2.5.6 (b) Tr ut h-t able for an inver t er.
Now consider t he logic diagr am as shown in Fig. 2.5.5(c), t hat shows an ar r angement
wher e input A is r un t hr ough t wo inver t er s. Input A is fir st inver t ed t o pr oduce a “not A” (A)
and t hen inver t ed a second t ime for “double not A” (A) . In t er ms of binar y digit s, we find t hat
when t he input 1 is inver t ed t wice, we end up wit h or iginal digit . Ther efor e, we find A = A.
A A
⇒ A = A
INPUT
A
OUTPUT
Logical 1
INVERT
Logical 0
INVERT
Logical 1
Fig. 2.5.5 (c) Effect of double inver t ing.
The symbol shown in figur e is t hat of a non-inver t ing buffer /dr iver. A buffer pr oduces t he
t r ansfer funct ion but does not pr oduce any logical oper at ion, since t he binar y value of t he
ouput is equal t o t he binar y value of t he input . The cir cuit is used mer ely for power ampli-
ficat ion of t he signal and is equivalent t o t wo inver t er s connect ed in cascade. Fig. 2.5.5(e)
shows the T.T. for t he buffer.
A A
OUTPUT INPUT
Fig. 2.5.5 (d) Non-inver t ing buffer /dr iver logic symbol.
INPUT OUTPUT
A B
Voltages Binary Voltage Binary
HIGH 1 HIGH 1
LOW 0 LOW 0
Fig. 2.5.5 (e) Tr ut h t able for buffer.
Example. Determine the output Y from the inverter for the given input waveform shown
in Fig. (2.5.5 f).
0 1 0 1
t
1
t
2
t
3
t
4
INPUTS
1 1 0
t
5
t
6
t
7
Y ? →
A
Fig. 2.5.5 (f)
84 S witching Theory
Solution. The out put of an Inver t er is det er mined by r ealizing t hat it will be high when
input is low and it will be low when input is high.
1 0 1 0
t
1
t
2
t
3
t
4
0 0 1
t
5
t
6
t
7
OUTPUT Y →
2.5.6 O the r G a te s a nd The ir Func tions
The AND, OR, and t he inver t er ar e t he t hr ee basic cir cuit s t hat make up all digit al
cir cuit s. Now, it should pr ove int er est ing t o examine t he ot her 14 possible ouput specificat ion
(except AND and OR) for an ar bit r ar y t wo-input gat e.
Consider Table (2.5.6.)
Table 2.5.6: Input/Output speci fi cati ons for the 16 possi ble outputs deri ved from
two-i nput gates
A B GND F
1
F
2
F
3
F
4
F
5
F
6
F
7
F
8
F
9
F
10
F
11
F
12
F
13
F
14
+V
0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
↓ ↓ ↓ ↓ ↓ ↓
N E N A E N
O X A N X O
R O N D N R
R D O
R
Scanning t he t able for gat es t hat exhibit t he Boolean AND and OR oper at or, we see t hat
F
1
(NOR), F
7
(NAND), F
8
(AND) and F
14
(OR) ar e t he only out put s fr om gat es which manifest
the AND and OR oper at or s. We shall see very shortly that both NAND and NOR gates can
be used as AND and OR gates. Because of t his, t hey ar e found in int egr at ed cir cuit for m. All
t he r est ar e mor e complex and deemed unuseful for AND/OR implement at ion and ar e not
nor mally found in gat e for m, wit h t wo except ions. They ar e F
6
and F
9
. F
6
is t he Input /out put
specificat ion for a gat e called t he EXCLUSIVE OR gat e and F
9
is t he specificat ion for t he
COINCIDENCE, EQUIVALENCE, or EXNOR gat e, also r efer r ed t o as an EXCLUSIVE NOR.
2.5.7 Unive rsa l G a te s
NAND and NOR gates. The NAND and NOR gat es ar e widely used and ar e r eadily
available fr om most int egr at ed cir cuit manufact ur er s. A major r eason for t he widespr ead use
of t hese gat es is t hat t hey ar e bot h UNIVERS AL gates, univer sal in t he sense t hat bot h can
be used for AND oper at or s, OR oper at or s, as well as Inver t er. Thus, we see t hat a complex
digit al syst em can be complet ely synt hesized using only NAND gat es or NOR gat es.
The NAND Gate. The NAND gat e is a NOT AND, or an inver t ed AND funct ion. The
st andar d logic symbol for t he NAND gat e is shown in Fig. (2.5.7a). The lit t le inver t bubble
(small cir cle) on t he r ight end of t he symbol means t o inver t t he out put of AND.
Digital Design Fundamentals–Boolean Algebra and Logic Gates 85
A
B
Y
A
B
A.B
(A.B)′
INPUTS OUTPUTS
( ) a ( ) b
Fig. 2.5.7 (a) NAND gat e logic symbol (b) A Boolean expr ession for t he out put of a NAND gat e.
Figur e 2.5.7(b) shows a separ at e AND gat e and inver t er being used t o pr oduce t he NAND
logic funct ion. Also not ice t hat t he Boolean expr ession for t he AND gat e, (A.B) and t he NAND
(A.B)′ ar e shown on t he logic diagr am of Fig. 2.5.7(b).
The t r ut h-t able for t he NAND gat e is shown in Fig. 2.5.7(c). The t r ut h-t able for t he
NAND gat e is developed by inver t ing t he out put of t he AND gat e. ‘The unique out put fr om
t he NAND gat e is a LOW only when all input s ar e HIGH.
INPUT OUTPUT
A B AND NAND
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
Fig. 2.5.7 (c) Trut h-t able for AND and NAND gat es.
Fig. 2.5.7 (d) shows t he ways t o expr ess t hat input A is NANDed wit h input B yielding
output Y.
Boolean
Expression
Logic
Symbol
Truth
Table
A
B
Y
NOT Symbol
A
0
0
1
1
B
0
1
0
1
Y
1
1
1
0
A . B = Y
AND Symbol
or AB = Y
or (AB) = Y ′
Fig. 2.5.7 (d)
Example. Determine the output Y from the NAND gate from the given input waveform
shown in Fig. 2.6.7 (e).
A
B
0 1 0 1
t
1
t
2
t
3
t
4
INPUTS
Y
0 1 0 0
OUTPUT
?
Fig. 2.5.7 (e)
86 S witching Theory
Solution. The out put of NAND gat e is det er mined by r ealizing t hat it will be low only
when bot h t he input s ar e high and in all ot her condit ions it will be high. The ouput Y is
shown in Fig. 2.5.7(f).
1 0 1 1
t
1
t
2
t
3
t
4
OUTPUT Y →
Fig. 2.5.7 (f)
The NAND gate as a UNIVERSAL Gate
The char t in Fig. 2.5.7(g) shows how would you wir e NAND gat es t o cr eat e any of t he
ot her basic logic funct ions. The logic funct ion t o be per for med is list ed in t he left column of
t he t able; t he cust omar y symbol for t hat funct ion is list ed in t he cent er column. In t he r ight
column, is a symbol diagr am of how NAND gat es would be wir ed t o per for m t he logic
funct ion.
Logic
Function
Symbol Circuit using NAND gates only
Inverter
AND
OR
A
B
A A′
A.B
A
B
A + B
A
A′
A
B
A.B
A
B
A + B
Fig. 2.5.7 (g)
The NOR gate. The NOR gat e is act ually a NOT OR gat e or an inver t ed OR funct ion.
The st andar d logic symbol for t he NOR gat e is shown in Fig. 2.5.7(h)
A
B
Y
A
B
A + B
(A + B)′
INPUTS OUTPUTS
(h) (i)
Fi g. 2.5.7 (h) NOR gat e logic symbol (i) Boolean expr ession for t he out put of NOR gat e.
Not e t hat t he NOR symbol is an OR symbol wit h a small inver t bubble on t he r ight side.
The NOR funct ion is being per for med by an OR gat e and an inver t er in Fig. 2.5.7(i). The
Boolean funct ion for t he OR funct ion is shown (A + B), t he Boolean expr ession for t he final
NOR funct ion is (A + B).
The t r ut h-t able for t he NOR gat e is shown in Fig. 2.5.7(j). Not ice t hat t he NOR gat e
t r ut h t able is just t he complement of t he out put of t he OR gat e. The unique out put fr om t he
NOR gat e is a HIGH only when all input s ar e LOW.
Digital Design Fundamentals–Boolean Algebra and Logic Gates 87
INPUTS OUTPUTS
A B OR NOR
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0
Fig. 2.5.7 (j) Tr ut h-t able for OR and NOR gat es.
Figur e 2.5.7(k) shows t he ways t o expr ess t hat input A is ORed wit h input B yielding
output Y.
Boolean
Expression
Logic
Symbol
Truth
Table
A
B
Y
NOT Symbol
A
0
0
1
1
B
0
1
0
1
Y
1
0
0
0
A + B = Y
OR Symbol
or (A + B) = Y ′
Fig. 2.5.7 (k)
Example. Determine the output Y from the NOR gate from the given input waveform
shown in Fig. 2.5.7(l).
A
B
0 1 0 1
t
1
t
2
t
3
t
4
INPUTS
Y
0 1 0 0
OUTPUT
?
Fig. 2.5.7 (l)
Solution. The out put of NOR gat e is det er mined by r ealizing t hat it will be HIGH only
when bot h t he input s ar e LOW and in all ot her condit ions it will be high. The out put Y is
shown in Fig. 2.5.7(m).
1 0 1 0
t
1
t
2
t
3
t
4
OUTPUT Y →
Fig. 2.5.7 (m)
88 S witching Theory
The NOR gate as a UNIVERSAL gate.
The char t in Fig. 2.5.7(n) shows how would your wir e NOR gat es t o cr eat e any of t he
ot her basic logic funct ions.
Logic
Function
Symbol Circuit using NOR gates only
Inverter
AND
OR
A
B
A A′
A.B
A
B
A + B
A
A′
A
B
A + B
A
B
A . B
Fig. 2.5.7 (n)
2.5.8 The Exc lusive OR Ga te
The exclusive OR gat e is somet imes r efer r ed t o as t he “Odd but not t he even gat e”. It
is oft en shor t end as “XOR gat e”. The logic diagr am is shown in Fig. 2.5.8 (a) wit h it s Boolean
expr ession. The symbol ⊕ means t he t er ms ar e XORed t oget her.
A
B
Y = A B
= AB + A B

′ ′
Fig. 2.5.8 (a)
The t r ut h t able for XOR gat e is shown in Fig. 2.5.8 (b). Not ice t hat if any but not all t he
input s ar e 1, t hen t he out put will be 1. ‘The unique char act er ist ic of t he XOR gat es t hat it
pr oduces a HIGH out put only when t he odd no. of HIGH input s ar e pr esent .’
INPUTS OUTPUTS
A B A ⊕ B = AB′ + A′B
0 0 0
0 1 1
1 0 1
1 1 0
Fig. 2.5.8 (b)
To demonst r at e t his, Fig. 2.5.8 (c) shows a t hr ee input XOR gat e logic symbol and t he t r ut h
t able Fig. 2.5.8 (d). The Boolean expr ession for a t hr ee input XOR gat e can be wr it t en as
Y = (A ⊕ B) ⊕ C
= (AB′ + A′B) ⊕ C
Now Let X = AB′ + A′B
⇒ We ha ve X ⊕ C
= XC′ + X′C
Digital Design Fundamentals–Boolean Algebra and Logic Gates 89
A
C
Y = A B C ⊕ ⊕ B
Fig. 2.5.8 (c)
INPUTS OUTPUTS
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Fig. 2.5.8 (d)
Put t ing t he value of X, we get
Y = (AB′ + A′B)C + (AB′ + AB).C
Y = AB′C′ + A′BC′ + A′B′C + ABC
The HIGH out put s ar e gener at ed only when odd number of HIGH input s ar e pr esent (see
T.T.)
‘This is why XOR function is also known as odd function’.
Fig. 2.5.8 (e) shows t he ways t o expr ess t hat input A is XORed wit h input B yielding
output Y.
Boolean
Expression
Logic
Symbol
Truth
Table
A
B
Y
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
0
A B = Y ⊕
XOR Symbol
Fig. 2.5.8 (e)
The XOR gat e using AND OR-NOT gat es.
we know A ⊕ B = AB′ + A′B
90 S witching Theory
A B ⊕
A
B
As we know NAND and NOR ar e univer sal gat es means any logic diagr am can be made
using only NAND gat es or using only NOR gat es.
XOR gate usi ng NAND gates only.
A B ⊕
A
B
XOR using NOR gat es only. The pr ocedur e for implement ing any logic funct ion using
only univer sal gat e (only NAND gat es or only NOR gat es) will be t r eat ed in det ail in sect ion
2.6.
A B ⊕
A
B
Example. Determine the output Y from the XOR gate from the given input waveform
shown in Fig. 2.5.8 (f).
A
B
0 1 1 0
0 0 0 1
Y
0 0 1 1
0
1
0
t
1
t
2
t
3
t
4
t
5
C
?
Fig. 2.5.8 (f)
Solution. The out put XOR gat e is det er mined by r ealizing t hat it will be HIGH only
when t he odd number of high input s ar e pr esent t her efor e t he out put Y is high for t ime
period t
2
and t
5
as shown in Fig. 2.5.8 (g).
0 1 0 0 1
t
1
t
2
t
3
t
4
t
5
OUTPUT Y →
Fig. 2.5.8 (g)
Digital Design Fundamentals–Boolean Algebra and Logic Gates 91
2.5.9 The Exc lusive NOR ga te
The Exclusive NOR gate is sometimes reffered to as the ‘COINCIDENCE’ or ‘EQUIVA-
LENCE’ gat e. This is oft en short ened as ‘XNOR’ gat e. The logic diagram is shown in Fig. 2.5.9 (a).
A
B
Y = A B
= AB + A B

.

′ ′
Fig. 2.5.9 (a)
Obser ve t hat it is t he XOR symbol wit h t he added inver t bubble on t he out put side. The
Boolean expr ession for XNOR is t her efor e, t he inver t of XOR funct ion denot ed by symbol O
.
.
AO
.
B = (A ⊕ B)′
= (AB′ + A′B)′
= (A′ + B) . (A + B′)
= AA′ + A′B′ + AB + BB′
= AB + A′B′.
The t r ut h t able for XNOR gat e is shown in Fig. 2.5.9 (b).
INPUTS OUTPUTS
A B AO
.
B = AB + A′B′
0 0 1
0 1 0
1 0 0
1 1 1
Fig. 2.5.9 (b)
Not ice t hat t he out put of XNOR gat e is t he complement of XOR t r ut h t able.
‘The unique output of the XNOR gate is a LOW only when an odd number of input are HIGH’.
A
C
Y = A B C
.

.
B
Fig. 2.5.9 (c)
INPUTS OUTPUTS
A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Fig. 2.5.9 (d)
92 S witching Theory
To demonst r at e t his, Fig. 2.5.9 (c) shows a t hr ee input XNOR gat e logic symbol and t he
t r ut h-t able 2.5.9 (d).
Figur e 2.5.9 (e) shows t he ways t o expr ess t hat input A is XNORed wit h input B yielding
output Y.
Boolean
Expression
Logic
Symbol
Truth
Table
A
B
Y
A
0
0
1
1
B
0
1
0
1
Y
1
0
0
1
A
.
B = Y
Fig. 2.5.9 (e)
Now at t his point , it is left as an exer cise for t he r eader t o make XNOR gat e using AND-
OR-NOT gat es, using NAND gat es only and using NOR gat es only.
Example. Determine the output Y from the XNOR gate from the given input waveform
shown in Fig. 2.5.9 (f).
0 1 1 0
1 1 1 0
Y
0 0 1 1
0
0
0
t
1
t
2
t
3
t
4
t
5
?
Fig. 2.5.9 (f)
Soluti on. The out put of XNOR gat e is
det er mined by r ealizing t hat it will be HIGH
only when t he even-number of high input s ar e
pr esent , t her efor e t he out put Y is high for t ime
period t
2
and t
5
as shown in Fig. 2.5.9 (g).
2.5.10 Exte nsion to M ultip le Inp uts in Log ic G a te s
The gat es we have st udied, except for t he inver t er and buffer can be ext ended t o have
mor e t han t wo input s.
A gat e can be ext ended t o have mult iple input s t he binar y oper at ion it r epr esent s is
commut at ive and associat ive.
0 1 0 0 1
t
1
t
2
t
3
t
4
t
5
OUTPUT Y →
Fig. 2.5.9 (g)
Digital Design Fundamentals–Boolean Algebra and Logic Gates 93
The AND and OR oper at ions defined in Boolean algebr a, posseses t hese t wo pr oper t ies.
For t he NAD funct ion, we have
x.y = y.x Commut at ive
and x.(yz) = (x.y).z Associat ive
Similar ly for t he OR funct ion,
x + y = y + x Commut at ive
and (x + y) + z = x + (y + z) Associat ive
It means t hat t he gat e input s can be int er changed and t hat t he AND and OR funct ion
can be ext ended t o t he or mor e var iables.
The NAND and NOR oper at ions ar e commut at ive but not associat ive. For example
*(x ↑ y) = (y ↑ x) ⇒ x′ + y′ = y′ + x′ = commut at ive
But x ↑ (y ↑ z) ≠ (x ↑ y) ↑ z
⇒ [x′.(y.z)′] ≠ [(x.y)′.z)]′
⇒ x′ + yz ≠ xy + z′
Similarly
**(x ↓ y) = (y ↓ x) ⇒ x′y′ = y′x′ → commut at ive
But x (y ↓ z) ≠ (x ↓ y) ↓ z
⇒ [x + (y + z)′]′ ≠ [(x + y)′ + z]
x′y + x′z ≠ xz′ + yz′
This difficult y can be over comed by slight ly modifying t he definit ion of oper at ion. We
define t he mult iple NAND (or NOR) gat e as complement ed AND (or OR) gat e.
Thus by t his new definit ion, we have
x ↑ y ↑ z = (xyz)′
x ↓ y ↓ z = (x + y + z)′
The gr aphic symbol for 3-input NAND and NOR gat es is shown.
x
y
z
(x + y + z)′
x
y
z
(xyz)′
(a) Three-input
NAND gate
(b) Three-input NOR gate
The exclusive–OR and equivalence gat es ar e bot h comment at ive and associat ive and can
be ext ended t o mor e t han t wo input s.
The r eader is suggest ed t o ver ify t hat , bot h X-OR and X-NOR pr osses commut at ive and
associat ive pr oper t y.
* NAND symbol
** NOR symbol
94 S witching Theory
SO LV ED EXAM PLES
Example 1. Give the concluding statement of all the logic gates, we have studied in this
chapter.
Solution. AND: The out put is HIGH only when all t he input s ar e HIGH, ot her wise
out put is LOW.
OR: The out put is LOW only when all t he input s ar e LOW, ot her wise out put is HIGH.
NOT: The out put is complement of input .
NAND: The out put is LOW only when all t he input s ar e HIGH, ot her wise t he out put
is HIGH.
NOR: The out put is HIGH only when all t he input s ar e LOW, ot her wise out put is LOW.
EX-OR: The out put is HIGH only when bot h t he input s ar e not same, ot her wise out put
is Low.
OR
The out put is HIGH only when odd number of input s ar e HIGH, ot her wise out put is
LOW.
EX-NOR: The out put is HIGH only when bot h t he input s ar e same, ot her wise out put
is LOW.
OR
The out put is HIGH only when even number of input s ar e HIGH, ot her wise out put is
LOW.
Example 2. S how how an EX-OR gate can be used as NOT gate or inverter.
Solution. The expr ession for NOT gat e is
y =
A
where y = out put and A = input
The expr ession for EX-OR gat e is
y = AB + AB
where A and B ar e input s.
In t he expr ession of EX-OR we see t hat t he fir st t er m AB
can give t he complement of input A, if B = 1 and second t er m
AB = 0 . So we connect t he B input t o logic HIGH (i.e., logic 1)
t o full fill t he r equir ement s above st at ed. i.e.,
fr om figur e
y = A.1 + A. 0
or y = A i.e., complement
Thus above connect ion act s as inver t er or NOT gat e.
Example 3. S how, how an AND gate and an OR gate can be marked.
Solution. Masking of gat es means disabling t he gat e. It is t he pr ocess of connect ing a
gat e in such a way t hat t he out put is not affect ed by any change in input s i.e., t he out put
r emains fixed t o a logic st at e ir r espect ive of input s.
Logic 1
Y
A
Fi g. Ex. 2: EX-OR Gat e
connect ed as NOT Gat e
Digital Design Fundamentals–Boolean Algebra and Logic Gates 95
Y = 0 always
Y = 1 always
Logic 0
Logic 1
A
B
A
B
Fig. Ex. 3: Masking of AND gat e and OR gat e
AND gat e can be masked by connect ing one of it s input t o logic LOW (i.e. logic 0) and
Or gat e can be mar ked by connect ing one of it s input t o logic HIGH (i.e. logic 1)
Example 4. Below shown waveforms are
applied at the input of 2-input logic gate.
0
1 1 1 1
0 0
1
1 1
0 0 0
A
B
0
Draw the output waveform if the gate is (a) AND gate (b) OR gate (c) EX-OR gate (d)
NAND gate (e) NOR gate.
Solution. The wavefor ms can be dr awbn be r ecalling t he concluding st at ement s of logic
gat es given in ear lier examples.
0
1 1 1 1
0 0
1
1 1
0 0 0
A
B
0
Output Waveforms
0
1 1 1
0 0
1 1
0
AND
OR
0
1
0 0
1 1 1
1 1 1 1 1
0
0
0
1 1 1 1 1
0
1
0 0
1
0 0
1
0 0 0 0 0 0 0 0
EX-OR
NAND
NOR
96 S witching Theory
Example 5. S how how a 2 input AND gate, OR gate, EX-OR gate and EX-NOR gate can
be made transparent.
Solution. Tr anspar ent gat e means a gat e t hat passes t he input as it is t o t he out put i.e.
t he out put logic level will be same as t he logic level applied at input . Let t he t wo input s ar e
A and B and out put is y. We will connect t he gat es in such a way t hat it gives y = A.
For AND gate we have expr ession
y = A.B
if B = 1
y = A
So connect input B t o logic 1 for OR gate we have
y = A + B
if B = 0
y = A
So connect input B t o logic 0 for EX-OR gate we have
y =
AB + AB
if B = 0,
t hen
AB
= A, and
AB = 0
and y = A
Hence connect input B t o logic 0 for EX-NOR gate we have
y = AB + AB
if B = 1,
t hen
AB
= 0 and AB = A
so y = A
Hence connect input B t o logic 1
It we t ake mult iple input logic gat es t hen connect ing t hem as above is called enabling
a gat e t hen connect ing t hem as above is called enabling a gat e e.g. if we t ake t hr ee input (A,
B, C) AND gat e and connect t he input (A, B, C) AND gat e and connect t he input C t o logic
1, t hen out put y = A.B. Thus t he gat e is enabled.
Example 6. Determine the purpose of below shown digital circuit.
Y
1
Y
2
Y
3
Y
0
B
A
Solution. Fr om t he figur e we see t hat
y
0
=
A B = AB + AB ⊕
y
1
= A.y
0
y
2
= y
0
y
3
= B.y
0
Y = A
Logic 1
A
B
Fi g. Transp-
ar ent AND gat e
Ex. 5 ( ): a
Y = A
A
B
Logic 0
Fi g. Ex. 5 ( ): b Transpar ent
OR gat e
Y = A
A
B
Logic 0
Fi g. Ex. 5 ( ): c Transpar ent
EX-OR gat e
Y = A
A
B
Logic 1
Fi g. Ex. 5 ( ): d Transpar ent
EX-NOR gat e
Digital Design Fundamentals–Boolean Algebra and Logic Gates 97
Now we dr aw t hr ee t r ut h t ables, one for each of t he out put s y
1
, y
2
, and y
3
t o det er mine
t he pur pose of t he cir cuit .
(i) Fr om t he t able (i), it is evident t hat
y
1
= 1, only when A = 1 and B = 0.
It means t hat y
1
is HIGH only when
A > B, as shown in t hir d r ow of
Table (i)
(ii) It is evident fr om Ta ble (i i) t ha t
y
2
= 1 if A = B = 0 and A = B = 1.
Thus y
2
goes HIGH only when A =
B

, as shown by fir st and last r ow of
Table (ii).
(iii) It is evident fr om Table (iii) t hat
y
3
= 1 if A = 0 and B = 1. Thus y
3
goes HIGH only when A < B (or B >
A), as shown by t he second r ow of
t able (iii).
Thus fr om t he above discussion it can be concluded t hat t he given cir cuit is 1-bit
dat a compar at or. In t his cir cuit when HIGH, y
1
indicates A > B, y
2
indicat e t he
equalit y t wo dat as, and y
3
indicat es A < B.
2.6 NAND AND NOR IMPLEMENTATION
In Sect ion 2.5.7 we have seen t hat NAND and NOR ar e univer sal gat es. Any basic logic
funct ion (AND, OR and NOT) can be implement ed using t hese gat es only. Ther efor e digit al
cir cuit s ar e mor e fr equent ly const r uct ed wit h NAND or NOR gat es t hat wit h AND, OR and
NOT gat es. Mor eover NAND and NOR gat es ar e easier t o fabr icat e wit h elect r onic compo-
nent s and ar e t he basic gat es used in all IC digit al logic families. Because of t his pr ominence,
r ules and pr ocedur es have been developed for implement at ion of Boolean funct ions by using
eit her NAND gat es only or NOR gat es only.
2.6.1 Imp le me nta tion of a M ultista g e ( or M ultile ve l) Dig ita l C irc uit using NAND
G a te s O nly
To facilit at e t he implement at ion using NAND gat es only, we fir st define t wo gr aphic
symbols for t hese gat es as follows-shown in Fig. 2.6.1(a) and (b).
(a) The AND-invest symol (b) The inver t -OR symbol
x
y
z
F (xyz)′
x
y
z
F = x + y + z ′ ′ ′
(xyz)′ =
(a) (b)
Fig. 2.6.1 (a) (b)
This symbol we have been This is an OR gr aphic symbol
difined in Sect ion (2.5). pr oceded by small cir ct es in all
It consist s of an AND t he input s.
gr pahic symbol followed by
a small cir cle.
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
0
0
Y
0
0
1
0
1
Table (i )
Table (i i )
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
0
0
Y
0
1
0
0
1
Table (i i i )
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
0
0
Y
1
0
0
1
1
98 S witching Theory
To obt ain a mult ilevel NAND cir cuit fr om a given Boolean funct ion, t he pr ocedur e is as
follows:
1. From t he given Boolean funct ion, draw t he logic diagam using basic gat es (AND, OR
and NOT). In implement ing digit al circuit , it is assumed t hat bot h normal and invent ed
input s are available. (e.g., If x and x′ bot h are given in funct ion, we can apply t hen
directly that is there is no need to use an inverter or NOT gate to obtain x′ from x).
2. Convert all AND gat es t o NAND using AND-inver t symbol.
3. Conver t all OR gat es t o NAND using Inver t -OR symbol.
4. Since each symbol used for NAND gives inver t ed out put , t her efor e it is necessar y
t o check t hat if we ar e get t ing t he same value as it was at input . [For example if
t he input is in it s nor mal fr om say x, t he out put must also be x, not x′ (inver t ed
or complement ed value). Similar ly if input is in it s complement ed for m say x′, t he
ouput must also be x′, not x (nor mal value)].
If it is not so, t hen for ever y small cir cle t hat is not compensat ed by anot her small
cir cle in t he same line, inser t an inver t er (i.e., one input NAND gat e) or complement
t he input var iable.
Now consider a Boolean funct ion t o demonst r at e t he pr ocedur e:
Y = A + (B + C′) (D′E + F)
Step 1. We fir st dr aw t he logic diagr am using basic gat es shown in Fig. 2.6.1 (c). (It is
assumed t hat bot h nor mal os complement ed for ms ar e available i.e., no need of inver t er ).
Y
A
B′
C
D′
E
F
I Level II Level III Level IV Level
Fig. 2.6.1 (c)
Ther e ar e four levels of gat ing in t he cir cuit s.
Step 2 and 3
Y
A
B′
C
D′
E
F
Fig. 2.6.1 (d)
Digital Design Fundamentals–Boolean Algebra and Logic Gates 99
Her e, we have conver t ed all AND gat es t o NAND using AND-inver t and all OR gat es t o
NAND using inver t OR symbol shown in Fig. 2.6.1 (d).
Step 4. Fr om t he above figur es obt ained fr om st ep 2 and 3, it is ver y clear t hat only t wo
input s D′ and E ar e emer ging in t he or iginal for ms at t he out put . Rest i.e., A, B′, C and F
ar e emer ging as t he complement of t heir or iginal for m. So we need an inver t er aft er input s
A, B′, C and F or alt er nat ively we can complement t hese var iables as shown in Fig. 2.6.1 (e).
Y
A
B
C′
D′
E
F
Fig. 2.6.1 (e)
Now because bot h t he symbols AND-inver t and inver t -OR r epr esent a NAND gat e, Fig.
2.6.1 (e) can be conver t ed int o one symbol diagr am shown in Fig. 2.6.1 (f). The t wo symbols
wer e t aken just for simplicit y of implement at ion.
Y
A′
B
C′
D′
E
F′
Fig. 2.6.1 (f)
Aft er a sufficient pr act ice, you can dir ect ly implement any Boolean funct ion a shown in
Fig. 2.6.1 (f).
2.6.2 Imp le me nta tion of a M ultile ve l d ig ita l c irc uit using NO R g a te s only
We fir st define t wo basic gr aphic symbols for NOR gat es as shown in Fig. 2.6.2 (a) and
(b).
(a) The OR-inver t symbol (b) The inver t -AND symbol
x
y
z
F = (x + y + z)′
x
y
z
F = x y z
(x + y + z)


′ ′
=
(a) This is an OR graphic symbol
followed by a small circle.
(b) This is an AND graphic symbol proceded
by small circles in all the inputs.
Fig. 2.6.2 (a) (b)
100 S witching Theory
Pr ocedur e t o obt ain a mult ilevel NOR cir cuit fr om a given Boolean funct ion is as follows:
1. Draw the AND-OR logic diagr am fr om t he given expr ession. Assume t hat bot h
nor mal and complement ed for ms ar e available.
2. Conver t all OR gat es t o NOR gat es using OR-inver t symbol.
3. Convert all AND gat es t o NOR gat es using inver t -AND symbol.
4. Any small cir cle t hat is not complement by anot her small cir cle along t he same line
needs an inver t er (one input NOR gat e) or t he complement at ion of input var iable.
Consider a Boolean expr ession t o demonst r at e t he pr ocedur e:
Y = (A + B). (C + D ) E + (F + G ) ′ ′ ′
Step 1. We fir st dr aw the AND-OR logic diagr am shown in Fig. 2.6.2 (c).
A′
B
C
D′
E
F
I Level II Level III Level IV Level
G′
Y
Fig. 2.6.2 (c)
Ther e ar e four levels of gat ing in t he cir cuit .
Step 2 and 3. Her e we have t o conver t all OR gat es t o NOR using OR-inver t and all
AND gat es t o NOR using inver t AND symbol. This is shown in Fig. 2.6.2(d).
A′
B
C
D′
E
F
G′
Y
Fig. 2.6.2 (d)
Step 4. Fr om Fig. 2.6.2 (d), it is clear t hat all t he input var iables ar e imer ging in t he
same for m at t he ouput Y as t hey wer e at input . Ther efor e t her e is no need of inver t er at
input s or complement ing t he input var iables.
Her e again, bot h symbols OR-inver t and invent -AND r epr esent a NOR gat e, so t he
diagr am of Fig. 2.6.2 (d) can be conver t ed int o one symble shown in Fig. 2.6.2 (e).
Digital Design Fundamentals–Boolean Algebra and Logic Gates 101
A′
B
C
D′
E
F
G′
(A + B)′ ′
( C + D ) ′ ′
Y
Fig. 2.6.2 (e)
2.7 EXERC ISES
1. Wr it e Boolean equat ions for F
1
and F
2
.
A B C F
1
A B C F
2
0 0 0 1 0 0 0 0
0 0 1 0 0 0 1 1
0 1 0 0 0 1 0 1
0 1 1 0 0 1 1 1
1 0 0 0 1 0 0 0
1 0 1 1 1 0 1 1
1 1 0 0 1 1 0 1
1 1 1 1 1 1 1 0
2. Consider 2-bit binar y number s, say A, B and C, D. A funct ion X is t r ue only when
t he t wo number s ar e differ ent const r uct a t r ut h t able for X.
3. Dr aw t r ut h t able and wr it e Boolean expr ession for t he following:
(a) X is a 1 only if A is a ⊥ and B is a ⊥ or if A is 0 and B is a 0.
(b) X is a 0 if any of the three variables A, B and C are 1’s. X is a ⊥ for all other conditions.
4. Pr ove t he following ident it ies by wr it ing t he t r ut h t ables for bot h sides:
(a) A.(B + C) = (A.B) + (A.C)
(b) (A.B.C)′ = A′ + B′ + C′
(c) A.(A + B) = A
(d) A + A′B = A + B
5. Pr ove t he following:
(a) (X Y) (X Y ) X + + ′ =
(b) XY X Z YZ XY X Z + ′ + = + ′
(c) ( ) . X Y X Y + ′ =
(d) ( ) ( ) X Y X Z X Y Z + + = + +
(e) ( ) ( ) X Y Z X Y Z X Y + + + + ′ = +
102 S witching Theory
6. Wit hout for mally der iving can logic expr ession, deduct t he value of each funct ion
W, X, Y, Z.
A B C W X Y Z
0 0 0 0 1 0 1
0 0 1 0 1 0 0
0 1 0 0 1 0 1
0 1 1 0 1 0 0
1 0 0 0 1 1 1
1 0 1 0 1 1 0
1 1 0 0 1 1 0
1 1 1 0 1 1 0
7. A lar ge r oom has t hr ee door s, A, B and C, each wit h a light swit ch t hat can t ur a
t he r oom light ON or OFF. Flipping any swit ch will change t he condit ion of t he
light . Assuming t hat t he light swit ch is off when t he swit ch var iables have t he
values 0, 0, 0 wr it e a t r ut h t able for a funct ion LIGHT t hat can be used t o dir ect
t he behaviour of t he light . Der ive a logic equat ion for light .
8. Use DeMor gan’s t heor m t o complement t he following Boolean expr ession.
(a) Z = Z = ( x y w v . . ) +
(b) Z = x y w y w v . . ( ) + ′ + ′
(c) Z = x y ′ + Υ
(d) F = AB + CD) ( ′′
(e) F = (A + B ) (C + D ′ ′ ′ b g
(f) F = A + B ) (C + D) ( ′ ′ b g
(g) F = (ABC) EFG) HIJ ) (KLM) ′ ′ ′ + ′ ′ ′ ′ ( ( b g b g
(h) F = (A + B) C + D) E + F) G + H) ′ ′ ′ ′ ′ ′ ( ( ( b g
9. A cer t ain pr oposit ion is t r ue when it is not t r ue t hat t he condit ions A and B bot h
hold. It is also t r ue when condit ions A and B bot h hold but condit ion C does not .
Is t he pr oposit ion t r ue when it is not t r ue t hat condit ions B and C bot h hold? Use
Boolean algebr a t o just ify your answer.
10. Define t he following t er ms:
(a) Connical
(b) Mint er m
(c) Mext er m
(d) Sum-of-sums for m
(e) Pr oduct -of-sum for m
(f) Connical sum-of-pr oduct
(g) Connical pr oduct -of-sums
Digital Design Fundamentals–Boolean Algebra and Logic Gates 103
11. Wr it e t he st andar d SOP and t he st andar d POS for m for t he t r ut h t ables:
(a) x y z F (b) x y z F
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 0 1 1 1
1 0 0 1 1 0 0 1
1 0 1 0 1 0 1 1
1 1 0 0 1 1 0 0
1 1 1 1 1 1 1 1
12. Conver t t he following expr essions int o t heir r espect ive connical for ms:
(a) AC + A BD + ACD ′ ′
(b) (A + B +C ) (A + D) ′
13. Which of t he following expr essions is in sum of pr oduct for m? Which is in pr oduct
of sums for m?
(a) A + (B.D)′
(b) C.D .E + F + D ′ ′
(c) (A + B).C
14. Find t he connical s-of-p for m for t he following logic expr essions:
(a) W = ABC + BC D ′
(b) F = VXW Y + W XYZ ′ ′
15. Wr it e down t he connical s-of-p for m and t he p-of-s for m for t he logic expr ession
whose TT is each of t he following.
(a) x
1
y
2
z
3
Z (b) W X Y Z F
0 0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 1 0
0 1 0 0 0 0 1 0 1
0 1 1 1 0 0 1 1 0
1 0 0 1 0 1 0 0 1
1 0 1 1 0 1 0 1 0
1 1 0 0 0 1 1 0 1
1 1 1 1 0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
104 S witching Theory
16. Conver t t he following expr essions t o sum-of-pr oduct for ms:
(a) AB + CD (AB + CD) ′
(b) AB (B C + BC) ′ ′
(c) A + B AC + (B + C) D ′
17. Given a Tr ut h t able
(a) Expr ess W
1
and W
2
as a sum of mint er ms
(b) Expr ess W
1
and W
2
as pr oduct of mint er ms
(c) Simplify t he sum of mint er m expr essions for W
1
and W
2
using Boolean algebr a.
18. Dr aw logic cir cuit s using AND, OR and NOT gat es t o r epr esent t he following:
(a) AB + A B ′ ′ (b) AB + A B + A BC ′ ′ ′
(c) A + B C + D (B + C ) ′ (d) A + BC + D (E + F ) ′ ′ ′
(e) (AB) (CD) ′ ′ ′
19. Pr oduce a gr aphical r ealizat ion of Inver t er, AND, OR and XOR using:
(a) NAND gat es
(b) NOR gat es
20. Implement t he Boolean funct ion
F = AB CD + A BCD + AB C D + A BC D ′ ′ ′ ′ ′ ′ ′ ′ wit h exclusive-OR and AND gat es.
21. Dr aw t he logic cir cuit s for t he following funct ions.
22. A war ning busser is t o sound when t he following condit ions apply:
(a) Swit ches A, B, C ar e on.
(b) Swit ches A and B ar e on but swit ch C is off.
(c) Swit ches A and C ar e on but swit ch B is off.
(d) Swit ches B and C ar e on but swit ch A is off.
Draw a t r ut h t able and obt ain a Boolean expr ession for all condit ions. Also dr aw t he
logic diagr am for it using (i) NAND gat es (ii) NOR gat es. If t he delay of a NAND
gat e is 15 ns and t hat of a NOR gat e is 12 ns, which implement at ion is t est er.
23. Obt ain t he following oper at ions using only NOR gat es.
(a) NOT (b) OR (c) AND
24. Obt ain t he following oper at ions using only NAND gat es.
(a) NOT (b) AND (c) OR
25. Find t he oper at ion per for med for each of t he get s shown in figur e below, wit h t he
help t he t r ut h t able.
(a)
A
B
Y
(b)
A
B
Y
(c)
A
B
Y (d)
A
B
Y
Digital Design Fundamentals–Boolean Algebra and Logic Gates 105
26. Wr it e t he expr ession for EX-OR oper at ion and obt ain
(i) The t r ut h t able
(ii) Realize t his operat ion using AND, OR, NOT gat es.
(iii) Realize t his oper at ion using only NOR gat es.
27. Var ify t hat t he (i) NAND (ii) NOR oper at ions ar e commut at ive but not associat e.
28. Var ify t hat t he (i) AND (ii) OR (iii) EX-OR oper at ions ar e commut at ive as well as
associat ive.
29. Pr ove t hat
(i) A posit ive logic AND oper at ion is equivalent t o a negat ive logic OR oper at ion
and vice ver sa.
(ii) A posit ive logic NAND operat ion is equivalent t o a negat ive logic NOR operat ion
and vice ver sa.
30. Pr ove t he logic equat ions using t he Boolean algebr aic (swit ching algebr aic) t heor ems.
(i)
A + AB + AB = A + B
(ii)
AB + AB + AB = AB
Var ify t hese equat ions wit h t r ut h t able appr oach.
31. Pr ove De Mor gan’s t heor ems.
32. Using NAND gat es pr oduce a gr aphical r ealizat ion of
(a) Inver t er
(b) AND
(c) OR
(d) XOR
33. Using NOR gat es also pr oduce a gr aphical r ealizat ion of
(a) Inver t er
(b) AND
(c) OR
34. Pr ove (X + Y) (X + Y′) = X
35. XY + X′Z + YZ = XY + X′Z
36. Pr ove t he following:
37. (a) (A + B)′ = A.B (b) (A + B) (A + C) = A + BC
38. Pr ove t he ident ifies:
(i) A = (A + B) (A + B)¢
(ii) A + B = (A + B + C) (A + B + C′)
39. Obt ain t he simplified expr essions in s-of-p for t he following Boolean funct ions:
(a) xy x yz x yz + ′ ′ + ′ ′
(b) ABD + A C D A B + A CD + AB D ′ ′ ′ + ′ ′ ′ ′ ′
106 S witching Theory
(c) x z w xy w x y xy ′ + ′ ′ + ′ + ′ ( )
(d) F (x y z , , ) ( , , , ) = Σ 2 3 6 7
(e) F (A, B, C ) (A + D) ′
40. Conver t t he following expr essions int o t heir r espect ive Canonical for ms
(a) AC + A'BD + ACD'
(b) (A + B + C') (A + D)
41. Wr it e t he st andar d SOP and t he st andar d POS for m for t he t r ut h t ables
(a) (b)
x y z F
(x, y, z)
x y z F
(x, y, z)
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 0 1 1 1
1 0 0 1 1 0 0 1
1 0 1 0 1 0 1 1
1 1 0 0 1 1 0 0
1 1 1 1 1 1 1 1
42. Consider 2-bit binar y number s, say A, B and C, D. A funct ion X is t r ue only when
t he t wo number s ar e differ ent .
(a) Const r uct a t r ut h t able for X
(b) Const r uct a four -var iable K-Map for X, dir ect ly fr om t he wor d definit ion of X
(c) Der ive a simplified logic expr ession for X.
43. Show an implement at ion of t he half-adder using NAND gat es only.
44. A t hr ee-bit message is t o be t r ansmit t ed wit h an even-par it y bit .
(i) Design t he logic cir cuit for t he par it y gener at or.
(ii) Design t he logic cir cuit for t he par it y checker.
45. Implement t he Boolean funct ion: F = AB′CD′ + A′BCD′ + AB′C′D + A′BC′D′ wit h
exclusive-OR and AND gat es.
46. Const r uct a 3-t o-8 line decoder.
47. Const r uct a 3 × 8 mult iplexer.
48. Const r uct a 8 × 3 ROM using a decoder and OR gat es.
49. Const r uct a 16 × 4 ROM using a decoder and OR gat es.
50. Det er mine which of t he following diodes below ar e conduct ing and which ar e non
conduct ing.
Digital Design Fundamentals–Boolean Algebra and Logic Gates 107
R
–5v
D
1
D
2
R
–10v
–5v
D
2
D
1
–12v
+5v
R
–5v
51. Det er mine which t r ansist or s ar e ON ar e which ar e OFF.
–5v
+5v –10v
–15v
+10v
–2v
–6v
52. Const r uct volt age and logic t r ut h t ables for t he cir cuit s shown below. Det er mine
A
(i)
C
B
D
1
D
2
D
3
R
1 = +5v
0 = –5v
–10v
(i)
A
Output
C
B
D
1
D
2
D
3
R
1 = 0v
0 = –5v
+5v
(ii)
t he logic oper at ion per for med by each. Assume ideal diodes i.e., –neglect t he volt age
dr op acr oss each diode when it is for war d biased.
53. Dr aw t he logic cir cuit s for t he following funct ions:
(a) B. (A. C ) + D + E ′ ′
(b) (A + B) C + D ′ .
(c) (A + B). (C + D) ′
54. Pr ove t he following ident it ies by wr it ing t he t r ut h t ables for bot h sides.
(a) A.(B + C) == (A.B) + (A.C)
(b) (A.B.C)′ == A′ + B′ + C′
108 S witching Theory
(c) A.(A + B) == A
(d) A + A′.B == A + B
55. A war ningbuzzer is t o sound when t he following condit ions apply:
• Swit ches A, B, C ar e on.
• Swit ches A and B ar e on but swit ch c is off.
• Swit ches A and C ar e on but swit ch B is off.
• Swit ches C and B ar e on but swit ch A is off.
Dr aw a t r ut h t able for t his sit uat ion and obt ain a Boolean expr ession for it . Minimize
t his expr ession and dr aw a logic diagr am for it using only (a) NAND (b) NOR gat es.
If t he delay of a NAND gat e is 15ns and t hat of a NOR gat e is 12ns, which
implement at ion is fast er.
56. Which of t he following expr essions is in sum of pr oduct s for m? Which is in pr oduct
of sums for m ?
(a) A.+(B.D)′
(b) C.D′.E + F′ + D
(c) (A + B).C
57. Wit hout for mally der iving an logic expr essions, deduce t he value of each funct ion
W, X, Y and Z.
A B C W X Y Z
0 0 0 0 1 0 1
0 0 1 0 1 0 0
0 1 0 0 1 0 1
0 1 1 0 1 0 0
1 0 0 0 1 1 1
1 0 1 0 1 1 0
1 1 0 0 1 1 1
1 1 1 0 1 1 0
58. Define t he following t er ms:
(a) Canonical
(b) Mint er m
(c) Maxt er m
(d) Sum-of-pr oduct s for m
(e) Pr oduct -of-sum for m
(f) Canonical sum-of-pr oduct s
(g) Canonical pr oduct -of-sums
59. An audio (beeper ) is t o be act ivat ed when t he key has been r emoved fr om t he
ignit ion of a car and t he headlight s ar e left on. The signal is also t o be act ivat ed
if t he key is in t he ignit ion lock and t he dr iver ’s door is opened. A 1 level is
pr oduced when t he headlight swit ch is on. A 1 level is also pr oduced fr om t he
Digital Design Fundamentals–Boolean Algebra and Logic Gates 109
ignit ion lock when t he key is in t he lock, and a 1 level is available fr om t he dr iver ’s
door when it is open. Wr it e t he Boolean equat ion and t r ut h t able for t his pr oblem.
60. A car has t wo seat swit ches t o det ect t he pr esence of a passenger and t wo seat belt
swit ches t o det ect fast ened seat belt s. Each swit ch pr oduces a 1 out put when
act ivat ed. A signal light is t o flash when t he ignit ion when t he ignit ion is swit ched
on any passenger pr esent wit hout his or her seat belt fast ened. Design a suit able
logic cir cuit .
61. Dr aw logic diagr ams for t he simplified expr essions found in Quest ion 37 using.
• NAND gat es only.
• NOR gat es only.
Assume bot h A and A′, B and B′ .. et c. ar e available as input s.
62. You ar e inst alling an alar m bell t o help pr ot ect a r oom at a museum for m
unaut hor ized ent r y. Sensor devices pr ovide t he following logic signals:
ARMED = t he cont r ol syst em is act ive
DOOR = t he r oom door is closed
OPEN = t he museum is open t o t he public
MOTION = Ther e is mot ion in t he r oom
Devise a sensible logic expr ession for r inging t he alar m bell.
63. A large room has t hree doors, A, B and C, each wit h a light swit ch t hat can t urn t he
room light ON or OFF. Flipping any swit ch will change t he condit ion of t he light .
Assuming t hat t he light swit ch is off when t he swit ch variables have t he values 0,
0, 0 writ e a t rut h t able for a funct ion LIGHT t hat can be used t o direct t he behaviour
of t he light . Derive a logic equat ion for LIGHT. Can you simplify t his equat ion ?
64. Design a combinat ional cir cuit t hat accept s a t hr ee-bit number and gener at es an
out put binar y number equal t o t he squar e of t he input number.
65. Design a combinat ional cir cuit whose input is a four -bit number and whose out put
is t he 2’s compliment of t he input number.
66. A combinat ional cir cuit has four input s and one out put . The out put is equal t o 1
when (I) all t he input s ar e equal t o 1 or (II) none of t he input s ar e equal t o 1 or
(III) an odd number of input s ar e equal t o 1.
(i) Obt ain t he t r ut h t able.
(ii) Find t he simplified out put funct ion in SOP
(iii) Find t he simplified out put funct ion in POS
(iv) Dr aw t he t wo logic diagr ams.
67. Find t he canonical s-of-p for m t he following logic expr essions:
(a) W = ABC + BC′D
(b) F = VXW′Y + W′XYZ
68. A cer t ain pr oposit ion is t r ue when it is not t r ue t hat t he condit ions A and B bot h
hold. It is also t r ue when condit ions A and B bot h hold but condit ion C does not .
Is t he pr oposit ion t r ue when it is t r ue t hat condit ions B and C bot h hold ? Use
Boolean algebr a t o just ify your answer.
110 S witching Theory
69. Wr it e down t he canonical s-of-p for m and t he p-of-s for m for t he logic expr ession
whose t r ut h t able is each of t he following.
(I) X
1
X
2
X
3
Z (II) A B C W
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 1 0 0 0 1 0 1
0 1 1 1 0 1 1 0
1 0 0 1 1 0 0 1
1 0 1 1 1 0 1 0
1 1 0 0 1 1 0 0
1 1 1 1 1 1 1 1
(III) W X Y Z F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 1 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
70. Use Quest ion 5.
(a) Using K-maps, obt ain t he simplified logic expressions for bot h s-of-p and p-of-s
for each t r ut h t able in t he quest ion 5 above.
(b) Fr om t he p-of-s expr essions, wor k backwar ds using a K-map t o obt ain t he
s-of-p canonical expr ession for each t r ut h t able.
71. Apply De-Mor gan’s t heor ems t o each expr ession
(a) A + B (b) AB (c) A + B + C (d) A B C
(e) A (B + C) (f) AB CD + (g) AB + CD (h)
(A + B) + C + D) (
Digital Design Fundamentals–Boolean Algebra and Logic Gates 111
(i) ( ( ABC) (EFG) HIJ ) (KLM) + (j)
A + BC CD BC + +
(k) ( ( ( ( A + B) C + D) E + F) G + H)
72. Conver t t he following expr essions t o sum-of-pr oduct s for ms:
(a) AB + CD (AB + CD) (b) AB (BC + BC) (c)
A + B [AC + (B + C) D]
73. Wr it e a Boolean expr ession for t he following
(a) X is a 1 only if a is a 1 and B is a 1 or if A is a 0 and B is a 0
(b) X is a 0 if any of t he t hr ee var iables A, B and C ar e 1’s. X is a 1 for all ot her
condit ions.
74. Dr aw logic cir cuit s using AND, OR and NOT element s t o r epr esent t he following
(a)
AB + AB
(b)
AB + AB + ABC
(c)
A + B [C + D(B + C)]
(d) A + BC + D(E + F ) (e)
(AB) (CD)
(f) [(A + B) (C + D)]E + FG
75. Use Dualit y t o der ive new Boolean ident it ies fr om t he ones you obt ained by
simplificat ion in t he pr evious quest ion.
76. Use De Mor gan’s Theor em t o complement t he following Boolean expr essions
(a) z = x y w v . ( . ) +
(b) z x y w y w v = + + . . . ( )
x
y
Pr ove t his imlement s XOR.
(c) z x y = +
(d) z x y w = + .
(e) z x y w = + ( ).
(f)
z x y w = + .
77. Using Boolean Algebr a ver ify t hat t he cir cuit in figur e 1 implement s an exclusive
OR (XOR) funct ion
(a) Express z
1
and z
2
as a sum of mint er ms
(b) Express z
1
and z
2
as a pr oduct of maxt er ms
(c) Simplify t he sum of t he mint erm for z
1
and z
2
using Boolean algebr a.
112 S witching Theory
3.0 INTRO DUC TIO N
The minimizat ion of combinat ional expr ession is consider ed t o be one of t he major st eps
in t he digit al design pr ocess. This emphasis on minimizat ion st ems fr om t he t ime when logic
gat es wer e ver y expensive and r equir ed a consider able amount of physical space and power.
However wit h t he advent of Int egr at ed cir cuit s (SSI, MSI, LSI and VLSI) t he t r adit ional
minimizat ion pr ocess has lessened somewhat , t her e is st ill a r easonable degr ee of cor r elat ion
bet ween minimizing gat e count and r educed package count .
It is ver y easy t o under st and t hat t he complexit y of logical implement at ion of a Boolean
funct ion is dir ect ly r elat ed t o t he complexit y of algebr aic expr ession fr om which it is imple-
ment ed.
Alt hough t he t r ut h t able r epr esent at ion of a Boolean funct ion is unique, but when
expr essed algebr aically, it can appear in many differ ent for ms.
Because of t he r eason ment ioned above, t he object ive of t his chapt er is t o develop an
under st anding of how moder n r educt ion t echniques have evolved fr om t he t ime consuming
mat hemat ical appr oach (Theor em r educt ion) t o quick gr aphical t echniques called ‘mapping’
and ‘t abular met hod’ for lar ge number of var iable in t he combinat ional expr ession.
3.1 M INIM IZATIO N USING PO STULATES AND THEO REM O F BO O LEAN ALG EBRA
The keys t o Boolean minimizat ion lie in t he t heor ems int r oduced in Chapt er 2. Sect ion
2.3.2. The ones of major int er est ar e t heor em member 6, 7 and 8.
Then, 6 (a) A + AB = A (b) A (A + B) = A Absorpt ion
7 (a) A + A′B = A + B (b) A (A′ + B) = AB
8 (a) AB + AB′ = A (b) (A + B) (A + B′) = A Logic Adjacency
Theor em 6 and 7 have special significance when applied t o expr ession in st andar d for m,
wher eas t heor em 8 is of par t icular impor t ance in simplifying canonical for m expr ession.
— Theor em 6 has a wood st at ement s—If a smaller term or expression is formed entirely
in a larger term, then the larger term is superfluous.
Theor em 6 can be applied only when an expr ession is in a ‘st andar d for m’, t hat is, one
t hat has at least one t er m which is not a MIN or MAX t er m.
112
3
CHAPTER
BOOLEAN FUNCTION
M INIM IZATION TECHNIQUES
Boolean Function Minimization Techniques 113
Example 3.1 F = CD + AB′C + ABC′ + BCD
Thm 6
[QA + AB = A]
= CD + AB′C + ABC′
⇒ Select one of t he smaller t er ms and examine t he lar ger t er ms which cont ain t his
smaller t er m.
— for applicat ion of Theor em 7, t he lar ger t er ms ar e scanned looking for of applicat ion
t he smaller in it s complement ed for m.
Example 3.2 F = AB + BEF + A′CD + B′CD
= AB + BEF + CD (A′ + B′)
= AB + BEF + CD (AB)′
Thm 7 → Using Demor gans’s
Theor em
= AB + BEF + CD (QA + A B = AB) ′
— Theor em 8 is t he basis of our next minimizat ion t echnique i.e., Kar naugh map
met hod. It has a wor d st at ement —‘If any two terms in a canonical or standard form expres-
sion vary in only one variable, and that variable in one term is the complement of the variable
in the other term then of the variable is superfluous to both terms.
Example 3.3 F = A′B′C′ + A′B′C + ABC′ + AB′C

Thm 8 Thm 8
F = A′B′ + AC
Example 3.4 F = A′B′C′ + AB′C′ + ABC′ + A′B′C

Th m 8
Th m 8
= A′B′ + AC′
By now it should become obvious t hat anot her t echniques is needed because t his t ech-
niques backs specific r ules t o pr edict each succeeding st ep in manipulat ive pr ocess.
Ther efor e, if we could develop some gr aphical t echnique wher eby t he applicat ion of
‘Theor em 8’ t he logical adjacency t heor em is made obvious and wher e t he desir ed gr ouping
could be plainly displayed, we would be in mind bet t er posit ion t o visualize t he pr oper
applicat ion of t heor em.
3.2 M INIM IZATIO N USING KARNAUG H M AP ( K- M AP) M ETHO D
In 1953 Maur ice Kar naugh developed K-map in his paper t it led ‘The map met hod for
synt hesis of combinat ional logic cir cuit s.
The map met hod pr ovides simple st r aight for war d pr ocedur e for minimizing Boolean
funct ions t hat may be r egar ded as pict or ial for m of t r ut h t able. K-map or der s and displays t he
114 S witching Theory
mint er ms in a geomet r ical pat t er n such t hat t he applicat ion of t he logic adjacency t heor em
becomes obvious.
— The K-map is a diagr am made up of squar es. Each squar e r epr esent s one mint er m.
— Since any funct ion can be expr essed as a sum of mint er ms, it follows t hat a Boolean
funct ion can be r ecognized fr om a map by t he ar ea enclosed by t hose squar es.
Whose mint er ms ar e included in t he oper at ion.
— By var ious pat t er ns, we can der ive alt er nat ive algebr aic expr ession for t he same
oper at ion, fr om which we can select t he simplest one. (One t hat has minimum
member of lit er als).
Now lest as st ar t wit h a t wo var iable K map.
3.2.1 Two a nd Three Va ria b le K M a p
If we examine a t wo var iable t r ut h t able, Fig. 3.2.1(a) we can make some gener al
obser vat ions t hat suppor t t he geomet r ic layout of K Map shown in Fig. 3.2.1(b).
Truth Table
Min-
term
INPUTS OUTPUTS
A B
0
0
1
1
0
1
0
1
Y
y
y
y
y
0
1
2
3
m
m
m
m
0
1
2
3
0
2
1
3
A
A

B′ B
or
y
y
0
2
0
1
0 1
y
y
1
3
B
A
(a) (b) (c)
Fig. 3.2.1 (a) (b) and (c)
The four squar es (0, 1, 2, 3) r epr esent t he four possibly combinat ions of A and B in a t wo
var iable t r ut h t able. Squar e 1 in t he K-map; t hen, st ands for A′B′, square 2 for A′B, and so
for t h. The map is r edr awn in Fig. 3.2.1(c) t o show t he r elat ion bet ween t he squar es and t he
t wo var iables. The 0’s and 1’s mar ked for each r ow and each column designat e t he values of
variables A and B r espect ively. A appear s pr imed in r ow 0 and unpr imed in r ow 1. Similar ly
B appear s pr imed in column 0 and unpr imed in column 1.
Now let us map a Boolean funct ion Y = A + B.
Met hod I—(i) Dr aw t he t r ut h t able of given funct ion.
Min-term A B Y
m
0
0 0 0
m
1
0 1 1
m
2
1 0 1
m
3
1 1 1
(ii) Dr aw a t wo var iable K map an fill t hose squar es wit h a 1 for which t he value of
mint er m in t he funct ion is equal t o 1.
1
1
1
0
1
0 1

m
m
0
2
0
1
0 1
m
m
1
3
B
A
B
A
The empt y squar e in t he map r epr esent t he value of mint er ms [m0 (or A′B′)] t hat is
equal t o zer o in t he funct ion. Thus, act ually t his empt y squar e r epr esent s zer o.
Boolean Function Minimization Techniques 115
Met hod II-(i) Find all t he mint er ms of t he funct ion Y = A + B.
Y = A + B = A(B + B′) + B(A + A′)
= AB + AB′ + AB + A′B
⇒ Y = AB + AB′ + A′B
(ii) Dr aw a t wo var iable K map using t his sum of mint er ms expr ession.
Y = AB + AB + A B ′ ′
↓ ↓ ↓
11 10 01 1
1
1
0
1
0 1
B
A
— These a K map, is not hing mor e t han an int er est ing looking Tr ut h-Table, and it simply
pr ovide a gr aphical display of ‘implicant s’ (mint er ms) involved in any SOP canonical or st and-
ar d for m expr ession.
Now examine a t hr ee var iable t r ut h t able shown in 3.2.1 (d).
Truth Table
Min term INPUTS OUTPUT
A B C Y
m
0
0 0 0 y
0
m
1
0 0 1 y
1
m
2
0 1 0 y
2
m
3
0 1 1 y
3
m
4
1 0 0 y
4
m
5
1 0 1 y
5
m
6
1 1 0 y
6
m
7
1 1 1 y
7
Fig. 3.2.1 (d)
Her e we need a K-map wit h 8 squar es r epr esent all t he combinat ion (Mint er ms) of input
variables A, B and C dist inct ly. A t hr ee-var iable map is shown in Fig. 3.2.1 (e).
m
m
0
4
0
1
00 01
m
m
1
5
BC
A
m
m
3
7
m
m
2
6
11 10
Fig. 3.2.1 (e)
It is ver y impor t ant t o r ealize t hat in t he t hr ee var iable K-map of Fig. 3.2.1 (e), t he
mint er ms ar e not ar r anged in a binar y sequence, but similar t o ‘Gr ay Code’ sequence.
The gr ay code sequence is a unit dist ance sequence t hat means only one bit changes in
list ing sequence.
116 S witching Theory
Our basic object ive in using K-map is t he simplify t he Boolean funct ion t o minimum
number of lit er als. The gr ay code sequencing gr eat ly helps in applying. ‘Logic Adjacency
t heor em’ t o adjacent squar es t hat r educes number of lit er als.
The map is Fig. 3.2.1 (e) is r edr awn in Fig. 3.2.1 (f) t hat will be helpful t o make t he
pict ur es clear.
A B C′ ′ ′ 0
1
00 01
BC
A
11 10
A B C ′ ′ A BC ′ A BC ′ ′
AB C′ ′ AB C ′ ABC ABC′
Fig. 3.2.1 (f)
We can see t hat any t wo adjacent squar es in t he map differ by only one var iable, which
is pr imed in one squar e and unpr imed in ot her.
For example m
3
(A′BC) and m
7
(ABC) ar e t wo adjacent squar es. Variable A is pr imed in
m
3
and unprimed in m
7
, wher eas t he ot her t wo var iables ar e same in bot h squar es. Now
applying ‘logic adjacency’ t heor em, it is simplified t o a single AND t er m of only t wo lit er als.
To clar ify t his, consider t he sum of m
3
and m
7
→ m
3
+ m
7
= A′BC + ABC = BC(A + A′) = BC.
3.2.2 Boole a n Exp re ssion M inimiza tion Using K- M a p
1. Const r uct t he K-map as discussed. Ent er 1 in t hose squar es cor r esponding t o t he
mint er ms for which funct ion value is 1. Leave empt y t he r emaining squar es. Now
in following steps the square means the square with a value 1.
2. Examine t he map for squar es t hat can not be combined wit h any ot her squar es and
fr om gr oup of such signal squar es.
3. Now, look for squar es which ar e adjacent t o only one ot her squar e and for m gr oups
cont aining only t wo squar es and which ar e not par t of any gr oup of 4 or 8 squar es.
A gr oup of t wo squar es is called a pair.
4. Next , Gr oup t he squar es which r esult in gr oups of 4 squar es but ar e not par t of
an 8-squar es gr oup. A gr oup of 4 squar es is called a quad.
5. Gr oup t he squar es which r esult in gr oups of 8 squar es. A gr oup of 8 squar es is
called octet.
6. For m mor e pair s, quads and out let s t o include t hose squar es t hat have not yet been
gr ouped, and use only a minimum no. of gr oups. Ther e can be over lapping of
gr oups if t hey include common squar es.
7. Omit any r edundant gr oup.
8. For m t he logical sum of all t he t er ms gener at ed by each gr oup.
Using Logic Adjacency Theorem we can conclude that,
— a gr oup of t wo squar es eliminat es one var iable,
— a gr oup of four sqs. eliminat es t wo var iable and a gr oup of eight squar es eliminat es
t hr ee var iables.
Now let us do some examples t o lear n t he pr ocedur e.
Example 3.2. S implify the boolean for F = AB + AB′ + A′B. Using two variable K-map.
This function can also be written as
F(A, B) = Σ(1, 2, 3)
Boolean Function Minimization Techniques 117
Solution. Step 1. Make a t wo var iable K-map and ent er 1 in squar es cor r esponding t o
mint er ms pr esent in t he expr ession and leave empt y t he r emaining squar es.
m
m
0
2
0
1
0 1
m
m
1
3
B
A
Step 2. Ther e ar e no 1’s which ar e not adjacent t o ot her 1’s. So t his st ep is discar ded.
1
1
1
0
1
0 1
B
A
Step 3. m
1
is adjacent t o m
3
⇒ for ms a gr oup of t wo squar es and is not par t of any gr oup
of 4 squar es. [A gr oup of 8 squar es is not possible in t his case].
1
1
1
0
1
0 1
B
A
Similarly m
2
is also adjacent t o m
3
⇒ for ms anot her gr oup of t wo squar es and is not a
par t of any gr oup of 4 squar es.
Step 4 and 5. Discar ded because t hese in no quad or out let .
Step 6. All t he 1’s have alr eady been gr ouped.
Ther e is an over lapping of gr oups because t hey include common mint er m m
3
.
Step 7. Ther e is no r edundant gr oup.
Step 8. The t er ms gener at ed by t he t wo gr oups ar e ‘OR’ oper at ed t oget her t o obt ain t he
expr ession for F as follows:
F = A + B
↓ ↓
Fr om Fr om gr oup
group m
2
m
3
m
1
m
3
↓ ↓
This r ow is This column is
cor r esponding cor r esponding t o
t o t he value t he value of B is
of A is equal equal t o 1.
t o 1.
Example 3.3. S implify the Boolean function F (A, B, C) = Σ (3, 4, 6, 7).
Solution. Step 1. Const r uct K-map.
Ther e ar e cases wher e t wo squar es in t he map ar e consider ed t o be adjacent even
t hr ough t hey do not t ouch each ot her. In a t hr ee var K-map, m
0
is adjacent t o m
2
and m
4
is adjacent t o m
6
.
118 S witching Theory
Algebraically m
0
+ m
2
= A′B′C′ + A′BC′ = A′C′
and m
4
+ m
6
= AB′C′ + ABC′ = AC′
m
m
0
4
0
1
00 01
m
m
2
5
BC
A
m
m
3
7
m
m
2
6
11 10
Consequent ly, we must modify t he definit ion of adjacent squar es t o include t his and ot her
similar cases. This we can under st and by consider ing t hat t he map is dr awn on a sur face
wher e t he r ight and left edges t ough each ot her t o for m adjacent squar es.
Step 2. Ther e ar e no 1’s which ar e not adjacent t o ot her 1’s so t his st ep is discar ded.
m

m
0
4
0
1
00 01
m
m
2
5
BC
A
m
m
3
7
m
m
2
6
11 10
1 1
1
1
Step 3. m
3
is adjacent t o m
7
. It for ms a gr oup of t wo squar es and is not a par t of any
gr oup of 4 or 8 squar es.
Similarly m
6
is adjacent t o m
7
. So t his is second gr oup (pair ) t hat is not a par t of any
gr oup of 4 or 8 squar es.
Now accor ding t o new definit ion of adjacency m
4
and m
6
ar e also adjacent and for m a
pair. Mor eover, t his pair (gr oup) is not a par t of any gr oup of 4 or 8 sqs.
Step 4 and 5. Discar ded, because no quad or oct et is possible.
Step 6. All t he 1’s have alr eady been gr ouped. These is an over lapping of gr oups because
t hey include a common mint erm m
7
.
Step 7. The pair formed b m
6
m
7
is redundant because m
6
is alr eady cover ed in pair
m
4
m
6
and m
7
in pair m
3
m
7
. Therefore, t he pair m
6
m
7
is discar ded.
Step 8. The t er ms gener at ed by t he r emaining t wo gr oups ar e ‘OR’ oper at ed t oget her
t o obt ain t he expr ession for F as follows:
F = AC′ + BC
↓ ↓
From group m
4
m
6
From group m
3
m
7
.
The r ow is cor r esponding Cor r espond t o bot h r ows
t o t he value of A = 1 and (⇒ A = 0 and A = 1) so A
in t he t wo columns (00 → is omit t ed, and single
B′C′ and t he 10 → BC′), t he column (⇒ B = 1 and C = 1),
value C = 0 ⇒ C′ is common ⇒ BC.
= AC′
Wit h a lit t le mor e pr act ice, you can make your self comfor t able in minimizat ion using K-
map t echnique. Then you have no used t o wr it e all t he st eps. You can dir ect ly minimize t he
given funct ion by dr awing simply t he map.
Now let us do one mor e example of a t hr ee var iable K-map.
Boolean Function Minimization Techniques 119
Example 3.4. S imply the following Boolean function by first expressing it in sum of
minterms.
F = A′B + BC′ + B′C′
Solution. The given Boolean expr ession is a funct ion of t hr ee var iables A, B and C. The
t hr ee pr oduct t er ms in t he expr ession have t wo lit er als and ar e r epr esent ed in a t hr ee
var iable map by t wo squar es each.
The t wo squar es cor r esponding t o t he fir st t er ms A′B ar e for med in map fr om t he
coincidence of A′ (⇒ A = 0, fir st r ow) and B (t wo last columns) t o gives squar es 011 and 010.
1
1
0
1
00 01
BC
A
1 1
1
11 10
B C′ ′ A B ′ BC′
Not e t hat when mar king 1’s in t he squar es, it is possible t o find a 1 alr eady placed t her e
fr om a pr eceding t er m. This happens wit h t he second t her m BC′, has 1’s in t he sqs. which
010 and 110, t he sq. 010 is common wit h t he fir st t er m A′B, so only one squar e (cor r esponding
t o 110) is mar ked 1.
Similar ly, t he t hir d t er m B′C′ cor r esponds t o column 00 t hat is squar es 000 and 100.
The funct ion has a t ot al of five mint er ms, as indicat ed by five 1’s in t he map. These ar e
0, 2, 3, 4 and 6. So t he funct ion can be expr essed in sum of mint er ms t er m:
F (A, B, C) = Σ(0, 2, 3, 4, 6)
Now, for t he simplificat ion pur pose, let us r edr aw t he map dr awn above:
1
1
0
1
00 01
BC
A
1 1
1
11 10
Fir st we combine t he four adjacent squar es in t he fir st and last columns t o given t he
single lit er al t er m C′.
The r emaining single squar e r epr esent ing mint er m 3 is combined wit h an adjacent
squar e t hat has alr eady been used once. This is not only per missible but r at her desir able
since t he t wo adjacent squar es give t he t wo lit er al t er m A′B and t he single sq. r epr esent t he
t hree lit eral mint erm A′BC. The simplified funct ion is t her efor e,
F = A′B + C′
3.2.3 M inimiza tion in Prod uc ts of Sums Form
So far, we have seen in all pr evious examples t hat t he minimized funct ion wer e ex-
pr essed in sum of pr oduct s for m. Wit h a minor modificat ion, pr oduct of sums (POS) for m can
be obt ained. The pr ocess is as follows:
1. Dr aw map as for SOP; mar k t he 0 ent r ies. The 1’s places in t he squar es r epr esent s
mint er ms of t he funct ion. The mint er ms not included in t he funct ion denot e t he
complement of t he funct ion. Thus t he complement of a funct ion is r epr esent ed on
t he map by t he squar es mar ked by 0’s.
2. Gr oup 0 ent r ies as you gr oup 1 ent r ies for a SOP r eading, t o det er mine t he
simplified SOP expr ession for F′.
120 S witching Theory
3. Use De Mor gan’s t heor em on F′ t o pr oduce t he simplified expr ession in POS for m.
Example 3.5. Given the following Boolean function:
F = A′C + A′B + AB′C + BC
Find t he simplified pr oduct s of sum (POS) expr ession.
Solution. Step 1. We dr aw a t hr ee var iable K-map. Fr om t he given funct ion we obser ve
t hat mint er ms 1, 2, 3, 5, and 7 ar e having t he value 1 and r emaining mint er ms i.e., 0, 4 and
6 ar e 0. So we mar k t he 0 ent r ies.
0
0
0
1
00 01
BC
A
1
1
1
0
11 10
1
1
Step 2. Mint er ms 0 and 4 for ms a pair, giving value = B′C′. Similar ly mint er ms 4 and
6 for ms a second pair giving value = AC′. Ther efor e we get F′ = AC′ + B′C′.
Step 3. Applying De Mor gan’s t heor em aut omat ically conver t s SOP expr ession int o POS
expr ession, giving t he value of F
⇒ (F′)′ = [AC′ + B′C′]′
⇒ F = [(AC′)′ . (B′C′)′]
⇒ F = (A + C) . (B + C)
3.2.4 Four Va ria b le K- M a p
Let us examine a four var iable t r ut h t able shown is Fig. We used a K-map wit h 16
squar es t o r epr esent all t he mint er ms of input var iables A, B, C and D dist inct ly. A four-
var iable K-map is shown in fig.
m
m
0
4
00
01
11
10
00 01
m
m
1
5
BC
AB
m
m
3
7
m
m
2
6
11 10
m
m
12
8
m
m
13
9
m
m
15
11
m
m
14
10
Truth Table
Minterm Inputs Output
A B C D Y
m
0
0 0 0 0 y
0
m
1
0 0 0 1 y
1
m
2
0 0 1 0 y
2
m
3
0 0 1 1 y
3
m
4
0 1 0 0 y
4
m
5
0 1 0 1 y
5
m
6
0 1 1 0 y
6
Boolean Function Minimization Techniques 121
Minterm Inputs Output
A B C D Y
m
7
0 1 1 1 y
7
m
8
1 0 0 0 y
8
m
9
1 0 0 1 y
9
m
10
1 0 1 0 y
10
m
11
1 0 1 1 y
11
m
12
1 1 0 0 y
12
m
13
1 1 0 1 y
13
m
14
1 1 1 0 y
14
m
15
1 1 1 1 y
15
The r ows and column ar e number ed in a r eflect ed-code sequence, wit h only one digit
changing value bet ween t wo adjacent r ows or columns.
The minimizat ion pr ocess is similar as well have done in a t hr ee var iable K-Map. How-
ever t he definit ion of adjacency can fur t her be ext ended. Consider ing t he map t o be on a
sur face wit h t he t op and bot t om edges, as well as sight and left edges, t ouching each ot her
of for m adjacent squar es.
For example m
0
is adjacent t o m
2
, m
4
as well as t o m
8
, similarly m
3
is adjacent t o m
1
,
m
2
, m
7
as will as t o m
11
and so on.
Example 3.6. S implify the given fraction.
F = ABCD + AB′C′D′ + AB′C + AB
Solution. Step 1. The given function is consisting of four variables A, B, C and D. We draw
a four variable K-map. The first t wo t erms in t he funct ion have fours lit erals and are repeat ed
in a four variable map by one square each. The squar e corresponding to first term ABCD is
equivalent t o mint erm 1111. (m
15
). Similarly the square for second term AB′C′D′ is equivalent
t o mint erm 1000 (m
8
) t he t hird t erm in t he funct ion has t hree lit erals and is represent ed in a
four var map by t wo adjacent squares. AB' corresponds t o 4t h row (i.e. 10) in t he map and C
corresponds t o last t wo columns (i.e. 11 and 10) in t he map. The last term AB has t wo (A t erm
with only one literal is represented by 8 adjacent squar e in map. Finally a 1 in all 16 squares
give F = 1. It means all t he mint erms are having t he value equal t o 1 in t he funct ion). Lit erals
and is represent ed by 4 adjacent squares. Here AB simply corresponds to 3
rd
row (i.e., AB = 11).
m
m
0
4
00
01
11
10
00 01
m
m
1
5
CD
AB
m
m
3
7
m
m
2
6
11 10
m
m
12
8
m
m
13
9
m
m
15
11
m
m
14
10
1 1 1 1
1 1 1
AB
ABCD
AB C ′
AB C D′ ′ ′
Now let us r edr aw t he map fir st for simplificat ion pur pose.
122 S witching Theory
Step 2. Is discar ded. (No 1’s which ar e not adjacent t o ot her 1’s)
Step 3. Discar d (No pair s which ar e not par t of any lar ger gr oup)
Step 4. Ther e ar e t hr ee quads.
Mint er ms 8, 10, 12, 14 fr om fir st quad.
Mint er ms 12, 13, 14, 15 for m second quad
and Mint er ms 10, 11, 14, 15 for m t hir d quad.
Step 5. Discar ded. (No oct ages)
Step 6. Discar ded (All 1’s have been gr ouped.)
Step 7. Discar d (No r edundant t er m)
Step 8. The t er ms gener at ed by t hr ee gr oups one ‘OR’ oper at ed as follow
F = AD′ + AB + AC.
↓ ↓ ↓
Fr om Second Third
Fir st gr oup gr oup.
group
Example 3.7. Obtain (a) minimal sum of product (b) minimal product of sum expression
for the function given below:
F(w, x y, z) = ∈ (0, 2, 3, 6, 7, 8, 10, 11, 12, 15).
Solution. The given funct ion can also be wr it t en in pr oduct of mint er m for m as
F(w, x, y, z) = ∏ (1, 4, 5, 9, 13, 14).
Squar es wit h 1’s ar e gr ouped t o obt ain minimal sum of pr oduct ; squar e wit h 0’s ar e
gr ouped t o obt ain minimal pr oduct of sum, as shown.
00
01
11
10
00 01
YZ
WX
11 10
1
1 1
1
1 1
1
1 1
1
(a) We draw a four variable map using mint er ms whose values in the funct ion are equal to 1.
– Mint er m 8 and 12. Four a pair.
– Mint er ms 0, 2, 8 and 10 for m I quad.
– Mint er ms 3, 7, 11, 15 for m II quad.
– Mint er ms 2, 3, 6, 7 for m III quad.
Ther efor e, F = x' z + yz + w' y + wy' z'
↓ ↓ ↓ ↓
Due t o II quad III quad Due t o pair
I quad.
(b) We dr aw a four var iable map using mint er ms whose values in t he funct ion ar e equal
t o zer o. These mint er ms ar e 1, 4, 5, 9, 13 and 14.
00
01
11
10
00 01
CD
AB
11 10
1 1 1 1
1 1 1
Boolean Function Minimization Techniques 123
00
01
11
10
00 01
YZ
WX
11 10
0
0
0
0
0
0
– Mint er m 14 can not be combined wit h any ot her squar e in t he map 4 four s a gr oup
wit h single squar es.
– Mint er ms 4 and 5 for m a pair.
– Mint er ms 1, 5, 9 and 13 for m a quad.
Ther efor e, F' = wxyz' + w'xy' + y'z
Applying De Mor gan's t heor em
(F')' = [wxyz′ + w′xy′ + y′z]′
⇒ F = (wxyz')' . w'xy'. (y'z)'
⇒ F = (w' + x'y'

+ z). (w + x' + y). (y + z').
3.2.5 Prime a nd Esse ntia l Imp lic a nts
So far we have seen a met hod for drawing and minimising Karnaugh maps in such a way
t hat unnecessary (redundant ) groupings can be avoided. Now let us est ablish some import ant
definit ions t hat will be used t o a syst emat ic procedure for combining squares in t he process of
K-map minimizat ion. To do t his, consider a funct ion defined as F (A, B, C, D) = Σ(0, 1, 2, 3,
5, 7, 8, 9, 10, 13, 15). Now we will analyze t he grouping shown in t he 4 variable map in Fig.
m
m
0
4
00
01
11
10
00 01
m
m
1
5
CD
AB
m
m
3
7
m
m
2
6
11 10
m
m
12
8
m
m
13
9
m
m
15
11
m
m
14
10
1
1 1
1 1
1
1 1
1 1 1
Her e we see t hat all r ealist ic gr oupings ar e shown. Not e fur t her t hat each gr oup is
sufficient ly lar ge t hat is can not be complet ely cover ed by any ot her simple gr ouping. Each
of t hese five gr oupings is defined as a Pr ime implicant .
I group → covering mint erms → 0, 2, 8, and 10, → B′D′
II group → covering mint erms → 0, 1, 2, and 3 → A′B′
III group → covering mint erms → 1, 5, 9, and 13 → C′D′
IV group → covering mint erms → 1, 3, 5 and 7 → A′D′
V group → covering mint erms → 5, 7, 9 and 15 → B′D′
IV group → covering mint erms → 0, 1, 8, 9 → B′C′
124 S witching Theory
Thus ‘a pri me i mpli cant i s a product term (or mi nterm) obtai ned by combi ni ng
the maxi mum possi ble number of adjacent squares i n the map.
As we examine t he set of pr ime implicat es t hat cover t his map, it becomes obvious t hat
some of t he ent r ies can be gr ouped in only one way. (Single way gr oupings). For example
t her e is only one way t o gr oup m
10
wit h 4 adjacent squar es. (⇒ I gr oup only). Similar ly t her e
is only one way t o gr oup m
15
wit h t he adjacent squar e (⇒ V gr oup only). The r esult ant t er ms
fr om t hese gr oupings ar e defined as essent ial pr ime implicant s.
Thus, ‘i f a mi nterm i n a square i s covered by only one pri me i mpli cant, the
pri me i mpli cant i s sai d to be essenti al’. The t wo essent ial prime implicant ⇒ B′D′ and
BD cover 8 mint er ms. The r emaining t hr ee viz m
1
, m
3
and m
9
must be consider ed next .
The prime implicant t able shows t hat m
3
can be covered eit her wit h A'B' or wit h A′D.
m
9
can be cover ed eit her wit h C'D or wit h B′C′.
m
1
can be cover ed wit h any of for m pr ime implicat es A'B' , A' D, B' C' or C'D.
Now t he simplified expr ession is obt ained for m t he sum of t wo essent ials pr ime impli-
cat es and t wo pr ime implicant t hat cover mint er ms. m
1
, m
3
, and m
9
. It means t her e one four
possible ways t o wr it e t he simplified expr ession.
(a) BD + B'D' + A' B' + C' D
(b) BD + B'D' + A' B' + B' C'
(c) BD + B' D' + A'D + C'D
(d) BD + B' D' + A'D + B' C'
The simplified expr ession is t hus obt ained fr om t he logical sum of all t he essent ial pr ime
implicant s plus t he pr ime implicant s t hat may be needed t o cover any r emaining mint er ms
not cover ed by simplified pr ime implicant s.
3.2.6 Don’t c a re M a p Entrie s
Many t imes in digit al syst em design,
some input combinat ions must be consid-
er ed as cases t hat “J ust don't happen”, and
t her e ar e cases when t he occur r ence of par -
t icular combinat ions will have no effect on
t he syst em, and if t hose combinat ions do
occur, “you don’t car e”. For example, con-
sider t he case wher e t he out put s of a 4-bit
binar y count er ; which happens t o home a
possible r ange fr om 0000 t o 1111, is t o be
conver t ed t o a decimal display having t he
r ange of 0, 1, 2, ....., 9. The conver t er might
be a digit al syst em having binary 4-bit in-
put s and decimal upt o as shown Fig. 3.2.6.
In this par t icular case, the input combina-
t ions 1001, 1010, 1011, 1100, 1101, 1110, 1111
are t o be considered by combinat ions t hat
just can not be accept ed by t he digit al sys-
t em if it is funct ion pr oper ly.
Digital
system
converting
4 bit binary
number to
a Decimal
number
0
1
2
3
4
5
6
7
8
9
0000
0001
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
9
10
11
12
13
14
15
Fi g. 3.2.6
Boolean Function Minimization Techniques 125
Ther efor e, when t his digit al syst em is being designed, t hese mint er ms in t he map ar e
t r eat ed in a special way. That is a φ or a or × (cr oss) is ent er ed int o each squar e t o signify
“don't care” MIN/MAX t er ms.
Reading a map, or gr ouping a map wit h don’t car e ent r ies is a simple pr ocess.
‘Group t he φ don’t care ⇒ x) wit h a 1 gr ouping if and only if t his gr ouping will r esult in
gr eat er, simplificat ion; ot her wise t r eat it as if it wer e a 0 ent r y.
Example 3.8. S implify the following Boolean function.
F (A, B, C, D) = Σ (0, 1, 2, 10, 11, 14)
d (5, 8, 9)
Solution. The K-map for t he given funct ion is shown wit h ent r ies X (don’t car e) in
squar es cor r esponding t o combinat ions 5, 8 and 9.
00
01
11
10
00 01
CD
AB
11 10
1
X 1 1
1 1 1
X
X
As discussed above, t he 1’s and d’s (Xs) ar e combined in or der t o enclose t he maximum
number of adjacent squar es wit h 1. As shown in K-map in Fig (), by combining 1’s and d’s (Xs),
t hr ee quads can be obt ained. The X in squar e 5 is left fr ee since it doss not cont r ibut e in
incr easing t he size of any gr oup. Ther efor e t he
I Quad cor es mint er ms 0, 2, 10 and d8
II Quad cor es mint er ms 0, 1 and d 8, 9.
III Quad cor es mint er ms 0, 1 and d 8, 9.
A pair cover s mint er ms 10 and 14.
So, F = B'D + AB' + B'C' + ACD'
Due II III Due
t o I quad Quad t o
quad. Pair.
3.2.7 Five Va ria b le K- M a p
The Kar naugh map becomes t hr ee dimensional when solving logic pr oblems wit h mar e
t han four var iables. A t hr ee dimensional K-map will be used in t his sect ion.
0
4
12
8
00
01
11
10
00 01
1
5
13
9
DE
BC
11 10
3
7
15
11
2
6
14
10
A = 0
16
20
28
24
00
01
11
10
00 01
17
21
29
25
DE
BC
11 10
19
23
31
27
18
22
30
26
A = 1
126 S witching Theory
The 5 var iable M-map cont ains 25 = 32 squar es. Inst ead of r epr esent ing a single 32-
squar e map, t wo 16-squar e K-maps ar e gener ally used. If t he var iable ar e A, B, C, D and E,
t he t wo ident ical 16-squar e maps cont ain B, C, D and E var iable wit h one 16-sq. map for A
= 1 and ot her 16-square map for A = 0 ⇒ (A). This is shown in Fig. 3.2.7 (a)
0
4
1
2
8
0
0
0
1
1
1
1
0
0
0
0
1
1
5
1
3
9
D
E
B
C
1
1
1
0
3
7
1
5
1
1
2
6
1
4
1
0
A = 0
1
6
2
0
2
8
2
4
0
0
0
1
1
1
1
0
0
0
0
1
1
7
2
1
2
9
2
5
D
E
B
C
1
1
1
0
1
9
2
3
3
1
2
7
1
8
2
2
3
0
2
6
A = 1
Fig. 3.2.7 (a)
The minimizat ion pr ocedur e descr ibed so far wit h r espect t o funct ions of t wo, t hr ee or
four var iables. Can be ext ended t o t he case of five var iables.
It is not ed t hat in or der t o ident ify t he adjacent gr ouping in t he 5-var iable maps, we must
imagine t hat t he t wo maps ar e super imposed on one anot her as shown. Ever y squar e in one
map is adjacent t o t he cor r esponding squar e in t he ot her map, because only one var iable,
changes bet ween such cor r esponding squar es. Thus r ows and columns for one map is adja-
cent t o t he cor r esponding r ow and column on t he ot her map and same r ules ar e used for
adjancencies wit h in one 16 squar e map. This is illust r at e in figur e:
DE
BC
Adjacent
Rows
Adjacent
Rows
Adjacent Groups
Adjacent cells
Adjacent columns
DE
BC
A =1 A =0
Fig. 3.2.7 (b)
Boolean Function Minimization Techniques 127
Example 3.9. S implify the given function.
F(A, B, C, D, E) = E (0, 4, 7, 8, 9, 10, 11, 16, 24, 25, 26, 27, 29, 31)
Solution. We make t wo 4-var iable maps and fill mint er ms 0-15 in map cor r esponding
to A = 0 and 16 t o 31 cor r esponding t o A = 1
1
1
1
00
01
11
10
00 01
1
DE
BC
11 10
1
1 1
Subcube
4
Subcube
5
Subcube
3
Subcube
1
1
1
00
01
11
10
00 01
1
1
DE
BC
11 10
1
1 1
Subcube
2
A = 0 A = 1
We have 5-subcubes aft er gr ouping adjacent squar es.
Subcube 1 is an oct at e which gives BC'
Subcube 2 is a qued which gives ABC' → In t he map corresponding t o A = 1
Subcube 3 is a pair which gives B'C'D' E'
Subcube 4 is a pair which gives A'B'C'E' → In t he map corresponding t o A = 0
Subcube 5 is a single squar es which gives A'B'C'D'E → In t he map cor r esponding t o A = 0.
⇒ F (A, B, C, D, E) = BC' + ABC' + B'C'D'B' + A'B'D'E' + A'B'C'D' E
3.2.8 Six va ria ble K- M a p
A six variable K-map cont ains 2
6
= 64 squares. These square are divided int o four ident ical
16-square maps as shown in Fig. 3.2.8 (a). It t he variables are A, B, C, D, E and F, t hen each
16 square map cont ains C, D, E, and F as variables along wit h anyone of 4 combinat ions of A
and B.
0
4
12
8
00
01
11
10
00 01
1
5
13
9
EF
CD
11 10
3
7
15
11
2
6
14
10
16
20
28
24
00
01
11
10
00 01
17
21
29
25
EF
CD
11 10
19
23
31
27
18
22
30
26
AB = 00 AB = 01
32
36
44
40
00
01
11
10
00 01
33
37
45
41
EF
CD
11 10
35
39
47
43
34
38
46
42
48
52
60
56
00
01
11
10
00 01
49
53
61
57
EF
CD
11 10
51
55
63
59
50
54
62
58
AB = 10 AB = 11
Fig. 3.2.8 (a)
128 S witching Theory
In or der t o ident ify t he adjacent gr oupings in t he 6-var iable maps, we must imagine t hat
t he 4 maps ar e super imposed on one anot her. Figur e shows differ ent possible adjacent squar es:
00
01
11
10
00 01
EF
CD
11 10 00
EF
CD
EF
CD
EF
CD
AB = 10 AB = 11
Adjaent
cells
(B C D E F ) ′ ′ ′ ′ ′
Adjacent
Queds
(C E) ′
Adjacent
Octates
(B E) ′
Adjacent columns
(AEF ) ′
Adjacent Rows
(ACD ) ′
AB = 00 AB = 01
Fig. 3.2.8 (b)
Example 3.10. S implify the given Boolean function.
F(A, B, C, D, E, F) = Σ(0, 4, 8, 12, 26, 27, 30, 31, 32, 36, 40, 44, 62, 63)
Solution. We make four 4-var ibale maps and fill t he ment ions 0-15 in map cor r espond-
ing t o AB = 00, 16-31 corresponding t o AB = 01, 32 – 47 corresponding t o AB = 10 and 48 t o
63 corresponding t o A B = 11.
1
1
1
1
00
01
11
10
00 01
EF
CD
11 10
00
01
11
10
00 01
EF
CD
11 10
AB = 00 AB = 01
1
1
1
1
00
01
11
10
00 01
EF
CD
11 10
00
01
11
10
00 01
EF
CD
11 10
1
1
AB = 10 AB = 11
1
1
1
1
1
1
Subcube
1 of
Two
Quads
Subcube 3 of
two pairs
Subcube 2
of one quad
Boolean Function Minimization Techniques 129
We have 3-subcubes aft er gr ouping adjacent squar e.
1. Subcubes 1 cont ains t wo quads gives B'E'F'
2. subcube 2 is for m of one quad gives A'BCE
3. subcube 3 is for m of t wo pair s gives BCDE
⇒ F(A, B, C, D, E, F) = B'EF' + A'BCE + BCDE.
Maps wit h seven or mor e var iables needs t oo many squar es and ar e impr act ical t o use.
The alt er nat ive is t o employ comput er pr ogr ams specifically wr it t en t o facilit at e t he simpli-
ficat ion of Boolean funct ions wit h a lar ge number of var iables.
3.2.9 M ulti O utp ut M inimiza tion
Finding t he opt imal cover for a syst em of out put expr essions all of which ar e a funct ion
of t he some var iables is somewhat t edious t ask. This t ask is basically one of ident ifying all
possible PIs t hat cover each implicat ed mint er m in each O/P expr ession, t hen car r ying out
a sear ch for t he minimal cost cover by using ‘shar ed’ t er ms.
Suppose you wer e given t he following syst em of expr essions and asked t o find t he
opt imal cover for t he complet e syst em, implying t hat you must find how t o opt imally shar e
t er ms bet ween t he expr essions.
F
1
(A, B, C) = Σ (0, 2, 3, 5, 6)
F
2
(A, B, C) = Σ (1, 2, 3, 4, 7)
F
3
(A, B, C) = Σ (2, 3, 4, 5, 6)
⇒ we fir st gener at e t he maps for t hr ee expr essions as shown
1
1
0
1
00 01
BC
A
1 1
1
11 10
F
1
1
0
1
00 01
BC
A
1 1
1
11 10
F
2
1
1
0
1
00 01
BC
A
1 1
1
11 10
F
3
1
Then we make up an implicant t able as shown in Fig. 3.2.9, showing how each mint er m
can be cover ed:
Mint er m F
1
F
2
F
3
m
0
A' B' C'/ A'C' – –
m
1
– A'B'C'/ A'C' –
m
2
A'B'C'/ A' B /A' C' /BC' A' BC'/ A'B A' BC' A'B' B' C'
m
3
A' BC/ A' B A' BC/ A'B /A' C/BC A' BC/ A'B
m
4
– AB'C' AB'C' / AB' /AC'
m
5
AB'C – AB'C / AB' /AC'
m
6
AB'C – AB'C / AC' /AC'
m
7
ABC/ BC –
Fig. 3.2.9 Implicant Table
130 S witching Theory
We for st scan t he t able for r ows wit h only a single ent r y. These ar e r elat ed t o essent ial
implicant s (m
0
, m
1
, m
7
). We t ake t he lar gest gr ouping and updat e t he t able (In t able by
making cir cle).
Next scan t he r ows for t hose which have t wo ent r ies, select ing t he funct ions t hat have
only a single way gr ouping opt ion (m
4
under F
2
and m
5
and m
b
under F
1
). It means have
t o find t he common t ur n. We t ake t he common t er m and updat e t he t able (In t able by making
ovals).
Finally, scan t he r ows for t hose r ows which have t wo ent r ies, select ing t he funct ions t hat
have only a single way gr ouping opt ion or we find t he common t er m. We t ake t he common
t er m and updat e t he t able (In t able by making r ect angular boxes).
Now using implicant t able, t he t hr ee funct ions can be wr it t en as:
F
1
= A C + A B + A B + AB C + BC ′ ′ ′ ′ ′ ′
= A C + A B + BC + AB C ′ ′ ′ ′ ′
F
2
= A C + A B + A B + AB C + BC ′ ′ ′ ′ ′
= A C + A B + AB C + BC ′ ′ ′ ′
F
3
= A B + A B + AB C + BC ′ ′ ′ ′
= A B + BC + AB C + AB C ′ ′ ′ ′ ′
We see; F
3
is t ot ally gener at ed fr om shar ed t er ms fr om F
1
and F
2
wit h consider able
saving over a combinat ional funct ion by funct ion r educt ion.
In summar y, we can say t hat many t imes mult iple out put s ar e der ived fr om t he same
input var iables. In t his case, we simplify and dr aw logic diagr am of each funct ion separ at ely.
Somet imes, t he simplified out put funct ions may have common t er ms. The common t er m used
by one O/P funct ion can be shar ed by ot her out put funct ions. This shar ing of common t er ms
r educes t he t ot al number of gat es.
3.3 M INIM IZATIO N USING Q UINE- M C C LUSKEY ( TABULAR) M ETHO D
The K-map met hod is suit able for simplificat ion of Boolean funct ions up t o 5 or 6
var iables. As t he number of var iables incr eases beyond t his, t he visualizat ion of adjacent
squar es is difficult as t he geomet r y is mor e involved.
The ‘Quine-McCluskey’ or ‘Tabular ’ met hod is employed in such cases. This it a syst em-
at ic st ep by st ep pr ocedur e for minimizing a Boolean expr ession in st andar d for m.
Proc e d ure for Find ing the M inima l Exp re ssion
1. Ar r ange all mint er ms in gr oups, such t hat all t er ms in t he same gr oup have same
number of 1’s in t heir binar y r epr esent at ion. St ar t wit h t he least number of 1’s and
cont inue wit h gr ouping of incr easing number of 1’s t he number of 1’s in each t er m
is called t he index of t hat t er m i.e., all t he mint er ms of some index ar e placed in
a some gr oup. The lowest of value index is zer o. Separ at e each gr oup by a t hick
line. This const it ut es t he I st age.
2. Compar e ever y t er m of t he Lowest index (say i) gr oup wit h each t er m in t he
successive gr oup of index (say, i + 1). If t wo mint er ms differ only one var iable, t hat
var iable should be r emoved and a dash (–) is placed at t he posit ion, t hus a new t er m
wit h only less lit er al is for med. If such a sit uat ion occur s, a check mar k () is
Boolean Function Minimization Techniques 131
placed next t o bot h mint er ms. Aft er all pair s of t er ms wit h indices i and (i + 1) have
been consider ed, a t hick line is dr awn under t he last t er ms.
When t he above pr ocess has been r epeat ed for all t he gr oups of I st age, one st age
of eliminat ion have been complet ed. This const it ut es t he II st age.
3. The III st age of eliminat ion should be r epeat ed of t he near ly for med gr oups of
second st age. In t his st age, t wo t er ms can be compar ed only t han t hey have dashes
in some posit ions.
The pr ocess cont inues t o next higher st ages unt il no fur t her compar isons ar e
possible. (i.e., no fur t her eliminat ion of lit er als).
4. All t er ms which r emain unchecked (No sign) dur ing t he pr ocess ar e consider ed
t o be pr ime implicant s (PIs). Thus, a set of all PIs of t he funct ion is obt ained.
5. Fr om t he set of all pr ime implicat es, a set of essent ial pr ime implicant s (EPIs) must
be det er mined by pr epar ing pr ime implicant char t as follow.
(a) The PIs should be represented m rows and each minterm of the function in a column.
(b) Cr osses should be placed in each r ow t o show whit e composit ion of mint er ms
t hat makes t he PIs.
(c) A complete PIs chart should be inspected for columns containing only a single
cross. PIs that cover minterms with a single cross in their column are called EPIs.
6. The mint er ms which ar e not cover ed by t he EPIs ar e t aken int o consider at ion and
a minimum cover is obt ained for m t he r emaining PIs.
Now t o clar ify t he above pr ocedur e, let s do an example st ep by st ep.
Example 3.11. S implify the given function using tabular method.
F = A, B, C, D = ∑ (0, 2, 3, 6, 7, 10, 12, 13)
Solution. 1. The mint er ms of t he funct ion ar e r epr esened in binar y for m. The binar y
r epr esent ed ar e gr ouped int o a number of sect ions int er ms of t he number of 1’s index as
shown in Table 3.3.1 (a).
Table 3.3.1 (a)
Minterms Binary No. Minterms Index Binary
ABCD of 1's Group ABCE
m
0
0 0 0 0 0 m
0
0 0 0 0 0
m
2
0 0 1 0 1 m
2
0 0 1 0
m
3
0 0 1 1 2 m
8
1
1 0 0 0
m
6
0 1 1 0 2 m
3
0 0 1 1
m
7
0 1 1 1 3 m
6
2
0 1 1 0
m
8
1 0 0 0 1 m
10
1 0 1 0
m
10
1 0 1 0 2 m
12
1 1 0 0
m
12
1 1 0 0 2 m
7
0 1 1 1
m
13
1 1 0 1 3 m
13
3
1 1 0 1
2. Compar e each binar y t er m wit h ever y t er m in t he adjacent next higher cat egor y.
If t hey differ only by one posit ion put a check mar k and copy t he t er m int o t he next
column wit h (–) in t he place wher e t he var iable is unmat ched, which is shown in
next Table. 3.3.1 (b
1
)
132 S witching Theory
Table 3.31 (b
1
)
Minterm Binary
Group A B C D
0, 2 0 0 – 0
0, 8 – 0 0 0
2, 3 0 0 1 –
2, 6 0 – 1 0
2, 10 – 0 1 0
8, 10 1 0 – 0
8, 12 1 – 0 0 PI
3, 7 0 – 1 1
6, 7 0 1 1 –
12, 13 1 1 0 – PI
Table 3.3.1 (b
2
)
Minterm Binary
Group A B C D
0, 2, 8, 10 – 0 – 0 PI
0, 8, 2, 10 – 0 – 0 PI eliminat ed
2, 3, 6, 7 0 – 0 – PI
2, 6, 3, 7 0 – 1 – PI eliminat ed.
3. Apply some pr ocess t o t he r esult ant column of Table 3.3.1(b
1
) and cont inue unt il no
fur t her eliminat ion of lit er als. This is shown in Table (3.3.1(b)) above.
4. All t er ms which r emain unchecked ar e t he PIs. However not e t hat t he mint er ms
combinat ion (0, 2) and (8, 10) for m t he same combinat ion (0, 2, 8, 10) as t he comp..
(0, 8 and (2. 10). The or der in which t hese combinat ions ar e placed does not pr ove
any effect . Mor eover as we know t hat x + x = x
1
t hus we can eliminat e one of t hese
combinat ions.
The same occur wit h combinat ion (2, 3) and (6, 7).
5. Now we pr epar e a PI char t t o det er mine EPIs as follows shown in Table 3.3.1 (c).
Table 3.3.1 (c)
Minterms
Prime Implicants 0 2 3 6 7 8 10 12 13
(8, 12) × ×
(12, 13) * × ×
(0, 2, 8, 10) * × × × ×
(2, 3, 6, 7) * × × × ×

Boolean Function Minimization Techniques 133
(a) All t he PIs ar e r epr esent ed in r ows and each mint er m of t he funct ion in a
column.
(b) Grosses are placed in each row t o show t he composit ion of mint erms t hat make
PIs.
(c) The column t hat cont ains just a single cr oss, t he PI cor r esponding t o t he r ow
in which t he cr oss appear is essent ial. Pr ime implicant . A t ick mar k is par t
against each column which has only one cr oss mar k. A st ar (*) mar k is placed
against each. EPI.
6. All t he mint er ms have been cover ed by EPIs.
Finally, t he sum of all t he EPIs gives t he funct ion in it s minimal SOP for m
EPIs. Binary representation Variable Representation
A B C D
12, 13 1 1 0 – ABC'
0, 2, 8, 10 – 0 – 0 B'D'
2, 3, 6, 7 0 – 1 – A'C
Ther efor e F = ABC' + B'D' + A'C.
If don't car e condit ions ar e also given along wit h t he pr ovolone fr ict ion, t hey ar e also
used t o find t he pr ime implicat ing, but it is not compulsor y t o include t hem in t he final
simplified expr ession.
Example 3.12. S implify the given function using tabular method.
F(A, B, C, D) = ∑(0, 2, 3, 6,7)
d (5, 8, 10, 11, 15)
Solution. 1. St ep 1 is shown in Table 3.3.2(a). The don’t care mint erms are also included.
Table 3.3.2 (a)
Minterms Binary No. Minterms Index Binary
A B C D of 1’s Group ABCD
m
0
0 0 0 0 0 m
0
0 0 0 0 0
m
2
0 0 1 0 1 m
2
0 0 1 0
m
3
0 0 1 1 2 m
8
1 1 0 0 0
m
5
0 1 0 1 2 m
3
0 0 1 1
m
6
0 1 1 0 2 m
5
2 0 1 0 1
m
7
0 1 1 1 3 m
6
0 1 1 0
m
8
1 0 0 0 1 m
10
1 0 1 0
m
10
1 0 1 0 2 m
7
3 0 1 1 1
m
11
1 0 1 1 3 m
11
1 0 1 1
m
15
1 1 1 1 4 m
15
4 1 1 1 1
2. St ep 2 is shown in Table 3.3.2 (b
1
).
3. St ep 3 is shown in Table 3.3.2 (b
2
).
134 S witching Theory
Table 3.3.2 (b
1
)
Minterm Binary
Group A B C D
0, 2 0 0 – 0
0, 8 – 0 0 0
2, 3 0 0 1 –
2, 6 0 – 1 0
2, 10 – 0 1 0
8, 10 1 0 – 0
3, 7 0 – 1 1
3, 11 – 0 1 1
5, 7 0 1 – 1 PI
6, 7 0 1 1 –
10, 11 1 0 1 –
7, 15 – 1 1 1
11, 15 1 – 1 1
Table 3.3.2 (b
2
)
Minterm Binary
Group A B C D
0, 2, 8, 10 – 0 – 0 PI
0, 8, 2, 10 – 0 – 0 PI Eliminat ed
2, 3, 6, 7 0 – i – PI
2, 3 10, 11 – 0 1 – PI
2, 6, 3, 7 0 – 1 – PI Eliminat ed
2, 10, 3, 11 – 0 1 – PI Eliminat ed
3, 7, 11, 15 – – 1 1 PI
3, 11, 7, 15 – – 1 1 PI Eliminat ed
4. All t he t er ms which r emain unchecked ar e PIs. Mor eover one of t wo same
combinat ions is eliminat ed.
5. St ep 5 is t o pr epar e a PI char t t o det er mine EPIs as shown in Table 3.3.2 (c).
Not e, however t hat don’t car e mint er ms will not be list ed as column headings in
t he char t as t hey do not have t o be cover ed by t he minimal (simplified) expr ession.
Boolean Function Minimization Techniques 135
Table 3.3.2 (c)
Prime Implicants Minterms
0 2 3 6 7
(5, 7) ×
(0, 2, 8, 10) * × ×
(2, 3, 6, 7) * × × × ×
(2, 3, 10, 11) × ×
(3, 7, 11, 15) × ×

6. All t he mint er ms have been cover ed by EPIs.
Ther efor e F (A, B, C, D) = B'D' + A'C
Example 3.13. S implify the given function using tabular method:
F (A, B, C, D, E, F, G) = S (20, 28, 38, 39, 52, 60, 102, 103, 127)
Solution. St ep 1 is shown in Table 3.3.3 (a).
Minterms Binary No. Minterms Index Binary
ABCDEFG of 1’s Group ABCDEFG
m
20
0 0 1 0 1 0 0 2 m
20
2 0 0 1 0 1 0 0
m
28
0 0 1 1 1 0 0 3 m
28
0 0 1 1 1 0 0
m
38
0 1 0 0 1 1 0 3 m
38
3 0 1 0 0 1 1 0
m
39
0 1 0 0 1 1 1 4 m
52
0 1 1 0 1 0 0
m
52
0 1 1 0 1 0 0 3 m
39
4 0 1 0 0 1 1 1
m
60
0 1 1 1 1 0 0 4 m
60
0 1 1 1 1 0 0
m
102
1 1 0 0 1 1 0 4 m
102
1 1 0 0 1 1 0
m
103
1 1 0 0 1 1 1 5 m
103
5 1 1 0 0 1 1 1
m
127
11 1 1 1 1 1 7 m
127
7 1 1 1 1 1 1 1 PI
2. St ep 2 is shown in Table 3.3.3 (b
1
).
3. St ep 3 is shown in Table 3.3.3 (b
2
).
Table 3.3.3 (b
1
)
Minterms Binary
Group A B C D E F G
20, 28 0 0 1 – 1 0 0
20, 52 0 – 1 0 1 0 0
28, 60 0 – 1 1 1 0 0
38, 39 0 1 0 0 1 1 –
38, 102 – 1 0 0 1 1 0
52, 60 0 1 1 – 1 0 0
39, 103 – 1 0 0 1 1 1
102, 103 1 1 0 0 1 1 –
136 S witching Theory
Table 3.3.2 (b
2
)
Mintesms Binary
Group A B C D E F G
20, 28, 52, 60 0 – 1 – 1 0 0 PI
20, 52, 28, 60 0 – 1 – 1 0 0 PI Eliminat ed
38, 39 102, 103 – 1 0 0 1 1 – PI
38, 102, 39, 103 – 1 0 0 1 1 – PI Eliminat ed
4. All t he t er ms which r emain unchecked ar e PIs. Mor eover one of t wo same
combinat ions is eliminat ed.
5. PI char t t o det er mine EPIs is shown in Table 3.3.3 (c).
Table 3.3.3 (c)
Prime Implicants Minterms
20 28 38 39 52 60 102 103 127
127 * ×
(20, 28, 52, 60) * × × × ×
(38, 39, 102, 103) * × × × ×

6. All t he mint er ms have been cover ed by EPIs.
Ther efor e F (A, B, C, D, E, F, G) = ABCDEFG + A'CEF'G' + BC' D' EF
3.4 EXERC ISES
1. Using Boolean algebr a simplify each of t he following logic expr essions as much as
possible:
(a) Z = A(A + AB) (A + ABC) (A + ABCD)
(b) C = (X X X X
1 2 2 3
′ + ′ ′ )
2. Dr aw t he simplest possible logic diagr am t hat implement s t he out put of t he logic
diagr am given below.
A
B
C
H
3. Wr it e t he logic expr ession and simplify it as much as possible and dr aw a logic
diagr am t hat implement s t he simplified expr ession.
Boolean Function Minimization Techniques 137
A
B
C
X
D
4. Obt ain t he simplified expr ession in s-of-p for t he following Boolean funct ions:
(a) xy x y z x yz + ′ ′ ′ + ′ ′
(b) ABD + A′C′D′ + A′B + ACD + AB′D′
(c) x z w xy w x y xy ′ + ′ ′ + ′ + ′ ( )
(d) F (x y z , , ) ( , , , ) = Σ 2 3 6 7
(e) F (A, B, C, D) = (7, 13, 14, 15) Σ
5. Use a K-map t o simplify each of t he following logic expr essions as much as possible:
(i) F = AB + A B + AB ′ ′
(ii) G = X Y Z + X YZ + XY Z + X Y Z + XYZ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′
(iii) H = A B CD + AB C D + A B C D + ABC D + A B C D + AB C D + ABCD ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′
(iv) W = X Y Z + X YZ + XYZ + XY Z + X YZ ′ ′ ′ ′ ′ ′
6. Simplify t he following logic expr essions using K-maps and t abular met hod.
(a) F(A, B, C) = A′C + B′C+AB′C′
(b) G(A, B, C, D) = B′CD + CD′ + A′B′C′D + A′B′C
7. Simplify t he Boolean funct ion F
(ABCDE)
= Σ(0, 1, 4, 5, 16, 17, 21, 25, 29)
8. Simplify t he following Boolean expr essions using K-maps and Tabular met hod.
(i) BDE + B′C′D + CDE + ABCE + ABC + BCDE
(ii) ABCE + ABCD + BDE + BCD + CDE + BDE
(iii) F
(ABCDEF)
= Σ(6, 9, 13, 18, 19, 27, 29, 41, 45, 57, 61)
9. Dr aw Kar naugh maps for t he following expr essions:
F = A .B . C + A .B . C + A.B . C + A.B. C ′ ′ ′ ′ ′ ′
F = A .B. C + A.B. C + A .B. C + A.B. C + A.B . C ′ ′ ′ ′ ′ ′
F = A B C D + A.B C D + A B C D + A .B . C D + A B C .D . . . . . . . . . . . ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′
+ A B C D + A .B . C.D + A B. C.D ′ ′ ′ ′ ′ ′ ′ . .
10. Simplify t he following logic expr essions using kar naugh maps. Dr aw logic diagr ams
for t hem using only (a) NAND, (b) NOR gat es, assuming input s A, B, C, and D only
ar e available.
Y = A B C D + A.B C D + A B C D + A .B . C D + A B C .D ′ ′ ′ ′ ′ ′ ′ ′ . . . . . . . . . . .
+ ′ ′ ′ ′ ′ A .B . C.D + A .B. C.D
138 S witching Theory
Y = A B C D + A .B C D + A B C D + A .B. C D + A B C.D + A.B . C.D ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ . . . . . . . . . . .
Y = A B C D + A.B C D + A B C D + A .B . C D+ A B C.D + A.B. C .D ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ . . . . . . . . . . .
+ ′ ′ ′ ′ ′ ′ ′ ′ A .B . C.D + A.B . C.D + A.B . C .D + AB . C.D
Y = A.B. C .D + A .B . C .D + A.B . C .D + A.B. C.D + A.B. C.D ′ ′ ′ ′ ′ ′ ′ ′ ′
11. The inst it ut e’s pool r oom has four pool t ables lined up in a r ow. Alt hough each t able
is far enough fr om t he walls of t he r oom, st udent s have found t hat t he t ables ar e
t oo close t oget her for best play. The exper t s ar e willing t o wait unt il t hey can
r eser ve enough adjacent t ables so t hat one game can pr oceed unencomber ed by
near by t ables. A light boar d visible out side t he pool r oom shows vacant t ables. The
manager has developed a digit al cir cuit t hat will show an addit ional light whenever
t he exper t s’ desir ed condit ions ar ise. Give a logic equat ion for t he asser t ion of t he
new light signal. Simplify t he equat ion using a K-Map.
12. Simlify t he Boolean funct ions using t abular met hod and ver ify r esult wit h K-map.
(a) F (w x y z , , , ) ( , , , , , , , , , , ) = Σ 0 1 2 4 5 6 8 9 12 13 14
(b) F (w x y z , , , ) ( , , , , , ) = Σ 2 3 12 13 14 15
(c) F (A B C D , , , ) ( , , , ) = Σ 4 6 7 15
(d) F (A B C D , , , ) ( , , , ) = Σ 7 13 14 15
(e) F ( , , x y z) ( , , , ) = Σ 7 13 14 15
13. Simplify t he Boolean funct ion F using t he don’t car e condit ions d, in (I) SOP and
(II) POS:
F = A B D + A CD + A BC ′ ′ ′ ′ d = ′ ′ ′ ′ A BC D + ACD + AB D
F = ( w x y x y xyz x z y w ′ ′ + ′ ′ + + ′ ′ + ) ( ) d w x y z yz wyz = ′ ′ + ′ + ( )
F = ACE + A CD E + A C DE ′ ′ ′ ′ ′ d = ′ ′ ′ ′ ′ DE + A D E + AD E
14. Use a Kar naugh map t o simplify each of t he following logic expr essions as much
as possible.
(a) F = A B CD + AB C D + A B CD + ABC D + ABCD ′ ′ ′ ′ ′ ′ ′ ′ ′
Solution. F = ABD + A′B′D + B′C′
(b) G = A C + B C + AB C + A B ′ ′ ′ ′ ′
Solution. G = AB + A B + A C or AB + A B + B C ′ ′ ′ ′ ′ ′
(c) H = B CD + CD + A B C D + A B C ′ ′ ′ ′ ′ ′ ′ ′
Soluti on. H = B CD + CD + A B C D + A B C ′ ′ ′ ′ ′ ′ ′ ′
(d) F = A + B + C ) (A + B + C) (A + B + C ) ( ′ ′ ′
Soluti on. F = B + AC′
15. Use a Kar naugh map t o simplify each of t he following logic expr essions as much
as possible.
(a) W = (AB C ) AB C) (ABC) ′ ′ ′ ′ ′ (
Boolean Function Minimization Techniques 139
(b) M = X X X X X X X X X
2 3 1 2 3 3 1 2 3
+ ′ ′ + ′ + ′
16. Using Boolean Algebra simplify
(a)
(A + B) (A + C)
(b) A + ABC + ABCD + ABCDE B
(c)
AB + ABC A +
(d) (A + A) (AB + ABC)
(e) AB + (A + B)C + AB
17. Use a kar naugh map t o simplify each funct ion t o a minimum sum-of-pr oduct s for m:
(a)
X = ABC + ABC + ABC
(b)
X = AC [B + A (B + C)]
(c)
X = DE F + DEF + DE F
18. A B C F
1
A B C F
2
0 0 0 1 0 0 0 0
0 0 1 0 0 0 1 1
0 1 0 0 0 1 0 1
0 1 1 0 0 1 1 1
1 0 0 0 1 0 0 0
1 0 1 1 1 0 1 1
1 1 0 0 1 1 0 1
1 1 1 1 1 1 1 0
Tr ansfer t he input -out put specificat ions for F
1
and F
2
given above t o 3 var iable
Kar naugh maps.
19. Using a Kar nagh map simplify t he following equat ions
(a)
X = AB + AC + BC + AB + AC + ABC + ABC
(b)
X = ABC + ACD + ABC + BCD + ABC + ABD + ABCD
(c)
X = D A[C + BC] + A [C + BC]) + BCD (
(d)
X = ABC + BCD + ABD + ABCD + ACD + ABCD
20. Simplify t he following using Boolean Algebr a
(a) z w x w x y = + . . .
(b)
z x y x y = + + ( ) . ( )
(c) z x y w y w x x y v = + + + . . . . .
(d) z x y x w y x w y = + + + + ( ). ( ).[ . ( ) ]
21. Consider t he funct ion
z f x y w v x v x w y w y v = = + + ( , , , ) ( . . ). . ( . )
(a) Dr aw a schemat ic diagr am for a cir cuit which would implement t his funct ion.
22. Simplify t he Boolean funct ion by t abular met hod
140 S witching Theory
F(A, B, C, D, E) = Σ(0, 1, 4, 5, 16, 17, 21, 25, 29)
23. Simplify t he following funct ion in (a) s–o-p
and (b) p–o–s
F(A, B, C, D) = ∏(3, 4, 6, 7, 11, 12, 13, 14, 15)
24. Simplify t he Boolean funct ion using t abular met hod.
F(A, B, C, D, E) = Σ(0, 1, 4, 5, 16, 17, 21, 25, 29, 30)
25. Simplify t he Boolean funct ion using t abular met hod
F(A, B, C, D, E, F) = Σ(6, 9, 13, 18, 19, 27, 29, 41, 45, 57, 61, 63)
4.0 INTRO DUC TIO N
Combinat ional logic cir cuit s ar e cir cuit s in which t he out put at any t ime depends upon
t he combinat ion of input signals pr esent at t hat inst ant only, and does not depend on any past
condit ions.
The block diagr am of a combinat ional cir cuit wit h m input s and n out put s is shown in
Fig. 4.0.
Combinational
Circuit
Inputs Outputs
X
1
X
2
X
3
X
m
Y
1
Y
2
Y
3
Y
n
(n 2 ) ≤
m
Fig. 4.0 Block Diagr am of combinat ional Logic cir cuit .
In par t icular, t he out put of par t icular cir cuit does not depend upon any past input s or
out put s i.e. t he out put signals of combinat ional cir cuit s ar e not fedback t o t he input of t he
cir cuit . Mor eover, in a combinat ional cir cuit , for a change in t he input , t he out put appear s
immediat ely, except for t he pr opagat ion delay t hr ough cir cuit gat es.
The combinat ional cir cuit block can be consider ed as a net wor k of logic get s t hat accept
signals fr om input s and gener at e signals t o out put s. For m input var iables, t her e ar e 2
m
possible combinat ions of binar y input values. Each input combinat ion t o t he combinat ional
cir cuit exhibit s a dist inct (unique) out put . Thus a combinat ional cir cuit can be discr ibed by n
boolean funct ions, one for each input combinat ion, in t er ms of m input var iables wit h n is
always less t han or equal t o 2
m
. [n < 2
m
].
Thus a combinat ional cir cuit per for ms a specific infor mat ion pr ocessing oper at ion which
is specified by Boolean funct ions.
n < 2
m
r epr esent t he condit ion, if in a par t icular applicat ion t her e ar e some unused input
combinat ions. For example we ar e using NBCD codes, t he six combinat ions (1010, 1011, 1100,
1101, 1110 and 1111) ar e never used. So wit h four input var iables (

m = 4) we ar e using only
10 i/p combinat ions

10 o/ps inst ead of 2
4
= 16.
The digit al syst ems per for m a member of infor mat ion pr ocessing t asks. The basic
ar it hmat ic oper at ions used by digit al comput er s and calculat or s ar e implement ed by combi-
nat ional cir cuit s using logic get s. We pr oceed wit h t he implement at ion of t hese basic funct ions
by fir st looking t he simple design pr ocedur e.
4
CHAPTER
COMBINATIONAL LOGIC
141
142 S witching Theory
C o m b ina tio na l c irc uit De sig n Pro c e d ure
It involves following st eps :
Step 1 : Fr om t he wor d descr ipt ion of t he pr oblem, ident ify t he input s and out put s and
dr aw a block diagr am.
Step 2 : Make a t r ut h t able based on pr oblem st at ement which complet ely descr ibes t he
oper at ions of cir cuit for differ ent combinat ions of input s.
Step 3 : Simplified out put funct ions ar e obt ained by algebr ic manipulat ion, k-map met hod
or t abular met hod.
Step 4 : Implement t he simplified expr ession using logic gent is.
To explain t he pr ocedur e, let us t ake an example t hat we have alr eady been used in
chapt er 2.
Example: A TV is connected through three switches. The TV becomes ‘on’ when atleast
two switches are in ‘ON’ position; In all other conditions, TV is ‘OFF’.
Soluti on. Step I : The TV is connect ed wit h 3 swit ches; t hus t her e ar e t hr ee input s t o
TV, r epr esent ed by var iables say A, B and C. The o/p of TV is r epr esent ed by var iable say, F.
The block diagr am is shown in Fig. 4.1 :
x
y
z
Combinational
Circuit
Inputs F-output
Fi g. 4.1
Step 2. Truth Tables
TV switches ← INPUTS OUTPUTS
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
0 → swit ch off
1 → swit ch on
It means for t he input combinat ions in which t her e ar e t wo or mor e 1's, t he out put F
= 1 (TV is ON) and for r est combinat ions, out put F = 0 (TV is OFF).
Step 3 : In gener al, in simplifying boolean funct ions upt o
four var iables, t he best met hod is K-map t echnique. Thus,
using a 3 var iable K-map, we can simplify t he funct ion obt ained
in st ep II.
1
1 1 1
00 01 11 10
1
0
BC
A
Combinational Logic 143
We get F = AB + AC + BC
We can observe t hat if t he velue of any t wo variables is equal t o 1, t he out put is equal t o 1.
Step IV. For implement at ion we need t hr ee ‘AND’ gat es and one ‘OR’ gat e as shown in
Fig. 4.2.
A
B
C
F = AB + AC + BC
AB
AC
BC
Fi g. 4.2
4.1 ARITHM ATIC C IRC UITS
The logic cir cuit s which ar e used for per for ming t he digit al ar it hmat ic oper at ions such
as addit ion, subt r act ion, mult iplicat ion and division ar e called ‘ar it hmat ic cir cuit s’.
4.1.1 Ad d e rs
The most common ar it hmet ic oper at ion in digit el syst ems is t he addit ion of t wo binar y
digit s. The combinat ional cir cuit t hat per for ms t his oper at ion is called a half-adder.
Ha lf Ad d e r
1. Fig. 4.3 shows a half adder (HA).
It has t wo input s A and B. t hat ar e t wo 1-bit member s, and
t wo out put sum (S) and car r y (C) pr oduced by addit ion of t wo bit s.
2. Truth Table :
Inputs Outputs
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
The sum out put is 1 when any of input s (A and B) is 1 and t he car r y out put is 1 when
bot h t he input s ar e 1.
3. Using a t wo variable k-map, separ at ely for bot h out put s S and C.
1
1
0 1
1
0
B
A
For ‘S’
1
1
0 1
1
0
B
A
For ‘C’
S = AB' + A'B C = A'B
= A ⊕ B.
HA
A
B
S
C
Fig. 4.3 Half Adder
144 S witching Theory
4. Logical Implement at ion.
(i) Using Basic gat es (as shown in Fig. 4.4(a)).
S = AB + A B ′ ′
C = AB
A B
Fig. 4.4 (a)
(ii) Using XOR gat e as shown in Fig. 4.4 (b).
A
B
S = A B = AB + A B ⊕ ′ ′
C = AB
Fig. 4.4 (b)
Implement at ion using only NAND or only NOR gat es is left as an exer cise.
Full Ad d e r
Full adder is a combinat ional cir cuit t hat per for ms t he addit ion of t hr ee binar y digit s.
1. Fig. 4.5 shows a full adder (FA). It has t hr ee
input s A, B and C and t wo out put s S and Co
produced by addit ion of t hree input bit s. Carry
out put is designat ed Co just t o avoid confu-
sion bet ween wit h i/p var iable C.
2. Truth Table : The eight possible combinat ions of t hr ee input var iables wit h t heir
r espect ive out put s is shown. We obser ve t hat when all t he t hr ee input s ar e 1, t he
sum and car r y bot h out put s, ar e 1.
Inputs Output
A B C S C
0
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
A
B
S
C
0
FA
C
Fig. 4.5 Full adder
Combinational Logic 145
3. Using a t hr ee var iable map for bot h out put s.
1
1 1
1
00 01 11 10
1
0
BC
A
For ‘S’
1
1 1 1
00 01 11 10
1
0
BC
A
For ‘C ’
0
S = ABC + AB'C' + A' BC' + A'B'C and C
0
AB + AC + BC.
4. Logical Implement at ion. (i) Using basic gat es as shown in Fig. 4.6.
S
C
A B C
Fi g. 4.6
(ii) A ‘Full Adder ’ can also be implement ed using t wo half adder s and an ‘OR’ Gat e as
shown in Fig. 4.7
The Sum S = ABC + AB'C' + A'BC' + A'B' C
= ABC + A' B' C + AB' C' + A'BC'
= C (AB + A' B') + C' (AB' + A' B)
= C (AB' + A' B)' + C' (AB' + A'B)
= (A ⊕ B) ⊕ C
and t he car r y C
0
= AB + AC + BC
= AB + C (A + B)
= AB + C (A + B) (A + A' ) (B + B' )
= AB + C [AB + AB' + A'B]
= AB + ABC + C (AB' + A'B)
= AB (1 + C) + C (A ⊕ B)
= AB + C (A ⊕ B)
146 S witching Theory
⇒ S = (A ⊕ B) ⊕ C and C
0
= AB + C (A ⊕ B)
A
B
HA
1
HA
2
S
C
0
C
Fig. 4.7 Implement at ion of Full Adder.
Block Diagr am r epr esent at ion of a full adder using t wo half addr ess :
C
A
B
HA
1
S
1
C
1
HA
2
S
2
C
2
Cout
Sum
S
1
and C
1
ar e out put s of fir st half adder (HA
1
)
S
2
and C
2
ar e out put s of second half adder (HA
2
)
A, B and C ar e input s of Full adder.
Sum and covt ar e out put s of full adder.
4.1.2 Sub tra c tors
The logic cir cuit s used for binar y subt r act ion, ar e known as ‘binar y subt r act or s’.
Half Subt r act or : The half subt r act or is a combinat ional cir cuit which is used t o per for m
t he subt r act ion of t wo bit s.
1. Fig. 4.8 shows a half subt r act or. (HS)
It has t wo input s, A (minered) and B (subt rat end) and
t wo out put s D (difference) and B
0
(Borrow). [The sym-
bol for borrow (B
0
) is t aken t o avoid confusion wit h
input variable B] produced by subt ract or of t wo bit s.
2. Truth Table
The differ ence out put is 0 if A = B and 1 is A ≠ B; t he bor r ow out put is 1 whenever
A < B. If A < B, t he subt r act ion is done by bor r owing 1 fr om t he next higher or der
bit .
Inputs Outputs
A B D B
0
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
HS
A
B
D
B
Fig. 4.8 Half subt r act or
Combinational Logic 147
3. Using a t wo var iable map, for out put s D and B.
1
1
0 1
1
0
B
A
‘D’
1
0 1
1
0
B
A
‘B ’
0
D = AB' + A' B B
0
= A'B
= A ⊕ B
4. Logical Implement at ion shwon in Fig. 4.9
(a) Using Basic gat es (b) using XOR gat e
D
A B
B
0
A
B
D
B
0
Fig. 4.9 (a) Basic gat e implement at ion Fig. 4.9 (b) X-OR gat e implement at ion
half subt r act or. of half subt act or
Full sub tra c to r
Full subt r act or is a combinat ional cir cuit t hat per for mer t he subt r act ion of t hr ee binar y
digit s.
1. Fig. 4.10 shows a full subt r act or (FS).
It has t hree input s A, B and C and t wo out put s D
and B
0
. pr oduced by subt r act ion of t hr ee input bit s.
2. Truth Table
The eight possible combinat ions of t hr ee input var iables wit h t her e r espect ive
out put s is shown. We obser ve t hat when all t he t hr ee input s ar e 1, t he diffr ence
and bor r ow bot h out put s ar e 1.
Inputs Output
A B C B
0
D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
A
B
S
B
0
FS
C
Fig. 4.10 Full subt r act or.
148 S witching Theory
3. Using a t hr ee var iable map for bot h out put s.
1
1 1
1
00 01 11 10
1
0
BC
A
For ‘D’
1
1
1 1
00 01 11 10
1
0
BC
A
For ‘B ’
0
D = ABC + AB' C' + A'BC' + A'B'C, B
0
= A' B + A'C + BC
D = ABC + AB′C′ + A′BC′ + A′B′C
4. Logical implement at ion—
(i) Using basic gat es : Left as an exer cise.
(ii) A ‘full subt r act or ’ can also be implement ed using t wo ‘half subt r act or s’ and an
‘OR’ gat e as shwon in Fig. 4.11.
The differ ence ‘D’ = ABC + AB'C' + A' BC' + A'B'C
= ABC + A' B' C + AB'C' + A'BC'
= C (AB + A' B' ) + C' (AB' + A'B)
= C (AB' + A'B)' + C' (AB' +A'B)
= C (A ⊕ B)' + C' (A ⊕ B)
= (A ⊕ B) ⊕ C
and t he bor r ow B
0
= A'B + A'C + BC
= A'B + C (A' + B)
= A'B + C (A' + B) (A + A') (B + B' )
= A'B + C [A'B + AB + A'B']
= A'B + A' BC + C (AB + A' B' )
= A'B (C + 1) + C (A ⊕ B)'
= A'B + C (A ⊕ B)'
⇒ D = (A ⊕ B) ⊕ C and B
0
= A'B + C (A ⊕ B)'
A
B
HS
1
HS
2
D
B
0
C
Fig. 4.11
Block Diagr am Repr esent at ion of a full subt r act or using t wo half subt r act or s :
Combinational Logic 149
C
A
B
HS
1
D
1
Bo
1
HS
2
D
2
Bo
2
Bout
Difference
Fig. 4.11 (a)
D
1
and B
01
ar e out put s of fir st half subt r act or (HSI)
D
2
and B
02
ar e out put s of second half subt r act or (HS
2
)
A, B and C ar e input s of full subt r act or.
Differ ence and Bovt ar e out put s of full subt r act or.
4.1.3 C od e C onve rte rs
In t he pr evious st udy of codes, coding was defined as t he use of gr oups of bit s t o
r epr esent it ems of infor mat ion t hat ar e mult ivalued. Assigning each it em of infor mat ion a
unique combinat ion of bit s makes a t r ansfor mat ion of t he or iginal infor mat ion. This we
r ecognize as infor mat ion being pr ocessed int o anot her for m. Mor eover, we have seen t hat
t her e ar e many coding schemes exist . Differ ent digit al syst ems may use differ ent coding
schemes. It is somet imes necessar y t o use t he out put of one syst em as t he input t o ot her.
Ther efor a sor t of code conver sion is necessar y bet ween t he t wo syst ems t o make t hem
compat ible for t he same infor mat ion.
‘A code conver t er is a combinat ional logic cir cuit t hat changes dat a pr esent ed in one t ype
of binar y code t o anot her t ype of binar y code.’ A gener al block diagr am of a code conver t er
is shown in Fig. 4.12.
Code
Converter
Code X Code Y
Fig. 4.12 Code coner t er
To under st and t he design pr ocedur e; we will t ake a specific example of 4-bit Binar y t o
Gr ay code conver sion.
1. The block diagr am of a 4-bit binar y t o gr ay code conver t er is shown in Fig. 4.13.
4-bit
binary
input
Binary
to
Gray
Code
Converter
B
3
B
2
B
1
B
0
G
3
G
2
G
1
G
0
4-bit
Gary
Code
Output
Fig. 4.13
If has four input s (B
3
B
2
B
1
B
0
) r epr esent ing 4-bit binar y number s and four out put s
(G
3
G
2
G
1
G
0
) r epr esent ing 4-bit gr ay code.
150 S witching Theory
2. Tr ut h t able for binar y t o gr ay code conver t er s.
Binary Inputs Gray code Outputs
B
3
B
2
B
1
B
0
G
3
G
2
G
1
G
0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
3. Now we solve all t he gr ay out put s dist ant ly wit h r espect t o binar y input s Fr om t he
t r ut h t able; t he logic expr essions for t he gr ay code out put s can be wr it t en as
G
3
= S (8, 9, 10, 11, 12, 13, 14, 15)
G
2
= Σ (4, 5, 6, 7, 8, 9, 10, 11)
G
1
= Σ (2, 3, 4, 5, 10, 11, 12, 13)
G
0
= Σ (1, 2, 5, 6, 9, 10, 13, 14).
The above expr essions can be simplified using K-map
Map for G
3
:
Fr om t he oct et , we get
G
3
= B
3
Map for G
2
:
Fr om t he t wo quads, we get
G
2
= B
3
' B
2
+ B
3
B
2
'
= B
3
⊕ B
2
.
1 1 1 1
00 01 11 10
01
00
B B
1 0
B B
3 2
1 1 1 1 11
10
1 1 1 1
00 01 11 10
01
00
B B
1 0
B B
3 2
1 1 1 1
11
10
Combinational Logic 151
Map for G
1
:
Fr om t he t wo quads, we get
G
1
= B
2
B
1
' + B
2
' B
1
= B
2
⊕ B
1
Map for G
0
:
Fr om t he t wo quads, we get
G
0
= B
1
' B
0
+ B
1
B
0
'
= B
1
⊕ B
0
.
4. Now t he above expr essions can be implement ed using X-OR gat es t o yield t he
disir ed code conver t er cir cuit shown in Fig. 4.14.
B
0
B
1
B
2
B
3
G
0
G
1
G
2
G
3
Binary
Input
Gray
Output
Fig. 4.14
Let us see one mor e example of XS-3 t o BCD code conver t er.
1. The block diagr am of an XS-3 t o BCD code conver t er is shown in Fig. 4.15.
It has four input s (E
3
, E
2
, E
1
, E
0
) r epr esent ing 4 bit XS-3 number and four out put s
(B
3
B
2
B
1
B
0
) r epr esent ing 4-bit BCD code.
4 bit
XS-3
Input
Excess-3
to
BCD
code
converter
E
3
E
2
E
1
E
0
B
3
B
2
B
1
B
0
4-bit
BCD
Coded
Output
Fig. 4.15
2. Truth Table for XS-3 t o BCD code conver t er.
XS-3 codes ar e obt ained fr om BCD code by adding 3 t o each coded number. Mor eo-
ver 4 binar y var iables may have 16 combinat ions, but only 10 ar e list ed. The six
not list ed ar e don’t car e-combinat ions (since in BCD codes, we use only t o member s
1
1
1
1
00 01 11 10
01
00
B B
1 0
B B
3 2
1
1
1
1
11
10
1 1
1 1
00 01 11 10
01
00
B B
1 0
B B
3 2
1 1
1 1
11
10
152 S witching Theory
viz. 0, 1, 2, ....9). Since t hey will never occur, we ar e at liber t y t o assign t o t he
out put var iable eit her a 1 or a 0, whichever gives a simpler cir cuit . In t his par t icu-
lar example, t he unused i/o combinat ions ar e list ed below t he t r ut h t able.
Min Excess-3 BCD Decimal
Terms Inputs Outputs Equivalent
E
3
E
2
E
1
E
0
B
3
B
2
B
1
B
0
m
3
0 0 1 1 0 0 0 0 0
m
4
0 1 0 0 0 0 0 1 1
m
5
0 1 0 1 0 0 1 0 2
m
6
0 1 1 0 0 0 1 1 3
m
7
0 1 1 1 0 1 0 0 4
m
8
1 0 0 0 0 1 0 1 5
m
9
1 0 0 1 0 1 1 0 6
m
10
1 0 1 0 0 1 1 1 7
m
11
1 0 1 1 1 0 0 0 8
m
12
1 1 0 0 1 0 0 1 9
Unused I/Ps Out put s
m
0
0 0 0 0 x x x x
m
1
0 0 0 1 x x x x
m
2
0 0 1 0 x x x x
m
13
1 1 0 1 x x x x
m
14
1 1 1 0 x x x x
m
15
1 1 1 1 x x x x
* XS-3 is also a class of BCD codes.
3. Now we solve all t he BCD out put s. Fr om t he t r ut h t able, t he logic expr essions for
t he BCD coded out put s can be wr it t en as :
B
3
= Σ (m
11
, m
12
), d (m
0
, m
1
, m
2
, m
13
, m
14
, m
15
)
B
2
= Σ (m
7
, m
8
, m
9
, m
10
), d (m
0
, m
1
, m
2
, m
13
, m
14
, m
15
)
B
1
= Σ (m
5
, m
6
, m
9
, m
10
), d (m
0
, m
1
, m
2
, m
13
, m
14
, m
15
)
B
0
= Σ (m
4
, m
6
, m
8
, m
10
, m
12
), d (m
0
, m
1
, m
2
, m
13
, m
14
, m
15
).
These expr essions can be simplified using k-map →
1
00 01 11 10
01
00
E E
1 0
E E
3 2
1 X X X 11
10
X X X
Map for B
3

1
00 01 11 10
01
00
E E
1 0
E E
3 2
1
X X X 11
10
X X X
Map for B
2

1 1
⇒ B
3
= E
3
E
2
+ E
3
E
1
E
0
⇒ B
2
= E
2
' E
0
' + E
2
E
1
E
0
Combinational Logic 153
1
00 01 11 10
01
00
E E
1 0
E E
3 2
1
X X 11
10
X X X
Map for B
3

1
00 01 11 10
01
00
E E
1 0
E E
3 2
1
X X X 11
10
X X X
Map for B
2

1
1
1
1
1
⇒ B
1
= E
1
' E
0
+ E
1
E
0
' ⇒ B
0
= E
0
'
= E
1
⊕ E
0
⇒ B
3
= E
3
E
2
+ E
3
E
1
E
0
B
2
= E
2
' E
0
0' + E
2
E
1
E
0
B
1
= E
1
⊕ E
0
B
0
= E
0
'
4. The expr essions for BCD out put s (B
3
B
2
B
1
B
0
) can be implement ed for t er ms of
input s (E
3
E
2
E
1
E
0
) t o for m a XS-3 t o BCD code conver t er cir cuit .
The implement at ion is left as an exer cise.
4.1.4 Pa rity G e ne ra tors a nd C he c ke rs
When digit al dat e is t r ansmit t ed fr om one locat ion t o anot her, it is necessar y t o know
at t he r eceiving end, wheat her t he r eceived dat a is fr ee of er r or. To help make t he t r ansmis-
sion accur at e, special er r or det ect ion met hods ar e used.
To det ect er r or s, we must keep a const ant check on t he dat a being t r ansmit t ed. To check
accur acy we can gener at e and t r ansmit an ext r a bit along wit h t he message (dat a). This ext r a
bit is known as t he par it y bit and it decides wheat her t he dat a t r ansmit t ed is er r or fr ee or
not . Ther e ar e t wo t ypes of par it y bit s, namely even par it y and odd par it y t hat we have
discussed in chapt er 1 under er r or det ect ing codes.
Fig. 4.16 shows an er r or det ect ing cir cuit using a par it y bit .
A B C
Error
Detector
P
A B C
Parity bit
Generator
Error
Alarm
A
B
C
Data
A
B
C
Data
Parity Checker
Inputs Transmission Outputs
Parity bit
Fig. 4.16
154 S witching Theory
In t his syst em t hr ee par allel bit s A, B and C and being t r ansmit t ed over a long dist ance.
Near t he input t hey ar e fed int o a par it y bit gener at or cir cuit . This cir cuit gener at es what
is called a par it y bit . It may be eit her ever or odd. For example, if it is a 3-bit even par it y
gener at or, t he par it y bit gener at ed is such t hat it makes t ot al member of 1s even. We can
make a t r ut h t able of a 3-bit even par it y gener at or cir cuit .
Truth Table for a 3-bit even par it y gener at or.
Inputs Data Output
Even parity bit
A B C P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
Next , t he t r ut h t able is conver t ed t o a logic cir cuit shown in Fig. 4.17.
P = A'B'C + A'BC' + AB'C' + ABC
= A' (B' C + BC' ) + A (B'C' + BC)
= A' (B ⊕ C) + A (B ⊕ C)
= A' (B ⊕ C) + A (B ⊕ C)'
= A ⊕ (B ⊕ C) = (A ⊕ B) ⊕ C = A ⊕ B ⊕ C.
The generat ed parit y bit is t ransmit t ed wit h t he dat a and near t he out put it is fed t o t he
error detector (parity checker) circuit. The det ect or circuit checks for t he parit y of t ransmit t ed
dat a. As soon as t he t ot al number of 1’s in t he t ransmit t ed dat a are found ‘odd’ it sounds an alarm,
indicat ing an error. If t ot al member of 1's are even, no alarm sounds, indicat ing no error.
In above example we ar e t r ansmit t ing 4 bit s. (3 bit s of message plus 1 even par it y bit ).
So, it is easy t o under st and t hat . Er r or det ect or is not hing but a 4 bit even-par it y checker
cir cuit . Fig. 4.18 (a) shows a t r ut h t able of a 4 bit even par it y checker cir cuit .
Inputs Outputs
Transmitted Data Parity error
with parity bit check
A B C P E
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
A
B
C
Parity
bit
P
3-bit even parity generator
circuit
Fig. 4.17
(Con t d .)
Combinational Logic 155
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
Fig. 4.18 (a)
Now below : We conver t t his t r ut h t able int o logic cir cuit shown in Fig. 4.18(b).
E = A' B' C' P + A'B'CP' + A'BC' P' + A'BCP +
AB'C'P' + AB'CP + ABC' P + ABCP'
= A' B' (C ⊕ P) + A' B (C⊕ P)' + AB' (C⊕ P)' + AB (C⊕ P)
= (C ⊕ P) (A ⊕ B)' + (C ⊕ P)' (A ⊕ B)
= (A ⊕ B) ⊕ (C ⊕ P)
A
B
C
D
E (Parity Error Check)
Fig. 4.18 (b) 4-bit even par it y checker.
If E = 1, Alar m sounds means er r or.
If E = 0, No alar m sounds means no er r or.
Now, it is possible t o implement t he par it y gener at or wit h t he cir cuit of par it y checker.
If t he input P is connect ed t o logic-0, causing t he value of C t o pass t hr ough t he gat e
inchanged. (because C ⊕ 0 = C). The advant age of t his is t hat t he same cir cuit can be used
for bot h par it y gener at ion and checking.
4.2 M SI AND LSI CIRCUITS
When designing logic cir cuit s, the “discr et e logic gat es”; i.e., individual AND, OR, NOT
etc. gat es, ar e oft en neit her t he simplest nor t he most economical devices we could use.
Ther e ar e many st andar d MSI (medium scale int egr at ed) and LSI (lar ge scale int egr at ed)
cir cuit s, or funct ions available, which can do many of t he t hings commonly r equir ed in logic
cir cuit s. Oft en t hese MSI and LSI cir cuit s do not fit our r equir ement s exact ly, and it is oft en
necessar y t o use discr et e logic t o adapt t hese cir cuit s for our applicat ion.
However, t he number and t ype of t hese LSI and VLSI (ver y lar ge scale int egr at ed)
cir cuit s is st eadily incr easing, and it is difficult t o always be awar e of t he best possible cir cuit s
available for a given pr oblem. Also, syst emat ic design met hods ar e difficult t o devise when t he
156 S witching Theory
t ypes of logic device available keeps incr easing. In general the “best” desi gn procedure
i s to attempt to fi nd a LSI devi ce whi ch can perform the requi red functi on, or
whi ch can be modi fi ed usi ng other devi ces to perform the requi red functi on. If
not hing is available, t hen t he funct ion should be implement ed wit h sever al MSI devices. Only
as a last opt ion should t he ent ir e funct ion be implement ed wit h discr et e logic gat es. In fact ,
wit h pr esent t echnology, it is becoming incr easingly cost -effect ive t o implement a design as
one or mor e dedicat ed VLSI devices.
When designing all but t he simplest logic devices, a “t op-down” appr oach should be
adopt ed. The device should be specified in block for m, and at t empt t o implement each block
wit h a small number of LSI or MSI funct ions. Each block which cannot be implement ed
dir ect ly can be t hen br oken int o smaller blocks, and t he pr ocess r epeat ed, unt il each block
is fully implement ed.
Of course, a good knowledge of what LSI and MSI functi ons are avai lable i n the
appropri ate technology makes thi s process si mpler.
4.2.1 The Dig ita l M ultip le xe r
One MSI funct ion which has been available for a long t ime is t he digit al select or, or
mult iplexer. It is t he digit al equivalent of t he r ot ar y swit ch or select or swit ch (e.g., t he
channel select or on a TV set ). It s funct ion is t o accept a binar y number as a “select or input ,”
and pr esent t he logic level connect ed t o t hat input line as out put fr om t he dat a select or.
A digit al mult iplexer (MUX) is a combinat ional cir cuit s t hat select s one input out of
sever al input s and dir ect it t o a single out put . The par t icular input select ion is cont r olled by
a set of select input s. Fig. 4.19 shows block diagr am of a digit al mult iplexer wit h n input s
lines and single out put line.
For select ing one out of n input , a set of m select
input s is r equir ed wher e
n = 2
m
On the basis of digital (binary) code applied at the select
inputs, one output of n data sources is selected. Usually, an
enable (or strobe) input (E) is built-in for cascading purpose.
Enable input is generally active-low, i.e., it performs its in-
tended operation when it is low (logic).
Note. 16:1 ar e t he lar gest available ICs, t her efor e for
lar ger input r equir ement s t her e should be pr ovision for
expansion. This is achieved t hr ough enable/st r oble input
(mult iplexer st acks or t r ees ar e designed).
A cir cuit diagr am for a possible 4-line t o 1-line dat a select or /mult iplexer (abbr eviat ed as
MUX for mult iplexer ) is shown in Fig. 4.20. Her e, t he out put Y is equal t o t he input I
0
, I
1
,
I
2
, I
3
depending on whet her t he select lines S
1
and S
0
have values 00, 01, 10, 11 for S
1
and
S
0
r espect ively. That is, t he out put Y is selected t o be equal t o t he input of t he line given by
t he binar y value of t he select lines S
1
S
0
.
The logic equat ion for t he cir cuit shown in Fig. 4.20 is:
Y = I S S I S S I S S I S S
0 1 0 1 1 0 2 1 3 4 1 0
. . . . . . . . + + +
This device can be used simply as a dat a select or /mult iplexer, or it can be used t o
per for m logic funct ions. It s simplest applicat ion is t o implement a t r ut h t able dir ect ly; e.g.,
Fig. 4.19 Block diagr am of t he
digit al mult iplexer.
Combinational Logic 157
wit h a 4 line t o 1 line MUX, it is possible t o implement any 2-var iable funct ion dir ect ly, simply
by connect ing I
0
, I
1
, I
2
, I
3
t o logic 1 in logic 0, as dict at ed by a t r ut h t able. In t his way, a
MUX can be used as a simple look-up t able for swit ching funct ions. This facilit y makes t he
MUX a ver y gener al pur pose logic device.
Fig 4.20 A four-line t o 1-line mult iplexer
Example. Use a 4 line t o 1 line MUX t o implement t he funct ion shown in t he following
t rut h t able (Y = A. B + A.B).
Fig. 4.21 A 4-line t o 1-line MUX implement at ion of a funct ion of 2 var iables
Simply connect ing I
0
= 1, I
1
= 0, I
2
= 0, I
3
= 1, and t he input s A and B t o t he S
1
and S
0
select or input s of t he 4-line t o 1-line MUX implement t his t r ut h t able, as shown in Fig. 4.21.
The 4-line t o 1-line MUX can also be used t o implement any funct ion of t hr ee logical
var iables, as well. To see t his, we need not e only t hat t he only possible funct ions of one
var iable C, ar e C, C, and t he const ant s 0 or 1. (i.e., C, C, C + C = 1, and 0). We need only
connect t he appr opr iat e value, C,
C
, 0 or 1, t o I
0
, I
1
, I
2
, I
3
t o obt ain a funct ion of 3 var iables.
The MUX st ill behaves as a t able lookup device; it is now simply looking up values of anot her
var iable.
Example. Implement t he funct ion
Y(A, B, C) = A. B. C + A.B. C + A. B. C + A. B. C
Using a 4-line t o 1-line MUX.
Her e, again, we use t he A and B var iables as dat a select input s. We can use t he above
equat ion t o const r uct t he t able shown in Fig. 4.22. The r esidues ar e what is “left over ” in each
mint er m when t he “addr ess” var iables ar e t aken a way. To implement t his cir cuit , we connect
I
0
and I
3
t o C, and I
1
and I
2
to
C
, as shown in Fig. 4.22.
158 S witching Theory
Fig. 4.22 A 4-line t o 1-line MUX implement at ion of a funct ion of 3 var iables
In gener al a 4 input MUX can give any funct ion of 3 input s, an 8 input MUX can give
any funct ional of 4 var iables, and a 16 input MUX, any funct ion of 5 var iables.
Example. Use an 8 input MUX t o implement t he following equat ion:
Y = A. B. C. D + A. B. C.D + A.B. C.D + A.B. C. D + A. B. C.D + A. B. C. D

+ A.B. C. D + A.B. C.D
Again, we will use A, B, C as dat a select input s, or addr ess input s, connect ed t o S
2
, S
1
and S
0
, r espect ively.
Fig. 4.23 An 8-line t o 1-line MUX implement at ion of a funct ion of 4 var iables
Values of t he addr ess set A, B, C wit h no r esidues cor r esponding t o t he addr ess in t he
above t able must have logic value 0 connect ed t o t he cor r esponding dat a input . The select
var iables A, B, C must be connect ed t o S
2
, S
1
and S
0
r espect ively. A cir cuit which implement s
t his funct ion is shown in Fig. 4.23.
This use of a MUX as a “t able look up” device can be ext ended t o funct ions of a lar ger
number of var iables; t he MUX effect ively r emoves t he t er ms involving t he var iables assigned
t o it s select input s fr om t he logic expr ession. This can somet imes be an effect ive way t o
r educe t he complexit y of implement at ion of a funct ion. For complex funct ions, however, t her e
ar e oft en bet t er implement at ions, as we use PLDs (see chapt er 5).
Alt hough it is obvious how t he funct ion shown in Fig. 4.20 can be ext ended a 2
n
line
t o 1 line MUX, for any n, in pr act ice, about t he lar gest devices available ar e only t o 16 line
t o 1 line funct ions. It is possible t o use a “t r ee” of smaller MUX’s t o make ar bit r ar ily lar ge
MUX’s. Fig. 4.24 shows an implement at ion of a 16 line t o 1 line MUX using five 4 line t o
1 line MUX’s.
Combinational Logic 159
Fig. 4.24 A 16-line t o 1-line MUX made fr om five 4-line t o 1-line MUX’s
4.2.2 De c od e rs ( De multip le xe rs)
Anot her commonly used MSI device is t he decoder. Decoder s, in gener al, t r ansfor m a set
of input s int o a differ ent set of out put s, which ar e coded in a par t icular manner ; e.g., cer t ain
decoder s ar e designed t o decode binar y or BCD coded number s and pr oduce t he cor r ect out put
t o display a digit on a 7 segment (calculat or t ype) display. Decoder s ar e also available t o
conver t number s fr om binar y t o BCD, fr om binar y t o hexadecimal, et c.
Normally, however, the term “decoder” implies a device which performs, in a sense, t he
inverse operat ion of a mult iplexer. A decoder accept s an n digit number as it s n “select ” input s
and produces an out put (usually a logic 0) at one of it s possible out put s. Decoders are usually
referred to as n line t o 2
n
line decoders; e.g. a 3 line t o 8 line decoder. This t ype of decoder
is really a binary t o unary number syst em decoder. Most decoders have invert ed out put s, so
t he select ed out put is set t o logic 0, while all t he ot her out put s remain at logic 1. As well, most
decoders have an “enable” input E , which “enables” t he operat ion of t he decoder—when t he E
input is set t o 0, t he device behaves as a decoder and select s t he out put det ermined by t he
select input s; when t he E input is set t o 1, t he out put s of t he decoder are all set t o 1. (The
bar over t he E indicat es t hat it is an “act ive low” input ; t hat is, a logic 0 enables t he funct ion).
160 S witching Theory
The enable input also allows decoder s t o be con-
nect ed t oget her in a t reelike fashion, much as we saw for
MUX’s, so large decoders can be easily const ruct ed from
smaller devices. The enable input also allows t he decoder
t o perform t he inverse operat ion of a MUX; a MUX se-
lect s as out put one of 2
n
input s, t he decoder can be used
t o present an input t o one of 2
n
out put s, simply by con-
nect ing t he input signal t o t he E input ; t he signal at t he
select ed out put will t hen be t he same as t he input at
E

t h i s a ppl i ca t i on i s ca l l ed “demu l t i pl exi n g. ” Th e
demult iplexer (DEMUX) performs t he reverse operat ion
of a mult iplexer. A demult iplexer is a circuit t hat accept s
single input and t ransmit it over several (one of 2
n
pos-
sible) out put s.
In t he block diagr am (Fig. 4.25) a demult iplexer, t he number of out put lines is n and t he
number of select lines is m.
where n = 2
m
One t he basis of select input code, t o which out put t he dat a will be t r ansmit t ed is
det er mined. Ther e is an act ive-low (low-logic) enable/dat a input . The out put for t hese devices
ar e also act ive-low.
Note. 4-line t o 16-line decoder s ar e t he lar gest available cir cuit s in ICs.
A t ypical 3 line t o 8 line decoder wit h an enable input behaves accor ding t o t he following
t r ut h t able, and has a cir cuit symbol as shown in Fig. 4.26.
Fig. 4.26 An 3-line t o 8-line decoder
Not e t hat , when t he E input is enabled, an out put of 0 is pr oduced cor r esponding t o each
mint er m of S
2
, S
1
, S
0
. These mint er m can be combined t oget her using ot her logic gat es t o
for m any r equir ed logic funct ion of t he input var iables. In fact , sever al funct ions can be
pr oduced at t he same t ime. If t he select ed out put was a logic 1, t hen t he r equir ed mint er ms
could simply be ORed t oget her t o implement a swit ching funct ion dir ect ly fr om it s mint er m
for m. Using de Mor gans t heor em, we can see t hat when t he out put s ar e inver t ed, as is
nor mally t he case, t hen t he mint er m for m of t he funct ion can be obt ained by NANDing t he
r equir ed t er ms t oget her.
Example. An implement at ion t he funct ions defined by t he following t r ut h t able using a
decoder and NAND gat es is shown in Fig. 4.27.
Fig. 4.25 Block diagr am of t he
demult iplexer /decoder
Combinational Logic 161
Fig. 4.27
IM PLEM ENTATIO N EXAM PLES O F C O M BINATIO NAL LO G IC DESIG N USING
M UX / DEM UX
We have alr eady seen how t o implement combinat ional cir cuit s using MUX/DEMUX. The
st andar d ICs available for mult iplexer s ar e 2:1, 4:1, 8:1 and 16:1. The differ ent digit al ICs ar e
given in appendix B, but for sake of convenience some of t he MUX/DEMUX ICs ar e given
here in Tables A and B.
Table A: Standard multi plexer ICs
IC No. Description Output
74157 Quad. 2:1 Mult iplexer Same as input
74158 Quad 2:1 MUX Inver t ed input
74153 Dual 4:1 MUX Same as input
74352 Dual 4:1 MUX Inver t ed input
74151A 8:1 MUX Complement ar y out put s
74152 8:1 MUX Inver t ed input
74150 16:1 MUX Inver t ed input
Table B: Standard Demulti plexer/Decoder ICs
IC No. Description Output
74139 Dual 1:4 Demult iplexer Inver t ed input
(2-line-t o-4-line decoder )
74155 Dual 1:4 Demult iplexer 1Y-Inver t ed I/P
(2-line-t o-4-line decoder ) 2Y-Same as I/P
74138 1:8 Demult iplexer Inver t ed I/P
(3-line-t o-8-line decoder )
74154 1:16 Demult iplexer Same as input
(4-line-t o-16-line decoder )
When using t he mult iplexer as a logic element eit her t he t r ut h t able or one of t he
st andar d for ms of logic expr ession must be available. The design pr ocedur e for combinat ional
cir cuit s using MUX ar e as follows:
162 S witching Theory
STEP 1: Ident ify t he decimal number cor r espond-
ing t o each mint er m in t he expr ession. The input lines
cor r esponding t o t hese number s ar e t o be connect ed t o
logic 1 (high).
STEP 2 : All ot her input lines except t hat used in
st ep 1 ar e t o be connect ed t o logic 0 (low).
STEP 3 : The cont r ol input s ar e t o be applied t o
select input s.
Example. Implement the following function with
multiplexer.
Y = F (A, B, C, D) = Σm (0, 1, 3, 4, 8, 9, 15)
Solution. STEP 1 : The input lines cor r espond-
ing t o each mint er ms (decimal number ) ar e t o be con-
nect ed t o logic 1.
Ther efor e input lines 0, 1, 3, 4, 8, 9, 15 have t o
be connect ed t o logic 1.
STEP 2 : All ot her input lines except 0, 1, 3, 4, 8,
9, 15 ar e t o be connect ed t o logic 0.
STEP 3 : The cont rol input s A, B, C, D ar e t o be applied t o select input s.
Note: Alt hough t he given pr ocedur e is simple t o implement but t he 16 t o 1 mult iplexer s ar e
t he lar gest available ICs, t her efor e t o meet t he lar ger input needs t her e should be pr ovision for
expansion. This is achieved wit h t he help of enable/st r oke input s and mult iplexer st acks or t r ees ar e
designed.
Example. Implement the following function with a 4×1 multiplexer.
Y = F (A, B, C) = Σm (1, 3, 5, 6)
Solution. Given Y = F (A, B, C) = Σm (1, 3, 5, 6)
=
A BC + ABC + ABC + ABC
We use t he A and B var iables as dat a select input s. We can use t he above equat ion t o
const r uct t he t able shown in Fig. 4.28. The r esidues ar e what is “left over ” in each mint er m
when the “addr ess” var iables ar e t aken away.
Input “Address” Other variables
(residues)
I
0
A B C
I
1 AB
C
I
2 AB
C
I
3
AB
C
Fig. 4.28 A 4-line t o 1-line MUX implement at ion of a funct ion of 3 var iables.
To implement t his cir cuit , we connect I
0
, I
1
and I
2
t o C and I
3
t o
C
as shown in Fig. 4.28.
Example. Using four-input multiplexer, implement the following function
Y = F (A, B, C) = Σm (0, 2, 3, 5, 7)
Control variables A, B.
I
I
I
I
0
1
2
3
Y
C
1
C
C
S
1
S
0
B A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Y
S
3
S
1
C A
S
2
B
S
0
D
16 : 1
MUX
Logic 1 Logic 0
E
(MSB) (LSB)
Combinational Logic 163
Solution. Given Y = F (A, B, C) = Σm (0, 2, 3, 5, 7)
=
ABC + ABC + ABC + ABC + ABC
We can use t he above equat ion t o const r uct t he t able shown in Fig. 4.29. The r esidues
are what is “left over ” in each mint er m when t he “addr ess/cont r ol” var iables ar e t aken away.
Input “Address” Other variables
(residues)
I
0
A B
C
I
1 AB
C+ C = 1
I
2 AB
C
I
3
AB C
Fig. 4.29 A 4-line t o 1-line MUX implement at ion of a funct ion of 3 var iables
To implement t his funct ion, we connect I
0
to
C
, I
1
t o 1 and I
2
and I
3
t o C, as shown
in Fig. 4.29.
Example. Design a full adder using 8:1 multiplexer.
Solution. The t r ut h t able of a full adder is given as
A B C S C
F
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
S (A, B, C) =
A BC + ABC + AB C + ABC = Σm ( , , , ) 1 2 4 7
C
F
(A, B, C) = ABC + ABC + ABC + ABC = (3, 5, 6, 7) Σm
The implement at ion for summat ion expr ession is
Step 1: The input lines cor r esponding t o 1, 2, 4, 7 ar e t o be connect ed t o logic 1.
Step 2: Ot her input lines ar e t o be connect ed t o logic 0.
Step 3: Cont rol input s A, B, C ar e t o be applied t o select input s. Fig. 4.30 A.
Similar ly for car r y expr ession.
Step 1: The input lines cor r esponding t o 3, 5, 6, 7 ar e t o be connect ed t o logic 1.
Step 2: Ot her input lines ar e t o be connect ed t o logic 0.
Step 3: Cont rol input s A, B, C ar e t o be applied t o select input s. Fig. 4.30 B.
I
I
I
I
0
1
2
3
Y
C
C
C
C
S
1
S
0
B A
4 : 1
MUX
164 S witching Theory
0
1
2
3
4
5
6
7
S
S
1
C A
S
2
B
S
0
8 : 1
MUX
Logic 1 Logic 0
0
1
2
3
4
5
6
7
C
F
S
1
C A
S
2
B
S
0
8 : 1
MUX
Logic 1 Logic 0
(A) (B)
Fig. 4.30 Full adder implement at ion using 8:1 Mult iplexer.
Example. Implement a full adder with a decoder and two OR-gates.
Solution. Fr om t he pr evious example we not e t hat expr ession for summat ion is given
by
S (A, B, C) = Σm (1, 2, 4, 7)
and expr ession for car r y is given by
C
F
(A, B, C) = Σm (3, 5, 6, 7)
The combinat ional logic of full adder can be implement ed wit h due help of 3-line t o 8-
line decoder /1:8 demult iplexer as shown in Fig. 4.31.
0
1
2
3
4
5
6
7
3 × 8
decoder
LSB
MSB
S
C
B
A
Fig. 4.31 Full adder implement at ion using 3 × 8 decoder.
Example. A combinational circuit is defined by the following Boolean functions. Design
circuit with a decoder and external gates.
Soluti on. Y
1
= F
1
(A, B, C) =A B C + AC
Y
2
= F
2
(A, B, C) = ABC + AC
Given Y
1
= A B C + AC
Fir st we have t o wr it e t he expr ession in mint er ms, if t he expr ession is not in t he for m
of mint erms by using (x x + = 1)
Combinational Logic 165
Fig. 4.32 Funct ion implement at ion using 3×8 decoder.
Ther efor e Y
1
= A BC + AC
Y
1
=
ABC + AC (B + B)
Y
1
= A BC + ABC + ABC
Y
1
= Σm (0, 5, 7)
Y
2
=
ABC + AC
Y
2
=
ABC + AC (B + B)
Y
2
=
ABC + ABC + ABC
Y
2
= Σm (1, 3, 5)
The combinat ional logic for t he boolean funct ion can be implement ed wit h t he help of
3-line t o 8-line decoder as shown in Fig 4.32.
Example. Realise the given function using a multiplexer
Y(A, B, C, D) = ΠM (0, 3, 5, 9, 11, 12, 13, 15)
Solution. To implement t he given funct ion, fir st we have t o expr ess t he funct ion in
t erms of sum of product . i.e.,
Y (A, B, C, D) = Σm (1, 2, 4, 6, 7, 8, 10, 14)
Now t he given funct ion in t his for m can be r ealized as
Step 1: Input lines corresponding t o 1, 2, 4, 6, 7, 8, 10, 14 are t o be connect ed t o logic 1.
Fig. 4.33 A 16-line t o 1-line MUX implement at ion.
166 S witching Theory
Step 2: Ot her input lines ar e t o be connect ed t o logic 0.
Step 3: Cont rol input s A, B, C, D ar e t o be applied t o select input s.
Example. Realize the following boolean expression using 4:1 MUX(S ) only.
Z =
A B C D ABCD AB CD AB CD AB C D ABCD + + + + +
Solution. Given Z = Σm (0, 6, 8, 10, 11, 15)
To implement t he given boolean expr ession we must have 16 input and 4 select ion
input s.
Since 4:1 mux has 4 input lines and t wo select ion lines. Ther efor e we can use 4, 4:1 MUX
wit h t heir select lines connect ed t oget her. This is followed by a 4:1 MUX t o select one of t he
four out put s. The select lines of t he 4:1 MUX (final) ar e dr iven fr om input s A, B. The complet e
cir cuit is shown in Fig. 4.34.
0
1
2
3
4 : 1
MUX
C D
4
5
6
7
4 : 1
MUX
C D
8
9
10
11
4 : 1
MUX
C D
12
13
14
15
4 : 1
MUX
C D
I
I
I
I
0
1
2
3
4 : 1
MUX
A B
Logic 0 Logic 1
Z
S
1
S
0
Fig. 4.34 A 4-line t o 1-line MUX implement at ion of a funct ion of 4 var iable.
Combinational Logic 167
Encoder
m
Inputs
n
Inputs
Fig. 4.35 Block Diagr am of an Encoder
4.2.3 Enc od e rs
The encoder is anot her example of combi-
nat ional cir cuit t hat per for ms t he inver se oper a-
t ion of a decoder. It is disigned t o gener at e a
diffr ent out put code for end input which becomes
act ive. In gener al, t he encoder is a cir cuit wit h
m input lines ( ) * m
n
≤ 2 (* m < 2
n
→ If unused
input combinat ions occur.) and n out put lines that
concert s an act ive input signal int o a coded out put signal. In an encoder, the number of out put s
is less than the number of input s. The block diagram of an encoder is shown in Fig. 4.35.
An example of an encoder is an oct al t o binar y encoder. An oct al t o binar y encoder accept
eight input s and pr oduces a 3-bit out put code cor r esponding t o t he act ivat ed input . The t r ut h
t able for t he oct al t o binar y encoder is shown in t able.
Inputs Outputs
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Y
2
Y
1
Y
0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
It has eight input s, one for each oct al digit and t hr ee out put s t hat gener at e t he cor r e-
sponding binar y number.
The t r ut h t able shows t hat Y
0
must be 1 whenever t he input O
1
or O
3
or O
5
or O
7
is
high. Thus,
Y
0
= O
1
+ O
3
+ O
5
+ O
7
Similarly Y
1
= O
2
+ O
3
+ O
6
+ O
7
and
Y
2
= O
4
+ O
5
+ O
6
+ O
7
.
Using t hese t hr ee expr essions, t he cir cuit can be implement ed using t hr ee 4-input OR
gat es as shown in Fig. 4.36.
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Y
0
Y
1
Y
2
Fig. 4.36 Oct al t o binar y encoder.
168 S witching Theory
The encoder has t wo limit at ions:
1. Only one input can be act ive at any given t ime. If t wo or mor e input s ar e equal
t o 1 at t he same t ime, t he O/P is undefined. For example if O
2
and O
5
ar e act ive
similt aneously, t he o/p of encoder will be 111 t hat is equal t o binar y 7. This does
not r epr esent binar y 2 or 5.
2. The out put wit h all O’s is gener at ed when all input s ar e ‘O’, and is also t r ue when
O
0
= ‘1’.
The fir st pr oblem is t aken car e by a cir cuit , called as ‘pr ior it y encoder ’. If est ablishes a
pr ior it y t o ensur e t hat only one input is act ive (High) at a given t ime.
The second pr oblem is t aken car e by an ext r a line in t he encoder out put , called ‘valid
out put indicat or ’ t hat specifies t he condit ion t hat none of t he input s ar e act ive.
Prio rity Enc o d e r
A pr ior it y encoder is an encoder t hat includes pr ior it y funct ion. If t wo or mor e input s
ar e equal t o 1 at t he same t ime, t he input having t he highest pr ior it y will t ake pr ecedence.
To under st and pr ior it y encoder, consider a 4 t o 2 line encoder which gives pr ior it y t o higher
subscr ipt number input t han lower subscr ipt number. The t r ut h t able is given below.
Truth Table of 4 t o 2 line pr ior it y encoder :
Inputs Outputs
D
0
D
1
D
2
D
3
Y
1
Y
2
V
0 0 0 0 x x 0
1 0 0 0 0 0 1
x 1 0 0 0 1 1
x x 1 0 1 0 1
x x x 1 1 1 1
The Xs ar e don’t car e condit ions. Input D
3
has t he highest pr ior it y, so r egar dless of
values of ot her input s, when t his input is 1, t he out put Y
1
Y
2
= 11. D
2
has next pr ior it y level.
The o/p is 10 if D
2
is 1, pr ovided D
3
= 0, ir r espect ive of t he values of t he ot her t wo lower -
pr ior it y input s. The o/p is 01 if D
1
is 1, pr ovided bot h D
2
and D
3
ar e O, ir r espect ive of t he
value of lower -pr ior it y input D
0
. The o/p is D
0
if 00 = 1, pr ovided all ot her input s ar e 0.
A valid out put indicat or, V is set t o 1, only when one or mor e of t he input s ar e equal
t o 1. If all t he input s ar e O, V is equal t o O. and t he ot her t wo out put s if t he cir cuit ar e not
used.
Now, simplifying using k-map t he out put s can be wr it t en as :
Y
1
= D
2
+ D
3
Y
2
= D
3
+ D
1
D
2
'
V = D
0
+ D
1
+ D
2
+ D
3
.
The logic diagr am for a 4 t o 2 line pr ior it y encoder wit h ‘valid out put indicat or ’ is shown
below in Fig. 4.37.
Combinational Logic 169
D
0
D
1
D
2
D
3
Y
1
Y
2
V
Fig. 4.37
4.2.4 Se ria l a nd Pa ra lle l Ad d e rs
In sect ion 4.1.1 we have discussed t he full-adder cir cuit . Full adder is a combinat ional
cir cuit t hat adds t hr ee binar y digit s. When we add t wo number s of any lengt h, t he t er ms we
have t o deal wit h ar e :
Input car r y, Augend, Addend, sum and out put car r y. We simply st ar t adding t wo binar y
digit s fr om LSB (r ight most posit ioned bit s). At t his posit ion, t he input car r y is always equal
t o zer o. Aft er addit ion, we get sum and out put car r y. This out put car r y wor ks as t he input
car r y t o t he next higher posit ioned augend and addend bit s. Next we add augend and addend
bit s along wit h t he input car r y t hat again pr oduces sum and out put car r y. The pr ocess r epeat s
upt o MSB posit ion (left most posit ioned bit s).
We obser ve t hat in t he pr ocess of addit ion we ar e act ually adding t hr ee digit s – t he input
car r y, t he augend bit and t he addend bit . And, we ar e get t ing t wo out put s t he sum and t he
out put car r y.
This can be illust r at ed by t he following example. Let t he 4-bit s wor ds t o be added be
r epr esent ed by:
A
3
A
2
A
1
A
0
= 1 1 0 1 and B
3
B
2
B
1
B
0
= 0 0 1 1.
Significant Place 4 3 2 1
Input Carry 1 1 1 0
Augend Word 1 1 0 1
Addend Word 0 0 1 1
Sum output carry 0 0 0 0
1 1 1 1
Carry-In
Carry-out
Now if we compar e t his wit h t he full adder cir cuit , we can easily obser ve t hat t he t wo
input s (A and B) ar e augend and addend bit s wit h t he t hir d input (c) as t he input car r y.
Similar ly t wo out put s ar e sum (s) and out put car r y (C
0
).
In general, t he sum of t wo n-bit number s can be gener at ed by using eit her of t he t wo
met hods : t he ser ial addit ion and t he par allel addit ion.
170 S witching Theory
Se ria l Ad d e r
In ser ial addit ion, t he addit ion oper at ion is car r ied out bit by bit . The ser ial adder uses
one full adder cir cuit and some st or age device (memor y element ) t o hold gener at ed out put
car r y. The diagr am of a 4 bit ser ial adder is shown in Fig. 4.38.
The t wo bit s at t he same posit ions in augend and addend wor d ar e applied ser ialy t o A
and B input s of t he full adder r espect ively. The single full adder is used t o add one pair of
bit s at a t ime along wit h t he car r y C
in
. The memor y element is used t o st or e t he car r y out put
of t he full adder cir cuit so t hat it can be added t o t he next significant posit ion of t he nember s
in t he augend and addend wor d. This pr oduces a st r ing of out put bit s for sum as S
0
, S
1
, S
2
and S
3
r espect ively.
A
B
C
S
C
out
Full
Adder
Circuit
A
3
A
2
A
1
A
0
B
3
B
2
B
1
B
0
Augend word
Addend Word
Input Carry-Cin
(Always ‘O’ at LSB)
O
S
3
S
2
S
1
S
0
Sum output
Output Carry
Storage Device
(Memory element)
Fig. 4.38 4-bit ser ial adder.
Pa ra lle l Ad d e r
To add t wo n-bit number s, t he par ellel met hod uses n full adder cir cuit s and all bit s of
addend and augend bit s ar e applied simult aneously. The out put car r y fr om one full adder is
connect ed t o t he input car r y of t he full adder one posit ion t o it s left .
The 4-bit adder using full adder cir cuit is capable of adding t wo 4-bit number s r esult ing
in a 4-bit sum and a car r y out put as shown in Fig. 4.39.
A
3
B
3
C
4
C
out
S
3
Full
Adder
C
3
A
2
B
2
C
3
S
2
Full
Adder
C
2
A
1
B
1
C
1
S
1
Full
Adder
C
0
A
0
B
0
C
1
S
0
Full
Adder
C
0
C
i n = 0
Fig. 4.39 4-bit binar y par allel adder.
The addit ion oper at ion is illust r at ed in t he following example. Let t he 4-bit wor ds t o be
added be represent ed by A
3
A
2
A
1
A
0
= 1 0 1 0 and B
3
B
2
B
1
B
0
= 0 0 1 1.
S ubscript i 3 2 1 0 ← Significant place.
Input car r y C
i
0 1 0 0
Augend A
i
1 0 1 0
Addend B
i
0 0 1 1
Sum S
i
1 1 0 1
Out put car r y C
i+1
0 0 1 0
Combinational Logic 171
In a 4-bit par allel adder, t he input t o each full adder will be A
i
, B
i
and C
i
, and t he out put s
will be S
i
and C
i+1
, where i var ies fr om 0 t o 3.
In t he least significant st age, A
0
, B
0
and C
0
(which is 0) ar e added r esult ing in sum S
0
and car r y C
1
. This car r y C
1
becomes t he car r y input t o t he second st age. Similar ly, in t he
second st age, A, B, and C ar e added r esult ing in S
1
and C
2
; in t he t hir d st age, A
2
B
2
and C
2
ar e added r esult ing in S
2
and C
3
; in t he fourt h st age A
3
, B
3
and C
3
ar e added r esult ing in
S
3
and C
4
which is t he out put car r y. Thus t he cir cuit r esult s in a sum (S
3
, S
2
, S
1
, S
0
) and
a car r y out put (C
out
).
An alt er nat ive block diagr am r epr esent at ion of a 4 bit binar y par allel adder is shown in
Fig. 4.40.
B
3
B
2
B
1
B
0
A
3
A
2
A
1
A
0
4-bit
binary
parallel adder
S
3
S
2
S
1
S
0
C
i n
C
out
Addend Augland
Fig. 4.40 4-bit binar y par allel adder.
Propagation Delay: Though t he parallel binary adder is said t o generat e it s out put
immediat ely aft er t he input s are applied, it speed of operat ion is limit ed by t he carry propaga-
t ion delay t hrough all st ages. In t he parallel binary adder, t he carry generat ed by t he adder is
fed as carry input t o (i + 1)t h adder. This is also called as ‘ripple carry adder’. In such adders,
t he out put (C
out
S
3
, S
2
, S
1
, S
0
) is available only aft er t he carry is propogat ed t hrough each of
the adders, i.e., from LSB t o MSB adder t hrough int ermediat e adders. Hence, t he addit ion
process can be considered t o be complet e only aft er t he carry propagat ion delay t hrough adders,
which is proport ional t o number of st ages in it ; one of t he met hods of speeding up t his process
is look-ahead carry addit ion, which eliminat es t he ripple carry delay. This met hod is based on
t he carry generat ing and t he carry propagat ing funct ions of t he full adder.
4- b it Look- a he a d C a rry G e ne ra tor
The look-ahead car r y gener at or is based on t he pr inciple of looking at t he lower or der
bit s of addend and augend if a higher or der car r y is gener at ed. This r educes t he car r y delay
by r educing t he number of gat es t hr ough which a car r y signal must pr opagat e. To explain it s
oper at ion consider t he logic diagr am of a full adder cir cuit Fig. 4.41.
Augend Ai
Addend Bi
C
i +1
(o/p carry)
S
i
(sum)
P
i
G
i
I/P
Carry
Ci
Fig. 4.41 Full Adder
172 S witching Theory
We define t wo new int er mediat e out put var iable Pi and Gi.
P
i
= A
i
⊕ B
i
; called car r y pr opagat e, and
G
i
= A
i
. B
i
, called car r y gener at e.
We now wr it e t he Boolean funct ion for t he car r y out put of each st age and subst it ut e for
each C
i
it s value fr om t he pr evious equat ions :
C
1
= G
0
+ P
0
C
0
C
2
= G
1
+ P
1
C
1
= G
1
+ P
1
(G
0
+ P
0
C
0
) = G
1
+ P
1
G
0
+ P
1
P
0
C
0
.
C
3
= G
2
+ P
2
C
2
= G
2
+ P
2
(G
1
+ P
1
G
0
+ P
1
P
0
C
0
)
= G
2
+ P
2
G
1
+ P
2
P
1
G
0
+ P
2
P
1
P
0
C
0
.
Not e t hat C
3
does not have t o wait for C
2
and C
1
t o pr opagat e; in fact C
3
is pr opagat ed
at t he same t ime as C
1
and C
2
.
Next we dr aw t he logic diagr am of t his 4 bit look-ahead car r y gener at or as shown in
Fig. 4.42.
C
3
C
2
C
1
P
2
G
2
P
1
G
1
P
0
G
0
C
0
Fig. 4.42 4-bit look-ahead car r y gener at or.
4- b it b ina ry p a ra lle l a d d e r with a look- a he a d c a rry g e ne ra tor ( FAST ADDER)
In t he 4-bit look ahead car r y gener at or. We have seen t hat all t he car r y out put s ar e
gener at ed simult aneously wit h t he applicat ion of Augend wor d, addend wor d and t he input
car r y. What is r emaining ar e t he sum out put s. Fr om t he newly defined full adder cir cuit of
Fig. 4.41, we not ice t hat t he sum out put S
i
= P
i
⊕ C
i
.
⇒ S
0
= P
0
⊕ C
0
= A
0
⊕ B
0
⊕ C
0
S
1
= P
1
⊕ C
1
= A
1
⊕ B
1
⊕ C
1
S
2
= P
2
⊕ C
2
= A
2
⊕ B
2
⊕ C
2
S
3
= P
3
⊕ C
3
= A
3
⊕ B
3
⊕ C
3
.
Similar ly car r y out put C
i+1
= G
1
+ P
i
C
i
⇒ Final o/p carry ⇒ C
4
= G
3
+ P
3
C
3
.
Combinational Logic 173
Using t he above equat ions, t he 4-bit binar y par allel adder wit h a look ahead car r y
gener at or can be r ealized as shown in Fig. 4.43.
B
3
A
3
P
3
G
3
C
4
C
3
P
3
S
3
Output carry
B
2
A
2
P
2
G
2
C
2
P
2
S
2
B
1
A
1
P
1
G
1
C
1
P
3
S
1
B
0
A
0
P
0
G
0
P
0
S
0
Input
Carry
C
0
C
0
4-bit
Look-aheed
Carry
Generator
of
Fig. 4.42
Fig. 4.43 Four bit binar y par allel adder wit h look-ahead car r y gener at or.
Fr om t he diagr am, not e t hat t he addit ion of t wo 4 bit number s can be done by a look
ahead car r y gener at or in a 4 gat e pr opagat ion t ime (4 st age implement at ion). Also, it is
impor t ant t o r ealize t hat t he addit ion of n-bit binar y number s t akes t he same 4-st age pr opa-
gat ion delay.
4- b it Pa ra lle l Ad d e r/ Sub tra c tor
The 4-bit binar y par allel adder /subt r act or can be r ealized wit h t he same cir cuit t aking
int o consider at ion t he 2’s complement met hod of subt r act ion and t he cont r olled inver sion
pr oper t y of t he exclusive or gat e.
The subt r act ion of t wo binar y number by t aking 2’s complement of t he subt r ahend and
adding t o t he minuend. The 2’s complement of t he subt r ahend can be obt ained by adding 1
t o t he 1’s complement of t he subt r ahend.
Fr om t he example OR oper at ion, we know when one of t he input is low t he out put is
same as t he ot her input and when ar e of t he input is high t he out put is t he complement of
t he ot her input .
Control input C
Other input X
Y
Y = C X' + C' X
Nat ur ally, if C = 0, Y = X
C = 1, Y = X'
174 S witching Theory
The 4-bit binar y par allel adder /subt r act or cir cuit is shown in Fig. 4.44. t hat per for m t he
oper at ion of bot h addit ion and subt r act ion. If has t wo four bit input s A
3
A
2
A
1
A
0
and B
3
B
2
B
1
B
0
. The cont r ol input line C, connect ed wit h t he input car r y of t he LSB of t he full adder,
is used t o per for m bot h oper at ions.
To per for m subt r act ion, t he C (cont r ol input ) is kept high. The cont r olled inver t er pr o-
duces t he 1' s complement of t he adder (B
3
' B
2
' B
1
' B
0
'). Since 1 is given t o input car r y of t he
LSB of t he adder, it is added t o t he complement ed addend pr oducing 2' s complement of t he
addend befor e addit ion.
A
3
B
3
A
2
B
2
A
1
B
1
A
0
B
0
C
4
S
3
C
3
S
2
C
2
S
1
C
1
S
0
FA FA FA FA
C
0
Output
Carry C →
out
Control
Input C
i n
Input
carry
C
i n
Fig. 4.44 Bit binar y par allel adder /subt r act or.
Now t he angend (A
3
A
2
A
1
A
0
) will be added t o t he 2's complement of addend (B
3
B
2
B
1
B
0
)
t o pr oduce t he sum, i.e., t he diffr ence bet ween t he addend and angend, and C
out
(out put
car r y), i.e. t he bor r ow out put of t he 4-bit subt r act or.
When t he cont r ol input ‘C’ is kept low, t he cont r olled inver t er allows t he addend (B
3
B
2
B
1
B
0
) wit hout any change t o t he input of full adder, and t he input car r y C
in
of LSB of full
adder, becomes zer o, Now t he augend (A
3
A
2
A
1
A
0
) and addend (B
3
B
2
B
1
B
0
) ar e added wit h
C
in
= 0. Hence, t he cir cuit funct ions as 4-bit adder r esult ing in sum S
3
S
2
S
1
S
0
and car r y
out put C
out
.
4.2.5 De c ima l Ad d e r
A BCD adder is a combinat ional cir cuit t hat adds t wo BCD digit s in par allel and pr oduces
a sum digit which is also in BCD. The block diagr am for t he BCD adder is shown in Fig. 4.45.
This adder has t wo 4-bit BCD input s A
8
A
4
A
2
A
1
and B
8
B
4
B
2
B
1
and a car r y input C
in
. It
also has a 4-bit sum out put S
8
S
4
S
2
S
1
and a car r y out put C
out
. Obviously t he sum out put
is in BCD for m. (This is why subscr ipt s 8, 4, 2, 1 ar e used).
If we consider t he ar it hmet ic addit ion of t wo decimal digit s in BCD, t he sum out put can
not be gr eat er t han 9 + 9 + 1 = 19. (Since each input digit does not exceed 9 and 1 being t he
possible car r y fr om pr evious st age).
Suppose we apply t wo BCD digit s t o a 4-bit binar y par allel adder. The adder will for m
t he sum in binar y and pr oduce a sum t hat will r ange fr om 0 t o 19. But if we wish t o design
a BCD adder, it must be able t o do t he following.
Combinational Logic 175
1. Add t wo 4-bit BCD number s using st r aight binar y addit ion.
2. If t he four bit sum is equal t o or less t han 9, t he sum is in pr oper BCD for m.
3. If t he four bit sum is gr eat er t han 9 or if a car r y is gener at ed fr om t he sum, t he
sum is not in BCD for m. In t his case a cor r ect ion is r equir ed t hat is obt ained by
adding t he digit 6 (0110) t o t he sum pr oduced by binar y adder.
B
8
B
4
B
2
B
1
A
8
A
4
A
2
A
1
S
8
S
4
S
2
S
1
Input carry
(C
i n
)
Output
carry (C
out
)
Addend
BCD digit
Augend
BCD digit
Fig. 4.45 Block diagr am of a BCD adder.
The t able shows t he r esult s of BCD addit ion wit h needed cor r ect ion.
Decimal Uncorrected Corrected
Digit BCD sum BCD sum
produced by produced by
Binary Adder. BCD Adder.
K Z
8
Z
4
Z
2
Z
1
C S
8
S
4
S
2
S
1
0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0 0 1
2 0 0 0 1 0 0 0 0 1 0
3 0 0 0 1 1 0 0 0 1 1
4 0 0 1 0 0 0 0 1 0 0
5 0 0 1 0 1 0 0 1 0 1
6 0 0 1 1 0 0 0 1 1 0
7 0 0 1 1 1 0 0 1 1 1
8 0 1 0 0 0 0 1 0 0 0
9 0 1 0 0 1 0 1 0 0 1
10 0 1 0 1 0 1 0 0 0 0
11 0 1 0 1 1 1 0 0 0 1
12 0 1 1 0 0 1 0 0 1 0
13 0 1 1 0 1 1 0 0 1 1
13 0 1 1 0 1 1 0 0 1 1
14 0 1 1 1 0 1 0 1 0 0
15 0 1 1 1 1 1 0 1 0 1
16 1 0 0 0 0 1 0 1 1 0
17 1 0 0 0 1 1 0 1 1 1
18 1 0 0 1 0 1 1 0 0 0
19 1 0 0 1 1 1 1 0 0 1
U
V
|
|
|
|
|
|
|
W
|
|
|
|
|
|
|
No
Cor r ect ion
Requir ed
U
V
|
|
|
|
|
|
|
W
|
|
|
|
|
|
|
Cor r ect ion
Requir ed
176 S witching Theory
The binary numbers are list ed, labled as K Z
8
Z
4
Z
2
Z
1
. K is t he out put carry and subscript
under Z represent t he weight 8, 4, 2 and 1. The first t able list s t he binary sums as produced
by a 4-bit binary adder. For represent ing t hem in BCD, t hey must appear as second t able.
Fr om t he t wo t ables it is clear t hat upt o 9, t he binar y sum is same as t he BCD sum,
so no cor r ect ion is r equir ed. When t he sum is gr eat er t han 9, t he binar y sum is diffr ent fr om
BCD sum, means cor r ect ion is r equir ed. Ther efor e, a BCD adder must include t he cor r ect ion
logic in it s int er nal const r uct ion. Mor eover, t he cir cuit is r equir ed t o develop a logic in it s
int er nal const r uct ion t hat indicat es for needed cor r ect ion.
This lat er logic can be developed by obser ving t he t wo t able ent r ies. Fr om t ables it is
clear t hat t he cor r ect ion is r equir ed when K = 1 or Z
8
Z
4
= 1 or Z
8
Z
2
= 1.
or when k = 1 or Z
8
(Z
4
+ Z
2
) = 1.
K = 1, means t he r esult is 16 or above,
Z
8
Z
4
=1, means t he r esult is 12 or above and
Z
8
Z
2
= 1, means t he r esult is 10 or above.
Ther efor e, t he condit ion for cor r ect ion can be wr it t en as :
C = K + Z
8
(Z
4
+ Z
2
)
i.e., whenever C = 1, we need correct ion ⇒ Add binar y 0110 (decimal 6) t o t he sum
pr oduced by 4 bit binar y adder. It also pr oduce an out put car r y for t he next st age. The BCD
adder can be implement ed using t wo 4-bit binar y par allel adder s as shown in Fig. 4.46.
B
8
B
4
B
2
B
1
A
8
A
4
A
2
A
1
Z
8
Z
4
Z
2
Z
1
Carry
out
Addend
BCD digit
Augend BCD
digit
K C
i n
4-bit Binary Adder-1
B
8
B
4
B
2
B
1
A
8
A
4
A
2
A
1
Carry
In
C
i n
4-bit Binary Adder-2
S
8
S
4
S
2
S
1
Logic O
Output
Carry (C )
out
Carry
In
(Correction-Logic)
C
0 1 1 0
Fig. 4.46 BCD Adder using t wo 4-bit binar y adder s along wit h t he cor r ect ion logic C.
Combinational Logic 177
Here A
8
A
4
A
2
A
1
and B
8
B
4
B
2
B
1
ar e t he BCD input s. The t wo BCD input s wit h input
car r y Cin ar e fir st added in t he 4-bit binar y adder -1 t o pr oduce t he binar y sum Z
8
, Z
4
, Z
2
, Z
1
and out put car r y K. The out put s of adder -1 ar e checked t o ascer t ain wheat her t he out put is
gr eat er t han 9 by AND-OR logic cir cuit r y. If cor r ect ion is r equir ed, t hen a 0110 is added wit h
t he out put of adder -1. Now t he 4-bit binar y adder -2 for ms t he BCD r esult (S
8
S
4
S
2
S
1
) wit h
car r y out C. The out put car r y gener at ed fr om binar y adder -2 can be ignor ed, since it supplies
infor mat ion alr eady available at out put car r y t er minal C.
4.2.6. M a g nitud e C omp a ra tor
A magnit ude compar at or is a combinat ional cir cuit designed pr imar ily t o compar e t he
r elat ive magnit ude of t he t wo binar y number s A and B. Nat ur ally, t he r esult of t his compar i-
son is specified by t hr ee binar y var iables t hat indicat e, wheather A > B, A = B or A < B.
The block diagr am of a single bit magnit ude compar at or is shown in Fig. 4.47.
Single-bit
magnitude
comparated
A > B
A = B
A < B
A
B
Outputs Inputs
Fig. 4.47 Block diagr am of single bit magnit ude compar at or.
To implement t he magnit ude compar at or t he pr oper t ies of Ex-NOR gat e and AND gat e
is used.
Fig. 4.48(a) shows an EX-NOR gat e wit h t wo input s A and B. If A = B t hen t he out put
of Ex-NOR gat e is equal t o 1 ot her wise 0.
A
B
=
1 if a = B and
0 if A B ≠
Fig. 4.48 (a)
Fig. 4.48 (b) and (c) shows AND gat es, one wit h A and B' as input s and anot her wit h A'
and B as t heir input s.
A
B′
= 1 if A > B
A′
B
= 1 if A < B
Fig. 48 (b) Fig. 4.48 (c)
The AND gat e out put of 4.48(b) is 1 if A > B (i.e. A = 1 and B = 0) and 0 if A < B (i.e.
A = 0 and B = 1). Similar ly t he AND gat e out put of 4.48(c) is 1 if A < B (i.e. A = 0 and B =
1) and O if A > B (i.e. A = 1 and B = 0).
If t he EX-NOR gat e and t wo AND gat es ar e combined as shown in Fig. 4.49(a), t he cir cuit
wit h funct ion as single bit magnit ude compar at or. For EX-NOR implement at ion.
A
B
Y A > B
1

Y A = B
2

Y A < B
2

Fig. 4.49 (a) Single bit magnit ude compar at or.
178 S witching Theory
We have used EX-OR followed by an inver t er.
Tr ut h t able of a single bit magnit ude compar at or.
Inputs Output
A B Y
1
Y
2
Y
3
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
It clear ly shows Y
1
is high when A > B.
Y
2
is high when A = B
Y
3
is high when A < B.
The same pr inciple can be ext ended t o an n-bit magnit ude compar at or.
4- b it M a g nitud e C omp a ra tor
Consider t wo numbers A and B, wit h four digit s each.
A = A
3
A
2
A
1
A
0
B = B
3
B
2
B
1
B
0
.
(a) The t wo number s ar e equal if all pair s of significant digit s ar e equal i.e. if A
3
= B
3
,
A
2
= B
2
, A
1
= B and A
0
= B
0
. We have seen t hat equalit y r elat ion is gener aed by
EX-NOR gat e. Thus
x
i
= A
i
. B
i
= A
i
B
i
+ A
i
' B
i
' , i = 0, 1, 2, 3.
Where x
i
r epr esent s t he equalit y of t wo number s
x
i
= 1, if A = B.
x
i
= 0, ot her wise.
If follows an AND oper at ion of all var iables.
⇒ (A = B) = x
3
x
2
x
1
x
0
= 1 only if all pair s ar e equal.
(b) To det ermine if A > B or A < B, we check t he r elat ive megnit ude of pair s of
significant digit s st ar t ing fr om MSB. If t he t wo digit s ar e equal, we compar e t he
next lower significant pair of digit s. The compar ison follows unt il a pair of unequal
digit s ar e r eached. If t he cor r esponding digit of A is 1 and t hat of B is 0, we say
that A > B. If t he corresponding digit A is 0 and t hat of B is 1 ⇒ A < B.
This discussion can be expr essed logically as :
(A > B) = A
3
B
3
' + x
3
A
2
B
2
' + x
3
x
2
A
1
B
1
' + x
3
x
2
x
1
A
0
B
0
'
(A < B) = A
3
' B
3
+ x
3
A
2
' B
2
+ x
3
x
2
A
1
' B
1
+ x
3
x
2
x
1
Ao' Bo.
The logical implement at ion is shown in Fig. 4.49(b)
Combinational Logic 179
A
3
B′
3
A
2
B′
2
A
1
B′
1
A
0
B′
0
A > B
A
3
B
3
x
3
A
2
B
2
x
2
A
1
B
1
x
1
A
1
B
1
x
0
A = B
A
3

B
3
A
2

B
2
A
1

B
1
A
0

B
0
A < B
Fig. 4.49(b) Logical implement at ion of or 4-bit magnit ude compar at or.
4.3 HAZARDS
In digit al cir cuit s it is impor t ant t hat undesir able glit ches (spikes) on signal should not
occur e. Ther efor e in cir cuit design one must be awar e of t he possible sour ces of glit ches
(spikes) and ensur e t hat t he t r ansit ions in a cir cuit will be glit ch fr ee. The glit ches (spikes)
caused by t he st r uct ur e of a given cir cuit and pr opagat ion delays in t he cir cuit ar e r efer r ed
to as hazards. Hazar ds occur in combinat ional cir cuit s, wher e t hey may cause a t empor ar y
false-out put value.
4.3.1 Ha za rd s in C omb ina tiona l C irc uits
Hazards is unwanted swit ching t r ansient s appear ing in t he out put while t he input t o
a combinat ional cir cuit (net wor k) changes. The r eason of hazar d is t hat t he differ ent pat hs
fr om input t o out put have differ ent pr opagat ion delays, since t her e is a finit e pr opagat ion
delay t hr ough all gat es. Fig. 4.50 depict s t he pr opagat ion delay in NOT gat e.
In t he cir cuit analysis, dynamic behaviour is an impor t ant consider at ion. The pr opaga-
t ion delay of cir cuit var ies and depends upon t wo fact or s.
• Pat h of change t hr ough cir cuit .
• Dir ect ion of change wit hin gat es.
180 S witching Theory
Input Output
Input
Output
Time
Propagation delay
Fig. 4.50
The glit ches (spikes) ar e moment ar y change in out put signal and ar e pr oper t y of cir cuit ,
not funct ion as depict ed in Fig. 4.51.
1
0
1
0
1
0
1
1 1
0
Fig. 4.51
Hazar ds/Glit ches (spikes) ar e danger ous if
• Out put sampled befor e signal st abilizes
• Out put feeds asynchr onous input (immediat e r esponse)
The usual solut ions ar e :
• Use synchr onous cir cuit s wit h clocks of sufficient lengt h
• Minimize use of cir cuit s wit h asynchr onous input s
• Design hazar d fr ee cir cuit s.
Example. S how that the combinational circuit
Q AB BD = +
having hazards.
Solution. For Q AB BD = + ; if B and D are 1 t hen Q should be 1 but because of propa-
gat ion delays, if B changes st age t hen Q will become unst able for a short t ime, as follows :
Q
(C)
A
B
D
A
D
B
(C)
Q
High
High
Glitch
Fig. 4.52 Ther efor e t he given combinat ional cir cuit having hazar ds.
Combinational Logic 181
4.3.2 Type s of Ha za rds
Two t ypes of hazar ds ar e illust r at ed in Fig. 4.53.
• St at ic hazar d
• Dynamic hazar d.
1. Sta tic 1 ( 0) ha za rd
A st at ic hazar d exist s if, in r esponse t o an out put
change and for some combinat ion of pr opagat ion de-
lays, a net wor k out put may moment ar ily go t o 0 (1)
when it should r emain a const ant 1 (0), we say t he
net wor k has a st at ic 1 (0) hazar d. Example of st at ic
hazar d is shown in Fig. 4.54 (a).
Example.
A
S
B
S′
F
Static-0 hazard Static-1 hazard
A
B
S
S′
F
Hazard
Fig. 4.54 (a)
2. Dyna mic Ha za rd
A differ ent t ype of hazar d may occur if,
when t he out put is suppose t o change fr om 0
t o 1 (or 1 t o 0), t he out put may change t hr ee
or mor e t imes, we say t he net wor k has a dy-
namic hazar d. Example of dynamic hazar d is
shown in Fig. 4.54 (b).
Example:
A
C
B1
Hazard
A
B
C
3
1
2
dynamic hazards
B2
B3
F
Fig. 4.54 (b)
0 0
1
Static 0-hazard
0
1
Static 1-hazard
1
Fig. 4.53
0 0
1
Dynamic hazard
1
0 0
1 1
Fig. 4.54 (b)
182 S witching Theory
4.3.3 Ha za rd Fre e Re a liza tions
The occur r ence of t he hazar d can be de-
t ect ed by inspect ing t he Kar naugh Map of t he
r equir ed funct ion. Hazar ds like example (Fig.
4.52) ar e best eliminat ed logically. The Fig. 4.52
is r edr awn her e (Fig. 4.55).
Q AB BD = +
The Kar naugh Map of t he r equir ed funct ion is given in Fig. 4.56.
00 01 11 10
AB
D
0
1
0
0
0 0 1
1 1 1
BD
AB
Fig. 4.56 K-Map of t he given cir cuit .
Whenever t he cir cuit move fr om one pr oduct t er m t o anot her t her e is a possibilit y of
moment ar y int er val when neit her t er m is equal t o 1, giving r ise t o an undesir able out put .
The r emedy for eliminat ing hazar d is t o enclose t he t wo mint er ms wit h anot her pr oduct t er m
t hat over laps bot h gr oupings.
The cover ing t he hazar d causing t he t r ansit ion wit h a r edundant pr oduct t er m (AD) will
eliminat e t he hazar d. The K-Map of t he hazar d-fr ee cir cuit will be as shown in Fig. 4.57.
00 01 11 10
AB
D
0
1
0
0
0 0 1
1 1 1
BD
AB
AD
Fi g. 4.57 K-Map of t he hazar d-fr ee cir cuit .
Ther efor e t he hazar d fr ee Boolean equat ion is
Q AB BD AD = + +
.
The Fig. 4.58 shows t he hazar d fr ee r ealizat ion of cir cuit shown in Fig. 4.55.
Q
A
B
D
Fig. 4.58 Hazar d fr ee cir cuit .
Now we will discuss eliminat ion of st at ic hazar ds wit h examples.
Elimina ting a sta tic - 1 ha za rd
Let t he example circuit is
F AC AD = +
. The K-map of t he cir cuit is given in Fig. 4.59.
Q
A
B
D
(C)
Fig. 4.55
Combinational Logic 183
00 01 11 10
AB
CD
00
01
0
1
0 1 1
1 1 1
11 1 1 0 0
10 0 0 0 0
A
C
D
B
Fig. 4.59 K-Map of t he example cir cuit .
By inspect ing Kar naugh Map of t he r equir ed funct ion, we not ice t he following point s.
• Input change wit hin pr oduct t er m (ABCD = 1100 t o 1101)
g1
g2
g3
1
1
0
0
A
C
A
D
1 F
1
0
1
• Input change t hat spans pr oduct t er ms (ABCD = 1101 t o 0101)
g1
g2
g3
10000
11111
00111
11111
A
C
A
D
11101 F
11000
00011
Values sampled
on a gate delay interval
• Glit ch only possible when move bet ween pr oduct t er ms.
00 01 11 10
AB
CD
00
01
0
1
0 1 1
1 1 1
11 1 1 0 0
10 0 0 0 0
A
C
D
B
Fr om above t hr ee point s it is clear t hat addit ion of r edundant pr ime implicant s so t hat
all movement s bet ween adjacent on-squar es r emains in a pr ime implicant will r emove
hazar d.
184 S witching Theory
00 01 11 10
AB
CD
00
01
0
1
0 1 1
1 1 1
11 1 1 0 0
10 0 0 0 0
A
C
D
B
Fig. 4.60 K-Map of t he hazar ds fr ee cir cuit .
Therefore
F AC AD = +
becomes
F AC AD CD = + +
.
Note that when a circuit is implemented in sum of products with AND-OR gates or with
NAND gates, the removal of static-1 hazard guarantees that no static-0 hazars or dynamic
hazards will occur.
Elimina ting a sta tic - 0 ha za rd
Let t he example cir cuit is
F (A C)(A D). = + +
The K-Map of t he cir cuit is given in Fig. 4.61.
00 01 11 10
AB
CD
00
01
0
1
0 1 1
1 1 1
11 1 1 0 0
10 0 0 0 0
A
C
D
B
Fig. 4.61 K-Map of t he example cir cuit .
By inspect ing Kar naugh Map of t he r equir ed funct ion, we see t hat occur r ence of st at ic-
0 hazard from ABCD = 1 10 t o 0110. It can be r emove by adding t he t er m
(C D). +
4.3.4 Esse ntia l Ha za rd
Similar t o st at ic and dynamic hazar ds in combinat ional cir cuit s, essent ial hazar ds occur
in sequent ial cir cuit s. Essent ial hazar ds is a t ype of hazar d t hat exist s only in asynchr onous
sequent ial cir cuit s wit h t wo or mor e feedbacks. Essent ial hazar d occur s nor mally in t oggling
t ype cir cuit s. It is an er r or gener ally caused by an excessive delay t o a feedback var iable in
r esponse t o an input change, leading t o a t r ansit ion t o an impr oper st at e. For example, an
excessive delay t hr ough an inver t er cir cuit in compar ison t o t he delay associat ed wit h t he
feedback pat h may cause essent ial hazar d. Such hazar ds cannot be eliminat ed by adding
r educant gat es as in st at ic hazar ds. To avoid essent ial hazar d, each feedback loop must be
designed wit h ext r a car e t o ensur e t hat t he delay in t he feedback pat h is long enough
compar ed t o t he delay of ot her signals t hat or iginat e fr om t he input t er minals.
Combinational Logic 185
4.3.5 Sig nific a nc e of Ha za rd s
A glit ch in an asynchr onous sequent ial cir cuit can cause t he cir cuit t o ent er an incor r ect
st able st at e. Ther efor e, t he cir cuit y t hat gener at es t he next -st at e var iables must be hazar d
fr ee. It is sufficient t o eliminat e hazar ds due t o changes in t he value of a single var iable
because t he basic pr emise in an asynchr onous sequent ial cir cuit is t hat t he values of bot h t he
pr imar y input s and t he st at e var iables must change one at a t ime.
In synchr onous sequent ial cir cuit s t he input signal must be st able wit hin t he set up and
hold t imes of flip-flops. It does not mat t er whet her glit ches (spikes) occur out side t he set up
and hold t imes wit h r espect t o t he clock signal.
In combinat ional cir cuit s, t her e is no effect of hazar ds, because t he out put of a cir cuit
depends solely on t he values of t he input s.
4.4 FAULT DETECTION AND LOCATION
Digit al syst em may sulffer t wo classes of fault s : t empor ar y fault s, which occur due t o
noise and t he non-ideal t r ansient behaviour of swit ching component s and second is per manent
fault s. which r esult fr om component failur es. The t r ansient behaviour of swit ching is st udied
in hazar ds. while per manent fault s t est ing and diagnosis consist s of t he following t wo
subpr oblems.
1. The fault det ect ion pr oblem.
2. The fault -locat ion pr oblem.
The ar e var ious met hods ar e used for t he fault det ect ion and locat ion t hese ar e :
1. Classical met hod.
2. Fault t able met hod.
3. Boolean differ ences met hod.
4. Pat h sensit izing met hod.
4.4.1 C la ssic a l M e thod
The pr ocess of applying t est s and det er mining whet her a digit al cir cuit is fault fr ee or
not is gener ally known as fault det ect ion.
One way of det er mining whet her a combinat ional cir cuit oper at es pr oper ly is by applying
t o t he cir cuit all possible input combinat ions and compar ing t he r esult ant out put s wit h eit her
t he cor r esponding t r ut h t able or a fault less ver sion of t he same cir cuit . Any diviat ion indicat es
t he pr esence of some fault . If a known r elat ionship exist s bet ween t he var ious possible fault s
and t he deviat ions of out put pat t er n t hen we can easily diagnose t he fault and classify it
wit hin a subset of fault s whose effect s on t he cir cuit out put ar e ident ical.
This classical met hod is gener ally ver y long, and consequent ly impr act ical. Mor eover, for
most cir cuit s t he fault can be det ect or even, t o locat e t hem by consider ably shor t er t est s,
wher eas by classical met hod t her e ar e lar ge number of t est have t o be done which ar e
unnecessar y. Such t est s ar e r efer r ed t o as eit her Fault det ect ion or Fault -locat ion t est s.
These t est ar e used for det ect ing t he pr esence of a fault , locat e t hem and diagnose it .
Assump tions a b out the typ e of d ig ita l c irc uit to b e c onsid e re d
1. It is assumed t hat t he digit al cir cuit s under st udy ar e combinat ional cir cuit s, t est -
ing pr ocedur es ar e developed for cir cuit s composed of loop-fr ee int er connect ion of
186 S witching Theory
AND, OR NOT, NAND, and NOR gat es ; t hat is feedback loops ar e not allowed in
t he cir cuit s being t est ed.
2. It is assumed t hat t he r esponse delays of all t he gat es element ar e t he same.
3. Since single fault will be det ect ed in all cases, while mult iple fault may not be
det ect ed in digit al cir cuit so it is assumed t hat most cir cuit s ar e r eliable enough so
t hat t he pr obabilit y of occur r ence of mult iple fault s in r at her small.
Assump tion a b out typ e of Fa ult to b e c onsid e re d
1. The fault s consider ed her e ar e assumed t o be fixed or per manent or non t r ansient
fault s by which mean t hat wit hout having t hem r epair ed, t he fault will be per ma-
nent ly t her e.
2. Most of t he fault s occur r ed in cur r ent ly used cir cuit s such as RTL, DTL, TTL, ar e
t hose which cause a wir e t o be (or appear logically t o be) st uck at zer o or st uck-
at -one (abbr eviat ed s-a-o and s-a-1). Rest r ict ing our consider at ion t o just t his class
of fault s is t echnically just ified, since most cir cuit failur es fall in t his class, and
many ot her failur es exhibit sympt omat ically ident ical effect .
3. A mult iple fault is defined as t he simult aneous occur r ence of any possible combi-
nat ion of s-a-o and s-a-1 fault s.
4.4.2 The Fa ult Ta b le M e thod
The most classic met hod for const r uct ing a set of t est s t o det ect and locat e a pr escr ibed
list of per manent logic fault s, single or mult iple, in a combinat ional cir cuit is t he fault t able
met hod.
“A Fault t able is a t able in which t here is a row for every possible t est (i.e. input combi-
nat ion) and a column for every fault . A 1 is ent ered at t he int ersect ion of t he ‘it h’ row and t he
‘j
th
’ column if t he fault corresponding t o t he ‘jt h’ column can be det ect ed by t he it h t est .”
Befor e st ar t ing wit h fault t able met hod we should know det ect able and undet ect able
fault s and a minimal complet e t est set of cir cuit .
A Fault of a combinat ional cir cuit is said t o be det ect able if t her e exist s a t est by which
we can judge whet her or not t he cir cuit has such a fault , ot her wise, we call t he fault
undet ect able.
A t est set of a cir cuit is said t o be complet e if it det ect s ever y fault of cir cuit under
consider at ion. A minimal complet e t est set of cir cuit is complet e t est set t hat cont ains a
minimum number of t est s. Let on consider ‘n’ input s t o t he cir cuit , t hen t her e ar e 2
n
number
of r ows. Thus a subset of 2
n
r ows const it ut e a complet e t est set for t he cir cuit .
The Fa ult ta b le
Let x
1
, x
2
......x
n
be input s t o a combinat ional cir cuit and let ‘f’ be it s fault fr ee out put .
Let ‘f’ be it s fault fr ee out put . Let f
α
denot e t he out put of t he cir cuit in t he pr esence of fault
α. consider an example, t he cir cuit shown belows in Fig. 4.62.
A
B
m
n 1
p
q
f = AB + C′
C′
2
Fig. 4.62 Cir cuit under t est .
Combinational Logic 187
C irc uit to b e te ste d
Suppose t hat any one of it s wir es m, n, p, and q may have s-a-o or s-a-1 Fault . We shall
denot e s-a-0 and s-a-1 fault s for wire ‘m’ as m
0
and m
1
r espect ively. Similar not at ion is used
for t he ot her wir es. The t r ut h t able for t his cir cuit is shown below, where column f denot es
t he fault -fr ee out put for example, columns fm
0
and fm
1
denot es t he cir cuit out put s in t he
presence of fault s m
0
and m
1
on wire m, and so on.
Inputs f = (mn + q) Outputs in presence of Faults
ABC = (p +q) fm
0
fn
0
fp
0
fq
0
fm
1
fn
1
fp
1
fq
1
= AB + C
1
(m = 0) (n = 0) (p = 0) (q = 0) (m = 1) (n = 1) (p = 0) (q = 1)
0 0 0 1 1 1 1 0 1 1 1 1
0 0 1 0 0 0 0 0 0 0 1 1
0 1 0 1 1 1 1 0 1 1 1 1
0 1 1 0 0 0 0 0 1 0 1 1
1 0 0 1 1 1 1 0 1 1 1 1
1 0 1 0 0 0 0 0 0 1 1 1
1 1 0 1 1 1 1 1 1 1 1 1
1 1 1 1 0 0 0 1 1 1 1 1
(Tr ut h t able for t he fault -fr ee out put and out put in pr esences of fault s)
An input combinat ion is r efer r ed t o as a t est for fault f
α
if, in r esponse t o t hat input
combinat ion, t he out put of t he correct ly operat ing circuit is different from t hat of t he circuit
impaired by fault ‘f
α
’. If we have observed t he ‘fm
0
’ column, t here is only one fault for input
combination 1 1 1, for ot her input combinat ion t here is no fault since f = fm
0
(for input
combinat ion 0 0 0, 0 0 1..... 1 1 0) where as for input combinat ion 1 1 1, f

fm
0
. On t he ot her
hand, Fault f
q1
can be det ect ed by t he t est s 0 0 1, 0 1 1, and 1 0 1, and so on, for ot her fault s.
More precisely, an input combinat ion a
1
, a
2
...., a
n
is a t est for det ect ing fault f
α
if and only if.
f a a a f a a a
n n
( , ..., ) ( , ... )
1 2 1 2
1 ⊕ =
α
where f (a
1
, a
2,
.....a
n
) and f a a a
n α
( , ... )
1 2
denot e, r espect ively, t he fault -fr ee out put and t he
incorrect out put in response t o t he input a
1
, a
2
....a
n
.
Fr om t he fault t able, it is clear t hat column (m
1
, m
0
) and (p
1
, q
1
) ar e ident ical.
Since t hese four gr oups ar e ident ical. Thus t hese Fault s ar e indist inguishable fault s of
t he fault t able. we combine t hem, choosing one funct ion fr om each gr oup, and delet e r est of
t hem, In t his way we can get fault t able fr om t r ut h t able as:
Fault table for mi ni mal set of fault detecti on test
Inputs Possible Faults
ABC {m
0
, n
0
, p
0
} q
0
m
1
n
1
{p
1
, q
1
}
(f ⊕ f
1
) (f ⊕ f
2
) (f ⊕ f
3
) (f ⊕ f
4
) (f ⊕ f
5
)
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1 1
(Contd.)
188 S witching Theory
1 0 0 1
1 0 1 1 1
1 1 0
1 1 1 1
(where f
1
= f
m0
= f
n0
= f
p0
, f
2
= f
q0
, f
3
= f
m1
, f
q
= f
n1
and f
5
= f
p1
= f
q1
and f is fault fr ee out put
of t he cir cuit ).
Eq uiva le nt Fa ults
As we have seen t hat columns f
m0
, f
n0
, and f
p0
ar e ident ical, and so ar e columns f
p1
, and
f
q1
. In ot her wor ds, t he cir cuit out put in t he pr esence of fault f
p1
is ident ical wit h t he out put
in t he pr esence of f
q1
. Hence is no input combinat ion which can dist inguish fault f
p1
from f
q1
.
Such fault s ar e called equivalent faults. Equivalent fault s ar e indist inguishable wher eas fault s
t hat ar e not equivalent ar e said t o t he dist inguishable fault s. The pr oblem of finding a
minimal set of t est s is now r educed t o t he pr oblem of finding a minimal set of r ows so t hat
ever y columns has a 1 ent r y in a least one r ow of t he set . Such a set of r ows will be said
to cover the fault table.
C ove ring the fa ult ta b le for d e te rmina tion of a minima l se t of fa ult d e te c tion
The minimal t est set found fr om t he fault t able wit h t he help of following t wo r ules:
1. Delet e any r ow t hat is cover ed by, or is same as, some ot her r ow.
2. Delet e any column t hat cover s, or is same as, some ot her column.
We can easily ver ify t hat r ows 010 and 100 can be r emoved because t hey ar e equivalent
t o 000 similar ly r ow 001 can be r emoved since it is dominat ed by r ow 101. Also r ow 110 does
not det ect any fault and can be r emoved fr om t he t able.
Fr om t he fault t able. It is seen t hat t est 011, 101 and 111 cover s column (m
0
, n
0
, p
0
),
m
1
, n
1
, (p
1
, q
1
) except q
0
are essential test. The essent ial t est ar e det er mined by obser ving
which fault s can be det ect ed by just a single t est . A four t h t est 000 det ect s q
0
and t hus
complet es t he set of t est s t hat det ect all single fault s in t he cir cuit being t est ed.
It is convenient t o dist inguish bet ween a fault -det ect ion t est , which r efer s t o a single
applicat ion of values t o t he input t er minals, and a fault -det ect ion exper iment , which r efer s
t o a set of t est s leading t o a definit e conclusion as t o whet her or not t he cir cuit oper at es
cor r ect ly for all input combinat ion. In above example t he exper iment consist s of four t est as
follows (t hr ough not necessar ily in t his or der ):
1. Apply 011: if t he out put is T = 1, cir cuit fault y and t he exper iment may be st opped;
it T = 0, apply second t est .
2. Apply 101: if T = 1, cir cuit fault y; ot her wise, apply next t est .
3. Apply 111: it T = 0, cir cuit is fault y; ot her wise, apply next t est .
4. Apply 000: if T = 0, cir cuit is fault y, if T = 1, cir cuit oper at es cor r ect ly.
The fault t able pr ovides a t ool for t he det er minat ion of a minimal set of fault det ect ion
t est for combinat ional logic cir cuit s. But for lar ger cir cuit s t his met hod become cumber some
due t o lar ge size of fault t able, comput at ion t ime and memor y r equir ement s.
For last example t he fault det ect ion t able becomes in r educed for m as:
Combinational Logic 189
Faults
Test {m
0
, n
0
, p
0
} q
0
m
1
n
1
{p
1
, q
1
}
0 0 0 1
0 1 1 1 1
1 0 1 1
1 1 1 1
Thus t he minimal complet e t est get for det ect ions of all single fault s of t his cir cuit is {0,
3, 5, 7}.
4.4.3 Fa ult d e te c tion b y Pa th Se nsitizing
Her e we shall show t hat a fault -det ect ion t est may be found by examining t he pat hs of
t r ansmission fr om t he locat ion of an assumed fault t o one of it s pr imar y out put .
⇒ In a logic circuit , a primary output is a line whose signal out put is accessible t o t he
ext er ior of t he cir cuit , and pr imar y input is a line t hat is not fed by any ot her line in t he
cir cuit .
⇒ A t r ansmission pat h, or simply pat h of a combinat ional cir cuit , is a connect ed dir ect ed
gr aph cont aining no loops fr om a pr imar y input t o one of it s pr imar y out put .
Path Sensi ti zi ng: A pat h is said t o be sensitized if t he input t o t he gat es along t his pat h
ar e assigned value so as t o pr opagat e any change on t he fault y line along t he chosen pat h
t o t he out put t er minal of t he pat h.
The main idea behind t he pat h-sensit izing pr ocedur e will be illust r at ed by a cir cuit which
det ect s a s-a-1 fault at it s one input as shown in Fig. 4.63.
A 0 1 →
1
1
n
m 1 0 →
0 – 1
p
1 0 →
q
0 1 →
Circuit
input
Circuit
output
Fig. 4.63 A cir cuit descr ibing a sensit ized pat h.
In t his cir cuit it is assume t hat t his pat h is t he only fr om A t o t he cir cuit out put and
a t est is done which det ect a s-a-1 fault at input A. In or der t o t est a s-a-1 fault at input A,
if is necessar y t o apply a 0 t o A and 1’s t o all r emaining input s t o t he AND and NAND gat es,
and 0’s t o all r emaining input s t o t he OR and NOR gat es in t he pat h. This ensur e t hat all
t he gat es will allow t he pr opagat ion of t he signal fr om A t o t he cir cuit out put and t hat only
t his signal will r each t he cir cuit out put . The pat h is now said t o be sensit ized.
In Fig. 4.63 if input A is s-a-1, t hen m changes fr om 1 t o 0, and t his changes pr opagat es
t hrough connect ions n and p and causes q t o change fr om 0 t o 1. Clear ly, it det ect s a s-a-1
fault at A also it det ect s s-a-0 fault s at m, n and p and s-a-1 fault at q. A s-a-0 fault at A is
det ect ed in similar manner. So s-a-0 and s-a-1 fault s can be det ect ed in t his pat h.
The basic pr inciples of t he pat h-sensit izat ion met hod, which is also known as t he one-
dimensional pat h sensit izat ion, can t hus be summar ized as follows:
(1) At t he sit e of t he fa ult a ssign a logica l va lue complement a r y t o t he fa ult being
t est ed, i.e., t o t est x
i
for s-a-1 assign x
i
= 1 a nd t o t est it for s-a-1 a ssign
x
i
= 0.
Essent ial
t est
R
S
|
T
|
190 S witching Theory
(2) Select a pat h fr om t he fault y line t o one of it s pr imar y out put . The pat h is said t o
be sensit ized if t he input s t o t he gat es along t he pat h ar e assigned values so as t o
pr opagat es t o t he pat h out put any fault s on t he wir es along t he pat h. The pr ocess
is called t he for war d dr ive phase of t he met hod.
(3) Along t he chooses pat h, except t he lines of t he pat h, assign a value “0” t o each input
of t he OR and NOR gat es in t he pat h and a value 1’s t o each input t o t he NAND
and AND gat es in t he pat h.
(4) To det er mine t he pr imar y input s t hat will pr oduce all t he necessar y signals values
specified in t he pr eceding st eps. This is accomplished by t r acing t he signals back-
war d fr om each of t he gat es along t he pat h t o t he pr imar y input s or cir cuit input s.
This pr ocess is called t he backwar d-t r ace phase of t he met hod. If on t he ot her hand,
a cont r adict ion is encount er ed, choose anot her pat h which st ar t s at fault y line and
r epeat t he above pr ocedur e.
(5) Apply st eps 1-4 t o all t he single pat hs. If none of t hem is sensit izable, apply t he
pr ocedur e t o all possible gr oups of t hr ee pat h, and so on.
These all pr ocedur e st eps can be under st ood easily by an example
Example. Der ive a t est for a s-a-1 fault on wir e h of Fig. 4.64 given below:
Sensitized
path
f
1
f
2
G
14
G
13
G
11
G
9
G
10
G
8
G
7
h
s-a-1
G
6
x
1
x
2
x
3
x
4
x
5
Fig. 4.64
The for war d der ive st ar t s by assigning a 0 t o h, and select ing a pat h t o be sensit ized.
We choose t o sensit ize t he pat h G
7
G
9
G
11
G
13
t o out put f
1
. Clear ly G
9
and G
13
are AND gat es
so t hat t heir ot her input s must be 1, while second input t o t he OR gat es G
11
must be 0. This
complet es t he for war d-der ive phase and pat h is next sensit ized. Next , we must det er mine t he
pr imar y input s which must pr ovide t he r equir ed logical value t o t he gat es along t he pat h.
This is accomplished by t r acing back fr om each gat e input t o t he cor r esponding pr imar y
input s. In t his example, it is quit e st r aight for war d t hat
x
5
= 1
x
4
= 1
x
3
= 0
and G
6
= 1
We get G
6
= 1 we may set -1 any one or bot h input s t o G
6
Suppose x
1
= 1
x
2
= 0
t hen set X = {1, 0, 0, 1, 1}
Combinational Logic 191
If, in r esponse t o t hese input s cir cuit pr oduces t he out put f
1
= 0; t hen fault in quest ion
does not exist .
If, on t he ot her hand, f
1
= 1, t he cir cuit has a fault .
Thus an er r oneous out put s implies t hat some fault exist along t he sensit ized pat h.
Limita tions of the me thod
Now suppose t hat we obser ve t he cir cuit r esponse t o t he above set at out put f
2
.
An analysis shows t hat t he input vect or X = {1, 0, 0, 1, 1} sensit izes t he t wo pat hs, t hese
ar e
G G G G
and
G G G G
7 9 11 14
7 10 12 14
U
V
|
W
|
which emanat e from h and t erminat e at f
2
.
It is easy, however, t o ver ify t hat t he fault h s-a-1 does not pr opagat e t o f
2
because t her e
ar e t wo sensit ized pat hs connect ing it t o t he cir cuit out put .
In fact f
2
= 1 via G
10
and G
12
when h = 0
and f
2
= 1 via G
9
and G
11
if h = 1
This does not imply t hat h cannot be t est ed via f
2
. It does imply, however, t hat , in or der
t o t est h for s-a-1 fault via f
2
, a t est must be found such t hat only one of t he t wo pat hs will
t he ot her pat h will not be sensit ized. One such t est t hat sensit izen only t he pat h G
7
G
10
G
12
G
14
is X {0, 0, 0, 0, 1}.
Ad va nta g e of the p a th- se nsitiza tion me thod
A major advant age of t he pat h sensit izat ion met hod is shown in Fig. 4.65:
A 0 1 →
1
1
n
m 1 0 →
1 0 →
p
1 0 → 0 1 →
0
0
1
1
Fig. 4.65 s-a-1 fault at A.
In many case a t est for a pr imar y input is also a t est for all t he wir es along t he sensit ized
pat h which connect s input s t o t he cir cuit out put . Consequent ly if we can select a set of t est
which sensit izes a set of pat h cont aining all connect ions in t he cir cuit , t hen it is sufficient t o
det ect just t hose fault s which appear on t he cir cuit input . In fanout fr ee cir cuit s in which each
gat e out put is connect ed t o just one gat e input , t her e is only one pat h fr om each cir cuit input
t o t he out put , and t hus t he set of pat hs or iginat ing at t he input s will indeed cont ain all
connect ions. In cir cuit s which cont ain r econver gent far out , t he pr oblem become mor e com-
plicat ed. In fact single-pat h-sensit izat ion met hod does not always gener at es a t est even if one
is known t o exist . So single pat h sensit izat ion met hod can det ect fault for a class of combi-
nat ional cir cuit s in which:
⇒ Each input is an independent input line t o t he cir cuit s.
⇒ The fanout of ever y gat e is ‘1’.
Now let s shows t hat single-pat h sensit izat ion met hod does not always gener at es a t est
even if one is known t o exist .
Consider t he fault h s-a-0 in t he cir cuit shown in Fig. 4.66.
192 S witching Theory
X
1
X
2
X
3
X
4
G
7
G
5
G
8
G
9
G
10
G
11
G
12
f
h
s-a-0
G
6
Fig. 4.66
We shall now show t hat it is impossible t o find a t est for t his fault by senset izing just
a single pat h. Let us choose t o sensit ize t he pat h G6 G
9
G
12
. This r equir es:
G
6
= 1, which implies x
2
= 0 and x
3
= 0.
G
10
= 0 r egar dless of whet her t her e is a fault or not , which implies x
4
= 1.
G
11
= 0 implies G
7
= 1 (since x
3
= 0), which in t urn implies x
4
= 0.
Evident ly, t o sat isfy bot h G
10
= 0 and G
11
= 0, we must set conflict ing r equir ement on
x
4
and t hus we have a cont r adict ion. By t he symmet r y of t he cir cuit it is obvious t hat an
at t empt t o sensit ize t he pat h t hr ough G
10
will also fail, and hence t he met hod of one dimen-
sional pat h sensit izing fails t o gener at es t he t est x = (0, 0, 0, 0) which man shown t o det ect
t his fault .
The one-dimensional pat h-sensit izing met hod failed in t his case because it allows t he
sensit izat ion of just a single pat h fr om t he sit e of t he fault . In fact , if we wer e allowed t o
sensit ize bot h pat hs, t hr ough G
9
and G
10
, simult aneously t he above t est would be gener at ed.
This development of t he t wo-dimensional pat h sensit izing which is also known as t he d-
algor it hm. The basic idea in t he d-algor it hm is t o sensit izes simult aneously all possible pat hs
fr om t he sit e of t he fault t o t he cir cuit out put s.
4.5 EXERC ISES
Problem 1: Develop a minimized Boolean implement at ion of a “ones count ” cir cuit t hat
wor ks as follows. The subsyst em has four binar y input s A, B, C, D and gener at es a 3-bit
out put , XYZ, XYZ is 000 if none of t he input s ar e 1, 001 if one input is 1,010 if t wo ar e one,
011 if t hr ee input s ar e 1, and 100 if all four input s ar e 1.
(a) Dr aw t he t r ut h t ables for XYZ (A, B, C, D).
(b) Minimize t he funct ions X, Y, Z, using 4-var iable K-maps. Wr it e down t he Boolean
expr essions for t he minimized Sum of Pr oduct s for m of each funct ion.
(c) Repeat t he minimizat ion pr ocess, t his t ime der iving Pr oduct of Sums for m.
Problem 2: Consider a combinat ional logic subsyst em t hat per for ms a t wo-bit addit ion
funct ion. It has t wo 2-bit input s A B and C D, and for ms t he 3-bit sum X Y Z.
(a) Dr aw t he t r ut h t ables for XYZ (A, B, C, D).
(b) Minimize t he funct ions using 4-var iable K-maps t o der ive minimized Sum of Pr od-
uct s for ms.
(c) What is t he r elat ive per for mance t o comput e t he r esult ing sum bit s of t he 2-bit
adder compar ed t o t wo full adder s connect ed t oget her ? (Hint : which has t he wor st
Combinational Logic 193
delay in t er ms of gat es t o pass t hr ough bet ween t he input s and t he final out put s,
and how many gat es is t his?).
Problem 3: Show how t o implement t he full adder Sum (A, B, C in) and Car r y (A, B,
C in) in t er ms of:
(a) Two 8 : 1 mult iplexer s;
(b) Two 4 : 1 mult iplexer s;
(c) If you ar e limit ed t o 2:1 mult iplexer s (and inver t er s) only, how would you use t hem
t o implement t he full adder and how many 2:1 mult iplexer s would you need?
Problem 4: Design a combinat ional logic subsyst em wit h t hr ee input s, 13, 12, 11, and
t wo out put s, 01, 01, t hat behaves as follows. The out put s indicat e t he highest index of t he
input s t hat is dr iven high. For example, if 13 is 0, 12 is 1, 11 is 1, t hen 01, 00 would be (10
(i.e. 12 is t he highest input set t o 1).
(a) Specify t he funct ion by filling out a complet e t r ut h t able.
(b) Develop t he minimized gat e-level implement at ion using t he K-map met hod.
(c) Develop an implement at ion using t wo 4 : 1 mult iplexer s.
(d) Compar e your implement at ion for (b) and (c). Which is bet t er and under what
cr it er ion?
Problem 5: Design a simple combinat ional subsyst em t o t he following specificat ion. t he
syst em has t he abilit y t o pass it s input s dir ect ly t o it s out put s when a cont r ol input , S, is not
asser t ed. It int er changes it s input s when t he cont r ol input s S is asser t ed. For example, given
four input s A, B, C, D and four out put s W, X, Y, Z when S = 0, WXYZ = ACD and when S
= 1, WXYZ = BCDA. Show how t o implement t his funct ionalit y using building blocks t hat ar e
r est r ict ed t o be 2 :1 mult iplexer s and 2 : 1 demult iplexer s.
Problem 6: Your t ask is t o design a combinat ional logic subsyst em t o decode a hexadeci-
mal digit in t he r ange of 0 t hr ough 9. A t hr ough F t o dr ive a seven segment display. The
hexadecimal numer als ar e as follows :
Design a minimized implement at ion in PLA for m. That is, look for common t er ms
among t he seven out put funct ions.
Problem 7: Det er mine number of days in a mont h (t o cont r ol wat ch display) used in
cont r olling t he display of a wr ist -wat ch LCD scr een.
Input s : mont h, leap your flag.
Out put s : number of days.
Problem 8: Consider t he following funct ions, which ar e five differ ent funct ions over t he
inputs A, B, C, D.
(1) F (A, B, C, ) = Σm (1, 2, 6, 7)
(2) F (A, B,C,D) = Σm (0, 1, 3, 9, 11, 12, 14, 15)
(3) F' (A, B, C, D) = Σm (2, 4, 5, 6, 7, 8, 10, 13)
(4) F (A, B, C, D) = (ABC + A'B') (C+D)
(5) F (A, B, C, D) = (A + B + C) (A + B + C' + D) (A + B' + C + D' ) (A' + B' )
194 S witching Theory
(a) Implement t hese in a single PLA st r uct ur e wit h four input s, five out put s, and an
unlimit ed number of pr oduct t er ms, how many unique pr oduct t er ms ar e t her e in
t his PLA implement at ion.
(b) If you ar e t r ying t o maximize t he number of shar ed pr oduct t er ms acr oss t he five
funct ions, r at her t han minimizing t he lit er al count for each funct ion independent ly,
how many unique t er ms do you obt ain? Dr aw t he new K-maps wit h your select ion
of implicant s t hat minimizes t he number of unique t er ms acr oss all five funct ions.
Problem 9: Consider t he following Boolean funct ion in Pr oduct of Sums for m :
F (A, B, C, D) = (A + B' + D) (A' + B' +D) (B' + C' + D') (A' + C + D) (A' + C' + D)
Show how t o implement t his funct ion wit h an 8 : 1 mult iplexer, with A, B, C on t he
cont r ol input s and D, it s complement , and t he const ant s 0 and 1 available as dat a input s.
Problem 10: Design a t wo-bit compar at or wit h t he following input s and out put s:
Input s : Number s N1 and N2 t o be compar ed
N1 = AB
N2 = CD.
Out put s : LT, GT, EQ
LT = 1 when AB < CD
GT = 1 when AB > CD
EQ = 1 when AB = CD
Problem 11: Design a 2X2 bit mult iplier :
Input s : Number s N1 and N2 t o be mult iplied
N1 = A1 A0
N2 = B1 B0
Out put s ; pr oduct s : P8, P4, P2, P0
P0 = Product wit h weight ing 2
0
= 1
P2 = Pr oduct wit h weight ing 2
1
= 2
P4 = Pr oduct wit h weight ing 2
2
= 4
P8 = Pr oduct wit h weight ing 2
3
= 8.
Problem 12: Analyse t he behaviour of t he Cir cuit below when Input A changes fr om one
logic st at e t o anot her.
A B C D
F
Problem 13: Analyse t he cir cuit below for st at ic hazar d.
A
S
B
S
Combinational Logic 195
Problem 14: Analyse t he pulse shaping cir cuit below :
A
C
B
D
Open
switch
+
Problem 15: Which of t he component s below cab be used t o build an inver t er ?
Problem 16: Consider t he Equat ion :
Z = A'B'C'D + A' B' CD' + A'BC' D' + A' BCD + ABC' D + ABCD' + AB'C'D' + AB' CD.
Implement t his using 2-1 mult iplexer s.
Problem 17: Use a 8-input mult iplexer t o gener at e t he funct ion
Y AB AD CD BC = + + +
Problem 18: Implement t he following funct ion wit h an mult iplexer.
y m = Σ ( , , , , , , ) 0 1 5 7 10 14 15
Problem 19: Given
Y m = Σ (1, 3, 5, 6)
Problem 20: Design a 32:1 mult iplexer using t wo 16:1 mult iplexer s.
Problem 21: Implement a 64 out put demult iplexer t r ee using 1 × 4 DEMUX.
Problem 22: Realize t he following funct ions of four var iables using
(i) 8 : 1 mult iplexer s (ii) 16 : 1 mult iplexer s.
Problem 23: Design a BCD-t o Gr ay code conver t er using
(i) 8:1 mut lplexer s (ii) dual 4 : 1 mult iplexer s and some gat es.
Problem 24: Design a Gr ay-t o-BCD code conver t er using
(i) t wo dual 4 : 1 mult iplexer s and some gat es.
(ii) one 1 : 16 demult iplexer and NAND gat es.
Problem 25: Design a 40:1 mult iplexer using 8 : 1 mult iplexer s.
Problem 26: Implement t he following combinat ional logic cir cuit using a 4 t o 16 line
decoder.
Y
1
= Σm (2, 3, 9)
Y
2
= Σm (10, 12, 13)
Y
3
= Σm (2, 4, 8)
Y
4
= Σm (1, 2, 4, 7, 10, 12)
196 S witching Theory
5
CHAPTER
5.0 INTRO DUC TIO N
Digit al cir cuit const r uct ion wit h small-scale int egr at ed (SSI) and medium-scale int egr at ed
(MSI) logic has long been a basis of int r oduct or y digit al logic design (r efer Chap. 3). In r ecent
t imes, designs using complex pr ogr ammable logic such as pr ogr ammable ar r ay logic (PLA)
chips and field pr ogr ammable gat e ar r ays (FPGAs) have begun r eplacing t hese digit al cir cuit s.
This chapt er deals wit h devices t hat can be pr ogr ammed t o r ealize specified logical
funct ions. Since evolut ion of pr ogr ammable logic devices (PLDs) st ar t ed wit h pr ogr ammable
ROM, it int r oduces ROMs and show how t hey can be used as a univer sal logic device and how
simple pr ogr ammable logic devices can be der ived fr om ROMs. It also gives an over view of
Complex Pr ogr ammable Logic Devices (CPLDs) and Field Pr ogr ammable Gat e Ar r ays (FPGAs).
5.1 READ O NLY M EM O RY ( ROM)
A Read Only Memor y (ROM) as shown in Fig. 5.1 is a mat r ix of dat a t hat is accessed one
r ow at a t ime. It consist s of k input lines and n out put lines. Each bit combinat ion of out put
lines is called a wor d while each bit combinat ion of input var iables is called an addr ess. The
number of bit s per wor d is equal t o t he number of out put lines n. A ROM is descr ibe by t he
number of wor ds 2
k
, t he number of bit s per wor d n.
The A input s ar e addr ess lines used t o select one r ow (called a wor d) of t he mat r ix for
access. If A = i, t hen row i is select ed and it s dat a appear s on t he out put t er minals D. In t his
case we say t hat t he cont ent s of row i ar e r ead fr om t he memor y.
ROM
A
0
A
1
A
k–1
D
n–1
D
1
D
0
Fi g. 5.1
If t her e ar e k addr ess lines, t hen t her e ar e 2
k
wor ds in t he ROM .The number of bit s
per wor d is called t he wor d size. The dat a values of t he wor ds ar e called t he cont ent s of
t he memor y and ar e said t o be st or ed in t he memor y. The t er m r ead only r efer s t o t he
pr oper t y t hat once dat a is st or ed in a ROM, eit her it cannot be changed, or it is not changed
ver y oft en.
196
PROGRAM M ABLE LOGIC DEVICES
Programmable Logic Devices 197
ROM can be viewed as a combinat ional cir cuit wit h AND gat es connect ed as a decoder
and number of OR gat es equal t o t he number of out put s. Int er nally a ROM cont ains a decoder
and a st or age ar r ay as shown in t he Fig. 5.2.
Decoder
A
0
A
1
A
k –1
m
0
m k
2 –1
D
n–1
D
1
D
0
m
1
0 0 1
1 1 0
0 1 1
Fi g. 5.2
When t he address is i, the it h out put of t he decoder m
i
is act ivat ed select ing r ow i of
t he dat a ar r ay. Funct ionally t he dat a ar r a y can be viewed as a pr ogr ammable OR ar r ay. Each
column act s as a st ack of OR gat es as shown in t he Fig. 5.3.
m
0
m
1
D
n–1
D
1
D
0
m k
2 –1
Fi g. 5.3
Depending on t he st or ed value (0/1)swit ch is open or closed. If a 0 is st or ed in a r ow, t he
swit ch is open and if a 1 is st or ed, t he swit ch is closed. The t ype of ROM is det er mined by
t he way t he swit ches ar e set or r eset (i.e., pr ogr ammed).
(I) Mask programmed ROMs: In t he mask pr ogr ammed ROMs, swit ch is r ealized at t he
t ime t he ROM is manufact ur ed. Eit her a connect ion is made by put t ing in a wir e, or t he
connect ion is left open by not put t ing in a wir e.
(II) Field programmable ROMs (PROMs): In t he field pr ogr ammable ROMs, swit ch is
r ealized by a fuse. When t he ROM is manufact ur ed all swit ches ar e closed since all t he fuses
ar e int act . To open a swit ch t he fuse is blown by sending a lar ger t han usual cur r ent t hr ough
it . Once a fuse is blown, it can not be r einst alled.
(III) Erasable ROMs (EPROMs): In t he er asable ROMs swit ch is r ealized by a special kind
of fuse t hat can be r est or ed t o it s usual closed st at e, usually by t he inser t ion of ext r a ener gy
(e.g., shining ult r aviolet light on t he fuse). All fuses ar e r eset when t his is done.
(IV) Electrically Programmable ROMs (EPROMs): In t he elect r ically pr ogr ammable ROMs
fuses ar e r eset by t he applicat ion of lar ger t han usual cur r ent s. Somet imes subsect ions of t he
ROM can be r eset wit hout r eset t ing all fuses.
198 S witching Theory
Consider a 32×8 ROM as shown in Fig. 5.4. The ROM consist s of 32 wor ds of bit size 8.
That is, t her e ar e 32 dist inct wor ds st or ed which may be available t hr ough eight out put lines.
The five input s ar e decoded int o 32 lines and each out put of t he decoder r epr esent s one of
t he mint er ms of a funct ion of five var iables. Each one of t he 32 addr esses select s only one
out put fr om t he decoder. The 32 out put s of t he decoder ar e connect ed t hr ough links t o each
OR gat e.
0
1
2
3
.
.
.
28
29
30
31
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
5 × 32
decoder
A
0
A
1
A
2
A
3
A
4
Fi g. 5.4
5.1.1 Re a lizing Log ic a l Func tions with RO M
The ROM is a t wo-level implement at ion in sum of mint er ms for m. ROMs wit h k addr ess
lines and n dat a t er minals can be used t o r ealize any n logical funct ions of k var iables. For
t his one have t o simply st or e t he t r ut h t able for each funct ion in a column of t he ROM dat a
ar r ay. The advant age of implement ing logical funct ions by means of some for m of pr ogr ammable
ROM, we have t he possibilit y of r econfigur able logic. That is, t he same har dwar e being
r epr ogr ammed t o r ealize differ ent logic at differ ent t imes. But t he disadvant age of using lar ge
ROMs t o r ealize logical funct ions is t hat , t he ROMs ar e much slower t han gat e r ealizat ions
of t he funct ions. The following example explains t he pr ocedur e for r ealizing logical funct ions.
Example. Design a combinat ional cir cuit using a ROM t hat accept s a 2-bit number and
gener at es an out put binar y number equal t o t he squar e of t he input number.
Step 1: Der ive t he t r ut h t able for t he combinat ional cir cuit . For t he given example t he
t r ut h t able is
Inputs Outpus Equivalent decimal
A
1
A
0
B
3
B
2
B
1
B
0
0 0 0 0 0 0 0
0 1 0 0 0 1 1
1 0 0 1 0 0 4
1 1 1 0 0 1 9
Step 2: If possible, r educe t he t r ut h t able for t he ROM by using cer t ain pr oper t ies in t he
t r ut h t able of t he combinat ional cir cuit . For t he given example, t wo input s and four out put s
ar e needed t o accommodat e all possible number s.
Programmable Logic Devices 199
Since out put B
0
is always equal t o input A
0
, t her efor e t her e is no need t o gener at e B
0
wit h a ROM. Also B
1
is known as it is always 0. Ther efor e we need t o gener at e only t wo
out put s wit h t he ROM; t he ot her t wo ar e easily obt ained.
Step 3: Find t he minimum size of ROM fr om st ep 2
The minimum size ROM needed must have t wo input s and t wo out put s. Two input s
specify four wor d, so t he ROM size must be 4×2. The t wo input s specify four wor ds of t wo
bit s each. The ot her t wo out put s of t he combinat ional cir cuit ar e equal t o 0 (D1) and A0(D0).
A
1
A
0
D
3
D
2
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 0
ROM t r ut h t able
5.2 PRO G RAM M ABLE LO G IC ARRAYS
The fir st t ype of user -pr ogr ammable chip t hat could implement logic cir cuit s was t he
Pr ogr ammable Read-Only Memor y (PROM), in which addr ess lines can be used as logic cir cuit
input s and dat a lines as out put s. Fig. 5.5 shows t he basic configur at ion of PROM.
Inputs
Fixed
AND array
(decoder)
Programmable
OR array
Outputs
Fig. 5.5 Basic configur at ion of Pr ogr ammable Read-Only Memor y (PROM)
Logic funct ions, however, r ar ely r equir e mor e t han a few pr oduct t er ms, and a PROM
cont ains a full decoder for it s addr ess input s. PROMs ar e t hus an inefficient ar chit ect ur e for
r ealizing logic cir cuit s, and so ar e r ar ely used in pr act ice for t hat pur pose. The fir st device
developed lat er specifically for implement ing logic cir cuit s was t he Field-Pr ogr ammable Logic
Ar r ay (FPLA), or simply PLA for shor t . A PLA consist s of t wo levels of logic gat es: a
programmable “wir ed” AND-plane followed by a pr ogr ammable “wir ed” OR-plane.
Inputs
Programmable
OR array
Outputs
Programmable
AND array
Fig. 5.6 Basic configurat ion of Programmable Logic Array (PLA)
A PLA is st ruct ured so t hat any of it s input s (or t heir complement s) can be AND’ed
t oget her in t he AND-plane; each AND-plane out put can t hus correspond t o any product t erm
of t he input s. Similarly, each OR plane out put can be configured t o produce t he logical sum of
any of t he AND-plane out put s. Wit h t his st ruct ure, PLAs are well-suit ed for implement ing logic
funct ions in sum-of-product s form. They are also quit e versat ile, since bot h t he AND t erms and
OR t erms can have many input s (t his feat ure is oft en referred t o as wide AND and OR gat es).
Pr ogr ammable Logic Ar r ays (PLAs) have t he same pr ogr ammable OR ar r ay as a ROM,
but also have a pr ogr ammable AND ar r ay inst ead of t he decoder as shown in Fig. 5.7. The
pr ogr ammable AND ar r ay can be used t o pr oduce ar bit r ar y pr oduct t er ms, not just mint er ms.
While t he decoder pr oduces all mint er ms of k var iables.
200 S witching Theory
AND
ARRAY
X
k
p
0
p
m
Y
n–1
Y
1
Y
0
p
1
X
1
X
0
OR
ARRAY
Fi g. 5.7
Since t he number of possible pr oduct t er ms m in PLA is much less t han t he number of
possible mint er ms 2
k
, so some funct ions may not be r ealizable in PLA.
The st r uct ur e of a r ow of t he pr ogr ammable AND ar r ay is shown in Fig. 5.8 (a).
X
k
X
1
X
0
p
i
1
Fig. 5.8 (a)
and of a column of t he pr ogr ammable OR ar r ay is shown in Fig. 5.8 (b).
Fig. 5.8 (b)
While t he not at ion of a PLA is shown in Fig. 5.9.
Fi g. 5.9
Programmable Logic Devices 201
5.2.1 Re a lizing Log ic a l Func tions with PLAs
Dur ing implement at ion (or pr ogr amming) a dot (or cr oss) is placed at an int er sect ion if
t he var iable is t o be included in t he pr oduct t er m or t o sum t er m. For example a PLA wit h
3 input s, 4 pr oduct t er ms and 2 out put s is shown.
Example. Implement t he following wit h PLA.
P1 = A' • C'
P2 = A' • C
P3 = A • B'
P4 = A • B • C
X = P3 = A • B'
Y = P2 + P4 = A' • C + A • B • C
Z = P1 + P3 = A' • C' + A • B'
A B C
P
1
P
2
P
3
P
4
X Y Z
Note: In t his implement at ion dot is placed at int er sect ion but cr oss can be used for
t he same.
202 S witching Theory
5.3 PROGRAMMABLE ARRAY LO G IC ( PAL)
When PLAs wer e int r oduced in t he ear ly 1970s, by Phillips, t heir main dr awbacks ar e
t hat t hey are expensive t o manufact ure and offered poor speed-performance. Bot h disadvant ages
ar e due t o t he t wo levels of configur able logic, because pr ogr ammable logic planes wer e
difficult t o manufact ur e and int r oduced significant pr opagat ion delays. To over come t hese
weaknesses, Pr ogr ammable Ar r ay Logic (PAL) devices ar e developed. As Fig. 5.10 (a) illust r at es,
PALs feat ur e only a single level of pr ogr ammabilit y, consist ing of a pr ogr ammable “wir ed”
AND plane t hat feeds fixed OR-gat es.
Inputs
Programmable
AND array
Fixed
OR array
Outputs
Fig. 5.10 (a) Basic configurat ion of Programmable Array Logic (PAL)
To compensat e for lack of gener alit y incur r ed because t he OR Out put s plane is fixed,
sever al var iant s of PALs ar e pr oduced, wit h differ ent number s of input s and out put s, and
var ious sizes of OR-gat es. PALs usually cont ain flip-flops connect ed t o t he OR-gat e out put s so
t hat sequent ial cir cuit s can be r ealized. PAL devices ar e impor t ant because when int r oduced
t hey had a pr ofound effect on digit al har dwar e design, and also t hey ar e t he basis for mor e
sophist icat ed ar chit ect ur es. Var iant s of t he basic PAL ar chit ect ur e ar e feat ur ed in sever al
ot her pr oduct s known by differ ent acr onyms. All small PLDs, including PLAs, PALs, and PAL-
like devices ar e gr ouped int o a single cat egor y called Simple PLDs (SPLDs), whose most
impor t ant char act er ist ics ar e low cost and ver y high pin-t o-pin speed-per for mance.
While t he ROM has a fixed AND ar r ay and a pr ogr ammable OR ar r ay, t he PAL has a
pr ogr ammable AND ar r ay and a fixed OR ar r ay. The main advant age of t he PAL over t he PLA
and t he ROM is t hat it is fast er and easier t o fabr icat e.
Fig. 5.10 (b) r epr esent s a segment of an unpr ogr ammed PAL.
I
2
I
1
F
1
F
4
F
2
F
3
F
5
F
6
Output
fuse
Fig. 5.10 (b) PAL segment
The symbol
Non-inverted output
Inverted output
Programmable Logic Devices 203
Repr esent s an input buffer which is logically equivalent t o
A buffer is used because each PAL input have t o dr ive many AND gat e input s. When t he
PAL is pr ogr ammed, t he fusible links (F
1
, F
2
, ..... F
8
) ar e select ively blown t o leave t he
desir ed connect ion t o t he AND gat e input s. Connect ions t o t he AND gat e input s in a PAL ar e
r epr esent ed by X’s as shown
A
B
C
ABC × × ×
A B C
ABC
Fig. 5.10 (c) shows t he use of PAL segment of Fig. 5.10 (b) t o r ealize t he funct ion I′ I
2

+ I
1
′ I
2
. The X’s indicat e t hat t he I
1
′ and I
2
′ lines ar e connect ded t o t he fir st AND gat e, and
t he I
1
, and I
2
lines ar e connect ed t o t he ot her gat e
× ×
× ×
I
1
I
2
I + I + I I
1 2
1
2
′ ′
Fig. 5.10 (c) Pr ogr ammed PAL Example
In ear ly PALs, only seven pr oduct t er ms could be summed int o an OR gat e. Ther efor e,
not all funct ions could be r ealized wit h t hese PLAs. Also, t he out put was inver t ed in t hese
ear ly PALs so t hat what was r eally r ealized is
(P1 + P2 + . . . + P7)′ = P1′ • P2′ • . . . • P7′
Example of fir st -gener at ion PAL is PAL 16L8 having following feat ur es.
• 10 input , 2 complement ed out put s, 6 I/O pins
• Programmable (one AND t er m) 3-st at e out put s
• Seven pr oduct t er ms per out put
• 20 pin chip
• 10 input (14 for 20V8)
A sum of pr oduct s funct ion wit h a small number of pr oduct t er ms may r equir e a lar ge
number pr oduct t er ms when r ealized wit h a PAL.
For example: To implement t he funct ion Z = A • B • C + D • E • F
The inver t ed out put of t he funct ion Z' is given as
Z′ = (A • B • C)' • (D • E • F)' = (A' + B' + C') • (D' + E' + F')
= A' • D' + A' • E' + A' • F' + B' • D' + B' • E' + B' • F'
+ C' • D' + C' • E' + C' • F'
= p1 + p2 + p3 + p4 + p5 + p6 + p7 + p8 + p9
204 S witching Theory
This has nine pr oduct t er ms and could not be r ealized in one pass wit h t he ear ly PALs.
The only way t o r ealize t he t his funct ion in a PAL is t o use t wo passes as shown.
5.3.1 C omme rc ia lly Ava ila b le SPLDs
For digit al har dwar e designer s for t he past t wo decades, SPLDs ar e ver y impor t ant
devices. SPLDs r epr esent t he highest speed-per for mance FPDs available, and ar e inexpensive.
They ar e also st r aight for war d and well under st ood.
Two of t he most popular SPLDs ar e t he PALs produced by Advanced Micr o Devices
(AMD) known as t he 16R8 and 22V10. Bot h of t hese devices ar e indust r y st andar ds and ar e
widely second-sour ced by var ious companies. The name “16R8” means t hat t he PAL has a
maximum of 16 input s (t her e ar e 8 dedicat ed input s and 8 input /out put s), and a maximum
of 8 out put s. The “R” r efer s t o t he t ype of out put s pr ovided by t he PAL and means t hat each
out put is “r egist er ed” by a D flip-flop. Similar ly, t he “22V10” has a maximum of 22 input s and
10 out put s. Her e, t he “V” means each out put is “ver sat ile” and can be configur ed in var ious
ways, some configur at ions r egist er ed and some not .
Anot her widely used and second sour ced SPLD is t he Alt er a Classic EP610. This device
is similar in complexit y t o PALs, but it offer s mor e flexibilit y in t he way t hat out put s ar e
pr oduced and has lar ger AND- and OR-planes. In t he EP610, out put s can be r egist er ed and
t he flip-flops ar e configur able as any of D, T, J K, or SR.
In addit ion t o t he SPLDs ment ioned above many ot her pr oduct s ar e commer cial available.
All SPLDs shar e common char act er ist ics, like some sor t of logic planes (AND, OR, NOR, or
NAND), but each specific pr oduct offer s unique feat ur es t hat may be par t icular ly suit able for
some applicat ions.
5.3.2 G e ne ric Arra y Log ic ( G AL)
Generic Ar r ay Logic (GAL) is a pr ogr ammable logic device t hat can be configur ed t o
emulat e many ear lier PLDs including t hose wit h int er nal flip-flops. GAL 16V8C and 20V8C
ar e examples of Gener ic Ar r ay Logic. The only differ ence bet ween t he t wo is t hat t he 16V8
is a 20-pin chip and t he 20V8 is a 24-pin chip, which uses t he ext r a pins for input s. The
char act er ist ics of t hese devices ar e:
• 10 input (14 for 20V8)
• Programmable (one AND t er m) 3-st at e out put s
• Seven or eight pr oduct t er ms per out put
• Pr ogr ammable out put polar it y
Programmable Logic Devices 205
• Realize eit her t r ue or complement ed out put signal
• Realize eit her POS or SOP dir ect ly
When using GAL as a combinat ional device, All out put s can be pr ogr ammed t o one of
t he following t hr ee configur at ions except t hat t he t wo end out put s have some minor limit at ions
as illust r at ed by Fig. 5.11.
Bidirectional I/O
Dedicated Output
1
Dedicated Input
0
I/o
Output
Input
Fig. 5.11
For example GAL 22V10C is a 24-pin chip having 12 input t er minals and 10 input /out put
t er minals. Among out put s, t wo of t he out put s can have up t o 8 pr oduct t er ms, two have 10,
t wo have 12, t wo have 14 and t wo have 16, except t he out put buffer cont r ol.
The Combinat ional Configur at ions for GAL 22V10C is
I/o
5.3.3 Ap p lic a tions of PLDs
PLDs ar e oft en used for addr ess decoding, wher e t hey have sever al clear advant ages over
t he 7400-ser ies TTL par t s t hat t hey r eplaced. Fir st , of cour se, is t hat one chip r equir es less
boar d ar ea, power, and wir ing t han sever al do. Anot her advant age is t hat t he design inside
t he chip is flexible, so a change in t he logic doesn’t r equir e any r ewir ing of t he boar d. Rat her,
t he decoding logic can be alt er ed by simply r eplacing t hat one PLD wit h anot her par t t hat
has been pr ogr ammed wit h t he new design.
206 S witching Theory
5.4 C O M PLEX PRO G RAM M ABLE LO G IC DEVIC ES ( C PLD)
As t echnology has advanced, it has become possible t o pr oduce devices wit h higher
capacit y t han SPLDs (PALs). The difficult y wit h increasing capacit y of a st rict SPLD archit ect ure
is t hat t he st r uct ur e of t he pr ogr ammable logic-planes gr ows t oo quickly in size as t he
number of input s is incr eased. It also significant ly slows t he chip down due t o long r ows of
AND gat es. The only feasible way t o provide large capacit y devices based on SPLD archit ect ures
is t hen t o int egr at e mult iple SPLDs ont o a single chip, and ar e r efer r ed t o as Complex PLDs
(CPLDs) as shown in Fig. 5.12.
Fig. 5.12 (a)
PAL-like block (details not shown)
D Q
D Q
D Q
Fig. 5.12 (b)
Programmable Logic Devices 207
5.4.1 Ap p lic a tions of C PLDs
Because CPLDs offer high speeds and a r ange of capacit ies, t hey ar e useful for a ver y
wide r ange of applicat ions, fr om implement ing r andom glue logic t o pr ot ot yping small gat e
ar r ays. One of t he most common uses in indust r y at t his t ime, and a st r ong r eason for t he
lar ge gr owt h of t he CPLD mar ket , is t he conver sion of designs t hat consist of mult iple SPLDs
int o a smaller number of CPLDs.
CPLDs can r ealize r easonably complex designs, such as gr aphics cont r oller, LAN
cont r oller s, UARTs, cache cont r ol, and many ot her s. As a gener al r ule-of-t humb, cir cuit s t hat
can exploit wide AND/OR gat es, and do not need a ver y lar ge number of flip-flops ar e good
candidat es for implement at ion in CPLDs. A significant advant age of CPLDs is t hat t hey
pr ovide simple design changes t hr ough r e-pr ogr amming (all commer cial CPLD pr oduct s ar e
r e-pr ogr ammable). Wit h pr ogr ammable CPLDs it is even possible t o r e-configur e har dwar e
(an example might be t o change a pr ot ocol for a communicat ions cir cuit ) wit hout power -down.
Designs oft en par t it ion nat ur ally int o t he SPLD-like blocks in a CPLD. The r esult is
mor e pr edict able speed-per for mance t han would be t he case if a design wer e split int o many
small pieces and t hen t hose pieces wer e mapped int o differ ent ar eas of t he chip. Pr edict abilit y
of cir cuit implement at ion is one of t he st r ongest advant ages of CPLD ar chit ect ur es.
5.5 FIELD- PRO G RAM M ABLE G ATE ARRAYS ( FPG A)
Field Programmable Gat e Arrays (FPGAs) ar e flexible, pr ogr ammable devices wit h a
broad range of capabilit ies. Their basic st ruct ure consist s of an array of universal, programmable
logic cells embedded in a configur able connect ion mat r ix. Ther e ar e t hr ee key par t s of FPGA
st r uct ur e: logic blocks, int er connect , and I/O blocks. The I/O blocks for m a r ing ar ound t he
out er edge of t he par t . Each of t hese pr ovides individually select able input , out put , or bi-
dir ect ional access t o one of t he gener al-pur pose I/O pins on t he ext er ior of t he FPGA package.
Inside t he r ing of I/O blocks lies a r ect angular ar r ay of logic blocks. And connect ing logic
blocks t o logic blocks and I/O blocks t o logic blocks is t he pr ogr ammable int er connect wir ing.
In FPGAs , CPLD’s PLDs ar e r eplaced wit h a much smaller logic block. The logic blocks
in an FPGA ar e gener ally not hing mor e t han a couple of logic gat es or a look-up t able and
a flip-flop. The FPGAs use a mor e flexible and fast er int er connect ion st r uct ur e t han t he
CPLDs. In t he FPGAs, t he logic blocks ar e embedded in a mesh or wir es t hat have pr ogr amm-
able int er connect point s t hat can be used t o connect t wo wir es t oget her or a wir e t o a logic
block as shown in Fig. 5.13.
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Configurable
Logic
Block (CLB)
I/O Block
Configurable
Logic
Block (CLB)
I/O Block
I
/
O

B
l
o
c
k
Configurable
Logic
Block (CLB)
Configurable
Logic
Block (CLB)
I
/
O

B
l
o
c
k
I/O Pins
Fig. 5.13 Fig. 5.14
208 S witching Theory
Ther e ar e sever al ar chit ect ur es for FPGAs available but t he t wo popular ar chit ect ur es
ar e t hat , used by Xilinx and Alt er a. The Xilinx chips ut ilize an “island-t ype” ar chit ect ur e,
wher e logic funct ions ar e br oken up int o small islands of 4–6 t er m ar bit r ar y funct ions, and
connect ions bet ween t hese islands ar e comput ed. Fig. 5.14 illust r at es t he basic st r uct ur e of
t he Xilinx FPGA. Alt er a’s ar chit ect ur e t ies t he chip input s and out put s mor e closely t o t he
logic blocks, as shown in Fig. 5.15. This ar chit ect ur e places t he logic blocks ar ound one
cent r al, highly connect ed r out ing ar r ay.
The cir cuit s used t o implement combinat ional logic in logic blocks ar e called lookup
t ables (LUT). For example t he LUT in t he Xilinx XC4000 uses t hr ee ROMs t o r ealize t he
LUTs and gener at e t he following classes of logical funct ions:
Logic
Array
Block
(LAB)
Logic
Array
Block
(LAB)
Logic
Array
Block
(LAB)
Programmable
Interconnection
Array
(PIA)
Logic
Array
Block
(LAB)
Logic
Array
Block
(LAB)
Logic
Array
Block
(LAB)
I/O Pins
Fig. 5.15
• Any t wo differ ent funct ions of 4 var iables each plus any ot her funct ion of 3 var iables.
• Any funct ion of 5 var iables. How?
• Any funct ion of 4 var iables, plus some (but not all) funct ions of 6 var iables.
• Some (but not all) funct ions of up t o 9 var iables.
G
G
H
Fi g. 5.16
The Fig. 5.16 shows t he LUT’s st r uct ur e in Xilinx XC4000. The boxes G and H ar e
ROMs wit h 16 1-bit wor ds and H is a ROM wit h 8 1-bit wor ds. While t he st r uct ur e of LUT’s
in Alt er a FPGAs ar e as shown in Fig. 5.17.
Programmable Logic Devices 209
= Pr ogr am – cont r olled mult iplexer
Fi g. 5.17
• Example of pr ogr ammed FPGA
5.5.1 Ap p lic a tions of FPG As
FPGAs have gained r apid accept ance and gr owt h over t he past decade because t hey can
be applied t o a ver y wide r ange of applicat ions. A list of t ypical applicat ions includes: r andom
logic, int egr at ing mult iple SPLDs, device cont r oller s, communicat ion encoding and filt er ing,
small t o medium sized syst ems wit h SRAM blocks, and many mor e.
Ot her int erest ing applicat ions of FPGAs are prot ot yping of designs lat er t o be implement ed
in gat e ar r ays, and also emulat ion of ent ir e lar ge har dwar e syst ems. The for mer of t hese
applicat ions might be possible using only a single lar ge FPGA (which cor r esponds t o a small
Gate Ar r ay in t er ms of capacit y), and t he lat t er would involve many FPGAs connect ed by
some sor t of int er connect .
Anot her promising area for FPGA applicat ion, which is only beginning t o be developed, is
t he usage of FPGAs as cust om comput ing machines. This involves using t he programmable
part s t o “execut e” soft ware, rat her t han compiling t he soft ware for execut ion on a regular CPU.
210 S witching Theory
5.6 USER- PRO G RAM M ABLE SWITC H TEC HNO LO G IES
The fir st t ype of user-pr ogr ammable swit ch developed was t he fuse used in PLAs. Alt hough
fuses ar e st ill used in some smaller devices, but for higher densit y devices, wher e CMOS
dominat es t he IC indust r y, differ ent appr oaches t o implement ing pr ogr ammable swit ches
have been developed. For CPLDs t he main swit ch t echnologies (in commer cial pr oduct s) ar e
float ing gat e t r ansist or s like t hose used in EPROM and EEPROM, and for FPGAs t hey ar e
SRAM and ant ifuse. Each of t hese ar e br iefly discussed below.
An EEPROM or EPROM t r ansist or is used as a pr ogr ammable swit ch for CPLDs (and
also for many SPLDs) by placing t he t r ansist or bet ween t wo wir es in a way t hat facilit at es
implement at ion of wir ed-AND funct ions. This is illust r at ed in Fig. 5.18, which shows EPROM
t r ansist or s as t hey might be connect ed in an AND-plane of a CPLD. An input t o t he AND-
plane can dr ive a pr oduct wir e t o logic level ‘0’ t hr ough an EPROM t r ansist or, if t hat input
is par t of t he cor r esponding pr oduct t er m. For input s t hat ar e not involved for a pr oduct t er m,
t he appr opr iat e EPROM t r ansist or s ar e pr ogr ammed t o be per manent ly t ur ned off. A diagr am
for an EEPROM based device would look similar.
+5V
EPROM EPROM
Input wire Input wire
Product wire
Fi g. 5.18 EPROM Pr ogr ammable Swit ches.
Alt hough t her e is no t echnical r eason why EPROM or EEPROM could not be applied t o
FPGAs, cur r ent commer cial FPGA pr oduct s ar e based eit her on SRAM or ant ifuse
t echnologies, as discussed below.
Fi g. 5.19 SRAM-cont r olled Pr ogr ammable Swit ches
Programmable Logic Devices 211
An example of usage of SRAM-cont r olled swit ches is illust r at ed in Fig. 5.19, showing t wo
applicat ions of SRAM cells: for cont r olling t he gat e nodes of pass-t r ansist or swit ches and t o
cont r ol t he select lines of mult iplexer s t hat dr ive logic block input s.
The figur es gives an example of t he connect ion of one logic block (r epr esent ed by t he
AND-gat e in t he upper left cor ner ) t o anot her t hr ough t wo pass-t r ansist or swit ches, and t hen
a mult iplexer, all cont r olled by SRAM cells. Whet her an FPGA uses pass-t r ansist or s or
mult iplexer s or bot h depends on t he par t icular pr oduct .
The ot her t ype of pr ogr ammable swit ch used in FPGAs is t he ant ifuse. Ant ifuses ar e
or iginally open-cir cuit s and t ake on low r esist ance only when pr ogr ammed. Ant ifuses ar e
suit able for FPGAs because t hey can be built using modified CMOS t echnology. As an example,
Act el’s ant ifuse st r uct ur e, known as PLICE, is depict ed in Fig. 5.20. The figur e shows t hat
an ant ifuse is posit ioned bet ween t wo int er connect wir es and physically consist s of t hr ee
sandwiched layer s: t he t op and bot t om layer s ar e conduct or s, and t he middle layer is an
insulat or. When unpr ogr ammed, t he insulat or isolat es t he t op and bot t om layer s, but when
pr ogr ammed t he insulat or changes t o become a low-r esist ance link. PLICE uses Poly-Si and
n+ diffusion as conduct or s and ONO as an insulat or, but ot her ant ifuses r ely on met al for
conduct or s, wit h amor phous silicon as t he middle layer.
Fig. 5.20 Actel Ant ifuse St r uct ur e
Table list s t he most impor t ant char act er ist ics of t he pr ogr amming t echnologies discussed
in t his sect ion. The left -most column of t he t able indicat es whet her t he pr ogr ammable swit ches
ar e one-t ime pr ogr ammable (OTP), or can be r e-pr ogr ammed (RP). The next column list s
whet her t he swit ches ar e volat ile, and t he last column names t he under lying t r ansist or
t echnology.
Table: Summary of Programming Technologies
Name Re-programmable Volatile Technology
Fuse no no Bipolar
EPROM Yes (out of cir cuit ) no UVCMOS
EEPROM Yes (in cir cuit ) no EECMOS
SRAM Yes (in cir cuit ) yes CMOS
Ant ifuse no no CMOS+
5.7 EXERC I SES
1. Realize t he following funct ions using PLA
f
1
(A, B, C) = Σ (0, 2, 4, 5)
f
2
(A, B, C) = Σ (1, 5, 6, 7)
212 S witching Theory
2. Realize t he following funct ions using PLA
f
1
= Σ (1, 2, 3, 5)
f
2
= Σ (2, 5, 6, 7)
f
3
= Σ (0, 4, 6)
3. What is a PLA ? Descr ibe it s uses.
4. What is ROM ? Descr ibe using block diagr am. What size ROM would it t ake t o
implement a binar y mult iplier t hat mult iplies t wo 4 bit -number s.
5. Implement t he combinat ional cir cuit specified by t he t r ut h t able given
Inputs Outputs
A
1
A
0
F
1
F
2
0 0 0 1
0 1 1 0
1 0 1 1
1 1 1 0
6. Der ive t he PLA pr ogr am t able for a combinat ional cir cuit t hat squar es a 3-bit
number. Minimize t he number of pr oduct t er ms.
7. Implement t he pr oblem 6 wit h t he ROM.
8. List t he PLA pr ogr am t able for t he BCD-t o-excess-3 code conver t er.
9. Wr it e shor t not es on user pr ogr ammable swit ch t echnologies.
10. Wr it e shor t not es on following:
(i) ROM (ii) PLA
(iii) PAL (iv) GAL
(v) CPLD (vi) FPGA
6.0 INTRO DUC TIO N
In t he ear lier chapt er s, we st udied t he digit al cir cuit s whose out put at any inst ant of
t ime ar e ent ir ely dependent on t he input pr esent at t hat t ime. Such cir cuit s ar e called as
combinat ional cir cuit s on t he ot her hand sequenti al ci rcui ts ar e t hose in which t he out put
at any inst ant of t ime is det er mined by t he applied input and past hist or y of t hese input s
(i.e. pr esent st at e). Alt er nat ely, sequent ial cir cuit s ar e t hose in which out put at any given
t ime is not only dependent on t he input , pr esent at t hat t ime but also on pr evious out put s.
Nat ur ally, such cir cuit s must r ecor d t he pr evious out put s. This gives r ise t o memor y. Oft en,
t her e ar e r equir ement s of digit al cir cuit s whose out put r emain unchanged, once set , even
if t he input s ar e r emoved. Such devices ar e r efer r ed as “memor y element s”, each of which
can hold 1-bit of infor mat ion. These binar y bit s can be r et ained in t he memor y indefinit ely
(as long as power is deliver ed) or unt ill new infor mat ion is feeded t o t he cir cuit .
Combinational
Circuit
Memory
Devices
External
Output
External
Input
Clock Input
Fig. 6.1 Block Diagr am of a Sequent ial Cir cuit
A block diagr am of a sequent ial cir cuit is shown in Fig. 6.1. A Sequenti al ci rcui t can
be r egar ded as a collect ion of memor y element s and combinat ional cir cuit , as shown in
Fig. 6.1. A feedback pat h is for med by using memor y element s, input t o which is t he out put
of combinat ional cir cuit . The binar y infor mat ion st or ed in memor y element at any given
t ime is defined as t he state of sequent ial cir cuit at t hat t ime. Pr esent cont ent s of memor y
element s is r efer r ed as t he present state. The combinat ional cir cuit r eceive t he signals
fr om ext er nal input and fr om t he memor y out put and det er mines t he ext er nal out put . They
also det er mine t he condit ion and binar y values t o change t he st at e of memor y. The new
cont ent s of t he memor y element s ar e r efer r ed as next state and depend upon t he ext er nal
6
CHAPTER
213
SYNCHRONOUS (CLOCKED)
SEQUENTIAL CIRCUITS
214 S witching Theory
input and pr esent st at e. Hence a sequent ial cir cuit can be complet ely specified by a t ime
sequence of input s, out put s and t he int er nal st at es. In gener al, clock is used t o cont r ol t he
oper at ion. The clock fr equency det er mines t he speed of oper at ion of a sequent ial cir cuit .
Ther e exist t wo ma in ca t egor y of sequent ia l cir cuit s, na mely synchr onous a nd
asynchr onous sequent ial cir cuit s.
A sequent ial cir cuit whose behaviour depends upon t he sequence in which t he input s
ar e applied, ar e called Asynchronous Sequenti al Ci rcui ts . In t hese cir cuit s, out put s ar e
affect ed whenever a change in input s ar e det ect ed. Memor y element s used in asynchr onous
cir cuit s most ly, ar e t ime delay devices. The memor y capabilit y of t ime delay devices ar e due
t o t he pr opagat ion delay of t he devices. Pr opagat ion delay pr oduced by t he logic gat es ar e
sufficient for t his pur pose. Hence “An Synchr onous sequent ial cir cuit can be r egar ded as a
combinat ional cir cuit wit h feedback”. However feedback among logic gat es make t he
asynchr onous sequent ial cir cuit s, oft en suscept ible t o inst abilit y. As a r esult t hey may become
unst able. This makes t he design of asynchr onous cir cuit s ver y t edious and difficult .
A Synchronous Sequential Circuit may be defined as a sequent ial cir cuit , whose
st at e can be affect ed only at t he discr et e inst ant s of t ime. The synchr onizat ion is achieved
by using a t iming device, t ermed as System Clock Generator, which gener at es a per iodic
t r ain of clock pulses. The clock pulses ar e feeded t o ent ir e syst em in such a way t hat
int er nal st at es (i.e. memor y cont ent s) ar e affect ed only when t he clock pulses hit t he cir cuit .
A synchr onous sequent ial cir cuit t hat uses clock at t he input of memor y element s ar e
referred as Clocked Sequenti al ci rcui t.
The clocked sequent ial cir cuit s use a memor y element known as Fli p-Flop. A flip-flop
is an elect r onic cir cuit used t o st or e 1-bit of infor mat ion, and t hus for ms a 1-bit memor y cell.
These cir cuit s have t wo out put s, one giving t he value of binar y bit st or ed in it and t he ot her
gives t he complement ed value. In t his chapt er it is our pr ime concer n t o discuss t he
char act er ist ics of most common t ypes of flip-flops used in digit al syst ems.
The r eal differ ence among var ious flip-flops ar e t he number of input s and t he manner
in which binar y infor mat ion can be ent er ed int o it . In t he next sect ion we examine t he most
gener al flip-flops used in digit al syst ems.
6.1 FLIP- FLO PS
We have ear lier indicat ed t hat flip-flops ar e 1-bit memor y cells, t hat can maint ain t he
st or ed bit for desir ed per iod of t ime.
A Bi stable device is one in which t wo well defined st at es exist , and at any t ime t he
device could assume eit her of t he st able st at es. A stable state is a st at e, once r eached by
a device does not changes unt ill and unless somet hing is done t o change it . A t oggle swit ch
has t wo st able st at es, and can be r egar ded as a bist able device. When it is closed, it r emains
closed (A st able st at e) unt ill some one opens it . When it is open, it r emains open (2nd st able
st at e) unt ill some one closes it i.e. make it t o r et ur n t o it s fir st st able st at e. So it is evident
t hat t he swit ch may be viewed as 1-bit memor y cell, since it maint ains it s st at e (eit her open
or close). Infact any bist able device may be r efer r ed as 1-bit memor y cell.
A Fli p-Flop may also be defined as a bist able elect r onics device whose t wo st able
st at es ar e 0V and + 5V cor r esponding t o Logic 0 and Logic 1 r espect ively. The t wo st able
st at es and flip-flop as a memor y element is illust r at ed in Fig. 6.2. Fig. 6.2 (a) shows t hat
t he flip-flop is in ‘St at e 0’ as out put is 0V. This can be r egar ded as st or ing Logic 0. Similar ly
flip-flop is said t o be in ‘St at e 1’, see Fig. 6.2 (b), when t he out put is 5 V. This can be r egar ded
S ynchronous (Clocked) S equential Circuits 215
as st or ing logic 1. Since at any given t ime flip-flop is in eit her of t wo st at es t he flip-flop may
also be r egar ded as Bist able Mult ivibr at or. Since t he st at e once r eached is maint ained unt ill
it is deliber at ely changed, t he flip-flop is viewed as memor y element .
Flip-Flop
0V
Output
+V = 5V
CC
(a) State 0 or Low State
Flip-Flop
5V
Output
+V = 5V
CC
(b) State 1 or High State
Fig. 6.2 Flip-Flop as Bist able Device
The basic memor y cir cuit or flip-flop can be easily obt ained by connect ing t wo inver t er s
(Not gat es) in ser ies and t hen connect ing t he out put of second inver t er t o t he input of fir st
inver t er t hr ough a feedback pat h, as shown in Fig. 6.3(a).
(a)
B A
S
Feed Back Path
Switch
V
1
V
3
V
2
(b)
B A
V = 0V
1
V
3
= 0V
V = 5V
2
S
(c)
B A
S
V = 0V
1
V = 0V
3
V = 5V
2
(d)
B A
S
V = 5V
1
V = 5V
3
V = 0V
2
Fi g. 6.3 Basic Flip-Flop or Lat ch ‘Logic 0’ = 0V, and ‘Logic 1’ = 5 V
It is evident fr om figur e t hat V
1
and V
3
will always be same, due t o ver y nat ur e of
inver t er s.
216 S witching Theory
Let us define Logic 0 = 0V and Logic 1 = 5 V. Now open t he swit ch ‘S’ t o r emove t he
feedback and connect V
1
t o gr ound, as shown in Fig. 6.3 (b). Thus input t o inver t er A is Logic
0 and it s out put would be Logic 1 which is given t o t he input of inver t er B. Since input t o
inver t er B is Logic 1, it s out put would be Logic 0. Hence input of inver t er A and out put of
inver t er B ar e same. Now if we close t he swit ch S feedback pat h is r econnect ed, t hen gr ound
can be r emoved fr om V
1
and V
3
can st ill be at 0V i.e. Logic 0. This is shown in Fig. 6.3 (c).
This is possible because once t he V
1
is given 0V (i.e. Logic 0) t he V
3
will also be at 0V and
t hen it can be used t o hold t he input t o inver t er A at 0V, t hr ough t he feedback pat h. This
is fir st st able st at e.
In t he simpler way if we connect t he V
1
t o 5 V and r epeat t he whole pr ocess, we r each
t o second st able st at e because V
3
= 5V. Essent ially t he V
3
holds t he input t o inver t er. A (i.e.
V
1
), allowing + 5V supply t o be r emoved, as shown in Fig. 6.3 (d). Thus V
3
= 5 V can be
maint ained unt ill desir ed per iod t ime.
A simple obser vat ion of t he flip-flop shown in Fig. 6.3 (a) r eveals t hat V
2
and V
3
ar e
always complement ar y, i.e.
V V
2 3
=
or
V V .
3 2
=
This does mean t hat “at any point of t ime,
ir r espect ive of t he value of V
1
, bot h t he st able st at es ar e available”, see Fig. 6.3 (c) 6.3 (d).
This is fundament al condit ion t o 9 Flip-Flop.
Since t he infor mat ion pr esent at t he input (i.e. at V
1
) is locked or lat ched in t he cir cuit ,
it is also r efer r ed or Latch.
When t he out put is in low st at e (i.e. V
3
= 0 V), it is fr equent ly r efer r ed as Reset State.
Wher e as when t he out put is in high st at e (i.e. V
3
= 5 V), it is convenient ly called as Set
State. Fig. 6.3 (c) and 6.3 (d) shows t he r eset and set st at es, r espect ively.
6.1.1 RS Flip - Flop
Alt hough t he basic lat ch shown by t he Fig. 6.3 (a) was successful t o memor ize (or st or e)
1-bit infor mat ion, it does not pr ovide any convenient mean t o ent er t he r equir ed binar y bit .
Thus t o pr ovide a way t o ent er t he dat a cir cuit of Fig. 6.3 (a) can be modified by r eplacing
t he t wo inver t er s by t wo 2-input NOR gat e or NAND gat es, discussed in following ar t icles.
The NOR LATCH: The NOR lat ch is shown by Fig. 6.4 (a) and 6.4 (b). Not ice t hat if
we connect t he input s, labelled as R and S, t o logic 0 t he cir cuit will be same as t he cir cuit
shown in Fig. 6.3 (a) and t hus behave exact ly same as t he NOT gat e lat ch of Fig. 6.3 (a).
The volt age V
2
and V
3
ar e now labelled as Q and
Q and
ar e declar ed as out put . Regar dless
of t he value of Q, it s complement is
Q as V V ( ).
3 2
=
The t wo input s t o t his flip-flop ar e R and
S, st and for RESET and SET input s r espect ively. A ‘1’ on input R swit ches t he flip-flop in
r eset st at e i.e. Q = ‘0’ and
Q =
‘1’. A ‘1’ on input s (SET input ) will br ing t he lat ch int o set
st at e i.e. Q = ‘1’ and
Q =
‘0’. Due t o t his act ion it is oft en called set-reset latch. The
oper at ion and behaviour is summar ized in t he t r ut h t able shown by Fig. 6.4 (c). Fig. 6.4 (d)
displays t he logic symbol of RS (or SR) flip-flop.
To under st and t he oper at ion of t his flip-flop, r ecall t hat a ‘1’ at any input of a NOR gat e
for ces it s out put t o ‘0’ wher e as ‘0’ at an input does not affect t he out put of NOR gat e.
When input s ar e S = R = 0, fir st r ow of t r ut h t ables it does not affect t he out put . As
a r esult t he Lat ch maint ains it s st at e. For example if befor e applicat ion of t he input s S =
R = 0, t he out put was Q = 1, t hen it r emains 1 aft er S = R = 0 ar e applied. Thus when bot h
S ynchronous (Clocked) S equential Circuits 217
t he input s ar e low t he flip-flop maint ain it s last st at e. That s why t he t r ut h t able has ent r y
Q in fir st r ow.
(c) Truth Table
R
Q
S B
A
R Q
S Q
Resul ting State
Last State or No
Change at output
Reset State
Set State
Indetermi nate
or Forbi dden Stat e
S
0 0
0 0
0
1
1
? 1
1
Q
Q
R
1
(d) Logic Symbol
( V
2
)
( V
3
)
Q
(b) Construction
V
2
A
V
3 R
V
1
(a) Construction
B
Fig. 6.4 Basic NOR Gat e Lat ch or RS (or SR) Flip-Flop
Now if S = 0 and R = 1, out put of gat e-A goes low i.e. Q = 0. The Q is connect ed t o
input of gat e-B along wit h S input . Thus wit h Q = 0 bot h t he input s t o NOR gat e B ar e LOW.
As a result Q 1. = This Q and Q ar e complement ar y. Since Q = 0 t he flip-flop is said t o be
in “r eset st at e”. This is indicat ed by t he second r ow of t he t r ut h t able.
Now if S = 1 and R = 0 out put of gat e-B is LOW, making bot h t he input s of gat e-A LOW,
consequent ly Q = 1. This is “set st at e”. As Q = 1 and Q 0, = t he t wo out put s ar e complement ar y.
This is shown in t hir d r ow of t r ut h t able.
When S = 1 and R = 1, out put of bot h t he gat es ar e for ced t o Logic 0. This conflict s
wit h t he definit ion t hat bot h Q and Q must be complement ar y. Hence t his condit ion must
not be applied t o SR flip-flop. But if due t o some r easons S = 1 and R = 1 is applied, t hen
it is not possible t o pr edict t he out put and flip-flop st at e is said t o be indet er minat e. This
is shown by t he last r ow of t r ut h t able.
It is wor t h t o devot e some t ime t o invest igat e why S = R = 1 r esult s indet er minat e st at e
while we said ear lier t hat out put of bot h t he gat es go LOW for t his input . This is t r ue due
t o t he logic funct ion of NOR gat e t hat if any of t he input is HIGH out put is LOW. In t he
cir cuit of Fig. 6.4 (b) bot h Q and Q ar e LOW as long as S and R ar e High. The pr oblem occur s
when input s S and R got o LOW fr om High. The t wo gat es can not have exact ly same
pr opagat ion delay. Now t he gat e having smaller delay will change it s st at e t o HIGH ear lier
t han t he ot her gat e. And since t his out put (i.e. Logic 1) is feeded t o t he second gat e, t he out put
of second gat e is for ced t o st ay at Logic 0. Thus depending upon t he pr opagat ion delays of
t wo gat es, t he flip-flop at t ains eit her of t he st able st at es (i.e. eit her Q = 1 or Q = 0). Ther efor e
it is not possible t o pr edict t he st at e of flip-flop aft er t he input s S = R = 1 ar e applied. That s
why t he four t h r ow of t r ut h t able cont ains a quest ion mar k (?). For t he above r easons t he
input condit ion S = R = 1 is for bidden.
218 S witching Theory
The NAND Gate Flip-Flop
The NOT gat e lat ch shown by Fig. 6.5 (b) may also be modified by r eplacing each
inver t er by a 2-input NAND gat e as shown in Fig. 6.5 (a). This is a slight ly differ ent lat ch
(a) Construction
A
B
Q
Q
S
R
Resul ting State
Last State or No
Change at output
Reset State
Set State
Indetermi nate
or Forbi dden State
S
1 1
0 1
1
0
0
? 0
0
Q
Out-
put ‘Q’
R
1
(b) Truth Table
Q
(c) Logic Symbol
S Q
R
Fig. 6.5 NAND Gat e Lat ch or S , R Flip-Flop
fr om t he NOR lat ch. We call it S R lat ch. The t r ut h t able (Fig. 6.5(b)) summar izes t he
oper at ion and Fig. 6.5(c) shows t he logic symbol for SR lat ch.
The name SR is given t o t his lat ch t o indicat e t hat int ended oper at ion is achieved on
asser t ing logic ‘0’ t o t he input s. This is complement ar y t o t he NOR lat ch in which oper at ion
is per for med when input is logic ‘1’.
The explanat ion of oper at ion of SR flip-flop lies in t he st at ement t hat , If any input of
NAND gat e goes LOW t he out put is HIGH, wher eas a ‘1’ at any NAND input does not affect
t he out put . Mor eover, t he out put will be LOW only and only when all t he input s t o NAND
gat e ar e HIGH.
When bot h
S and R
ar e HIGH i.e.
S = R = 1,
t hen t he NAND out put ar e not affect ed.
Thus last st at e is maint ained. When S = 1 and
R = 0
t hen out put of gat e-B goes HIGH
making bot h t he input s t o NAND-A as HIGH. Consequent ly Q = 0 which is r eset st at e. In
t he similar way
S = 0
and
R = 1
br ing t he cir cuit t o set st at e i.e. Q = 1. When bot h t he
input s ar e LOW i.e.
S = R = 0
bot h Q and
Q
ar e for ced t o st ay HIGH which int ur ns lead
t o indet er minat e st at e for t he similar r easons given for NOR lat ch.
The SR flip-flop can be modified fur t her by using t wo addit ional NAND gat es.
These t wo gat es, labelled as C and D, ar e connect ed at
S and R
Fig. 6.5 (a) input s t o
act as NOT gat e, as shown in Fig. 6.6 (a). This conver t s SR lat ch int o a lat ch t hat behaves
exact ly same as t he NOR gat e flip-flop (i.e. NOR lat ch), shown in Fig. 6.4 (b). Hence t his
lat ch also is r efer r ed as SR flip-flop. The t r ut h t able and logic symbol will be same as t hat
of NOR lat ch. The t r ut h t able may also be obt ained by inver t ing all t he input bit s in SR
t r ut h t able shown in Fig. 6.5 (b) as input t o SR lat ch is complement ed. To under st and t he
oper at ion of t his lat ch, consider t he Fig. 6.6 (a).
When bot h S and R input s ar e LOW out put s of NAND gat es C and D ar e HIGH. This
is applied t o t he input s of SR lat ch which maint ains t he last st at e in r esponse t o
S = R = 1
(see Fig. 6.5 (b)). In t he same way, applicat ion of S = 0 and R = 1 r esult s S = 1 and R = 0 ,
and consequent ly t he lat ch at t ains “Reset St at e”. Similar ly t he ot her input combinat ion in
t r ut h t able can be ver ified.
S ynchronous (Clocked) S equential Circuits 219
(b) Construction
R Q
S Q S
R
C
D
(a) Modification in S R Flip-Flop
S
A
C
D
B
Q
R
S Q
Q
(d) Logic Symbol
(c) Truth Table
Resul ting State
Last State preserved
Change at output or No
Reset State or
Low Stat e
Set State or
Hi gh State
Indetermi nate
or Forbi dden State
S
0 0
0 0
0
1
1
? 1
1
Q
Out-
put Q
R
1
Q
R
Fig. 6.6 NAND Gat e Lat ch or SR Flip-Flop
At t his point we advice r eader s t o ver ify t he t r ut h t able of SR lat ch t hr ough t he NAND
gat e const r uct ion of t his lat ch, shown in Fig. 6.6 (b).
For t he beginner s it is wor t h t o go back t o t he beginning of t his ar t icle (i.e. st ar t of
6.1.1). Infact t he SR (or RS) flip-flop gives t he basic building block t o st udy and analyze
var ious flip-flops, and t heir applicat ion in t he design of clocked sequent ial cir cuit s.
Example 6.1. Draw the internal block diagram alongwith pinout for IC 74LS 279, a
quad set reset latch. Explain its operation in brief with the help of truth table.
Sol. Fig. 6.7 shows t he r equir ed block diagr am and pinout .
1 2 3 4 5 6 7 8
R S
1
S
2
Q R S
1
16 15 14 13 12 11 10 9
Vcc S
1 R Q S
1
S
2
R Q
GND Q
Fi g. 6.7 IC 74LS279, A Quad Set Reset Lat ch
Fr om t he figur e it is evident t hat t he IC cont ains 4
SR
lat ch shown ear lier in Fig. 6.5.
Two flip-flops have t wo input s, named S R
1
, ar e exact r epr oduct ion of
S R
lat ch shown in
Fig. 6.5. Remaining t wo flip-flops have t hr ee input s labelled
S S R,
1 2
, ,
in which inst ead of
single

S
input we get t wo set input s
S and S
1 2
. Since t he lat ches ar e const r uct ed by NAND
gat es a LOW eit her on
S
1
or on
S
2
will set t he lat ch. Tr ut h t able summar izing it s oper at ion
220 S witching Theory
is shown in Fig. 6.8. Not t hat making
R = 0
and eit her of
S and S
1 2
LOW, lea ds t o
indet er minat e st at e.
1
2
3
R
S
1
S
2
S
Set State
Reset state
Last State
Indeterminate
Indeterminate
Q
1
1
?
?
×
×
×
×
1 1
1
Q
1 1
0
0
R
S
2
S
1
Set State
Resulting State
1
1
0
0
0
0 0
0
Fi g. 6.8 Truth Table; ‘X’ → don’t car e Fig. 6.9 Convert ing
S and S
1 2
into S
Also if
S and S
1 2
ar e shor t ed (or t ied) t oget her, as shown in Fig. 6.9, t he t wo set input s
can be conver t ed int o single set input

S
.
When
S and S
1 2
ar e shor t ed t oget her, t he lat ch
exact ly becomes SR flip-flop of Fig. 6.5.
6.1.2 D Flip- Flop
The SR lat ch, we discussed ear lier, has t wo input s S and R. At any t ime t o st or e a bit ,
we must act ivat e bot h t he input s simult aneously. This may be t r oubling in some applicat ions.
Use of only one dat a line is convenient in such applicat ions.
Mor eover t he for bidden input combinat ion S = R = I may occur unint ent ionally, t hus
leading t he flip-flop t o indet er minat e st at e.
In or der t o deal such issues, SR flip-flop is fur t her modified as shown in Fig. 6.10. The
r esult ant lat ch is r efer r ed as D flip-flop or D lat ch. The lat ch has only one input labelled D
(called as Dat a input ). An ext er nal NAND gat e (connect ed as inver t er ) is used t o ensur e t hat
S and R input s ar e always complement t o each ot her. Thus t o st or e infor mat ion in t his lat ch,
only one signal has t o be gener at ed.
D Q
Q
(d) Logic Symbol
(b) Construction (a) Modification in S R Flip-Flop
R Q
S Q
E
D
A
C
D
B
Q
E
Q
D
Resulting State
Reset State or
Low State
Set State or
High State
1
Q
(c) Truth Table
0 0
1
D
Fig. 6.10 D Flip-flop or D lat ch
S ynchronous (Clocked) S equential Circuits 221
Oper at ion of t his flip-flop is st r aight for war d. At any inst ant of t ime t he out put Q is
same as D (i.e. Q = D). Since out put is exact ly same as t he input , t he lat ch may be viewed
as a delay unit . The flip-flop always t akes some t ime t o pr oduce out put , aft er t he input is
applied. This is called pr opagat ion delay. Thus it is said t hat t he infor mat ion pr esent at point
D (i.e. at input ) will t ake a t ime equal t o t he pr opagat ion delay t o r each t o Q. Hence t he
infor mat ion is delayed. For t his r eason it is oft en called as Delay (D) Flip-Flop. To under st and
t he oper at ion of t his lat ch, considr Fig. 6.10 (a).
As shown in figur e, t he D input goes dir ect ly t o S and it s complement is applied t o R
input . When dat a input is LOW i.e. D = 0, we get S = 0 and R = 1.50 flip-flop r eaches t o
RESET St at e wher e Q = 0. When D = 1 t he S input r eceives 1 and R = 0. Thus t he flip-
flop goes t o SET st at e, wher e Q = 1. This oper at ion is summar ized in t r ut h t able, shown
in Fig. 6.10 (c). It is int er est ing t o not e t hat t he next st at e of D flip-flop is independent of
pr esent st at e. It means t hat if input D = 1 t he next st at e will be SET st at e, weat her
pr esent ly it is in SET or RESET st at e.
Fur t her mor e, by Fig. 6.10 (a) it is clear t hat t he ext er nal inver t er ensur es t hat t he
for bidden condit ion S = R = 1 will never ar r ive. The D flip-flops ar e popular ly used as t he
delay devices and/or lat ches. In gener al, simply saying lat ch means a D flip-flop.
Example 6.2. A logic circuit having a single input labelled X, and two outputs Y
1
and
Y
2
is shown in fig. 6.11. Investigate the circuit and find out does this circuit represents a
latch? If yes, then name the latch and draw the truth table for this circuit.
Sol. To invest igat e t he cir cuit , we find out values of out put s Y
1
and Y
2
for each and
ever y possibilit y of input X.
A car efully inspect ion of cir cuit r eveals t hat t he por t ion of t he cir cuit which consist of
t wo NAND gat es A and B
A
C
B
S R Latch
Y
1
Y
2
X
S Q
R Q
C
X
Y
1
Y
2
Fi g. 6.11 Logic Cir cuit for Example 6.2 Fi g. 6.12 Simplified cir cuit for Fig. 6.11
represent SR flip-flop. This por t ion of t he cir cuit is sur r ounded by dot t ed lines in Fig. 6.11.
The cir cuit is r edr awn in Fig. 6.12 for simplicit y. This simplificat ion shows t hat input t o
S is X and input t o

R is X or S = X and R = X. The out put s Y
1
and Y
2
ar e not hing but t he
Q and Q
out put s SR lat ch i.e. Y
1
= Q and
Y = Q.
Thus t he out put s Y
1
and Y
2
ar e always
compliment ar y..
Hence when t he input X is LOW i.e. X = 0, it r esult s in S 1 = and R 0. = The lat ch is
for ced t o r eset st at e, in which case Q = 0 and
Q = 1,
consequent ly Y
1
= 0 and Y
2
= 1. Thus
for X = 0 we get Y
1
= 0 and Y
2
= 1. In t he similar way when X = 1,
S = 0
and
R = 1
making
Y
1
= 1 and Y
2
= 0 which is set st at e. We now summar ize t hese r esult s in a t r ut h t able shown
222 S witching Theory
in Fig. 6.13. Fr om t he t r ut h t able it is clear t hat Y
1
= X and
Y X
2
=
. Thus t he given cir cuit
r epr esent s a D Lat ch which gives Q = D and
Q = D.
In t he Figs. 6.11 and 6.12 t he input
D is r enamed as X and t he out put s
Q and Q
are named as Y
1
and Y
2
r espect ively.
X S R Q Q
Y = Q
1
0 0 0 0 1
1
1 1
0 1 1 0 1 0
Y = Q
2
(a)
1 1
1 0 0
0
X Y
2
Y
1
(b)
Fi g. 6.13 Truth Table for Fig. 6.12
In Fig. 6.12, if t he out put of gat e C is connect ed t o

R
and input X is dir ect ly connect ed
t o

S
t hen Y
1
(= Q)
= X and Y Q) X.
2
(= =
Ther efor e t he cir cuit may be r efer r ed as inver t ed
D lat ch.
6.1.3 C loc ke d Flip - Flop s
All t he flip-flops discussed ear lier ar e said t o be transparent, because any chance in
input is immediat ely accept ed and t he out put changes accor dingly. Since t hey consist of logic
gat es along wit h feedback t hey ar e also r egar ded as asynchronous fli p-flops.
However, oft en t her e ar e r equir ement s t o change t he st at e of flip-flop in synchr onism
wit h a t r ain of pulses, called as Clock. In fact we need a cont r ol signal t hr ough which a flip-
flop can be inst r uct ed t o r espond t o input or not . Use of clock can ser ve t his pur pose.
T
(b)
t
OFF
T
(a)
t
ON
t
ON
t
OFF
Fig. 6.14 Repr esent at ion of Pulse
A clock signal can be defined as a t r ain of pulses. Essent ially each pulse must have t wo
st at es, ON st at e and OFF st at e. Fig. 6.14 shows t wo alt er nat e r epr esent at ion of a pulse, and
Fig. 6.15 shows a clock signal. The clock pulses ar e char act er ized by t he duty cycle, which
is r epr esent at ive of ON t ime in t he t ot al t ime per iod of pulse, and is given as:
Dut y Cycle = D =
t
t t
t
ON
ON OFF
ON
or D
T +
=
In t he digit al syst ems we need a clock wit h dut y cycle D ≤ 50%. The OFF t ime of a
pulse is also r efer r ed as bi t-ti me . This is t he t ime in which flip-flop r emains unaffect ed in
eit her of t wo st able st at es. The st at e of lat ch dur ing t his t ime is due t o t he input signals
pr esent dur ing ON t ime of pulse.
St at e Q
n + 1
is due t o t he input s pr esent dur ing ON t ime of (n + 1)t h pulse i.e at
t = nT. In t he analysis and discussion we adopt t he designat ion Q
n
t o represent “present
state” which is t he st at e befor e t he ON t ime of (n + 1)t h pulse or st at e just befor e t he t ime
t = nT in Fig. 6.15, and Q
n + 1
as “next state” i.e. t he st at e just aft er t he ON t ime of
S ynchronous (Clocked) S equential Circuits 223
(n + 1)t h clock pulse. Thus Q
n
r epr esent s t he st at e (or out put ) in bit t ime n and Q
n + 1
r epr esent s t he out put Q in bit t ime n + 1, as shown in Fig. 6.15.
Bit-TIME
Bit-Time
n
n + 1
Qn+1
state
Qn
state
1 Bit-Time
3
1 Bit-Time
2
Bit-Time
1
1st Pulse
t
ON
t
OF F
t
OF F
t
ON t
ON
2nd Pulse
3rd Pulse
4th
nth Pulse
(n+1)th
Pulse
(n+2)th
Pulse
(n+3)th
Pulse
O T 2T 3T (n–1)T
nT
(n+1)T
(n+2)T
tim
High
Low
t
ON
t
ON
t
OF F
Fi g. 6.15 Clock Signal-Pulse Tr ain of Shape shown in Fig. 6.14 (b).
As we said ear lier, t he clock pulse can be used as a cont r ol signal. It allows t he flip-
flop t o r espond t o input s dur ing t
ON
per iod of clock, it is called enabli ng t he flip-flop. Wher e
as t he flip-flop is inst r uct ed, not t o r espond t o input s dur ing t
OFF
per iod of clock, i.e. flip-flop
maint ains it s out put irrespect ive of changes in input . This is called disabling t he flip-flop.
In t his way it is possible t o strobe or clock t he flip-flop in or der t o st or e t he infor mat ion
at any t ime said alt er nat ely clocking allow us t o select ively enable or disable t he flip-flop
which is a necessar y r equir ement in lar ge digit al syst ems.
Clocked SR Fli p-Flop: A simple way t o get a clocked SR flip-flop is t o AND t he input s
signals wit h clock and t hen apply t hem t o S and R input s of flip-flop as shown in fig. 6.16
(a). For t he simplicit y SET and RESET input s of unclocked SR lat ch ar e labelled S
1
and R
1
r espect ively. Wher e as ext er nal input s ar e labelled S and R.
S
1
Q
R
1
Q
G
1
G
2
S
CLK
R
CLK Qn Sn Rn
Q
n+1
Comments
0 0
0 0 0 0
0 0 0
0 0
0
0
1
1
1
1
1
1
1
1
1
1 1 ?
1 1 1
1
1
0
1 0 × × 1
0 × ×
?
0
1
1
0
0
1
1
1
1
1
Flip-Flop disabled no change
in state and last state maintained
Last State Qn+1=Qn
Reset state
Set state
Indeterminate
Last state Qn+1=Qn
Reset state
Set state
Indeterminate
(a) Construction of clocked Sr flip-flop. (b) Truth Table
(c) Chare terigtic Equation
S Q
R Q
CLK
(d) Logic Symbol
1
1
×
×
1 1
Q
n
0
00 11 01 10
Q =S +R Q
n+1 n n n
S R =0
n n
Q S R
n+1 n n
Fig. 6.16 Clocked RS (or SR) Flip-Flop
224 S witching Theory
When clock (abbr eviat ed as CLK) is LOW, out put s of gat es G
1
and G
2
ar e for ced t o 0,
which is applied t o flip-flop input s. Thus when CLK = 0, S
1
= 0 and R
1
= 0. Since bot h t he
input s ar e LOW, flip-flop r emain in it s pr evious st at e. Alt er nat ively if Q
n
= 0, Q
n + 1
= 0 and
if Q
n
= 1 we get Q
n + 1
= 1. Thus dur ing t
OFF
per iod input s have no effect on t he cir cuit . This
is shown in fir st t wo r ows of t r ut h t able given in Fig. 6.16 (b).
When clock is HIGH, gat es G
1
and G
2
ar e t r anspar ent and signals S and R can r each
t o flip-flop input s S
1
and R
1
. The next st at e will now be det er mined by t he values of S and
R. Thus dur ing t
ON
point CLK = 1 causing S
1
= S and R
1
= R and t he cir cuit behaves exact ly
same as t he nor mal flip-flop discussed in subsect ion 6.11, as shown by r est of t he r ows of
t r ut h t able.
Not e t hat in t r ut h t able, input s ar e labelled S
n
, R
n
. They r epr esent t he value of input s
dur ing bit -t ime ‘n’ at t he t
ON
t ime of (n + 1)t h pulse or at t = nT in Fig. 6.15. The out put
also is Q
n + 1
not simply Q. Because pr esence of clock pulses for ce us t o consider t wo differ ent
inst ant s of t ime : t he t ime befor e applicat ion of pulse, Q
n
(i .e. present state) and t he t ime
aft er t he applicat ion of pulse, Q
n + 1
(i .e. next state).
Char act er ist ic equat ion for t his flip-flop is obt ained fr om K-map shown in Fig. 6.16 (c),
which is an algebr ic expr essions for t he binar y infor mat ion of t he t r ut h t able. This expr ession
gives t he value of next st at e as a funct ion of pr esent st at e and pr esent input s. The
indet er minat e condit ions ar e mar ked “X”-don’t car e in t he map because, depending upon t he
pr opagat ion delay of logic gat es, st at e can be eit her 1 or 0. Inclusion of r elat ion S
n
.R
n
= 0
as a par t of char act er ist ics equat ion is due t o t he r equir ement t hat bot h S
n
and R
n
must not
be made 1 simult aneously.
Finally, t he logic symbol of clocked SR flip-flop is shown in Fig. 6.16 (d), which now has
t hr ee input s named S, R and CLK.
(a)
Q
Q
S
R
CLK
Q
Q
S
R
CLK
(b)
Fi g. 6.17 Two Differ ent Realizat ions of Clocked SR Flip-Flop.
Figur e 6.17 shows t wo alt er nat e r ealizat ions of clocked SR flip-flop. Bot h t he r ealizat ions ar e
popular ly used in MSI and LSI (Medium and Lar ge Scale Int egr at ed) cir cuit s. In many t ext s
t he signal CLOCK is also labelled ENABLE or EN.
Example 6.3. Fig. 6.18 (a) shows the input waveforms S , R and CLK, applied to clocked
S R flip-flop. Obtain the output waveform Q and explain it in brief. Assume flip-flop is resent
initially.
Sol. The r esult ing wavefor m at t he out put Q is shown in Fig. 6.18 (b). To under st and
t he out put wavefor m, r ecall t hat t he input s affect t he flip-flop only when t he clock = 1
ot her wise flip-flop maint ains it s pr evious out put ir r espect ive of pr esent input .
Init ially at t = 0 flip-flop is r eset i.e. Q = 0. At t his t ime S = 1 and R = 0, but flip-flop
r emains unaffect ed since CLK = 0.
S ynchronous (Clocked) S equential Circuits 225
(b) Resultant output waveforms
0
1
t
1 t
2
t
3
t
4
t
5
t
6
t
8
t
7
t
9 t
10
t
11
CLK
0
1
1
0
R
S
Q
1
0
t
(a) Given Inputs and Clock Waveforms
Fi g. 6.18 Wavefor ms for Example 6.3
At t
1
clock goes HIGH and out put also goes HIGH i.e. Q = 1 since S = 1 and R = 0
at t his t ime. At t ime t
2
CLK = 0 and flip-flop r emain SET unt ill t
3
, ir r espect ive of changes
in S and R.
At t ime t = t
3
CLK = 1 and because S = 0 and R = 1 at t his inst ant , we get Q = 0. At
t
4
bot h input s ar e LOW while clock is st ill HIGH. Since S = R = 0 at t his inst ant flip-flop
r emains r eset unt ill just aft er t ime t
5
.
Just aft er t
5
S goes HIGH making Q = 1. At time t
6
clock swit ches t o LOW st at e. J ust
before t his HIGH t o LOW t ransit ion of clock S = 1 and R = 0 and Q = 1. Thus flip-flop remains
set untill t
7
. Changes in R and S does not affect flip-flop during t
6
to t
7
as CLK = 0.
At t = t
7
clock goes HIGH, at which t ime R = 1 and S = 0. So flip-flop ent er s in r eset
st at e. Q = 0 is r et ained unt ill t
8
wher e R swit ches t o 0 and S swit ches t o 1. Ther efor e
Q = 1 at t his t ime.
Clock goes LOW at t
9
and since Q = 1 just befor e clock goes LOW, flip-flop r emains set
untill t
10
wher e clock goes HIGH again. The input s S and R changes dur ing t ime bet ween
t
9
to t
10
, but can not affect t he out put since CLK = 0.
At t = t
10
clock goes HIGH and since R = 1 and S = 0 at t
10
, t he flip-flop at t ains r eset
st at e. At t he t ime t = t
11
clock goes LOW and st ill R = 1 and S = 0 was maint ained at t he
input , t he flip-flop r emains in LOW st at e beyond t
11
.
C loc ke d SR Flip - flop with C le a r a nd Pre se t
When t he power is fir st applied t o t he flip-flop, it come up in r andom st at e i.e. st at e
of cir cuit is uncer t ain. It may be in SET st at e or in RESET st at e. This is highly undesir ed
in major it y of applicat ion. Ther e ar e r equir ement s t hat t he flip-flop must be in a par t icular
st at e befor e t he act ual oper at ion begins. In pr act ice it may be r equir ed t o pr eset (Q = 1) or
226 S witching Theory
clear (Q = 0) t he flip-flop t o st ar t t he oper at ion. In flip-flops such pr ovisions can easily be
pr ovided for t his pur pose.
(a) Construction
S
R
Q
Q
R
CLK
S
P (Preset)
R
CLR(Clear)
CLK CLK
P
R
Out-
Put Q
0
0
0
0 0
0
0
?
Q
n+1
1
1
1
0 1
1
1
Resulting State
Clear or Reset
Preset or Set
Indeterminate
Normal Flip-Flop
Next state is due
to S R inputs:
(b) Truth table
S
CLK
R
P
R
CLR
Q
(c) Logic Symbol
Q
Fig. 6.19 SR Flip-Flop wit h ‘CLEAR’ and ‘PRESET’
Q
Q
S
R
CLK
P
R
CLR
S
CLK
R
P
R
CLR
(c) Logic Symbol
Q
Q
(a) Construction
(b) Truth Table
CLK CLR
P
R
Out-
Put Q
0
0
0
1 1
0
?
Q
n+1
1
0
10
1 0
0
1
Resulting State
Clear
Preset or Set
Indeterminate
Normal Flip-Flop
Next state is
determined
by S R inputs:
1
Fi g. 6.20 Alt er nat e Realizat ion of ‘CLEAR’ and ‘PRESET’ wit h SR Flip-Flop
S ynchronous (Clocked) S equential Circuits 227
Two differ ent r ealizat ions t o accommodat e a pr eset (abbr eviat ed as P
R
) and a clear
(abbr eviat ed as CLR) input s ar e shown in Figs. 6.19 and 6.20. The P
R
and CLR ar e dir ect
input s and ar e called asynchronous i nputs; as t hey don’t need t he clock t o oper at e. Bot h
of t he above cir cuit s r equir e t hat P
R
and CLR input s should be applied only in absence of
clock ot her wise unexpect ed behaviour can be obser ved. Mor e over bot h P
R
and CLR should
not asser t ed at same t ime as it leads t o indet er minat e st at e. Logic values t o be applied t o
pr eset and clear ar e accommodat ed in t he t r ut h t ables. Befor e st ar t ing nor mal clocked
oper at ion t he t wo dir ect input s must be connect ed t o a fix value as shown by t he last ent r ies
of cor r esponding t r ut h t ables. The logic symbols for t he t wo cir cuit s ar e also shown in t he
figur e.
In Fig. 6.19, due t o t he const r uct ion of cir cuit t he flip-flop can be pr eset or clear on
t he applicat ion of Logic 1 at P
R
or CLR r espect ively. In cont r ast , r ealizat ion shown in fig.
6.20 demands a Logic 0 t o be applied at t he par t icular asynchr onous input , in or der t o
per for m t he int ended oper at ion. For nor mal oper at ion t hese input s must be connect ed t o
Logic 1, as indicat ed by t he last r ow of t r ut h t able shown in Fig. 6.20 (b). Similar ly in fig.
6.19 t he P
R
and CLR must be connect ed t o Logic 0 t o obt ain nor mal flip-flop oper at ion.
The cir cuit s pr oposed in Figs. 6.19 and 6.20 r equir es t hat t he P
R
and CLR should only
be applied when clock is LOW. This imposes a r est r ict ion t o use t hese t wo signals. An
impr ovement may be consider ed t o r emove t his r est r ict ion.
Fig. 6.21 shows a clocked SR flip-flop wit h pr eset and clear
(P and CLR
R
)
input s t hat
can over r ide t he clock.
P and CLR
R
can be safely applied at any inst ant of t ime weat her
clock is pr esent or not .
CLK
CLR P
R
Out-
Put Q
Resulting State
0 0 1 Clear
0
0 0
1 1 1
Normal Flip-Flop
Next state is
determined by
S and R Inputs.
Indeterminate
Preset
?
Q
n+1
1 1
(b) Truth Table
×
×
×
Q
Q
R
CLK
P
R
CLR
E
A
C
D
B F
S
(a) Construction
Fi g. 6.21 SR Flip-Flop wit h Clock Override ‘Clear’ and ‘Pr eset ’
As shown in figur e t wo AND gat es, E and F, ar e used t o accommodat e pr eset (P )
R

and
Clear
(CLR)

input s. The t r ut h t able summar ies t he effect of t hese asynchr onous input s in t he
cir cuit . Out put Q is pr ovided t hr ough gat e E wher eas
Q
is out put of gat e F. Bot h
P
R and
CLR
ar e act ive LOW signals i.e. asser t ing Logic ‘0’ at t hese input s per for m t he int ended oper at ion.
Accor ding t o fir st r ow of t r ut h t able when CLR = 0 and
P
R
= 1
is applied t hen ir r espect ive
of t he value of S, R and CLK, out put of gat e E is 0. Thus Q = 0 and it is feeded t o t he input
of NAND gat e B. So out put of NAND-B is 1 which is applied t o t he input of gat e F. Since
we applied
P
R
= 1,
bot h t he input s t o AND gat e F ar e HIGH. Consequent ly t he out put of gat e
228 S witching Theory
F goes HIGH, which is available at
Q
out put of flip-flop. Hence when
PR = 1
and
CLR = 0
is applied, we get Q = 0, and
Q = 1
. This is fr equent ly called as clearing t he flip-flop.
Similar ly when
PR = 0
and
CLR = 1
is applied, out put of gat e F, which is
Q,
goes LOW
i.e.
Q = 0
. This for ces t he gat e-A t o give HIGH out put . Since
CLR = 1
is alr eady pr esent ,
out put of gat e E, which is Q, goes HIGH. Thus when
P R = 0
and
CLR = 1
is applied we get
Q = 1 and
Q = 0
, which is r equir ed st at e. This is r efer r ed as pr eset t ing.
Since bot h PR and CLR ar e act ive LOW input s, t hey must be connect ed t o Logic 1, in
or der t o obt ain nor mal flip-flop oper at ion as shown by four t h r ow of t r ut h t able. Also making
both PR and CLR LOW is for bidden as it r esult s in indet er minat e st at e, for t he similar
r easons explained ear lier.
C loc ke d D Flip - Flop
In subsect ion 6.1.2 we obt ained a D flip-flop by using an ext er nal inver t er pr esent at
t he input of SR lat ch as shown in Fig. 6.10 (a). In t he similar way a clocked D flip-flop is
obt ained by using an ext er nal inver t er at t he input of clocked SR flip-flop. The clocked D
flip-flop is shown below in Fig. 6.22. Not e t hat unclocked RS lat ch of Fig. 6.10 (a) is r eplaced
by a clocked RS flip-flop shown in Fig. 6.16 (d).
S Q
R Q
CLK
(a) Modification in clocked
S R Flip-Flop
(b) Construction
Q
Q
R
CLK
E
D
C A
B
D
1
0
0
1 1
(c) Truth Table
×
CLK
1 1 1
1
0 0
1 1 1
1
0
0 0 ×
0
1
Set State
Comments
Flip-Flop
Disabled
last state
Maintained
Rest State
Set State
Reset State
Q
n+1
Q
n
D
n
1
1
0
0
1
Q
n
Q
n+1
D
n
1
Q =D
n+1 n
CLK
D Q
Q
(d) Characteristic (e) Logic Symbol
D
0 0
Fig. 6.22 Clocked D Flip-Flop Equat ion
The char act er ist ics equat ion is der ived fr om K-map shown in Fig. 6.22 (d), which
specifies t hat ir r espect ive of pr evious st at e next st at e will be same as t he dat a input . In
t r ut h t able D
n
r epr esent s t he dat a input at t he t
ON
t ime of nt h pulse.
S ynchronous (Clocked) S equential Circuits 229
The oper at ion of clocked D flip-flop is same as explained in subsect ion 6.1.2, when
CLK = 1. When CLK = 0, t he D input has no effect on t he flip-flop and t he pr esent st at e
is maint ained. This is evident by t he fir st t wo r ows of t r ut h t able. The Logic symbol of
clocked D flip-flop is shown in Fig. 6.22 (e).
Similar t o clocked SR flip-flops, t he clocked D flip-flop may also be accommodat ed
wit h t he asynchr onous input s “pr eset ” and “clear ”. One par t icular r ealizat ion is shown in
Fig. 6.23. An alt er nat ive ar r angement t o obt ain a D flip-flop, dir ect ly fr om SR flip-flop wit h
clear and pr eset is shown in Fig. 6.24.
(a) Construction
S
R
Q
Q
CLK
D
P
R
CLR
D
CLK
P
R
CLR
Q
Q
(b) Logic Symbol
Fig. 6.23 D Flip-Flop wit h Clear and Pr eset
(b) Logic Symbol
D
CLK
P
R
CLR
Q
Q
(a) Modification in S R Flip-Flop
CLK
P
R
CLR
Q
Q S
R
D
Fi g. 6.24 Alt er nat e Realizat ion of Clear and Pr eset in D Flip-Flop
On compar ing Fig. 6.23 (a) wit h Fig. 6.19 (a), we find t hat bot h t he cir cuit s ar e same
except t hat , in t wo ext er nal input s ar e connect ed t oget her t hr ough an inver t er placed
bet ween t hem. Thus bot h t he cir cuit s behave similar ly and explanat ion of Fig. 6.19 (a) is
equally valid in t his case. Similar ly, t he ar r angement shown in Fig. 6.24 (a) is built upon
t he clock SR flip-flop shown in Fig. 6.20 (c).
Example 6.4. In a certain digital application it is required to connect an S R flip-flop
as toggle switch, which changes its state every time when clock pulse hits the system. S how
the arrangement and explain in brief how it works as a toggle switch.
Sol. SR flip-flop can be connect ed as a t oggle swit ch as shown in Fig. 6.25. On t he
ar r ival of CLOCK pulse t his ar r angement for ces t he flip-flop eit her t o go t o SET st at e if
cur r ent ly it is RESET or t o RESET st at e if cur r ent ly it is SET.
As shown, a feedback pat h connect s t he out put Q t o R input while anot her feedback
pat h connect s t he
Q
t o input S. Recall t hat t he st at e of flip-flop can be changed only when
t he CLK = 1 and t he last st at e r eached, is maint ained while CLK = 0.
230 S witching Theory
CRK
S
R
Q
Q
Fi g. 6.25 SR Flip-Flop Connect ed as Toggle Swit ch
To st ar t let t he flip-flop is init ially r eset , i.e. Q = 0 and
Q = 1
. Same t ime due t o t he
feedback, applied input s ar e S = 1 and R = 0 because S = Q and R = Q.
As soon as t he clock goes HIGH flip-flop ent er s int o SET st at e i.e. Q = 1 and
Q = 0.
Thus t he input s would be
S = Q = 0
and R = Q = 1 because of feedback pat h and r emain
unchanged unt ill t he next clock pulse ar r ives.
The moment clock goes HIGH again, flip-flop changes it s st at e and at t ains RESET st at e
where Q = 0 and
Q = 1.
Again t hr ough t he feedback input s become R = 0 and S = 1. Not e
t hat t his is t he init ial st at e we assumed in beginning. Thus aft er t he ar r ival of t wo successive
clock pulses, t he swit ch has r et ur ned t o it s init ial st at e Q = 0 and
Q = 1.
Ther efor e, t he swit ch shown in Fig. 6.25 t oggle bet ween t he t wo st at es wit h clock.
Mor eover t he swit ch r epr oduces it s st at e (eit her Q = 0 or Q = 1) aft er t wo successive clock
pulses has ar r ived. This does mean t hat it r eally does not mat t er weat her t he init ially
assumed st at e is Q = 0 or Q = 1.
In pr act ice t he feedback pat hs in Fig. 6.25 may lead t o uncer t aint y of t he st at e. In t he
above par agr aphs we assumed t hat t he input s available at S and R do not change dur ing t he
t
ON
per iod of clock. Thus t he change in st at e can occur only once in a single clock pulse,
which is not t r ue. If t he pr opagat ion delay (t
P
) of t he flip-flop is smaller t han t he t
ON
t ime,
mult iple t r ansit ions (or st at e changes mor e t han once) can be obser ved in a single clock
pulse. Hence at t he end of clock pulse t he st at e of flip-flop is uncer t ain. This sit uat ion is
referred as race-around condi ti on.
Race ar ound has r esult ed because t he flip-flop r emains t r anspar ent as long as CLK =
1 (or for ent ir e t
ON
t ime). At t his point we r efr ain our selves fr om discussing it fur t her. We
addr ess t he complet e discussion on it , only aft er examining and ident ifying t he similar
sit uat ions in var ious flip-flops.
Example 6.5. Realize a toggle switch, that changes its state on the arrival of clock, by
using a D flip-flop. Explain its operation briefly.
S ynchronous (Clocked) S equential Circuits 231
Sol. Fig. 6.26 shows a D flip-flop configur ed t o wor k as t oggle swit ch when clock is
applied.
CLK
Q
Q
D
Fi g. 6.26 D Flip-Flop as Toggle Swit ch
As shown t he out put
Q
is connect ed t o D via a feedback pat h, so t hat
D = Q
always. To
under st and t he oper at ion r ecall t hat “in a D flip-flop out put at any inst ant of t ime, pr ovided
CLK = 1, is same as input .” So Q = D always, if CLK = 1. Furt hermore out put Q = D, so
t hr ough t he feedback pat h complement of dat a D is now feeded t o input . Thus if init ially t he
flip-flop was r eset (Q = 0) t he
Q = 1
is applied t o input t hr ough t he feedback pat h. Consequent ly
D = 1 will be r et ained unt ill next clock pulse ar r ive. As soon as CLK = 1, D = 1 affect s t he
circuit . This result s in change in st at e of flip-flop giving Q = D = 1 and
Q = 0
at t he out put .
But at t he same t ime
Q
is feeded t o D input due t o which input changes t o D = Q = 0. On
t he arrival of next clock pulse t he circuit t oggles again and change it s st at e in similar way.
It is evident again fr om Fig. 6.26 t hat even t his swit ch also, suffer s fr om t he “r ace
ar ound” pr oblem, explained in example 6.4. The pr oblem is a consequence of t he feedback
pat h pr esent bet ween
Q
and D. The ouput of t his swit ch r aces for t he same r easons as was
given for SR flip-flop in example 6.4.
6.1.4 Trigge ring of Flip Flops
By a moment ar ily change in t he input signal t he st at e of a flip-flop is swit ched. (0-1-
0). This moment ar ily change in t he input signal is called a t r igger. Ther e ar e t wo t ypes by
which flip-flops can be t r igger ed.
Edge t r igger
Level (pulse) t r igger
An edge-t r igger ed flip-flop r esponds only dur ing a clock pulse t r ansit ion i.e. clock pulses
swit ches fr om one level (r efer ence volt age) t o anot her. In t his t ype of flip-flops, out put
t r ansit ions occur at a specific level of t he clock pulse. When t he pulse input level exceeds
t his r efer ence level, t he input s ar e locked out and flip-flop is t her efor e unr esponsive t o
fur t her changes in input s unt il t he clock pulse r et ur ns t o 0 and anot her clock pulse occur s.
An edge-t r igger ed flip-flop changes st at es eit her at t he posit ive edge (r ising edge) or at t he
negat ive edge (falling edge) of t he clock pulse on t he cont r ol input .
When t he t r igger ing occur s on t he posit ive going edge of t he clock, it is called posit ive
edge t r igger ing and when t he t r igger ing occur s at t he t r ailing edge of t he clock t his is called
as negat ive edge t r igger ing.
232 S witching Theory
The t er m pulse-t r igger ed or level t r igger ed means t hat dat a ar e ent er ed int o flip-flop
on t he r ising edge of t he clock pulse, but t he out put does not r eflect t he input st at e unt il
t he falling edge of t he clock pulse. As t his kind of flip-flops ar e sensit ive t o any change of
t he input levels dur ing t he clock pulse is st ill HIGH, t he input s must be set up pr ior t o t he
clock pulse’s r ising edge and must not be changed befor e t he falling edge. Ot her wise,
ambiguous r esult s will happen.
6.1.5 JK a nd T Flip - Flop s
Pr oblem of SR flip-flop t o lead t o indet er minat e st at e when S = R = 1, is eliminat ed
in J K flip-flops. A simple r ealizat ion of J K flip-flop by modifying t he SR t ype is shown in Fig.
6.27 (a). In J K t he indet er minat e st at e of SR flip-flop is now modified and is defined as
TOGGLED STATE (i.e. it s own complement st at e) when bot h t he input s ar e HIGH. Table
shown in Fig. 6.27 (b), summar izes t he oper at ion of J K flip-flop for all t ypes of input
possibilit ies. Char act er ist ic equat ion in Fig. 6.27 (c) is der ived fr om K-Map, filled by t he dat a
pr ovided by t r ut h t able.
Tr ut h t able shows t he input applied fr om ext er nal wor ld (J and K). It also shows t he
flip-flop input s S and R and t he whose values ar e due t o t he modificat ion and in accor dance
wit h t he values of J and K. Input signal J is for Set and K is for RESET. Bot h J and K ar e
ANDED wit h
Q
and Q r espect ively t o gener at e appr opr iat e signal for S and R. Since Q and
Q
ar e always complement ar y, only one of t he AND gat es (Fig. 6.27 (a)) is enable at a t ime.
So eit her only J or only K can r each t o one of S and R input s, t hus any one of input s will
r eceive t he dat a t o be st or ed. While t he ot her AND gat e is disabled i.e. it s out put is 0, t hus
second input of SR flip-flop will always be 0. Thus indet er minat e st at e never occur s even
when bot h J and K input s ar e HIGH.
Q
Q
S
CLK
R
J
K KQ
JQ
(a) Realization of JK
Flip-Flop from SR Flip-Flop
1 1
1 1 1
01 11 10
00
0
Q
n
Q
n+1
J K
n n
Q =J .Q +K Q
n+1 n n n n
(c) Characteristic Equation
CLO
CK
Present
State
External
Inputs
Flip-Flop
Inputs
Output or
Next state
1
1 1 1 1 1 0 0 0
1 1 1 1 1 1 0
1 1 0 1 0 0 0 1
1 1 1 1 1
1 1 1 1 0 0 0 0
0 0 1 0 0 0 × ×
0
1
0 × × 0 0
1
1 0 1
0
0 0 0 0
0 0
0
0 0 1 1 1
1 1 0 0 0
0
0 0
Q
n
Q
n+1
CLK
Q
n
Q
n
J
n
K
n
S
n
R
n
Q
n
Q
n
1
Resulting
state
Flip-Flop Disa-
bled for CLK=0,
no change
No change at
output. Present
state becomes
next state
Reset state
Set State
Toggled state
next state is
complement
of present state
0
0 0 0
(b) Detailed truth table
Fig. 6.27 J K Flip-Flop Thr ough SR Flip-Flop
S ynchronous (Clocked) S equential Circuits 233
(b) Logic Symbol
CLK
Q
Q K
J
(a) Construction
Q
Q
J
CLK
KQ
JQ
K
Fig. 6.28 Clocked J K Flip-Flop
(a) Construction
Q
Q
CLK
KQ
JQ
J
K
CLR
P
R
CLK
Q
Q K
J
CLR
P
R
(b) Logic Symbol
Fi g. 6.29 J K Flip-Flop wit h Act ive LOW Pr eset and Clear
As an example assume t hat init ially Q
n
= 0,
Q 1
n
=
and input s applied ar e J = 1 and
K = 0. So we get S
n
= J. Q 1
n
=
and R
n
= K. Q
n
= 0. Applicat ion of S = 1 and R = 0, when
clock ar r ives, swit ches t he st at e of flip-flop HIGH. Now if we assume Q
n
= 1.
Q 0
n
=
wit h
same J and K, input s r esult in S
n
= J
n
.
Q 0
n
=
and R
n
= K
n
Q
n
= 0 applied t o SR Flip-flop. When
bot h t he S and R input s ar e LOW flip-flop does not under go any change of st at e. So Q
n +1
= Q
n
= 1. These t wo input s ar e shown in 7t h and 8t h r ow of t r ut h t able. In t he similar way
ent r ies in ot her r ows of t r ut h t able can be ver ified.
Not e t hat when bot h input s are HIGH (i.e. J = 1 and K = 1) t hen, in Fig. 6.27 (a), we find
t hat now S = J = Q and R = K = Q. Thus it is evident t hat t he t wo ext ernal AND gat es become
full t ransparent and circuit may be viewed as if
Q
is connect ed t o S input and Q connect ed t o
R input . Thus at J = K = 1 flip-flop behaves as an SR t oggle swit ch shown in Fig. 6.25.
Note : Asynchronous input s
P and CLR
R
must not be act ivat e when clock is pr esent ,
ot her wise unexpect ed behaviour may be obser ved. Hence all t he discussions pr esent ed in
example 6.4 for t oggle swit ch is equally valid for J K flip-flop when bot h J and K ar e HIGH.
Furt hermore, when J = K = 1 t hen due t o t he t wo feedback pat hs t he out put may st art
racing around t he input s causing mult iple t ransit ions. Thus “Race Around” condit ion may
occur in J K flip-flop when bot h input s are HIGH, for t he similar reasons given in example 6.4.
Two gat e level const r uct ions for t he J K flip-flop is shown in Fig. 6.28 (a) and 6.29 (a)
along wit h t heir logic symbols shown in figur e (b) in each figur es.
234 S witching Theory
1 1 1 0 0
0 0 ×
× 1
0 0 0 0
0 0
0
0 1 1
1
Q
n
Q
n+1
Q
n
T
n
J
n
K
n
Q
n
Resul ting
state
Fli p-Flop Disa-
bl ed for CLK=0,
no change next
state=present
Toggl ed state or
compl emented
state next state
=present state
Next state
Out-put
Applied Inputs
Present
States
CLK
Maintain Out-put
state no change
in out-put next
state=present state
0 1 × ×
0
Q
n
1 0 × ×
1 0 1
1
1 1 0 1 1 1
1 1
Q
n
(d) Construction with active
low clear & preset
Q
Q
CLK
TQ
TQ
CLR
P
R
CLK
Q
Q
T
CLR
P
R
(e) Logic Symbol
1
1
1 0
0
1
Q
n+1
T
n
Q =T Q +T Q
n+1 n n n n
(c) Characteristic
Equation
CLK
Q
Q
J
(a) Realization of T
Flip-Flop from J K
K
(b) Detailed truth table
T
T
Fi g. 6.30 Clocked T (Toggles) Flip-Flop wit h Act ive LOW Asynchr onous Input s
The J K flip-flops ar e ver y popular as indet er minat e st at e (as pr esent in SR t ype) does
not exist . Fur t her mor e, due t o t he t oggling capabilit y, when bot h input s HIGH, on each
ar r ival of pulse, it for ms t he basic element for count er s. For t his pur pose J K flip-flop is
fur t her modified t o pr ovide a T flip-flop as shown in Fig. 6.30.
T flip-flop is a single input ver sion of J K flip-flop, in which t he input s J and K ar e
connect ed t oget her, as shown , and is pr ovided as a single input labelled as T. The oper at ion
is st r aight for war d and easy, and summar ized in t r ut h-t able given in Fig. 6.30 (b), while
char act er ist ic equat ion is der ived in Fig. 6.30 (c).
When t he clock is absent , t he flip-flop is disable as usual and pr eviously lat ched out put
is maint ained at out put . When t he clock is pr esent and T = 0, even t hough flip-flop is enabled
t he out put does not swit ch it s st at e. It happens so because for T = 0 we get J = K = 0 and t hus
next st at e is same as pr esent st at e. Thus if eit her CLK = 0 or T = 0, st at e does not change
next st at e is always same as pr esent st at e.
When T = 1 dur ing CLK = 1, it causes J = K = 1 and as ear lier discussed it will t oggle
t he out put st at e. Thus when input T is HIGH, flip-flop t oggles it s out put on t he ar r ival of
clock, and for t his r eason input T is called as t he Toggle Input . Essent ially t he T flip-flop
also, suffer fr om r ace ar ound condit ion, (when input is HIGH) and t hus causing mult iple
t r ansit ion at out put due t o same r easons given in example 6.4.
S ynchronous (Clocked) S equential Circuits 235
If t he r ace ar ound pr oblem is some how eliminat ed t hen T flip-flop can be used as
fr equency divider cir cuit . To obt ain such oper at ion input T is per manent ly made HIGH and
t he fr equency t o be divided is applied CLK input s. At t he out put s Q and
Q
we r eceive a
squar e wave whose t ime per iod is now doubled due t o which fr equency r educes t o half of
t he input fr equency. Not e t hat Q and
Q
gener at e squar e waves complement ar y t o each
ot her.
6.1.6 Ra c e Around C ond ition a nd Solution
Whenever t he widt h of t he t r igger pulse is gr eat er t han t he pr opagat ion t ime of t he
flip-flop, t hen flip-flop cont inues t o t oggle 1-0-1-0 unt il t he pulse t ur ns 0. When t he pulse
t ur ns 0, unpr edict able out put may r esult i.e. we don’t know in what st at e t he out put is
whet her 0 or 1. This is called r ace ar ound condit ion.
In level-t r igger ed flip-flop cir cuit s, t he cir cuit s is always act ive when t he clock signal
is high, and consequent ly unpr edict able out put may r esult . For example, dur ing t his act ive
clock per iod, t he out put of a T-FF may t oggle cont inuously. The out put at t he end of t he
act ive per iod is t her efor e unpr edict able. To over come t his pr oblem, edge-triggered cir cuit s
can be used whose out put is det er mined by t he edge, inst ead of t he level, of t he clock signal,
for example, t he r ising (or t r ailing) edge.
Anot her way t o r esolve t he pr oblem is t he Mast er -Slave cir cuit shown below:
Feedback
Inputs
Clock
Clock
Master
FF
Slave
FF
Q
Q
The oper at ion of a Mast er -Slave FF has t wo phases:
• Dur ing t he high per iod of t he clock, t he mast er FF is act ive, t aking bot h input s and
feedback fr om t he slave FF. The slave FF is de-act ivat ed dur ing t his per iod by t he
negat ion of t he clock so t hat t he new out put of t he mast er FF won’t effect it .
• Dur ing t he low per iod of t he clock, t he mast er FF is deact ivat ed while t he slave
FF is act ive. The out put of t he mast er FF can now t r igger t he slave FF t o pr oper ly
set it s out put . However, t his out put will not effect t he mast er FF t hr ough t he
feedback as it is not act ive.
Clock
T
Q
Clock
T
Q
?
236 S witching Theory
It is seen t hat t he t r ailing edge of t he clock signal will t r igger t he change of t he out put
of t he Mast er-Slave FF. The logic diagr am for a basic mast er-slave S-R flip-flop is shown
below.
S
Clock
R
Master
Q
Q′
Flip-flops ar e gener ally used for st or ing binar y infor mat ion. One bit of infor mat ion can
be wr it t en int o a flip-flop, and lat er r ead out fr om it . If a mast er -slave FF is used, bot h r ead
and wr it e oper at ions can t ake place dur ing t he same clock cycle under t he cont r ol of t wo
cont rol signals read and wri te,
• Dur ing t he fir st half of clock cycle : clock = read = wri te = 1, t he old cont ent in
slave-FF is r ead out , while t he new cont ent is being wr it t en int o mast er -FF at t he
same t ime.,
• Dur ing t he second half of clock cycle : clock = read = wri te = 0, t he new cont ent
in mast er-FF is wr it t en int o slave-FF.
MS-D-FF
Data-in
Write
Clock
M S Read
Data-out
6.1.7 O p e ra ting C ha ra c te ristic s of Flip - flop s
The oper at ion char act er ist ics specify t he per for mance, oper at ing r equir ement s, and
oper at ing limit at ions of t he cir cuit s. The oper at ion char act er ist ics ment ions her e apply t o
all flip-flops r egar dless of t he par t icular for m of t he cir cuit .
Propagation Delay Time—is t he int er val of t ime r equir ed aft er an input signal has been
applied for t he r esult ing out put change t o occur.
Set-up Time—is t he minimum int er val r equir ed for t he logic levels t o be maint ained
const ant ly on t he input s (J and K, or S and R, or D) pr ior t o t he t r igger ing edge of t he clock
pulse in or der for t he levels t o be r eliably clocked int o t he flip-flop.
Hold Time—is t he minimum int er val r equir ed for t he logic levels t o r emain on t he
input s aft er t he t r igger ing edge of t he clock pulse in or der for t he levels t o be r eliably
clocked int o t he flip-flop.
Maximum Clock Frequency—is t he highest r at e t hat a flip-flop can be r eliably t r igger ed.
S ynchronous (Clocked) S equential Circuits 237
Power Dissipation—is t he t ot al power consumpt ion of t he device.
Pulse Widths—ar e t he minimum pulse widt hs specified by t he manufact ur er for t he
Clock, SET and CLEAR input s.
6.1.8 Flip - Flop Ap p lic a tions
Fre q ue nc y Divisio n
When a pulse wavefor m is applied t o t he clock input of a J -K flip-flop t hat is connect ed
t o t oggle, t he Q out put is a squar e wave wit h half t he fr equency of t he clock input . If mor e
flip-flops ar e connect ed t oget her as shown in t he figur e below, fur t her division of t he clock
fr equency can be achieved.
HIGH
CLK
J Q
K Q
Q
0
PR
CLR
J Q
K Q
Q
1
PR
CLR
Q
0
Q
1
CLK
1
0
1
0
1
0
The Q out put of t he second flip-flop is one-four t h t he fr equency of t he or iginal clock
input . This is because t he fr equency of t he clock is divided by 2 by t he fir st flip-flop, t hen
divided by 2 again by t he second flip-flop. If mor e flip-flops ar e connect ed t his way, t he
fr equency division would be 2 t o t he power n, where n is t he number of flip-flops.
Pa ra lle l Da ta Stora g e
In digit al syst ems, dat a ar e nor mally
st ored in groups of bit s t hat represent numbers,
codes, or ot her infor mat ion. So, it is common
t o t ake sever al bit s of dat a on par allel lines
and st or e t hem simult aneously in a gr oup of
flip-flops. This oper at ion is illust r at ed in t he
figur e below.
Each of t he t hr ee par allel dat a lines is
connect ed t o t he D input of a flip-flop. Since
all t he clock input s ar e connect ed t o t he same
clock, t he dat a on t he D input s ar e st or ed
simult aneously by t he flip-flops on t he posit ive
edge of t he clock.
D Q
PR
CLR
Q
D
0
Q
0
D Q
PR
CLR
Q
D
1
Q
1
D Q
PR
CLR
Q
D
2
Q
2
Clock
238 S witching Theory
Anot her ver y impor t ant applicat ion of flip-flops is in digit al count er s, which ar e cover ed
in det ail in t he chapt er 7. A count er t hat count s fr om 0 t o 2 is illust r at ed in t he t iming
diagr am given below. The t wo-bit binar y sequence r epeat s ever y four clock pulses. When it
count s t o 3, it r ecycles back t o 0 t o begin t he sequence again.
PR
J Q
K Q
CLK
HIGH
CLR
PR
J Q
K Q
HIGH
CLR
1
0
1
0
1
0
1 2 3 4 5
0 1 0 1
0 0 1 1
0 1 2 3 0
Q
0
Q
1
Q
0
Q
1
CLK
6.2 FLIP FLO P EXC ITATION TABLE
The char act er ist ic t able is useful dur ing t he analysis of sequent ial cir cuit s when t he
value of flip-flop input s ar e known and we want t o find t he value of t he flip-flop out put Q
aft er t he r ising edge of t he clock signal. As wit h any ot her t r ut h t able, we can use t he map
met hod t o der ive t he char act er ist ic equat ion for each flip-flop.
Dur ing t he design pr ocess we usually know t he t r ansit ion fr om pr esent st at e t o t he
next st at e and wish t o find t he flip-flop input condit ions t hat will cause t he r equir ed t r ansit ion.
For t his r eason we will need a t able t hat list s t he r equir ed input s for a given change of st at e.
Such a list is called t he excitation table. Ther e ar e four possible t r ansit ions fr om pr esent
st at e t o t he next st at e. The r equir ed input condit ions ar e der ived fr om t he infor mat ion
available in t he char act er ist ic t able. The symbol X in t he t able r epr esent s a “don’t car e”
condit ion, t hat is, it does not mat t er whet her t he input is 1 or 0.
The differ ent t ypes of flip flops (RS, J K, D, T) can also be descr ibed by t heir excit at ion,
t able as shown below. The left side shows t he desir ed t r ansit ion fr om Q
n
t o Q
n+1
, t he r ight
side gives t he t r igger ing signals of var ious t ypes of FFs needed for t he t r ansit ions.
Desired transition Triggering signal needed
Q
n
Q
n+1
S R J K D T
0 0 0 x 0 x 0 0
0 1 1 0 1 x 1 1
1 0 0 1 x 1 0 1
1 1 x 0 x 0 1 0
S ynchronous (Clocked) S equential Circuits 239
6.3 FLIP- FLO P C O NVERSIO NS
This sect ion shows how t o conver t a given t ype A FF t o a desir ed t ype B FF using some
conver sion logic.
The key her e is t o use t he excit at ion t able, which shows t he necessar y t r igger ing signal
(S, R, J , K, D and T) for a desir ed flip flop st at e t r ansit ion Q
n
→ Q
n+1
.
Q
n
Q
n+1
S R J K D T
0 0 0 x 0 x 0 0
0 1 1 0 1 x 1 1
1 0 0 1 x 1 0 1
1 1 x 0 x 0 1 0
Example 1. Convert a D-FF to a T-FF :
?
T
D-FF
Clock
Q′
Q
We need t o design t he cir cuit t o gener at e t he t r igger ing signal D as a funct ion of T
and Q : D = f (T, Q)
Consider t he excit at ion t able :
Q
n
Q
n+1
T D
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 1
Tr eat ing D as a funct ion of T and cur r ent FF st at e Q Q
n
we have
D = T' Q + TQ = T⊕Q
D-FF
T
Q
Q′
Clock
Example 2. Convert a RS -FF to a D-FF :
240 S witching Theory
D
?
S
R
Q′
Q
Clock
We need t o design t he cir cuit t o gener at e t he t r igger ing signals S and R as funct ions
of D and Q. Consider t he excit at ion t able :
Q
n
Q
n+1
D S R
0 0 0 0 X
0 1 1 1 0
1 0 0 0 1
1 1 1 X 0
The desir ed signal S and R can be obt ained as funct ions of T and cur r ent FF st at e Q
fr om t he Kar naugh maps :
0 0
1 X
0
0
D
Q
0 1
0
0
D
Q
0 1
X
0
1
0
S = D R = D′
S = D, R = D′
S
R
Q
Q′
D
Clock
Example 3. Convert a RS -FF to a J K-FF.
?
J
K
S
R
Q
Q′
Clock
S ynchronous (Clocked) S equential Circuits 241
We need t o design t he cir cuit t o gener at e t he t r igger ing signals S and R as funct ions
of J , K and Q. Consider t he excit at ion t able.
Q
n
Q
n+1
J K S R
0 0 0 x 0 x
0 1 1 x 1 0
1 0 x 1 0 1
1 1 x 0 x 0
The desir ed signals S and R as funct ion J , K and cur r ent FF st at e Q can be obt ained
fr om t he Kar naugh maps:
0 1
1 1
0
1
K
QJ
00 01
S = Q J ′
X X
0 0
11 10
X 0
X 0
0
0
K
QJ
00 01
R = QK
0 0
1 1
11 10
S = Q' J , R = QK
J
K
S
R
Q
Q′
Clock
6.4 ANALYSIS O F C LO C KED SEQ UENTIAL C IRC UITS
The behaviour of a sequent ial cir cuit is det er mined fr om t he input s, t he out put s and
t he st at es of it s flip-flops. Bot h t he out put and t he next st at e ar e a funct ion of t he input s
and t he pr esent st at e.
The suggest ed analysis pr ocedur e of a sequent ial cir cuit is set out below.
We st ar t wit h t he logic schemat ic fr om which we can der ive excit at ion equat ions for
each flip-flop input . Then, t o obt ain next -st at e equat ions, we inser t t he excit at ion equat ions
int o t he char act er ist ic equat ions. The out put equat ions can be der ive fr om t he schemat ic,
and once we have our out put and next -st at e equat ions, we can gener at e t he next -st at e
and out put t ables as well as st at e diagr ams. When we r each t his st age, we use eit her
t he t able or t he st at e diagr am t o develop a t iming diagr am which can be ver ified t hr ough
simulat ion.
242 S witching Theory
Logic Schematic
Derive excitation equation
(Boolean Expression)
Derive next-state and output
equations
Generate next-state and output
tables
Generate state diagram
Develope timing diagram
Example 1. Modulo-4 counter
Derive the state table and state diagram for the sequential circuit shown in Figure A.
x
CLK
FF1
D Q
Q′
FF2
D Q
Q′
Fi gure: A Logic schemat ic of a sequent ial cir cuit .
S ynchronous (Clocked) S equential Circuits 243
Sol ut i on.
Step 1 : Fir st we der ive t he Boolean expr essions for t he input s of each flip-flops in
t he schemat ic, in t er ms of ext er nal input X and t he flip-flop out put s Q
1
and Q
0
. Since t her e
ar e t wo D flip-flops in t his example, we der ive t wo expr essions for D
1
and D
0
:
D
0
= x⊕Q
0
= x′Q
0
+ xQ
o

D
1
= x′Q
1
+ xQ
1
′Q
0
+ xQ
1
Q
0

These Boolean expr essions ar e called excit at ion equat ions since t hey r epr esent t he
input s t o t he flip-flops of t he sequent ial cir cuit in t he next clock cycle.
Step 2 : Der ive t he next -st at e equat ions by conver t ing t hese excit at ion equat ions int o
flip-flop char act er ist ic equat ions. In t he case of D flip-flops, Q(next ) = D. Ther efor e t he next
st at e equal t he excit at ion equat ions.
Q
0
(next ) = D
0
=x′Q
0
+ xQ
0

Q
1
(next ) = D
1
= x′Q
1
+ xQ
1
′ Q
0

Step 3 : Now conver t t hese next -st at e equat ions int o t abular for m called t he next -st at e
t able.
Present S tate Next S tate
Q
1
Q x = 0
x = 1
0 0
0 1
0 0
0 1
0 1 1 0
1 0 1 0
1 1
1 1
1 1
0 0
Each r ow is cor r esponding t o a st at e of t he sequent ial cir cuit and each column r epr esent s
one set of input values. Since we have t wo flip-flops, t he number of possible st at es is four
- t hat is, Q
1
Q
0
can be equal t o 00, 01, 10, or 11. These ar e pr esent st at es as shown in t he
t able.
For t he next st at e par t of t he t able, each ent r y defines t he value of t he sequent ial
cir cuit in t he next clock cycle aft er t he r ising edge of t he CLK. Since t his value depends on
t he pr esent st at e and t he value of t he input signals, t he next st at e t able will cont ain one
column for each assignment of binar y values t o t he input signals. In t his example, since
t her e is only one input signal, Cnt , t he next -st at e t able shown has only t wo columns,
corresponding t o x = 0 and x = 1.
244 S witching Theory
Not e t hat each ent r y in t he next -st at e t able indicat es t he values of t he flip-flops in t he
next st at e if t heir value in t he pr esent st at e is in t he r ow header and t he input values in
t he column header.
Each of t hese next -st at e values has been comput ed fr om t he next -st at e equat ions in
STEP 2.
Step 4 : The st at e diagr am is gener at ed dir ect ly fr om t he next -st at e t able, shown in
Fig. B.
00 01
10 11
x = 1
x = 0
x = 1
x = 0
x = 1
x = 1
x = 0 x = 0
Fi g. B : St at e diagr am.
Each ar e is labelled wit h t he values of t he input signals t hat cause t he t r ansit ion fr om
t he pr esent st at e (t he sour ce of t he ar c) t o t he next st at e (t he dest inat ion of t he ar c).
In gener al, t he number of st at es in a next -st at e t able or a st at e diagr am will equal 2m
where m is t he number of flip-flops. Similar ly, t he number of ar cs will equal 2
m
× 2
k
, wher e
k is t he number of binar y input signals. Ther efor e, in t he st at e diagr am, t her e must be four
st at es and eight t r ansit ions. Following t hese t r ansit ion ar cs, we can see t hat as long as
x = 1, t he sequent ial cir cuit goes t hr ough t he st at es in t he following sequence : 0, 1, 2, 3,
0, 1, 2, ...... On t he ot her hand, when x = 0, t he cir cuit st ays in it s pr esent st at e unt il x
changes t o 1, at which t he count ing cont inues.
Since t his sequence is char act er ist ic of modulo-4 count ing, we can conclude t hat t he
sequent ial cir cuit in Figure A is a modulo-4 count er wit h one cont r ol signal, x, which enables
count ing when X = 1 and disables it when x = 0.
Example 2. Derive the next state, the output table and the state diagram for the
sequential circuit shown in Fig. B.
Soluti on. The input combinat ional logic in Figur e B is t he same as in Example 1, so
t he excit at ion and t he next -st at e equat ions will be same as in Example 1.
Excit at ion equat ions :
D
0
= x⊕Q
0
+ x′Q
0
+ xQ
0

D
0
= x′Q
1
+ xQ
1
′Q
0
+ xQ
1
Q
0

S ynchronous (Clocked) S equential Circuits 245
x
CLK
FF1
D Q
Q′
FF2
D Q
Q′
Y
Figure B : Logic schemat ic of a sequent ial cir cuit .
Next -st at e equat ions :
Q
0
(next ) = D
0
= x′Q
0
+ xQ
0

Q
1
(next ) = D
0
= x′Q
1
+ xQ
1
′Q
0
+ xQ
1
Q
0
In addit ion, however, we have comput ed t he out put equat ion.
Out put equat ion : Y = Q
1
Q
0
As t his equat ion shows, t he out put Y will equal t o 1 when t he count er is in st at e
Q
1
Q
0
= 11, and it will st ay 1 as long as t he count er st ays in t hat st at e.
Next -st at e and out put t able :
Present S tate Next S tate Output
Q
1
Q
0
x = 0 z
00
01
00 0
01
01 10 0
10 10 0
11
11 1
11
00
246 S witching Theory
Clock cycle 1 Clock cycle 2 Clock cycle 3 Clock cycle 4
1K
X
Q
1
Q
0
Y
t
0
t
1
t
2
t
3
t
4
t
5
00
Y = 0
01
Y = 0
10
Y = 0
11
Y = 1
x = 1
x = 0
x = 1
x = 0
x = 1
x = 1
x = 0 x = 0
Fig. St at e diagr am of sequent ial cir cuit in Figur e B.
Timing d ia g ra m
Figur e C. Timing diagr am of sequent ial cir cuit in Figure A.
Not e t hat t he count er will r each t he st at e Q
1
Q
0
= 11 only in t he t hir d clock cycle, so
t he out put Y will equal 1 aft er Q
0
changes t o 1. Since count ing is disabled in t he t hir d clock
cycle, t he count er will st ay in t he st at e Q
1
Q
0
= 11 and Y will st ay asser t ed in all succeeding
clock cycles unt il count ing is enabled again.
6.5 DESIG N O F C LO C KED SEQ UENTIAL C IRC UITS
The design of a synchr onous sequent ial cir cuit st ar t s fr om a set of specificat ions and
culminat es in a logic diagr am or a list of Boolean funct ions fr om which a logic diagr am can
S ynchronous (Clocked) S equential Circuits 247
be obt ained. In cont r ast t o a combinat ional logic, which is fully specified by a t r ut h t able,
a sequent ial cir cuit r equir es a st at e t able for it s specificat ion. The fir st st ep in t he design
of sequent ial cir cuit s is t o obt ain a st at e t able or an equivalence r epr esent at ion, such as a
st at e diagr am.
The r ecommended st eps for t he design of sequent ial cir cuit s ar e set out below.
Specify the problem
(Word description of the circuit behaviour)
Derive the state diagram
Obtain the state table
The number of states may be reduced
by state reduction method
Choose the type of flip-flops to be used
Determine the number of flip-flops
needed
Derive excitation equations
Using the map or any other simplification
method, derive the output functions and
the flip-flop input functions
Draw the logic diagram
A synchr onous sequent ial cir cuit is made up of flip-flops and combinat ional gat es. The
design of t he cir cuit consist s of choosing t he flip-flops and t hen finding t he combinat ional
st r uct ur e which, t oget her wit h t he flip-flops, pr oduces a cir cuit t hat fulfils t he r equir ed
specificat ions. The number of flip-flops is det er mined fr om t he number of st at es needed in
t he cir cuit .
248 S witching Theory
Sta te Ta b le
The st at e t able r epr esent at ion of a sequent ial cir cuit consist s of t hr ee sect ions labelled
present state, next state and output. The pr esent st at e designat es t he st at e of flip-flops befor e
t he occur r ence of a clock pulse. The next st at e shows t he st at es of flip-flops aft er t he clock
pulse, and t he out put sect ion list s t he value of t he out put var iables dur ing t he pr esent st at e.
Sta te Dia g ra m
In addit ion t o gr aphical symbols, t ables or equat ions, flip-flops can also be r epr esent ed
gr aphically by a st at e diagr am. In t his diagr am, a st at e is r epr esent ed by a cir cle, and t he
t r ansit ion bet ween st at es is indicat ed by dir ect ed lines (or ar cs) connect ing t he cir cles.
Sta te Dia g ra ms of Va rious Flip - Flop s
Table below shows t he st at e diagr ams of t he four t ypes of flip-flops.
Q = 0 Q = 1
S, R = 0, 0 S, R = 0, 0
S, R = 1, 0
S, R = 0, 1
SR
Name State Diatram
Q = 0 Q = 1
J, K = 0, 0 J, K = 0, 0 JK
J, K = 1, 0 or 1, 1
J, K = 0, 1 or 1, 1
Q = 0 Q = 1
D = 1 D = 1
D = 1
D = 0
D
Q = 0 Q = 1
T = 0 T = 0
T = 1
T = 1
T
One can see fr om t he t able t hat all four flip-flops have t he same number of st at es and
t r ansit ions. Each flip-flop is in t he set st at e when Q = 1 and in t he r eset st at e when
S ynchronous (Clocked) S equential Circuits 249
Q = 0. Also, each flip-flop can move fr om one st at e t o anot her, or it can r e-ent er t he same
st at e. The only differ ence bet ween t he four t ypes lies in t he values of input signals t hat
cause t hese t r ansit ions.
A st at e diagr am is a ver y convenient way t o visualize t he oper at ion of a flip-flop or even
of lar ge sequent ial component s.
Sta te Re d uc tio n
Any design pr ocess must consider t he pr oblem of minimizing t he cost of t he final
cir cuit . The t wo most obvious cost r educt ions ar e r educt ions in t he number of flip-flops and
t he number of gat es.
The number of st at es in a sequent ial cir cuit is closely r elat ed t o t he complexit y of t he
r esult ing cir cuit . It is t her efor e desir able t o know when t wo or mor e st at es ar e equivalent
in all aspect s. The pr ocess of eliminat ing t he equivalent or r edundant st at es fr om a st at e
t able/diagr am is known as state reduction.
Example. Let us consider t he st at e t able of a sequent ial cir cuit shown in Table A.
Table A. State table
Present S tate Next S tate Output
x = 0 x = 0
x = 1 x = 1
B 1
A C 0
F 0
B D 1
E
C F 1
F 0
D E 1
A 0
E D 0
B 1
F C 0
It can be seen fr om t he t able t hat t he pr esent st at e A and F bot h ha ve t he same
next st at es, B (when x = 0) and C (when x = 1). They also pr oduce t he same out put 1
(when x = 0) and 0 (when x = 1). Ther efor e st at es A and F ar e equivalent . Thus one of
t he st at es, A or F can be r emoved fr om t he st at e t able. For example, if we r emove r ow
F fr om t he t able and r eplace all F’s by A’s in t he columns, t he st at e t able is modified
as shown in Table B.
250 S witching Theory
Table B. State F removed
Present Next S tate Output
S tate x = 0 x = 0
x = 1 x = 1
A B 1
C 0
B A 0
D 0
C D 1
E 1
D A 0
E 1
E A 0
D 0
It is appar ent t hat st at es B and E ar e equivalent . Removing E and r eplacing E’s by B’s
r esult s in t he r educe t able shown in Table C.
Table C. Reduced state table
Present Next S tate Output
S tate x = 0 x = 0
x = 1 x = 1
A B 1
C 0
B A 0
D 0
C D 1
B 1
D A 0
B 1
The r emoval of equivalent st at es has r educed t he number of st at es in t he cir cuit fr om
six t o four. Two st at es ar e consider ed t o be equivalent if and only if for ever y input sequence
t he cir cuit pr oduces t he same out put sequence ir r espect ive of which one of t he t wo st at es
is t he st ar t ing st at e.
6.6 FINITE STATE M AC HINE ( FSM )
Defi ni ti on: A t ypical sequent ial syst em composed of
• Input s fr om out side wor ld;
S ynchronous (Clocked) S equential Circuits 251
• Internal state of t he syst em st or ed in t he memor y element s;
• Outputs t o out side wor ld;
• Next state decoder;
• Output decoder.
Bot h t he next st at e and t he out put ar e funct ions of t he input and t he cur r ent st at e :
Next St at e = G(Input , Cur r ent St at e)
Out put = F(Input , Cur r ent St at e)
Such a syst em is also called a Mealy Machine, or Class A machine. Finit e st at e machine
has differ ent var iat ions.
A G e ne ra l M od a l of FSM —M e a ly ( C la ss A) M a c hine
Output
function F
Output = F(Input, Current state)
Current state
Next state = G(Input, Current state)
State Registers
Next state
function G
Input
Finit e st at e machine can be designed t o cont r ol pr ocesses of digital nat ur e (discr et e in
t ime, binar y in var iable values) which can be descr ibed by Boolean algebr a. This is compar able
wit h but differ ent fr om t he PID cont r oller s which ar e used t o cont r ol pr ocesses of analog
nat ur e (cont inuous in bot h t ime and var iable values) descr ibed by differ ent ial equat ions.
Finite Sta te M a c hine ( FSM ) Use d a s a C ontrolle r
Wit h t he help of following st eps one can design an FSM for solving a given pr oblem :
1. Under st and t he pr oblem and det er mine t he number of states needed. If t her e ar e
N st at es, t hen at least log
2
N flip-flop’s ar e needed t o r epr esent t hese st at es. This
is t he most impor t ant st ep!
252 S witching Theory
System under
control
Controller
(FSM)
Control input
Control ouput
System
output
(feed back)
Moore (Class B) Machine
Output =
F(Current state)
Output
function F
Current state
State registers
Next state =
G(Input, Current state)
Next state
function G
Input
Class C Machine
State registers
Next state
function G
Next state =
G(Input, Current state)
Input
Output =
F(Current state)
Class D Machine
State registers
Next state
function G
Next state = G(Input)
Output = Current state
Input
Next state = G(Input)
Output = Current state
Class E Machine
State Registers
S ynchronous (Clocked) S equential Circuits 253
2. Draw t he state di agram. At each st at e, find out wher e t o go as t he next st at e and
what out put t o gener at e each combinat ion of input s.
3. Make t he state table based on t he st at e diagr am. The cur r ent st at e (r epr esent ed
by t he Q(t)’s of t he FFs) and input s ar e list ed on t he left as ar gument s, while t he
cor r esponding next st at e (r epr esent ed by Q(t+1)’s of t he FFs) and out put s ar e list ed
on t he r ight as t he funct ions.
4. Design t he ne xt s t at e de code r and t he out put de code r using t he st at e t able
as t he t r ut h t able. If D-FFs ar e used, t hen Q(t +1) of t he it h FF can be used
dir ect ly as t he signal D
i
t o set t he FF. However, when ot her t ypes of FFs ar e
t o be used, t he excit at ion t able is helpful t o figur e out t he signals (S, R, J , K,
or T) needed t o r ealize t he desir ed st at e t r ansit ion : Q(t) → Q(t +1) for each of
t he FFs.
5. Si mpli fy t he funct ions by K-map, and i mplement t he next st at e and out put
decoder s at logic gat e level.
Previous
State A
Input/F (Input, A)
Previous
State B
Next State C Next State D
B = G(Input, A)
Input 1/F(Input 1, B) Input 2/F(Input 2, B)
C = G(Input 1, B) D = G(Input 2, B)
Next State = G(Input, Present State)
Output = F(Input, Present State)
Note: Many of t he pr oblems of int er est t o us only r equir e Mor e or class B machine (t he
out put s ar e funct ions of t he st at e only) or class C machine (t he out put s ar e t he same as t he
st at e). In t hese cases, t he out put s can be gener at ed as funct ions of t he new st at e aft er t he
t r ansit ion is complet ed.
Example 1. A ser ial adder r eceives t wo oper ands A = a
n–1
, ...., a
i
, ... a
0
B = b
n–1
,..., b
n
... b
n
as t wo sequences of bit s (i = 0, 1, ..., n – 1) and adds t hem one bit at a t ime t o
gener at e t he sequence of bit s S
i
of t he sum as t he out put . Implement t his ser ial adder as
a finit e st at e machine.
* Input s : a
i
and b
i
* Out put : S
i
* Two st at es : car r y S = 1, or no car r y S = 0
254 S witching Theory
* St at e diagr am:
10/1
0
No carry
1
Carry
00/0
01/1
00/1
11/0
01/0
10/0
11/1
* St at e t able:
Present Inputs Next Output
S tate S a
i
b
i
S tate S ’ S
i
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
0 1
1 1
0
1
S
ab
00 01
S = ab + aS + bS ′
1 0
1 1
11 10
0 1
1 0
0
1
S
ab
00 01
S = a b S ⊕ ′ ⊕
0 1
1 0
11 10
• Next st at e decoder : S′ = G(a
i
, b
i
, S) = a
i
b
i
+ a
i
S + b
i
S
• Out put decoder : S
i
= F(a
i
, b
i
, S) = a
i
⊕ b
i
⊕ S
The FSM implement at ion of t he ser ial adder cont ains t hr ee pieces of har dwar e: (i) a
D-FF for keeping t he st at e (whet her or not t her e is a car r y fr om t he it h bit t o t he (i+1)t h
bit ), (ii) t he next st at e decoder S = a
i
b
i
+ a
i
S + b
i
S t hat set s t he D-FF, and (iii) t he out put
decoder t hat gener at es t he sum bit s
i
= a
i
⊕ b
i
⊕ S. Not e t hat a MS-FF is used for t he out put
so t hat t he out put is a funct ion of t he cur r ent st at e and input , and it will st ay unchanged
aft er t he st at e t r ansit ion (fr om cur r ent t o next st at e).
Example 2. Design t he FSM cont r oller for t he t r affic light s at an int er sect ion (Nor t h/
Sout h (NS) vs. East /West (EW) wit h gr een and r ed light s only. The r ule : (a) if no car
det ect ed, st ay t he same st at e, (b) if cars are det ect ed in t he direct ion wit h red light (independent
of whet her car s ar e det ect ed in t he dir ect ion wit h gr een light ), swit ch st at e.
S ynchronous (Clocked) S equential Circuits 255
a
b
D
S
D
S
Clock
Next State
Decoder
Output
Decoder
• St at es :
• S = 0: NS gr een (EW r ed);
• S = 1: EW gr een (NS r ed).
• Input s :
• NS = 1/0: NS car det ect ed/not det ect ed
• EW = 11/0: EW car det ect ed/not det ect ed
• out put : same as st at es (a class C FSM).
The st at e diagr am :
S = 0
NS green
NS = 1
EW = X
EW = 1
NS = X
EW = X
NS = 0
EW = 0
NS = X
S = 1
EW green
The st at e t able:
Present Inputs’ Next S ignals to trigger the FF
S tate (PS ) NS EW S tate D S R J K T
0 x 0 0 0 0 x 0 0 0
0 x 1 1 1 1 0 1 x 1
1 0 x 1 1 x 0 x 0 0
1 1 x 0 0 0 1 x 1 1
The next st at e decoder can be implement ed in any of t he four t ypes of flip flops. Given
t he desir ed st at e t r ansit ion (fr om pr esent st at e t o next st at e), t he signals needed t o t r igger
t he chosen FF can be obt ained by t he excit at ion t able (also shown in t he st at e t able), t o be
gener at ed by t he next st at e decoder. Not e t hat if D-FF is used, t he t r igger ing signal is t he
same as t he desir ed next st at e.
• D-FF : D =
PS
.EW + PS.
NS
• RS-FF : S =
PS
.EW, R = PS.NS
256 S witching Theory
• J K-FF : J = EW, K = NS
• T-FF : T =
PS
.EW + PS.NS
EW
NS
S
EW green
NS green
NS
EW
T
EW green
NS green
R
EW
NS
EW green
NS green
J
K
6.7 SO LVED EXAM PLES
Example 1. For the state diagram shown in Fig. 6. Write state table & reduced state table.
a
c
g
f
d
e
b
0/1
0
/0
0
/1
1/0
0
/0
1/0
0
/1
1
/
1
1/0
0/0
1/1
1
/0
0
/
0
1/1
Soluti on. Fr om t he st at e diagr am, a st at e t able is pr epar ed as shown in t able 6.
Present S tate Next state Output
x = 0 x = 1 x = 0 x = 1
a c b 0 0
b d c 0 0
c g d 1 1
d e f 1 0
e f a 0 1
f g f 1 0
g f a 0 1
S ynchronous (Clocked) S equential Circuits 257
It has been shown fr om t he t able 6 t hat t he pr esent st at e e and g bot h have t he
same next st at es f (when x = 0) and a (when x = 1). They also pr oduce t he same out put
0 (when x = 0) and 1 (when x = 1). Ther efor e st at es e and g ar e equivalent . Thus one
of t he st at es, e or g can be r emoved fr om t he st at e t able. For example, if we r emove
r aw g fr om t he t able and r eplace all g’s by e’s in t he columns, t he st at e t able is modified
as shown in t able 6.
Table 6. Staste g removed
Present S tate Next state Output
x = 0 x = 1 x = 0 x = 1
a c b 0 0
b d c 0 0
c e d 1 1
d e f 1 0
e f a 0 1
f e f 1 0
Similar ly st at e d and f ar e also equivalent , t her efor e one of t hem say I, can be eliminat ed.
Aft er r eplacing all f’s by d’s in t he columns, t he r educed st at e t able is given in t able 6.
Table 6. Reduced state table
Present S tate Next state Output
x = 0 x = 1 x = 0 x = 1
a c b 0 0
b d c 0 0
c e d 1 1
d e f 1 0
e d a 0 1
Example 2. A sequential circuit has two flip-flops say A and B, two inputs say X and
Y, and an output say Z. The flip-flop input functions and the circuit output function are as
follows :
JA = xB + y′B′
JB = xA′
Z = xy A + x′y′B
KA = xy′B′
KB = xy′ + A
Obtain state table, state diagram and state equations.
Sol ut i on.
St at e t able for t he pr oblem is shown in t able 6.1.
258 S witching Theory
Present state Next state Output z
A B xy = 00 xy = 01 xy = 10 xy = 11 xy = 00 xy = 01 xy = 10 xy = 11
A B A B A B A B
0 0 1 0 0 0 1 1 0 1 0 0 0 0
0 1 0 1 0 1 1 0 1 1 1 0 0 0
1 0 1 0 1 0 0 0 1 0 0 0 0 1
1 1 1 0 1 0 1 0 1 0 1 0 0 1
Fi g. 6 State table
Wit h t he help of st at e t able we can dr aw t he st at e diagr am as shown in figur e 6.
00
10
00/0 10/0
00/0
01/0
11/1
01
11
11/0
10/0
11/0
00/1
01/0
10/0
11/1
01/0
00/1
01/0
Fig. 6. St at e diagr am
The st at e equat ion will be
A (t+1) = xB + Y' + Y A + x' A
B (t+1) = x A'B' + x'AB + Y A'B
Example 3. A clocked sequential circuit has three states, A, B and C and one input X.
As long as the input X is O, the circuit alternates between the states A and B. If the input
X becomes 1 (either in state A or in state B), the circuit goes to state C and remains in the
state C as long as X continues to be 1. The circuit returns to state A if the input becomes
0 once again and from then one repeats its behaviour. Assume that the state assignments are
A = 00, B = 01 and C = 10.
(a) Draw the state diagram.
(b) Give the state table for the circuit.
Soluti on. (a) Fir st dr aw cir cles for 3 st at es A, B, C and
wr it e st at e assignment s.
The dir ect ed line indicat e t he t r ansit ion and input on
t he dir ect ed line ar e t hose causes t he change on t he line. The
figur e 6. Shows t he st at e diagr am.
00
A
10
C
01 B
0
1
1 1
Fi g. 6
S ynchronous (Clocked) S equential Circuits 259
(b) Fr om t he st at e diagr am, a st at e t able is dr awn as shown in t able 6.
Table 6. State table
Present S tate Next state Output
x = 0 x = 1 x = 0 x = 1
A B C 0 1
B A C 0 1
C A C 0 1
Given t he st at e assignment s A = 00, B = 01, C = 10.
Example 4. A new clocked x-Y flip-flop is defined with two inputs X and Y in addition
to the clock input. The flip-flop functions as follows :
If XY = 00, the flip-flop changes state with each clock pulse.
If XY = 01, the flip flop state Q becomes 1 with the next clock pulse.
If XY = 10, the flip flop state Q become 0 with the next clock pulse.
If XY = 11, no change of state occurs with the clock pulse.
(a) Write the truth table for the X-Y flip-flop.
(b) Write the Excitation table for the X-Y flip flop.
(c) Draw a circuit 40 implement the X-Y flip-flop using a J -K flip-flop.
Soluti on. (a) Tr ut h t able for t he clocked X-Y flip flop is shown in t able 6.
Inputs Next state
X Y Q
n+1
0 0 Q
n
0 1 1
1 0 0
1 1 Q
n
(b) The Excit at ion t able for t he X-Y flip flop is shown in t able 6.
Q
n
Q
n+1
X Y
0 0 1 x
0 1 0 x
1 0 x 0
1 1 x 1
x = dist ance
(c) On compar ing Excit at ion t able of X-Y flip-flop wit h J K flip-flop
X =
J
: Y =
K
Ther efor e t he X-Y flip flop can be implement ed using J -K flip-flop as shown in figur e 6.
260 S witching Theory
CLK
X
Y
J
K
Q
n
Q
n
Example 5. For the digital circuit shown in the figure 6. Explain what happens at the
nodes N
1
, N
2
, F and F , when
(I) C
K
=1 and ‘A’ changes from ‘0’ to ‘1’.
(II) A = 1 and ‘C
K
’ changes from ‘1’ to ‘0’.
(III) C
K
= 0 and ‘A’ changes from ‘1’ to ‘0’.
(IV) Initially, C
K
= 0 and ‘A’ changes from 0 to 1, and then C
K
goes to 1.
(V) What is the circuit performing.
C
K
G
4
G
3
N
1
F
F
G
2
N
2
G
1
A
Sol ut i on.
(I) N
1(n)
N
2(n)
C
K
A G
1
G
2
G
3
G
4
N
2(n+1)
N
1(n+1)
0 0 1 1 0 0 0 1 0 0
1 0 1 1 0 0 0 0 0 0
0 1 1 1 0 0 0 1 0 0
1 1 1 1 0 0 0 0 0 0
Init ially if N
1
, N
2
ar e 0, it r emains at 0. If at 1, t hey go t o 0.
As N
1
, N
2
ar e at 0, in init ially, if F is 1, F is 0. or init ially if F = 0,
F
is 1.
That is F, F do not change t heir init ial st at es.
(II) N
1(n)
N
2(n)
C
K
A G
1
G
2
N
2(n+1)
G
3
G
4
N
1(n+1)
0 0 0 1 0 1 1 0 1 0
1 0 0 1 0 1 1 1 0 1
0 1 0 1 0 1 1 0 1 0
1 1 0 1 0 1 1 1 0 1
N
2
cont inues t o be 1 what ever be it s init ial st at e. N
1
r emains at 0 if init ially 0, and
1 if init ially 1.
If F = 0, F = 0
S ynchronous (Clocked) S equential Circuits 261
If N
1
= 0, F will become 1 and F = 0
If N
1
= 1, F will be 0 and F also 0, which is pr ohibit ed st at e.
(III) N
1(n)
N
2(n)
C
K
A G
1
G
2
N
2(n+1)
G
3
G
4
N
1(n+1)
0 0 0 0 1 0 0 1 0 1
1 0 0 0 1 0 0 1 0 1
0 1 0 0 0 1 1 0 1 0
1 1 0 0 0 1 1 1 0 1
N
2
= 0, F = 1, F = 0, N
1
= 0, F = 1, N
1
= 1, F = 0, F = 1
N
2
= 1, F = 1, F = 0, N
1
= 0, F = 1, N
1
= 1, F = 0, F = 1
(IV) The change of st at e is similar t o (II), C
K
= 0, A = 1 init ially and finally as at (I),
C
K
= 1, A = 1.
(V) The cir cuit is funct ioning as a SR lat ch.
Example 6. The full adder given in figure 6 receives two external inputs x & y; the
third input Z comes from the output of a D flip-flop. The carry output is transferred to the
flip-flop, every clock pulse. The external S output gives the sum of x, y and z. Obtain the state
table and state diagram of the sequential circuit.
Sol ut i on.
Full Adder
S
C
x
y
z
Q
D
CP
The st at e t able for t he given cir cuit is shown in figur e 6.
Present state Inputs Next state Output
z x y z S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Fi g. 6. State table
262 S witching Theory
The st at e diagr am cor r esponding t o st at e-t able of figur e 6.
0
1
00/0
01/1
10/1
01/0
10/0
11/1
11/0
00/1
Fig. 6. St at e diagr am
6.8 EXERC ISES
1. An R-S lat ch can be based on cr oss-coupled NOR gat es. It is also possible t o cont r uct an
R’-S’ lat ch using cr oss-coupled NAND gat es.
(a) Dr aw t he R’-S’ lat ch, labelling t he R’ and S’ input s and t he Q and Q’ out put s.
(b) Show t he t iming behaviour acr oss t he four configur at ions of R’ and S’. Indicat e on your
t iming diagr am t he behaviour in ent er ing and leaving t he for bidden st at e when R’=S’=0.
(c) Dr aw t he st at e diagr am t hat shows t he complet e input /out put and st at e t r ansit ion
behaviour of t he R’-S’ lat ch.
(d) What is t he char act er ist ic equat ion of t he R’-S’ lat ch.
(e) Dr aw a simple schemat ic for a gat ed R-S lat ch wit h an ext r a enable input , using
NAND gat es only.
2. Consider a D-t ype st or age element implement ed in five differ ent ways :
(a) D-lat ch (i.e., D wir ed t o t he S-input and D’ wir ed t o t he R-input of an R-S lat ch);
(b) Clock Enabled D-lat ch;
(c) Mast er -Slave Clock Enabled D-Flip-flop;
(d) Posit ive Edge-t r igger ed Flip-flop;
(e) Negat ive Edge-t r igger ed Flip-flop,
Complet e t he following t iming char t s indicat ing t he behaviour of t hese alt er nat ive st or age
element s. Ignor e set -up and hold t ime limit at ions (assume all const r aint s ar e meant ):
CLK
D
D-latch
Clocked D-latch
DM/S Flip-Flop
Positive edge FF
Negative edge FF
3. Complet e t he t iming diagr am for t his cir cuit .
S ynchronous (Clocked) S equential Circuits 263
T
D
CLK
Q
Q
T
CLK
Q
4. Design a cir cuit t hat implement s t he st at e diagr am
1/1 S0 S1
S2
1/1
1/0
0/0
0/1
0/1
5. Design a cir cuit t hat implement s t he st at e diagr am
S0
0/0
1/0
S4
0/0
1/1
S3
S2
S1
0/1
0/1
1/1
0/1
1/0
1/0
6. A sequent ial net wor k has one input X and t wo out put s S and V. X r epr esent a four bit binar y
number N, which is input least significant bit fir st . S r epr esent s a four bit binar y number
equal t o N + 2, which is out put least significant bit fir st . At t he t ime t he four t h input is
sampled, V = 1, in N + 2 is t oo lar ge t o be r epr esent ed by four bit s; ot her wise V = 0.
Der ive a Mealy st at e gr aph and t able wit h a minimum number of st at es.
7. A sequent ial net wor k has one input X and t wo out put s S and V. X r epr esent a four bit binar y
number N, which is input least significant bit fir st . S r epr esent s a four bit binar y number
264 S witching Theory
equal t o N – 2, which is out put least significant bit fir st . At t he t ime t he four t h input is
sampled, V = 1, in N – 2 is t oo small t o be r epr esent ed by four bit s; ot her wise V = 0.
Der ive a Mealy st at e gr aph and t able wit h a minimum number of st at es
8. Design a synchr onous cir cuit using negat ive edge-t r iger ed D flip-flops t hat pr ovides an
out put signal Z which has one-fift h t he fr equency of t he clock signal. Dr aw a t iming diagr am
t o indicat e t he exact r elat ionship bet ween t he clock signal and t he out put signal Z. To
ensur e illegal st at e r ecover y, for ce all unused or illegal st at es t o go t o 0.
9. Consider t he design of a sequence det ect or finit e st at e machine t hat will asser t a 1 when
t he cur r ent input equals t he just pr eviously seen input .
(a) Dr aw as simple st at e diagr ams for a MEALY MACHINE and a MOORE MACHINE
implement at ion as you can (minimizat ion is not necessar y). The MEALY MACHINE
should have fewer st at es. Br iefly explain why.
(b) If t he Mealy Machine is implement ed as a SYNCHRONOUS MEALY MACHINE, dr aw
t he t iming diagr am for t he example input /out put sequence descr ibed above.
(c) If t he t iming behaviour s ar e differ ent for t he MOORE, MEALY, and SYNCHRONOUS
MEALY machines, explain t he r eason why.
10. A sequent ial cir cuit is specified by t he following flip-flop input funct ions. Dr aw t he logic
diagr am of t he cir cuit .
J A = Bx’ KA = Bx
J B = x KB = A⊕x
11. Design t he cir cuit and dr aw t he logic diagr am of t he sequent ial cir cuit specified by t he
following st at e diagr am. Use an RS flip-flop.
0
00
01
10
XY = 0
01
10
11
XY =
XY = 11
XY = 00
12. Complet e t he t r ut h t able for t he lat ch const r uct ed fr om 2 NOR gat es.
S R Q Q’
1 0
0 0 (aft er S = 1, R = 0)
0 1
0 0 (aft er S = 0, R = 1)
1 1
1
0
1
0
R(Reset)
S(Set)
Q
Q
13. Const r uct a logic diagr am of a clocked D flip-flop using AND and NOR gat es.
14. Explain t he mast er -slave flip-flop const r uct ed fr om t wo R-S flip-flop.
15. Dr aw t he logic diagr am of a mast er -slave D flip-flop using NAND gat es.
7
CHAPTER
7.0 INTRO DUC TIO N
Regist er s ar e t he gr oup of flip-flops (single bit st or age element ). The simplest t ype of
r egist er is a dat a r egist er, which is used for t he t empor ar y st or age of dat a. In it s simplest
for m, it consist s of a set of N D flip-flops, all shar ing a common clock. All of t he digit s in t he
N bit dat a wor d ar e connect ed t o t he dat a r egist er by an N line “dat a bus”. Fig. 7.0 shows
a four bit dat a r egist er, implement ed wit h four D flip flops.
D
Q
Q
I
0
O
0
D
Q
Q
I
1
O
1
D
Q
Q
I
2
O
2
D
Q
Q
I
3
O
3
Clock
Fig. 7.0 4-bit D r egist er
The dat a r egist er is said t o be a synchr onous device, because all t he flip flops change
st at e at t he same t ime.
7.1 SHIFT REGISTERS
A common for m of r egist er used in many t ypes of logic cir cuit s is a shift r egist er.
Regist er s like count er s, ar e sequent ial cir cuit s and as t hey employ flip flops t hey possess
memor y; but memor y is not t he only r equir ement of a shift r egist er. The funct ion of st or age
of binar y dat a can be ver y well per for med by a simple r egist er. Shift r egist er s ar e r equir ed
t o do much mor e t han t hat . They ar e r equir ed t o st or e binar y dat a moment ar ily unt il it is
ut ilized for inst ance, by a comput er, micr opr ocessor, et c. Somet imes dat a is r equir ed t o be
pr esent ed t o a device in a manner which may be differ ent fr om t he way in which it is fed
t o a shift r egist er. For inst ance, shift r egist er can pr esent dat a t o a device in a ser ial or
par allel for m, ir r espect ive of t he manner in which it is fed t o a shift r egist er. Dat a can also
be manipulat ed wit hin t he shift r egist er, so t hat it is pr esent ed t o a device in t he r equir ed
for m. These devices can also shift left or r ight and it is t his capabilit y which gives t hem t he
name of shift r egist er. Fig. 7.1 show t he many ways in which dat a can be fed int o a shift
r egist er and pr esent ed by it t o a device.
Shift r egist er s have found consider able applicat ion in ar it hmat ic oper at ions. Since moving
a binar y number one bit t o t he left is equivalent t o mult iplying t he number by 2 and moving
t he number one bit posit ion t o t he r ight amount s t o dividing t he number by 2. Thus,
mult iplicat ions and divisions can be accomplished by shift ing dat a bit s. Shift r egist er s find
consider able applicat ion in gener at ing a sequence of cont r ol pulses.
265
SHIFT REGISTERS AND COUNTERS
266 S witching Theory
Serial
Input
1010
Serail
Output
1010
Serial
Input
1001
(a) Serial input/Serial output
Parallel Output
1 0 0 1
(b) Serial input/Parallel output
Serail
Output
1001
(c) Parallel input/Serial output
Parallel Output
1 1 0 1
(b) Parallel input/Parallel output
1 0 0 1
Parallel input
1 1 0 1
Parallel input
Fig. 7.1 Dat a conver sion wit h a shift r egist er
Shift r egist er is simply a set of flip flops (usually D lat ches or RS flip flops) connect ed
t oget her so t hat t he out put of one becomes t he input of t he next , and so on in ser ies. It is
called a shift r egist er because t he dat a is shift ed t hr ough t he r egist er by one bit posit ion on
each clock pulse. Fig. 7.2 shows a four bit shift r egist er, implement ed wit h D flip flops.
D
Q
Q D
Q
Q D
Q
Q D
Q
Q in out
Clock
Fig. 7.2 4-bit ser ial-in ser ial-out shift r egist er
On t he leading edge of t he fir st clock pulse, t he signal on t he DATA input is lat ched in
t he fir st flip flop. On t he leading edge of t he next clock pulse, t he cont ent s of t he fir st flip-
flop is st or ed in t he second flip-flop, and t he signal which is pr esent at t he DATA input is
st or ed is t he fir st flip-flop, et c. Because t he dat a is ent er ed one bit at a t ime, t his called a
ser ial-in shift r egist er. Since t her e is only one out put , and dat a leaves t he shift r egist er one
bit at a t ime, t hen it is also a ser ial out shift r egist er. (Shift r egist er s ar e named by t heir
met hod of input and out put ; eit her ser ial or par allel.) Par allel input can be pr ovided t hr ough
t he use of t he pr eset and clear input s t o t he flip-flop. The par allel loading of t he flip flop can
be synchr onous (i.e., occur s wit h t he clock pulse) or asynchr onous (independent of t he clock
pulse) depending on t he design of t he shift r egist er. Par allel out put can be obt ained fr om t he
out put s of each flip flop as shown in Fig. 7.3.
D
Q
Q D
Q
Q D
Q
Q D
Q
Q in
Clock
O
0
O
1
O
2
O
3
Fig. 7.3 4-bit ser ial-in par allel-out shift r egist er
S hift Registers and Counters 267
Communicat ion bet ween a comput er and a per ipher al device is usually done ser ially,
while comput at ion in t he comput er it self is usually per for med wit h par allel logic cir cuit r y. A
shift r egist er can be used t o conver t infor mat ion fr om ser ial for m t o par allel for m, and vice
ver sa. Many differ ent kinds of shift r egist er s ar e available, depending upon t he degr ee of
sophist icat ion r equir ed.
Her e we deal wit h t he basic char act er ist ics of shift r egist er s and t heir applicat ions.
Nor mally shift r egist er s ar e obt ained t hr ough D-Flip-Flops. However if r equir ed ot her flip
flops may also be used. D-Flip-Flops ar e used because of simplicit y t hat dat a pr esent ed at
input is available at t he out put . Thr oughout t he chapt er it is our st r at egy t o discuss all t he
shift r egist er s using D-flip-flops only. If one need t o use some ot her Flip-Flop, say J K Flip-
Flip, t hen we r ecommend following pr ocedur e–
1. Design t he shift r egist er using D-flip flops only.
2. Take J K Flip-Flip and conver t it int o D Flip-Flop.
3. Replace each of t he D-Flip-Flop of st ep1 by t he flip-flop obt ained in st ep 1 aft er
conver sion.
To elabor at e t his let us consider t he shift r egist er shown in Fig. 7.2.
Step 1: It is r eadily obt ained in Fig. 7.2.
Step 2: Conver t J K int o D-Flip-Flop. It is shown below in Fig. 7.4
J
Q
Q
Clock
D
K
Fig. 7.4 J K Flip-flop conver t ed int o D-Flip-Flop
Step 3: Replace each D-Flip-Flop of Fig. 7.2 by t he one shown in Fig. 7.4.
J
Q
Q
Clock
In
K
J
Q
Q
K
J
Q
Q
K
J
Q
Q
K
Out
Fig. 7.5 (a) 4-bit ser ial in ser ial out shift r egist er using J K Flip-Flop
J
Q
Q
Clock
In
K
J
Q
Q
K
J
Q
Q
K
J
Q
Q
K
Out D
FF0 FF1 FF2 FF3
Fig. 7.5 (b) 4-bit ser ial in–ser ial out shift r egist er using J K Flip-flop
268 S witching Theory
O PERATIO N
A 4-bit shift r egist er const r uct ed wit h D t ype flip-flop (Fig. 7.2) and J K flip-flop (Fig. 7.5).
By addit ion or delet ion of flip-flop mor e or fewer bit s can be accommodat ed. Except for FF0,
t he logic level at a dat a input t er minal is det er mined by t he st at e of t he pr eceding flip-flop.
Thus, D
n
is 0 if t he pr eceding flip-flop is in t he r eset st at e wit h Q
n–1
= 0, and D
n
= 1 if
Q
n–1
= 1. The input at FF0 is det er mined by an ext er nal sour ce.
Fr om t he char act er ist ic of D-flip-flop we know t hat immediat ely aft er t he t r igger ing
t r ansit ion of t he clock, t he out put Q of flip-flop goes t o t he st at e pr esent at it s input D just
befor e t his clock t r ansit ion. Ther efor e, at each clock t r ansit ion, pat t er n of bit s, 1s and 0s, is
shift ed one flip-flop t o t he r ight . The bit of t he last flip-flop (FF3 in Fig. 7.6) is lost , while t he
fir st flip-flop (FF0) goes t o t he st at e det er mined by it s input D
0
. This oper at ion is shown in
Fig. 7.6. We have assumed t hat t he flip-flop t r igger s on t he posit ive-going t r ansit ion of t he
clock wavefor m, and init ially we have D0

= 0, FF0 = 1 and FF2 = FF3 = FF4 = 0.
1
0
1
0
1
0
1
0
1
0
Clock
Pulses
1 2 3 4 5
FF0
1
FF1
0
FF2
0
FF3
0
FF0
0
FF1
1
FF2
0
FF3
0
FF0
0
FF1
0
FF2
1
FF3
0
FF0
0
FF1
0
FF2
0
FF3
1
Fig. 7.6 A 4-bit shift r egist er oper at ion
7.2 MODES OF OPERATION
This sect ion descr ibes, t he basic modes of oper at ion of shift r egist er s such as Ser ial In-
Ser ial Out , Ser ial In-Par allel Out , Par allel In-Ser ial Out , Par allel In-Par allel Out , and bi-
dir ect ional shift r egist er s.
7.2.1 Se ria l In–Se ria l O ut Shift Re g iste rs
A basic four -bit shift r egist er can be const r uct ed using four D-flip-flops, as shown in
Fig. 7.7. The oper at ion of t he cir cuit is as follows. The r egist er is fir st clear ed, for cing all four
out put s t o zer o. The input dat a is t hen applied sequent ially t o t he D input of t he fir st flip-
flop on t he left (FF0). Dur ing each clock pulse, one bit is t r ansmit t ed fr om left t o r ight .
Assume a dat a wor d t o be 1001. The least significant bit of t he dat a has t o be shift ed t hr ough
t he r egist er fr om FF0 t o FF3.
S hift Registers and Counters 269
D
Q
Q D
Q
Q D
Q
Q D
Q
Q
Data output
CLK
Data input
SET SET SET SET
CLR CLR CLR CLR
CLEAR
CLEAR
FF0 FF1 FF2 FF3
0 0 0 0
FF0 FF1 FF2 FF3
Fi g. 7.7
In or der t o get t he dat a out of t he r egist er, t hey must be shift ed out ser ially. This can
be done dest r uct ively or non-dest r uct ively. For dest r uct ive r eadout , t he or iginal dat a is lost
and at t he end of t he r ead cycle, all flip-flops ar e r eset t o zer o.
To avoid t he loss of dat a, an ar r angement for a non-dest r uct ive r eading can be done by
adding t wo AND gat es, an OR gat e and an inver t er t o t he syst em. The const r uct ion of t his
cir cuit is shown in Fig. 7.8.
FF0 FF1 FF2 FF3
CLK
Input data
R/W control
Output data
Fi g. 7.8
The dat a is loaded t o t he r egist er when t he cont r ol line is HIGH (i.e. WRITE). The
dat a can be shift ed out of t he r egist er when t he cont r ol line is LOW (i.e. READ).
7.2.2 Se ria l In- Pa ra lle l O ut Shift Re g iste rs
For t his kind of r egist er, dat a bit s ar e ent er ed ser ially in t he same manner as discussed
in t he last sect ion. The differ ence is t he way in which t he dat a bit s ar e t aken out of t he
r egist er. Once t he dat a ar e st or ed, each bit appear s on it s r espect ive out put line, and all bit s
ar e available simult aneously. A const r uct ion of a four-bit ser ial in-par allel out r egist er is
shown in Fig. 7.9.
D
Q
Q D
Q
Q D
Q
Q
CLK
Input data
SET SET SET
D
Q
Q
SET
CLR CLR CLR CLR
CLEAR
FF0 FF1 FF2 FF3
Q
0
Q
1
Q
2
Q
3
Fi g. 7.9
270 S witching Theory
7.2.3 Pa ra lle l In- Se ria l O ut Shift Re g iste rs
A four -bit par allel in-ser ial out shift r egist er is shown in Fig. 4.10. The cir cuit uses
D-flip-flops and NAND gat es for ent er ing dat a (i.e., wr it ing) t o t he r egist er.
D
0
, D
1
, D
2
and D
3
ar e t he par allel input s, wher e D
0
is t he most significant bit and D
3
is t he least significant bit . To wr it e dat a in, t he mode cont r ol line is t aken t o LOW and t he
dat a is clocked in. The dat a can be shift ed when t he mode cont r ol line is HIGH as SHIFT
is act ive high. The r egist er per for ms r ight shift oper at ion on t he applicat ion of a clock pulse.
Fig. 7.10
7.2.4 Pa ra lle l In- Pa ra lle l O ut Shift Re g iste rs
For par allel in-par allel out shift r egist er s, all dat a bit s appear on t he par allel out put s
immediat ely following t he simult aneous ent r y of t he dat a bit s. The following cir cuit is a four -
bit par allel in-par allel out shift r egist er const r uct ed by D-flip-flops.
D
Q
Q D
Q
Q D
Q
Q
CLEAR
SET SET SET
D
Q
Q
SET
CLR CLR CLR CLR
Q
0
Q
1
Q
2
Q
3
CLK
D
0
D
1
D
2
D
3
Fig. 7.11
The D’s ar e t he par allel input s and t he Q’s ar e t he par allel out put s. Once t he r egist er
is clocked, all t he dat a at t he D input s appear at t he cor r esponding Q out put s simult aneously.
7.2.5 Bid ire c tiona l Shift Re g iste rs ( Unive rsa l Shift Re g iste r)
The r egist er s discussed so far involved only r ight shift oper at ions. Each r ight shift
oper at ion has t he effect of successively dividing t he binar y number by t wo. If t he oper at ion
is r ever sed (left shift ), t his has t he effect of mult iplying t he number by t wo. Wit h suit able
gat ing ar r angement a ser ial shift r egist er can per for m bot h oper at ions.
S hift Registers and Counters 271
A bi-dir ect ional, or r ever sible shift r egist er is one in which t he dat a can be shift
eit her left or r ight . A four-bit bi-dir ect ional shift r egist er using D-flip-flops is shown in
Fig. 7.12.
Her e a set of NAND gat es ar e configur ed as OR gat es t o select dat a input s fr om t he r ight
or left adjacent bist ables, as select ed by t he LEFT/RIGHT cont r ol line.
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
Output
CLEAR
CLK
MSB
LEFT/RIGHT
Input data
Fig. 4.12
7.3 APPLICATIONS OF SHIFT REGISTERS
Shift r egist er s can be found in many applicat ions. Her e is a list of a few.
7.3.1 To Produc e Time De la y
The ser ial in-ser ial out shift r egist er can be used as a t ime delay device. The amount
of delay can be cont r olled by:
• t he number of st ages in t he r egist er (N)
• t he clock fr equency (f)
The t ime delay ∆T is given by
∆T = N* f
7.3.2 To Simp lify C omb ina tiona l Log ic
The r ing count er t echnique can be effect ively ut ilized t o implement synchr onous sequent ial
cir cuit s. A major pr oblem in t he r ealizat ion of sequent ial cir cuit s is t he assignment of binar y
codes t o t he int er nal st at es of t he cir cuit in or der t o r educe t he complexit y of cir cuit s
r equir ed. By assigning one flip-flop t o one int er nal st at e, it is possible t o simplify t he
combinat ional logic r equir ed t o r ealize t he complet e sequent ial cir cuit . When t he cir cuit is in
a par t icular st at e, t he flip-flop cor r esponding t o t hat st at e is set t o HIGH and all ot her flip-
flops r emain LOW.
272 S witching Theory
7.3.3 To Conve rt Se ria l Da ta to Pa ra lle l Da ta
A comput er or micr opr ocessor -based syst em commonly r equir es incoming dat a t o be in
par allel for mat . But fr equent ly, t hese syst ems must communicat e wit h ext er nal devices t hat
send or r eceive ser ial dat a. So, ser ial-t o-par allel conver sion is r equir ed. As shown in t he
pr evious sect ions, a ser ial in-par allel out r egist er can achieve t his.
7.4 C O UNTERS
7.4.1 Introd uc tion
Bot h count er s and r egist er s belong t o t he class of sequent ial cir cuit s. Her e we will
mainly deal wit h count er s and also consider design pr ocedur es for sequent ial logic cir cuit s.
As t he impor t ant char act er ist ic of t hese cir cuit s is memor y, flip-flops nat ur ally const it ut e t he
main cir cuit element of t hese devices and, t her efor e, t her e will be consider able emphasis on
t heir applicat ion in cir cuit design.
You must alr eady be familiar wit h some sequent ial devices, in which oper at ions ar e
per for med in a cer t ain sequence. For inst ance, when you dial a phone number, you dial it in
a cer t ain sequence, if not , you cannot get t he number you want . Similar ly, all ar it hmet ic
oper at ions have t o be per for med in t he r equir ed sequence.
While dealing wit h flip-flops, you have dealt wit h bot h clocked and unclocked flip-flops.
Thus, t her e ar e t wo t ypes of sequent ial cir cuit s, clocked which ar e called synchr onous, and
unclocked which ar e called asynchr onous.
In asynchr onous devices, a change occur s only aft er t he complet ion of t he pr evious
event . A digit al t elephone is an example of an asynchr onous device.
If you ar e dialing a number, say 6354, you will fir st punch 6 followed by 3, 5 and 4. The
impor t ant point t o not e is t hat , each successive event occur s aft er t he pr evious event has
been complet ed.
Sequent ial logic cir cuit s find applicat ion in a var iet y of binar y count er s and st or age devices
and t hey ar e made up of flip-flops. A binar y count er can count t he number of pulses applied at
it s input . On t he applicat ion of clock pulses, t he flip-flops incor por at ed in t he count er under go
a change of st at e in such a manner t hat t he binar y number st or ed in t he flip-flops of t he count er
r epr esent s t he number of clock pulses applied at t he input . By looking at t he count er out put ,
you can det er mine t he number of clock pulses applied at t he count er input .
Digit al cir cuit s use sever al t ypes of count er s which can count in t he pur e binar y for m
and in t he st andar d BCD code as well as in some special codes. Count er s can count up as well
as count down. In t his sect ion we will be looking at some of t he count er s in common use in
digit al devices.
Anot her ar ea of concer n t o us will be t he design of sequent ial cir cuit s. We will be
consider ing bot h synchr onous and asynchr onous sequent ial cir cuit s.
7.4.2 Bina ry Rip p le Up - C ounte r
We will now consider a 3-bit binar y up-count er, which belongs t o t he class asynchr onous
count er cir cuit s and is commonly known as a r ipple count er. Fig. 7.13 shows a 3-bit count er,
which has been implement ed wit h t hr ee T-t ype (t oggle) flip-flops. The number of st at es of which
t his count er is capable is 2
3
or 8. This count er is also r efer r ed t o as a modulo 8 (or divide by
8) count er. Since a flip-flop has t wo st at es, a count er having n flip-flops will have 2
n
st at es.
S hift Registers and Counters 273
When clock pulses ar e applied t o a r ipple count er, t he count er pr ogr esses fr om st at e t o
st at e and t he final out put of t he flip-flop in t he count er indicat es t he pulse count . The cir cuit
r ecylces back t o t he st ar t ing st at e and st ar t s count ing all over again.
Fig. 7.13 3-Bit binar y up-count er
Ther e ar e t wo t ypes of r ipple count er s, (a) asynchr onous count er s and (b) synchr onous
count er s. In asynchr onous count er s all flip-flops ar e not clocked at t he same t ime, while in
synchr onous count er s all flip-flops ar e clocked simult aneously.
You will not ice fr om t he diagr am t hat t he nor mal out put , Q, of each flip-flop is connect ed
t o t he clock input of t he next flip-flop. The T input s of all t he flip-flops, which are T-t ype, ar e
held high t o enable t he flip-flops t o t oggle (change t heir logic st at e) at ever y t r ansit ion of t he
input pulse fr om 1 t o 0. The cir cuit is so ar r anged t hat flip-flop B r eceives it s clock pulse fr om
t he Q
A
out put of flip-flop A and, as a consequence, t he out put of flip-flop B will change it s logic
st at e when out put Q
A
of flip-flop A changes fr om binar y 1 t o 0. This applies t o all t he ot her
flip-flops in t he cir cuit . It is t hus an asynchr onous count er, as all t he flip-flops do not change
t heir logic st at e at t he same t ime.
Let us assume t hat all t he flip-flops have been r eset , so t hat t he out put of t he count er
at t he st ar t of t he count is 0 0 0 as shown in t he fir st r ow of Table 7.1. Also r efer t o Fig.
7.14 which shows t he out put changes for all t he flip-flops at ever y t r ansit ion of t he input pulse
from 1 → 0.
Fig. 7.14 Wavefor m for 3-bit binar y r ipple up-count er
When t he t r ailing edge of t he fir st pulse ar r ives, flip-flop A set s and Q
A
becomes 1, which
does not affect t he out put of flip-flop B. The count er out put now is as shown in r ow 2 of t he
t able. As a r esult of t he second clock pulse, flip-flop A r eset s and it s out put Q
A
changes fr om
1 t o 0, which set s flip-flop B and t he count er out put now is as shown in r ow 3 of t he t able.
274 S witching Theory
When t he t hir d clock pulse ar r ives, flip-flop A set s and it s out put Q
A
becomes 1, which does
not change t he st at e of t he B or t he C flip-flop. The count er out put is now as shown in r ow 3
of t he t able. When t he four t h pulse occur s, flip-flop A r eset s and Q
B
becomes 0 which in t ur n
r eset s flip-flop B and Q
B
becomes 0, which set s flip-flop C and it s out put changes t o 1.
Table 7.1 Count-up sequence of a 3-bi t bi nary counter
Input pulse Count
2
2
2
1
2
0
Q
c
Q
B
Q
A
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1 RECYCLE
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
When t he 5t h clock pulse ar r ives, flip-flop A set s and Q
A
becomes 1; but t he ot her flip-
flops r emain unchanged. The number st or ed in t he count er is shown in t he 6t h r ow of t he
t able. The 6t h pulse r eset s flip-flop A and at t he same t ime flip-flop B and C ar e set . The 7t h
pulse set s all t he flip-flops and t he count er out put is now shown in t he last r ow of t he t able.
The next clock pulse will r eset all t he flip-flops, as t he count er has r eached it s maximum
count capabilit y. The count er has in all 8 st at es. In ot her wor ds it r egist er s a count of 1 for
ever y 8 clock input pulses. It means t hat it divides t he number of input pulses by 8. It is t hus
a divide by 8 count er.
C ount C a p a b ility of Rip p le C ounte rs
If you r efer t o Table 7.1 and t he wavefor m diagr am, Fig. 7.14, it will be appar ent t o you
t hat t he count er funct ions as a fr equency divider. The out put fr equency of flip-flop A is half
t he input fr equency and t he out put of flip-flop B is one-four t h of t he clock input fr equency.
Each flip-flop divides t he input fr equency t o it by 2. A 3-bit count er will t hus divide t he clock
input fr equency by 8.
Anot her impor t ant point about count er s is t heir maximum count capabilit y. It can be
calculat ed fr om t he following equat ion
N = 2
n
– 1
wher e N is t he maximum count number and
n is t he number of flip-flops.
For example if n = 12, t he maximum count capabilit y is
N = 2
12
– 1 = 4095
If you have t o calculat e t he number of flip-flops r equir ed t o have a cer t ain count capabilit y,
use t he following equat ion :
n = 3.32 log
10
N
For example if t he r equir ed count capabilit y is 5000
n = 3.32 log
10
5000 = 12.28
which means t hat 13 flip-flops will be r equir ed.
S hift Registers and Counters 275
C ounting Sp e e d of Rip p le C ounte rs
The primary limit at ion of ripple count ers is t heir speed. This is due t o t he fact t hat each
successive flip-flop is driven by t he out put of t he previous flip-flop. Therefore, each flip-flop in t he
count er cont ribut es t o t he t ot al propagat ion delay. Hence, it t akes an appreciable t ime for an
impulse t o ripple t hrough all t he flip-flops and change t he st at e of t he last flip-flop in t he chain.
This delay may cause malfunct ion, if all t he flip-flops change st at e at t he same t ime. In t he
count er we have just considered, t his happens when t he st at e changes from 011 t o 100 and from
111 t o 000. If each flip-flop in t he count er changes st at e during t he course of a count ing operat ion,
and if each flip-flop has a propagat ion delay of 30 nanoseconds, a count er having t hree flip-flops
will cause a delay of 90 ns. The maximum count ing speed for such a flip-flop will be less t han.
1
90
10
9
×
or 11.11 MHz.
If t he input pulses occur at a r at e fast er t han 90 ns, t he count er out put will not be a
t r ue r epr esent at ion of t he number of input pulses at t he count er. For r eliable oper at ion of
t he count er, t he upper limit of t he clock pulses of t he count er can be calculat ed fr om
f =
1
10
9
n t
×
where n is t he number of flip-flops and
t is t he pr opagat ion delay of each flip-flop.
7.4.3 4- BIT BINARY RIPPLE UP- COUNTER
A 4-bit binar y r ipple up-count er can be built wit h four T-t ype flip-flops. The diagr am will
follow t he same pat t er n as for a 3-bit up-count er. The count -up sequence for t his count er is given
in Table 7.2 and a wavefor m diagr am is given in Fig. 7.15. Aft er t he count er has count ed up t o
Table 7.2 Count-up sequence of a 4-bi t bi nary up-counter
Input pulse Count
2
3
2
2
2
1
2
0
Q
D
Q
C
Q
B
Q
A
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0 RECYCLE
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 or 0 0 0 0 0
276 S witching Theory
1111, it r ecycles t o 0000 like t he 3-bit count er. You must have obser ved t hat each flip-flop divides
t he input fr equency by, 2 and t he count er divides t he fr equency of t he clock input pulses by 16.
C
l
o
c
k
1 0
1 0 1 0 1 0 1 0
Q
A
Q
B
Q
C
Q
D
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Fig. 7.15 Wavefor m for 4-bit binar y up-count er
S hift Registers and Counters 277
7.4.4 3- Bit Bina ry Ripple Down C ounte r
The binar y r ipple up-count er we have just consider ed incr eases t he count by one, each
t ime a pulse occur s at it s input . The binar y r ipple down count er which we ar e going t o
consider in t his sect ion decr eases t he count by one, each t ime a pulse occur s at t he input .
A cir cuit for a 3-bit down count er is given in Fig. 7.16. If you compar e t his count er wit h t he
up-count er in Fig. 7.13 t he only differ ence you will not ice is t hat , in t he down count er in
Fig. 7.16 t he complement out put
Q,
inst ead of t he nor mal out put , is connect ed t o t he clock
input of t he next flip-flop. The count er out put which is r elevant even in t he down count er is
t he nor mal out put , Q, of t he flip-flops.
Q
A
Q
B
Q
C
Q
C
Q
B
Q
A 1 1 1
Clock
Pulses
Q Q Q
T T T
Fig. 7.16 3-bit binar y r ipple down count er
We can now analyze t he cir cuit and examine it s oper at ion. It will help you t o follow t he
oper at ion of t he count er, if you refer t o Table 7.3 and wavefor m of t he count er given in
Fig. 7.17 for each input pulse count . Let us assume t hat t he count er is init ially r eset , so t hat
t he count er out put is 0 0 0. When t he fir st input pulse is applied, flip-flop A will set , and it s
complement out put will be 0. This will set flip-flop B, as t her e will be a 1 → 0 t r ansit ion at
t he clock input . The count er out put will now be 1 1 1.
Table 7.3 Count-down sequence of a 3-bi t bi nary counter
Clock pulse Count
2
2
2
1
2
0
Q
C
Q
B
Q
A
0 0 0 0
1 1 1 1
2 1 1 0
3 1 0 1
4 1 0 0 RECYCLE
5 0 1 1
6 0 1 0
7 0 0 1
8 0 0 0
When t he second clock pulse is applied, flip flop A will r eset and it s complement out put
will become 1, which will not affect t he ot her flip-flops. The count er out put will now be 1 1
0 as shown in r ow 3 of t he Table 7.3.
When t he t hir d clock pulse occur s, flip-flop A will set and it s complement out put will
become 0, which will r eset flip-flop B, it s out put becomes 0, and t he complement out put will
278 S witching Theory
be 1, which will not affect t he ot her flip-flops. The count er will now show an out put of 1 0
1, as in t he four t h r ow of t he t able.
You will not ice t hat ever y clock pulse decr ement s t he count er by 1. Aft er t he eight h clock
pulse, t he count er out put will be 0 0 0 and t he count er will r ecycle t her eaft er.
The wavefor m for t his 3-bit down count er is given in Fig. 7.17.
Fig. 7.17 Wavefor m for 3-bit binar y down-count er.
7.4.5 Up - Down C ounte rs
The count er s which we have consider ed so far can only count up or down; but t hey
cannot be pr ogr ammed t o count up or down. However, t his facilit y can be easily incor por at ed
by some modificat ion in t he cir cuit r y. You might r ecall t hat in an up-count er t he nor mal
out put of a flip-flop is connect ed t o t he clock input of t he following flip-flop, and in a down
count er it is t he complement out put which is connect ed t o t he clock input of t he following
flip-flop. The change fr om nor mal t o complement connect ion t o t he clock input of t he following
flip-flop can be easily managed. A cir cuit for t his pur pose is shown in Fig. 7.18.
The nor mal and complement out put s of flip-flops ar e connect ed t o AND gat es D and E
and t he out put of t he AND gat es goes t o t he clock input of t he next flip-flop via OR gat es F.
When t he up-down cont r ol is binar y 1, gat es D and F ar e enabled and t he nor mal out put of
each flip-flop is coupled via OR gat es F t o t he clock input of t he next flip-flop. Gat es E ar e
inhibit ed, as one input of all t hese gat es goes low because of t he Inver t er. The count er,
t her efor e, count s up.
When t he up-down cont r ol is binar y 0, gat es D ar e inhibit ed and gat ed E ar e enabled.
As a consequence t he complement out put of each flip-flop is coupled via OR gat es F t o t he
clock input of t he next flip-flop. The count er, t her efor e, count s down.
Clock
J Q
Q K
D
E
F CLK
A
J Q
Q K
D
E
F CLK
B
J Q
Q K
CLK
C
Up down
control
Fig. 7.18 Up-down count er
S hift Registers and Counters 279
7.4.6 Re se t a nd Pre se t Func tions
Reset and Pr eset funct ions ar e usually necessar y in most count er applicat ions. When
using a count er you would, in most cases, like t he count er t o begin count ing wit h no pr ior
count s st or ed in t he count er. Reset t ing is a pr ocess by which all flip-flops in a count er ar e
clear ed and t hey ar e t hus in a binar y O st at e. J K flip-flops have a CLEAR or RESET input
and you can act ivat e t hem t o r eset flip-flops. If t her e ar e mor e t han one flip-flop, t he r eset
input s of all flip-flops ar e connect ed t o a common input line as shown in Fig. 7.19.
You will not ice t hat t he r eset input s of all t he flip-flops in t he count er ar e act ive low, and
t her efor e, t o r eset t he count er you t ake t he r eset input line low and t hen high. The out put
of t he count er will t hen be 0 0 0 0.
At t imes you may want t he count er t o st ar t t he count fr om a pr edet er mined point . If you
load t he r equir ed number int o t he count er, it can st ar t count ing fr om t hat point . This can
be easily accomplished by using t he ar r angement shown in diagr am. The pr eset input s of all
t he flip-flops ar e connect ed t o NAND gat e out put s. One input of each NAND gat e is connect ed
t o a common PRESET line and t he desir ed number is fed int o t he ot her input s of t he NAND
gat es. To load a number int o t he count er, fir st clear t he count er and t hen feed t he r equir ed
number int o t he NAND gat es as indicat ed in t he diagr am. When you t ake t he PRESET line
high moment ar ily, t he out put of NAND gat es 1 and 4 will be 1, so flip-flops A and D will
r emain r eset . The out put of gat es 2 and 3 will be 0 and so flip-flops B and C will be set . The
number st or ed in t he count er will now be 0 1 1 0, which is t he number r equir ed t o be loaded
in t he count er.
J Q
K Q
CLK A
PRE
CLR
Counter
Input
Reset
Q
A
1
J Q
K Q
CLK B
PRE
CLR
Q
B
2
J Q
K Q
CLK C
PRE
CLR
Q
C
3
J Q
K Q
CLK D
PRE
CLR
Q
D
4
Preset
+V
CC
0 1 1 0
Fig. 7.19
It is also possible t o load a number in a count er in a single oper at ion, by using t he
ar r angement shown in Fig. 7.20.
The ar r angement for dat a t r ansfer, which is a single pulse oper at ion makes use of t he
Pr eset and Clear input s of t he flip-flops. When t he clock pulse is low, t he out put of bot h
NAND gat es 1 and 2 is high, which has no effect on t he Pr eset and Clear input s of t he flip-
flop and t her e is no change in it s out put . If t he D
0
input is high, t he out put of NAND gat e
1 will go low when t he clock pulse goes high. This will r esult in out put Q
A
going high at t he
same t ime. Since one input of NAND gat e 2 will be low at t his t ime, t he clear input t o t he
flip-flop r emains high.
280 S witching Theory
2 1
J Q
K Q
CLK A
PRE
CLR
Q
A
D
0
J Q
K Q
CLK B
PRE
CLR
D
1
J Q
K Q
CLK C
PRE
CLR
D
2
J Q
K Q
CLK D
PRE
CLR
D
3
Q
B
Q
C
Q
D
Clock
Input
Fig. 7.20 Single pulse dat a t r ansfer
If t he D
0
input is low and t he clock pulse goes high, t he out put of NAND gat e 1 will
r emain high, which will have no effect on t he Pr eset input . The out put of NAND gat e 2 will
go low, which will clear t he flip-flop and Q
A
will go low.
7.4.7 Unive rsa l Sync hronous C ounte r Sta g e
The up and down count er s which we have consider ed so far ar e asynchr onous count er s,
also known as r ipple count er s, for t he simple r eason t hat , following t he applicat ion of a clock
pulse, t he count r ipples t hr ough t he count er, since each successive flip-flop is dr iven by t he
out put of t he previous flip-flop. In a synchronous count er all flip-flops are driven simult aneously
by t he same t iming signal.
The asynchr onous count er, t her efor e, suffer s fr om speed limit at ion as each flip-flop
cont r ibut es t o t he t ot al pr opagat ion delay. To over come t his dr aw-back, flip-flops wit h lower
pr opagat ion delay can be used; but t he ideal solut ion is t o use synchr onous count er s. In t hese
count er s t he cir cuit is so ar r anged t hat t r igger ing of all flip-flops is done simult aneously by
t he input signal, which is t o be count ed. In t hese count er s t he t ot al pr opagat ion delay is t he
delay cont r ibut ed by a single flip-flop.
J
K
CLK A
Q
Q
1
CLK
CLR
1 2
Q
A
J
K
CLK B
Q
Q
Q
B
J
K
CLK C
Q
Q
Q
C
J
K
CLK D
Q
Q
Q
D
Fig. 7.21 (a) Synchr onous count er
The design concept used in t he synchr onous count er shown in Fig. 7.21 (a) uses count er
st age blocks and t his design concept lends it self t o building lar ge synchr onous count er s.
Count er modules of t he t ype used in t his cir cuit and also shown separ at ely in Fig. 7.21 (b)
can be int er connect ed t o build count er s of any lengt h.
S hift Registers and Counters 281
J
K
CLK
Q
Q
Carry
Input
Carry
Output
Clock
Fig. 7.21 (b) Univer sal count er st age block.
Let us consider t he synchr onous count ing cir cuit shown in Fig. 7.21(a). It is a 4-bit
count er and t he clock input s of all t he flip-flops ar e connect ed t o a common clock signal,
which enables all flip-flops t o be t r igger ed simult aneously. The Clear input s ar e also connect ed
t o a common Clear input line. The J and K input s of each flip-flop ar e connect ed t oget her,
so t hat t hey can t oggle when t he J K input is high. The J K input of flip-flop A is held high.
Also not ice t he t wo AND gat es 1 and 2, and t he way t hey ar e connect ed. Gat e 1 ensur es t hat
t he J K input t o flip-flop C will be binar y 1 when bot h input s Q
A
and Q
B
ar e binar y 1. AND
gat e 2 ensur es t hat t he J K input t o flip-flop D will be binar y 1 only when out put s Q
A
, Q
B
and
Q
C
ar e binar y 1.
We can now look int o t he out put st at es r equir ed for t he flip-flops t o t oggle. This has been
summar ized below :
1. Flip-flop A t oggles on negat ive clock edge.
2. Flip-flop B t oggles when Q
A
is 1
3. Flip-flop C t oggles when Q
A
and Q
B
ar e 1
4. Flip-flop D t oggles when Q
A
, Q
B
ar e Q
C
ar e 1
This means t hat a flip-flop will t oggle only if all flip-flops pr eceding it ar e at binar y
1 level.
We can now look int o t he count ing pr ocess of t his count er. We begin by r eset t ing t he
count er, which is done by t aking CLR t empor ar ily low.
MSB LSB
Q
D
Q
C
Q
B
Q
A
0 0 0 0
Since Q
A
is low and J and K ar e high, t he fir st negat ive clock edge will set flip-flop A.
The count er out put will now be as follows:
Q
D
Q
C
Q
B
Q
A
0 0 0 1 Aft er 1st clock pulse.
When t he second negat ive clock edge occur s, both A and B flip-flops will t oggle and t he
count er out put will change t o t he following:
Q
D
Q
C
Q
B
Q
A
0 0 1 0 Aft er 2nd clock pulse.
282 S witching Theory
When t he t hir d clock pulse ar r ives, flip-flop B will not t oggle as Q
A
is 0 but flip-flop A
will t oggle. The count er will show t he following out put .
Q
D
Q
C
Q
B
Q
A
0 0 1 1 Aft er 3r d clock pulse.
The four t h clock pulse will t oggle flip-flops A, B and C, as bot h Q
A
and Q
B
ar e 1. The
count er out put is now as follows:
Q
D
Q
C
Q
B
Q
A
0 1 0 0 Aft er 4t h clock pulse.
The count er will cont inue t o count in t he binar y syst em unt il t he count er out put r egist er s
1 1 1 1, when it will be r eset by t he next clock pulse and t he count ing cycle will be r epeat ed.
7.4.8 Sync hronous C ounte r IC s
Many t ypes of count er ICs ar e available and it is ver y likely t hat one of t hese will meet
your design r equir ement s. You may not , t her efor e, find it necessar y t o design your own
count er. However, should t hat become necessar y, a var iet y of J K flip-flops ar e available, wit h
which you can design one t o meet your specific needs.
Some of t he count er ICs available ar e list ed below :
Counter type Parallel load IC No.
1 Decade Up Synchr onous 74160
Synchr onous 74162
2 Decade Up/Down Synchr onous 74168
Synchr onous 74ALS568
Asynchr onous 74ALS190
Asynchr onous 74ALS192
3 4-bit binar y Up count er Synchr onous 74161
Synchr onous 74163
4 4-bit binar y Up/Down Synchr onous 74169
count er Asynchr onous 74191
Asynchr onous 74193
Asynchr onous 74ALS569
All t he count er s list ed her e have par allel load capabilit y, which implies t hat a binar y dat a
input applied t o t he count er will be t r ansfer r ed t o t he out put when t he load input on t he count er
is asser t ed. The load oper at ion may be synchr onous or asynchr onous. If it is asynchr onous, t he
dat a applied will be t r ansfer r ed t o t he out put as soon as t he load input is asser t ed.
In case it is synchr onous, t he dat a will not be t r ansfer r ed t o t he out put unt il t he next
clock pulse occur s. In eit her case t he count er s will begin t o count fr om t he loaded count when
clock pulses ar e applied.
The decade up-count er s count fr om 0000 t o 1001. Decade up-and down-count er s can be
pr ogr ammed t o count fr om 0000 t o 1001, or fr om 1001 t o 0000. 4-Bit binar y count er s in t he
up-count mode count fr om 0000 and 1111 and in t he down-count mode count fr om 1111 t o 0000.
S hift Registers and Counters 283
We will now discuss t he facilit ies available in count er IC 74193 and it s operat ing procedures.
Pin connect ions for t his IC ar e given in Fig. 7.22. Fig. 7.23(a) gives it s t r adit ional symbol and
Fig. 7.23 (b) gives t he IEEE/IEC symbol.
7.4.8.1 C ounte r Func tions
Cle a r ( Re se t) Func tion
As t he Clear input is act ive high, it is nor mally held low. To clear t he count er it is t aken
high moment ar ily.
Fig. 7.22 Pin connect ions for IC 74193
8 16 3 2 6 7
14 11 15 1 10 9
CLEAR LOAD A B C D
DOWN
UP
5
4
CO
BO
12
13
GND V
CC
Q
A
Q
B
Q
C
Q
D
74193
Fig. 7.23 (a) Tr adit ional symbol for IC 74193
Loa d ( Pre se t) Func tion
To load t he count er wit h a pr edet er mined 4-bit binar y number, it is fed int o t he par allel
dat a input s A, B and C and D. The number is shift ed int o t he count er by t aking t he LOAD
input moment ar ily low. Bot h Clear and LOAD input s ar e asynchr onous and will over r ide all
synchr onous count ing funct ions.
284 S witching Theory
CLR
UP
14
5
DOWN
4
11
LOAD
15
1
10
9
A
B
C
D
3D 1
2
4
8
3
2
6
7
Q
Q
Q
Q
A
B
C
D
13
12
CO
BO
1 CT = 15
2 CT = 0
CT = 0
2 +
G1
1–
G2
G3 74193
Fig. 7.23 (b) IEEE/IEC symbol for IC 74193
Ca rry out ( C O ) a nd Borrow Out ( BO ) Func tions
These input s ar e used t o dr ive t he next IC74193, if a lar ger count capabilit y is r equir ed.
While cascading t hese count er s, t he
CO and BO
out put s of a pr evious count er ar e connect ed
t o t he UP and Down input s r espect ively, of t he next count er in t he chain.
Up- c ounting Func tion
For count ing up, t he count er is connect ed as shown in Fig. 7.24. In t he up-count ing mode
t he car r y out put
CO
r emains high, unt il t he maximum count 1111 is r eached, when t he car r y
out put goes low. At t he next clock pulse t he count er out put falls t o 0 0 0 0 and t he car r y out put
CO goes high. If t her e is anot her IC in cascade, it will be incr ement ed fr om 0 0 0 0 t o 0 0 0 1.
8 16 3 2 6 7
14 11 15 1 10 9
CLEAR LOAD A B C D
DOWN
UP
5
4
CO
BO
12
13
GND V
CC
Q
A
Q
B
Q
C
Q
D
74193
+5V
Clock
+5V
Fig. 7.24 Count er connect ed t o count up
Down- c ounting Func tion
For down-count ing connect ion ar e made as shown in Fig. 7.25. In t he down-count ing
oper at ion t he bor r ow out put
BO
st ays high unt il t he minimum count 0 0 0 0 is r eached, when
t he borrow out put BO dr ops low. The bor r ow out put det ect s t he minimum count er value.
At t he next input pulse t he count er out put r ises t o 1 1 1 1 and t her e is a 0 → 1 t r ansit ion
at t he borrow out put
BO
. If anot her count er is connect ed in cascade it will be decr ement ed.
S hift Registers and Counters 285
8 16 3 2 6 7
14 11 15 1 10 9
CLEAR LOAD A B C D
DOWN
UP
5
4
CO
BO
12
13
GND V
CC
Q
A
Q
B
Q
C
Q
D
74193
+5V
+5V
Clock
Fi g. 7.25 Count er connect ed t o count down
Pre se tting ( Up- Counting Mode )
The count er can be pr eset t o any 4-bit binar y number, which is fir st fed int o t he par allel
inputs A, B, C and D, and t he load input is held low moment ar ily, which shift s t he number
int o t he count er. It is not necessar y t o r eset t he count er befor e pr eset t ing it . Let us suppose
t hat t he number shift ed int o t he count er 1 0 1 0 and t he count er is made t o count up. The
count er out put will be st epped up aft er each input pulse and aft er t he 6t h pulse t he out put
will be 0 0 0 0. The count ing up begins fr om t he number pr eset in t he count er and t he 6t h
pulse r eset s t he count er and t hen it st ar t s count ing up fr om t his point .
Pre se tting ( Down- Counting Mode )
The count er is set up in t he down-count ing mode and, as befor e, suppose t he number
fed int o t he count er is 1 0 1 0 and t he count er is made t o count down. The 10t h, input pulse
will r eset t he count er t o 0 0 0 0 and t he 11t h, pulse will show a count of 1 1 1 1 and t hen
it will begin t o count down fr om t his number.
Pre se tting ( Using Counte r Output)
The count er can also be pr eset by connect ing it as shown in Fig. 7.26. The desir ed
number, say 1 0 1 0 is fed int o t he A B C D input s and t he count er input is connect ed t o a
1 Hz clock signal when t he count er r eaches t he maximum, count , 1 1 1 1, t he NAND gat e
out put will go low and t he binar y number 1 0 1 0 will be shift ed int o t he count er. The count er
will now begin t o count up fr om t his pr eset number and when t he count again r eaches 1 1
1 1, t he count er will r et ur n t o t he pr eset number 1 0 1 0 and will again begin t o count up
as befor e. You will not ice t hat as soon as t he count er r eaches t he maximum count 1 1 1 1
(or decimal 15), it is immediat ely pr eset t o 1 0 1 0 (or decimal 10). Since st at e 15 is being
used t o pr eset t he count er, it is no longer a st able st at e. The st able st at es in t his count ing
oper at ion will be 10, 11, 12, 13 and 14, and t he modulus (number of discr et e st at es) of t he
count er will be 5.
The count er modulus in t he up-count ing mode for any pr eset number n is given by
Modulus = 16 – n – 1
In t his case Modulus = 16 – 10 – 1 = 5
286 S witching Theory
Fig. 7.26 Pr eset t ing using count er out put
In t he down-count ing mode, t he count er will count down fr om t he pr eset number, 1010
(or decimal 10). As befor e t he count er will count down as follows; 9, 8, 7, 6, 5, 4, 3, 2, 1, 0.
In t his case t he count er modulus will be as follows :
Modulus = n + 1
In t his case Modulus = 10 + 1 = 11
When t he count er is pr eset in t his manner, it should never be pr eset t o number 15 as
t his is not a st able st at e, and it is likely t o get lat ched up in t his st at e.
Modulo N Counte r Using IC 74193
In Sec. 7.4.8 you have seen how t his IC can count up or down fr om a pr eset number.
In fact it can funct ion as a modulo count er by using a NAND gat e t o pr eset t he count er t o
t he desir ed number. Ther e is a simpler way of implement ing a modulo count er wit h t his IC,
but it has some dr awbacks which we will discuss shor t ly. A cir cuit for a modulo count er using
t his IC in t he down-count ing mode is given in Fig. 7.27.
8 16 3 2 6 7
14 11 15 1 10 9
CLEAR LOAD A B C D
DOWN
UP
5
4
CO
BO
12
13
GND V
CC
Q
A
Q
B
Q
C
Q
D
74193
+5V
Clock
Fig. 7.27 IC 74193 connect ed as a modulus count er
S hift Registers and Counters 287
Clock pulses ar e applied at t he down-count input and t he up-count input is held high. Also
obser ve t hat t he bor r ow out put
BO
is connect ed t o t he load input . The bor r ow out put det ect s
t he st at e of t he bor r ow out put when t he count r eaches 0 0 0 0. Since it is connect ed back
t o t he load input , t he binar y number loaded int o t he A B C D input s is shift ed int o t he
count er. The decimal number loaded int o t he count er r epr esent s it s modulus.
To oper at e t he count er load, t he binar y equivalent of t he decimal number r epr esent ing
t he r equir ed modulus int o t he ABCD input s and apply clock pulses at t he down-count input .
If t he binar y number loaded int o t he count er is 1 0 0 0 (decimal 8) and t he count er is
decr ement ed wit h clock pulses, t he modulus number t hat is 1 0 0 0 will be loaded int o t he
count er, as soon as t he out put r eaches t he st at e 0 0 0 0. It will again count down t o 0 0 0
0 and will again be pr eset t o 1 0 0 0.
You must have r ealized t hat as soon as t he pr eset number is loaded int o t he count er,
t he bor r ow out put , t hat is 0 0 0 0 will disappear. It is impor t ant , t her efor e, t hat t he bor r ow
out put st at e, 0 0 0 0, must be of sufficient dur at ion t o enable t he pr eset number t o be shift ed
int o t he count er. This implies t hat t he pr opagat ion delay of t he gat es r esponsible for pr eset t ing
t he count er t o t he number at t he A B C D input s must be of shor t er dur at ion t han t he
dur at ion of t he clock pulse. To a cer t ain ext ent t his can be ensur ed by int r oducing some delay
bet ween t he bor r ow out put and t he load input . This can be done by connect ing an even
number of inver t er s bet ween t he bor r ow out put BO and t he load input .
7.4.9 M od ulus C ounte rs
The modulus of a count er, as discussed befor e, is t he number of discr et e st at es a count er
can t ake up. A single flip-flop can assume only t wo st at es 0 and 1, while a count er having t wo
flip-flops can assume any one of t he four possible st at es. A count er wit h t hr ee flip-flops will
have 8 st at es and so on. In shor t t he number of st at es is a mult iple of 2. Wit h n flip-flops
t he number of possible st at es will be 2
n
. Thus by building count er s which count in t he nor mal
binar y sequence, we can build count er s wit h modulus of 2, 4, 8, 16 et c. In t hese count er s t he
count incr eases or decr eases by 1 in pur e binar y sequence. The pr oblem ar ises in building
count er s whose modulus is 3, 5, 7, 9 et c. For inst ance, if we need, a count er wit h a modulus
of 3, we have t o use a count er wit h a modulus of 4 and so ar r ange t he cir cuit t hat it skips
one of t he st at es. Similar ly, for a count er wit h a modulus of 5 we r equir e 2
3
or 8 st at es and
ar r ange t he cir cuit so t hat it skips 3 st at es t o give us a modulus of 2
n
– 3 or 5 st at es. Thus
for a modulus N count er t he number n of flip-flops should be such t hat n is t he smallest
number for which 2
n
> N. It , t her efor e, follows t hat for a decade (mod-10) count er t he number
of flip-flops should be 4. For t his count er we shall have t o skip 2
4
– 10 or 6 st at es. Which
of t hese st at es ar e t o be skipped is a mat t er of choice, which is lar gely gover ned by decisions
which will make t he cir cuit as simple as possible.
Many methods have been developed for designing such counters. We will consider the following:
( 1) Counte r Re se t Me thod
In t his met hod t he count er is r eset aft er t he desir ed count has been r eached and t he
count cycle st ar t s all over again fr om t he r eset st at e.
( 2) Logic Ga ting Me thod
This met hod pr ovides t he exact count sequence r equir ed wit hout any need t o r eset t he
count er at some st age.
288 S witching Theory
( 3) Counte r Coupling Me thod
This met hod is used t o implement count er s of t he r equir ed modulus. For inst ance we
can int er connect mod-2 and mod-3 count er s t o implement a modulus 3 × 2 or mod-6 count er.
7.4.10 C ounte r Re se t M e thod ( Async hronous C ounte rs)
Let us fir st consider t he t ypical case of a count er which has 3 st at es as shown in
Fig. 7.28.
7.4.10.1 Mod- 3 Counte r
0
2 1
Fig. 7.28 St at e diagr am for a mod-3 count er
It is obvious t hat a mod-3 count er will r equir e t wo flip-flops which, when connect ed as
a count er, will pr ovide four st at es as shown in Table 7.4.
Table 7.4 States for a two fli p-flop counter
Q
A
Q
B
Count value
LS B (Decimal)
0 0 0
1 0 1
0 1 2
1 1 3
0 0 0
This count er count s in t he binar y sequence 0, 1, 2, 3 and t hen it r et ur ns t o 0, t he
st ar t ing point . Each count is r efer r ed t o as a st at e. If we ar e building a mod-3 count er, t he
most convenient solut ion is t o skip st at e 3 and t hen r et ur n t o st at e 0 fr om st at e 2 and t hen
again go t hr ough st at es 0, 1, 2 befor e r et ur ning t o st at e 0. What we need is a combinat ional
logic cir cuit , which will feed a r eset pulse t o t he count er dur ing st at e 3, and immediat ely aft er
st at e 2, which is t he last desir ed st at e. This r eset pulse is applied t o t he CLR input s which
r eset s t he count er t o 0 aft er st at e 2.
A cir cuit diagr am for a mod-3 count er t oget her wit h t he r equir ed combinat ional logic is
given in Fig. 7.29.
When bot h out put s Q
A
and Q
B
ar e 1, t he out put of t he NAND gat e, which pr ovides t he
r eset pulse, goes low and bot h t he flip-flops ar e r eset . The count er r et ur ns t o st at e 0 and it
st ar t s count ing again in 0, 1, 2, 0 sequence. The wavefor ms for t his count er ar e given in
Fig. 7.30.
S hift Registers and Counters 289
Fi g. 7.29 Modulo-3 count er
Fig. 7.30 Wavefor m for Mod-3 count er
7.4.10.2 Mod- 5 Counte r
The minimum number of flip-flops r equir ed t o implement t his count er is t hr ee. Wit h
t hr ee flip-flops, t he number of st at es will be 8. A modulo-5 count er will have only 5 st at es.
A st at e diagr am for t his count er is given in Fig. 7.31. It will pr ogr ess fr om st at e 000 t hr ough
100. The t r ut h t able for t his count er, which will det er mine t he st age at which t he r eset pulse
should be applied, is given in Table 7.5.
0
4
3 2
1
001
010 011
100
000
Fig. 7.31 St at e diagr am for Mod-5 count er
290 S witching Theory
The t r ut h t able shows t hat st at e 5 will be t he r eset st at e and t hat st at es 6 and 7 will
be t he don’t car e st at es. The next st ep is t o plot t he st at es on a map as shown in Fig. 4.39.
Table 7.5 Truth table for Mod-5 Counter
Q
A
Q
B
Q
C
State
LS B
0 0 0 0
1 0 0 1
0 1 0 2
1 1 0 3
0 0 1 4
1 0 1 5
0 1 1 6 X
1 1 1 7 X
X, Don’t car e st at es
0
0
0
4
X
6
0
2
A 0
0
1
1
5
X
7
0
3
A 1
B C B C
00 01
B C
11
B C
10
Fig. 7.32
The map shows t hat t he r eset pulse is det er mined by
R = Q Q Q A B C . . .
The logic diagr am
for t his count er is given in Fig. 7.33. The diagr am shows t hat a r eset pulse will be applied
when bot h A and C ar e 1. You may have not iced t hat t he r eset pulse shown in Fig. 7.30 for
t he Mod-3 count er was ver y nar r ow and in some cases it may not be suit able t o cont r ol ot her
logic devices associat ed wit h t he count er. The Mod-5 count er cir cuit Fig. 7.33 incor por at es an
RS flip-flop, which pr oduces a r eset pulse, t he widt h of which is equal t o t he dur at ion for
which t he clock pulse is low. The way it wor ks is like t his. St at e 5 is decoded by gat e D, it s
out put goes low, t he RS flip-flop is set , and out put
Q
goes low, which r eset s all t he flip-flops.
The leading edge of t he next clock pulse r eset s t he RS flip-flop,
Q
goes high which r emoves
t he r eset pulse. The count er t hus r emains r eset for t he dur at ion of t he low t ime of t he clock
pulse. When t he t r ailing edge of t he same clock pulse ar r ives, a new cycle is st ar t ed. The
wavefor m for Mod-5 count er is given in Fig. 7.34.
S hift Registers and Counters 291
Fi g. 7.33 Modulus-5 count er
1
0
1
0
1
0
1
0
1
0
1 2 3 4 5 6 7
0 1 0 1 0 0 1 0
0 0 1 1 0 0 0 1
0 0 0 0 1 0 0 0
0 1 2 3 4 0 1 2
Counter
State
Reset
Pulse
Q
C
Q
B
Q
A
Clock
Pulse
Counter in Reset
State EOR this period
Fig. 7.34 Wavefor m for Modulus-5 asynchr onous count er
7.4.10.3 Mod- 10 ( De c a de ) Counte r
The decade count er discussed her e is also an asynchr onous count er and has been
implement ed using t he count er r eset met hod. As t he decade count er has t en st at es, it will
r equir e four flip-flops t o implement it . A st at e diagr am for t his count er is given in Fig. 7.35
and t he t r ut h t able is given in Table 7.6.
292 S witching Theory
0 1
2
3
4
5
6
7
8 9
Last desired
State
Counter guided
to State 0 by
External Logic
Fig. 7.35 St at e diagr am for decade count er
Table 7.6 Truth table for decade counter
Q
A
Q
B
Q
C
Q
D
S tate
LS B
0 0 0 0 0
1 0 0 0 1
0 1 0 0 2
1 1 0 0 3
0 0 1 0 4
1 0 1 0 5
0 1 1 0 6
1 1 1 0 7
0 0 0 1 8
1 0 0 1 9
0 1 0 1 10
1 1 0 1 11 X
0 0 1 1 12 X
1 0 1 1 13 X
0 1 1 1 14 X
1 1 1 1 15 X
The t able shows t hat st at e 9 will be t he last desir ed st at e and st at e 10 will be t he r eset
st at e. St at e 11, 12, 13, 14 and 15 will be t he don’t car e st at es. The next st ep is t o plot t he
st at es on a map t o det er mine t he r eset pulse. This has been done in Fig. 7.36.
The map shows t hat t he r eset pulse is det er mined by t he following expr ession:
R = Q Q Q Q
A B C D
. . .
S hift Registers and Counters 293
Fig. 7.36
The decade count er cir cuit Fig. 7.37 is essent ially a binar y r ipple count er, which can
count fr om 0000 t o 1111; but since a decade count er is r equir ed t o count only fr om 0000 t o
1001, a r eset pulse is applied at count 10 when t he count er out put is Q Q Q Q A B C D . . . . In or der
t o have cont r ol over t he r eset pulse widt h, a 4-input NAND gat e is used t o decode st at e 10.
Fig. 7.37 Decade (Mod-10) asynchr onous count er using count r eset and pulse widt h cont r ol.
294 S witching Theory
To decode count 10, logic input s t hat ar e all one at t he count of 10, ar e used t o feed t he NAND
gat e. At t his count t he NAND gat e out put goes low pr oviding a 1 → 0 change which t r igger s
t he one-shot unit . The
Q
out put of t he one shot unit is used, as it is nor mally high and it
goes low dur ing t he one-shot t iming per iod, which depends on t he RC const ant s of t he cir cuit .
The t iming per iod of t he one-shot can be a adjust ed, so t hat t he slowest count er st at e r eset s.
Alt hough only A and D flip-flops need t o be r eset , t he r eset pulse is applied t o all t he flip-flop
t o make doubly sur e t hat all flip-flops ar e r eset .
1 0
1
2
3
4
5
6
7
8
9
Q
C
Q
B
Q
A
C
l
o
c
k
P
u
l
s
e
1
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1 0 1 0 1 0
Q
D
1 0 1 0
0
1
2
3
4
5
6
7
8
9
0
C
o
u
n
t
e
r
S
t
a
t
e
R
e
s
e
t
P
u
l
s
e
F
i
g
.

7
.
3
8

W
a
v
e
f
o
r
m

f
o
r

d
e
c
a
d
e

c
o
u
n
t
e
r
S hift Registers and Counters 295
Since decade (Modulus-10) count er s have 10 discr et e st ar t s, t hey can be used t o divide
t he input fr equency by 10. You will not ice t hat at t he out put of t he D-flip-flop, t her e is only
one out put pulse for ever y 10 input pulses. These count er s can be cascaded t o incr ease count
capabilit y.
The wavefor m for t his count er is shown in Fig. 7.38.
7.4.11 Log ic G a ting M e thod
The count er r eset met hod of implement ing count er s, which we have discussed in t he
pr evious sect ion, has some inher ent dr awbacks. In t he fir st place, t he count er has t o move
up t o a t empor ar y st at e befor e going int o t he r eset st at e. Secondly, pulse dur at ion t iming is
an impor t ant consider at ion in such count er s, for which pur pose special cir cuit s have t o be
incor por at ed in count er design.
We will now consider anot her appr oach t o count er design, which pr ovides for t he exact
count sequence. We will discuss t he design of some modulus count er s t o illust r at e t he
pr ocedur es.
7.4.11.1 Mod- 3 Counte r ( Sync hronous)
Let us suppose t hat we ar e r equir ed t o design a modulo-3 count er which confor ms t o t he
t rut h t able given in Table 7.7.
Table 7.7 Truth table for Mod-3 Counter
Input pulse count Counter states
A B
0 0 0
1 1 0
2 0 1
3 0 0
Based on t his t r ut h t able, t he out put wavefor m for t his Mod-3 count er should be as
shown in Fig. 7.39.
1 2 3 4
0 1 0 0 1
0 0 1 0 0
1
0
1
0
1
0
Clock
A
B
Fig. 7.39 Wavefor m for Mod-3 count er
You will not ice fr om t he wavefor m of t he count er, t hat flip-flop A t oggles on t he t r ailing
edge of t he fir st and second pulses. Also obser ve t hat flip-flop B t oggles only on t he second
296 S witching Theory
and t hir d clock pulses. We have t o bear t his in mind, in figur ing out logic levels for t he J and
K input s of t he flip-flops.
Suppose t hat init ially bot h t he flip-flops ar e r eset . Since flip-flop A has t o t oggle when t he
t r ailing edges of t he fir st and t he second clock pulses ar r ive, it s J and K input s should be at
logic 1 level dur ing t his per iod. This is achieved by connect ing t he K input t o logic 1 level
and t he J input t o t he complement out put of flip-flop B, as dur ing t his per iod t he B out put
of flip-flop B is at a high logic level. In t his sit uat ion, t he fir st clock pulse pr oduces a logic
1 out put and t he second clock pulse pr oduces a logic 0 out put .
The J input of flip-flop B is connect ed t o t he nor mal out put of flip-flop A. Ther efor e, when
t he fir st clock pulse ar r ives, t he J input of flip-flip B is low. It s out put will r emain low as you
will not ice fr om t he t r ut h t able and t he wavefor m. The second pulse is r equir ed t o t oggle t his
flip-flop and it s K input is, t her efor e held high. When t he second clock pulse ar r ives, t he flip-
flop will t oggle as bot h t he J and K input s ar e high. The out put will go high. At t he same
t ime it s complement out put will be low, which makes t he J input of flip-flop A low.
When t he t hir d clock pulse ar r ives, t he out put of flip-flop A will go low. Since aft er t he
second clock pulse t he out put of flip-flop A was alr eady low, t he t hir d clock pulse pr oduces a
low out put at flip-flop B. Both the A and B flip-flops ar e now r eset and t he cycle will be
r epeat ed.
A logic diagr am for t he Mod-3 count er is given in Fig. 7.40.
A
A
K
A
J
A
CLK
B
B
K
B
J
B
CLK
1
Clock
A B
1
Fig. 7.40 Mod-3 count er (Synchr onous)
7.4.11.2 Mod- 5 Counte r ( Async hronous)
We will use t he same pr ocedur e t o design a mod-5 count er as befor e. The t r ut h t able
r equir ed for t his count er is given in Table 7.8.
Table 7.8 Truth table for Mod-5 counter
Input pulse Counter states
count A B C
0 0 0 0
1 1 0 0
2 0 1 0
3 1 1 0
4 0 0 1
5 0 0 0
S hift Registers and Counters 297
The wavefor m for t his count er based on t his t r ut h t able is given in Fig. 7.41. You will
not ice fr om t he t r ut h t able and t he waveform t hat t he A flip-flop complement s each input
pulse, except when t he nor mal out put of flip-flop C is logic 1, which is so aft er t he t r ailing
edge of t he 4t h, clock pulse. It , t her efor e, follows t hat t he K input of flip-flop A should be a
const ant logic 1 and t he J input should be connect ed t o t he complement out put of flip-flop will
be 0 when C is 1 so t hat t he out put of flip-flop A r emains low aft er t he t r ailing edge of t he
5t h clock pulse.
If you obser ve t he changing pat t er n of t he out put of t he B flip-flop, you will not ice t hat
it t oggles at each t r ansit ion of t he A out put from 1 → 0. It is, t her efor e, obvious t hat t he A
out put should be connect ed t o t he clock input of t he B-flip-flop and t he J and K input s of t his
flip-flop should be at logic 1 level.
1 2 3 4 5
0 1 0 1 0 0
0 0 1 1 0 0
1
0
1
0
1
0
Clock
A
B
0 0 0 0 1 0
1
0
C
Fig. 7.41 Wavefor m for Mod-5 count er
Aft er t he 3r d clock pulse, t he out put s of A and B flip-flops ar e 1. An AND gat e is used
t o make t he J input t o flip-flop C as 1 when bot h A and B ar e 1. The K input t o flip-flop C
is also held at logic 1 t o enable it t o t oggle. The clock is also connect ed t o t he clock input
t o flip-flop C, which t oggles it on t he 4t h, clock pulse and it s out put becomes 1. When t he
5t h, clock pulse ar r ives, t he J input t o flip-flop C is 0 and it r eset s on t he t r ailing edge of t his
clock pulse. Ther eaft er t he cycles ar e r epeat ed. The logic diagr am for t he mod-5 count er is
given in Fig. 7.42.
Fig. 7.42 Logic diagr am for Mod-5 count er
298 S witching Theory
7.4.11.3 Mod- 10 ( De c a de ) Counte r ( Async hronous)
The t r ut h t able for a Decade count er is given in Table 7.9.
Table 7.9 Truth Table for Decade counter
Input pulse Counter states
count A B C D
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 (0) 0 0 0 0
The wavefor m for t his count er based on t his t r ut h t able is given in Fig. 7.43.
1
0
1 2 3 4 5 6 7 8 9
C
B
A
Clock 10
0 1 0 1 0 1 0 1 0 1 0
0 0 1 1 0 0 1 1 0 0 0
0 0 0 0 1 1 1 1 0 0 0
0 0 0 0 0 0 0 0 1 1 0 D
1
0
1
0
1
0
1
0
Fig. 7.43 Wavefor m for Decade Count er
If you compare t rut h Table 7.9 for t he Decade count er wit h Table 7.2 which gives t he
count -up sequence for a 4-bit binar y up-count er, you will not ice a close similar it y bet ween t he
t wo, up t o input pulse 8. You will also not ice a close r esemblance bet ween wavefor ms of
Fig. 7.43 and Fig. 7.15 up t o a cer t ain point .
The count r ipples t hr ough t he A, B and C flip-flops for t he fir st seven input pulses, as
in t he st andar d 4-bit binar y up-count er. At t his point t he count er will show an out put of 1 1
1 0 (decimal 7). On t he applicat ion of t he 8t h pulse, flip-flops A, B and C must r eset and t he
D out put should be 1, t hat is t he count er st at e should change fr om 1 1 1 0 t o 0 0 0 1. In or der
t hat t he J input t o flip-flop D is 1, so t hat when K is 1 t he D flip-flop out put goes fr om 0 t o
S hift Registers and Counters 299
1; B and C out put s ar e applied t o t he input of an AND gat e and it s out put goes t o t he J input .
In or der t hat t he B and C out put s ar e 0, when D out put is 1 for t he 8t h and t he 9t h count ,
t he complement out put of t he D flip-flop which will be 0 when D is 1, is connect ed t o t he J
input of t he B flip-flop.
Aft er t he t r ailing edge of t he 8t h pulse D becomes 1 and A, B and C become 0, t he 9t h
pulse is r equir ed t o change t he out put fr om 0 0 0 1 t o 1 0 0 1. Since no change is r equir ed
in t he D out put , t he D-flip-flop is t r igger ed by t he A out put . When t he 9t h pulse ar r ives, t he
A out put changes fr om 0 t o 1, but t his causes no change in t he D out put . When t he 10t h input
pulse ar r ives, it changes t he A out put fr om 1 t o 0, which changes t he D out put fr om 1 t o 0.
The count er out put changes fr om 1 0 0 1 t o 0 0 0 0. Dur ing t he 9t h and t he 10t h pulses, t he
B and C out put s will r emain unchanged.
A logic diagr am for t he Decade count er is given in Fig. 7.44.
Fig. 7.44 Logic diagr am for Decade count er
7.4.12 De sig n of Sync hronous C ounte rs
In most of t he count er designs we have considered so far, t he flip-flops are not t riggered
simult aneously. In synchronous count ers all st ages are t riggered at t he same t ime. The out put
of each st age depends on t he gat ing input s of t he st age. If you refer t o previous count er designs,
you will observe t hat t he gat ing input s have been assigned values t o give t he desired out put s.
The basic framework of a synchronous count er would be somewhat like t he part ial logic
diagram given in Fig. 7.45. You will not ice t hat all t he clock input s are connect ed t o a common
line and t he J and K input s of t he flip-flops have been left open. They are required t o have t he
values necessary t o give t he required out put s aft er each input pulse. The J and K input s of each
flip-flop are t herefore required t o have t he values which produce t he desired count er st at es at
each input pulse. The ent ire purpose of t he exercise is t o det ermine t he input values for each
st age. A t ypical design procedure can be summed up in t he following st eps.
Q
A
K
A
J
A
CLK A
A
Q
A
Q
B
K
B
J
B
CLK B
B
Q
B
Clock
Fig. 7.45
300 S witching Theory
(a) Wr it e t he desir ed t r ut h t able for t he count er.
(b) Wr it e t he count er t r ansit ion t able which should list t he st ar t ing st at e and t he
subsequent st at es t he count er is r equir ed t o t ake up.
(c) Wit h t he help of t he excit at ion t able and using t he count er t r ansit ion t able, wr it e
down t he input values for t he J and K input s t o enable each flip-flop t o at t ain t he
out put st at e as r equir ed by t he t r ansit ion t able.
(d) Pr epar e Kar naugh maps for t he J and K input s of each st age.
(e) Der ive Boolean algebr a expr essions for each of t he input s t o t he flip-flops.
(f) Dr aw t he synchr onous count er cir cuit incor por at ing t he J and K input values
obt ained fr om t he above st eps.
We will t ake up a specific case t o illust r at e t he above pr ocedur e.
7.4.12.1 Mod- 3 Sync hronous Counte r
We have implement ed a Mod-3 synchr onous count er as descr ibed in Sec. 7.4.11.1. We will
implement t he same count er by t he pr ocedur e descr ibed her e. We will follow t he t r ut h t able
given in Table 7.7. For your convenience t he excit at ion t able for J K flip-flops is r epr oduced her e.
Table 7.10 Exci tati on table for JK fli p-flop
Present state Next state J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
We now pr epar e a count er design t able list ing t he t wo flip-flops and t heir st at es and also
t he four input s t o t he t wo flip-flops as in t able 7.11.
Table 7.11 Counter desi gn table
Counter state Flip-flop inputs
A B A B
J
A
K
A
J
B
K
B
0 0 1 X 0 X
1 0 X 1 1 X
0 1 0 X X 1
0 0
The t able shows t hat if t he count er is in t he st at e A = 0, B = 0 and a clock pulse is
applied, t he count er is r equir ed t o st ep up t o A = 1, B = 0. When t he count er is in t he st at e
A = 1, B = 0 and a clock pulse is applied, t he count er has t o st ep up t o A = 0, B = 1. Last ly
when anot her clock pulse is applied t he count er has t o r eset .
Fr om t he excit at ion t able for J K flip-flops we can det er mine t he st at es of t he J and K
input s, so t hat t he count er st eps up as r equir ed. For inst ance for t he A flip-flop t o st ep up
fr om 0 t o 1, J
A
should be 1 and K
A
should be X. Similar ly t he J and K input values of bot h
t he flip-flops for t he r emaining count er st at es have been wor ked out as shown in t he t able.
The next st ep is t o der ive boolean algebr a expr essions for each of t he input s t o t he flip-
flops. In t he above exer cise, our effor t was t o gener at e flip-flop input s in a given r ow, so t hat
S hift Registers and Counters 301
when t he count er is in t he st at e in t hat r ow, t he input s will t ake on t he list ed values, so t hat
t he next clock pulse will cause t he count er t o st ep up t o t he count er st at e in t he r ow below.
We now for m boolean algebr a expr essions fr om t his t able for t he J
A
, K
A
, J
B
and K
B
input s t o t he flip-flops and simplify t hese expr essions using Kar naugh maps. Expr essions for
t hese input s have been ent er ed in Kar anaugh maps in Fig. 7.46 (a), (b), (c) and (d). The
simplified expr essions obt ained for t he input s ar e also indicat ed under t he maps.
The count er cir cuit when dr awn up wit h t he following r esult ant dat a will be t he same
as wor ked out befor e in Fig. 7.40.
J
A
=
B
K
A
= 1
J
B
= A
K
B
= 1
1
0
0
2
A 0
X
1
X
3
A 1
0 1
X
0
X
2
A 0
1
1
X
3
A 1
0 1
( )
Map for J
J = B
a
A
A
( )
Map for K
K = 1
b
A
A
X
0
X
2
A 0
1
1
X
3
A 1
0 1
X
0
1
2
A 0
X
1
X
3
A 1
0 1
( )
Map for J
J = A
c
B
B
( )
Map for K
K = 1
d
B
B
B B B B
Fig. 7.46 (a), (b), (c) and (d)
7.4.12.2 Mod- 5 Counte r ( Sync hronous)
The Mod-5 count er we are going t o implement will be a synchronous count er, but it will have
t he same count er st at es as given earlier in Table 7.8. The count er design t able for t his count er
list s t he t hree flip-flops and t heir st at es as also t he six input s for t he t hree flip-flops. The flip-flop
input s required t o st ep up t he count er from t he present t o t he next st at e have been worked out
wit h t he help of t he excit at ion t able (Table 7.10). This list ing has been shown in Table 7.12.
302 S witching Theory
1
0
A 0
A 1
BC
00
( ) Map for J
J = C
a
A
A
0
4
X
6
1
2
X
1
X
5
X
7
X
3
BC
01
BC
11
BC
10
X
0
A 0
A 1
BC
00
( ) Map for K
K = 1
b
A
A
X
4
X
6
X
2
1
1
X
5
X
7
1
3
BC
01
BC
11
BC
10
0
0
A 0
A 1
BC
00
( ) Map for J
J = A
c
B
B
0
4
X
6
X
2
1
1
X
5
X
7
X
3
BC
01
BC
11
BC
10
X
0
A 0
A 1
BC
00
( ) Map for K
K = A
d
B
B
X
4
X
6
0
2
X
1
X
5
X
7
1
3
BC
01
BC
11
BC
10
0
0
A 0
A 1
BC
00
( ) Map for J
J = AB
e
C
C
X
4
X
6
0
2
0
1
X
5
X
7
1
3
BC
01
BC
11
BC
10
X
0
A 0
A 1
BC
00
( ) Map for K
K = 1
f
C
C
1
4
X
6
X
2
X
1
X
5
X
7
X
3
BC
01
BC
11
BC
10
Fig. 7.47
A
A
K
A
J
A
C
C
K
C
J
C
1
Clock
A
B
B
B
K
B
J
B
C
CLK CLK CLK
1
Fig. 7.48 Synchr onous Mod-5 count er
S hift Registers and Counters 303
Table 7.12 Counter desi gn table for Mod-5 counter
Input pulse Counter states Flip-flop inputs
count A B C J
A
K
A
J
B
K
B
J
C
K
C
0 0 0 0 1 X 0 X 0 X
1 1 0 0 X 1 1 X 0 X
2 0 1 0 1 X X 0 0 X
3 1 1 0 X 1 X 1 1 X
4 0 0 1 0 X 0 X X 1
5 (0) 0 0 0
The flip-flop input s have been det er mined wit h t he help of t he excit at ion t able. Table
7.10. Some examples follow:
A flip- flop
The init ial st at e is 0. It changes t o 1 aft er t he clock pulse. Ther efor e J
A
should be 1 and
K
A
may be 0 or 1 (t hat is X).
B flip- flop
The init ial st at e is 0 and it r emains unchanged aft er t he clock pulse. Ther efor e J
B
should
be 0 and K
B
may be 0 or 1 (t hat is X).
C flip- flop
The st at e r emains unchanged. Ther efor e J
C
should be 0 t o K
B
should by X.
The flip-flop input values ar e ent er ed in Kar naugh maps Fig. 7.47 [(a), (b), (c), (d), (e) and
(f)] and a boolean expr ession is for med for t he input s t o t he t hr ee flip-flops and t hen each
expr ession is simplified. As all t he count er st at es have not been ut ilized, Xs (don’t ) ar e ent er ed
t o denot e un-ut ilized st at es. The simplified expr essions for each input have been shown under
each map. Finally, t hese minimal expr essions for t he flip-flop input s ar e used t o dr aw a logic
diagr am for t he count er, which is given in Fig. 7.48.
7.4.12.3 Mod- 6 Counte r ( Sync hronous)
The desir ed count er st at es and t he J K input s r equir ed for count er flip-flops ar e given in
t he count er design t able (Table 7.13).
Table 7.13 Counter desi gn table for Mod-6 counter
Input pulse Counter states Flip-flop inputs
count A B C J
A
K
A
J
B
K
B
J
C
K
C
0 0 0 0 1 X 0 X 0 X
1 1 0 0 X 1 1 X 0 X
2 0 1 0 1 X X 0 0 X
3 1 1 0 X 1 X 1 1 X
4 0 0 1 1 X 0 X X 0
5 1 0 1 X 1 0 X X 1
6 (0) 0 0 0
304 S witching Theory
As befor e, t he J K input s r equir ed for t his have been det er mined wit h t he help of t he
excit at ion t able, (Table 7.10). These input values ha ve been ent er ed in Kar naugh maps
Fig. 7.49 and a boolean expr ession is for med for t he input s t o t he t hr ee flip-flops and t hen
each expr ession is simplified. Xs have been ent er ed in t hose count er st at es which have
not been ut ilized. The simplified expr essions for each input have been shown under each
map and finally a logic diagr am based on t hese expr essions has been dr awn, as given in
Fig. 7.50.
1
0
A 0
A 1
BC
00
( ) Map for J
J = 1
a
A
A
1
4
X
6
1
2
X
1
X
5
X
7
X
3
BC
01
BC
11
BC
10
X
0
A 0
A 1
BC
00
( ) Map for K
K = 1
b
A
A
X
4
X
6
X
2
1
1
1
5
X
7
1
3
BC
01
BC
11
BC
10
0
0
A 0
A 1
BC
00
( ) Map for J
J = AC
c
B
B
0
4
X
6
X
2
1
1
0
5
X
7
X
3
BC
01
BC
11
BC
10
X
0
A 0
A 1
BC
00
( ) Map for K
K = A
d
B
B
X
4
X
6
0
2
X
1
X
5
X
7
1
3
BC
01
BC
11
BC
10
0
0
A 0
A 1
BC
00
( ) Map for J
J = AB
e
C
C
X
4
X
6
0
2
0
1
X
5
X
7
1
3
BC
01
BC
11
BC
10
X
0
A 0
A 1
BC
00
( ) Map for K
K = A
f
C
C
0
4
X
6
X
2
X
1
1
5
X
7
X
3
BC
01
BC
11
BC
10
Fig. 7.49
S hift Registers and Counters 305
Fig. 7.50 Synchr omous Mod-6 count er.
7.4.13 Loc kout
The mod-6 count er we have just discussed ut ilizes only six out t he t ot al number of
eight st at es available in a count er having t hr ee flip-flops. The st at e diagr am for t he mod-
6 count er given in Fig. 7.51, shows t he st at es which have been ut ilized and also st at es
011 and 111 which have not been ut ilized. The count er ma y ent er one of t he unused st at es
and may keep shut t ling bet ween t he unused st at es and not come out of t his sit uat ion.
This condit ion may develop because of ext er nal noise, which may affect st at es of t he flip-
flops. If a count er has unused st at es wit h t his char act er ist ic, it is said t o suffer fr om
lockout .
111
000
100
010
110
001
101
011
Unused
States
Fig. 7.51 St at e diagr am for Mod-6 count er.
The lockout sit uat ion can be avoided by so ar r anging t he cir cuit t hat whenever t he
count er happens t o be in an unused st at e, it r ever t s t o one of t he used st at es. We will
r edesign t he mod-6 count er so t hat whenever it is in st at e 0 1 1 or 1 1 1, t he count er
swit hces back t o t he st ar t ing point 0 0 0. You will not ice fr om Fig. 7.49 t hat J s and Ks wer e
mar ked X in squar es cor r esponding t o t he unused st at es. We will now assign values for J s
and Ks for t he unused st at es, so t hat t he count er r ever t s t o st at e 0 0 0. This has been done
in Table 7.14.
306 S witching Theory
Table 7.14
Counter states Flip-flop inputs
A B C J
A
K
A
J
B
K
B
J
C
K
C
0 1 1 0 X X 1 X 1
1 1 1 X 1 X 1 X 1
0 0 0
These values of J s and Ks have been ent er ed in K-maps for t hose count er st at es wher e
Xs had been ent er ed pr eviously. K-maps for t he r evised values of J s and Ks ar e given in Fig.
7.52. Boolean expr essions ar e for med for t he input s t o t he t hr ee flip-flops and t he expr essions
so obt ained ar e simplified. The expr essions for each input have been shown under each map
and t he logic diagr am for t he impr oved mod-6 count er is given in Fig. 7.53.
1
0
A 0
A 1
BC
00
( ) Map for J
J = B + BC
a
A
A
1
4
0
6
1
2
X
1
X
5
X
7
X
3
BC
01
BC
11
BC
10
X
0
A 0
A 1
BC
00
( ) Map for K
K = 1
b
A
A
X
4
X
6
X
2
1
1
1
5
1
7
1
3
BC
01
BC
11
BC
10
0
0
A 0
A 1
BC
00
( ) Map for J
J = AC
c
B
B
0
4
X
6
X
2
1
1
0
5
X
7
X
3
BC
01
BC
11
BC
10
X
0
A 0
A 1
BC
00
( ) Map for K
K = A +C = AC
d
B
B
X
4
1
6
0
2
X
1
X
5
1
7
1
3
BC
01
BC
11
BC
10
0
0
A 0
A 1
BC
00
( ) Map for J
J = AB
e
C
C
X
4
X
6
0
2
0
1
X
5
X
7
1
3
BC
01
BC
11
BC
10
X
0
A 0
A 1
BC
00
( ) Map for K
K = A + B = AB
f
C
C
0
4
1
6
X
2
X
1
1
5
1
7
X
3
BC
01
BC
11
BC
10
Fig. 7.52
S hift Registers and Counters 307
Fig. 7.53 Mod-6 count er which will r eset when it happens t o r each an unut ilized st at e
7.4.14 M SI Counte r IC 7490 A
Of t he many TTL MSI decade count er s, IC 7490 A is most widely used for count ing in
t he st andar d 8421 BCD code. The logic diagr am for t his count er is given in Fig. 7.54 and it s
pin connect ions and logic symbol ar e given in Fig. 7.55 and 7.56 r espect ively.
You will not ice fr om Fig. 7.54 t hat it has t hr ee J K flip-flops A, B and C and, alt hough
t he D flip-flop is an RS flip-flop, it funct ions like a J K flip-flop, since it s nor mal out put is
connect ed t o t he R input . If you r efer t o Fig. 7.42, which shows a mod-5 count er, you will
not ice t hat t he B, C and D flip-flops in IC 7490 A also for m a similar mod-5 count er. Also not ice
t hat out put Q
A
pin 12, of flip-flop A, which funct ions as a mod-2 count er, is not int er nally
connect ed. It has t o be ext er nally connect ed t o input B (pin 1) t o enable it t o funct ion as a
mod 2 × 5 or decade count er, when t he input clock is applied at A (pin 14). It basically count s
fr om binar y 0000 t o 1001 and back t o 0000.
To r eset t he count er, gat e 1 is pr ovided wit h t wo input s MR
1
and MR
2
, any one of which
will r eset t he count er wit h a high input . This makes it possible t o r eset t he count er fr om any
one of t wo sour ces. Nor mally bot h input s ar e t ied t oget her. MS
1
and MS
2
, input s t o gat e 2
ar e used t o pr eset t he count er t o binar y 1001 (decimal 9) by t aking any one or bot h input s
t o gat e 2 high. Nor mally bot h input s ar e t ied t oget her. It is wor t h not ing t hat , alt hough t his
is an asynchr onous count er, it has a count fr equency of appr oximat ely 32 MHz, and t her efor e
it finds wide applicat ion in fr equency count er s.
As you will see lat er, t his count er also finds applicat ion as a modulo count er and it can
be used t o divide t he input fr equency by 5, 6, 7 et c.
Table 7.15 Bi -qui nary (5 × 2) sequence
Output
Q
A
Q
D
Q
C
Q
B
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
1 0 0 0
308 S witching Theory
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
Fig. 7.54 Logic diagram for count er IC 7490 A
Fig. 7.55 Pin connect ions for count er IC 7490 A
12
9
8
11
Q
A
Q
B
Q
C
Q
D
14
1
6
7
2
3
CP
0
CP
1
MS
1
MS
2
MR
1
MR
2
7490 A
Fig. 7.56 Logic symbol for count er IC 7490 A
S hift Registers and Counters 309
When t his count er is used as a decade count er in t he 2 × 5 configur at ion, Q
A
(Pin 12)
is connect ed t o pin 1 as in Fig. 7.57 and clock pulse ar e applied at pin 14. The out put at Q
D
(Pin 11) will be low fr om a count of 0000 t o 1110. The out put at pin 11 will be high at count s
of 0001 and 1001 or decimal 9. At t he next 1 t o 0 t r ansit ion of t he clock pulse, t he count er
will be r eset and at t he same t ime, if t her e is anot her count er in cascade as shown in
Fig. 7.58 it s count will go up fr om 0000 t o 1000 or decimal 1 on t he 1 → 0 t r ansit ion of t he
same clock pulse. In ot her wor ds, when t he fir st count er has r eached it s maximum count of
9, t he next pulse will r eset it t o 0 and t he second count er will be st epped up fr om 0000 t o
1000 and t he t wo put t oget her will show a count of 10 and a maximum count of 99.
The wavefor m for t his count er, connect ed in t he 2 × 5 configur at ion, will be as shown
in Fig. 7.43 and t he count ing sequence will be as shown in Table 7.9, which is in pur e binar y
sequence. If you look at t he D out put in Fig. 7.43, you will obser ve t hat it is not symmet r ical.
If t his count er is connect ed in t he 5 × 2 mode, t he out put will have a symmet r ical shape.
To oper at e t his count er in t he 5 × 2 mode, pin 14 is connect ed t o Q
D
(pin 11) and t he
clock signal is applied at pin 1 as has been shown in Fig. 7.59. The out put will now follow
t he bi-quinar y (5 × 2) sequence as show in Table 7.15, which is differ ent fr om t he pur e binar y
sequence in Table 7.9. Bi-quinar y (5 × 2) sequence wavefor ms ar e shown in Fig. 7.60. The
count er will show a count of 0001 aft er t he fir st clock pulse and t he 10t h pulse will r eset t he
count er t o 0000 on it s t r ailing edge, which will also incr ement t he next count er if anot her
count er is connect ed in cascade. Two count er s connect ed in cascade in t he 5 × 2 configur at ion
ar e shown in Fig. 7.61.
Fig. 7.57 IC 7490 A connect ed as a decade count er (2 × 5) configur at ion
For t wo decade count er s connect ed in cascade, t her e will be only one out put pulse for
ever y t en input clock pulses, which shows t hat t he fr equency of t he t r ain of input pulses is
scaled down by a fact or of 10. In ot her wor ds if t he input fr equency is f, t he out put fr equency
will be f/10.
In digit al inst r ument s, it is oft en necessar y t o divide a fr equency by a given fact or and
for t his funct ion scaler s ar e used. Scaler s will accept input pulses and out put a single pulse
at t he r equir ed int er val. A single decade scaler will divide a t r ain of pulses by 10 and four
decade scaler s will divide t he input fr equency by 10
4
.
310 S witching Theory
12
9
8
11
Q
A
Q
B
Q
C
Q
D
14
1
6
7
2
3
CP
0
CP
1
MS
1
MS
2
MR
1
MR
2
7490 A
Clock
Input
LSB
MSB
LSD
12
9
8
11
Q
A
Q
B
Q
C
Q
D
14
1
6
7
2
3
CP
1
MS
1
MS
2
MR
1
MR
2
7490 A
MSD
Fig. 7.58 IC 7490 A connect ed as a t wo-decade count er (00–99)
12
9
8
11
Q
A
Q
B
Q
C
Q
D
14
1
6
7
2
3
CP
0
CP
1
MS
1
MS
2
MR
1
MR
2
7490 A
Clock
Input
LSB
MSB
Fig. 7.59 IC 7490 A connect ed as a decimal scaler (5 × 2) configur at ion
12
9
8
11
Q
A
Q
B
Q
C
Q
D
14
1
6
7
2
3
CP
1
MS
1
MS
2
MR
1
MR
2
7490 A
Output f/10
CP
0
Clock
Input
(f)
Fig. 7.60 Wavefor ms in bi-quinar y (5 × 2) sequence
S hift Registers and Counters 311
7.4.14.1 Modulo- N c ounte rs ba se d on IC 7490 A
IC 7490 A has found sever al applicat ions in cir cuit s r equir ing fr equency division. Some
of t he cir cuit s in common use based on t his IC have been discussed her e.
Modulo- 5 Counte r
When used as a Mod-5 count er, connect ions ar e t o be made as shown in Fig. 7.62. The
count sequence for t his count er is as given in Table 7.16.
Fig. 7.61 Divide by 100 scaler
Table 7.16 Count sequence for Mod-5 counter
Input pulse count Counter output
Q
D
Q
C
Q
B
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 (0) 0 0 0
12
9
8
11
Q
A
Q
B
Q
C
Q
D
14
1
6
7
2
3
CP
0
CP
1
MS
1
MS
2
MR
1
MR
2
7490 A
Clock
Input
LSB
MSB
2
0
2
1
2
2
Fig. 7.62 Mod-5 count er using IC 7490 A
312 S witching Theory
Modulo- 6 Counte r
IC 7490 A is t o be connect ed as in Fig. 7.63 t o obt ain a Mod-6 count er. It s count er
sequence is given in Table 7.17.
Table 7.17 Count sequence for Mod-6 counter
Input pulse Counter output
count Q
D
Q
C
Q
B
Q
A
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 (0) 0 1 1 0
12
9
8
11
Q
A
Q
B
Q
C
Q
D
14
1
6
7
2
3
CP
0
CP
1
MS
1
MS
2
MR
1
MR
2
7490 A
Clock
Input
LSB
MSB
Fig. 7.63 Mod-6 count er using IC 7490 A
As t he count er is r equir ed t o r eset when t he count r eaches 6, t hat is 0 1 1 0 when bot h
Q
B
and Q
C
out put s ar e high, t hese t wo out put s ar e connect ed t o t he r eset input s so t hat t he
count er r eset s at t his count . Thus t he count er sequences fr om 0000 t o 0101 and t her eaft er
it r eset s and t he cycle is r epeat ed.
Modulo- 9 Counte r
When used as a Mod-9 count er, t his IC is r equir ed t o be connect ed as shown in Fig. 7.64.
The count er is r equir ed t o r eset when t he count r eaches 1001. Ther efor e pins 11 and 12 ar e
connect ed t o pins 3 and 2. Also not ice t hat pin 12 is connect ed t o pin 1 and clock input is
applied t o pin 14, so t hat it looks like a decade count er which r eset s when t he count r eaches
decimal 9.
S hift Registers and Counters 313
12
9
8
11
Q
A
Q
B
Q
C
Q
D
14
1
6
7
2
3
CP
0
CP
1
MS
1
MS
2
MR
1
MR
2
7490 A
Clock
Input
LSB
MSB
Fig. 7.64 Mod-9 count er using IC 7490A
7.4.15 M SI Counte r IC 7492A
Count er IC 7492 A, which is ver y similar t o IC 7490 A, also finds consider able applicat ion
in cir cuit s r equir ing fr equency division. A logic diagr am of t his IC is given in Fig. 7.65 and
it s pin connect ions and logic symbol ar e given in Fig. 7.66 and 7.67 r espect ively.
In t his count er flip-flops B, C, and D ar e connect ed in t he 3 × 2 configur at ion and,
t her efor e, if input is applied at pin 1, and out put s ar e t aken fr om Q
B
, Q
C
and Q
D
, t his count er
will funct ion as mod-6 count er.
If out put Q
A
, pin 12, is connect ed t o input pin 1, t his IC funct ions as a 2 × 3 × 2 or mod-
12 count er. Table 7.18 gives t he t r ut h t able for t his IC when Q
A
, pin 12, is connect ed t o input ,
pin 1. Some fr equency division cir cuit s based on t his IC have been consider ed her e.
Table 7.18
Input pulse Counter output
count Q
D
Q
C
Q
B
Q
A
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 1 0 0 0
7 1 0 0 1
8 1 0 1 0
9 1 0 1 1
10 1 1 0 0
11 1 1 0 1
12 0 0 0 0
314 S witching Theory
Fig. 7.65 Logic diagram for IC 7492 A
Fig. 7.66 Pin connect ions for IC 7492 A
12
11
9
8
Q
A
Q
B
Q
C
Q
D
14
1
6
7
CP
0
CP
1
MR
1
MR
2
7492 A
Fig. 7.67 Logic symbol for IC 7492 A
S hift Registers and Counters 315
7.4.15.1 Divide - by- N c irc uits ba se d on IC 7492 A
This IC like 7490 A is also a useful t ool for cir cuit s which r equir e fr equency division.
Some cir cuit s based on t his IC have been consider ed her e.
Divide - by- 6- Circ uit
As has been ment ioned ear lier, flip-flops B, C and D in t his IC ar e connect ed in t he
3 × 2 configur at ion. To oper at e as a divide-by-6, cir cuit input is applied at pin 1 and out put
is t aken fr om Q
D
, pin 8, as shown in Fig. 7.68.
12
11
9
8
Q
A
Q
B
Q
C
Q
D
14
1
6
7
CP
0
CP
1
MR
1
MR
2
7492 A
Clock
Input (f)
Ouput f/6
Fig. 7.68 Divide-by-6 cir cuit
Divide - by- 9 Circ uit
Fig. 7.68 gives t he diagr am for a cir cuit using IC 7492 A, which divides t he input
fr equency by 9. Input is applied at pin 1 and, when t he input pulse count r eaches decimal 9,
out put s Q
D
and Q
A
go high, and as t hey ar e connect ed t o r eset input s, pins 7 and 6, t he
count er is r eset . Out put is t aken fr om Q
A
, pin 12.
12
11
9
8
Q
A
Q
B
Q
C
Q
D
14
1
6
7
CP
0
CP
1
MR
1
MR
2
7492 A
Clock
Input (f)
Ouput f/9
Fig. 7.69 Divide-by-9 cir cuit
316 S witching Theory
Divide - by- 12- Circ uit
A cir cuit based on IC 7492 A which will divide t he input fr equency by 12 is given in Fig.
7.70. Clock input is applied at pin 1 and t he out put is t aken fr om Q
D
, pin 12. When t he cir cuit
r eaches pulse count 12, it is aut omat ically r eset and it r epeat s t he cycle all over again.
Fig. 7.70 Divide-by-12 cir cuit
7.4.16 Ring C ounte r
Ring count er s pr ovide a sequence of equally spaced t iming pulses and, t her efor e, find
consider able applicat ion in logic cir cuit s which r equir e such pulses for set t ing in mot ion a
ser ies of oper at ions in a pr edet er mined sequence at pr ecise t ime int er vals. Ring count er s ar e
a var iat ion of shift r egist er s.
The r ing count er is t he simplest for m of shift r egist er count er. In such a count er t he flip-
flops ar e coupled as in a shift r egist er and t he last flip-flop is coupled back t o t he fir st , which
gives t he ar r ay of flip-flops t he shape of a r ing as shown in Fig. 7.71. In par t icular t wo
feat ur es of t his cir cuit should be not ed.
(1) The Q
D
and
Q
D
out put s of t he D flip-flop ar e connect ed r espect ively, t o t he J and
K input s of flip-flop A.
(2) The pr eset input of flip-flop A is connect ed t o t he r eset input s of flip-flops B, C and D.
Fig. 7.71 Ring Count er
S hift Registers and Counters 317
If we place only one of t he flip-flops in t he set st at e and t he ot her s in t he r eset st at e
and t hen apply clock pulses, t he logic 1 will advance by one flip-flop ar ound t he r ing for each
clock pulse and t he logic 1 will r et ur n t o t he or iginal flip-flop aft er exact ly four clock pulses,
as t her e ar e only four flip-flops in t he r ing. The r ing count er does not r equir e any decoder,
as we can det er mine t he pulse count by not ing t he posit ion of t he flip-flop, which is set . The
t ot al cycle lengt h of t he r ing is equal t o t he number of flip-flop st ages in t he count er. The
r ing count er has t he advant age t hat it is ext r emely fast and r equir es no gat es for decoding
t he count . However it is uneconomical in t he number of flip-flops. Wher eas a mod-8 count er
will r equir e four flip-flops, a mod-8 r ing count er will r equir e eight flip-flops.
The r ing count er is ideally suit ed for applicat ions wher e each count has t o be r ecognized
t o per for m some logical oper at ion.
We can now consider how t he modified shift r egist er shown in Fig. 4.78 oper at es. When
t he pr eset is t aken low moment ar ily, flip-flop A set s and all ot her flip-flops ar e r eset . The
count er out put will now be as follows:
Q
A
Q
B
Q
C
Q
D
1 0 0 0
At t he negat ive clock edge of t he 1st pulse, flip-flop A r eset s Q
A
becomes 0, Q
B
becomes
1 and Q
C
and Q
D
r emain 0. The count er out put is now as follows:
Q
A
Q
B
Q
C
Q
D
1 0 0 0
Aft er t he 4t h clock pulse, t he count er out put will be as follows:
Q
A
Q
B
Q
C
Q
D
1 0 0 0
You will not ice t hat t his was t he posit ion at t he beginning of t he oper at ion, when t he
pr eset input was act ivat ed. A single logic 1 has t r avelled r ound t he count er shift ing one flip-
flop posit ion at a t ime and has r et ur ned t o flip-flop A. The st at es of t he flip-flops have been
summarized in Table 7.19.
Table 7.19 Ri ng counter states
S tates Counter output
Q
A
Q
B
Q
C
Q
D
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
The r elevant wavefor ms ar e shown in Fig. 7.72.
If pr eset and clear input s ar e not available, it is necessar y t o pr ovide t he r equir ed gat ing,
so t hat t he count er st ar t s fr om t he init ial st at e. This can be simply ar r anged by using a NOR
gat e as shown in Fig. 7.73.
318 S witching Theory
1 2 3 4 5
1 0 0 0 1
0 1 0 0 0
State
Q
A
Q
B
0 0 1 0 0
Q
C
0 1 2 3 0
0 0 0 1 0
Q
D
Shift
Pulses
Fig. 7.72
The NOR gat e ensur es t hat t he input t o flip-flop A will be 0 if any of t he out put s of A,
B, C flip-flops is a logic 1. Now, on t he applicat ion of clock pulses 0s will be moved r ight int o
t he count er unt il all A, B and C flip-flops ar e r eset . When t his happens, a logic 1 will be shift ed
int o t he count er, and as t his 1 is shift ed r ight t hr ough t he A, B and C flip-flops it will be
pr eceded by t hr ee mor e 0s, which will again be followed by a logic 1 fr om t he NOR gat e when
flip-flops, A, B and C ar e all r eset .
Fig. 7.73 Ring count er wit h cor r ect ing cir cuit
7.4.17 Johnson C ounte r
The r ing count er can be modified t o effect an economy in t he number of flip-flops used
t o implement a r ing count er. In modified for m it is known as a swit cht ail r ing count er or
Johnson count er. The modified r ing count er can be implement ed wit h only half t he number
of flip-flops.
In t he r ing count er cir cuit shown in Fig. 7.71, t he Q
D
and
QD
out put s of t he D-flip-flop
wer e connect ed r espect ively, t o t he J and K input s of flip-flop A. In t he J ohnson count er, t he
S hift Registers and Counters 319
out put s of t he last flip-flop ar e cr ossed over and t hen connect ed t o t he J and K input s of t he
fir st flip-flop. Fig. 7.74 shows a J ohnson count er using four J K flip-flops in t he shift r egist er
configur at ion, shown Q
D
and
Q
D
out put s connect ed r espect ively, t o t he K and J input s of flip-
flop A. Because of t his cr oss-connect ion, t he J ohnson count er is somet imes r efer r ed t o as a
t wist ed r ing count er.
Fig. 7.74 Four -st age J ohnson count er
To enable t he count er t o funct ion accor ding t o t he desir ed sequence, it is necessar y t o
r eset all t he flip-flops. Init ially t her efor e, Q
D
is 0 and Q
A
is 1, which makes t he J input of
flip-flop A logic 1. We will now st udy how shift pulses alt er t he count er out put .
(1) Since t he J input of flip-flop A is 1, t he 1st shift pulse set s t he A flip-flop and t he
ot her flip-flops r emain r eset as t he J input s of t hese flip-flops ar e 0 and K input s
ar e 1.
(2) When t he 2nd shift pulse is applied, since Q
D
is st ill 1, flip-flop A r emains set and
flip-flop B is set , while flip-flop C and D r emain r eset .
(3) Dur ing t he 3r d shift pulse, flip-flop C also set s, while flip-flops A and B ar e alr eady
set ; but flip-flop D r emains r eset .
(4) Dur ing t he 4t h, pulse, flip-flop D also set s while flip-flops A, B and C ar e alr eady set .
(5) Dur ing t he 5t h pulse as
QD
is 0, flip-flop A r eset s, while flip-flops B, C and D r emain
set .
The ent ir e sequence of st at es, which ar e 8 in all, is as shown in Table 7.20.
You will not ice fr om Table 7.20 t hat J ohnson count er wit h four flip-flops has eight valid
st at es. Since four flip-flops have been used, t he t ot al number of st at es is 16, out of which 8
are invalid, which have been list ed in Table 7.21.
The valid st at es r equir e decoding, which is differ ent fr om nor mal decoding used for
st andar d pur e binar y count sequence. You will not ice t hat st at e 1 is uniquely defined, when
t he out put s of flip-flops A and D ar e low. Thus a 2-input AND gat e wit h input s as shown in
t he t able can decode st at e 1. St at e 2 is also fully defined by A high and B low. Similar ly, t he
ot her out put s can be decoded by t he gat es wit h input s as shown in Table 7.20.
320 S witching Theory
Table 7.20
State Q
D
Q
C
Q
B
Q
A
Binary Output decoding
equivalent
1 0 0 0 0 0 AD
A
D
2 0 0 0 1 1 AB
A
B
3 0 0 1 1 3 BC
B
C
4 0 1 1 1 7 CD
C
D
5 1 1 1 1 15 AD
A
D
6 1 1 1 0 14 AB
A
B
7 1 1 0 0 12 BC
B
C
8 1 0 0 0 8 CD
C
D
Table 7.21 Invali d States
Q
D
Q
C
Q
B
Q
A
Binary
equivalent
0 1 0 0 4
1 0 0 1 9
0 0 1 0 2
0 1 0 1 5
1 0 1 1 11
0 1 1 0 6
1 1 0 1 13
1 0 1 0 10
In or der t o ensur e t ha t t he count er count s in t he pr escr ibed sequence given in
Table 7.20, an init ial r eset pulse may be applied, which will r eset all t he flip-flops. If t his is
not done, t her e is no sur et y t hat t he count er will r ever t t o t he valid count ing sequence. If
t he count er should find it self in an unused st at e, it may cont inue t o advance fr om one
disallowed st at e t o anot her. The solut ion t o t he pr oblem lies in applying ext r a feedback, so
t hat t he count er r ever t s t o t he cor r ect count ing sequence. For t his pur pose, t he self-cor r ect ing
cir cuit given in Fig. 7.76 may be used. The input t o t he AND gat e is Q
A
Q
B
Q
C
Q
D
and t hus
it decodes t he wor d 1 0 0 1, which over r ides t he input , which is 0 and t he count er pr oduces
an out put of 1 1 0 0, which is a par t of t he allowed count ing sequence. Fr om t hen onwar ds
t he count er funct ions in t he desir ed sequence.
S hift Registers and Counters 321
1 2 3 4 5 6 7 8 1 2 3 4
1 2 3 4 5 6 7 8 9 10 11 12
0 1 1 1 1 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0 0 0 1 1
0 0 0 1 1 1 1 0 0 0 0 1
0 0 0 0 1 1 1 1 0 0 0 0
State
Shift
Pulse
Q
A
Q
B
Q
C
Q
D
Fig. 7.75 Wavefor ms for a 4-st age J ohnson count er
Fig. 7.76 Self-st ar t ing and self-cor r ect ing J ohnson count er
7.4.17.1 Five - sta ge Johnson Counte r
While discussing t he 4-st age J ohnson count er, you must have obser ved t hat t his count er
divides t he clock fr equency by 8. Ther efor e, a J ohnson count er wit h n flip-flops will divide t he
clock fr equency by 2n or, in ot her wor ds, t her e will be 2n discr et e st at es. If we have five flip-
flops connect ed as a J ohnson count er, we will have 10 discr et e st at es. Consequent ly, we will
have a decade count er. However, it should be not ed t hat t his count er will have in all 32 st at es,
out of which t he desir ed count sequence will ut ilize only 10 st at es and t he r emaining 22 will
have t o be disallowed. As in t he case of a four flip-flop J ohnson count er, some for m of feedback
will have t o be incor por at ed, t o disallow t he illegal st at es. A self-cor r ect ing cir cuit like t he one
shown in Fig. 7.76 may be used wit h t his count er Table 7.22 shows t he sequence of t he t en
allowed st at es for t his count er. The wavefor ms ar e shown in Fig. 7.77.
322 S witching Theory
Table 7.22
State E D C B A Output
decoding
1 0 0 0 0 0
AE
2 0 0 0 0 1
AB
3 0 0 0 1 1
B C
4 0 0 1 1 1
CD
5 0 1 1 1 1
DE
6 1 1 1 1 1 A E
7 1 1 1 1 0
AB
8 1 1 1 0 0
B C
9 1 1 0 0 0
CD
10 1 0 0 0 0 DE
For decoding t he out put of t he 5-st age J ohnson count er use 2-input AND gat es. The
input s t o t hese gat es have been indicat ed in Table 7.22.
Fig. 7.77 Wavefor m for a 5-st age J ohnson count er
7.4.18 Ring C ounte r Ap p lic a tions
Ring count er s find many applicat ions as
(1) Fr equency divider s
(2) Count er s
(3) Code gener at or s and
(4) Per iod and sequence gener at or s
S hift Registers and Counters 323
Fre que nc y divide rs
If you look at t he wavefor m Fig. 7.72 of t he 4-st age r ing count er shown in Fig. 7.71, you
will not ice t hat t he B flip-flop pr oduces one out put pulse for t wo input pulses, t hat is it divides
t he fr equency of t he shift pulse by 2. Similar ly, flip-flop C pr oduces one out put pulse for ever y
t hr ee input pulses, t hat is it divides t he input fr equency by 3, and flip-flop D divides t he input
frequency by 4. If t here are n flip-flops t hey will divide t he shift pulse by n. Thus a shift
r egist er connect ed as a r ing count er can be used as a fr equency divider.
Counte rs
A shift r egist er, when connect ed as a r ing count er, can also be used as a count er. For
inst ance, t he flip-flop out put s of t he r ing count er in Fig. 7.71 also give an indicat ion of t he
number of pulses applied and, t her efor e count ing r equir es no decoding.
Se que nc e ge ne ra tors
Sequence gener at or s ar e cir cuit s which gener at e a pr escr ibed sequence of bit s in
synchr onism wit h a clock. By connect ing t he out put s of flip-flops in a r ing count er t o t he logic
cir cuit s whose oper at ions ar e t o be cont r olled accor ding t o a cer t ain sequence, a r ing count er
can per for m a ver y useful funct ion. Since r ing count er s ar e act ivat ed by fixed fr equency
clocks, t he t iming int er vals bet ween t he logic cir cuit s t o be cont r olled can be ver y pr ecise.
This is of par t icular impor t ance in comput er s wher e inst r uct ions have t o be execut ed at
t he r ight t ime and in t he cor r ect sequence.
7.4.18.1 Fe e dba c k Counte rs
The r ing count er s which we have consider ed so far have a cycle lengt h which is t he same
as t he number of flip-flops in t he count er. For inst ance, t he r ing count er in Fig. 7.71 has a
cycle lengt h of 4. It is possible t o design a r ing count er which pr oduces a longer cycle lengt h
of 2
n
–1, where n is t he number of flip-flops in t he r ing count er. The t r ick lies in decoding t he
out put s of t he shift r egist er and feeding t he decoded out put back t o t he input . This t echnique
can be used t o develop a wide var iet y of count sequences and out put wavefor ms. To achieve
a cycle lengt h of 2
n
– 1, an exclusive-OR gat e may be used as t he feedback element , which
pr ovides a feedback t er m fr om an even number of st ages t o t he fir st st age. Table 7.23
int ended for count er s up t o 12 st ages, shows t he st ages t he out put s of which ar e t o be fed
back t o t he fir st flip-flop in t he chain.
Q
Q
K
J
FF1
Q
1
Q
2
Q
4
CLK
Q
3
Preset
Q
Q
K
J
FF2
Q
Q
K
J
FF3
Q
Q
K
J
FF4
PRE PRE PRE PRE
Fi g. 7.78 Four -st age feedback count er
324 S witching Theory
This t able can be used for designing count er s of t he t ype shown in Fig. 7.78, when t he
feedback element consist s of a single XOR gat e. The count sequence for t his 4-st age count er
is given in Table 7.24. When you r efer t o Table 7.23, you will not ice t hat t he feedback t er m
for a 4-st age count er using an XOR gat e as t he feedback element is F = (Q
3


Q
4
). The t r ut h
t able for an XOR gat e r epr oduced below will enable you t o det er mine t he input t o t he fir st
st age in t he count er.
Input Output
A B F
0 0 0
0 1 1
1 0 1
1 1 0
Table 7.23 Feedback terms for counter desi gn
No. of stage Feedback stage
2 Q
1
Q
2
3 Q
2
Q
3
4 Q
3
Q
4
5 Q
3
Q
5
6 Q
5
Q
6
7 Q
6
Q
7
8 Q
4
Q
5
Q
6
Q
8
9 Q
5
Q
9
10 Q
7
Q
10
11 Q
9
Q
11
12 Q
6
Q
8
Q
11
Q
12
In det er mining t he count er st at es, all t hat is necessar y is t o det er mine t he feedback
input t o t he fir st flip-flop and, since J K flip-flops have been used, t he input t o t he fir st flip-
flop will be t he same as t he out put of t he XOR gat e, which depends on t he out put s of FF3
and FF4. Table 7.24 has been pr epar ed on t his basis.
It is impor t ant t o not e t hat t he 0 st at e of count sequence has t o be excluded by addit ional
gat ing or by using t he pr eset input . If you r efer t o t he fir st r ow of t he t able, you will obser ve
t hat bot h out put s Q
3
t o Q
4
ar e 1 and t her efor e F = 0. Consequent ly, t he input t o t he fir st
flip-flop is also 0, which will make it s out put on t he fir st clock pulse 0. The out put s of FF2
and FF3 will r emain unchanged on t he fir st clock pulse. You can det er mine t he out put s in
t he r emaining r ows on t his basis.
A close look at t he t able will show you t hat t he out put of FF2 r esembles t he out put of
FF1, but it is delayed by one clock pulse fr om t hat of FF1. Similar ly, t he out put s of FF3 and
FF4 ar e also delayed by one clock pulse as compar ed t o t he out put s of t he immediat ely
pr eceding flip-flops.
S hift Registers and Counters 325
Table 7.24 Count sequence for 4-stage feedback counter
Clock input Output
Q
1
Q
2
Q
3
Q
4
0 1 1 1 1
1 0 1 1 1
2 0 0 1 1
3 0 0 0 1
4 1 0 0 0
5 0 1 0 0
6 0 0 1 0
7 1 0 0 1
8 1 1 0 0
9 0 1 1 0
10 1 0 1 1
11 0 1 0 1
12 1 0 1 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
This pr ocedur e can be used for designing count er s which ar e r equir ed t o cycle t hr ough
a lar ge number of st at es. For inst ance a count er which uses 8 flip-flops will cycle t hr ough
2
8
– 1 or 255 st at es. We have used only a single XOR gat e as t he feedback element , but t he
feedback logic can be designed differ ent ly t o sequence t hr ough any desir ed sequence or
wavefor m.
7.4.18.2 Se que nc e ge ne ra tors
Her e we ar e concer ned wit h pseudo-r andom sequence gener at or s. They will be r andom
in t he sense t hat t he out put gener at ed will not cycle t hr ough t he nor mal binar y count . The
sequence is t er med pseudo, as it is not r andom in t he r eal sense, because it will sequence
t hr ough all t he possible st at es once ever y 2
n
– 1 clock cycles. The r andom sequence gener at or
given in Fig. 7.79 has n st ages and it will t her efor e sequence t hr ough 2
n
– 1 values befor e
it r epeat s t he same sequence of values.
Let us consider t he sequence 100110011001. The bit sequence in t his number has a
lengt h of 4 t hat is 1001, if you r ead it fr om t he fir st bit on t he left . You can also r ead t he
sequence fr om t he 2nd and 3r d bit s on t he left , when t he bit pat t er ns will appear t o be 0011
and 0110. No mat t er how you r ead it , t he bit lengt h does not change, nor does t he sequence
of bit s change. You can descr ibe t he pat t er n of bit s as 1001, 0011 or 0110.
We can now consider t he st r uct ur e of a sequence gener at or given in a simple for m in
Fig. 7.79 using D-t ype flip-flops connect ed as in a shift r egist er. The out put of t he flip-flops
ar e connect ed t hr ough a feedback decoder t o t he input of t he fir st flip-flop. The out put of t he
decoder is a funct ion of t he flip-flop out put s connect ed t o it and t he decoder cir cuit r y. We can
st at e t his as follows :
F = f (Q
1
, Q
2
, Q
3
, Q
n
)
326 S witching Theory
Fig. 7.79 Basic st r uct ur e of a sequence gener at or
The desir ed sequence of bit s will appear at t he out put of each of t he flip-flops, but t he
out put of each of t he successive flip-flops will show a delay in t he appear ance of t he sequence
by one clock int er val over t he one which pr ecedes it .
The minimum number of flip-flops r equir ed t o gener at e a sequence of lengt h S is given
by
S = 2
n
– 1
Where n is t he number of flip-flops in t he chain.
However, if t he minimum number of flip-flops is used, it is not possible t o say off hand,
t hat it will be possible t o gener at e a sequence of t he r equir ed lengt h; but for a given number
of flip-flops t her e is invar iably one sequence which has t he maximum lengt h.
It is impor t ant t hat in t he gener at ion of a sequence no st at e should be r epeat ed, as t hat
will put a limit on t he number of st at es, because ever y st at e det er mines t he development of
t he fut ur e sequence. Besides, t he all 0 st at e has t o be excluded, as in t his case t he input t o
t he fir st flip-flop in t he chain will be 0, which implies t hat t he next st at e will also be 0, in
which case t he sequence gener at or would st op funct ioning.
We will now consider t he st eps in t he gener at ion of t he sequence 1001001 of seven bit s.
The number of st ages t hat will be r equir ed t o gener at e t his sequence can be det er mined as
follows:
S = 2
n
– 1
Since S = 7; n should be 3, t hat is t hr ee flip-flops will be r equir ed.
However, t her e is no guar ant ee t hat a 7-bit sequence can be gener at ed in 3 st ages. If
it is not possible, we can t r y t o implement t he sequence by using a 4-st age count er ; but in
t his par t icular case, as you will see, it will be possible t o gener at e t his sequence wit h t hr ee
st ages. The basic ar r angement for gener at ing t his sequence is shown in Fig. 7.80, which uses
t hr ee J K flip-flops. The out put s of FF2 and FF3 const it ut e t he input s t o t he logic decoder,
which in t his case in an XOR gat e. The out put of t he XOR gat e, which const it ut es t he input
F t o FFI can be st at ed as follows:
F = (Q
2


Q
3
)
You must have not iced t hat t he out put s of FF2 t o FF3 ar e one CLK pulse behind t he
out put s of flip-flops immediat ely pr eceding t hem. Aft er t he fir st sequence of 7 st at es has been
complet ed, t he sequence is r epeat ed when t he 8t h (or 1st ) CLK pulse ar r ives. Also obser ve
S hift Registers and Counters 327
t hat no out put st at e has been r epeat ed, which shows t hat it has been possible t o implement
t he sequence wit h only 3 flip-flops.
K
J
FF1
Q
1
Q
2
Clock
Q
3
Present
K
J
FF2
K
J
FF3
PRE PRE PRE
F = (Q + Q )
2 3
Fig. 7.80 Thr ee-st age sequence gener at or
When a lar ger or smaller number of flip-flops is used, t he input t o t he fir st flip-flop can
be wor ked out on t he same basis; but t he feedback logic will be differ ent as shown in
Table 7.25 for sequence gener at or s using up t o 8 st ages. For inst ance for a gener at or using
four flip-flops, F will be as follows:
F = (Q
3


Q
4
)
Table 7.25 Logi c desi gn table for shi ft regi ster
sequences of maxi mum length (S = 2
n
–1)
Clock Feedback state
n
2 Q
1
Q
2
3 Q
2
Q
3
4 Q
3
Q
4
5 Q
3
Q
5
6 Q
5
Q
6
7 Q
6
Q
7
8 Q
2
Q
3
Q
4
Q
8
The implement at ion of sequence 1001011 has been pr esent ed in Table 7.26.
The count sequence has been developed as follows: You will not ice fr om t he t able t hat
at t he commencement of t he oper at ion, t he count er is set as shown against CLK 1. Befor e
CLK 2 is applied at FF1 input , t he F input t o it should be 0, so t hat it s out put changes fr om
1 t o 0. Since Q
2
and Q
3
ar e bot h 1, t he F input t o FF
1
will be 0. This condit ion is, t her efor e,
sat isfied. The second clock pulse, t her efor e, changes Q
1
fr om 1 t o 0 and Q
2
and Q
3
r emain
on 1 as t he input s t o t hese flip-flops ar e 1. Since bot h Q
2
and Q
3
ar e again 1, t he F input
t o FF
1
, befor e t he ar r ival of t he 3r d clock pulse will again be 0. Ther efor e, on t he ar r ival of
CLK pulse 3, t he out put of Q
1
will r emain 0, as t he input t o it is 0. On t he same CLK pulse
Q
2
will change fr om 1 t o 0 as t he input t o it is 0 and Q
3
will r emain on 1 as t he input t o
Q
3
is st ill 1. Successive changes in t he out put s have been wor ked out on t his basis.
328 S witching Theory
Table 7.26
Clock interval Flip-flop outputs Input to FF1
CLK F = (Q
2


Q
3
)
Q
1
Q
2
Q
3
1 1 1 1 0
2 0 1 1 0
3 0 0 1 1
4 1 0 0 0
5 0 1 0 1
6 1 0 1 1
7 1 1 0 1
. . . . .
. . . . .
. . . . .
. . . . .
1 1 1 1 1
7.5 EXERC I SES
1. Can one st or e decimal number 12 in an 8-bit shift r egist er.
2. The number st or ed in a 4-bit binar y up-count er is 0101. What will be st at e of t he
count er aft er t he following clock pulses ?
(a) 3r d clock pulse
(b) 5t h clock pulse
(c) 8t h clock pulse
(d) 12t h clock pulse
3. In a 4-bit r ipple up-count er how many clock pulses will you apply, st ar t ing fr om
st at e 0 0 0 0, so t hat t he count er out put s ar e as follows ?
(a) 0 0 1 0
(b) 0 1 1 1
(c) 1 0 0 1
(d) 1 1 1 0
4. Dr aw t he logic diagr am for a binar y up-count er using four J K flip-flops and dr aw t he
t r ut h t able and t he out put wavefor ms.
5. Connect four edge-t r igger ed D-t ype flip-flops t o make an asynchr onous up-count er.
6. How many J K flip-flops will you r equir e t o make t he following modulo count er s ?
(a) Mod-4 (b) Mod-6
(c) Mod-9 (d) Mod-11
7. What will be maximum count capabilit y of a count er having 12 J K flip-flops ?
S hift Registers and Counters 329
8. How many flip-flops will you r equir e t o at t ain a count capabilit y of 8500 ?
9. An asynchr onous count er has four flip-flops and t he pr opagat ion delay of each flip-
flop is 20 ns. Calculat e t he maximum count ing speed of t he count er.
10. A synchr onous count er has four flip-flops and t he pr opagat ion delay of each is 20 ns.
What is it s maximum count ing speed ?
11. By how much will a r ipple down-count er having t hr ee flip-flops divide t he input
fr equency ?
12. Dr aw a logic diagr am, t r ut h t able and out put wavefor ms for a r ipple down-count er
wit h four flip-flops.
13. What will be t he out put st at es of a four flip-flop binar y down-count er, aft er t he
following input clock pulses, if t he init ial st at e of t he count er was 1111 ?
(a) 4 (b) 7 (c) 9 (d) 14
14. Dr aw t he logic diagr am of a pr eset t able down count er wit h a maximum pr eset
capabilit y of 7.
15. What will be t he modulus of IC 74193 in t he up-count ing mode, if t he number s
pr eset in t he count er ar e as follows ?
(a) Decimal 5 (b) Decimal 7
(c) Decimal 9 (d) Decimal 12
16. What will be t he modulus of IC 74193 in t he down-count ing mode, when t he binar y
number s pr eset in t he count er ar e t he same as in Pr oblem 15 ?
17. A 74193 up-count er st ar t s count ing up fr om binar y number 1 0 0 0. What will be
t he st at e of t he count er aft er t he 8t h clock pulse ?
18. Dr aw t he logic diagr am of a Mod-6 count er using t he count er r eset met hod. Wr it e
it s t r ut h t able and dr aw t he out put wavefor ms.
19. Show how you will connect t wo ICs 74193 t o build an 8-bit up-down count er.
20. What is t he maximum count ing capacit y of a chain of five BCD count er s ?
21. A BCD count er is r equir ed t o have t he following st at es. Aft er how many clock pulses
will t hese st at es be r eached, if t he count er was init ially r eset ?
(a) 0 0 1 0
(b) 0 1 0 0
(c) 0 1 1 0
(d) 1 0 0 1
22. Connect t wo ICs 74193 t o make a moduluo-20 divider cir cuit .
23. Design a mod-10 (Decade) synchr onous count er using J K flip-flops.
24. Dr aw decoding gat es for t he decade count er in Fig. 4.51.
25. Dr aw decoding gat es for t he count er of Fig. 4.49.
26. Redesign t he synchr onous mod-5 count er cir cuit discussed in Sec 4.8.12.2 so t hat
whenever t he count er r eaches t he unut ilized st at e 1 0 1, 0 1 1 and 1 1 1 t he count er
is r eset .
27. Design a Mod-7 count er using IC 7490 A.
330 S witching Theory
28. Design a divide-by 120 count er using ICs 7490 A and 7492 A.
29. Design a cor r ect ing cir cuit for a 4-st age r ing count er using a NAND gat e inst ead
of a NOR gat e as used in Fig. 4.80.
30. Det er mine t he maximal lengt h sequence, which can be gener at ed using four J K flip-
flops and dr aw t he sequence gener at ed by t he fir st flip-flop in t he chain.
31. Draw wavefor ms t o illust r at e how a ser ial binar y number 1011 is loaded int o a shift
r egist er.
32. A binar y number is t o be divided by 64. By how many posit ions will you shift t he
number and in what dir ect ion.
33. Descr ibe t he wor king of shift r egist er wit h PISO/SIPO oper at ion.
34. Design a mod-5 synchr onous count er having t he st at es 011, 100, 101, 110, 111
r espect ively. Obt ain a minimal cost design wit h J -K F/F.
35. Design a shift r egist er count er t o gener at e a sequence lengt h of 8 having self-st ar t
feat ur e.
8
CHAPTER
331
ASYNCHRONOUS SEQUENTIAL LOGIC
8.0 INTRO DUC TIO N
Much of t oday’s logic design is based on t wo major assumpt ions: all signals ar e binar y,
and t ime is discr et e. Bot h of t hese assumpt ions ar e made in or der t o simplify logic design.
By assuming binar y values on signals, simple Boolean logic can be used t o descr ibe and
manipulat e logic const r uct s. By assuming t ime is discr et e, hazar ds and feedback can lar gely
be ignor ed. However, as wit h many simplifying assumpt ions, a syst em t hat can oper at e
wit hout t hese assumpt ions has t he pot ent ial t o gener at e bet t er r esult s.
Asynchr onous cir cuit s keep t he assumpt ion t hat signals ar e binar y, but r emove t he
assumpt ion t hat t ime is discr et e. This has sever al possible benefit s:
No C loc k Ske w
Clock skew is t he differ ence in ar r ival t imes of t he clock signal at differ ent par t s of t he
cir cuit . Since asynchr onous cir cuit s by definit ion have no globally dist r ibut ed clock, t her e is
no need t o wor r y about clock skew. In cont r ast , synchr onous syst ems oft en slow down t heir
cir cuit s t o accommodat e t he skew. As feat ur e sizes decr ease, clock skew becomes a much
gr eat er concer n.
Lowe r Powe r
St andar d synchr onous cir cuit s have t o t oggle clock lines, and possibly pr echar ge and
dischar ge signals, in por t ions of a cir cuit unused in t he cur r ent comput at ion. For example,
even t hough a float ing point unit on a pr ocessor might not be used in a given inst r uct ion
st r eam, t he unit st ill must be oper at ed by t he clock. Alt hough asynchr onous cir cuit s oft en
r equir e mor e t r ansit ions on t he comput at ion pat h t han synchr onous cir cuit s, t hey gener ally
have t r ansit ions only in ar eas involved in t he cur r ent comput at ion.
Note: t hat t her e ar e t echniques being used in synchr onous designs t o addr ess t his issue
as well.
Ave ra g e - C a se Inste a d of Worst- C a se Pe rforma nc e
Synchr onous cir cuit s must wait unt il all possible comput at ions have complet ed befor e
lat ching t he r esult s, yielding wor st -case per for mance. Many asynchr onous syst ems sense
when a comput at ion has complet ed, allowing t hem t o exhibit aver age-case per for mance. For
cir cuit s such as r ipple-car r y adder s wher e t he wor st -case delay is significant ly wor se t han t he
aver age-case delay, t his can r esult in a subst ant ial savings.
332 S witching Theory
Ea sing of G lob a l Timing Issue s
In syst ems such as a synchr onous micr opr ocessor, t he syst em clock, and t hus syst em
per for mance, is dict at ed by t he slowest (critical) pat h. Thus, most por t ions of a cir cuit must
be car efully opt imized t o achieve t he highest clock r at e, including r ar ely used por t ions of t he
syst em. Since many asynchr onous syst ems oper at e at t he speed of t he cir cuit pat h cur r ent ly
in oper at ion, r ar ely used por t ions of t he cir cuit can be left unopt imized wit hout adver sely
affect ing syst em per for mance.
Be tte r Te c hno lo g y M ig ra tio n Po te ntia l
Int egr at ed cir cuit s will oft en be implement ed in sever al differ ent t echnologies dur ing
t heir lifet ime. Ear ly syst ems may be implement ed wit h gat e ar r ays, while lat er pr oduct ion
r uns may migr at e t o semi-cust om or cust om ICs. Gr eat er per for mance for synchr onous
syst ems can oft en only be achieved by migrat ing all syst em component s t o a new t echnology,
since again t he overall syst em performance is based on t he longest pat h. In many asynchronous
syst ems, migrat ion of only t he more crit ical syst em component s can improve syst em performance
on average, since performance is dependent on only t he current ly act ive pat h. Also, since many
asynchronous syst ems sense comput at ion complet ion, component s wit h different delays may
oft en be subst it ut ed int o a syst em wit hout alt ering ot her element s or st ruct ures.
Automa tic Ad a p ta tion to Physic a l Prop e rtie s
The delay t hr ough a cir cuit can change wit h var iat ions in fabr icat ion, t emper at ur e, and
power -supply volt age. Synchr onous cir cuit s must assume t hat t he wor st possible combinat ion
of fact or s is pr esent and clock t he syst em accor dingly. Many asynchr onous cir cuit s sense
comput at ion complet ion, and will r un as quickly as t he cur r ent physical pr oper t ies allow.
Rob ust M utua l Exc lusion a nd Exte rna l Inp ut Ha nd ling
Element s t ha t gua r a nt ee cor r ect mut ua l exclusion of independent signa ls a nd
synchr onizat ion of ext er nal signals t o a clock ar e subject t o metastability. A met ast able st at e
is an unst able equilibr ium st at e, such as a pair of cr oss-coupled CMOS inver t er s at 2.5V,
which a syst em can r emain in for an unbounded amount of t ime. Synchr onous cir cuit s r equir e
all element s t o exhibit bounded r esponse t ime. Thus, t her e is some chance t hat mut ual
exclusion cir cuit s will fail in a synchr onous syst em. Most asynchr onous syst ems can wait an
ar bit r ar ily long t ime for such an element t o complet e, allowing r obust mut ual exclusion. Also,
since t her e is no clock wit h which signals must be synchr onized, asynchr onous cir cuit s mor e
gr acefully accommodat e input s fr om t he out side wor ld, which ar e by nat ur e asynchr onous.
Wit h all of t he pot ent ial advant ages of asynchr onous cir cuit s, one might wonder why
synchr onous syst ems pr edominat e. The r eason is t hat asynchr onous cir cuit s have sever al
pr oblems as well. Pr imar ily, asynchr onous cir cuit s ar e mor e difficult t o design in an ad hoc
fashion t han synchr onous cir cuit s. In a synchr onous syst em, a designer can simply define t he
combinat ional logic necessar y t o comput e t he given funct ions, and sur r ound it wit h lat ches.
By set t ing t he clock r at e t o a long enough per iod, all wor r ies about hazar ds (undesir ed signal
t r ansit ions) and t he dynamic st at e of t he cir cuit ar e r emoved. In cont r ast , designer s of
asynchr onous syst ems must pay a gr eat deal of at t ent ion t o t he dynamic st at e of t he cir cuit .
Hazar ds must also be r emoved fr om t he cir cuit , or not int r oduced in t he fir st place, t o avoid
incor r ect r esult s. The or der ing of oper at ions, which was fixed by t he placement of lat ches in
a synchr onous syst em, must be car efully ensur ed by t he asynchr onous cont r ol logic. For
complex syst ems, t hese issues become t oo difficult t o handle by hand.
Asynchronous S equential Logic 333
Finally, even t hough most of t he advant ages of asynchr onous cir cuit s ar e t owar ds higher
per for mance, it isn’t clear t hat asynchr onous cir cuit s ar e act ually any fast er in pr act ice.
Asynchr onous cir cuit s gener ally r equir e ext r a t ime due t o t heir signaling policies, t hus
incr easing aver age-case delay. Whet her t his cost is gr eat er or less t han t he benefit s list ed
pr eviously is unclear, and mor e r esear ch in t his ar ea is necessar y.
Even wit h all of t he pr oblems list ed above, asynchr onous design is an impor t ant r esear ch
ar ea. Regar dless of how successful synchr onous syst ems ar e, t her e will always be a need for
asynchr onous syst ems. Asynchr onous logic may be used simply for t he int er facing of a
synchr onous syst em t o it s envir onment and ot her synchr onous syst ems, or possibly for mor e
complet e applicat ions.
8.1 DIFFERENC E BETWEEN SYNC HRO NO US AND ASYNC HRO NO US
Sequent ial cir cuit s ar e divided int o t wo main t ypes: synchronous and asynchronous.
Their classificat ion depends on t he t iming of t heir signals.
S ynchronous sequent ial cir cuit s change t heir st at es and out put values at discr et e inst ant s
of t ime, which ar e specified by t he r ising and falling edge of a fr ee-r unning clock signal. The
clock signal is gener ally some for m of squar e wave as shown in Figur e 8.1 below.
Clock Period
Falling edge
Rising edge
Clock width
Fig. 8.1 Clock Signal
From t he diagram you can see t hat t he clock period is t he t ime bet ween successive
t r ansit ions in t he same dir ect ion, t hat is, bet ween t wo r ising or t wo falling edges. St at e
t r ansit ions in synchr onous sequent ial cir cuit s ar e made t o t ake place at t imes when t he clock
is making a t r ansit ion fr om 0 t o 1 (r ising edge) or fr om 1 t o 0 (falling edge). Bet ween
successive clock pulses t her e is no change in t he infor mat ion st or ed in memor y.
The r ecipr ocal of t he clock per iod is r efer r ed t o as t he clock frequency. The clock width
is defined as t he t ime dur ing which t he value of t he clock signal is equal t o 1. The r at io of
t he clock widt h and clock per iod is r efer r ed t o as t he dut y cycle. A clock signal is said t o be
active high if t he st at e changes occur at t he clock’s r ising edge or dur ing t he clock widt h.
Ot her wise, t he clock is said t o be active low. Synchr onous sequent ial cir cuit s ar e also known
as clocked sequential circuits.
The memor y element s used in synchr onous sequent ial cir cuit s ar e usually flip-flops.
These cir cuit s ar e binar y cells capable of st or ing one bit of infor mat ion. A flip-flop cir cuit has
t wo out put s, one for t he nor mal value and one for t he complement value of t he bit st or ed
in it . Binar y infor mat ion can ent er a flip-flop in a var iet y of ways, a fact which give r ise t o
t he differ ent t ypes of flip-flops.
334 S witching Theory
In asynchronous sequent ial cir cuit s, t he t r ansit ion fr om one st at e t o anot her is init iat ed
by t he change in t he pr imar y input s; t her e is no ext er nal synchr onizat ion. The memor y
commonly used in asynchr onous sequent ial cir cuit s ar e t ime-delayed devices, usually
implement ed by feedback among logic gat es. Thus, asynchr onous sequent ial cir cuit s may be
r egar ded as combinat ional cir cuit s wit h feedback. Because of t he feedback among logic gat es,
asynchr onous sequent ial cir cuit s may, at t imes, become unst able due t o t r ansient condit ions.
The differ ences bet ween synchr onous and asynchr onous sequent ial cir cuit s ar e:
• In a clocked sequent ial cir cuit a change of st at e occur s only in r esponse t o a
synchr onizing clock pulse. All t he flip-flops ar e clocked simult aneously by a common
clock pulse. In an asynchr onous sequent ial cir cuit , t he st at e of t he cir cuit can
change immediat ely when an input change occur s. It does not use a clock.
• In clocked sequent ial cir cuit s input changes ar e assumed t o occur bet ween clock
pulses. The cir cuit must be in t he st able st at e befor e next clock pulse ar r ives. In
asynchr onous sequent ial cir cuit s input changes should occur only when t he cir cuit
is in a st able st at e.
• In clocked sequent ial cir cuit s, t he speed of oper at ion depends on t he maximum
allowed clock fr equency. Asynchr onous sequent ial cir cuit s do not r equir e clock
pulses and t hey can change st at e wit h t he input change. Ther efor e, in gener al t he
asynchr onous sequent ial cir cuit s ar e fast er t han t he synchr onous sequent ial cir cuit s.
• In clocked sequent ial cir cuit s, t he memor y element s ar e clocked flip-flops. In
asynchr onous sequent ial cir cuit s, t he memor y element s ar e eit her unclocked flip-
flops (lat ches) or gat e cir cuit s wit h feedback pr oducing t he effect of lat ch oper at ion.
In clocked sequent ial cir cuit s, any number of input s can change simult aneously (dur ing
t he absence of t he clock). In asynchr onous sequent ial cir cuit s only one input is allowed t o
change at a t ime in t he case of t he level input s and only one pulse input is allowed t o be
pr esent in t he case of t he pulse input s. If mor e t han one level input s change simult aneously
or mor e t han one pulse input is pr esent , t he cir cuit makes er r oneous st at e t r ansit ions due
t o differ ent delay pat hs for each input var iable.
8.2 MODES OF OPERATION
Asynchronous sequent ial cir cuit s can be classified int o t wo t ypes:
• Fundament al mode asynchr onous sequent ial cir cuit
• Pulse mode asynchr onous sequent ial cir cuit
Fund a m e nta l M o d e
In fundament al mode, t he input s and out put s ar e r epr esent ed by levels r at her t han
pulses. In fundament al mode asynchr onous sequent ial cir cuit , it is also assumed t hat t he t ime
differ ence bet ween t wo successive input changes is lar ger t han t he dur at ion of int er nal
changes. Fundament al mode oper at ion assumes t hat t he input signals will be changed only
when t he cir cuit is in a st able st at e and t hat only one var iable can change at a given t ime.
Pulse M od e
In pulse mode, t he input s and out put s ar e r epr esent ed by pulses. In t his mode of
oper at ion t he widt h of t he input pulses is cr it ical t o t he cir cuit oper at ion. The input pulse
must be long enough for t he cir cuit t o r espond t o t he input but it must not be so long as t o
Asynchronous S equential Logic 335
be pr esent even aft er new st at e is r eached. In such a sit uat ion t he st at e of t he cir cuit may
make anot her t r ansit ion.
The minimum pulse widt h r equir ement is based on t he pr opagat ion delay t hr ough t he
next st at e logic .The maximum pulse widt h is det er mined by t he t ot al pr opagat ion delay
t hr ough t he next st at e logic and t he memor y element s.
In pulse-mode oper at ion, only one input is allowed t o have pulse pr esent at any t ime.
This means t hat when pulse occur s on any one input , while t he cir cuit is in st able st at e, pulse
must not ar r ive at any ot her input . Figur e 8.2 illust r at es unaccept able and accept able input
pulse change. X
1
and X
2
ar e t he t wo input s t o a pulse mode cir cuit . In Fig. 8.2 (a) at t ime
t
3
pulse at input X
2
ar r ives.
X
1
t
1
t
2
t
4
t
5
t
6
t
3
X
2
t
t
Fi g. 8.2 (a) Unaccept able pulse mode input changes
X
2
X
1
t
t
Fig. 8.2 (b) Accept able pulse mode input changes
While t his pulse is st ill pr esent , anot her pulse at X
1
input arrives at t
4
. Ther efor e, t his
kind of t he pr esence of pulse input s is not allowed.
Bot h fundament al and pulse mode asynchr onous sequent ial cir cuit s use unclocked S-R
flip-flops or lat ches. In t he design of bot h t ypes of cir cuit s, it is assumed t hat a change occur s
in only one input s and no changes occur s in any ot her input s unt il t he cir cuit ent er s a st able
st at e.
8.3 ANALYSIS OF ASYNC HRO NO US SEQ UENTIAL M AC HINES
Analysis of asynchr onous sequent ial cir cuit s oper at ion in fundament al mode and pulse
mode will help in clear ly under st anding t he asynchr onous sequent ial cir cuit s.
8.3.1 Fund a me nta l M od e C irc uits
Fundament al mode cir cuit s ar e of t wo t ypes:
• Cir cuit s wit hout lat ches
• Cir cuit s wit h lat ches
8.3.2 C irc uits without La tc he s
Consider a fundament al mode cir cuit shown in Fig. 8.3.
336 S witching Theory
( ) a
Next State
Logic
External
Inputs
Output
logic
Q
1
Q
2
X
2
X
1
Next State
Logic
Output Logic
Q
1
Q
2
Y
X
1
X
2
X
2
X
2
X
1
X
2
X
1
X
1
X
2
Q
1
Q
2
Q
2
Q
1
Q
2
Q
2
X
1
Q
2
(b)
Fi g. 8.3 Fundament al mode asynchr onous sequent ial cir cuit wit hout lat ch
(a) block diagr am (b) cir cuit diagr am
Asynchronous S equential Logic 337
This cir cuit has only gat es and no explicit memor y element s ar e pr esent . Ther e ar e t wo
feedback pat hs fr om Q
1
and Q
2
t o t he next -st at e logic cir cuit . This feedback cr eat es t he
lat ching effect due t o delays, necessar y t o pr oduce a sequent ial cir cuit . It may be not ed t hat
a memor y element lat ch is cr eat ed due t o feedback in gat e cir cuit .
The fir st st ep in t he analysis is t o ident ify t he states and the state variables. The
combinat ion of level signals fr om ext er nal sour ces X
1
, X
2
is r efer r ed t o as t he input st at e and
X
1
, X
1
are t he input state variables. The combinat ion of t he out put s of memor y element s ar e
known as secondary, or internal states and t hese var iables ar e known as internal or secondary
state variables. Her e, Q
1
and Q
2
ar e t he int er nal var iables since no explicit element s ar e
pr esent . The combinat ion of bot h, input st at e and t he secondar y st at e (Q
1
, Q
2
, X
1
, X
2
) is
known as t he total state. Y is t he out put var iable.
The next secondar y st at e and out put logic equat ions ar e der ived fr om t he logic cir cuit
in t he next -st at e logic block. The next -secondar y st at e var iables ar e denot ed by Q
1
+
and Q
2
+
t hese ar e given by
Q X X X X Q X Q Q
Q X X Q X Q X Q
Y X Q Q
1
+
1 2 1 2 2 2 1 2
2
+
1 2 1 1 2 2 2
1 1 2
= + +
= + +
= ⊕ ⊕
Her e, Q
1
and Q
2
ar e t he pr esent secondar y st at e var iables when X
1
, X
2
input -st at e
variables occur, t he cir cuit goes t o next secondar y st at e. A st at e t able shown in Table 8.1 is
const r uct ed using t hese logic equat ions. If t he r esult ing next secondar y st at e is same as t he
present st at e, i.e. Q Q and Q Q
1
+
1 2
+
2
= = , t he t ot al st at e Q
1
, Q
2
, X
1
, X
2
is said t o be st able.
Ot her wise it is unst able.
The st abilit y of t he next t ot al st at e is also shown in Table 8.1.
Table 8.1 State Table
Present total state Next total state S table total state Output
Q
1
Q
2
X
1
X
2
Q
1
+
Q
2
+
X
1
X
2
Yes/ No Y
0 0 0 0 0 0 0 0 Yes 0
0 0 0 1 0 1 0 1 No 0
0 0 1 1 0 0 1 1 Yes 1
0 0 1 0 1 0 1 0 No 1
0 1 0 0 0 0 0 0 No 1
0 1 0 1 1 1 0 1 No 1
0 1 1 1 0 1 1 1 Yes 0
0 1 1 0 1 1 1 0 No 0
1 1 0 0 0 0 0 0 No 0
1 1 0 1 1 1 0 1 Yes 0
1 1 1 1 0 1 1 1 No 1
1 1 1 0 1 1 1 0 Yes 1
1 0 0 0 0 0 0 0 No 1
1 0 0 1 1 0 0 1 Yes 1
1 0 1 1 1 0 1 1 Yes 0
1 0 1 0 1 0 1 0 Yes 0
338 S witching Theory
8.3.3 Tra nsition Ta ble
A st at e t able can be r epr esent ed in anot her for m known as transition table. The t r ansit ion
t able for t he st at e t able of Table 8.1 is shown in Fig. 8.4.
In a t r ansit ion t able, columns r epr esent input st at es (one column for each input st at e)
and r ows r epr esent secondar y st at es (one r ow for each secondar y st at e). The next secondar y
st at e values ar e wr it t en int o t he squar es, each indicat ing a t ot al st at e. The st able st at es ar e
cir cled. For any given pr esent secondar y st at e (Q
1
Q
2
), t he next secondar y st at e is locat ed in
t he squar e cor r esponding t o r ow for t he pr esent secondar y st at e and t he column for t he input
st at e (X
1
X
2
).
For example, for Q
1
Q
2
= 11 and X
1
X
2
= 00, t he next secondar y st at e is 00 (t hir d r ow,
fir st column) which is an unst able st at e.
00 00
01
11 11
10 10 10
10 01
11 11
00
00
00
01
00 01 11 10
00
01
11
10
Q
1
Q
2
X
1
X
2
Q
1
Q
2
Next State
+
+
Input State
Present internal
state
Fig. 8.4 Transit ion t able for Table 8.1.
For a given input sequence, t he t ot al st at e sequence can be det er mined fr om t he t r ansit ion
t able.
Example. For the transition table shown in Fig 8.4, the initial total state is Q
1
Q
2
X
1
X
2
= 0000. Find the total state sequence for an input sequence X
1
X
2
= 00, 01, 11, 10, 00.
Solution. For a given int er nal st at e of t he cir cuit , a change in t he value of t he cir cuit
input causes a hor izont al move in t he t r ansit ion t able t o t he column cor r esponding t o t he new
input value. A change in t he int er nal st at e of t he cir cuit is r eflect ed by a ver t ical move. Since
a change in t he input can occur only when t he cir cuit is in a st able st at e, a hor izont al move
can st ar t only fr om a cir cled ent r y.
The init ial t ot al st at e is 0000 (fir st r ow, fir st column) which is a st able st at e. When t he
input st at e changes fr om 00 t o 01, t he cir cuit makes a t r ansit ion (hor izont al move) fr om t he
pr esent t ot al st at e t o t he next t ot al st at e 0101 (fir st r ow, second column) which is unst able.
Next , t he cir cuit makes anot her t r ansit ion fr om 0101 t o 1101 (ver t ical move) (second r ow,
second column) which is also an unst able st at e. Finally in t he next t r ansit ion (ver t ical move)
it comes t o st able st at e 1101 (t hir d r ow, second column). All t hese t r ansit ions ar e indicat ed
by ar r ows. Thus we see t hat a single input change pr oduces t wo secondar y st at e changes
Asynchronous S equential Logic 339
befor e a st able t ot al st at e is r eached. If t he input is next changed t o 11 t he cir cuit goes t o
t ot al st at e 0111 (hor izont al move) which is unst able and t hen t o st able t ot al st at e 0111 (ver t ical
move). Similar ly, t he next input change t o 10 will t ake t he cir cuit t o unst able t ot al st at e 1110
(hor izont al move) and finally t o st able t ot al st at e 1110 (ver t ical move). A change in input st at e
fr om 10 t o 00 causes a t r ansit ion t o unst able t ot al st at e 0000 (hor izont al move) and t hen t o
st able t ot al st at e 0000 (ver t ical move), complet ing t he st at e t r ansit ions for t he input sequence.
All t he st at e t r ansit ions ar e indicat ed by ar r ows.
The t ot al st at e sequence is
0000 0101 1101 0111 1110
0000
.
Fr om t he pr eceding discussions we see t hat fr om t he logic diagr am of an asynchr onous
sequent ial cir cuit , logic equat ions, st at e t able, and t r ansit ion t able can be det er mined. Similar ly,
fr om t he t r ansit ion t able, logic equat ions can be wr it t en and t he logic cir cuit can be designed.
8.3.4 Flow ta ble
In asynchr onous sequent ial cir cuit s design, it is mor e convenient t o use flow table r at her
t han t r ansit ion t able. A flow t able is basically similar t o a t r ansit ion t able except t hat t he
int er nal st at es ar e r epr esent ed symbolically r at her t han by binar y st at es. The column headings
ar e t he input combinat ions and t he ent r ies ar e t he next st at es, and out put s. The st at e
changes occur wit h change of input s (one input change at a t ime) and logic pr opagat ion delay.
The flow of st at es fr om one t o anot her is clear ly under st ood fr om t he flow t able. The
t r ansit ion t able of Fig. 8.4 const r uct ed as a flow t able is shown in Fig. 8.5. Her e, a, b, c ,and
d ar e t he st at es. The binar y value of t he out put var iable is indicat ed inside t he squar e next
t o t he st at e symbol and is separ at ed by a comma. A st able st at e is cir cled.
a
d, 1 b, o
c, 1 c, 0
a, 1
a, 0
a, 1
b, 1
00 01 11 10
a
b
c
d
Q
1
Q
2
X
1
X
2
Input State
Present internal
state
, 0
d , 1 d , 0 d , 0
c , 1
b , 0
a , 1
c , 1
U
n
s
t
a
b
l
e

S
t
a
t
e
O
u
t
p
u
t
Stable State
Fig. 8.5 Flow t able
Fr om t he flow t able, we obser ve t he following behavior of t he cir cuit .
When X
1
X
2
= 00, t he cir cuit is in st at e a . It is a st able st at e. If X
2
changes t o 1 while
X
1
= 0, t he cir cuit goes t o st at e b (hor izont al move) which is an unst able st at e. Since b is an
unst able st at e, t he cir cuit goes t o c (ver t ical move), which is again an unst able st at e. This
340 S witching Theory
causes anot her ver t ical move and finally t he cir cuit r eaches a st able st at e c . Now consider
X
1
changing t o 1 while X
2
= 1, t her e is a hor izont al movement t o t he next column. Her e b
is an unst able st at e and t her efor e, t her e is a ver t ical move and t he cir cuit comes t o a st able
state
b
. Next change in X
2
fr om 1 t o 0 while X
1
r emaining 1 will cause hor izont al move t o
st at e c (unst able st at e) and finally t o st able st at e c due t o t he ver t ical move. Similar ly
changing X
1
fr om 1 t o 0 while X
2
= 0 will cause t he cir cuit t o go t o t he unst able st at e a and
finally t o st able st at e a . The flow of cir cuit st at es ar e shown by ar r ows.
In t he flow t able of Fig. 8.5 t her e ar e mor e t han one st able st at es in r ows. For example,
t he fir st r ow cont ains st able st at es in t wo columns. If ever y r ow in a flow t able has only one
st able st at e, t he flow t able is known as a primitive flow table.
Fr om a flow t able, t r ansit ion t able can be const r uct ed by assigning binar y values t o each
st at e and fr om t he t r ansit ion t able logic cir cuit can be designed by const r uct ing K-maps for
Q and Q
1
+
2
+
.
8.3.5 C irc uits with La tc he s
In Chapt er 6 lat ches wer e int r oduced. Lat ch cir cuit s using NAND and NOR gat es ar e
shown in Fig. 8.6.
S
R
Q
Q
R
S
Q
Q
( ) a
( ) b
Fig. 8.6 (a) S - R lat ch using NAND gat es. (b) S-R lat ch using NOR gat es.
For t he cir cuit of Fig 8.6a, t he next -st at e equat ion is
Q S. Q S. (QR)
S + RQ
+
= =
=
Similar ly, for t he cir cuit of Fig. 8.6 b, t he next -st at e equat ion is

Q R + Q R + (S + Q)
R . (S Q)
SR + RQ
+
= =
= +
=
Since, S = R = 1 is not allowed, which means SR = 0, t her efor e,
SR SR SR S(R R) S = + = + =
which gives,
Q S RQ
+
= + It is same as t he next -st at e equat ion for t he cir cuit of Fig 8.6a
Asynchronous S equential Logic 341
The t r ansit ion t able of S-R lat ch is shown in Fig. 8.7.
Q
0
1
0
1
0
0 0
0
1
1
SR
00 01 11 10
Q
+
= SR + RQ
= S + RQ
Q
+
Fig. 8.7 Tr ansit ion t able of S-R lat ch
Fr om t he t r ansit ion t able of S-R FLIP-FLOP, we obser ve t hat when SR changes fr om 11
t o 00 t he cir cuit will at t ain eit her t he st able st at e € (fir st r ow, fir st column) or x (second r ow,
fir st column) depending upon whet her S goes t o 0 fir st or R goes t o 0 fir st r espect ively.
Ther efor e, S= R = 1 must not be applied.
Consider an asynchr onous sequent ial cir cuit wit h lat ches shown in Fig. 8.8
S
1
R
1
S
2
R
2
S-R
FF-2
Q
1
X
1
X
2
Q
1
Q
2
Q
1
Q
2
Q
2
S-R
FF-1
X
1
X
2
Q
2
X
1
Q
2
X
1
X
2
Q
1
X
1
X
2
Q
1
0
Y
Fig. 8.8 Asynchr onous sequent ial cir cuit wit h lat ches
For FF-1, R
1
= 0 and t he excit at ion equat ion for S
1
is
S
1
= X X Q X Q
1 2 2 1 2
+
The next -st at e equat ion is
Q
1
+
=
S R Q
1 1 1
+
Subst it ut ing t he value of S
1
we obt ain,
Q
1
+
=
X X Q X Q Q
1 2 2 1 2 1
+ +
Similar ly, t he excit at ion equat ions for FF-2 ar e
S
2
=
X X Q R =X X Q
1 2 1 2 1 2 1
,
342 S witching Theory
The next -st at e equat ion is
Q
2
+
=
S R Q
2 2 2
+
=
X X Q + X X Q Q
1 2 1 1 2 1 2
.
Using next -st at e equat ion for FF-1 and FF-2, t r ansit ion t able is obt ained as shown in Fig.
8.9.
00 01 11 10
Q
1
Q
2
X
1
X
2
00
01
11
10
00 00
11 11 11
10 10 10 10
10
11 11 01 01
10 01
Q
1
Q
2
+ +
Fig. 8.9 Tr ansit ion t able for t he cir cuit of Fig. 8.8
The out put funct ion is
Y = X
1
X
2
Q
1
Q
2
It s flow t able is shown in Fig. 8.10.
d, 0
c , 0
00 01 11 10
a
b
c
d
Q
1
Q
2
X
1
X
2
a , 0 a , 0
d , 0 d , 0 d , 0 d , 0
c , 0
b , 0 b , 0
c , 1 d, 0
c, 0 c, 0
b, 0
Q
1
Q
2
+ +
Fig. 8.10 Flow t able for t he cir cuit of Fig. 8.8
Asynchronous S equential Logic 343
Fr om a flow t able, t r ansit ion t able can be obt ained by assigning binar y values t o t he
st at es. Fr om t he t r ansit ion t able, logic equat ions can be obt ained by const r uct ing K-maps for
S and R input s of ever y lat ch. For t his, t he excit at ion t able of S-R lat ch will be used. Logic
cir cuit can t hen be designed using t he logic equat ion for S, R input s of ever y lat ch.
Example. Design logic circuit using S - R latches for the transition table of Fig. 8.4.
Solution. Since, t her e ar e t wo int er nal st at es Q
1
and Q
2
, t her efor e, t wo S-R lat ches ar e
r equir ed for t he design of logic cir cuit . Let t he t wo lat ches be L
1
and L
2
. The input s and
out put s of t hese lat ches ar e given as
Latch Inputs Outputs
L
1
S
1
, R
1
Q
1
,
Q
1
L
2
S
2
, R
2
Q
2
,
Q
2
The excit at ion t able of an S-R lat ch is given in Table 8.2. This is same as for S-R flip-
flop.
Table 8.2 Excitation table of S-R latch
Present state Next state Inputs
Q Q+ S R
0 0 0 ×
0 1 1 0
1 0 0 1
1 1 × 0
To det er mine S
1
and R
1
for differ ent values of X
1
X
2
, we make use of Q
1
and Q
1
+
values
for ever y squar e of t r ansit ion t able. For example, t his squar e in t he fir st r ow and fir st column
gives Q
1
= 0 and Q
1
+
= 0. This means, for t he pr esent st at e 0 t he cir cuit gives next st at e as
0 for Q
1
. Cor r esponding t o t his we find t he value of S
1
and R
1
using t he Table 8.2, which ar e
S
1
= 0 and R
1
= X.
Thus t he ent r y in t he cell cor r esponding t o X
1
X
2
= 00 and Q
1
Q
2
= 00 for K-map of S
1
will be 0 and for K-map of R
1
it will be X. Similar ly, K-map ent r ies ar e det er mined for S
1
and R
1
.
Following similar pr ocedur e, K-maps for S
2
and R
2
ar e const r uct ed. The K-maps ar e
given in Fig. 8.11.
Fr om t he K-map of Fig. 8.11, we obt ain logic equat ions for S
1
, R
1
, S
2
, and R
2
.
S
1
= X X X X Q
1 2 1 2 2
+
R
1
= X X X Q
1 1 2 2
+
S
2
= X X Q
1 2 2
R
2
= X X
1 2
The logic cir cuit is shown in Fig. 8.12.
344 S witching Theory
00 01 11 10 Q
1
Q
2
X
1
X
2
00
01
11
10
0 0 0
0
1
0
0
1 1
0 × ×
× × × 0
( ) K-map for S
1
a
00 01 11 10
Q
1
Q
2
X
1
X
2
00
01
11
10
×
0 ×
×
1
1
0
0
0
0
0
0
×
1
0
( ) K-map for R
1
b
00 01 11 10 Q
1
Q
2
X
1
X
2
00
01
11
10
0 1 0 0
0
0 ×
×
×
×
0 0 0 0
( ) K-map for S
2
c
×
×
00 01 11 10 Q
1
Q
2
X
1
X
2
00
01
11
10
0 ×
×
×
0
×
× ×
1
1 0
0 0
×
0
0
( ) K-map for R
2
d
×
Fig. 8.11
L
2
S
2
R
2
R
1
S
1
L
1
Q
1
Q
1
X
1
X
2
Q
1
X
1
X
2
X
1
X
2
Q
2
Q
2
X
1
X
2
X
1
X
2
X
1
X
2
Q
1
Q
2
Fig. 8.12
Asynchronous S equential Logic 345
8.3.6 Ra c e s a nd C yc le s
A race condit ion exist s in an asynchr onous sequent ial cir cuit when mor e t han one st at e
var iable change value in r esponse t o a change in an input var iable. This is caused because
of unequal pr opagat ion delays in t he pat h of differ ent secondar y var iables in any pr act ical
elect r onic cir cuit . Consider a t r ansit ion t able shown in Fig. 8.13. When bot h t he input s X
1
and X
2
ar e 0 and t he pr esent st at e is Q
1
Q
2
= 00, t he r esult ing next st at e
Q Q
1
+
2
+
will have
Q
1
+
= 1 and
Q
2
+
= 1 simult aneously if t he pr opagat ion delays in t he pat hs of Q
1
and Q
2
ar e
equal.
00 01 11 10
Q
1
Q
2
X
1
X
2
00
01
11
10
00
11 10 11
10 10
00
11
11
00
11 11
11 01
01 10
Q
1
Q
2
+ +
Fig. 8.13
Since Q
1
and Q
2
bot h ar e t o change and in gener al t he pr opagat ion delays in t he pat hs
of Q
1
and Q
2
ar e not same, t her efor e, eit her Q
1
or Q
2
may change fir st inst ead of bot h
changing simult aneously. As a consequence of t his t he cir cuit will go t o eit her st at e 01 or t o
st at e 10.
If
Q
2
+
changes fast er t han
Q
1
+
, t he next st at e will be 01, t hen 11 (fir st column, second
r ow) and t hen t o t he st able st at e 11 (fir st column, t hir d r ow) will be r eached. On t he ot her
hand, if Q
1
+
changes fast er t han Q
2
+
, t he next -st at e will be 10, t hen 11 (fir st column, four t h
r ow) and t hen t o t he st able st at e (fir st column, t hir d r ow) will be r eached. In bot h t he
sit uat ions, t he cir cuit goes t o t he same final st able st at e 11 . This sit uat ion, wher e a change
of mor e t han one secondar y var iable is r equir ed is known as a race.
Ther e ar e t wo t ypes of r aces: noncritical race and critical race.
In t he case of noncr it ical r ace, t he final st able st at e in which t he cir cuit goes does not
depend on t he sequence in which t he var iables change. The r ace discussed above is a noncr it ical
r ace. In t he case of cr it ical r ace, t he final st able st at e r eached by t he cir cuit depends on t he
sequence in which t he secondar y var iables change. Since t he cr it ical r ace r esult s in differ ent
st able st at es depending on t he sequence in which t he secondar y st at es change, t her efor e, it
must be avoided.
Example. In the transition table of Fig. 8.13, consider the circuit in stable total state
1100. Will there be any race, if the input state changes to 01? If yes, find the type of race.
346 S witching Theory
Solution. When t he cir cuit is in st able t ot al st at e, X
1
X
2
= 00. Now X
2
changes t o 1
while X
1
= 0. Fr om Fig. 8.13 we see t hat t he r equir ed t r ansit ion is t o st at e 00. If
Q
1
+
and
Q
2
+
become 00 simult aneously, t hen t he t r ansit ion will be
11 → 00 → 00
These t r ansit ions ar e shown by solid ar r ows in Fig. 8.14.
00 01 11 10
Q
1
Q
2
X
1
X
2
00
01
11
10
00
11
10
Q
1
Q
2
+ +
00
00
Fig. 8.14
If
Q
2
+
becomes 0 fast er t han
Q
1
+
, t he cir cuit will go t o t he st at e 10 and t hen t o
10
, which
is a st able st at e. The t r ansit ion is
11
→ 10 →
10
On t he ot her hand, if Q
1
+
becomes 0 fast er t han Q
2
+
, t he t r ansit ion will be
11 → 01 → 00 → 00
It is shown by dot t ed ar r ow in Fig. 8.13. Thus, we see t hat t he cir cuit at t ains differ ent
st able st at es
00
or
10
depending upon t he sequence in which t he secondar y var iables
change.
Ther efor e, t he r ace condit ion exist s in t his cir cuit and it is cr it ical r ace.
Races can be avoided by making a pr oper binar y assignment t o t he st at e var iables in a
flow t able. The st at e var iables must be assigned binar y number s in such a way so t hat only
one st at e var iable can change at any one t ime when a st at e t r ansit ion occur s in t he flow t able.
The st at e t r ansit ion is dir ect ed t hr ough a unique sequence of unst able st at e var iable change.
This is r efer r ed t o as a cycle. This unique sequence must t er minat e in a st able st at e,
ot her wise t he cir cuit will go fr om one unst able st at e t o anot her unst able st at e making t he
ent ir e cir cuit unst able.
8.3.7 Pulse - mod e C irc uits
In a pulse-mode asynchr onous sequent ial cir cuit , an input pulse is per mit t ed t o occur
only when t he cir cuit is in st able st at e and t her e is no pulse pr esent on any ot her input .
Asynchronous S equential Logic 347
When an input pulse ar r ives, it t r igger s t he cir cuit and causes a t r ansit ion fr om one st able
st at e t o anot her st able st at e so as t o enable t he cir cuit t o r eceive anot her input pulse. In t his
mode of oper at ion cr it ical r ace can not occur. To keep t he cir cuit st able bet ween t wo pulses,
flip-flops whose out put s ar e levels, must be used as memor y element s.
For t he analysis of pulse-mode cir cuit s, t he model used for t he fundament al-mode cir cuit s
is not valid since t he cir cuit is st able when t her e ar e no input s and t he absence of a pulse
conveys no infor mat ion. For t his a model similar t o t he one used for synchr onous sequent ial
cir cuit s will be convenient t o use.
In pulse-mode asynchr onous cir cuit s t he number of columns in t he next -st at e t able is
equal t o t he number of input t er minals.
Consider a pulse-mode cir cuit logic diagr am shown in Fig. 8.15. In t his cir cuit t her e ar e
four input var iables X
1
, X
2
, X
3
, and X
4
, and Y is t he out put var iable. It has t wo st at es Q
1
and Q
2
.
S-R
FF-2
S-R
FF-1
Q
1
Q
1
S
1
R
1
X
4
X
3
X
2
S
2
R
2
Q
1
X
3
X
4
X
1
Q
1
Q
2
Q
2
Q
2
X
4
Y
Fig. 8.15
The excit at ion equat ions ar e:
S (X X ) or S X X
R X or R X
S Q X or S Q X
R (X Q X ) or R X Q X
1 2 3 1 2 3
1 4 1 4
2 1 1 2 1 1
2 4 1 3 2 4 1 3
= + = +
= =
= =
= + = +
The out put equat ion is: Y =
X Q
4 2
The next -st at e equat ions ar e obt ained by using t he excit at ion equat ions and t he
char act er ist ic equat ion of lat ch.
348 S witching Theory
These ar e:
Q
1
+
=
S R Q
1 1 1
+
=
X X X Q
2 3 4 1
+ +
and
Q S R Q
Q X X Q X Q
Q X X Q X Q
Q X X Q X Q
Q X Q Q X Q X X
2
+
2 2 2
1 1 4 1 3 2
1 1 4 1 3 2
1 1 4 1 3 2
1 1 1 2 4 2 3 4
= +
= + +
= +
= + +
= + +
( ) .
. ( ) .
. ( ) .
The t r ansit ion t able is const r uct ed by evaluat ing t he next -st at e and out put for each
pr esent st at e and input value using next -st at e equat ions and out put equat ion. The t r ansit ion
t able is shown in Fig. 8.16.
Q
1
Q
2
Input variables
X
1
00
01
11
10
01, 0
X
2
X
3
X
4
10, 0 10, 0 00, 1
01, 0 11, 0 10, 0 00, 0
00, 0 11, 0 11, 0 11, 0
10, 0 10, 0 10, 0 10, 0
Output
value
Next-state
value
Present
State
Fig. 8.16
It has four r ows (one r ow for each combinat ion of st at e var iables) and four columns (one
column for each input var iable). Since in pulse-mode cir cuit s only one input var iable is
per mit t ed t o be pr esent at a t ime, t her efor e, t he columns ar e for each input var iable only and
not for t he combinat ions of input var iables.
Flow t able can be const r uct ed fr om t he t r ansit ion t able and is shown in Fig. 8.17. Her e,
S
0
, S
1
, S
2
, and S
3
ar e t he four st at e var iables.
Q
1
Q
2
X
1
S , 0
1
X
2
X
3
X
4
S , 0
3
S , 0
3
S , 1
0
S , 0
1
S , 0
2
S , 0
3
S , 0
0
S , 0
2
S , 0
2
S , 0
2
S , 0
0
S , 0
3
S , 0
3
S , 0
3
S , 1
0
S
0
S
1
S
2
S
3
Present
State
Input variables
Fig. 8.17
Asynchronous S equential Logic 349
Fr om a flow t able a t r ansit ion t able can be const r uct ed by assigning binar y values t o t he
st at es. Fr om a t r ansit ion t able next -st at e equat ions can be obt ained and t he logic diagr am can
t hen be obt ained.
8.4 ASYNC HRO NO US SEQ UENTIAL C IRC UIT DESIG N
Design of asynchr onous sequent ial cir cuit s is mor e difficult t han t hat of synchr onous
sequent ial cir cuit s because of t he t iming pr oblems involved in t hese cir cuit s. Designing an
asynchr onous sequent ial cir cuit r equir es obt aining logic diagr am for t he given design
specificat ions. Usually t he design pr oblem is specified in t he for m of st at ement s of t he desir ed
circuit performance precisely specifying t he circuit operat ion for every applicable input sequence.
8.4.1 De sig n Ste p s
1. Pr imit ive flow t able is obt ained fr om t he design specificat ions. When set t ing up a
pr imit ive flow t able it is not necessar y t o be concer ned about adding st at es which
may ult imat ely t ur n out t o be r edundant . A sufficient number of st at es ar e t o be
included t o complet ely specify t he cir cuit per for mance for ever y allowable input
sequence. Out put s ar e specified only for st able st at es.
2. Reduce t he pr imit ive flow t able by eliminat ing t he r edundant st at es, which ar e
likely t o be pr esent . These r edundant st at es ar e eliminat ed by mer ging t he st at es.
Merger diagram is used for t his pur pose.
3. Binar y number s ar e assigned t o t he st at es in t he r educed flow t able. The binar y
st at e assignment must be made t o ensur e t hat t he cir cuit will be fr ee of cr it ical
r aces. The out put values ar e t o be chosen for t he unst able st at es wit h unspecified
out put ent r ies. These must be chosen in such a way so t hat moment ar y false
out put s do not occur when t he cir cuit swit ches fr om one st able st at e t o anot her
st able st at e.
4. Tr ansit ion t able is obt ained next .
5. Fr om t he t r ansit ion t able logic diagr am is designed by using t he combinat ional
design met hods. The logic cir cuit may be a combinat ional cir cuit wit h feedback or
a circuit wit h S -R lat ches.
The above design st eps is illust r at ed t hr ough an example.
Example. The output (Y) of an asynchronous sequential circuit must remain 0 as long
as one of its two inputs X
1
is 0. While X
1
= 1, the occurrence of first change in another input
X
2
, should give Y = 1 as long as X
1
= 1 and becomes 0 where X
1
returns to 0. Construct a
primitive flow table.
Solution. This cir cuit has t wo input s X
1
, X
2
and one out put Y. For t he const r uct ion of
flow t able, t he next -st at e and out put ar e r equir ed t o be obt ained. The flow t able is shown in
Fig. 8.18.
For X
1
X
2
= 00, let us t ake st at e a. When t he cir cuit has X
1
X
2
= 00 t he out put is 0
(since X
1
= 0) and t he cir cuit is in st able st at e a . The next -st at e and out put ar e shown in
t he fir st column, fir st r ow of Fig. 8.18.Since only one input is allowed t o change at a t ime,
t her efor e, t he next input may be X
1
X
2
= 01 or 10.
If X
1
X
2
= 01, let us t ake anot her st at e b, cor r espondingly t he second r ow of t he flow
t able corresponds t o st at e b. when t he input s change from X
1
X
2
= 00 t o 01, t he circuit is
350 S witching Theory
required t o go t o st able st at e b and out put is 0 (since X
1
= 0). Therefore, t he ent ry in t he
second column, first row will be b, 0 and in t he second column, second row will be b , 0. The
out put corresponding t o unst able st at e b is t aken as 0 so t hat no moment ary false out put s occur
when t he circuit swit ches bet ween st able st at es. On t he ot her hand if X
1
X
2
= 10, t he circuit
is required t o go t o anot her st able st at e c wit h out put 0.Therefore, t he ent ries in t he fourt h
column, first row and fourt h column, t hird row will be respect ively c, 0 and c , 0.
00 01 11 10
X
1
X
2
a
b
c
d
e
f
a , 0
b
, 1 f e, 1
–, –
–, –
–, –
a, –
b, – , 1 e f, 1
b, 0
–, –
f, –
–, –
c, 0
–, –
b, 0
a, 0
a, 0
, 0
d, 0
, 0 c e, –
, 0 d
Present-
state
Fi g. 8.18 Flow table
Since bot h t he input s cannot change simult aneously, t her efor e, fr om st able st at e a , t he
cir cuit cannot go t o any specific st at e cor r esponding t o X
1
X
2
= 11 and accor dingly t he ent r y
in t he t hir d column, fir st r ow will be –, –. The dashes r epr esent t he unspecified st at e, out put .
Now consider t he st able st at e b . The input s X
1
X
2
can change t o 00 or 11.If X
1
X
2
=
00, t he cir cuit will go t o st at e a. Ther efor e, t he ent r y in t he fir st column, second r ow will
be a, 0. Fr om t his unst able st at e t he cir cuit goes t o st able st at e a . On t he ot her hand if
X
1
X
2
= 11, t hen t he cir cuit goes t o a new st at e d. The out put cor r esponding t o X
1
X
2
= 11
will be 0 since, t her e is no change in X
2
, which is alr eady 1. Ther efor e, t he ent r y in t he t hir d
column, second r ow will be d, 0. The four t h r ow cor r esponds t o st at e d, and t he ent r y in t he
t hir d column, four t h r ow, will be d , 0. From b , t he cir cuit is not r equir ed t o go t o any
specific st at e and t her efor e, t he ent r y in t he four t h column, second r ow will be –,–.
Similarly, now consider st able st at e c . The input s can change t o X
1
X
2
= 11 or 00. If
X
1
X
2
= 11, t he cir cuit goes t o a new st able st at e e and t he out put will be 1, since X
2
changes fr om 0 t o 1 while X
1
= 1. The ent r y in t he t hir d column, t hir d r ow will be c, –. Out put
has t o change fr om 0 t o 1 fr om st able st at e c t o st able st at e e , which may or may not
change t o 1 for unst able e. The ent r y in t he t hir d column, fift h r ow will be e , 1. The ent r y
in t he second column t hir d r ow will be –, – and t he ent r y in t he fir st column, t hir d r ow will
be a, 0 (for X
1
X
2
= 00).
In t he same manner, we consider t he st able d and obt ain t he ent r ies f, – (four t h
column, fourt h row); f , 1 (four t h column, sixt h r ow); b, 0 (second column, four t h r ow) and
–, – (fir st column, four t h r ow).
Asynchronous S equential Logic 351
Similar pr ocedur e applied t o e and f , yields t he r emaining ent r ies of t he flow t able.
Since, ever y r ow in t he flow t able of Fig. 8.18 cont ains only one st able st at e, t her efor e,
t his flow t able is a pr imit ive flow t able.
8.4.2 Re d uc tion of Sta te s
The necessit y of r educing t he number of st at es has been discussed in chapt er 6 and t he
equivalent st at es have been defined. When asynchr onous sequent ial cir cuit s ar e designed, t he
design pr ocess st ar t s fr om t he const r uct ion of pr imit ive flow t able. A pr imit ive flow t able is
never complet ely specified. Some st at es and out put s ar e not specified in it as shown in Fig.
8.18 by dashes. Ther efor e, t he concept of equivalent st at es can not be used for r educt ion of
st at es. However, incomplet ely specified st at es can be combined t o r educe t he number of st at es
in t he flow t able. Two incomplet ely specified st at es can be combined if t hey ar e compatible.
Two st at es are compatible if and only if, for ever y possible input sequence bot h pr oduce
t he same out put sequence whenever bot h out put s ar e specified and t heir next st at es ar e
compat ible whenever t hey ar e specified. The unspecified out put s and st at es shown as dashes
in t he flow t able have no effect for compat ible st at es.
Example. In the primitive flow table of Fig. 8.18, find whether the states a and b are
compatible or not. If compatible, find out the merged state.
Solution. The r ows cor r esponding t o t he st at es a and b ar e shown in Fig. 8.19. Each
column of t hese t wo st at es is examined.
00 01 11 10
a
b a, 0 b, 0 d, 0
–, –
c, 0
–, –
b, 0 a , 0
X X
1 2
Fig. 8.19
Column-1. Bot h t he r ows have t he same st at e a and t he same out put 0. a in fir st r ow
is st able st at e and in t he second r ow is unst able st at e.
Since for t he same input bot h t he st at es a and b have t he same specified next -st at e a
and t he same specified out put 0. Ther efor e, t his input condit ion sat isfies t he r equir ement s of
compat ibilit y.
Column-2. The input condit ion X
1
X
2
= 01 sat isfies t he r equir ement s of compat ibilit y as
discussed for column-1.
Column-3. The fir st r ow has unspecified next -st at e and out put and t he second r ow has
specified st at e and out put . The unspecified st at e and out put may be assigned any desir ed st at e
and out put and t her efor e, for t his input condit ion also t he r equir ement s of compat ibilit y ar e
sat isfied.
Column-4. The r equir ement s of compat ibilit y ar e sat isfied for t he r easons same as
applicable t o column-3.
Ther efor e, we conclude t hat since t he next -st at es and t he out put s for all t he input
combinat ions ar e compat ible for t he t wo st at es a and b, t he t wo st at es ar e compat ible.The
mer ged st at e will be as shown in Fig. 8.20
352 S witching Theory
00 01 11 10
a , 0
X X
1 2
b , 0 d, 0 c, 0 a
Fig. 8.20
When t he mer ged st at e ent r ies ar e det er mined a cir cled ent r y and an uncir cled ent r y
r esult s in a cir cled ent r y, since t he cor r esponding st at e must be st able as shown in Fig. 8.20.
Example. In the primitive flow table of Fig. 8.18 find whether the states a and e are
compatible or not. Examine their compatibility if the entries in the fourth column for the states
a and e have same output.
Solution. The par t ial flow t able for st at es a and e of Fig. 8.18 is shown in Fig. 8.21.
00 01 11 10
a
e –, – b, – e , 1 f, 1
c, 0
–, –
b, 0 a , 0
X X
1 2
Fig. 8.21
Fr om t his we obser ve t he following
Column-1 compat ible
Column-2 compat ible
Column-3 compat ible
Column-4 not compat ible, since t he out put s ar e differ ent .
Ther efor e, t he st at es a and e ar e not compat ible.
In case of same out put in column-4, t he out put s ar e said t o be not conflict ing and t he
st at es a and e ar e compat ible if and only if t he st at es c and f ar e compat ible. This is r efer r ed
t o as c, f is implied by a, b or a, b implies c, f.
8.4.3 M e rg e r Dia g ra m
A merger diagram (or graph) is pr epar ed for a pr imit ive flow t able t o det er mine all t he
possible compat ible st at es (maximal compat ible st at es) and fr om t his a minimal collect ion of
compat ibles cover ing all t he st at es.
A mer ger gr aph is const r uct ed following t he st eps out lined below:
• Each st at e is r epr esent ed by a ver t ex, which means it consist s of n ver t ices, each
of which cor r esponds t o a st at e of t he cir cuit for an n- st at e pr imit ive flow t able.
Each ver t ex is labelled wit h t he st at e name.
• For each pair of compat ible st at es an undir ect ed ar c is dr awn bet ween t he ver t ices
of t he t wo st at es. No ar c is dr awn for incompat ible st at es.
• For compat ible st at es implied by ot her st at es a br oken ar c is dr awn bet ween t he
st at es and t he implied pair s ar e ent er ed in t he br oken space.
The flow t able is r equir ed t o be examined for all t he possible pair s of st at es. All t he pair s
ar e checked and t he mer ger gr aph is obt ained. Thus we see t hat t he mer ger gr aph displays
all possible pair s of compat ible st at es and t heir implied pair s. Next it is necessar y t o check
whet her t he incompat ible pair (s) does not invalidat e any ot her implied pair. If any implied pair
Asynchronous S equential Logic 353
is invalidat ed it is neglect ed. All t he r emaining valid compat ible pair s for m a gr oup of maximal
compat ibles.
The maximal compat ible set can be used t o const r uct t he r educed flow t able by assigning
one r ow t o each member of t he gr oup. However, t he maximal compat ibles do not necessar ily
const it ut e t he set of minimal compat ibles. The set of minimal compat ibles is a smaller
collect ion of compat ibles t hat will sat isfy t he r ow mer ging.
The condit ions t hat must be sat isfied for r ow mer ging ar e:
• t he set of chosen compat ibles must cover all t he st at es, and
• t he set of chosen compat ibles must be closed.
The condit ion of cover ing r equir es inclusion of all t he st at es of t he pr imit ive flow gr aph
in t he set of chosen compat ibles. This condit ion only defines a lower bound on t he number
of st at es in t he minimal set . However, if none of t heir implied pair s ar e cont ained in t he set ,
t he set is not sufficient and t his is r efer r ed t o as closed condit ion not being sat isfied. Ther efor e,
condit ion of closed covering is essent ially r equir ed for r ow mer ging.
8.5 ESSENTIAL HAZARDS
Similar t o st at ic and dynamic hazar ds in a combinat ional cir cuit s, essent ial hazar ds occur
in sequent ial cir cuit s. Essent ial hazar d is a t ype of hazar d t hat exist s only in asynchr onous
sequent ial cir cuit s wit h t wo or mor e feedbacks. Essent ial hazar d occur s nor mally in t oggling
t ype cir cuit s. It is an er r or gener ally caused by an excessive delay t o a feedback var iable in
r esponse t o an input change, leading t o a t r ansit ion t o an impr oper st at e. For example, an
excessive delay t hr ough an inver t er cir cuit in compar ison t o t he delay associat ed wit h t he
feedback pat h many cause essent ial hazar d. Such hazar ds cannot be eliminat ed by adding
r edundant gat es as in st at ic hazar ds. To avoid essent ial hazar d, each feedback loop must be
designed wit h ext r a car e t o ensur e t hat t he delay in t he feedback pat h is long enough
compar ed t o t he delay of ot her signals t hat or iginat e fr om t he input t er minals.
Even t hough an asynchr onous sequent ial cir cuit (net wor k) is fr ee of cr it ical r aces and t he
combinat ional par t of t he net wor k is fee of st at ic and dynamic hazar ds, t iming pr oblems due
t o pr opagat ion delays may st ill cause t he net wor k t o malfunct ion and go t o t he wr ong st at e.
To bet t er under st and, consider for example t he net wor k of Fig. 8.22.
FF1
0 1 0 → →
y
1
y
1
S
1
R
1
0 1 0 → →
0 1 →
G
1
G
2
y
2
y
2
x
0 1 →
0 1 →
0 1 →
x
1→0
FF2
y
2
y
2
S
2
R
2
0 1 0 → →
0 1 0 → →
G
3
G
4
y
1
1→0
1→0
y
1
0 1 →
x
y y
1 2
00
01
10
11
11
11
00
00
01
10
01
10
0 1
x
y y
1 2
00
01
10
11
c
c
a
a
b
d
b
d
0 1
Characteristic equation
y (next) = S + R y = xy + (x + y )y
y (next) = S + R y = xy + (x + y ) y
1 1 1 1 2 2 1
2 2 2 2 1 1 2
0 1 →
x
Fig. 8.22 Net wor k wit h essent ial hazar ds.
354 S witching Theory
Ther e is no hazar ds in t he combinat ional par t of t he net wor k, and flow t able inspect ion
shows t hat t her e ar e no cr it ical r aces. If we st ar t in st at e a and change x t o 1, t he net wor k
should go t o st at e
d
. Let consider t he following possible sequence of event s.
(i) x change 0 t o 1.
(ii) Gat e 3 (G2) out put changes 0 t o 1.
(iii) Flip-flop (FF1) out put y
1
changes 0 t o 1.
(iv) G4 out put changes 0 t o 1.
(v) FF2 out put changes 0 t o 1.
(vi) Invert er out put x changes 1 t o 0.
(vii) G1 out put changes 0 t o 1, G2 out put changes back t o 0, and G4 out put changes back
t o 0.
(viii) Flip-flop out put y
1
changes back t o 0.
Though t he net wor k should go t o st age d when change x t o 1 but t he final st at e of t he
network is b inst ead of d . The malfunct ion illust r at ed in example net wor k of figur e is
r efer r ed t o as an essent ial hazar d. This came about because t he delay in inver t er was lar ge
t han t he ot her delays in t he net wor k, so t hat par t of t he net wor k having value x = 1 while
ot her part have value x = 0. The final r esult was t hat t he net wor k act ed as if t he input x
had changed t hr ee t imes inst ead of once so t hat t he net wor k went t hr ough t he sequence of
st at es y
1
y
2
= 00, 10, 11, 01. Essent ial hazar ds can be locat ed by inspect ion of t he flow t able.
An essent ial hazar d can be defined as follows:
A flow t able has an essent ial hazar d st ar t ing in st able t ot al st at e
s
for input var iable
x
i
if and only if t he st able t ot al st at e r eached aft er one change in x
i
differ ent fr oms t he st able
t ot al st at e r eached aft er t hr ee changes in x
i
.
If an essent ial hazar d exist s in t he flow t able for t ot al st able st at e
s
and input x
i
, t hen
due t o some combinat ion of pr opagat ion delays net wor k go t o t he wr ong st at e when x
i
is
changed st art ing in
s
on r ealizat ion. This occur s because t he change in x
i
r eaches differ ent
par t s of t he net wor k at differ ent t imes.
In or der t o t est a flow t able for essent ial hazar ds it is necessar y t o t est each st able t ot al
for each possible input change using t he definit ion of essent ial hazar d given.
Essent ial hazar ds can be eliminat ed by adding delays t o t he net wor k. For t he net wor k
show in figur e, t he essent ial hazar d can be eliminat ed by adding a sufficient ly lar ge delay t o
t he out put of FF1, because he change in x out put of FF1 does.
We can summar ize t he design of an asynchr onous net wor k is fr ee of t iming pr oblems as:
(i) Make a st at e assignment which is fr ee of cr it ical r aces.
(ii) Design t he combinat ional par t of t he net wor k so t hat it is fr ee of hazar ds (if r equir e
by adding r edundant gat es).
(iii) Add delays in t he feedback pat hs for t he st at e var iables as r equir ed t o eliminat e
essent ial hazar ds.
8.6 HAZARD- FREE REALIZATIO N USING S- R FLIP- FLO PS
The design of hazar d-fr ee asynchr onous net wor ks can be simplified using S-R flip-flops.
We have alr eady seen in chapt er 6 t hat a moment ar y 1 applied t o t he S or R input can set
or r eset t he flip-flop, however a moment ar y 0 applied t o S or R will have no effect on t he flip-
Asynchronous S equential Logic 355
plop st at e. Since a 0-hazard can produce a moment ary false 1, t he net works realizing S and R
must be free of 0-hazards but t he S and R net works may cont ain 1-hazards. A minimum t wo-
level sum of product s expression is free of 0-hazards but it may cont ain 1-hazards. For t his
reason, t he minimum sum of product s can be used as a st art ing point for realizing t he S-R flip-
flop input equat ions. Simple fact oring or t ransformat ion which do not int roduce 0-hazards can
be applied t o t he minimum sum-of-product s expressions, in t he process of realizing S and R.
A t ypical net wor k st r uct ur e wit h t he S-R flip-flop dr iven by 2-level AND-OR net wor ks
const r uct ed fr om cr oss-coupled NOR gat es is shown in Fig. 8.23(a). The Fig. 8.23(b) shows
equivalent net wor k st r uct ur e wit h mult iple input NOR gat es. The t wo st r uct ur e ar e equivalent
since in bot h cases.
Q =
( .......) Q + R R
1 2
+ + ′
and
Q
= (Q + S
1
+ S
2
+ .......)′
R
S
Q
Q
S
2
S
1
R
2
R
1
( ) S-R flip-flop driven by 2-level AND-OR network a
Q
Q
S
2
S
1
R
2
R
1
( ) Equivalent network structure b
Fi g. 8.23 Gat e st r uct ur es for S-K flop-flip r ealizat ion of flow t able.
356 S witching Theory
Even if an asynchr onous net wor k is r ealized using S-R flip-flops and S and R net wor ks
ar e fr ee of 0-hazar ds, essent ial hazar ds may st ill be pr esent . Such essent ial hazar ds may be
eliminat ed as discussed pr eviously by adding delays in t he feedback pat hs for t he st at e
variables.
An alt er nat ive met hod for eliminat ing essent ial hazar ds involves changing t he gat e
st r uct ur e of t he net wor k. This met hod can be applied only if wir ing delays ar e negligible and
all t he gat e delays ar e concent r at ed at t he gat e out put s.
As illust r at ed in pr evious sect ion, t he following sequence of event s is needed for an
essent ial hazar d t o cause a net wor k of malt funct ion.
(i) An input var iable changes.
(ii) A st at e var iable changes in r esponse t o t he input var iable change.
(iii) The effect of t he st at e var iable change pr opagat es t hr ough t he net wor k and init iat es
anot her st at e var iable change befor e.
(iv) The or iginal input var iable change has pr opagat ed t hr ough t he ent ir e net wor k.
Ther efor e, in an asynchr onous net wor k wit h S-R flip-flops, we can eliminat e t he essent ial
hazar ds by ar r anging t he gat e st r uct ur e so t hat t he effect of any input change will pr opagat e
t o all flip-flop input s befor e any st at e var iable changes can pr opagat e back t o t he flip-flop
input s. For example, t he essent ial hazar d of Fig. 8.24 can be eliminat ed by r eplacing t he R
2
and S
2
net wor ks wit h t he net wor k of Fig. 8.24.
y
1
x
y
1
R
2
S
2
Fig. 8.24
Assuming t hat wir ing delays ar e negligible t hat t he gat e delay is concent r at ed at t he
gat e out put any change in x will pr opagat e t o R
2
and S
2
befor e flip-flop 1 out put y
1
can
change st at e and t his change in y
1
can pr opagat e t o R
2
and S
2
. This eliminat es t he essent ial
hazar d.
In t he Fig. 8.23 (b), each AND gat e can have input s of t he for m shown in Fig. 8.25 (a),
where x’s ar e ext er nal input s t o t he cir cuit , and t he y’s ar e feedback fr om flip-flop out put s.
If t her e ar e essent ial hazar ds in t he flow t able, t hen t he cir cuit could malfunct ion due t o t he
inver t er delays. By r eplacing t he AND gat e wit h t he NOR-AND net wor k of Fig. 8.25 (b), t he
invert ers on t he x var iables ar e eliminat ed. Ther efor e by r eplacing all of t he AND gat e in
Fig. 8.23 wit h t he NOR-AND combinat ions as indicat ed in Fig. 8.25, all of t he est imat es
hazar ds will be eliminat ed.
Asynchronous S equential Logic 357
( ) Replacement for ( ) b a
S (or R )
i i
x
n
x
q
y

1
y

j
y
k
y
p
x
1
x
m
x
q
x
n
x
1
x
m
y
y
y
j
y′
k
y′
p
S (or R )
i i
( ) AND gate with general inputs a
Fig. 8.25 A gat e t r ansfor mat ion for eliminat ion of essent ial hazar ds.
8.7 SO LVED EXAM PLES
Example 1. Construct merger diagram for the primitive flow table of Fig. 8.18. Determine
maximal compatibles and the minimal set of compatibles.
Solution: For const r uct ion of mer ger diagr am, ever y r ow of t he pr imit ive flow t able is
checked wit h ever y ot her r ow t o det er mine compat ibilit y of st at es.
Consider r ow-1 (st at e a)
a, b ar e compat ible
a, c ar e compat ible
a, d ar e compat ible if c, f ar e compat ible
a, e ar e compat ible if c, f ar e compat ible
a, f ar e compat ible if c, f ar e compat ible
r ow-2 (st at e b)
b, c ar e compat ible if d, e ar e compat ible
b, d ar e compat ible
b, e ar e not compat ible (out put s ar e conflict ing)
b, f ar e not compat ible (out put s ar e conflict ing)
r ow-3 (st at e c)
c, d ar e compat ible if e, d and c, f ar e compat ible
358 S witching Theory
c, e ar e not compat ible (out put s ar e conflict ing)
c, f ar e not compat ible (out put s ar e conflict ing)
r ow-4 (st at e d)
d, e ar e not compat ible (out put s ar e conflict ing)
d, f ar e not compat ible (out put s ar e conflict ing)
r ow-5 (st at e e)
e, f ar e compat ible
The pr imit ive flow t able has six st at es t her efor e, t her e ar e six ver t ices in t he mer ger
diagr am as shown in Fig. 8.26.
a
f
e
d
c
b
Fi g. 8.26 Merger di agram
Solid ar cs ar e dr awn bet ween (a, b), (a, c), (b, d) and (f, e) ver t ices. Cor r esponding
t o t hese st at es being compat ibles. Since (c, f) and (d, e) ar e not compat ible, t her efor e,
t her e ar e no implied pair s available.
Fr om t he mer ger diagr am, we get t he maximal compat ibles:
(a, b), (a, c), (b, d), (e, f)
Since ( a, b) is cover ed by (a, c) and (b, d), t her efor e, t he minimal set is (a, c), (b, d),
(e, f)
Example 2. Determine the reduced flow table of Fig. 8.19.
Solution: Fr om t he mer ger diagr am, we have obt ained t hr ee pair s of compat ible st at es:
These compat ibles ar e mer ged and ar e r epr esent ed by
a, c : S
0
b, d : S
1
e, f : S
2
The r educed flow t able is shown in Fig.
8.27
00 01 11 10
X
1
X
2
S
0, 0 S , 0
1
S
1
S
2
S
0
S , –
2
S , –
2
S , 0
0
S , –
0
S , –
1
S , 0
1
S , 0
1
S , 1
2
S , 1
2
S , 0
0
Present-state
Fig. 8.27 Reduced flow t able
Asynchronous S equential Logic 359
Example 3. Assign binary states to the reduced flow table of Fig. 8.27. Avoid critical race.
Solution: Let us assign t he following binar y st at es t o S0, S1, and S2 for t he r educed flow
t able of Fig. 8.27
S0 → 00
S1 → 01
S2 → 11
The t r ansit ion t able will be as shown in Fig. 8.28
00 01 11 10 Q
1
Q
2
X
1
X
2
00
01
11
10
00, 0
01, 0 01, 0
00, 0
11, 1 11, 1 01, – 00, –
00, 0 11, –
11, – 01, 0
Fig. 8.28 Tr ansit ion t able
In t he t r ansit ion t able of Fig. 8.28, we obser ve t hat r ace condit ion occur s in t he following
cases:
(i) Fr om st able st at e 00 t o unst able st at e 11 when X
1
X
2
changes fr om 10 t o 11.
(ii) Fr om st able st at e 11 t o unst able st at e 00 when X
1
X
2
changes fr om 10 t o 00.
To avoid cr it ical r ace, one unst able st at e 10 is added wit h t he ent r ies 00, –; –, –; 11,
–; –, – and t he ent r ies in t hir d column, fir st r ow is changed fr om 11, – t o 10, – and in fir st
column, t hir d r ow fr om 00, – t o 10, –.
The modified t r ansit ion t able is given in Fig. 8.29.
00 01 11 10 Q
1
Q
2
X
1
X
2
00
01
11
10 00, –
–, –
11, –
–, –
11, 1 11, 1 01, – 10, –
00, 0 01, 0 01, 0 11. –
00, 0 10, – 01, 0 00, 0
Fig. 8.29 Modified t r ansit ion t able
360 S witching Theory
Example 4. Design logic circuit with feedback for the transition table of Fig. 8.29.
Solution: The K-maps for
Q Q
1
+
2
+
,
, and Y det er mined fr om t he t r ansit ion t able ar e given
in Fig. 8.30.
Fr om t he K-maps, we obt ain,
Q
1
+
=
X X Q X Q Q X X Q X Q
1 2 2 2 1 2 1 2 2 1 1
+ + +
Q
2
+
=
X X X Q X Q
1 2 1 2 1 1
+ +
Y = Q
1
Logic cir cuit using gat es can be obt ained fr om t he above logic equat ions.
Thus we see t hat t he design st eps out lined above can be used t o design an asynchr onous
sequent ial cir cuit .
Fig. 8.30 K-Maps for (a) Q
1
+
(b) Q
2
+
(c) Y
Example 5. In the state transition table of Fig. 8.13, if X
1
X
2
= 10 and the circuit is in
stable state 01 , find the cycle when X
2
is changed to 1 while X
1
remaining 1.
Solution: The cir cuit is in st able st at e 01 (four t h column, second r ow). When X
2
changes t o 1, t he cir cuit will go t o t he st at e 11 (t hir d column, second r ow), t hen t o st at e 10
Asynchronous S equential Logic 361
(t hir d column, t hir d r ow) and finally t o t he st able st at e 10 (t hir d column, four t h r ow). Thus
t he cycle is
01 → 11 → 10 → 10
8.8 EXERC ISES
1. (a) Explain t he differ ence bet ween asynchr onous and synchr onous sequent ial
cir cuit s.
(b) Define fundament al mode of oper at ion.
(c) Define pulse mode of oper at ion
(d) Explain t he differ ence bet ween st able and unst able st at es.
(e) What is t he differ ence bet ween int er nal st at e and t ot al st at e.
2. Descr ibe t he design pr ocedur e for asynchr onous sequent ial cir cuit s.
3. What do you mean by cr it ical and non-cr it ical r aces? How can t hey be avoided.?
4. Descr ibe cycles in asynchr onous sequent ial cir cuit s.
5. Design a J K flip-flop asynchr onous sequent ial cir cuit t hat has t wo input s and single
out put . The cir cuit is r equir ed t o give an out put equal t o 1 if and only if t he same
input var iable changes t wo or mor e t imes consecut ively.
6. Design an asynchr onous cir cuit t hat has t wo input s and single out put .The cir cuit
is r equir ed t o give an out put whenever t he input sequence 00,10,11 and 01 ar e
r eceived but only in t hat or der.
7. (a) Design a n a synchr onous bina r y count er wit h one pulse input a nd t wo
out put s,capable of count ing fr om zer o t o t hr ee .When t he cir cuit is pulsed aft er
t he count has r eached t hr ee,it should r et ur n t o zer o.The out put should pr ovide
cont inuosly t he count modulo 4.
(b) Repr at t he pr oblem for level input s and out put s.
8. Find all of t he essent ial hazar ds in t he following flow t able. How can t able essent ial
hazar d which occur s st ar t ing in b be eliminat ed.
X
1
X
2
Q
1
Q
2
00 01 11 10
a 00 a b a d
b 01 a b c –
c 11 – d c d
d 10 a d a d
362 S witching Theory
9
CHAPTER
9.0 INTRO DUC TIO N
Finit e st at e machines ar e a power ful t ool for designing sequent ial cir cuit s, but t hey ar e
lacking in t hat t hey do not explicit ly r epr esent t he algor it hms t hat comput e t he t r ansit ion or
out put funct ions, nor is t iming infor mat ion explicit ly r epr esent ed. We can r ecast t he idea of
a st at e machine t o include a r epr esent at ion of t he algor it hms. The r esult is an algorithmic
state machine, or ASM. “The ASM char t separ at es t he concept ual phase of a design fr om t he
act ual cir cuit implement at ion.” An algor it hmic st at e machine diagr am is similar t o a flowchar t
but wit h some differ ences. Squar e boxes r epr esent t he st at es, diamonds r epr esent decisions,
and ovals r epr esent out put s. St at es can also have out put s, and t he out put s associat ed wit h
a st at e ar e list ed in t he st at e box. St at e boxes ar e labelled wit h t he st at e name and possibly
wit h a binar y code for t he st at e. The basic unit of an ASM is t he ASM block. An ASM block
cont ains a single st at e box, a single ent r y pat h, and one or mor e exit pat hs t o ot her ASM
blocks. Algor it hmic st at e machines capt ur e t he t iming of st at e t r ansit ions as well.
9.1 DESIG N O F DIG ITAL SYSTEM
In t he ear lier chapt er s we have pr esent ed t he analysis and design of var ious t ypes of
Digit al Syst em for specified t ask. A close look on all such syst ems r eveal t hat t hese syst ems
can be viewed as collect ion of t wo subsyst ems.
(i) The Dat a Pr ocessing or manipulat ing subsyst em which include t he oper at ion such
as shift ing, Adding, count ing, dividing et c.
(ii) The cont r ol subsyst em or simply cont r ol. This subsyst em has t o init iat e, super wise
and sequence t he oper at ion in dat a pr ocessing unit .
Usually design of dat a pr ocessor is afair and simple design. But design of cont r ol logic
wit h available r esour ces is a complex and challenging par t , per haps because of t iming r elat ions
bet ween t he event . And in t his chapt er we ar e major it y concer ned wit h design of cont r ol.
The cont r ol subsyst em is a sequent ial cir cuit whose int er nal st at es dict at e t he cont r ol
command t o sequence t he oper at ions in dat a pr ocessing unit . The digit al cir cuit used as
cont r ol subsyst em is r esponsible t o gener at e a t ime sequence of cont r ol signals t hat init iat es
oper at ion in dat a pr ocessor, and t o det er mine t he next st at e of cont r ol subsyst em it self. The
t ask of dat a pr ocessing and cont r ol sequence ar e specified by means of a hardware algorithm.
An algor it hm is a collect ion of produces t hat t ells how t o obt ain t he solut ion. A flow chart
is a simple way t o r epr esent t he sequence of pr ocedur es and decision pat hs for algor it hm.
A hardware algorithm is a pr ocedur e t o implement t he pr oblem wit h t he available
har dwar e or r esour ce. A flow char t for har dwar e algor it hm t r anslat es t he wor d st at ement s
362
ALGORITHMIC STATE MACHINE
Algorithmic S tate Machine 363
t o an infor mat ion of diagr am, t hat enumer at es t he sequence of oper at ions along wit h t he
necessar y condit ion for t heir execut ion.
A special flow char t , developed specifically t o define t he “Digit al Har dware Algor it hm” is
called as an Algorithmic State Machine (ASM) chart . In fact , a sequent ial circuit is alt ernat ely
called as st at e machine and for ms t he basic st r uct ur e of a digit al syst em. A convent ional flow
char t descr ibes t he sequence of pr ocedur al st eps and decision pat hs for an algor it hm wit hout
concer n for t heir t iming r elat ionship. The ASM char t descr ibes t he sequence of event s as well
as t he t iming r elat ionship bet ween t he st at es of sequent ial cont r oller s and t he event s t hat
occur while going fr om one st at e t o next st at e. The ASM char t is specifically adapt ed t o
accurat ely specify t he cont rol sequence and dat a processing in digit al syst ems, while considering
t he const r aint s of available har dwar e.
9.2 THE ELEM ENTS AND STRUC TURE O F THE ASM C HART
An ASM char t is composed of four element s. These ar e t he “st at e box”, t he “decision box”,
t he “condit ional out put box” and “edges”.
Sta te Bo xe s
St at e boxes descr ibe a st at e of t he ASM. In gener al an ASM is a sequent ial syst em. The
st at e box r epr esent s t he condit ion of t he syst em. The symbol for a st at e box is as follows:
Entrance Point
Optional State
Number
State Name
Register Operation
or Operation name
or Outputs
Exit Point
R
Begin
S
1
001
1
Fig. 9.1 (a) St at e Box Fi g. 9.1 (b) Example of St at e Box
The st at e box has exact ly one ent r ance point and one exit point . The st at e box also has
a name and is oft en assigned a number for clar it y. Inside t he st at e box we place t he names
of t he syst em out put s t hat must be asser t ed while t he syst em is in t hat st at e. We can also
place var iable assignment s in t he st at e box, in or der t o “r emember ” t he fact t hat t he syst em
has been in t hat st at e. This is useful in pr ogr am design.
NOTE: Sequent ial syst ems ar e syst ems wit h memor y; t heir out put depends on t heir
input as well as t heir hist or y. The hist or ical infor mat ion t hat t he syst em st or es is called a
‘st at e’. Combinat ional syst ems ar e t he opposit e, having no memor y. Combinat ional syst ems
out put depends only on pr esent input s.
De c isio n Bo xe s
Decision boxes ar e used t o show t he examinat ion of a var iable and t he out comes of t hat
examinat ion. In t his model t he out come of a decision is always eit her t r ue or false. This
364 S witching Theory
means t hat t her e is always exact ly one input t o a decision box and exact ly t wo exit s fr om t he
box. The exit point s ar e always labelled “t r ue” or “false” for clar it y. When input condit ion is
assigned a binar y value, t he t wo exit pat hs ar e labelled 1 and 0. 1 in place of ‘Tr ue’ and 0
in place of ‘False’. The condit ion which is being examined is wr it t en inside t he decision box.
The symbol for a decision box is shown her e:
True
Exit-Point if condition
False
Exit Point if condition False
Entry Point
Boolean condition to
be examined
Fig. 9.2 Decision Box
Not e t hat t he decision box does not imply a syst em st at e. When a decision box is
execut ed t he decision is made and t he syst em pr oceeds immediat ely t o t he next it em in t he
ASM char t .
C o nd itio na l O utp ut Bo xe s
Condit ional out put boxes ar e used t o show out put s which ar e asser t ed by t he syst em “on
t he way” fr om one st at e t o anot her. The symbol for t he condit ional out put box is shown her e
in Fig. 9.3(A).
Register Operation or
outputs to be asserted
Entry point
Exit point
01 S
1
S
0 00
00
R
1
1
Initial state
1
Z
X
Fig. 9.3 (a) Condit ional Box Fig. 9.3 (b) Use of Condit ional Box.
There is always one ent ry and one exit point from a condit ional out put box. Inside t he box
we writ e t he name of t he signal t hat must be assert ed by t he syst em as it passes from one st at e
t o anot her. Input pat h t o condit ional box must come from an exit pat h of decision box.
Condit ional out put boxes do not imply a syst em st at e. We can put var iable assignment s
in t he st at e box. Figur e 9.3 (b) shows an example using condit ional box. The fir st one in
diagr am is init ial st at e (Labled S
0
) syst em which at t ains cer t ain condit ions fulfilled befor e
st ar t ing t he act ual pr ocess. The cont r ol t hen checks t he input X. If X = 0, t hen cont r ol
gener at es t he Z out put signal and go t o st at e S
1
ot her wise it moves t o next st at e wit hout
gener at ing Z. R
1
← 1 in st at e box S
1
is a r egist er oper at ion t hat loads R
1
by 1.
Algorithmic S tate Machine 365
Edges ar e used t o connect ot her ASM char t element s t oget her. They indicat e t he flow
of cont r ol wit hin t he syst em. The symbol for an edge is as follows:
Not e t hat t he edge must always indicat e which dir ect ion is being t aken, by using one or
mor e ar r ow heads.
9.2.1 ASM Bloc k
An ASM block is a st r uct ur e t hat cont ains one st at e box and all decision boxes and
condit ional boxes connect ed t o it s exit pat h spanning just befor e anot her st at e box. An ASM
block has only one ent r y pat h put number of exit pat hs r epr esent ed by t he st r uct ur e of
decision boxes. Fig. 9.4 shows an ASM block, in ASM char t by dashed lines ar ound it .
X
Y
1
0
1
S
0
000
R
Start
1
0
R
2
0
R
3
1
0
S
1
001
S
2
010
Valid
An ASM Block
Fig. 9.4 Example of ASM Block-St r uct ur e enclosed by dashed line r epr esent an ASM block.
Each ASM block is an ASM char t r epr esent s t he st at e of syst em dur ing one clock pulse. The
oper at ions specified by t he st at e box, condit ional boxes, and decision boxes ar e execut ed dur ing
a common clock pulse while t he syst em is in S
0
st at e. The same clock pulse is also r esponsible
t o move t he cont r oller t o one of t he next st at es, S
1
or S
2
det er mined by binar y st at us of X and
Y. A st at e box wit hout any decision or condit ional boxes const it ut es a simple block.
9.2.2 Re g iste r O p e ra tion
A digit al syst em consist of one or mor e r egist er s for dat a st or age. Thus oper at ion t o be
per for med on dat a is act ually per for med on t he r egist er t hat st or es t he dat a. A r egist er is a
gener al designat ion which includes shift r egist er s, count er s, st or age r egist er s, and single Flip-
Flops. A single Flip-flop is ident ified as 1-bit r egist er. A r egist er is designat ed by use of one
or mor e capit al let t er s such as A, B, RA, RB, R
1
, R
2
. In pr act ice most convenient designat ion
is let t er R along wit h number s such R
1
, R
2
, ... R
n
.
366 S witching Theory
Regist er oper at ions can be incr ement , decr ement , shift , r ot at e, addit ion, cleaning, copying,
dat a t r ansfer et c. The dat a t r ansfer t o a r egist er fr om anot her r egist er or fr om t he r esult of
mat hemat ical oper at ions et c. ar e shown (or symbolized) by dir ect ed ar r ow whose head is
t owar ds t ar get r egist er and t ale is t owar ds sour ce r egist er. Fig. 9.5 summar izes t he symbolic
not at ions for some of r egist er oper at ions.
S ymbolic Initial Initial Value Value of Description
Notation Value of of S ource Target of Operation
of Operation Target Register Register
Register After
Operation
A ← B A = 01010 B = 00000 A = 00000 Copy t he cont ent of r egist er B
int o regist er A
R
1
← 0 R
1
= 11111 – R
1
= 00000 Clear r egist er R
1
A ← A + B A = 01010 B = 00101 A = 01111 Add t he cont ent s of r egist er B
t o r egist er A and put r esult in
A.
R ← R – 1 R = 01101 – R = 00100 Decr ement r egist er R by 1.
R ← R + 1 R = 00101 – R = 00110 Incr ement r egist er R by 1.
“Shift Left A” A = 10111 – A = 01110 Shift cont ent of A t o left by
1-bit
“Rot at e A = 10111 – A = 11011 Rot at e cont ent of A t o r ight by
Right A” 1-bit
R ← 1 R = 01010 – R = 00001 Set cont ent R t o 1
Fig. 9.5 Symbolic Repr esent at ion or r egist er oper at ion.
Assume 5-bit r egist er t o under st and t he oper at ions. Not e t hat shift and r ot at e oper at ion
are not same. Shift left means MSB ← MSB-1, MSB-1 ← MSB-2, ..., LSB + 1 ← LSB,
LSB ← 0. If r ot at e r ight oper at ion t hen MSB ← ISB, MSB-1 ← MSB, ... LSB ← LSB + 1. It
is clear t hat in shift oper at ion loose MSB if left shift or LSB if r ight shift because as above
explained MSB was over wr it t en by cont ent of MSB-1, and pr ior t o t his value of MSB was not
saved. And t hat ’s why a 0 is inser t ed at LSB. In r ot at e oper at ion we don’t loose t he st at us
of bit s. If we r ot at e left t hen st at us of MSB is t r ansfer r ed t o LSB and t hen it is over wr it t en
by t he value of MSB-1.
Equipped wit h t his many knowledge and underst anding we are able t o draw and underst and
t he simple ASM char t s and wit h analysis and synt hesis we can figur e out t he similar it y of
ASM char t s wit h t hat of st at e diagr am.
In t he next sect ion (ar t 9.3) we pr esent some simple examples t o give you a feel of ASM
char t and it s r epr esent at ion.
9.2.3 ASM C ha rts
Example 9.1. 1-Bi t Ha l f Ad d er : The half adder take the two data bits if S TART input
is activated otherwise it remains in initial state. The data bits are read into register R
1
and
R
2
and sum and carry bits are maintained in register R
3
and R
4
respectively AS M chart for
this task is shown into Fig. 9.6.
Algorithmic S tate Machine 367
S
0
00
InitialState
Start
R
4
R
3
SUM
0
1
O
1
1
S
1
01
0
R Input bit A
1

R Input bit B
2

R R EX-OR R
3 1 2

R R AND R
4 1 2

CARRY
Fig. 9.6 ASM Chart for 1-bit Half Adder.
368 S witching Theory
By observing t he ASM char t of Fig. 9.6 we see t hat t her e ar e t hr ee st at e boxes which
cont r ibut es t o t hr ee ASM blocks. And we know t hat t he st at e box and condit ional blocks ar e
execut ed by one common clock pulse cor r esponding t o t he st at e defined by st at e box in t he
part icular ASM block.
9.2.4 M O D- 5 C ounte r
Example. We present counter having one input X and one output Z. Counter will have five
states, state O (i.e., S
0
) to state 4 (i.e., S
4
) and it moves to next state only and only if input
X = 1 at the time of arrival of clock pulse. If X = 0 at this time counter does not moves to next
state and maintains its current state. Also when in state S
4
then X = 1 at clock pulse moves
the system to next state S
0
i.e., to initial state so that counting can be restarted from 000. The
output Z produces a pulse when X = 1 at 5 clock pulses or when state changes from S
4
to S
0
.
Initial State
So 000
1
Z
×
×
S
3
011
0
1
S
4 100
1
0
S
2
1
010
×
S
1
0
×
001
×
0
0
Fig. 9.7 ASM char t for MOD-5 Count er.
Not e t hat in t he ASM char t shown in Fig. 9.7 st at e boxes ar e blank and does not specify
any oper at ion. But t he blocks cor r esponding t o t hese st at es cont ains decision boxes which
means t hat only oper at ion t o be done in t hese st at es ar e t o t est t he st at es of input .
Now let us consider t he synt hesis and we wish t o use D flip flop. The 3D-Flip-Flops
t oget her ar e used t o assign t he 3-bit binar y name t o st at es. We know t hat for D flip-flops
excit at ion input D
i
should be same as next st at e var iable Y
i
. By simply obser ving t he assigned
state on ASM char t of Fig. 9.7, we car r y out t he t ask.
Let t he t hr ee out put s of flip-flops ar e Y
2
Y
1
Y
0
i.e., t he t hr ee bit binar y name for st at e.
(1) Fir st finding t he changes in bit Y
0
in ASM char t . When pr esent st at e is 000 or 010
t hen t he next value of Y
0
has t o become 1. Thus
D
0
= Y
0
= X (0, 2) + (5, 6, 7) Σ Σφ
Similar ly for Y
1
and Y
2
.
(2) The next value of Y
1
has t o become 1 only for t he pr esent st at es 001 and 010. So
D
1
= Y
1
= X (1, 2) + (5, 6, 7) Σ Σφ
Algorithmic S tate Machine 369
(3) Similar ly, next value of Y
2
has t o become 1 only for t he pr esent st at e 011. So
D
2
= Y
2
= X (3) + (5, 6, 7) Σ Σφ
(4) Similar ly next value of Z has t o become 1 only and only for pr esent st at e 100. So
Z = X (4) + (5, 6, 7) Σ Σφ
Not e t hat st at e 5, 6, 7 i.e., 101, 110, 111 never occur s and t hat ’s why t hese t hr ee st at es
are writ t en Σφ(5, 6, 7) .
Thus t he synt hesis equat ions can be summar ized as
D
0
= Y
0
= X. (0, 2) + (5, 6, 7) Σ Σφ
D
1
= Y
1
= X. (1, 2) + (5, 6, 7) Σ Σφ
D
2
= Y
2
= X. (3) + (5, 6, 7) Σ Σφ
and Z = X. (4) + (5, 6, 7) Σ Σφ
Her e input X is ANDed wit h all t he expr essions for t he excit at ions. In t his syst em input
X is used t o enable t he count er. Thus excit at ion equat ions can be given as–
D
0
= Y
0
=
XY Y Y XY Y Y
2 1 0 2 1 0
+
D
1
= Y
1
=
XY Y Y Y Y Y X
2 1 0 2 1 0
+
D
2
= Y
2
= XY Y Y
2 1 0
and Z = XY Y Y
2 1 0
Wher e st at e S
0
is represent ed by
Y Y Y
2 1 0
as it s name assigned was 000. In fact if value
of st at e value is 0 t hen it is r epr esent ed by
Y
i
and if it is 1 t hen use Y
i
.
Similar ly t he st at es ar e r epr esent ed for S
1
t o S
4
.
9.3.5 Se q ue nc e De te c tor
Exampl e . We now consider a sequence detector to detect “0101” and allowing the
overlapping. This example is chosen to illustrate the similarity between state diagram. If we
have already drawn a state diagram then drawing the AS M chart is a very easy job. The state
diagram to detect 0101 is shown in Fig. 9.8.
1/1
0/0
1/0
S
0
S
1 1/0
1/0
0/0
0/0
S
2
0/0
S
3
Fig. 9.8 St at e Diagr am of 0101 sequence Det ect or wit h over lapping.
370 S witching Theory
Number Mar ked wit h segment s connect ing t wo st at es ar e value of input and out put and
wr it t en as Input /out put . If it s 1/0 means Input -1 t hen Out put is 0, while in t his st at e.
It is evident fr om t he st at e diagr am t hat t her e ar e four st at es S
0
, S
1
, S
2
, S
3
. So 2-bit
binar y code can be associat ed t o t hese st at es t o ident ify t he par t icular st at e. Thus we use t wo
D flip-flops t o assign binar y number Y
1
Y
0
t o t he st at es. As ear lier indicat ed use of D Flip Flop
makes t he excit at ion t able same as t r ansit ion t able because for D flip-flop D
i
= Y
i
. In fact we
car r y out t hese exer cise aft er dr awing ASM char t , but her e we did it ear lier t o r eflect t he
similar it y bet ween ASM char t and st at e gr aph as major differ ence bet ween t he t wo is indicat ion
of t iming r elat ion in t he dr awing. Below is t he ASM char t i.e., Fig. 9.9 for t he pr oblem.
Z
0
11 S
3
1
1
00
S
0
S
1
0
1
S
2
01
×
×
×
0
1
x
10
0
Fig. 9.9 ASM char t for 0101 Sequence Det ect or.
Not e t hat , as in ear lier examples, her e also X is input t hr ough which t he sequence is
applied t o t he syst em. Z is out put which goes high when t he int ended sequence is det ect ed.
Not e t he similar it y bet ween t he st at e diagr am and ASM char t . A close inspect ion of t wo
gr aphs, shows t hat for ever y st at e of st at e diagr am, t here exist one ASM blocks and t here
is one st at e box per ASM block in the ASM char t . Thus t here are four ASM blocks in Fig.
9.9 each of which cont ains a decision box and last one cont ains a condit ional box also in
Algorithmic S tate Machine 371
addit ion t o st at e box. We again asser t t he fact t hat all t he oper at ions owing t o an ASM block
ar e t o be complet ed in t he same clock per iod. We now consider synt hesis t o find out t he
equat ions for excit at ions.
Her e also we use obser vat ion (as was done in example 2) t o det er mine t hat when next
st at e var iables Y
0
and Y
1
become 1. Thus
D
0
= Y
0
= X (0, 2) Σ
∴ D
0
= Y
0
=
XY Y X Y Y
1 0 1 0
+
as t he S
0
st at e = 00 =
Y Y
1 0
S
2
st at e = 010 =
Y Y
1 0
If input X = 0 make next st at e t o comes t hen input = X and if input X = 1 causes t he
next st at e t hen input = X.
In equat ion for D
0
,
XY Y
1 1
shows t hat next st at e var iable Y
0
= 1 when X = 0 and pr esent
st at e is S
0
(i.e., 00). Similar ly
XY Y
1 0
means next st at e var iable Y
0
= 1 if t he input X = 0 while
in st at e S
2
(i.e., 10). See the ASM char t t o ver ify t he st at ement s.
Similarly D
1
= Y
1
=
XY Y XY Y
1 0 1 0
+
and Z = XY
1
Y
0
9.3 TIM ING C O NSIDERATIO NS
The t iming of all t he r egist er s and flip-flops is cont r olled by a mast er clock gener at or.
The clock pulses ar e equally applied t o t he element s (i.e., r egist er s, flip-flops) of bot h dat a
pr ocessing and cont r ol subsyst ems. The input signals ar e synchr onized wit h t he clock as
nor mally t hey happen t o be t he out put of some ot her cir cuit ut ilizing t he same clock. Thus
t he input s change t he st at e dur ing an edge t r ansit ion of clock. In t he similar way, t he out put s,
t hat ar e a funct ion of pr esent st at e and synchr onous input s, will also be synchr onous.
We r e-inser t t hat major differ ence bet ween a convent ional flow chart and ASM char t is
in defining and int er pr et ing t he t iming r elat ion among t he var ious oper at ions. Let us consider
the ASM char t shown in Fig. 9.4. If it would be a convent ional flow char t , t hen t he list ed
oper at ions wit hin t he st at e, decision and condit ional boxes ar e execut ed sequent ially i.e., one
aft er anot her in t ime sequence. Alt er nat ely saying, at one clock pulse only one of t he boxes
will be execut ed, wher e t he box may be a st at e box or a decision box or a condit ional box.
Thus a t ot al denial of t iming r elat ion among t he var ious act ivit ies. In cont r ast t o it , an ent ir e
ASM block is t r eat ed as one unit . All t he act ivit ies specified wit hin t he block must happen
in synchr onism wit h t he t r ansit ion of posit ive edge of t he clock, while t he syst em changes
fr om cur r ent st at e t o next st at e. Her e it is assumed t hat all t he flip-flops ar e posit ive edge
t r igger ed. For illust r at ion pur pose consider t he ASM char t shown in Fig. 9.4 and Fig. 9.10
shows he t r ansit ion of cont r ol logic bet ween t he st at es.
Next State
(S or S )
1 2
Present State
(S )
0
Positive transition
of Pulse
Clock
Fig. 9.10 Tr ansit ion bet ween St at es.
372 S witching Theory
In or der t o under st and t he st at e t r ansit ion at t he posit ive edge of clock r efer t he
Fig. 9.4 and 9.10 simult aneously along wit h t he following discussion.
The ar r ival of fir st posit ive t r ansit ion of clock, t r ansfer s t he cont r ol subsyst em int o S
0
st at e. The act ivit ies list ed in var ious boxes of ASM block, cor r esponding t o S
0
st at e can now
be execut ed, as soon as t he posit ive edge of second clock pulse ar r ives. At t he same t ime
depending upon values of input s X and Y t he cont r ol is t r ansfer r ed t o next st at e which may
be eit her st at e S
1
or St at e 2. Refer r ing t o t he ASM block indicat ed by dashed line in Fig. 9.4
we can list out oper at ion t hat occur simult aneously when t he posit ive edge of second clock
pulse appear s. They ar e–
Recall t hat syst em is S
0
st at e befor e second clock pulse
(1) Regist er R
1
is clear ed.
(2) If input X is 1, t he out put signal VALID is gener at ed and t he cont r ol ent er s in S
2
st at e.
(3) If input X is 0, t hen t he cont r ol t est s t he input Y.
(4) If input Y is 0 r egist er R
3
is set t o one. If input Y is 1 r egist er R
2
is clear ed. In
eit her t he case next st at e will be S
1
st at e.
Obser ve t he ASM char t closely (in Fig. 9.4), and we find t hat next st at e is decided by t he
st at us of input X only. If X = 1 t hen next is S
2
st at e and when X = 0 t hen weat her input
Y = 0 or 1 t he next st at e will always be S
1
. Also not e t hat t he oper at ion in t he dat a pr ocessing
subsect and change in st at e of cont r ol subsyst em occur at t he same t ime, dur ing t he posit ive
t r ansit ion of same clock pulse. We now consider a design example t o demonst r at e t iming
relat ion bet ween t he component s of ASM chart .
Example 9.4. Design a digital system having one 4-bit binary counter ‘C’ whose internal
bits are labelled C
4
C
3
C
2
C
1
with C
4
MS B and C
1
as LS B. It has two flip-flops named ‘X’ and
‘Y’. A start signal incrementing the counter ‘C’ by 1 on arrival of next clock pulse and continues
to increment until the operation stops. Given that the counter bits C
3
and C
4
determines the
sequence of operation. The system must satisfy following–
(1) Initiate the operation when start signals = 1 by clearing counter ‘C’ and flip-flop “Y”,
i.e., C = 0000 and Y = 0.
(2) If counter bit C
3
= 0, it causes E to cleared to 0 i.e E = 0 and the operation proceeds.
(3) If counter bit C
3
= 1, E is set to 1 i.e. E = 1 and
(a) if C
4
= 0, count proceeds.
(b) if C
4
= 1, F is set to 1 i.e. F = 1 on next clock pulse and system stops counting.
Solution. ASM char t for t he given pr oblem is shown in Fig. 9.11. A close inspect ion
r eveals t hat
When, no oper at ion, syst em is in init ial st at e S
0
, and keep wait ing for st ar t signals ‘S’.
When S = 1, count er C = 0000 and Y = 0 and simult aneously cont r ol goes t o S
1
st at e.
It means clear ing of count er ‘C’ and flip-flop ‘Y’ occur s dur ing S
0
st at e.
The count er is incr ement ed by 1 dur ing st at e S
1
, on t he ar r ival of ever y clock pulse.
Dur ing each clock pulse simult aneously wit h incr ement dur ing same t r ansit ion of clock, one
of t he t hr ee possibilit y is t est ed t o det er mine t he next st at e:
(1) Eit her X is clear ed and cont r ol st ays at S
1
(C
3
= 0).
Algorithmic S tate Machine 373
or
(2) X is set (X = 1) and cont r ol maint ains S
1
st at e (A
4
A
3
= 10).
or
(3) X is set and cont r ol advanced t o st at e S
2
(A
4
, A
3
= 11).
When in S
2
st at e flip-flop ‘Y’ is set t o 1 and cont r ol move back t o it s init ial st at e S
0
. The
ASM char t consist of t hr ee blocks, one ext er nal input S, and t wo st at us input s S
4
and S
3
.
× 0 ←
S
Inital State
S
0
0
1
× 1 ←
1
0
C
3
0
S
2
1
C
4
C C+1 ←
Y 1 ←
Y 0 ←
S
1
C 0 ←
Fig. 9.11 ASM char t for example 9.4.
Example 9.5. Design a digital system for weight computation in a given binary word.
Solution. The weight of a binar y number is defined as t he number of 1’s cont ained in
binar y r epr esent at ion. To solve t he pr oblem let t he digit al syst em have
1. R – A r egist er wher e binar y wor k is st or ed.
2. W – A r egist er t hat count s number of 1’s in binar y number st or ed in R.
3. F – A flip-flop.
The oper at ion of t he syst em is t o shift a single bit of R int o F. Then check t he out put
of t he F. If it is 1 incr ement count in W by 1. If it is O no incr ement in W. The moment all
t he bit s ar e shift ed and t est ed oper at ion st ops and W cont ains t he weight of t he given wor d.
374 S witching Theory
The ASM char t for t his pr oblem is shown in Fig. 9.12. Not e t hat t he syst em have 3 input s
S, Z and F. Z is used t o sense weat her all t he bit s in r egist er R ar e O or not . Z = 1 indicat es
t hat r egist er R cont ains all zer os, and t he oper at ion must st op.
Init ially machine is in st at e S
0
and r emains is st at e S
0
unt il t he swit ch S (i.e., st ar t
signal) is made 1. If S
0
= 1 t hen in S
0
st at e, t he clock pulse causes. Input wor d t o be loaded
int o R, count er W t o have all 1’s and machine t o t r ansfer r ed t o st at e S
1
.
In st at e S
1
a clock pulse causes t wo wor ks simult aneously. Fir st it incr ement s W by 1.
If W is incr ement ed for t he fir st t ime, t hen t he count in W becomes all 0’s as init ially it was
all 1’s second it t est s Z. If Z = 0 machine goes t o st at e S
2
.

If Z = 1 machine goes t o st at e S
0
and count in W is weight of t he binar y wor d.
S
0
00
Initial State
Start
O
1
1
S
1
01
R Input ←
W All 1’s ←
W W + 1 ←
Z
Shift R into F
S
2
10
S
3
11
F
1
0
Fig. 9.12 ASM char t for weight comput at ion.
Algorithmic S tate Machine 375
In st at e S
2
a bit of r egist er R is shift er int o flip-flop F, and machine goes t o st at e S
3
.
In st at e S
3
, shift ed bit in F is t est ed. If f F = 0 t he machine goes t o st at e S
2
t o shift next
bit int o F. If F = 1 it goes t o st at e S
1
t o increment t he count in W.
9.4 DATA PRO C ESSING UNIT
Once t he ASM char t is pr epar ed, t he syst em (or machine) can be designed. The design
is split t ed in t wo par t s:
(a) Dat a Pr ocessing Unit
(b) Cont r ol Unit .
The dat a pr ocessing unit cont ains t he element t hat per for ms t he oper at ions like incr ement
t he count , shift a bit et c.
The cent r al unit is t he subsyst em t hat is r esponsible t o move t he machine fr om one st at e
t o anot her, accor ding t o t he condit ions specified by ASM char t .
In t his sect ion we ar e concer ned wit h t he design of dat a pr ocessing unit only.
Example 9.6. Design data processing unit for binary weight computation, discussed in
Examples 9.5.
Solution: Pr oposed dat a pr ocessing unit is shown in Fig. 9.13. The cont r ol sub-syst em
has 3 input s S, Z, F as discussed in Example 9.5. It has four cont r ol signals C
0
, C
1
, C
2
, C
3
cor r esponding t o st at es S
0
, S
1
, S
2
, S
3
r espect ively (r efer t o ASM char t shown in Fig. 9.12).
We advise t he r eader s t o go t hr ough Example 9.5 again.
Next shown in figur e is a shift r egist er R. Ser ial input ‘0’ is a dat a input . Each t ime dat a
in R is shift ed left t his input inser t s a 0 at LSB. A HIGH on SHIFT LEFT input shift s t he
dat a pr esent in R t o left by 1 bit and loads a ser ial 0 at LSB. A HIGH on LOAD INPUT DATA
loads t he INPUT DATA int o R. This is t he binar y wor d whose weight is t o be calculat ed. This
wor d is loaded as par allel dat a int o R.
A NOR gat e is used t o det er mine weat her all t he bit s of R ar e 0 or not . All t he bit s of
R ar e br ought t o t he input of NOR. As soon as all t he bit s or R become O out put of NOR goes
HIGH. If any of t he bit of R is 1 out put of NOR r emains LOW. Out put of NOR is feeded as
input Z t o cont r ols, wher e it is checked for 0 or 1.
A flip-flop F is connect ed a MSB of R. This flip-flop is used t o collect each shift ed bit fr om
r egist er R. Ever y t ime R r eceives shift left command, it s MSB is shift ed out and is r eceived
in flip-flop F. The out put of flip-flop is feeded t o cont r ols as input F, wher e it is checked for
1 or 0.
Last in figur e is count er W which is yet anot her r egist er act ing as count er. A HIGH on
LOAD INPUT loads all 1’s into W. A HIGH INCREMENT increment s t he count in W by 1.
Init ially t he syst em is in st at e S
0
(refer ASM char t of Fig. 9.12 along wit h Fig. 9.13). As
soon as START = 1, C
0
is act ivat ed. This causes LOAD INPUT DATA signals of bot h R and
W t o go HIGH. Thus binar y wor k is loaded int o R and init ial count is loaded int o W. At t he
same t ime t he machine moves t o st at e S
1
.
In st at e S
1
signal C
1
is act ivat ed. This causes INCREMENT signal of W t o go HIGH and
consequent ly t he count in W is incr ement ed by 1. When it is incr ement ed for t he fir st t ime.
All 1’s become all 0’s. At t he same t ime input Z is t est ed by cont r ols. If Z = 1 cont r ol goes
back t o st at e S
0
. If Z = 0 cont r ol goes t o st at e S
2
.
376 S witching Theory
W
‘CP’-CLOCK PULSE
CP
INPUT DATA
LOAD INPUT DATA
SHIFT LEFT
SERIAL INPUT ‘0’
SHIFT REGISTER ‘R’
F
Q D
Flip
Flop
F
CP
Z = 1 if R = 0
F
Z
S
C
0
C
1
C
2
C
3
START
INCREMENT
LOAD INPUT DATA
COUNTER W
CP
Input all 1’s
CONTROL
Fig. 9.13 Dat a pr ocessing unit for Binar y weight comput at ion.
In st at e S
2
t he signal C
2
is act ivat ed. The C
2
causes SHIFT LEFT of R t o go HIGH and
enables t he flip-flop F. Thus t he cont ent of R shift ed t o left by 1-bit . Hence MSB of R is shift ed
out and is collect ed by F and at t he same t ime a 0 is inser t ed at t he LSB t hr ough ser ial input .
Now t he machine moves on t o st at e S
3
.
In st at e S
3
t he out put of F is t est ed by cont r ol subsyst em. If F = 1 machine should go
t o st at e S
1
i.e., C
1
t o be act ivat ed next . If F = 0 machine should go t o st at e S
2
i.e., C
2
t o be
next . Since all t hese act ivit ies ar e int er nal t o cont r ol subsyst em, C
3
is not connect ed t o any
element of dat a pr ocessing unit . In fact C
3
is used t o act ivat e t he signals C
1
or C
2
and is
pr ocessed int er nally by cont r ol unit .
9.5 C O NTRO L DESIG N
As ear lier st at ed t he job of t he cont r ol subsyst em is t o move t he machine fr om one st at e
t o ot her st at e accor ding t o input s given t o it . In gener al var iables defined by t he “decision
boxes” in an ASM char t ar e t r eat ed as input s t o t he cont r ol subsyst em.
Algorithmic S tate Machine 377
Ther e ar e many met hods t o obt ain a cont r ol subsyst em accor ding t o t he ASM char t s.
Her e we consider only t wo met hods:
(i) Mult iplexer Cont r ols
(ii) PLA cont r ols.
9.5.1 M ultip le xe r C ontrol
In t his appr oach we use t he mult iplexer s t o r ealize t he cont r ol subsyst em. The number
of mult iplexer s depends upon t he number of st at es in ASM char t . For example if t her e ar e
4-st at es t hen we need 2-bit binar y number t o specify t hese st at es uniquely. So we t ake t wo
mult iplexer s, one for each bit of r epr esent at ion. In gener al, if ‘n’ is number of mult iplexer s
t hen 2
n
> No. of st at es.
The t ype of mult iplexer also depends upon t he number of st at es. If t her e ar e four st at es
in ASM char t t hen t he mult iplexer should be a 4 × 1 mult iplexer. Alt er nat ely
Number of MUX input s > No. of st at es
In gener al design t he out put of mult iplexer s denot es t he PRESENT STATE var iable as
t hese out put s r eflect cur r ent st at us of cont r ol unit . The input s t o mult iplexer r epr esent s t he
NEXT STATE var iable. It is because if t hese input s ar e changed out put of mult iplexer s may
change and t hus we say t hat t he st at e is changed.
To being wit h we consider our example of binar y weight comput at ion illust r at ed in
Examples 9.5 and 9.6. We ur ge t he r eader s t o go t hr ough t hese t o examples car efully befor e
pr oceeding fur t her.
Example 9.7. Design t he cont rol syst em for binary weight comput at ion, by using
multiplexers.
Solution. The ASM char t for binar y weight comput at ion is dr awn in Fig. 9.12. Refer r ing
t o t he char t we find t hat t her e ar e 4 st at es. So,
2
n
> 4
or n > 2
So we t ake 2 mult iplexer s (n = 2) MUX 1 and MUX 0. Since t her e ar e 4 st at es we select
4 input mult iplexers i.e., 4 × 1 mult iplexer s.
Aft er select ing t he mult iplexer s next st ep is t o dr aw st at e t able, as shown in Fig.
9.14(a). The fir st 3 columns of t he t ables shows pr esent st at es, next st at e and t he input s
t hat causes t he next st at e. Last column of t he t able is mult iplexer input . As ear lier st at ed
mult iplexer input s ar e next st at e var iables. Thus ent r ies in t his columns ar e made by
making obser vat ions on input s and next st at e. For example, if pr esent st at e is S
0
i.e.,
mult iplexer out put Y
1
= 0 and Y
0
= 0, t hen st at us of swit ch S decides t he next st at e. If
S = 0 t he next st at e is S
0
i.e., Y
1
= 0 and Y
0
= 0. If S = 1 t he next st at e is S
1
i.e., Y
1
= 0
and Y
0
= 1. Hence when S = 0, Y
0
= 0 and when S = 1, Y = 1, Y
0
= 0 so we say Y
0
= S.
Since Y
1
= 0 always t he first ent r y in MUX input s column is 0 S. Consequent ly input I
0
of
MUX 1 must be connect ed t o 0 and input I
0
of MUX 0 must be connect ed t o S. The same
is shown in Fig. 9.14(b). Reader s ar e advised t o ver ify all t he r ows of st at e t able in similar
way.
378 S witching Theory
Present S tate Inputs Next S tate MUX Inputs
Y
1
Y
0
S Z F Y
1
Y
0
D
1
= Y
1
D
0
= Y
0
MUX 1 MUX 0
S
0
0 0 0 × × 0 0 0 S
1 × × 0 1
S
1
× 1 × 0 0
0 1 × 0 × 1 0
Z
0
S
2
1 0 × × × 1 1 1 1
S
3
1 1 × × 0 1 0
× × 1 0 1 F F
(a) State Table
2 to 4
Line
Decoder
C
0
C
1
C
2
C
3
D
0
Y
0
CP
D
1
Y
1
CP
MUX 1
I
0
I
1
I
2
I
3
0
Z
1
F
I
0
I
1
I
2
I
3
S
0
1
F
MUX 0
S
1
S
0
(b) Logic Diagram
Fig. 9.14 Cont rol Subsyst em for binary Weight comput at ion.
Fig. 9.14 (b) shows t he complet e cont r ol design for weight comput at ion. The out put s of
mult iplexer s ar e feeded t o a 0 flip-flops, whose out put s Y
1
and Y
0
ar e br ought back t o select
lines S
0
and S
1
of mult iplexer s. Y
1
and Y
0
ar e decoded fur t her by using 2 t o 4 line decoder
t o gener at e t he cont r ol signals C
0
, C
1
, C
2
, C
3
cor r esponding t o st at es S
0
, S
1
, S
2
, S
3
r espect ively.
To under st and t he oper at ion let us consider t hat cont r ol is in sat e S
0
so Y
1
= 0 and
Y
0
= 0 i.e., S
1
= S
0
= 0. Sine S
1
, S
0
= 0 0, input I
0
of bot h t he mult iplexer s ar e select ed. As
long as S = 0, both Y
1
= Y
0
= 0 and machine r emains is st at e S
0
. As soon as S = 1 out put
Algorithmic S tate Machine 379
of MUX becomes 1 and consequent ly Y
1
= 0 and S
0
= 1. Thus signal C
1
is act ivat ed and select
input s become S
1
= 0 and S
0
= 1. Hence input s I
1
of bot h mult iplexer s select ed. Not e t hat
by act ivat ion of C
1
st at e S
1
has ar r ived. At t he input I
1
of MUX 1,
Z
is connect ed whose value
is r esponsible t o make Y
1
= 0, Y
0
= 0 or Y
1
= 1, Y
0
= 0. Thus input Z is t est ed in st at e 1,
which was t o be done in S
1
according t o t he ASM char t shown in Fig. 9.12. Like wise t he
complet e oper at ion can be ver ified.
9.5.2 PLA C ontrol
Use of PLA t o r ealize, cont r ol subsyst em makes t he syst em mor e compact and efficient .
PLAs have int ernal AND-OR array i.e., t he out put s of PLA r epr esent sum of pr oduct . Thus,
over all st r at egy is t o pr epar e on SOP equat ion for each bit of st at e r epr esent at ion. For
example, if 4-st at es ar e t her e we need t wo bit s of r epr esent at ion. Thus we need t wo SOP
equat ions. Aft er get t ing t he SOP equat ions next st ep is t o pr epar e PLA pr ogr am t able. Such
a t able is a input -out put t able accor ding t o which PLAs ar e pr ogr ammed.
Example 9.8. Design a control system for binary weight computation, by using the PLA.
Solution. We advise t he r eader s t o go t hough t he ASM char t given in Fig. 9.12 and
mult iplexer cont r ol shown in Fig. 9.14.
We now obt ain t wo SOP equat ion for next st at e var iables Y
1
and Y
0
accor ding t o st at e
t able given in Fig. 9.14(a). Let C
0
, C
1
, C
2
, C
3
ar e signals cor r esponding t o st at es S
0
, S
1
, S
2
,
S
3
Y
1
= Y Y Z Y Y Y Y F
1 0 1 0 1 0
+ +
or Y
1
= C Z C C F
1 2 3
+ +
as (Y
1
Y
0
= 0 1 means C
1
and Y
1
Y
0
= 11 means C
3
)
Similarly Y
0
= Y Y S Y Y Y Y F
1 0 1 0 1 0
+ +
= C
0
S + C
2
+ C
3
F
The PLA pr ogr am t able and PLA cont r ol block is shown in Fig. 9.15. Let us examine
t he PLA pr ogr am t able. Not e t hat Y
1
Y
0
in t he input side of t able r epr esent s t he pr esent
st at e and Y
1
Y
0
in t he out put side r epr esent s t he next st at e. Fur t her all ent r ies at t he
input side is made for pr oduct t er ms and at t he out put side ent r ies ar e r esult s of sum of
pr oduct s.
Fir st four r ows in t he pr ogr a m t a ble a r e simply showing t he va lues of Y
1
Y
0
and
cor r esponding st a t e t o be excit ed. For exa mple if pr esent st a t e is Y
1
= 0 and Y
0
= 0, t hen
if it is st a t e S
0
a nd signa l C
0
is a ct iva t ed. This is shown in fir st r ow. At t he out put side
Y
1
Y
0
shows next st a t e. Now obser ve t he t hir d r ow, which shows t ha t ma chine is in st a t e
S
2
so C
2
is act ivat ed. But accor ding t o t he ASM char t shown in Fig. 9.12, if t he machine
is in st a t e S
2
it goes t o st a t e S
3
wit hout t est ing a ny input . Hence a t t he out put side of
t a ble we ma r ked Y
1
= 1 and Y
0
= 1. Not e t ha t Y
1
and Y
0
on t he out put side a r e filled
up accor ding t o t he t wo SOP equat ions obt ained in t he beginning. In fact t he fir st four
r ows a r e used t o show wha t will be t he cont r ol signa l t o be a ct iva t ed when ma chine is
in a st a t e.
380 S witching Theory
Product Inputs Outputs
Terms Y
1
Y
0
S Z F Y
1
Y
0
C
0
C
1
C
2
C
3
C
0
=
Y Y
1 0
0 0 1 0 0 0
C
1
=
Y Y
1 0
0 1 0 1 0 0
C
2
= Y Y
1 0
1 0 1 1 0 0 1 0
C
3
= Y
1
Y
0
1 1 0 0 0 1
C
1
Z =
Y Y Z
1 0
0 1 0 1 0 0 1 0 0
C
3
F = Y
1
Y
0
F
1 1 0 1 0 0 0 0 1
C
0
S =
Y Y S
1 0
0 0 1 0 1 1 0 0 0
C
3
F = Y
1
Y
0
F 1 1 1 0 1 0 0 0 1
(a ) PLA Program Table
Q
D
1
CP
Q D
0
CP
Y = D
0 0
Y
0
Y
1
Y = D
1 1
PLA
F
Z
S
C
3
C
2
C
1
C
0
(b) Logic Diagram
Fig. 9.15 Cont r ol subsyst em for weight comput at ion using PLA.
Algorithmic S tate Machine 381
The r est of t he four r ows in PLA pr ogr am t able shows t he input t o be t est ed when machine
is in a st at e and what should be t he next st at e if t est ing is t r ue. Consider t he 7t h r ow having
pr oduct t er ms ent r y C
0
S =
Y Y S
1 0
. This t est s t he input S when machine is in st at e S
0
. At t he
input side Y
1
= Y
0
= 0 t o show st at e S
0
and ent r y S = 1 is st at us of input S . At t he out put side
in t his r ow C
0
= 1 as machine is in st at e S
0
. Next Y
1
= 0 and Y
0
= 1 at t he out put side indicat es
t hat since input S = 1, t he machine must go t o st at e S
1
at next clock pulse.
9.6 EXERC ISES
1. Draw the ASM char t for a binar y mult iplier.
2. A binar y st r eam is ar r iving ser ially. St r eam is such t hat LSB ar r ives fir st and MSB
ar r ives last syst em r equir ement is such t hat t he syst em must out put t he 2’s
complement of each incoming bit ser ially. Dr aw the ASM char t and design cont r ol
subsyst em and dat a pr ocessing subsyst em for t his syst em.
3. Dr aw the ASM char t t o compar e t wo 4-bit binar y dat as.
4. Draw the ASM char t for 1-bit full adder.
5. Draw the ASM char t for 2-bit binar y count er having one enable input .
6. Design a synchr onous st at e machine t o gener at e following sequence of st at es.
7
3
5
1
7. Draw the ASM char t and st at e diagr am for t he cir cuit shown.
Input
Clock
Q
Q
D
Output
Q
Q
D
8. Draw the ASM char t and st at e diagr am for decade count er.
9. Draw the ASM char t and st at e diagr am t o conver t t wo digit hexadecimal number
int o packed BCD number.
10. Draw the ASM char t and st at e diagr am for 1 bit full subt r act or.
382 S witching Theory
10
CHAPTER
382
SWITCHING ELEMENTS AND
IMPLEMENTATION OF LOGIC GATES
10.0 INTRO DUC TIO N
In ear lier chapt er s we have st udied t he basic logic gat es and seen how t hey can be
r ealized using swit ches in ON/OFF fashion (or TRUE/FALSE). The semiconduct or devices
can be used t o r eplace t hese swit ches and can r ealize t hese logic funct ions. A cir cuit employing
semiconduct or devices t o r ealized logic funct ions is called as di gi t al c i rc ui t . Since
semiconduct or devices ar e used t o r eplace t he swit ch, t hese devices and t heir swit ching
char act er ist ics ar e discussed fir st in t his chapt er. Infact using semiconduct or devices offer s
sever al advant ages, t hat will be appar ent t hr oughout t his chapt er.
Advent of semiconduct or IC t echnology in lat e 1950’s and ear ly 1960’s made it possible
t o fabr iat e lar ge number of cir cuit component s on a small piece of semiconduct or, whose ar ea
is few mm
2
. Thus a la r ge number of cir cuit s could be int egr a t ed on sma ll piece of
semiconduct or. This small piece of semiconduct or is called as CHIP and a chip wit h cir cuit s
fabr icat ed on it is chrit ened as Integrated Ci rcui t or IC in shor t . Var ious t ypes of digit al
cir cuit s ar e available in for m of ICs. In par t icular, advent of MOS t echnology made mor e
number of component s and logic cir cuit s on one IC. Thus giving r ise t o ver y lar ge scale
int egr at ion which r esult ed in high capacit y memor y devices, micr opr ocessor and many ot her
complex cir cuit s available on a small chip.
10.1 FUNDAM ENTALS O F SEM IC O NDUC TORS AND SEM IC O NDUC TO R SWITC HING
DEVIC ES
10.1.1 Se m ic ond uc tors
By t he idea of elect r ical pr oper t ies of solids, we know t hat mat er ials ar e br oadly
cat egor ized as conduct or, semi conduct or, and insulat or, on t he basis of t heir conduct ivit y.
SEMI CONDUCTORS ar e t hose which have elect r ical conduct ivit y int er mediat e t o t hat of an
conduct or and insulat or. In fact in a semiconduct or t he filled ener gy band, called valance
band and t he unfilled ener gy band, called conduct ion band ar e separ at ed by a small ener gy
gap, called band gap ener gy E
G
.
By pr oviding ener gy fr om an ext er nal sour ce, t he char ge car r ier s at filled band can be
r aised t o conduct ion band. Thus t he mat er ials can st ar t conduct ion.
Ther e ar e numer ous element al and compound semiconduct or s ar e available out of
which silicon ad Ger manium ar e t wo common element al semiconduct or s. The silicon is used
most ly because ener gy gap of silicon is a bit lar ger t han t he ger manium t hus pr oviding a
good oper at ional mechanism, as we will see lat er.
Switching Elements and Implementation of Logic Gates 383
Fig. 10.1 Ener gy Band Diagr am for semiconduct or s
Bot h t he silicon and germanium at oms have 4 elect rons in t heir out er shell, which forms
covalent bands wit h neighbouring at oms in a semiconduct or mat erial. This is shown in Fig.
10.2. By providing energy from an elect rical source t hese covalent bands can be brocken and
free charge carriers are available for conduct ion. Many of t hese covalent s bonds are broken
even at room t emperat ure so at room t emperat ure semiconduct ors (short hand SCs) can behave
some what like conduct ors. A semiconduct or in it s ext reme pure form is called as intrinsic
semiconductor. At room t emperat ure conduct ivit y of int rinsic semiconduct ors are poor. Thus
t o increase t he no. of free charge carriers (or conduct ivit y) it usual t o add some impurit y t o
int rinsic semiconduct ors. This dramat ically increases t he conduct ivit y of semiconduct ors, and
make it suit able for various applicat ions. A semiconduct or wit h impurit y added t o it is called
as extrinsic semiconductor. The process of adding impurit ies t o semiconduct ors is called
doping. These ext rinsic semiconduct ors are also called as doped semiconductors.
Fi g. 10.2 For mat ion of Covalent Bonds in Semiconduct or.
In a semiconduct or whenever a covalent bond is br oken t he elect r on get s fr ee fr om it s
par ent at om and leaves a vacancy, t hus a +ve char ge equal t o t he magnit ude of elect r on
char ge is left wit h t he par ent at om. Thus t he at om is ionized. An elect r on fr om neighbour ing
at om can fill t his vacancy, but cr eat es a vacancy t her e, if t his pr ocess r epeat s t his vacancy
can be moved fr om one place t o anot her and t hus giving a mechanism of conduct ion. This
vacancy is called hole which has an equal but opposit e char ge t o t hat of an elect r on. In a
semiconduct or conduct or bot h holes and elect r ons pr ovide t he conduct ion mechanism. Infact
fr ee elect r ons t r avels in conduct ion band wher e hole movement is due t o t he movement of
elect r ons in valence band. Bot h t he char ge car r ier s t r avel in a dir ect ion opposit e t o each
ot her but const it ut e cur r ent in same dir ect ion.
In a semiconduct or bot h elect r ons and holes moves r andomly t hr ough t he semiconduct or
cr yst al dur ing which an elect r on can fill a hole causing fr ee elect r ons and holes t o disappear.
384 S witching Theory
This pr ocess is called Recombination. In a semiconduct or t he rat e of charge carrier generat ion
(gener at ion of bot h elect r ons and holes) is equal t o t he r at e of r ecombinat ion and r emains
const ant in t ime.
In an int r insic semiconduct or t he number of fr ee elect r on (n) and fr ee holes (p) is same
i.e.,
n = p = n
i
...(10.1)
where n
i
is int r insic concent r at ion of holes or elect r ons in int r insic semiconduct or. The n
i
can be appr oximat ed as
n
i
2
= BT per cm
3 E K T 3 G B
e
− / .
...(10.2)
wher e B = mat er ial const ant = 5.4 × 10
31
for sillicon
T = Temper at ur e in Kelvin
E
G
= Band gap ener gy of SC = 1.12 eV for silicon
K
B
= Bolt zman const ant = 1.38 × 10
–23
joules/kelvin
= 8.62 × 10
–5
eV/K
By using eqn (10.2) for sillicon we get t hat at r oom t emper at ur e i.e., at 27°C we get
appr oximat ely 1.51 × 10
10
fr ee car r ier /cm
3
. A silicon cr yst al has 5 × 10
23
at oms/cm
3
. So
n
i
= 1.51 × 10
10
shows t hat at r oom t emper at ur e only one of ever y billion at om is ionized.
In a semiconduct or r ecombinat ion causes a pair of fr ee char ge car r ier s, called elect r on
hole pair (EHP) t o disappear and br eaking of a covalent gives an EHP. Also br eaking of a
covalent bond ionizes an at om by fr eeing an elect r on, for t his r eason gener at ion of fr ee
char ge car r ier s is called i oni zati on process.
In a semiconduct or movement of char ge car r ier can be obt ained by t wo mechanism
di ffusi on and dri ft. If t her e is unifor m concent r at ion of char ge car r ier s t hr oughout t he
cr yst al of a semiconduct or t her e is not net flow of char ges i.e., no cur r ent . If in one por t ion
concent r at ion is high and in anot her por t ion concent r at ion is low t hen t he char ge car r ier s
will diffuse t o low concent r at ion r egion and t hus const it ut ing di ffusi on current I
D
. If an
elect r ic field is applied t o semiconduct or s fr ee elect r ons and holes ar e acceler at ed and
acquir es a velocit y called dri ft veloci ty and is given as
V
drift
= µE ...(10.3)
wher e µ = mobilit y of char ge car r ier s in cm
2
/V.sec
E = applied elect r ic field in V/Cm
V
drift
= dr ift velocit y in cm/sec
Not e t hat mobilit y of a hole is lower t han t hat of an elect r on.
The elect r ic cur r ent caused by dr ift velocit y is called as dri ft current.
As ear lier st at ed, t o incr ease t he conduct ivit y of a semiconduct or doping is done. Ther e ar e
t wo t ype of doping is used t o incr ease fr ee char ge car r ier s; depending upon weat her we want
t o incr ease no. of holes or no. of elect r ons. In a doped semiconduct or if impur it y incr eases
no. of fr ee-elect r ons it is called n-type semiconduct or and in which case elect r ons becomes
major it y car r ier and holes become minor it y car r ier. If impur it y incr eases no. of fr ee holes
it is called p-type semiconduct or. To obt ain n-t ype semiconduct or a pent avalent impur it y
(e.g., ant imony or phosphor ous wit h 5 elect r ons in out er or bit s) is int r oduced. Out of 5
valence elect r ons of impur it y at oms four elect r ons for ms covalent bonds wit h sur r ounding
semiconduct or at oms and one elect ron remains-free. Thus t he free elect ron can be donat ed
Switching Elements and Implementation of Logic Gates 385
for current conduct ion. For t his reason such impurit y at oms are called donor atoms. Similarly
int roducing a t rivalent impurit y (e.g., boron or medium) gives a p-t ype semiconduct or in which
holes are majorit y carriers. In t his case only t hree elect ron exist s in out er orbit s which form
covalent bonds wit h t hree neighbouring at oms. But t his impurit y is having a vacant posit ion
i.e., hole which is fr ee and can not be used t o for m four t h covalent bond in lat t ice st r uct ur e.
Thus a fr ee hole is cr eat ed. But t his impur it y can accept an elect r on t o for m four t h covalent
bond causing hole movement . For t his reason t rivalent impurit ies are also called acceptor
i mpuri ti es.
“It should be noted that p-type or n-type semiconductors are electrically natural. The
majority carriers in each type are neutralized by bound cha r ges associated with the impurity
atoms, see Fi g. 10.3.
10.1.2 Se mic ond uc tor Diod e or PN Junc tion
When a PN-junct ion is for med t hen due t o concent r at ion gr adient , t he char ge car r ier s
diffuses on eit her side of t he junct ion. But soon aft er cr ossing t he junct ion t he fr ee char ge
car r ier disappear by r e-combinat ion. This leaves t he ion wit hout neut r alizing car r ier. The
pr ocess of diffusion cont inue unt il a pot ent ial bar r ier against t he flow of char ge car r ier is
for med. This is shown in Fig. 10.3. The PN junct ion in open cir cuit is sold t o be in equilibr ium.
Since t he r ecombinat ion occur immediat ely aft er t he junct ion, t his r egion is out of or
deplet ed of fr ee char ge car r ier and t hus it is called depleti on regi on. It is in t his r egion
t he pot ent ial bar r ier is built up and t he char ge car r ier must over come t his bar r ier t o cr oss
t he junct ion. Symbol of PN junct ion diode is shown in Fig. 10.4.
Fi g. 10.3 A PN J unct ion Diode Under Open-Cir cuit Ter minals
Fi g. 10.4 Symbol of PN J unct ion Diode.
When no ext er nal volt age applied t he inbuilt junct ion volt age V
O
, shown in Fig. 10.3 is
given as
V
O
=
V
N N
T
A D
log
.
e
i
n
2
F
H
G
I
K
J
...(10.4(a))
wher e V
T
=
K T B.
q
= Ther mal volt age ...(10.4(b))
386 S witching Theory
q = elect r onic char ge
N
A
, N
D
= Doping concent r at ion on p-side and n-side r espect ively.
For silicon t he junct ion inbuilt volt age V
O
t ypically var ies bet ween 0.6 t o 0.8 V.
Let us connect a dc supply V
F
t o t he diode such t hat posit ive t er minal of supply is
connect ed t o p-t ype and negat ive is connect ed t o n-t ype as shown in Fig. 10.5. This configurat ion
of t he diode is forward bi asi ng.
Fig. 10.5 Diode in for war d bias
The volt age V
F
is t hus called as t he for war d volt age. As we incr ease t he V
F
t he widt h
of t he deplet ion st ar t r educing. Alt er nat ely, t he pot ent ial bar r ier V
O
r educes as shown in
Fig. 10.6(b).
Depletion Region
V
n-type
o
p-type
( ) a
Depletion Region
V – V n-type
o F
p-type
( ) b
Fig. 10.6 Pot ent ial Bar r ier at PN J unct ion
(a) at equilibr ium (open cir cuit ) (b) At for war d bias
If we incr ease V
F
fur t her, sit uat ion can soon be r eached at which deplet ion r egion widt h
is zer o. And t he moment V
F
> V
O
, t he char ge car r ier s ar e swept acr oss t he junct ion under
t he influence of elect r ic field. Thus cur r ent flows t hr ough t he device in a dir ect ion shown
in Fig. 10.5. The cur r ent flowing t hr ough t he device in t his case is called as for war d cur r ent .
If t he bat t er polar it ies ar e r ever sed i.e., posit ive t er minal is connect ed t o n-t ype and
negat ive t er minal is connect ed t he p-t ype, t hen we get what called reverse biasing. This
is shown in Fig. 10.7. Not e t hat bat t er y is now-labelled V
R
(r ever se volt age), in or der t o
dist inguish it fr om for ward volt age V
F
.
Fig. 10.7 Diode In Rever se Bias
In t his case t he elect r ons of t he n-t ype ar e at t r act ed t owar ds t he posit ive plat e of bat t er y
and holes ar e at t r act ed t owar ds t he negat ive plat e. Consequent ly t he widt h of deplet ion
Switching Elements and Implementation of Logic Gates 387
r egion incr eases. And incr ease, in deplet ion r egion incr eases t he pot ent ial bar r ier acr oss t he
junct ion as shown in Figur e 10.8(b).
Depletion Region
V
n-type
o
p-type
( ) a
V + V n-type
o R
p-type
( ) b
Depletion
Region
Fig. 10.8 Pot ent ial Bar r ier at PN J unct ion
(a) At Equilibr ium (open cir cuit )
(b) At r ever se bias
In t his sit uat ion appar ent ly no cur r ent flows t hr ough t he junct ion. But in r ealit y due
t o t he flow of minor it y car r ier s t her e exist a small r ever se cur r ent called as leakage
current.
10.1.2.1 I–V C ha ra c te ristic s of Diod e s
Fig. 10.9 I–V char act er ist ics of a silicon diode wit h
expanded and compr essed scale.
As shown in figur e t he char act er ist ics is divided in 3 par t s.
1. The for war d biased r egion V>0
2. The r ever se based r egion V<0
3. The br eakdown r egion V<–V
K
Not e t hat scale for I<0 is expanded and t hat for V<0 is compr essed.
Forwa rd Re gion
In t he for war d r egion i – v r elat ionship is appr oximat ed as
I = I
S
V/ V
T
( ) e
η
−1 ...(10.5)
wher e I
S
is a const ant for a diode at a given t emper at ur e.
388 S witching Theory
V
T
is t er mal volt age defined by equat ion 10.4(b).
at t = 27°C or T = 300°K t he t her mal volt age
V
T
≅ 26 mV ...(10.6(a))
η is a par amet er and η = 1 for ger manium and η = 2 for silicon.
The cur r ent I
S
in eqn 10.5 is called as SCALE CURRENT. The name is given because
I
S
is dir ect ly pr opor t ional t o t he cr oss-sect ional ar ea of junct ion. This means doubling t he
junct ion ar ea will double t he I
S
which consequent ly doubles t he diode cur r ent I as shown by
equat ion 10.5, for a given for ward volt age V.
An inspect ion of i – v char act er ist ics r eveals t hat almost no cur r ent flows (i.e., less t han
1% or so) for volt ages V < 0.6 V. For volt ages var ying bet ween 0.6 V t o 0.8V t her e flows an
appr eciable amount of cur r ent . Thus we say t hat 0.6 V is a t hr eshold value of volt age t hat
must be applied for conduct ion. This is called as cut-i n voltage (V
γ
). Thus for silicon diode
cut in volt age is
V
γ
= 0.6 V ...(10.6(b))
Since for a fully conduct ing diode volt age dr op lies in a nar r ow r ange of 0.6 t o 0.8V we
can appr oximat e t