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module ci7402(out0, in0, in1);

output [3:0]out0;
input [3:0]in0, in1;
assign
assign
assign
assign
endmodule

out[0]
out[1]
out[2]
out[3]

=
=
=
=

!(in0[0]
!(in0[1]
!(in0[2]
!(in0[3]

|
|
|
|

in1[0]);
in1[1]);
in1[2]);
in1[3]);