You are on page 1of 24

Story so far

• simplest description of computer? • what makes it general purpose?

CPU CPU
CPU
CPU

Main Memory

Memory

Story so far • simplest description of computer? • what makes it general purpose? CPU CPU

Story so far

• simplest description of computer? • what makes it general purpose?

CPU CPU Registers Control Unit Arithmetic & Logic Unit (ALU)
CPU
CPU
Registers
Control
Unit
Arithmetic & Logic Unit (ALU)
Main Memory Memory Program Data
Main Memory
Memory
Program
Data

• this lecture: internal structure of the CPU

- how it relates to the instruction set

CPU Organisation: Overview

CPU

Memory

CPU 1. Fast Memory 000 Addres Register 001 s file I 2. Arithmetic/logic 002 Bus R
CPU
1. Fast Memory
000
Addres
Register
001
s
file
I
2. Arithmetic/logic
002
Bus
R
n
003
R 1
N
t
ALU
e
Input Reg1
Data
r
Output Reg
Bus
RAM
n
a
Input Reg2
l
Control
B
3. Control
Program Counter
Bus
u
Instr. Decoder
Instr. Register
s
3FD
Control Unit
3FE
3FF

TOY1 Instruction Set

OPCODE

REG

ADDRESS

4-bit 2-bit 10-bit if opcode=LOAD then Rn = (a) if opcode=ADD then Rn = (b) (a)
4-bit
2-bit
10-bit
if opcode=LOAD
then Rn = (a)
if opcode=ADD
then Rn = (b)
(a)
(b)
wl 2012 7.4
Micro-steps: LOAD R2,[201] wl 2012 7.5

Micro-steps: LOAD R2,[201]

wl 2012 7.5

Understand CPU structure

step by step

– step 1: just main elements, no connections, no control – step 2: add control elements, e.g. multiplexers (mux) – step 3: derive control signals: next lecture

• Register Transfer Level (RTL) description: simple

– 6 registers: PC, IR, A 1 , A 2 , A out , MDR (memory data register) – 2 components respond in same cycle: UX, ALU, combinational – 2 components have Read and Write signals: Memory, Register file

• circuit diagram (see notes on basic logic design)

– with or without control elements (e.g. mux) – with or without control unit

Abstraction: include the minimum
Abstraction: include the minimum

Control and next

instruction logic

PC

Abstraction: include the minimum Control and next instruction logic PC Write IR M read M write

Write

IR M read M write addr Write Memory data
IR
M read
M write
addr
Write
Memory
data

MDR

A 2 R read R write Write ALU A out index Register Write A 1 File
A 2
R read
R write
Write
ALU
A out
index
Register
Write
A 1
File
data
Write
ALU control
Abstraction: include the minimum Control and next instruction logic PC Write IR M read M write

Write

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals 1 ALU Control signal

+1
+1

81

+1 81 IR M read M write 80 addr Write Memory data store in 80 MDR
IR M read M write 80 addr Write Memory data store in 80 MDR
IR
M read
M write
80
addr
Write
Memory
data
store in 80
MDR
A 2 R read R write Write ALU A out index Register Write A 1 File
A 2
R read
R write
Write
ALU
A out
index
Register
Write
A 1
File
data
Write
ALU control

PC

+1 81 IR M read M write 80 addr Write Memory data store in 80 MDR

Write

LOAD R2,[201]:

1. PC=PC+1, IR=M[PC]

Write

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals 1 ALU Control signal

… C 1 Control C 2 Unit IR 0-3 M read
C
1
Control
C
2
Unit
IR 0-3
M
read
IR 6-15 IR M read M write 201 UX addr Write Memory 09 data
IR 6-15
IR
M read
M write
201
UX
addr
Write
Memory
09
data
MDR
MDR

)

Write

PC

… C 1 Control C 2 Unit IR 0-3 M read IR 6-15 IR M read

Write

LOAD R2,[201]:

2. MDR = M[addr] addr = UX(IR 6

..

15

R read R write index Register File data
R read
R write
index
Register
File
data
A 2 Write ALU A out Write A 1 Write ALU control
A 2
Write
ALU
A out
Write
A 1
Write
ALU control

UX: Unsign eXtension from 10 to 16 bits

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals 1 ALU Control signal

wl 2012 7.9

PC Write LOAD R2,[201]: 3. R[IR .. 5 ] = MDR IR M read M write

PC

PC Write LOAD R2,[201]: 3. R[IR .. 5 ] = MDR IR M read M write

Write

LOAD R2,[201]:

3. R[IR 4

..

5

] = MDR

IR M read M write IR 4-5 addr Write R read R write Memory 2 index
IR
M read
M write
IR 4-5
addr
Write
R read
R write
Memory
2
index
data
Register
09
File
MDR
data

Write

A 2 Write ALU A out Write A 1 Write ALU control
A 2
Write
ALU
A out
Write
A 1
Write
ALU control

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals 1 ALU Control signal

… C 1 Control C 2 Unit M read
C
1
Control
C
2
Unit
M
read
IR M read M write UX addr Write Memory data
IR
M read
M write
UX
addr
Write
Memory
data

)

MDR
MDR

Write

PC

… C 1 Control C 2 Unit M read IR M read M write UX addr

Write

LOAD R2,[201]:

2. MDR = M[addr] addr = UX(IR 6

..

15

R read R write index Register File data
R read
R write
index
Register
File
data
A 2 Write ALU A out Write A 1 Write ALU control
A 2
Write
ALU
A out
Write
A 1
Write
ALU control

but step 1: IR = M[PC] so need mux

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals 1 ALU Control signal

+1 … C 1 Control C 2 Unit M read
+1
C
1
Control
C
2
Unit
M
read
+1 … C 1 Control C 2 Unit M read M read M write UX M
M read M write UX M addr 1 Write Memory C 1 data
M read
M write
UX
M
addr
1
Write
Memory
C
1
data
+1 … C 1 Control C 2 Unit M read M read M write UX M
IR A 2 R read R write Write ALU A out index Register Write A 1
IR
A 2
R read
R write
Write
ALU
A out
index
Register
Write
A 1
File
MDR
data
Write
ALU control

PC

+1 … C 1 Control C 2 Unit M read M read M write UX M

Write

+1 … C 1 Control C 2 Unit M read M read M write UX M

include mux M 1

Write

P

Q

  • 0 if C = 0 then P

  • 1 if C = 1 then Q

if ALU Control = 0 then A out = A 1 + A 2

  • C if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals

  • 1 ALU Control signal

  • 1 multiplexer signal

wl 2012 7.12

Micro-steps: ADD R2,[202]

Micro-steps: ADD R2,[202] wl 2012 7.13

wl 2012 7.13

+1
+1

82

+1 82 IR M read M write 81 addr Write Memory data store in 81 MDR
IR M read M write 81 addr Write Memory data store in 81 MDR
IR
M read
M write
81
addr
Write
Memory
data
store in 81
MDR
A 2 R read R write Write ALU A out index Register Write A 1 File
A 2
R read
R write
Write
ALU
A out
index
Register
Write
A 1
File
data
Write
ALU control

PC

+1 82 IR M read M write 81 addr Write Memory data store in 81 MDR

Write

ADD R2,[202]:

1. PC=PC+1, IR=M[PC]

Write

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals 1 ALU Control signal

… C 1 Control C 2 Unit M read
C
1
Control
C
2
Unit
M
read
IR M read M write 202 UX addr Write Memory 06 data
IR
M read
M write
202
UX
addr
Write
Memory
06
data
MDR
MDR

)

Write

PC

… C 1 Control C 2 Unit M read IR M read M write 202 UX

Write

ADD R2,[202]:

2. MDR = M[addr] addr = UX(IR 6

..

15

R read R write index Register File data
R read
R write
index
Register
File
data

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

A 2 Write ALU A out Write A 1 Write ALU control
A 2
Write
ALU
A out
Write
A 1
Write
ALU control

10 read/write signals 1 ALU Control signal

PC Write ADD R2,[202]: 3. A = R[IR ] A = MDR .. 5 M read

PC

PC Write ADD R2,[202]: 3. A = R[IR ] A = MDR .. 5 M read

Write

ADD R2,[202]:

3. A 1 = R[IR 4 ] A 2 = MDR

..

5

M read M write addr Memory data
M read
M write
addr
Memory
data
2 IR IR 4-5 A 2 Write R read R write Write index Register A 1
2
IR
IR 4-5
A 2
Write
R read
R write
Write
index
Register
A 1
File
MDR
09
06
data
Write

Write

ALU A out Write ALU control
ALU
A out
Write
ALU control

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals 1 ALU Control signal

PC Write ADD R2,[202]: 4. A = A + A IR M read M write addr

PC

PC Write ADD R2,[202]: 4. A = A + A IR M read M write addr

Write

ADD R2,[202]:

4. A out = A 1 + A 2

IR M read M write addr Write Memory data
IR
M read
M write
addr
Write
Memory
data

MDR

PC Write ADD R2,[202]: 4. A = A + A IR M read M write addr

Write

A 2 0F 06 R read R write Write ALU A out index Register Write A
A 2
0F
06
R read
R write
Write
ALU
A out
index
Register
Write
A 1
File
09
data
Write
ALU control

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals 1 ALU Control signal

M read M write addr Memory data IR 2 IR 4-5 read index R write A
 
M read M write addr Memory data
M read
M write
addr
Memory
data
IR
IR

2

IR 4-5
IR 4-5

R read

index

R write
R write
  • A 2

Write

ALU
ALU

ALU control

 

PC

Write

A out
A out

Write

0F

MDR Write A 1
MDR Write
MDR
Write
A 1
A 1
   

Write

 

Register

 

File

 

ADD R2,[202]:

     

data

Write

5. R[IR 4

5

] = A out

 
   

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals 1 ALU Control signal

PC Write Recall: LOAD R2,[201]: 3. 5 R[IR .. ] = MDR and ADD R2,[202]: R[IR

PC

PC Write Recall: LOAD R2,[201]: 3. 5 R[IR .. ] = MDR and ADD R2,[202]: R[IR

Write

Recall:

LOAD R2,[201]:

  • 3. 5

R[IR 4

..

] = MDR

and

ADD R2,[202]:

R[IR 4

  • 5. 5

..

] = A out

IR M read M write IR 4-5 addr Write R read R write Memory 2 index
IR
M read
M write
IR 4-5
addr
Write
R read
R write
Memory
2
index
data
Register
09
File
MDR
data

Write

if ALU Control = 0 then A out = A 1 + A 2

if ALU Control = 1 then A out = A 1 - A 2

A 2 Write ALU A out Write A 1 Write ALU control
A 2
Write
ALU
A out
Write
A 1
Write
ALU control

10 read/write signals 1 ALU Control signal

wl 2012 7.19

IR M read M write addr A 2 Write R read R write Memory Write ALU
IR M read M write addr A 2 Write R read R write Memory Write ALU
IR
M read
M write
addr
A 2
Write
R read
R write
Memory
Write
ALU
A out
index
data
Register
Write
A 1
File
MDR
data
Write
ALU control
Write
C 2
include mux M 2

if ALU Control = 0 then A out = A 1 + A 2

10 read/write signals

  • 1 ALU Control signal

  • 1 multiplexer signal

wl 2012 7.20

PC

IR M read M write addr A 2 Write R read R write Memory Write ALU

Write

P 0 if C = 0 then P Q 1 if C = 1 then Q
P
0
if C = 0 then P
Q
1
if C = 1 then Q

if ALU Control = 1 then A out = A 1 - A 2
C

+1
+1

83

+1 83 IR M read M write 82 addr Write Memory data store in 82 MDR
IR M read M write 82 addr Write Memory data store in 82 MDR
IR
M read
M write
82
addr
Write
Memory
data
store in 82
MDR
A 2 R read R write Write ALU A out index Register Write A 1 File
A 2
R read
R write
Write
ALU
A out
index
Register
Write
A 1
File
data
Write
ALU control

PC

+1 83 IR M read M write 82 addr Write Memory data store in 82 MDR

Write

GOTO 300 1. PC=PC+1, IR=M[PC]

Write

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals 1 ALU Control signal

… C 1 Control UX C 2 Unit IR 0-3 M read
C
1
Control
UX
C
2
Unit
IR 0-3
M
read

300

… C 1 Control UX C 2 Unit IR 0-3 M read 300 PC Write GOTO

PC

… C 1 Control UX C 2 Unit IR 0-3 M read 300 PC Write GOTO

Write

GOTO 300 2. PC = UX(IR 6

..

15

)

IR M read M write addr Write Memory data
IR
M read
M write
addr
Write
Memory
data

MDR

… C 1 Control UX C 2 Unit IR 0-3 M read 300 PC Write GOTO

Write

  • 300 IR 6-15

R read R write index Register File data
R read
R write
index
Register
File
data
A 2 Write ALU A out Write A 1 Write ALU control
A 2
Write
ALU
A out
Write
A 1
Write
ALU control

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals 1 ALU Control signal

+1 … C 1 M 3 Control UX C 2 Unit M C read 3
+1
C
1
M
3
Control
UX
C
2
Unit
M
C
read
3
+1 … C 1 M 3 Control UX C 2 Unit M C read 3 PC

PC

+1 … C 1 M 3 Control UX C 2 Unit M C read 3 PC

Write

IR M read M write addr Write Memory data
IR
M read
M write
addr
Write
Memory
data

MDR

IR 6-15

R read R write index Register File data
R read
R write
index
Register
File
data

C 4 or A 1 ≤0

include mux M 3

A 2 Write ALU A 1
A 2
Write
ALU
A 1

Write

ALU control

A out
A out

Write

+1 … C 1 M 3 Control UX C 2 Unit M C read 3 PC

Write

if ALU Control = 0 then A out = A 1 + A 2 if ALU Control = 1 then A out = A 1 - A 2

10 read/write signals

  • 1 ALU Control signal

  • 2 multiplexer signals

wl 2012 7.23

+1 … C 1 M 3 Control UX C 2 Unit M read C 3 IR
+1
C
1
M
3
Control
UX
C
2
Unit
M
read
C
3
IR
0-3
IR 6-15
IR 6-15
C 4 or A 1 ≤0
IR
M read
M write
IR
4-5
UX
M
addr
A 2
1
Write
PC
R read
R write
Memory
C
Write
ALU
1
A out
index
data
Write
Register
Write
A 1
File
MDR
M
data
2
Write
ALU control
Write
C 2
Now put everything
together!
10 read/write signals
if ALU Control = 0 then A out = A 1 + A 2
if ALU Control = 1 then A out = A 1 - A 2
1 ALU Control signal
4 multiplexer signals
wl 2012 7.24