srr07018 Lab Manual Project -| Electronic Circuit Analysis and Design Second fain —_—————— Instructor Resources Department of Electrical Engineering LABORATORY SAFETY AND EQUIPMENT USE PROCEDURES 1. For safety reasons, undergraduate students are never permitted to work unsupervised in any lnboratory when utilizing above 25 V. 2, Students may work in the EE teaching labs (Electronics, Radio, Measurement, etc.) at times other than the regularly scheduled lb period(s) under the following conditions: a. They submit a properly filed out and signed lab use permission form in advance to the EE Shop. b, They use the lab between the hours of 8:00 ‘AM and 4:50 PM unless there are graduate students with permission in advance from the lab supervisor to work at other times. ¢, There is another person with them in the lab competent to render aid or cal for heb. 3, Do not move equipment from one bench to another. If you have an instrument that is or seems to be defective, notify your instructor at once; please red-tag defective equipment and briefly describe the problem. The lab instructor should notify personnel in the EE Shop and they will replace any defective instrument. 4. Never switch plug-in modules, These are internally back-wired and iaputs/outputs can easily be shorted. Several of the plug-ins are key and slot configured to prevent them from being phigged into the wrong bay. Attempting to force them into position can severely damage connectors or P.C. boards. Please contact someone in the EE Shop ifyou have an equipment problem. We will try to resolve it 5. Do not write on equipment or ab benches. Ifneeded, blank removable stick-on labels will be provided for you to bel circuit components. Please ask, 6. Ifyou blow a fisse or find one already blown, it must be replaced with the correct value and physical size. Each fase holder is labeled with the correct fuse size in amperage. All fises are available at the EE Shop. Please bring the blown-out fuse with you. 7. Ifyou have a defective component (transistor, diode, IC, ete.), you can exchange it for a good one at the EE Shop. 8. Never leave a lib unattended with the door blocked open. Shop personnel will be happy to let you back into the lab as many times as necessary. 9. Ifyour shoes are muddy, wipe them offon the mats provided at all outside doors, not on the lab Iitpukwnvmbbe convengeslelectricalineamend Vnstructorabrervab_erwal mint ‘Wetsnons Lab Manual Project. stools. Do not place textbooks or other articles on electronic equipment. 10, Do not remove any equipment or software from a laboratory without securing prior approval of the EE Shop and the professor in charge of that lab. 11. Labs will be checked at 4:50 PM each day. The only students allowed in labs after 5:00 PM are those in regularly scheduled labs or those accompanied by an instructor, who must remain with the student(s). 12. At the end of each lab session: a. retum equipment, components, connectors, and software with manuals to their proper location, b. tum ofall equipment and bench power. ¢. tum offall battery-operated equipment. 4. leave the lab with a clean, orderly, professional appearance. 13. Become familiar with the operation of the lab equipment to be used by reading the appropriate sections of the equipment manuals provided at each bench. 14, Never use soldering irons or guns without protecting work bench tops. A piece of masonite will be provided by the EE Shop for you to use on work bench tops. 15. EE Shop personnel will attempt to help you in any way they can, Please help them by keeping. the labs neat and orderly, 16. Never Joan a laboratory key to anyone or diverge the keypad code. 17. Do not eat or drink in the labs. 18, Use the lab telephone for emergency calls only. Project 1 Power Supplies Objective: This project will show some of the basic principles of power supplies using fallwave rectifer, Zener diode, and fixed-voltage regulator circuits. Components: Bridge Rectifier (50 PIV, 1 A), Zener diode (10 V at 500 mW), 7805 regulator Introduction: Most of the direct current (DC) power used in electronic devices is derived by converting 60 Hz, 115 V alternating current (AC) power to direct current power. This AC to DC conversion usually involves a step-down transformer, rectifier, fier, and a regulator. The step-down transformer is used to decrease the AC line voltage from 115 VRMS to an RMS value near the DC voltage needed. The output ofthe step-down transformer is then fed into a diode rectifier circuit that only outputs positive halves of the input sinusoid, A fiter is then used to smooth the rectifier ‘pitanamntbe comengcsilectricalhearerO net abranab rao 24grro2018 tpukwnumbbe convengestelectricalneamend VinstruclorNabmeriab_ anual int Lab Manual Project output to achieve a nearly constant DC voltage level. A regulator can be added after the filter to ensure a constant output voltage in spite of changes in load current and input voltages. ‘Two different types of voltage regulators will be used in this project. The first involves a Zener diode circuit and the second involves a voltage regulator circuit. A Zener diode can be used as a voltage regulator when the diode is reverse biased and operated in the breakdown region. To ‘maintain voltage regulation, the Zener diode must be operated in the breakdown region at a current greater than the "knee" current (IZK). For currents greater than IZK, the Zener diode characteristic curve is nearly vertical and the voltage across the diode changes very litte. Of course there is a ‘maximum current the diode can tolerate, so good regulation is provided when the diode is reverse biased with currents between IzK and IZMAX. Zener diodes are available with a wide variety of breakdown voltages. Another type of voltage regulator is available with the 7800 series regulators, This series of fixed-voltage regulators is numbered 78xx, where xx corresponds to the value of the output voltage. Output voltages from 5 to 24 volts are available. These regulators are easy to use and work very well. Design: 1. Find approximations for the DC voltage level and AC peak to peak ripple voltage for the bridge rectifier and fiter circuit of Figure 1-1 2. For the Zener diode regulator circuit of Figure 1-2 assume that the Zener diode will regulate at 10 V over a current range of S mA to 25 mA. Assuming that the current flowing through R is always between 5 mA and 25 mA and the Zener diode is regulating at 10 V, find the minimum values of R and RL required. You may assume the forward diode drop for the two diodes is ~ 1 V. ML Transformer Figure 1-1: “(6 R 115 Yenes) | 2 Yanss + z - R, vy, — 1 Yn ‘Transformer 7 Figure 1-2: Zener Diode RegulatorntpiAwwn tne comlengeslelectricatineamen0 Vintruclor abv rerual rnd Lab Manual Project 7805 Rp Vy Figure 1 - 3: 7805 Regulator O° Pin 1 = Input Pin 2 = Ground Pin 3 = Output 123 TT Figure 1 - 4: 7805 Pin Configuration Lab Procedure: 1. Construct the bridge rectifier circuit of Figure 1-1 without the capacitor. Use the Variae with the step-down transformer for the input voltage to the bridge rectifier. With the transformer phigged into the Variac, adjust the Variac until the secondary voltage ftom the transformer equals 12 VMS. BE CAREFUL not to short the secondary terminals! Observe the secondary waveform on the oscilloscope. Put the oscilloscope on DC coupling and observe the load voltage waveform VL. Remember that both the input source and the load cannot share a common ground terminal. 2. Remove power ffom the circuit. Insert the capacitor as shown in Figure 1-1 being sure to observe the correct polarity. Energize the circuit. With the oscilloscope on DC coupling observe VL. Measure the DC voltage level using the digital voltmeter. With the oscilloscope on AC coupling observe the ripple voltage VR. Compare these measured values with the calculated values. 3. Observe the effect of loading on the circuit by changing the load resistor from 1 kO to 500 ©. Measure the DC voltage level with the digital voltmeter. Observe the ripple voltage with the oscilloscope set on AC coupling. Compare these values with the previously recorded values, 4. Record the Zener diode characteristic curve from the digital curve tracer. Note the value of the breakdown voltage in the breakdown region. Also note the value of the “knee" current IZK. 5. After verifying your designed values for R and Rt with the instructor, construct the Zener diode regulator circuit of Figure 1-2. Measure the DC voltage level with the digital voltmeter for the minimum value of RL along with several values above and below the minimum value. Be carefil not to overload the Zener diode. Comment on the circuit's operation for these difierent load resistances.soos Lab Manual Prec, 6. Construct the 7805 regulator circuit of Figure 1-3 being carefil to observe the correct pin configuration of the regulator. Measure the load voltage for RL equal to 300.2, 200.0, and 100 Q. Calculate the current for each ofthese cases. Does the value of the load resistor affect the output voltage? 7. Using RL equal to 200 Q, record the 7805 regulator input voltage (pin 1) and output voltage (pin 3). Decrease the regulator input voltage by decreasing the setting of the ‘Variac, For each decrease in amplitude, record the regulator input and output voltages. Continue decreasing the amplitude until the output of the regulator drops a measurable amount below 5 V. What is the minimum input voltage needed for the 7805 regulator to produce a 5 V output? Questions: 1. Why can't the input source and load have a common ground in the bridge rectifier circuit? 2, Can the Zener diode be used as a conventional diode? Explain your answer and verify with a curve from the curve tracer. 3. Would the value of the output fiter capacitor have to increase, decrease, or remain the same to maintain the same ripple voltage ifthe bridge rectifier were changed to a half-wave rectifier? Explain your answer, 4, How would increasing the frequency of the input source affect the ripple voltage assuming all components remained the same? Project 2 Analog Applications of the Operational Amplifier Objective: This project will demonstrate some of the analog applications of an operational amplifier through a summing circuit and a bandpass fier eitcuit. Components: 741 op-amp Introduction: Figure 2-1 shows a weighted summer circuit in the inverting configuration. This circuit can be used to sum individual input signals with a variable gain for each signal, The virtual ground at the inverting input terminal of the op-amp keeps the input signals isolated fiom each other. This isolation makes it possible for each input to be summed with a different gain, ‘The bandpass fiter shown in Figure 2-2 uses an op-amp in combination with resistors and capacitors. Since the op-amp can increase the gain of the fiter, the fiter is classified as an active fier. This bandpass fiter circuit is extremely usefill because the center frequency can be changed by varying a resistor instead of changing the values of the capacitors. The center frequency is given by: htpihwrhbe convengeslelectricalineamend nstructorlebmanab_ enw int 564sr102015, Lab Manual Project on, x tae RR ‘The center frequency can be changed by varying the variable resistor R3. Increasing R3 decreases the center frequency while decreasing R3 increases the center frequency. The bandwidth is given by: 1 zOR, ‘Notice that the bandwidth is independent of the variable resistor RS so the center frequency may be varied without changing the value of the bandwidth. The gain atthe center frequency of the bandpass fiter is given by: Af= & or oR Design: 1. Find the relationship between the output and inputs for the weighted summer circuit of Figure 2-1 2. Design a bandpass fiter with a center frequency of 2.0 kHz and a bandwidth of 200 Hz. Let the voltage gain at the center frequency be 20. Check your design with PSPICE. Use + 15 V supplies for the op-amp. Use RL= 2.4 kQ. 1A Ry Figure 2 - 1: Weighted Summer bio nhibe.comlengcsielectricalneamenOfitructrlabrer i merual bint 664srra1s Lab Morus Project Figure 2 - 2: Bandpass Filter ‘Lab Procedure: 1. Construct the summing amplifer of Figure 2-1. Design for the transfer fimetion to be Vo=-2 VINI - ViN2. Use + 15 V supplies for the op-amp. Use RL= 2.4 kQ. 2. Let Vint be a 1 V peak sine wave at 1 kHz and VIN2 equal to 5 V DC. Verify the ampiifier's operation by monitoring the output waveform on the oscilloscope. 3. Construct the bandpass filter of Figure 2-2. Use the designed values for the resistors and capacitors. Use +15 V supplies for the op-amp. Use RL = 2.4 kQ. 4, Record and plot the frequency response (you may want to use computer control for the sweep and data collection). Find the center frequency, comer frequencies, bandwidth, and center frequency voltage gain to verify that the specifications have been met. 5. Change R3 to lower the center frequency from 2.0 kHz to 1.0 kHz. Repeat part 4 for the new fiequency response. Verify that the new center frequency is 1.0 kHz. ‘What is the new bandwidth? What is the new center frequency voltage gain? Compare with the measurements of Procedure 4. Questions: 1. Could the summer circuit be used with the inputs connected to the noninverting terminal and produce the same affect without the inversion?” Explain, 2, What is/are the benefit(s) of using an op-amp circuit to produce a bandpass filter over using an RLC circuit with a noninverting op-amp at the output of the RLC circuit? Project 3 Analog Computer Applications using the Operational Amplifier Objective: This project will focus on the use ofthe operational amplifier in performing the mathematical operations of integration and differentiation, The design of simple hpuhwoumtne comfengesielectricetneamend Vinstucteabrenat_ renwal it 7164srro2015, itpukwauntte.comiengesfelecricareamen Vinstructer eben rrarual ind Lab Manus Project circuit (analog computer) to solve a differential equation will alo be included. ‘Components: 741 op-amp Introduction: Figures 3-1 and 3-2 illustrate two op-amp based circuits designed to perform differentiation and integration respectively. The operations are performed "real-time" and can be helpful in observing both initial transients and steady state response. The analysis of the circuits is based on the "ideal" ‘op-amp assumptions and performed in the time domain, The resistor RI shown in the two circuits is included to help with stability and for general circuit protection, ‘The value for Rr is nominally set equal to the feedback resistor (Figure 3-1) or the input resistor (Figure 3-2). The purpose of the optional resistor is left for student investigation in conjunction with the summary questions, ‘The differentiator and integrator circuits may be combined with "standard" inverting and non- inverting op-amp circuits to provide the building blocks for analog computers. The resultant analog computer circuits are designed to solve differential and/or integraV differential equations in a real time environment. The ability to easily include, and change, initial conditions and forcing fimctions are additional benefits of the analog computers. Figure 3-3 illstrates a circuit designed to solve the second order differential equation KY" - Y = 0 with the initial condition Y(0) = - Vx and K = RiR2C1C2. The inital condition is "set" by using the momentary contact switch to force the output to equal the applied voltage at t= 0 (the time the switch is closed). While the major advances in digital computers and digital signal processing have reduced the use of these three circuits, they are still fast and relatively inexpensive method for process control and stabilty/operation analysis for systems that can be represented in terms of differential equations. Design: 1. Derive the expressions relating the input and output signals for the circuits shown in Figures 3-1 and 3-2. 2 222 - 05% = 70) 2. Design an analog computer to solve dé! dt with y(0) = 2. Solve the differential equation when f(t) = 0 and verify your results using PSpice®. Figure 3 - 1: Differentiatorerrors Lab Manual Project c Ry ©ptionan| R VE A ees Vo R R Figure 3 - 2: Integrator hitial condition) ‘te cy i. > -RyC, dylat a Figure 3 - 3: Analog Computer (linear, second order, homogenous differential equation) Lab Procedure: 1. Construct the circuit shown in Figure 3-1, Use + 15 V supplies for the op-amp and aload resistance of = 2.4 kQ. 2. Verify the operation of the circuit using a 500 mV peak, 50 Hz sinewave as the ‘input signal. Be sure to design the "gain" such that the output does not saturate. 3. Repeat step 2 with a sinewave frequency of 500 Hz. Does the circuit stil operate correctly? What changes need to be made to prevent output saturation? 4, Repeat steps 2 and 3 using a triangle wave and then using a square wave with the same magnitudes and frequencies as used in steps 2 and 3. 5. Construct the circuit shown in Figure 3-2. Again, use + 15 V supplies for the op- amp and a load resistance of = 2.4 kQ. 6. Repeat steps 2 through 4 for this circuit. Be sure to adjust your "gain" as necessary to maintain an output signal within the saturation limits of = + 12 V. hipitwnuinthe confengeselectricalneamen0instructorisbmeeab ara inl 9641102015 La Maal ret 7. Construct the circuit designed to solve the differential equation in part 2 of the design section. Verify the operation of the design using three different input waves (sine, triangle, and square). Determine the operation for at least three different frequencies -- 10 Hz, 1 kHz, and 100 kHz. Explain any differences in operation of the circuit. What affect does the initial condition have on the result? Questions: 1. How could you use the differentiator to obtain an estimate of the slew rate for the op-amp? 2, Why should you include a resistor in parallel with the capacitor in the integrator? 3. What is the purpose of the resistor in series with the input capacitor in the differentiator? 4. Is it possible to design a circuit to perform the differentiation and integration functions using the non-inverting input? Explain your answer. Project 4 Digital Applications of the Operational Amplifier Objective: This project will show the versatile operation of an operational amplifier in voltage comparator (Schmitt trigger) circuits. Components: 741 op-amp Introduction: ‘A voltage comparator is a two-input circuit that compares the voltage at one input to the vollage at the other input. Usually one input isa reference voltage and the other input a time varying signal. If the time varying input is below or above the reference voltage, then the comparator provides a low or high output accordingly. The ideal operation ofa comparator is shown in Figure 4-1. If VREF is zero, the comparator can be used as a zero-crossing detector. If VREF is not zero, the comparator can be referred to as a level detector. The comparator is the basis for most A/D circuits. In these ADD circuits, the reference voltage is gradually changed by a counter and compared to the analog ‘input voltage until it equals the analog input voltage. The Schmitt trigger is a comparator that uses hysteresis, The transfer characteristic of the Schmitt trigger is shown in Figure 4-2: The Schmitt trigger basically has two thresholds, one on each side of the reference vollage. This gives a buffer zone for the rejection of noise and interference of the input signal. The hysteresis enables the comparator to tum on at one voltage value and possibly tur offat another voltage value. For example, a decreasing signal will remain at Out+ until VIL is crossed and then remain at Out- until the signal increases and crosses VTH. Ifthe noise voltage in a noisy input signal does not exceed the hysteresis voltage, then false, or nnilipl triggering is avoided. Hysteresis in the Schmit trigger also ensures that the output is the same frequency as the input for noisy input signals that may cross the threshold several times while rising and falling. The Schmit trigger is especially useful for slowly varying and noisy input signals. The comparator circuits of Figures 4-3 and 4-4 design using the operational amplifier allows for flexibility in setting the gain, thresholds, and reference voltage. Design: hitpakwrurtte convengesieletricalipeemen0 Vinstrucoriabmarab_ mara inl 1064aran015 {Lab Manuat Project 1. Find the relationship between the resistances in the comparator circuit shown in Figure 4-3 along with the thresholds VIL and VTH. Remember that you can not use all the ideal op-amp assumptions when only positive feedback is used. You should alo recognize that the output will generally be at the saturation point. 2. Modify the above equations for a reference voltage not equal to zero. 3. Repeat steps 1 and 2 for the circuit in Figure 4-4. y, Figure 4 - 1: Ideal Comparator Transfer Charaeteristic y, out* Out” Figure 4 - 2: Comparator Transfer Characteristic with Hysteresis R Figure 4 -3: Non-Inverting Comparator with Hysteresis mtpuhwwutte.comengesilectrcalneamen0 Vinstructerabmanvab, manual rind ‘64sr102015 {Lab Morual Project AA, Ywe_VA a \ I in A A. Figure 4 - 4: Inverting Comparator with Hysteresis Lab Procedure: 1. Construct the comparator circuit of Figure 4-3. Set the reference voltage to zero and the thresholds | V above and below zero. Use #15 V supplies for the op-amp. 2. Verify the comparator's operation by using computer control of the function generator to sweep the input voltage fiom -5 V DC to +5 V DC. Observe the high threshold vollage. Measure the slope of the line between the low and high output limits. Note: The step size for the sweep may have to be reduced to determine the slope. 3. Sweep the input voltage fiom +5 V DC to -5 V DC and observe the low threshold voltage. Measure the slope of the line between the low and high output limits. Again, the step size for the sweep may have to be reduced to determine the slope. 4, Now use a2 V peak sine wave at 1 KHz as the input. Monitor the input and output waveforms on the oscilloscope. 5. Repeat the above 4 steps for the circuit shown in Figure 4-4, Comment on the differences and similarities between the two circuits. Questions: 1. How can you determine the maximum frequency at which the Schmitt trigger can operate? 2. Does either circuit (Figure 4-3 or 4-4) have an advantage in operating over the other? Explain your answer. 3. What are the primary advantages/disadvantages of the comparator in Figure 4-4 as compared to that shown in Figure 4-37 Project 5 Sample and Hold Circuits using Operational Amplifiers Objective: ‘The design and operation of sample and hold circuits based on operational amplifiers is the basis of this project. ntpuhw the. comfengesilectricalnearendVinstructornabrer id enval rtm 1264srr02015 Lab Manual Project Components: 741 op-amp, IN4001 diodes (2), 2N7000 MOSFET Introduction: For an analog signal to be processed by a digital system it must be converted to a digital signal. A sample and hold circuit is one way of accomplishing this conversion. In a sample and hold circuit, the analog input signal is sampled and then held at the same value until a new sample is taken, Two important properties of sample and hold circuit are the highest possible sampling rate and how constant the sample remains during the hold interval The sample and hold circuit shown in Figure 5-1 uses an op-amp in the noninverting configuration and a MOSFET. The control voltage is generally a square wave (system clock) which represents the sampling rate and the length of time to hold the sample. The MOSFET acts as a switch which is on during sampling and off during the hold time. When the square wave is positive, the circuit samples the input signal, During sampling the MOSFET turns on to complete the path to the capacitor and the circuit output is approximately the same as the input signal, When the square wave is negative, the circuit isin the hold mode. During the hold time the MOSFET tums off and the output is the value the capacitor charged to during the previous sampling interval. Figure 5-2 illustrates another sample and hold circuit with improved operating characteristics. This improvement comes at the expense of additional complexity and components. An understanding of the necessary conversion timing, voltage levels, and operating frequencies are all important in deciding on the type of sample and hold circuit best suited for the job. Design: 1. Verify the operation of the sample and hold circuit of Figure 5-1 with PSPICE®. Use a1 V peak sine wave at 60 Hz for the input waveform, Use 15 V supplies for the op-amp. Set the control voltage to insure a sufficient sampling rate. The student may ant to use the Nyquist criteria in determining the minimum control signal ftequency. 2. Repeat step 1 for the circuit shown in Figure 5-2. Compare the results for the two circuits, Explain/discuss any differences between the two circuits in terms of the results ofthe computer analysis. 3. Compare the analysis results from steps 1 and 2 with a manual (approximate) analysis using ideal component approximations, Comment on any differences. V control G 502 al: JE +} Dils v 0: y, 2 pe : puta bie comengeslelecrcallneemendVinetructeiebmenvi erual bint rets02015 Leb Manual Project Figure 5 - 1: Simple Sample and Hold Circuit Figure 5 - 2: Advanced Sample and Hold Circuit : Lab Procedure: 1. Construct the sample and hold circuit of Figure 5-1. Use a square wave with an upper limit of +10 V and a lower limit of -10 V for Veontrol, To begin with, use Rt = 100 and C =2 1F, and a sampling rate around 1 kHz. Use #15 V supplies for the op- amp. 2. Use the Variae with the step-down transformer for the input waveform. With the transformer phigged into the Variac, adjust the Variae until the secondary voltage fiom the transformer has a peak of = 1 V. 3. Monitor the input and output waveforms on the oscilloscope. Do the two waveforms match? Note any offiet error. Try and explain any errors. 4, Repeat steps 1-3 for the circuit illustrated in Figure 5-2. Questions: 1. For each of the sample and hold circuits, determine the approximate decay rate of the capacitor voltage in mV/s during the hold mode. Relate this to the values of the capacitor and associated equivalent resistance. 2. Do these circuits seem to follow a typical capacitance voltage "droop" or decay between sampks? 3. Does either circuit provide a better (closer) capacitor and input signal equality? Explain your answer. 4, What is the maximum hold time for each sample and hold circuit ifthe capacitor voltage is designed to change by < 10% of the sampled vahie? Project 6 BJT Digital Logic Gates Objective: This project will investigate the operation of BIT based digital logic gates, ‘Components: 2N2222 BJT (5), IN4001 diode htpikwaumbbe.comengesllectrcalneemend instructerabmarvib anual rind 1964sr02015 Lab Manual Project Introduction: ‘Two types of transistors commonly used in implementing logic circuits are BJTs and MOSFETs. In logic circuits, the transistor acts as a switch with two states - on and off, There are many characteristics used to evaluate the performance of logic circuits. Some of these characteristics are: power consumption, switching speed, noise margins, and fan-out. Noise margin is the maximum noise voltage that may be present in a gate without upsetting the proper operation of the circuit, ie. ‘maintaining correct logic levels | and 0. Fan-out specifies the number of standard loads that the output ofa gate can drive and still maintain proper operation. One advantage of MOSFET logic gates is their high input impedance, and therefore low power consumption. BIT based gates (TTL, ECL, DIL, etc.) generally have faster switching times then comparable MOSFET based gates Figure 6-1 shows a two input TTL NAND gate. When used as an inverter, this NAND. gate will have a transfer characteristic as shown in Figure 6-2. The low level and high level input and output values are indicated. ‘The output impedance ofa gate is normally modeled by a combination of resistance and capacitance. This load model is applicable to any load including similar logic gates connected to the ‘output. When the gate output switches from the low to the high state, the load capacitance mast ccharge thus creating a propagation delay. The TIL NAND gate of Figure 6-3 is the same as the TIL NAND gate of Figure 6-1 with a totem-poke output stage. The totem-pole output stage consists ofa CC (\with an additional 130 © resistor) stage stacked on top ofa CE stage with a diode in between, The CE stage has the ability to sink large load currents and rapidly discharge the load capacitance. The CC stage with its low output impedance can source large load currents and quickly charge the load capacitance. Therefore higher speed operation and better drive capabilities are obtained using the totem-pole output stage. Another popular BJT logic family is the Emitter Coupled Logic (ECL) circuit shown in Figure 6-4. The ECL circuit is designed to provide complementary outputs (NOR and OR) without saturating the transistors as occurs in the basic TTL logic family. The logic switching is accomplished by effectively transferring the current through R3 (or current source in place ofR3) through either the reference transistor branch or the input transistor(s) branch. ECL is inherently faster then TTL logic based in part on the non-saturating transistors. Another advantage ofthe ECL circuit is the availabilty of both the output variable and its complement (” a4’), The relatively low noise margins for the ECL however make it very susceptible to noise. The use of negative power supplies is one way to help reduce the likelihood of large noise components interfering with the circuit operation 3.9kQ Figure 6 - 1: TTL NAND Gate hau be comenges/lectrcalloeamend Vinstrucellabrervib,rerual rit 1864aro015 Lab Manual Project Pole Output Qs [—NoR 15kQ, Figure 6 - 4: ECL Logic Gate Design: 1. Verify the operation of the TTL NAND gates with and without the totem pole ‘output stage using both manual approximations and PSPICE®, 2. Determine the values of resistors Ri and R2 so that the reference voltage (VREF) for ‘the ECL circuit in Figure 6.4 is ~ - 1.2 V using VEE = - 5.2 V. ‘htipdwaw.mbthe.comfenges/electricalineamend V/instructor/labmaniab_manual.mbtrrl 1864srta01s Leb Manual Project 3. Verify that your design values from step 2 result in proper operation of the ECL circuit. Specify the maximum and minimum input level magnitudes to insure proper switching of the circuit. You may assume a delta of at least 100 mV between the base terminals ofthe emitter coupled transistors insures complete current switching, Lab Procedure: 1. Construct the TTL NAND gate of Figure 6-1, Verify its operation by completing a voltage truth table for the gate. Use 5 V for a high input and 0 V (ground) for a low input. Observe the output of the gate with the voltmeter. 2. Tie inputs A and B together to form an inverter. Vary the input voltage from 0 V to 5 V (you can actually see the necessary voltages by sweeping between 0 V and 2 V) and record the output voltage. Plot the transfer characteristic (Vo vs, Vi). Compare your transfer curve with Figure 6-2 to find the points ViL, VoL, VOH, and ViH. 3. Obtain a high output state with inputs A and B still tied together, Place the decade resistance box between the output and ground. Note: Always connect the decade resistance box with the resistance set at the maximum value. Vary the resistance until the output falls to 2.0 V, Determine the maximum high output load current ([08). 4. Obtain a low output state with inputs A and B still ied together, Place the decade resistance box (read connection note in Lab Procedure 3) between the 5 V supply and the output. Vary the resistance until the output rises to 800 mV. Determine the maximum low output load current (LoL), 5. Add the totem-poke output stage to the NAND gate to form the circuit of Figure 6- 3. Verify ts operation by completing a voltage truth table for the gate. You should also produce a plot of Vo vs. Vi using the lab software, 6. Repeat Lab Procedures 3,4 for the totem-pole NAND gate. Compare the results with the previous case. 7. Construct the ECL logic gate of Figure 6-4. Be sure to connect the ground and supply correctly. Verify the circuit operation by constructing a voltage truth table. Use 0 V for the high and - 5 V for the low. Record the output voltages for each output under the four input combinations. 8. Repeat Lab Procedure 2 for the two ECL outputs. Questions: 1. What finctions do the diode and 130 © resistor serve in the totem-pole output stage? 2. Which output stage of the TTL NAND gate allowed the largest output currents? 3. How would you modify the NAND circuit in Figure 6-3 to achieve the logical NOR operation without changing the output (totem pole) stage? itpytumuntte.confengesllectricalneemend inetructoretmaniab ‘anual hind ressrr02015 Leb Menu Project 4, Are the NOR and OR outputs symmetric (mirrored images) over the entire input operating range? Exphin any differences. 5. Would the answer to question 4 change if 3 in Figure 6-4 were replaced by a constant current source? Why or why not? Project 7 FET Digital Logic Gates Objective: This project wil investigate the operation of MOSFET based digital logic gates. ‘Components: 2N7000 n-MOSFET (4), BP170P p-MOSFET (2) Introduction: As discussed in Project 6, there are basically two types of transistors used in implementing logic circuits --- BJTs and MOSFETs. This project will focus on the logic circuits implemented using MOSFETs. Circuits involving both passive and active loads using n- MOSFETs and circuits designed using both n-channel and p-channel devices (CMOS) will be designed and tested. One advantage of MOSFET logic gates is their high input impedance resulting in low power consumption. This is especially true for CMOS gates. As mentioned in Project 6, BJT based gates (TTL, ECL, BL, etc.) generally have faster switching times then comparable MOSFET based gates Figures 7-1 and 7-2 show a MOSFET NAND gate and NOR gate respectively. Notice that both these gates are implemented entirely through the use of MOSFETs without any resistors or diodes. The gate and drain ofM1 in each circuit are connected together to imitate a load resistor. In this configuration, M1 acts as an active load for the circuit. Figure 7-3 ilustrates a CMOS NAND gate. The circuit is designed using p- MOSFETs as the active load and n-MOSFETs as the drivers. Each input signal is connected to both an n-channel and a p-channel MOSFET. In this configuration, the output "capacitance" (the input to a subsequent gate for example) can be rapidly charged through the p-channel device or discharged through the n-channel device. The low drain to source channel resistance of the non-saturated MOSFET provides the low time constant associated with the rapid charging/discharging capability. Notice that only one of the two devices (p-channel or n-channel) can be on for a given high or low input signal. This on/off arrangement results in no power consumption except during the actual switching of the output level. Design: 1. Verify the operation of the NAND and NOR gates in Figures 7-1 and 7-2 with PSPICE®. 2. Design a MOSFET based logic circuit with active load to achieve the fimction: D= A+ BC The design should minimize the number of MOSFETs required. 3. Design a CMOS circuit to achieve a two input NOR logic operation. Verify your design using PSPICE®. hitpkwmutbe conenges/lecrcalreamend Vinstructerebrervib rearward 1064sr102015 Lab Manual Project Ypp sv Figure 7 - 2: MOSFET NOR Gate with active load Yop sv 1. Mpg LJ PL pt Vout Vp Figure 7 - 3: CMOS NAND Gate htpihwnuntbe convengesielectricalineamennstructorabmarvab. manual min! 196497102015 Lab Manual Project ‘Lab Procedure: Not ‘The MOSFETs can be easily damaged by static electricity, so careful handling is important. 1. Construct the MOSFET NAND gate of Figure 7-1. Verify its operation by completing a voltage truth table for the gate and produce a plot of Vo vs. Vi using computer control of the input voltage sweep to obtain the data, 2, Replace M1 in Figure 7-1 with a 1 kQ resistor and repeat step 1. Repeat this step again using a 10 kQ resistor. Compare the results from the three different loads and comment on the operation changes. 3. Construct the MOSFET NOR gate of Figure 7-2. Verify its operation by completing a voltage truth table for the gate produce a plot of Vo ws. Vi using computer control of the input voltage sweep to obtain the data, 4, Have your design for the 2*4* BC’ function verified by the instructor. Construct the circuit and verify its operation by completing a voltage truth table for the gate. Again produce a plot of Vo vs. Vi using the computer software. 5, Construct the CMOS NAND gate in Figure 7-3 and repeat step 1 for this circuit. 6. Construct the CMOS NOR you designed in the step 3 of the design section and verify is operation. Questions: 1. Which logic family, TTL, MOSFET, or CMOS allows the easiest logic implementations? Why? 2. Does the active load improve the operation of the MOSFET logic circuits? Explainjustify your answer. 3, Compare the output logic swings for Figures 7-1 and 7-3. Comment on the reasons behind any differences/similarties. 4, Why doesn’t the high output of Figures 7-1 and 7-2 equal VoD? 5, What is the primary reason MOSFET logic is slower than BIT based logic? Project 8 BJT Current Sources Objective: The design of'a constant current (independent current source) based on BJT operation willbe the basis of this project. Limitations on the operation will also be presented. ‘Components: 2N2222 BIT (4) Introduction: ‘The independent current source is one of the basic building blocks in circuit design. This project will nipuhawn athe comlengeslelectricalinesrerOtinstuctortabranfab anual mttnt ares072015 Lab Manual Project focus on the operation of two types of BIT based current sources as shown in Figures 8-1 and 8-2. These circuits are designed so the current through the "load" is not dependent on the load, but rather is dependent on the current in the "reference" branch. The reference branch current is a constant, independent of the load being driven, These current sources are generally referred to as (Current Mirrors since the current in the Joad branch efféctively mirrors the reference current. The Joad currents as shown in Figure 8-1 are approximately equal to the reference current while the Joad current in Figure 8-2 (Widlar Current Source) is a fraction of the reference current. The transistors are assumed to be matched with a reasonable forward beta (2 50) so the base currents can generally be ignored in the analysis and design of the current mirrors. The three transistors in Figure 8-1 are connected so that all three have the same base emitter voltage. The base (collector) current flowing in each transistor i a function of the base-emitter voltage as determined using the diode equation. Ifthe transistors are matched (approximately equal junction areas and reverse saturation currents) the current in each collector will be the same since the base-emitter voltages are equal. Ifthe transistors have beta (B) > SO, the base currents can be ignored relative to the reference current (ref) without introducing a significant error. The reference current is therefore mirrored through each load. The reference current can be determined using the ‘nominal base-emitter turn on voltage ( ~ 700 mV) as indicated below: ‘The reference current in Figure 8-2 is determined using the same equation used for Figure 8-1. The load current however, is not equal to the reference current even ifthe base currents are ignored. An examination of Figure 8-2 shows that the base-emitter voltage for the load branch transistor is smaller then that of the reference branch transistor. The two base-emitter vollages are related as: Vesey = Vixens) * loat Re ‘Again, the base currents are ignored in this equation, The two currents can be evaluated using the diode equation as indicated: Yoav Combining these three equations results in the following equation relating Iref and Tload in terms off the thermal voltage (Vi) and RE: i. Paste) ~ Vaptioat) ~ iol “f,) = Leas Re The value of RE can then be determined for specific values of lad current. Parallel load branches can be added in a manner similar to that shown in Figure 8-1 with each load current being different. Notice that the load current(s) for the Widlar current mirror is (are) always less than the reference current, Design: htpsAunumtbe comiengeselectricalieeren nstructorfabmarvab_ manual mind 2168srr0z015 Lab Manual Project 1. Verify the operation of the current mirrors shown in Figures 8-1-and 8-2 with PSPICE®. You may represent the load as a positive voltage source in series with a variable resistor connected between ground and the load branch of the current source. 2. Determine the number of mirrored currents possible for the circuit in Figure 8-1 if the transistor beta is 100 and you would like your currents to match the reference current within 10 %, 3. Design a current mirror based on the circuit in Figure 8-1 that will supply 10 mA to a load using a VEE = - 15 V. Determine any limitations on the load (represented as a resistor in series with a 10 V DC source). Discuss the reason for any imitations. 4, Design a Widlar source to supply | mA AND 10mA if RE is bypassed. You should again use a VEE =- 15 V. You should specify any limitations on your design. a) JT Current Mirror (< 0 Veg © Figure 8 - 2: Widlar Current Mirror Pre-Lab Procedure for Lab 9: (This information is needed for the required amplifier design) 1. From the digital curve tracer, find the value of BDC and B AC at the designed Q- Itpihwuumtbe comengesielectrcancamend inst uctoriatmerviaranual nt 2amsrio2015, bitpuhwnumtie convengesielectricalneamend VnstructorNabmerab_ enna mint Lab Manual Project point (use Ic = 10 mA and Va 0 V) ofa CE amplifier. Remember BDc = Ic/IB and BAC= AIC/ATB, How do the two 8 values compare? 2. Determine the values of hoe and hie from the digital curve tracer. The slope of the transistor IC-VCE curves in the active region is hoe. Find hie by looking at the base- emitter junction as a diode on the curve tracer. The tangent slope of the IB- VBE curve at the 1BQ point is I/hie, Lab Procedure: 1. Construct the current mirror designed in step three of the design procedures. Connect the resistance decade box (set to at least 1 kQ) between the load branch of the current mirror and the positive terminal ofa ++ 15 VDC source. Vary the decade box resistance between 10 kO and 0 Q in appropriate steps to plot the load current (¥1 axis) and collector-emitter voltage (VCE) for Q2 (Y2 axis) versus the load resistance (X axis). Discuss the results of the graphs in terms of circuit operation, limitations, and linearity. Comment on the ability to use this current mirror as an independent current source. 2. Repeat step | using a 220 Q load in one branch and the decade box as the load in a parallel branch, Comment on any similarties/dfferences in the results from the two circuits, 3. Construct the Widlar source designed in step 4 of the design section. Connect the resistance decade box (set to at least 1 k(2) between the load branch of the current mirror and the positive terminal ofa + 15 V DC source. Vary the decade box resistance between 10 KO and 0.Q in appropriate steps to plot the load current (¥1 axis) and collector-emitter voltage (VCE) for Q2 (Y2 axis) versus the load resistance (X axis). Discuss the results of the graphs in terms of circuit operation, limitations, and linearity. Comment on the ability to use this current mirror as an independent current source. 4, Install a resistive load (= 1 kQ) in place of the decade box for the Widlar current mirror. Set the decade box resistance to the value of RE from step 4 of the design section. Vary the decade box resistance as. appropriate to verify that the maximum current through the resistive load can increase to 10 mA. Plot the resus; Hoad on the Y1 axis and VcE2 on the Y2 axis versus the decade box resistance. Are the graphs as predicted by the design equations? Comment on the similarties/dfferences between the theoretical and experimental results, Questions: 1. What affect does the matching of the Betas used in the mirror circuits have on the stability of the load currents? What about the match of the junction areas? 2. In the Widlar current source, the design equations use a typical VBE turn on voltage 0f700 mV and the diode equation to determine the load current. Comment on the validity of this design procedure. How would you design the circuit using the diode equation for both junctions?sr07015 ‘Lab Manual Project 3. The loads for these experiments were illustrated using resistances. What other devices/circuits/systems would be valid loads? Which ones would not make valid Joads? Discuss the justification for your answers. 4, How would you determine the "resistance" of each of the two current mirrors (Single load branch with and without RE) as seen by the load? Would a high or low source (current mirror) be most beneficial? Explain your answer. 5, Discuss some of the limitations placed on the load and load source for proper ‘current source operation. Are there limits on the load resistance if the load source is + 15 V? Explain your answers. Project 9 Common Emitter Amplifier (designed for two lab periods) Objective: This project will show how the h-parameters for a BIT can be measured and used in an equivalent circuit model for the BIT. A CE small signal amplifier will be biased and designed to specifications along with both low and high frequency response and adjustment, Series-series feedback will alo be used to control the bandwidth and input impedance of the CE amplifer. Components: 2N2222 BJT Introduction: In order for circuits involving transistors to be analyzed, the terminal behavior of the transistor must be characterized by a model. Two of the models often used for a BIT are the hybrid-r and the h- parameter mode. The complete hybrid-r circuit model for the BJT is shown in Figure 9-1. This ‘model includes the intemal capacitances and output resistance of the BJT. Inclusion of the internal transistor capacitances makes the hybrid-7 model valid throughout the entire frequency range of the transistor. Typical data sheet values of Cr and Cy are 13 pF and 8 pF respectively. These values are so strall that Cx and Ch. may be considered open circuits for midband frequencies. ‘The resistance rx typically has a Value in the tens of ohms and can be considered a short circuit while 1 and ro are usually extremely large in valne and can be considered open circuits. ‘The h-parameter small signal model for the BIT is characterized by the four h-parameters and is shown in Figure 9-2. Unlike the hybrid- model, the h-parameter model does not ordinarily inchide frequency related effects and components and is therefore generally valid only at midband frequencies and below . However the h-parameter model is very usefil since the h-parameters can be easily measured for a BIT. The value of bre is usually on the order of 10-4 and can be considered a short circuit. The value of hoe is usually on the order of 10-5 S making I/hoe effectively an open circuit for most circuit configurations and biases, Making the same assumptions, the hybrid-r- and h-parameter models are equivalent at midband frequencies. Fora transistor to operate as an amplifier, it must have a stable bias in the active region. To bias a transistor, a constant DC current must be established in the collector and emitter. This current should be as insensitive as possible to variations in temperature and (or hie). The voltage across the base-emitter junction decreases about 2 mV for each 1 °C rise in temperature, therefore it is important to stabilize VBE to ensure that the transistor does not overheat. The circuit shown in Figure 9-3 is the biasing scheme most often used for discrete transistor circuits, For this circuit, the hitpukwumbte comenges/electrcallneamend Vinstructerllbrab, renal srbint 2A8102015, ‘Lab Manual Project base is supplied with a faction of the supply voltage VCC through the voltage divider RBI, Rn2. For ease of circuit analysis, the Thevenin equivalent circuit shown in Figure 9-4 can replace the voltage divider network. To ensure that the emitter current is insensitive to variations in | and VBE, VB should be much greater than VBE and RBB shoukl be much less than BRE. RBB is usually 20-30% of the product BRE. The voltage across REis also usually 2-3 volts for good stabilization, This same biasing scheme can be used for all three of the BIT amplifier configurations (CB, CC, CE). The BIT CE amplifier is shown in Figure 9-5. The signal source and resistive load are capacitively coupled to the amplifier. The coupling capacitors C1 and C2, emitter bypass capacitor CE, and internal transistor capacitances shape the frequency response of the amplifier. A typical amplifier frequency response curve is shown in Figure 9-6. The low half power comer frequency FL is controlled by the input and output coupling capacitors and the emitter bypass capacitor. The high half power comer frequency FH is controlled by the internal transistor capacitances and any Separate load capacitor. The bandwidth is the difference between the high and low comer frequencies (Fit - FL). As the signal frequency drops below midband, the impedance of the coupling capacitors C1 and C2 and emitter bypass capacitor CE increases. The coupling capacitors Grop more signal voltage and the emitter bypass capacitor begins to open up and causes increased series-series feedback resulting in a reduction of the gain, One method of relating Ci, C2, and CE to the low cutoff frequency is the short circuit time constant method. The time constant method is advantageous because it provides an approximate value forthe culof? frequencies without exactly finding all the poles and zeros ofa circuit. The time constant method also helps show which Capacitors are dominant in determining the comer frequencies. The short circuit time constant method relates FL and circuit capacitors by: Ligecd — 1) Bede, R, Where FL is the low half power frequency, ne is the number of coupling and bypass capacitors in the circuit, and Ci the value, in Farads, of the ith capacitor. Ris isthe resistance facing the ith capacitor with the th capacitor removed and all other coupling and bypass capacitors replaced by short circuits and the input signal reduced to zero, This resistance calculation is repeated for each coupling and bypass capacitor inthe circuit The intemal capacitances ofa transistor have values inthe picofurad (pF) range that begin to decrease the gain ofthe amplifier for frequencies above midband. A method of relating the internal transistor capacitances Cx and Cm to the high cutoff frequency is the open circuit tine constant method. This method relates FH and the internal transistor capacitances by: Te jlo 2nerGk Where FH is the high half power frequency, ne is the number of internal transistor capacitors in the Circuit, and Cis the value, in Farads, of the ith capacitor. Ri i the resistance ficing the ith capacitor with the ith capacitor removed and al intemal transistor capacitors rephced by pen eircuts and the input signal reduced to zero, This resistance calculation is repeated for each internal transistor capacitor in the circuit, !nipulwmurtte comfengesieletricalresmen0 Vnstructorabmar tab anual mtn 28168Lab Manval Prec “When the emitter resistor of the CE amplifier is left unbypassed, the input current signal flows through the unbypassed emitter resistor as does the output signal current. This unbypassed emitter resistor in the CE amplifier produces series-series feedback. The feedback resistor is RE. Feedback is used in amplifiers to control input and output impedances, extend bandwidth, enhance signal-to-noise ratio, and reduce parameter sensitivity. These feedback performance improvernents are allat the expense of gain in the amplifier. Figure 9 - 1: Hybrid-x BJT Model D> Mets 50 3. low cutoff frequency FL between 100 Hz and 200 Hz. 4. input impedance as seen by the source 2 1 kQ. 5. Vo symmetric swing = 2.0 volts peak (4 V p-p) 6. load resistor RL = 1.5 kQ 7. source resistance RS = 50 © (this is in addition to the function generator's internal resistance) Lab Procedure: (steps 1 and 2 may be omitted if done prior to this lab period. and the same BJT is used) 1. From the digital curve tracer, find the value of BDC and BAC at the designed Q- point ofthe CE amplifier. Remember BDC = Ic/IB and BAC= AIC/AIB. How do the ‘two B values compare? 2, Determine the values of hoe and hie from the digital curve tracer. The slope of the transistor IC-VCE curves in the active region is hoe. Find hie by looking at the base- emitter junction as a diode on the curve tracer. The tangent slope of the IB-VBE curve at the 1BQ point is 1 /hic. 3. Construct the CE amplifier of Figure 9-5. Remember RS is installed in addition to the internal 50 Q resistance of the fiction generator. Note that (Rt + RE2) shoukl cequal the designed value for RE and RE! ~ RE2. Verify that the specifications have been met by measuring the Q-point, midband voltage gain, and peak symmetric output voltage swing. Note any distortion in the output signal. 4, Observe the loading affect by replacing RL first by 150 Q and then by 15 kQ. Note any changes in the output signal and comment on the loading affect. 5, Use computer control to record and plot the frequency response. Find the comer frequencies and bandwidth to verify that the specifications have been met. 6. Measure the input impedance seen by the source [look at the current through Rs and the node voltage on the transistor side of RS] and the output impedance seen by the load resistor [look at the open circuit voltage and the current through and voltage across RL = 1.5 kQ]. Verify that the input impedance specification has been met. hitpuhwnu nti comengesltectricelneamenintructrlbreviae anual mint 20689102016. hitpdsuvwurtne comengesielectricalneamend VinstructerNebmanteb ental int Lab Manual Project 7. Now adjust the bypass capacitor CE so that REI is not bypassed (which is a series- series feedback configuration). Measure the Q-point and midband voltage gain, Note any distortion in the output signal 8. Repeat steps 4 - 6, 9. Remove the bypass capacitor CE completely. Measure the Q-point and midband voltage gain. Note any distortion in the output signal. 10. Repeat steps 4 - 6, Questions: 1. Compare the measurements in Lab Procedures 3-10 to the theoretical predictions such as those obtained using PSPICE®. Note how increasing the feedback affects the gain, bandwidth, and input and output impedances. 2. Can you think ofa way to vary the amount of feedback (gain) using a potentiometer ofa value equal to RE without affecting the Q point? 3. How can Fi be reduced using extemal components? 4, Why is the value of FH measured in the lab generally different from (lower than) the value of FH determined using PSPICE® or manual calculations? Project 10 Common Collector Amplifier Objective: This project will how the biasing, gain, frequency response, and impedance properties ofa common collector amplifier. Components: 2N2222 BJT Introduction: ‘The common collector amplifer as shown in Figure 10-1 i one of the most usefil small-signal amplifier configurations, The same biasing scheme and frequency response approximation technique 83s used for the common emitter amplifier can also be used forthe common collector amplifier. The only change that needs to be made in biasing is that the voltage across the emitter resistor RE is ‘usually larger for the common collector to allow a greater output voltage swing, The collector resistor is also usually omitted in the common collector configuration. The main characteristics of the common collector amplifier are high input impedance, low output impedance, less than unity voltage gain, and high current gain. This amplier is most often used as a bulfr or isolation amplifier to connect a high impedance source 10 low impedance load without loss of signal The load seen by the amplifr’s signal source is the input impedance of the amplifier. With a high input impedance, the CC ampifier loads the source very lightly. Therefore the signal source is largely isolated or buffered fom the rest ofthe cieuit. The maximum current gain for the CC ample is B+ 1. This high current gain allows the CC amplifier to increase the power ofthe signal. These power and current sais make the CC amplifier a practical choice as an output stage ampli driving several devices and/or low impedance loads. Design:ros Lab Manual Preect Design a common collector amplifier with the following specifications: 1. use a 2N2222 BIT and a 12 volt DC supply 2, midband gain Vo/Vs 2 0.5 3. low cutoff frequency FL between 100 Hz and 200 Hz 4, input impedance seen by the source 2 10 kQ 5, Vo symmetric swing 2 3.0 volts peak (6 V p - p) 6. load resistor RL= 200 2 7. source resistance RS = 50 Q (this is in addition to the function generator's internal “resistance) ec Rei c L 2 | | Ry | | Function | ee Generator Ry R Figure 10 - 1: Common Collector Amplifier Lab Procedure: 1. Construct the CC amplifier of Figure 10-1. Remember Rs is installed in addition to the internal 50 © resistance of the function generator. Verify the amplifier operation by ‘measuring the Q-point and midband voltage gain, Monitor the output on the oscilloscope to make sure the waveform is not clipped. Note any distortion in the output signal. 2, Adjust the input signal level to get a 3.0 volt peak symmetric output voltage swing. 3, Determine the midband current gain IL/Is [measure Is by looking at the current through Rs] What isthe overall power gain? 14, Observe the loading affect by replacing RL frst by ~ 50 Q and then by = 750 Q. htpikwaunthe comengeslelecrcaliwamen0 Vinstuctrebenviab anual hint 064eran ‘Lab Manual Project Note any changes in the output signal and comment on the loading affect. 5. Use computer control to record and plot the frequency response. Find the corner frequencies and bandwidth to verify that the specifications have been met. 6. Measure the input impedance seen by the source [look at the current through RS and the node voltage on the transistor side of RS] and the output impedance seen by the load resistor [look at the open circuit Vollage and the current through and voltage across RL]. Verify that the input impedance specification has been met. Questions: 1. How can you achieve maximum power transfer ftom the input signal source to the amplifier circuit? Is the load resistance a factor in the answer? 2. What value of load resistance results in maximum voltage gain? What bad resistance results in maximum power transfer to the load? 3. Compare the results of the current gain found in Lab Procedure 3 with the maximum possible gain of B +1. Comment on any differences. 4. Compare the measurements in Lab Procedures 1-6 to the theoretical predictions such as those obtained using PSPICE®. Note that you must adjust the circuit file to determine the output impedance. 5. What other method could be used to measure RO? Project 11 Common Emitter, Common Collector Amplifiers with Current Source Biasing (designed for two lab periods) Objective: This project will focus on the use of BUT current mirrors to provide the DC biasing for Common Emitter and Common Collector amplifiers, two of the Primary BIT amplifier stages. The design of each amplifer type (CE and CC) to achieve a specific design goal using current biasing willbe examined. The frequency response and feedback adjustments will also be investigated. Components: 2N2222 BIT Introduction: One ofthe primary differences between discrete and integrated amplifier design isthe use of resistors, This change in design approach is based primarily on two major factors. First, resistors require a large amount of semiconductor "real estate, especially when compared to active devices, therefore the use of active devices in place of resistors is desirable. The second fictor relates to the abilty to obtain specific resistance values in the integrated circuits. While very precise resistance ratios can be obtained, processing, fabrication, and material parameters combine to make exact (= 1% tolerance) individual values very dificult and expensive to obtain, These two problems have ead to a change inthe DC bias design for both analog amplifrs and digital circuits, Tis project willexamine the use of BUT current mirror, as discussed in Project 8, to provide the DC bins for a Common Emiter and a Common Collector amplifer. The actual AC amplifier analysis and design is the same for both discrete and integrated circuits with the related change in the biasing network. itp:dhuwutbe. comfengesielectricalneamend VinstuctorNabmenat_ meal tnd 3164Lab Manual Project “The students are referred to Projects 9 and 10 for detailed discussions on the AC analysis of the two amplifier types. A discussion of the changes associated with current biasing will be the focus of this project. Figure 11-1 shows the Common Emitter Amplifier with the biasing current source in the emitter é (fe branch. The collector current is approximately equal to the bias current and basically independent of beta. This removes the need to try and provide a beta stable bias circuit using base resistors in conjunction with an emiter resistor. The designer is then allowed to adjust RBto improve the input impedance without having to worry about the relationship between RE and the base bias network. “The small signal gain for this circuit is: Rg -or bale tae ue (Ralls +7) which shows how RB can be adjusted to improve the coupling of the source signal into the amplifier and thus increase the overall vollage gain. Note that *5 in the gain equation is the effective source resistance of 8s * 502 , Feedback can still be provided by placing a resistor (RE) in series with the current source by-pass capacitor (CE). ‘A Common Collector amplifier with current source biasing is shown in Figure 11-2. The biasing current is again inchided in the emitter branch. The collector current and RB can be adjusted effectively independent ofthe specific transistor beta in order to mect design input, output, and gain specifications. Notice that RE has also been eliminated from the citcuit through the use of current biasing, Again, as in the Common Emitter ampli, the voltage gain for the Common Collector amplifier isa strong fiction of the value chosen for RB. As seen from the smal signal gain equation: R 1 +8) nlltall Re] =| 4 A 8)rall%all de +R = ; (Rolls +r, + (1+ 8)rallall 2s) ‘The gain approaches the theoretical limit of 1 for a lange range of loads when Ry Rs the current source impedance and the transistor output impedance are represented by 101 and 12 respectively in the above equation and s represents the effective source resistance of Rs t 502, hitpukwaumnbhe comienges/electrcallneamenoVinstructorebmervib,-ranual srt aewwe 502 | Me a | | | | | Faneion Conratar RL R Figure 11 - 1: Common Emitter Amplifier with Current Source Biasing I Vcc { 50Q R, pees ae xy | | Taras ‘VEE Functic Gas | Im, x out Figure 11 - 2: Common Collector Amplifier with Current Source Biasing Design: 1. Design a common emitter amplifier as shown in Figure 11-1 with the following specifications: A. use a 2N2222 BIT and a 12 volt DC supply B. midband gain Vo/Vs > 50 C. low cutoff frequency FL between 100 Hzand 200 Hz. D. input impedance as seen by the source > 5 kOQ E. Vo symmetric swing > 2.0 vols peak (4 V p-p) F. ad resistor RL= 1.5 kQ G, source resistance Rs = 50 Q (this is in addition to the function generator’s htp.dwwumbhe confergesielectricalneamend instruct abmen tat) mera tint 364svor01s Lab Menus Project, internal resistance) H. Widlar current mirror to meet bias current specifications. You ‘may assume you have a+ 12 V supply available. 2. Determine the value of RE to place in series with the CE shown in Figure 11-1 in order to provide feedback for the CE amplifer designed in step 1. ‘The new volage gain should be 5 while all other specifications remain unchanged. 3. Design a common collector amplifier as shown in Figure 11-2 with the following specifications: ‘A. we a 2N2222 BIT and a 12 volt DC supply B, midband gain Vo/Vs = 0.7 C. low cutoff frequency FL between 100 Hz and 200 Hz. D. input impedance as seen by the source 2 10 kQ E. Vo symmetric swing 2 3.0 volts peak (6 V p-p) F. load resistor RL= 250 2 G. sourve resistance RS = 50 02 (this is in addition to the fimction generator’s internal resistance) H. Widlar current mirror to meet bias current specifications. You ‘may assume you have a + 12 V supply available. Lab Procedure: (steps 1 and 2 may be omitted if done prior to this lab period and the same BJs are used) 1. From the digital curve tracer, find the value of BDC and AC at the designed Q- point of the CE amplifier. Remember Dc = Ic/IB and BAC = AIC/AIB. How do the two B values compare? 2, Determine the values of hoe and hie from the digital curve tracer. The slope of the transistor IC-VCE curves in the active region is hoe. Find hie by looking at the base- emitter junction as a diode on the curve tracer. The tangent slope of the IB-VBE curve at the 1b point is l/h. 3, Construct the CE amplifier of Figure 11-1 as designed in step 1 of the design section, Remember RS is installed in addition to the internal 50 Q resistance of the function generator. Verify that the design specifications have been met by measuring the Q-point (IC and VE), midband voltage gain, and peak symmetric output voltage swing, Note any distortion in the output signal. 4, Observe the loading affect by replacing RL first by 150 © and then by 15 kQ. Note any changes in the output signal and comment on the loading affect. 5. Use computer control to record and plot the ffequency response. Find the comer frequencies and bandwidth to verify that the design specifications have been met. itpuhauemihe comiengesielectrialinearerotinsructolabmanta manual mel 3464‘8110/2015 hit:mwwanhne comfengesielectricalneamerd Vinstuctrfabearab rental mint Lab Manual Project 6. Measure the input impedance seen by the source (look at the current through Rs and the node voltage on the transistor side of Rs] and the output impedance seen by the load resistor [look at the open circuit volage and the current through and voltage across RL = 1.5 kQ], Verify that the input impedance specification has been met. 7. Now insert the RE determined in step 2 of the design section in series with the by- pass capacitor Cr to forma series-series feedback configuration. Measure the Q- Point and midband voltage gain, Note any distortion in the output signal, 8. Repeat steps 4 - 6, 9. Construct the CC amplifier of Figure 11-2 as designed in step 3 of the design section. Remember RS is installed in addition to the intemal 50 Q resistance of the function generator. Verify the amplifer operation by measuring the Q-point and midband voltage gain. Monitor the output on the oscilloscope to make sure the ‘waveform is not clipped. Note any distortion in the output signal. 10. Adjust the input signal level to get a 3.0 volt peak symmetric output voltage swing 11, Determine the midband current gain IL/Is [measure Is by looking at the current through Rs] What is the overall power gain? 12, Observe the loading afféct by replacing RL fist by ~ 50 © and then by ~ 750.0. Note any changes in the output signal and comment on the loading affect, 13, Repeat steps 5 and 6, Questions: |. Could these circuits be supplied witha current source without using both positive and negative DC sources? Explain your answer, 2. What are the advantages/disadvantages of using a Widlar current mirror instead of ‘one without the RE in the load branch? 3. Why is the current source bypassed for the CE amplifier but not for the CC. circuit? 4. What value of load resistance results in maximum voltage gain? What load resistance results in maximum power transfer to the oad? 5. Compare the Lab measurements for each amplifier to the theoretical predictions (such as those obtained using PSPICER). Note how increasing the feedback in the CE amplifier affects the gain, bandwidth, and input and output impedances. 6. Compare the results of the current gain found in Lab Procedure 11 with the maximum possible gain of B +1, Comment on any differences. 7. What other method could be used to measure Ro for these circuits? 8. Why is the value of FH measured in the lab generally different from (lower than) the value of FH determined using PSPICE® or manual calculations? Project 12erozois Lab hana Pret Cascade Amplifier Objective: This project will show the overall gain, frequency response, and coupling ‘ofa common emitter - common collector cascade amplifier. ‘Components: 2N2222 BIT Introduction: Mulistage amplifiers are made up of single transistor amplifiers connected in cascade. The first stage usually provides a high input impedance to minimize loading the source (transducer). The middle stages usvally account for most ofthe desired voltage gain. The final stage provides a low output impedance to prevent loss of signal (gan) and to be able to handle the amount of current requited by the lad. In analyzing multistage amplifiers, the loading effect of the next stage must be considered since the input impedance of the next stage acts as the load for the current stage, Therefore, the AC analysis ofa multistage amplifr is usually done starting with the final stage. The individual stages are usually coupled by either capacitor or direct coupling. Capacitor coupling is most ofien used when the signals being amplified are AC signals. In capacitor coupling the stages are separated by a capacitor which blocks the DC voltages between each stage. This DC blocking prevents the bias point of each stage from being upset. “The CE-CC cascade two stage amplifiers a good muitistage configuration because the CE and CC amplifiers together provide some very desirable characteristics. The CE amplifier makes up the first stage and is capable of providing high voltage gain. The input impedance ofthe CE isa function of hie (r=) and can be moderately low for high bias currents, but several kilohmss for low current operating points. The output impedance of the CE is approximately equal to Rc, which is usually in the kilohm range. The CC amplifier makes up the second stage and has the characteristic of high input impedance, low output impedance, high current gain, and a less than unity voltage gain Ina cascade configuration, the overall voltage and current gains are given by: AV overall = AV first stage * AV second stage Atoverall= Al fist stage * Alsecond stage Design: 1. Find the overall voltage gain for the CE-CC cascade amplifier using the eircuits fiom either labs 9 and 10, of fiom lab 11. Remember to take into account that the Joad resistances and input impedances are now different for the multistage amplifier. 2, Find a suitable value for C12 to capacitively couple the first and second stages. Think of C12 as an output coupling capacitor forthe first stage and make sure that C12 does not cause a dominant pole by making: Si fase hiipikanunbine.comengesilecricalneamend Vintructlabmenviab anual mt B64sr1ar2015 Lab Mantel Project NOTE: Ci2 Must be Non-polarized Figure 12 - 1: CE - CC Cascade Amplifier | 1 we BSS, +) y, I | Function Tr = Generator in NOTE: C12 Must be Non-polarized Figure 12 - 2: CE - CC Cascade Amplifier with current source biasing Pre-Lab Procedure for Lab 13: (This information is needed for the required Lab 13 designs) Note: ‘The MOSFET ean be easily damaged by static electricity, so careful handling is important 1. Find the value of the threshold voltage Vr and conductivity parameter K from the digital curve tracer (remember the relation ID = K [Ves - Vp in the saturation region). 2. Determine the value of rds from the digital curve tracer. ‘The slope of the transistor ID-Vps curves in the active region is I/ds. !ntpvtummite.comengesilectrcalneamer0 intructorebranab maul rnd m4srr072015 {Lab Manual Projet Lab Procedure: Construct the CE-CC cascade amplifier as shown in Figure 12-1 or Figure 12-2 using the component values from the appropriate CE and CC lab(s) [Projects 9 and 10 or Project 11] along with the value of C12 calculated in the Design section. Make the following measurements. 1. Measure the midband voltage gains Vo1/Vs, Vo/Vi2 for each individual stage and the overall voltage gain Vo/VS for the entire cascade amplifier. Be sure to monitor the output on the oscilloscope to make sure the waveform is not clipped. Compare with the resulis of the previous related lab(s). 2, Measure the input impedance seen by the source and the output impedance seen by the load resistor. See CE and CC lab for measurement method. Compare with the results of the previous related lab(s). 3. Use computer control to record and plot the frequency response of the cascaded amplifier. Find the comer frequencies and banelwidth. 4, Find the maximum, non-distorted output voltage swing. 5, Now, using the same component values, reverse the order of the stages making the CC the first stage and the CE the final stage. You should check the value of C12 since the impedances are changed. Repeat steps 1-4 above. What effect does this stage reversal have? Questions: 1. Compare AVI and AV? to the voltage gains of the previous related lab(s). Why are the gains the same or diferent? 2, Does the cascade circuit of Figure 12-2 require two separate current sources or can it be constructed using one current mirror (Widlar for example) with two load branches? Justify/explain your answer. 3, For the cascade configuration, can the output impedance of the first stage be matched to the input impedance of the second stage when the cascade ampli is a CE-CC? What about for a CC-CE combination? 4, What effect, ifany, would matching the output impedance of stage one with the input impedance of stage two have on the voltage and current gains? Project 13 FET Current Sources Objective: The design of a constant current (independent current source) based on FET operation will be the basis of this project. Limitations on the operation will abo be presented. Components: 2N7000 FET (enhancement) (4) Introduction: ‘The independent current source is one of the basic building blocks in circuit design. This project will Iiipuhwavntie.comengesllectricaneamend instructarlabrenvia_merual nnd saorrozo1s bitphwumbeconvengesielectricaneamend nstructerlabmeeaby anual inl Lab Manu Prcect focus on the operation of two types of FET based current sources as shown in Figures 13-1 and 13-2. These circuits are designed so the current through the “load” is not dependent on the load but rather on the gate-to-source voltages associated with the reference and load branch FETS. The reference branch gate-to-source voltages are a function of the total supplied voltage, the FET parameters and the channel width to channel length (W/L) ratios for the two reference branch FETS, independent of the load being driven. These current sources are generally referred to as Current Mirrors since the current in the load branch effectively mirrors the reference current. The load currents as shown in Figure 13-1 are approximately equal to the reference current when all four FETS are identical while the load current in Figure 13-2 is fraction of the reference current, ‘The transistors are assumed to be matched so variations in the threshold voltage (V'), saturation region coefficient (K), and W/L ratios can generally be ignored in the analysis and design of the current mirrors. ‘The two transistors in the reference branch are connected so the gate-to-source (VGS) and drain- to-source (VDs) voltages are equal. The two FETS are therefore operating in the saturation region since Vs > Vas - VP (remember that VT > 0 for these FETs and Vps = Vos for this configuration). For identical FET devices Vast = Vas2 = - Vss/2 since, by KCL, ID1 = ID2=K (W/L) (Ves - V1)2. Itis interesting to note that the ratio of these two gate-to-source voltages can easily be changed at the time of fabrication by simply changing the channel width of one of the FET devices thereby changing the W/L ratios. The FET in each of the two load branches, in Figure 13-1 has the same gate-to-source voltage as M2 and therefore have the same current as the reference branch since all four FET devices are assumed to be identical. The reference current is therefore mirrored through each load. The load current can be determined as indicated below: a v,) ‘The reference gate-to-source voltages in Figure 13-2 are determined using the same procedure as for Figure 13-1. ‘The load current however, is not equal to the reference current since VGS3 < GS? by lioad RS. It should be noted that the W/L ratios would be changed rather then including an Rs if this current mirror were actually being integrated. A briefexplanation of W{-¥s fat cE the reasoning behind the decision not to integrate a resistor can be found in the infroduetion for Project 11. The load current for Figure 13-2 an be determined using the following two equations: Vesa = Vass * tna Rs 2 Trout = K (Voss ~ Pr) Again, the assumption of effectively identical FETs is employed. The value of Rs can then be determined for specific values of oad current, Parallel load branches can be added in a manner similar to that shown in Figure 13-1 with each load current being different. Notice that the load current(s) for the current mirror shown in Figure 13-2 is (are) always less than the reference current. Design: 1. Verify the operation of the current mirrors shown in Figures 13-1 and 13-2 with PSPICE®. You may represent the load as a positive voltage source in series with a variable resistor connected between ground and the load branch of the current source.shozns biputanwntine.comengesllecricalineamen0 Vintructorabrerviab manual tnd 2b Mania Prcect, 2. Design a current mirror based on the circuit in Figure 13-1 that will supply 10 mA. to a load using the "nominal" specification sheet values of VT and K for each FET if the pre-lab was not completed during Lab 12. Determine any limitations on the load (represented as a resistor in series with a 10 V DC source). Discuss the reason for any limitations, 3. Design a current source illustrated in Figure 13-2 to supply | mA AND 10mA if Rs is bypassed. You should again specify a Vss to achieve the desired currents. You should specify any limitations on your design, ia Toad? Fe Teste Pea boone} Figure 13 - 2: FET Current Mirror with Source resistance Lab Procedure: 1. Construct the current mirror designed in step 2 of the design procedures. Connect the resistance decade box (set to at least | kQ) between the load branch of the current mirror and the positive terminal ofa + 15 V DC source. Vary the decade box resistance between 10 kQ and 0 Q in appropriate steps to plot the load current (Y1 axis) and drain-source voltage (Vs) for M3 (2 axis) versus the load resistance (XLab Manual Project axis). Discuss the results ofthe graphs in terms of circuit operation, limitations, and linearity. Comment on the abilty to use this current mirror as an independent current source. 2. Repeat step 1 using a 220 © load in one branch and the decade box as the load in # parallel branch. Comment on any sinilarties/differences inthe results fiom the two circuits, 3. Construct the current source designed in step 3 of the design section. Comect the resistance decade box (set to at least 1 kQ) between the load branch of the current mirror and the positive terminal ofa + 15 V DC source. Vary the decade box resistance between 10 kO. and 0 0 in appropriate steps to plot the load current (Yi 8x8) and drain source volage (Vs) for M3 (Y2 ans) versus the load resistance (X axis) Discuss the results ofthe graphs in terms of circuit operation, limitations, and linearity. Comment on the abilty to use this current mirror as an independent current source, 4, Install a resistive load (© 1 kQ) in pce of the decade box for the Figure 13-2 current mirror. Set the decade box resistance to the value of RS from step 3 of the design section. Vary the decade box resistance as appropriate to verify thatthe maximum current through the resistive load can ‘increase to 10 mA, Plot the results; Tload on the Y1 axis and Vps3 on the Y2 axis versus the decade box resistance. Are the graphs as predicted by the design equations? Comment on the similarities/differences between the theoretical and experimental results, Questions: 1. Discuss some of the limitations placed on the number of parallel branches that can be added. Is there a limit since the ‘gates effectively do not draw any current? 2. In the current source illustrated in Figure 13-2, can you assume the load FET is always saturated? Explain your answer. 5. The loads for these experiments were illustrated using resistances. What other devices/citeuits/systems would be valid loads? What ones would not make valid Joads? Discuss the justification for your answers. 4. How would you determine the resistance" of each ofthe two current mirrors (Single load branch with and without Rs) as seen by the ad? Would a high or bw Source (current mirror) be most beneficial? Explain your answer, 5. Discuss some ofthe limitations placed on the load and load source for proper Surrent source operation. Are there limits on the load resistance if the load source is + 15 V? Explain your answers, Project 14 MOSFET Amplifiers Objective: This project willshow the biasing, gain, ffequeney response, and ‘mpeclance properties of te MOSFET common source and common drain amplifes, !ntoulwawu mbt comenges/tectrcalreamend Vinetructer brent, menual ind atisrro015 Lab Manus Project ‘Components: 2N7000 MOSFET Introduction: ‘Two ofthe most popular configurations of small-signal MOSFET amplifiers are the common source (CS) and common drain (CD) configurations. These two circuits are shown in Figures 14-1 and 14-2 respeotively. The common source and common drain amples, Ike all MOSFET amplifers, have the characteristic of high input impedance. The value ofthe input impedance for both ampliers i basicaly ited only by the biasing resistors RoI and RCD. Vales Of ROI and RG are usually chosen as high as possible to keep the input impedance high. High input impedance is desirable to keep the amplifier from loading the signal source. One popular biasing Scheme for the CS and CD configurations consists ofthe voltage divider Ro! and Ree. This voltage divider supplies the MOSEET gate with a constant DC vokage. This is very similar to the BJT biasing arangement described in Project 9, The main diference with the BIT biasing scheme & that ideally no current flows from the volage divider into the MOSFET. “The CS and CD MOSFET amplifiers can be compared to the CE and CC BIT amplifiers respectively. Like the CE ampiir, the CS amplifier has a negative volage gin and an outpyt impedance approximately equa othe drain resistor (collector resistor for the CE amplifier). The CD amplifier is comparable to the CC amplifier with the characteristics of high iput impedance, ‘ow output impedance, and less than unity vollage gain. The comer frequencies of the CS and CD fequency response can ako be approximated using the short circuit and open circuit ine constant ethods described in Project 9. A comparison of the smal signal model for the BIT (Figure 9-1) tind the FET (Figure 14-3) shows the similarity between the two devices in terms ofthe small signal analysis modeb. ‘The 2N7000 MOSFET used inthis project i a n-channel enhancement-type MOSFET. For the cnhancement-type MOSFET, the gate to source voltage must be positive and no drain current will flow until Vos exceeds the positive threshold voltage VT. VT is a parameter of each particular MOSFET and is temperature sensitive. Ths parameter sensity to temperature js one reason for establishing stable DC bias. The 2N7000 MOSFET data sheet fists the minimum and raaxtmurn values of VT as 0.8 V and 3.0 V respectively. Design: Design a common source amplifier as shown in Figure 14-1 with the folowing specifications: 1. use a 2N7000 MOSFET and a 20 volt DC supply 2, midband gain VorV1 2 6.0 3. low cutoff frequency FL < 100 Hz 4. Vo symmetric swing > 3.0 volts peak (6 V p - P) 5. load resistor RL= 5 kQ. 6, source resistance Ri = 50 Q. (this is in addition to the Tektronix fimction generator's. internal resistance) Design a common drain amplifier as shown in Figure 14-2 with the following itpuhwawebhe confengcsielectrcalinearerdtfinstructortabranvib,rranual mtn metaroaors Lab Manna Project specifications: 1. use a 2N7000 MOSFET and a 20 volt DC supply 2. midband gain Vo/V1 > 0.5 3. low cutoff frequency FL < 100 Hz 4. Vo symmetric swing > 5.0 volts peak (10 V p - p) 5, load resistor RL= 200 Q 6. source resistance RI = 50 Q (this is in addition to the Tektronix fiction generator’s internal resistance) pp Ra Bb ‘t 7 i out 308 Rr + Y, Rar Function |g = | Generator in R Figure 14 - 1: Common Source MOSFET Amplifier pp Ror I 50Q R, “i Vout © oe Fi, Function | |p Generator in Figure 14 - 2: Common Drain MOSFET Amplifier np mine.comengcsietectricaloeamend instructor labreviab_manval ntl 464srro2018 Lab Manual Project wel Figure 14 - 3: Small Signal FET Model Lab Procedure: (steps 1 & 2 may be omitted if done prior to this lab period and the same FET is used) Note: The MOSFET can be easily damaged by static electricity, so careful handling is important 1. Find the value of the threshold voltage Vir and conductivity parameter K from the digital curve tracer (remember the relation ID = K[VGs - Vi] in the saturation region). 2. Determine the value of rds fiom the digital curve tracer. The slope of the transistor ID-VDS curves in the active region is 1/ras. 3. Construct the CS circuit shown in Figure 14-1. Remember RI is installed in addition to the internal 50 resistance of the function generator. 4. Verify that the specifications have been met by measuring the Q-point, midband voltage gain, and peak symmetric output voltage swing. Note any distortion in the output signal 5. Adjust the output signal to obtain the maximum, non-distorted output voltage swing. Is the design specification met? 6. Observe the loading affect by replacing RL frst by 500 Q and then by 25 kQ. Note any changes in the output signal and comment on the loading affect. 7. Use computer control to record and plot the frequency response. Find the comer frequencies and bandwidth to verify that the specifications have been met. 8. Measure the input impedance seen by the source [look at the current through RI and the node voltage on the transistor side of Ri] and the output impedance seen by the load resistor [look at the open circuit voltage and the current through and voltage across RL]. Verify that the input impedance specification has been met. 9, Construct the CD circuit shown in Figure 14-2. Remember Rl is installed in addition to the internal 50 resistance of the function generator. 10, Repeat steps 4-8 Questions: 1. Compare the gain, frequency response, input impedance, and output impedance of hiipuimumbie.comengesilectricalnearen0 instructor abreviab_manual tnd aaaere Lab Manual Project the CS amplifier with the results from the CE amplifier. Compare the CD amplifier with the CC amplifier. Comment on the differences/similarities, Project 15 MOSFET Amplifiers with Current Source Biasing Objective: This project wil focus on the use of FET current mirrors to provide the DC biasing for Common Source and Common Drain amplifiers, two ofthe primary FET amplifier stages. The design of each amplifier type (CS and CD) to achieve a specifi: design goal using current biasing will be examined. The frequency response and feedback adjustments will also be investigated Components: 2N7000 FET Introduction: One ofthe primary dffrences between discrete and integrated amplior design, as mentioned in Project 11, isthe use of biasing resistors. The savings in ‘Semiconductor real estate” s even more dramatic when the resistor area is compared to that ofthe active FETs. The abilty to easily change the W/L ratios for the FETs used in the current source (see Project 13 for additional discussion) overall process. Ths "side elect" makes FET based current sources well sited for integrated Citeuis since the FETs are used for the entre source. Ths project willexamine the use of an FET Curent mitror, as discussed in Project 13, to provide the DC bias for a Common Source and a Common Drain amplifier The actual AC amplifer analysis and design isthe same for both disorete and integrated circuits once the related changes due to the new biasing network have been incorporated. The students are referred to Projects 9 and 10 for detailed discussions on the AC analysis ofthe single transistor ampli types. A discussion of the changes associated with curent biasing will be the focus of this project, Fieure 15-1 shows the Common Source Amplifer withthe biasing current source inthe source branch, The drain curent is equal tothe bins current since there is no gate curen for the FET and it therefore independent ofthe transistor device related parameters such as Vr and K. This independence removes the need to try and provide a stable bis circuit using gate resistors in conjunetion with a souree resistor. The designer is then allowed to adjust RG to improve the input ‘impedance without having to worry about the relationship between RS and the gate bias network or the dissipation power associated with very lange gate resistors, The small signal gain for this circuit is: which shows how RG can be adjusted to improve the coupling of the source signal into the ampliier and thus increase the overall voltage gain, Note that 7 inthe guin equation s the effective source resistance of 8s * 508 Feedback can still be Provided by placing a resistor (Rs) in series with the current source by-pass capacitor (Cs), /p:uwearbe.coneng csllecicalheemenO instructor tatmanteb_ manuel! 45164vro01s Lab Manual Preect, 'A-Common Drain amplier with current source biasing is shown in Figure 15-2. The biasing current is agnin incnded inthe source branch. The drain curent and RG can be adjusted effeetively independent of te specific transistor parameters in order to meet design input output and gain specifications. Notice that RS has also been eliminated from the circuit through the use of current biasing. Again, as in the Common Source ampli, the voltage gan forthe Common Drain ampifir i a strong finction ofthe value chosen for RG. As seen from the smal signal gain equation: R avait [23 tk, i. " (1+ gq allradl Rs) the voltage gain approaches the theoretical limit of 1 for a large range ofloads when 8 @ >? 8x. ‘The eurent source impedance and the transistor output impedance are represented by ras} and rds? respectively in the above equation and Rr represents the effective source resistance of R, +502, Function |p Generator in Rout Figure 15 - 1: Common Source Amplifier with Current Source Biasing ¥N LAWA— | Function | Generator in Resi Figure 15-2: Common Drain Amplifier with Current Source Biasing Design: htp:twawmbhe.confengcsielecrcalfneamen0 fintructoriabraiiab, manual rtrd a6beha ares 6 Lab Manual Project |. Design a Common Source amplifer as shown in Figure 15-1 with the following specifications: A. use a 2N7000 MOSFET and a 20 volt DC supply B. midband gain Vo/Vs > 6.0 C. low cutoff frequency FL between 100 Hzzand 200 Hz D. input impedance as seen by the source > 20 kQ E. Vo symmetric swing > 3.0 volts peak (6 V p - p) F. load resistor RL = 5 kQ. G. source resistance Ri = 50 Q (this is in addition to the function generator's internal resistance) H. FET current mirror to meet bias current specifications. You may assume you have a + 20 V supply available. 2, Determine the value of RS to place in series with the Cs shown in Figure 15-1 jn order to provide feedback for the CS amplifier designed in step 1. The new vollage gain should be 2 while all other specifications remain unchanged. 3. Design a Common Drain amplifier as shown in Figure 15-2 with the following Specifications: A. use a 2N7000 MOSFET and a 20 volt DC supply B, midband gain Vo/Vs > 0.7 C. low cutoff frequency FL between 100 Hz and 200 Hz D. input impedance as seen by the source > 10 kO E. Vo symmetric swing > 5.0 vols peak (10 V p-p) F, load resistor RL = 200 G. source resistance Ri = 50 © (this is in addition to the function ‘generator’s internal resistance) H. FET current mitror to meet bias current specifications. You ‘may assume you have a +t 20 V supply available, Pre-Lab Procedure for Lab 16: (This information is needed for the required JFET amplifier design) 'pulwmumbbe comiengcselectrcalheemen0 estructorabmarvabrranuol hind atH84ara01s Lab Manu Project 1. Find the value of the threshold voltage VP and Ipps from the digital curve tracer. 2, Determine the value of ro from the digital curve tracer. The slope of the transistor ID-Vps curves in the active region is 1/to, Lab Procedure: (steps 1 & 2 may be omitted if done prior to this lab period and the same FET is used) Note: ‘The MOSFET can be easily damaged by static electricity, so careful handling is important 1. Find the value of the threshold voltage Vr and conductivity parameter K. from the digital curve tracer (remember the relation Ib = K [Vas - Vr} in the saturation region). 4, Determine the value of rds from the digital curve tracer. The slope of the transistor Ib-Vbs curves in the active region is I/tds 3, Construct the CS circuit shown in Figure 15-1. Remember, RI is installed in addition to the internal 50 Q resistance of the function generator. 4, Verify that the specifications have been met by measuring the Q-point, midband Voltage gain, and peak symmetric output voliage swing, Note any distortion in the output signal, 5, Adjust the output signal to obtain the maximum, non- 6.0 3. low cutoff frequency FL < 100 Hz, 4. Vo symmetric swing 2 3.0 volts peak (6 V p - p) 5, load resistor RL= 5 kQ 6. source resistance RI = 50 Q (this is in addition to the Tektronix function generator's internal resistance) Design a common drain amplifier as shown in Figure 16-2 with the following specifications: 1.use a 2N5951 JFET and a 20 volt DC supply 2, midband gain VolVi > 0.5 3. low cutoff frequency FL< 100 Hz 4. Vo symmetric swing > 1.0 volt peak (2 Vp - p) 5. load resistor RL = 250. 6. source resistance RI = 50 © (this is in addition to the Tektronix function generator's internal resistance) ntpuhwuuarhe.comlengcslelctricalnearend instructor labranfay manual mbt S068eri0n0%5 ‘Lab Manual Project | 300" | yy | My | | Function. | . = Generator i “sidraaie Raul Bias Figure 16 - 1: Common Source JFET Amplifier Yop | 300" | Yop 7 | | Ry | | IN Function | : Generator ae Reg ‘Bias Figure 16 - 2: Common Drain JFET Amplifier co, pp Rp ‘Vout 502 ee O» Function | = Generator Figure 16 - 3: Sawtooth Waveform Generator Lab Procedure: (step 1 may be omitted if done prior to this lab period and the hipahwwumhne.comfengesiolectricalineamend instructerabmerab eral rid S164072015 Lab Manus Prefect, same JFET is used) 1. Find values for the parameters VP and IDss from the digital curve tracer, Determine the value of rds ftom the digital curve tracer. The slope of the transistor ID-Vbs curves in the active region is I/rds. 2. Construct the CS circuit shown in Figure 16-1. Remember, RI is installed in addition to the internal 50 © resistance of the function generator. 3. Verify that the specifications have been met by measuring the Q-point, midband voltage gain, and peak symmetric output voltage swing. Note any distortion in the output signal. 4. Adjust the output signal to obtain the maximum, non-distorted output voltage swing Is the design specification met? 5. Observe the loading affect by replacing RL. first by 500 Q and then by 25 kQ. ‘Note any changes in the output signal and comment on the loading affect. 6. Use computer control to record and plot the frequency response. Find the comer frequencies and bandwidth to verify that the specifications have been met. 7. Measure the input impedance seen by the source [look at the current through RI and the node voltage on the transistor side of Ri] and the output impedance seen by the load resistor (look at the open circuit voltage and the current through and voltage across RL]. Verify that the input impedance specification has been met. 8. Construct the CD circuit shown in Figure 16-2. Remember RI is installed in addition to the internal 50 © resistance of the function generator. 9. Repeat steps 3-7. 10. Construct the sawtooth waveform generator of Figure 16-3. Use a square wave with an upper limit of 0 V and a lower limit of - 1.5 | VP at a frequency of 1 kHz for the input signal. Use Vp = 20 V. To begin with, use RD = 10 kQ and C = 100 nF. Observe the linearity of the output waveform. Questions: 1. Compare the results ofthe input and output impedance measurements with the those of the MOSFET lab (Project 14). Discuss any differences and/or similarities. 2. Would the amplifier circuits shown work if RS were replaced by a short? Why or why not? 3. Could you design a bias without Rs using only a single polarity power supply? Exphin, 4, What affect do the values of C and R in the sawtooth circuit have on the output waveform? What afféct does the input squarewave have on the output? Project 17 Differential Amplifiers itv nite comfengesieectricalineamerO instructor abana manual tind 5264srr02015, tptowzmnhite.comengesilectrica/neamend instructor Rabe ia_manual mbm Leb Manual Project Objective: This project will focus on single stage differential amplifiers. Both BIT and FET amplifiers will be examined as will the use of resistor and current source biasing. ‘Components: 2N2222 BJT, 2N7000 FET Introduction: The operational amplifier has had a dramatic impact on electronic circuit design, both analog and digital, over the last 25 years. While the complexity, speed and capability of the Op-Amp have changed dramatically over this time, the basic operation still depends heavily on the input differential amplifier stage. It is this differential amplifier stage that will be examined in this project. The differential amplifier is designed to effectively shift a constant current between two branches as a fiction of the difference between the two input signals. Ideally, as a result of the changing current, the amplifier output reflects only the difference between the inputs. The quality for the amplifier design is determined, in part, by examining the output of the differential amplifier under two specific input conditions. The ratio of the differential mode voltage gain [ADM] (inputs are equal in ‘magnitude and opposite in sign) to the common mode voltage gain [ACM] (both inputs are equal) is used to determine the Common Mode Rejection Ratio (CMRR). The higher the ratio, the better the differential amplifier stage is able to discriminate between the actual difference in the signals present at the two input terminals. The input impedance is another important measure of the quality of the differential amplifier stage. These two items, CMRR and Zin, will be the primary focus of this project. Figure 17-1 illustrates a BIT based differential amplifier and Figure 17-2 shows an FET based stage. The differential output versions (Figures 17-1 (A) and 17-2 (B)) have a resistor in each branch and the output is measured between the two collectors (drains). Many differential amplifiers are designed as single ended outputs since the information contained in either of the collector (Grain) terminals is sufficient to determine the differential input, Figures 17-1 (B) and 17-2 (B) illustrate the single ended designs. In the single ended case one of the branch resistors (Ri for example) is removed and replaced by a short circuit. The determination of the non-inverting (VP) and inverting (VN) input terminal is made by looking at the relationship between a change on the input terminal and the corresponding change in the output voltage. The non-inverting terminal causes an increase in the output voltage for an increase in the input signal. There is a 180° phase shift between the inverting input signal change and the output signal change. The current source illustrated between each diagram is generally implemented using an appropriate BJT or FET current mirror, A discussion of current mitrors can be found in Projects 8 and 13. The use of a resistor in place of the current mirror is also used to provide an approximately constant current source, Both types of current supplies will be investigated in this project.“A @) Figure 17 - 2: FET Differential Amplifier Design: 1. Design a single ended BIT differential amplifier capable of providing a + 10 V output swing across a 1 kQ resistor using + 15 V DC power supplies. The switching current should be supplied by a BJT current mirror, Indicate the value of Vout when both inputs are grounded. Verify your design PSPICE®. 2. Repeat step 1 using a single resistor to provide the switching current. 3. Design a single ended FET differential amplifier capable of providing a + 5 V output swing across a 1 kQ resistor using + 15 V DC power supplies. The switching curent should be supplied by an FET current mirror. Indicate the value of Vout when both inputs are grounded. Verify your design PSPICE®. itpuhwumihe.comfengesielectricalinearerO ‘inet uctoriabraviab_ manual mbit 5484a10/2015 Lab Manual Project 4, Repeat step 3 using a single resistor to provide the switching current . Lab Procedure: 1. Construct the differential amplifier designed in step 1 of the design procedures. Verify the circuit operation with both inputs grounded. Be carefil in making voliage ‘measurements so as not to effectively by-pass your current source. 2. Apply a differential voltage signal (Vx) to each input. The individual input voltages should be equal in magnitude but opposite in polarity. Measure the output voltage and determine the differential mode voltage gain (ADM), Measure the input current for terminal and determine the effective input impedance as seen by the total differential input voltage (2VX), Be carefil not to over drive the amplifier, 3. Apply a common mode signal (equal magnitude and same polarity) to the two inputs. Adjust your common mode voltage to the total differential voltage used in step 2 (2 Vx). Measure the output voltage and determine the common mode voltage gain (AcM). Again, be careful not to overdrive the amplifier. Determine the input impedance for this input condition. Compare this input impedance with the impedance determined in step 2. Discuss possible causes for any differences between the two values, 4. Determine the CMRR (ADM/ACM) for the amplifier 5. Reverse the polarities on the inputs for steps 2 and 3 and determine the differential ‘mode gain, common mode gain, and CMRR for the revised inputs. Comment on any similarities and/or differences, 6, Repeat steps 2 - 5 for each of the other three differential amplifier designs, 7. Prepare a summary of the various measurements and resuits for all the tests. Analyze the summary data and provide a brief discussion of the differences/similarites between the various designs. Questions: 1. Could any, or all, ofthese circuits be designed using a single DC power supply? Explain your answer. 2. What, ifany, imitations are there on the value of the common mode signal? Are they different for the amplifiers designed using a current source when compared to those using a single resistor for the current supply? 3. Are the two voltage gains, ADM and ACM affected by the value of the input voltages used? Explain your answer. 4. Is the input impedance affected by the decision to use a current mirror versus the single resistor? Ifso, how can the difference be explained? 5. Comment on the benefitdisadvantage of using an FET current mirror for the BJT based differential amplifier. Repeat for the reversed situation, 6. Discuss the benefits/disadvantages of the single ended output versus the differential puto tho comiengestelectrcalneamend Vinetructer labret merual tim) soreerro015 hitpukwaumtbe, comenges/electsicalnearen0instructrtabrenvidb_manuol til Lab Manual Project output designs. Project 18 Sinusoidal Oscillator Objective: This project will demonstrate the basic operation and design of a Wien bridge RC oscillator. Components: 741 op-amp, IN4001 diode(2) Introduction: “An oscillator isa circuit that converts a DC input to an AC output. This project investigates sinusoidal output oscillators. Sinusoidal oscillators consist of an amplifier in a positive feedback loop with a frequency selective network (Figures 18-1 and 18-2). The amplifier ean be a transistor amplifier or an operational amplifier. The frequency of the oscillator is determined by the frequency selective network. The criteria for an oscillator to produce sinusoidal oscillations is that the ‘magnitude ofthe loop gain equal unity and the phase of the loop gain equal zero at the frequency selected for oscillations. ‘An oscillator with a loop gain of exactly unity is unrealizable because of varying component values, parameters, and temperatures. To keep the oscillations from ceasing or increasing, a nonlinear circuit can be used to control the gain and force the loop gain to remain at unity. The Wien bridge oscillator of Figure 18-2 uses two diodes in the circuit to limit the amplitude of the oscillations. “The Wien bridge oscillator without amplitude stabilization is shown in Figure 18-1. Wien bridge oscillators are noted for high stability and low distortion. This oscillator will oscillate at the frequency: 1 2aRC t= when: Fenn & For oscillations to start, the value R2/R1 should be made slightly greater than 2.0. These relations also hold for the Wien bridge oscillator with amplitude stabilization shown in Figure 18-2. Design: Design the Wien bridge oscillator shown in Figure 18-1 with an oscillation frequency in the range of 1.9 kHz and 2.1 kHz. Use £15 V supplies for the op-amp. Verify your design with PSPICE®,ert02015, Ry out c= BR Figure 18 - 1: Wien Bridge Oscillator zi N Vi 10kQ. 10kQ 10kQ 10kQ Dz Figure 18 -2: Wien Bridge Oscillator with Amplitude Stabilization Lab Procedure: 1. Construct the Wien bridge oscillator circuit of Figure 18-1. Use the designed values {or the resistors and capacitors. Use +15 V supplies for the op-amp. 2. Monitor the output on the oscilloscope. Observe any distortion in the output waveform or ifthe output oscillations begin to increase without bound. If oscillations do not start, try increasing the ratio R2/R1 to slightly greater than 2.0. This can be _nipuhmwwmtne comlengesllectricalineamen instructor manual mbtml Sti681102015, Lab Menuet Project done easily ifyou use a decade resistance box for R2, Ifoscillations increase without bound, try getting the ratio R2/RI closer to 2.0. 3. Determine the ffequency of the oscillations, What is the peak amplitude of the oscillations? Measure the actual values used for R1 and R2. Remember they must be measured outside of the circuit. 4, Now add the amplitude stabilization circuit to construct the Wien bridge oscillator of Figure 18-2. Be sure to connect the 10 kQ potentiometer correctly, 5. Before applying power to the circuit, adjust the pot to the bottom of ts range. Tum the power on, and while monitoring the output waveform on the oscilloscope gradually increase the pot setting until sustained oscillations occur. Note the changes in the output waveform amplitude and shape during the pot's adjustment. 6. Determine the frequency of the oscillations. What is the peak amplitude of the oscillations? Note any distortion in the output sine wave. Questions: 1. Why isn't an input volage source needed to obtain an output voltage? 2. Compare the operation of the two Wien bridge oscillator circuits. Comment on differences and similavites. Justify your answers. 3. Write the nodal equations for the oscillator circuit of Figure 18-1. Show how the oscillation frequency is determined. Project 19 Push-Pull (Class AB, B) Amplifiers Objective: This project will investigate the operation of a push-pull amplifer. Class B and Class AB operation will be examined. Components: 2N2222 BIT, 2N2907 Introduction: Many strall signal amplifiers, both BJT and FET, are biased to provide symmetric output voltage swings. This bias arrangement, as examined in many of the previous projects, requires a DC collector (drain) current and a DC collector-emitter (drain-source) voltage even when no input signal is being amplified. The product of this bias current and voltage results inthe transistor dissipating power at all times: The class of amplifiers that have a continuous power dissipation are referred to as Class A amplifiers, The Push -Pull ampliferilustrated in Figure 19-1 is referred to as a Class B amplifier since the transistors are off unless an input signal is present and there is one transistor used for positive and one transistor used for negative output voltage swings. In this arrangement, there is no DC power dissipated by the transistor. The transistors illustrated in Figure 19-2 have a very small bias applied to the each base to improve the linearity of the amplifier and teduce crossover distortion. This type of arrangement is referred to as Class AB since it has characteristics of both Class A and Class B amplifiers. There are many additional amplifier classes including C, D, E, F, G, H, and S, each of which is designed for specific operating conditions. The _ntpihwwin mite comiengesieecticalineamerO instructor labrenfab marta mbt sa168sroo1s hitphwwnmbe.comlengesielectricalneamen0 Vist ucterabmariab manual sind Leb Manual Peoect majority of these additional amplifier types rely on frequency dependent input and/or output matching networks for proper operation and are beyond the scope of this project. The operation of the Class B and Class AB amplifier will be the focus of this project. ‘The Push-Pull amplifier is designed to provide large output voltage swings and power gain. The two transistors are arranged to allow one (NPN) to provide the current drive for positive swings and the other (PNP) to provide the drive for the negative swings, The NPN transistor is said to Source current while the PNP is said to Sink current. This Source-Sink relationship leads to the designation as a Push (source) - Pull (sink) amplifier. The circuit in Figure 19-1 requires a non-zero input signal (~ VBE(on)) to be present before either transistor turns on, This resus in a distorted output signal since there is no output signal when the input signal is between ~ - 700 mV and = + 700 mV. The non-linearity (distortion) in the output signal is referred to as Crossover Distortion since it occurs when the input signal crosses over from positive to negative or negative to positive. ‘The amplifer shown in Figure 19-2 is designed to prevent the crossover distortion by maintaining the two transistors at the Edge of Conduction (EOC). Ideally, this arrangement allows each transistor to respond to any non-zero input. The actual design however usually aims to maintain the two transistors in a slightly forward biased operating state, Since each transistor has a small DC bias it will dissipate a small DC power even in the absence of an input signal. The Class AB designation is a consequence of this power dissipation. Care must be taken in the Class AB design not fo have a large "reverse" crossover distortion by having both transistors operating for a given input signal. Yoo | | | I yo | | BL Function | Ver Generator R Figure 19 - 1: Class B Push-Pull AmplifierLab Manual Project Wee ¥ Function Generator out 502 ly ? Vou R, Vv. Figure 19 - 2: Class AB Push-Pull Amplifier Design: 1, Design a Class B amplifier as illustrated in Figure 19-1 that can drive a 2 kQ load with a& 10 V output swing. Determine the gain for the amplifier. You may assume you have between + 15 V and + 20 V power supplies available. Verily your design using PSPICER. 2, Repeat step 1 for the Class AB amplifier illustrated in Figure 19-2. You may use 400 Q as a starting point for the value of R. Be careful in your PSPICE® analysis to use a diode that can handle the DC current, Lab Procedure: 1, Construct the amplifier designed in step 1 of the design procedure. Verify proper operation of the design. 2. Determine the amplifier voltage, current, and power gains along with the maximum. symmetric (effectively) output swing possible for your design. 3. Adjust the input signal to produce a 5 V peak output wave and measure the crossover distortion in terms of input voltage levels and the phase angle(s) over which the output wave is zero. Repeat for a 2 V peak output wave. 4, Observe the loading affect by replacing RL. first by 150 © and then by 15 kQ. Note any changes in the output signal and comment on the loading affect. 5. Use computer control to record and plot the frequency response. Find the comer frequencies and bandwidth. 6. Measure the input impedance seen by the source [look at the current ffom the function generator and the node voltage at the base of the transistors] and the output impedance seen by the load resistor [look at the open circuit voltage and the current ntpuhwuumbe.comlengcsielecticalneamend instructorlabrenlab_mankal mbt encenos Lab Manual Project through and voltage across RL= 2 kQ]. 7. Repeat steps | - 6 for the Class AB amplifier designed in step 2 of the design procedure, Questions: 1. Compare the output waveforms for the two circuits and discuss the similarities and differences especially in terms of crossover distortion, 2. The two designs do not have input or output coupling capacitors. Why are they omitted from these designs? Would the operation be improved ifthey were inchded? 3. Could either (or both) of these amplifiers be designed using a single power supply? Justify your answer. 4. Do the two transistors have to be "matched, ie, equal device parameters such as B and Vie(on), to operate properly. Explain your answer. Project 20 BJT/FET Cascade Amplifier Objectives This project will show the overall gain, frequency response, and coupling ofa common emitter - common source cascade amplifier. Components: 2N2222 BIT, 2N7000 Introduction: Muktistage amplifiers are made up of single transistor amplifiers connected in cascade. The first stage usually provides a high input impedance to minimize loading the source (transducer). The middle stages usually account for most of the desired voltage gain. The final stage provides a low output impedance to prevent loss of signal (gain) and to be able to handle the amount of current required by the load. In analyzing multistage amplifiers, the loading effect of the next stage must be considered since the input impedance of the next stage acts as the load for the current stage. Therefore the AC analysis ofa muktistage amplifier is usually done starting with the final stage. The individual stages are usually coupled by either capacitor or direct coupling. Capacitor coupling is most often used when the signals being amplified are AC signals. In capacitor coupling the stages are separated by a capacitor which blocks the DC voltages between each stage. This DC blocking prevents the bias point of each stage from being upset. ‘The cascade amplifier examined in this lb consists ofa BUT common emitter stage and an FET common source stage, The high gain capabilty of BIT based CE stage and the high input impedance of the FET based stage makes the FET/BIT cascade combination a good possibilty for the input section of a high gain system, The effect of the order of the two stages on input and output ‘impedances, overall voliage, current, and power gains, and frequency response will be specifically examined in this project. The CE amplifer stage is capable of providing high voltage gain. The input impedance of the CE is a function of hie (te) and can be moderately low for high bias currents, but several kilohms for low current operating points, The output impedance of the CE is approximately equal to Re, which is usually inthe kilohm range. ‘The CS has the characteristic of high input impedance, high current gain, and a relatively low voltage gain, btipahwumtive convengesielectricalneamen0 Vinetructeriebrarvib_srenualnbnd e164srr02015 Lab Manuel Project Ina cascade configuration, the overall vollage and current gains are given by: AVoverall= AV fist stage * AVsecond stage Aloverall = Al first stage * Af second stage Design: 1. Using the CE amplifier from either Project 9 or 11, and the CS amplifier, from either Project 14 or 15, find the overall voltage gain for the CE-CS cascade amplifier ilustrated in Figure 20-1. You should look at the individual stages with and without feedback in determining the gain possibilities. Remember to take info account that the Joad resistances and input impedances are now different for the multistage amplifier. 2. Find a suitable value for C12 to capacitively couple the first and second stages. Think of C12 as an output coupling capacitor for the first stage and make sure that C12 does not cause a dominant pole by making: ck faig 3, Repeat steps 1 and 2 for a CS-CE cascade arrangement. Nec Vina He ‘Active Device JU i ‘Active Device 63 El Grrecter le berrermar toy ope Vout 2 (iC SS e Network Network 5 oot ee To Ground or Vig ‘To Ground oF Vi Funct wep TT, ze NOTE: C12 Must be Non-polarized Figure 20 - 1: CE - CS Cascade Amplifier Lab Procedure: Construct the CE-CS cascade amplifier as shown in Figure 20-1 using the component values from the appropriate CE and CS earlier Lab Projects along with the value of C12 calculated in the Design section, Make the following measurements. 1. Measure the midband voltage gains Vo1/Vs, Vo/Ve for each individual stage and the overall voltage gain VO/VS for the entire cascade amplifier. Be sure to monitor the pub eh comlengcsleoctricalnearer0 instructor labranfas_manwal. mbt earssrr02018 Lab Manu Project output on the oscilloscope to make sure the waveform is not clipped. Compare with the results of the previous related lab(s). 2, Measure the midband current gains Io1/Is, 1o/l2 for each individual stage and the overall current gain Io/Is for the entire cascade amplifier. Be sure to monitor the output on the oscilloscope to make sure the waveform is not clipped. Compute the overall power gain for the cascade combination. 3. Measure the input impedance seen by the source and the output impedance seen by the load resistor. See CE and CS kab for measurement method. Compare with the resuits of the previous related lnb(3) 4. Use computer control to record and plot the frequency response of the cascaded amplifier. Find the comer frequencies and bandwidth. 5. Find the maximum, non-distorted output voltage swing. 6. Now, using the same component values, reverse the order of the stages making the CS the first stage and the CE the final stage. You should check the value of C12 since the impedances are changed. Repeat steps 1-5 above. What effect does this stage reversal have? Questions: 1. Compare Avi and AV2 to the voltage gains of the previous related lab(s). Why are the gains the same or different? 2. For the cascade configuration, can the output impedance of the first stage be ‘matched to the input impedance of the second stage when the cascade amplifier fs a CE-CS? What about for a CS-CE combination? 3. What effect, ifany, would matching the output impedance of stage one with the input impedance of stage two have on the voltage and current gnins? 4, How did the measured results compare with those determined in the Design section? Explain any differences. 5, Discuss the advantages/disadvantages ofa FET/BJT cascade amplifier compared to a BJT/BIT or FET/FET cascade combination. Carbon Film % Watt Resistors a | 1002 1kQ 10ka 100 ka foe 129 1202 1.2kQ 12kQ 120kQ. 1sQ 1500 1.5kQ 15kQ [se 182 180 1.8kQ | 18k. 180 kQ. | 222 | 2200 2.2kO 22kQ 220 kQ 1 ipihwnrbbe confengeselecrcalneamend Vnstrucerilebrenviae_manual bl11072015, Lab Manual Project 272 [2702 2.7kQ 27kQ 270 kQ 332 3302 3.3kQ 33 kQ. 330 kQ 392 3902 3.9kQ, 39kQ. 390 kQ 470 4702 4.7kQ 47kQ. 470 kQ js 560.2 5.6kQ 56kQ 560 kQ 682 680.2 6.8kQ 68kQ 680 kQ 8202 8209 1 8.2kO 82kQ 820kQ | | 1MQ | Lo Ceramic Disk Capacitors 10 pF 100 pF 4.7 nF (0.0047 wF) 22 pF 220 pF 10 nF (0.01 pF) 39 pF 390 pF 22 nF (0.022 uF) 47 pF 470 pF 47 nF (0.47 pF) [# = 1 68 pF 1 nF (0.001 uF) 100 nF (0.1 uF) Electrolytic Capacitors luF 100 uF 10 pF 220 pF Back feedback form | permissions | intemational | locate vour campus rep | request a review copy dlaital solutions | publish with us | customer service | mhhe home Copyright ©2001 The McGraw-Hill Companies. Any use Is subject to the Terms of Use and Privacy Polley. McGraw-Hill Higher Education Is one of the many fine businesses of the The McGraw-Hill Companies, !nipuhwwmnmbbe.comengcs/etecticalneamend instuctarlabmavlab_ manual hen