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CURRICULUM VITAE

SAURABH DWIVEDI
MODEL DESIGN ENGINEER-2
ARM
BANGALORE, INDIA

SAURABH DWIVEDI
Phone: +919901306802
E-mail: saurabhdwivedi87@gmail.com

CAREER SUMMARY
1.

Overall 4+ years of experience in VLSI industries on SPICE modeling, post-layout


extraction, Reliability analysis for circuits, DRC/LVS & characterization.

2.

Expertise includes Generation of layouts & Spice Modelcard(BSIM & BSIM-CMG), RC


extraction, Model QA & Circuit level Reliability analysis(Inverter chain simulations for
IO design), post-silicon characterization of devices using different VLSI tools.

PROFESSIONAL Experience
Design Engineer (Process Technology Group)
ARM
June 2014 Present (8 months) Bengaluru Area, India
Working in Process Technology Group of Physical IP division with following responsibilities:
1. Physical verification, Parasitic Extraction, Spice model evaluation and Design rule from various
major foundries.
2. Support IO, Memory, Test chip teams for any issue in PDK for various foundries.
3. Hands on experience on Physical Verification like DRC, LVS. & P-cell creation for various foundry
projects,
4. BSIM (planar & 3D transistor) model evaluation for matured to cutting edge technologies.
Model Design Engineer-2 in LSI India R&D Pvt. Ltd., Bangalore, India
November 2012 June 2014
Job Responsibility:
1. Responsible for MOS modeling validation & characterization in advanced technology
Such as 28nm, 16FinFET, Com3_SiGe, Com3plus_SiGe.
2. Responsible for supporting design teams (IO, Memory, Mixed signal) related to device
modeling & extraction.
3. Supported IO teams for cross-technology (28nm,16FF etc) Reliability simulations for
Inverter chain.
4. Responsible for reliability analysis of devices & generating Spice Models in advanced
technology nodes.
5. Extracting Layout Dependent Effects for advanced nodes such as 28nm, 16FF .
6. Responsible for BJT & MOSCAP com3_sg post-silicon validation with Spice models.
7. Responsible & owner of device characterization lab for CV measurement which includes
troubleshooting in probe station & environment setup.

R & D Engineer in Taiwan Semiconductor Manufacturing Company (TSMC), Taiwan


September 2010 - October 2012
Job Responsibility:
1. Responsible for supporting Design teams for any issues in Device models & circuit level
simulations in advanced nodes.
2. Responsible for MOS modeling & RF characterization (Add Multifinger effect, flicker
noise, t-noise) in 90nm, 65nm, 55nm, 28nm, 20nm technology.

3. Responsible for MOSCAP device Modeling in different technology.


4. Responsible for solving cases for MOS mismatch modeling for different customers using
Cadence Virtuoso Analog Design Environment (ADE).
5. Co-work with integration team for 65nm passive devices (MIMCAP, RTMOM) and to
check the compatibility of different tools with tsmc design process.
6. Generating ESD guess models in 90nm, 65nm for different customers.

ACADEMIC DETAILS
Year
2010
2008

Degree / Exam
MTech in RF Design & Technology
B.E. in Electronics & Communication

Institute
IIT Delhi
REC Re wa

GPA / Marks (%)


8.355
80.09

INDUSTRIAL TRAINING
BHARAT SANCHAR NIGAM LIMITED (Jun, 2007 - July, 2007)
Description -Four weeks industrial training in BSNL, Rewa (M.P.) to understand the functioning of
OCB-283 and the Broadband services which is provided by BSNL.

IIT DELHI THESIS

Title - Reconfigurable Passive Circuits using RF MEMS on microwave laminate.


Description -To design and develop a process flow using PCB MEMS(micro electro
mechanical systems) technology by which reconfigurable circuits(circuits which can operate at
many frequency accordingly) can be used for different purpose such as frequency hopping of
signals etc .

OTHER PROJECTS

EMBEDDED WEB SERVER (Jan, 2008 - May, 2008)


1. It is a microprocessor or microcontroller that contains an internet software suite as well as
application code for monitoring and controlling systems.
2. It is an integral part of embedded network. Such a system can serve web pages over a
TCP/IP network, allowing any browser with access to the network ability to control and
monitor a network application.

TOOL SKILLS

Synopsys Tools:
Cadence Tools:
Mentor Tools:
Agilent Tools:
ProPlus Tools:
Others:
Lab Tools:
Software Tools:

Finesim, Hspice, StarRCXT, ICC


Spectre, Virtuoso, RelXpert, Pspice, QRC
Eldo, Calibre
ICCAP, ADS
BSIMProPlus, NoisePro
EMX, Ansoft HFSS, Microwave CST, Intellisuit, Coventor
VNA, Spectrum Analyzer, LCR meter, Oscilloscope, Cascade Prober

Perl, C, C++, Matlab, Labview, C55 DSP Programming Language.

ACTIVITIES & INTEREST


1.
2.
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Presented tutorials on Characterization & Spice modeling.


Catch the Spark award within 3 month probation period in LSI R&D for individual work on
28nm reliability models & CV measurement setup & automated measurement.
Certificate of appreciation for organizing different workshops in IIT Delhi.
Member of Taiwan Cricket Club during the stay in TSMC, Taiwan.
Volunteered different sports activities like Badminton in LSI India R&D.

OTHER INTERESTS

1. Playing Cricket, Badminton, Billiards. 2.


Keen Interest on Photography.
.PERSONAL DETAILS
Date of Birth

28th June 1987

Marital Status

Single

Nationality

Indian

Place: Bengaluru

Saurabh Dwivedi