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Sr059210202 Pulse Digital Circuits

Sr059210202 Pulse Digital Circuits

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JNTU previous papers old papers supplementary regular papers ist year 2-1 2-2 3-1 3-2 4-1 4-2 first year second year third year fourth year semester cse ece it eee mechanical civil
JNTU previous papers old papers supplementary regular papers ist year 2-1 2-2 3-1 3-2 4-1 4-2 first year second year third year fourth year semester cse ece it eee mechanical civil

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Code No: R059210202

Set No. 1

II B.Tech I Semester Supplementary Examinations, February 2007 PULSE & DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆

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Figure 1: 3. Write Short notes on: (a) Diode switching times (c) FET as a switch. (b) Switching characteristics of transistors

1. (a) Verify V2 = (V/2)(e2x −1)/(e2x +1) = (V/2) tanhx for a symmetrical square wave applied to a low pass RC circuit. (b) Derive the expression for percentage tilt(P) of a square wave output of RC high pass circuit. [8+8]

2. (a) Determine Vo for the network shown in figure 1 for the given waveform. Assume ideal Diodes.

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(b) Explain how an Schmitt trigger circuit acts as a comparator. (b) Derive the relation between the slope, transmission and displacement errors
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(b) Draw the basic circuit diagram of positive peak clamper circuit and explain its operation. [8+8]

[4+8+4]

4. (a) Draw the circuit diagram of a Schmitt trigger circuit and explain its operation. Derive the Expressions for its UTP and LTP. [12+4]

5. (a) Draw and clearly indicate the restoration time and flyback time on the typical waveform of a time base voltage.
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Code No: R059210202 (c) Explain how UJT is used for sweep circuit?

Set No. 1
[6+4+6]

6. (a) Draw the circuit diagram of an astable multivibrator to obtain frequency division by 6. Explain its working with waveforms. (b) Explain the terms phase delay and phase jitter. [8+8]

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Figure 2: (b) Give some applications of logic gates. (c) Define a positive and negative logic systems. ⋆⋆⋆⋆⋆
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7. (a) Explain the effect of circuit capacitances on the operation of a bi-directional diode gate. (b) In the circuit of figure 2 consider that RL=RC=100K ohms and that R2=2 K ohms, Rf=50 ohms for Vs=25V, compute A, Vnmin, and Vcmin. [8+8]

8. (a) What are the basic logic gates which perform almost all the operations in Digital communication systems.

(d) Draw a pulse train representing a 11010111 in a synchronous positive logic digital system. [4+4+4+4]

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Code No: R059210202

Set No. 2

II B.Tech I Semester Supplementary Examinations, February 2007 PULSE & DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆

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1. (a) Derive the conditions necessary for good integrator: Figure 1: 3. (a) Explain the terms pertaining to transistor switching characteristics. i. ii. iii. iv. v. vi. Rise time. Delay time. Turn-on time. Storage time. Fall time. Turn-off time.

(b) A square wave whose peak to peak amplitude is 1V extends ±0.5V with respect to ground. The duration of the positive section is 0.1 Sec. and of the negative section is 0.2 Sec. If this wave form is impressed on RC high pass circuits whose time constant is 0.2 Sec. what are the steady state maximum and minimum values of the output waveform? [6+10]

2. (a) A symmetrical 10 kHz square wave whose peak -to-peak excursion are ±10V with respect to ground is impressed upon the diode clamping circuit shown in figure 1. The Diodes has Rf = 100 Ω, Rr = α and Vγ = 0. Sketch the steady state output waveform Indicating clearly the voltage levels.

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(b) Explain positive peak voltage limiters above and below reference level. [8+8]

(b) Give the expression for risetime and falltime in terms of transistor parameters and operating currents. [6+10] 4. (a) Design a collector coupled transistor monostable multivibrator to produce a time delay of 100 µsec. Use transistors have hF E of 250. Use ±12v sources, VCE(sat) = 0.3v, VBE(sat) = 0.7v and VBEcutof f = 0v
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Code No: R059210202

Set No. 2

(b) Show that the astable multivibrator works as voltage controlled oscillator. [10+6] 5. (a) What is a Linear time base generator? Give its Applications (b) Write the differences between the voltage and current time base generators? (c) Why the time base generators are called sweep circuits? [6+6+4]

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(b) Give some applications of logic gates. (c) Define a positive and negative logic systems.

6. (a) What is relaxation oscillator? Name some negative resistance devices used as relaxation oscillators and give its applications. (b) With the help of a circuit diagram and waveforms, explain the frequency division by an astable multivibrator? [8+8]

7. (a) Draw the equivalent circuit and derive the gain and control voltages of bidirectional two diode sampling gate and also give its disadvantages. (b) Draw the Block diagram of sampling scope and explain each block in brief. [8+8]

8. (a) What are the basic logic gates which perform almost all the operations in Digital communication systems.

(d) Draw a pulse train representing a 11010111 in a synchronous positive logic digital system. [4+4+4+4]

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⋆⋆⋆⋆⋆

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Code No: R059210202

Set No. 3

II B.Tech I Semester Supplementary Examinations, February 2007 PULSE & DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆

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Figure 1: (b) Explain synchronized clamping circuit. 3. Write Short notes on: (a) Diode switching times (b) Switching characteristics of transistors (c) FET as a switch.

1. (a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is the period of an input ‘Em sin ωt′ . (b) What is the ratio of the rise time of the three sections in cascade to the rise time of Single section of low pass RC circuit. [8+8]

2. (a) Design a biased positive voltage clamping figure 1 the input is a symmetrical square wave of ±10v at 1Khz. The tilt on the output wave form should not exceed 1% signal source resistance is 500 ohms. Output voltage desired is ±2.7v.

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[8+8]

[4+8+4]

4. (a) Draw the circuit of a self-biased binary using NPN transistors and explain its working. (b) Design an astable multivibrator to generate 5kHz square wave with a duty cycle of 40% and if amplitude 12V. Use NPN transistor having hF E = 100, VBesat = 0.7V, VCEsat = 0.2, ICmax = 100mA. Show the waveforms seen at both the collector and bases. [8+8]
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Code No: R059210202

Set No. 3

5. (a) Draw and clearly indicate the restoration time and flyback time on the typical waveform of a time base voltage. (b) Derive the relation between the slope, transmission and displacement errors (c) Explain how UJT is used for sweep circuit? [6+4+6]

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(b) Give some applications of logic gates. (c) Define a positive and negative logic systems. ⋆⋆⋆⋆⋆

6. (a) What do you mean by a relaxation circuit? Give a few examples of relaxation circuits. (b) With the help of neat waveforms, explain sine wave frequency division with a sweep circuit. [8+8]

7. (a) Explain the basic principles of sampling gates using series switch and also give the applications of sampling gates. (b) Explain the effect of control voltage on gate output of unidirectional sampling gate using diode with some example. [8+8]

8. (a) What are the basic logic gates which perform almost all the operations in Digital communication systems.

(d) Draw a pulse train representing a 11010111 in a synchronous positive logic digital system. [4+4+4+4]

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Code No: R059210202

Set No. 4

II B.Tech I Semester Supplementary Examinations, February 2007 PULSE & DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆

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2. (a) T=1000 µ sec V= 10 V Duty cycle = 0.2 i. Sketch waveform with voltage levels at steady state figure 1 ii. Forward and reverse direction tilt iii. Af / Ar Figure 1: (b) Write a short note on non- linear wave shaping. 3. (a) Explain the terms pertaining to transistor switching characteristics. i. ii. iii. iv. v. vi. Rise time. Delay time. Turn-on time. Storage time. Fall time. Turn-off time.

1. (a) A pulse of amplitude 5 V and duration 20 µ sec is applied to High pass RS circuit having R= 10 k Ω and C = 1000 pf. Calculate the output V0 (t) Sketch the output waveform. Calculate the tilt and undershoot. (b) What is meant by an attenuator and explain the application of an attenuator in a CRO probe. [10+6]

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[12+4]
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Code No: R059210202

Set No. 4

(b) Give the expression for risetime and falltime in terms of transistor parameters and operating currents. [6+10] 4. (a) Explain the operation of bistable multivibrator with relevant triggering circuit and waveforms. (b) Explain the reason for occurrence of over shoot at the base of normally ON transistor of one shot. Derive an expression for overshoot. [8+8]

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5. (a) What is a Linear time base generator? Give its Applications (c) Why the time base generators are called sweep circuits? (b) Write the differences between the voltage and current time base generators? 6. (a) What do you mean by synchronization ? (b) What is the condition to be met for pulse synchronization? (c) Compare sine wave synchronization with pulse synchronization?

[6+6+4]

[4+6+6]

7. (a) Explain the effect of circuit capacitances on the operation of a bi-directional diode gate. (b) In the circuit of figure 2 consider that RL=RC=100K ohms and that R2=2 K ohms, Rf=50 ohms for Vs=25V, compute A, Vnmin, and Vcmin. [8+8]

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Figure 2: 8. (a) What are the basic logic gates which perform almost all the operations in Digital communication systems. (b) Give some applications of logic gates. (c) Define a positive and negative logic systems.
Seminar Topics - Scholarships - Admission/Entrance Exam Notifications 2 ofUSA-UK-Australia-Germany-France-NewZealand Universities List 3 www.andhracolleges.com Engineering-MBA-MCA-Medical-Pharmacy-B.Ed-Law Colleges Information

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Code No: R059210202

Set No. 4

(d) Draw a pulse train representing a 11010111 in a synchronous positive logic digital system. [4+4+4+4] ⋆⋆⋆⋆⋆

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