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An Efficient OFDM Transceiver Design suitable to IEEE 802.11a WLAN standard

An Efficient OFDM Transceiver Design suitable to IEEE 802.11a WLAN standard

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In today’s advanced Communication technology one of the multicarrier modulations like Orthogonal Frequency Division Multiplexing (OFDM) has become broadened, mostly in the field of wireless and wired communications such as digital audio/video broadcast (DAB/DVB), wireless LAN (802.11a and HiperLAN2), and broadband wireless (802.16). In this paper we discuss an efficient design technique of OFDM transceiver according to the IEEE 802.11a WLAN standard. The various blocks of OFDM transceiver is simulated using ModelSimSE v6.5 and implemented in FPGA Xilinx Spartan-3E Platform. Efficient techniques like pipelining and strength reduction techniques are utilized to improve the performance of the system. This implementation results show that there is a remarkable savings in consumed power and silicon area. Moreover, the design has encouraged the reduction in hardware resources by utilizing the efficient reconfigurable modules.
In today’s advanced Communication technology one of the multicarrier modulations like Orthogonal Frequency Division Multiplexing (OFDM) has become broadened, mostly in the field of wireless and wired communications such as digital audio/video broadcast (DAB/DVB), wireless LAN (802.11a and HiperLAN2), and broadband wireless (802.16). In this paper we discuss an efficient design technique of OFDM transceiver according to the IEEE 802.11a WLAN standard. The various blocks of OFDM transceiver is simulated using ModelSimSE v6.5 and implemented in FPGA Xilinx Spartan-3E Platform. Efficient techniques like pipelining and strength reduction techniques are utilized to improve the performance of the system. This implementation results show that there is a remarkable savings in consumed power and silicon area. Moreover, the design has encouraged the reduction in hardware resources by utilizing the efficient reconfigurable modules.

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An Efficient OFDM Transceiver Design suitable to

IEEE 802.11a WLAN standard

T.Suresh
Research Scholar, R.M.K Engineering College
Anna University, Chennai
TamilNadu, India
fiosuresh@yahoo.co.in
Dr.K.L.Shunmuganathan
Professor & Head, Department of CSE
R.M.K Engineering College, Kavaraipettai
TamilNadu, India
kls_nathan@yahoo.com


Abstract—In today’s advanced Communication technology one of
the multicarrier modulations like Orthogonal Frequency Division
Multiplexing (OFDM) has become broadened, mostly in the field
of wireless and wired communications such as digital audio/video
broadcast (DAB/DVB), wireless LAN (802.11a and HiperLAN2),
and broadband wireless (802.16). In this paper we discuss an
efficient design technique of OFDM transceiver according to the
IEEE 802.11a WLAN standard. The various blocks of OFDM
transceiver is simulated using ModelSimSE v6.5 and
implemented in FPGA Xilinx Spartan-3E Platform. Efficient
techniques like pipelining and strength reduction techniques are
utilized to improve the performance of the system. This
implementation results show that there is a remarkable savings in
consumed power and silicon area. Moreover, the design has
encouraged the reduction in hardware resources by utilizing the
efficient reconfigurable modules.
Keywords-FPGA; VHDL; OFDM; FFT; IFFT; IEEE 802.11a
I. INTRODUCTION
Wireless communications are evolving towards the Multi-
standard systems and other communication technologies, are
utilizing the widely adopted Orthogonal Frequency Division
Multiplexing (OFDM) technique, among the standards like
IEEE 802.11a&g for Wireless Local Area Networks (WLANs),
Wi-Fi, and the growing IEEE802.16 for Metropolitan Access,
Worldwide Interoperability for Microwave Access
(WIMAX)[1]. The fast growth of these standards has helped
the way for OFDM to be among the widely adopted standards
and to be the fundamental methods for the improvements of the
next generation telecommunication networks. In broadband
wireless communication, designers need to meet a number of
critical requirements, such as processing speed, flexibility, and
fast time to market. These requirements influence the designers
in selecting both the targeted hardware platform and the design






Figure 1. OFDM point to point System
tool. Therefore, to support high data rates and computational
intensive operations, the underlying hardware platform must
have significant processing capabilities. FPGAs, here,
promotes itself as a remarkable solution for developing
wireless LAN (802.11a and HiperLAN2), and broadband
wireless systems (802.16) with their computational
capabilities, flexibility and faster design cycle[2]. Therefore,
to support high data rates and computational intensive
operations, the underlying hardware platform must have
significant processing capabilities. The aim of this paper is to
implement the reconfigurable architecture for the digital
baseband part of an OFDM transceiver that conforms the
802.11a standard, by including 16 QAM modulator, FFT (Fast
Fourier Transform) and IFFT (Inverse Fast Fourier
Transform), serial to parallel and parallel to serial converter
using hardware programming language VHDL (VHSIC
Hardware Description Language). Moreover, this design is
area and power efficient by making the use of strength
reduction transformation technique that will reduce the
number of multipliers used to perform the computation of
FFT/IFFT processing.
The paper is organized as follows: Section II describes the
OFDM point to point system. Section III represents the
simulated methods of OFDM blocks and their results. Section
IV briefs about the pipelining process. Section V explains the
FFT/IFFT implementation by using Strength Reduction
technique. Section VI shows the implementation results and
resource reductions. Section VII concludes the paper.









C
h
a
n
n
e
l
Serial data
in
Serial data
out
Modulation
(16 QAM)
Serial to
parallel
converter

IFFT
Parallel to
serial
converter
Cyclic
prefix
insertion
Demodulation
(16 QAM)

Parallel to
serial
converter

FFT
Serial to
parallel
converter
Cyclic
prefix
removal
Convolution
decoder

Convolution
encoder
(IJCSIS) International Journal of Computer Science and Information Security,
Vol. 8, No. 2, May 2010
118 http://sites.google.com/site/ijcsis/
ISSN 1947-5500

II. OFDM POINT TO POINT SYSTEM
The simplest form of a point-to-point OFDM system could
be considered as transmitter building blocks into the receiver
side. It represents the basic building blocks that are used in
both the transmission and reception sides as shown in Fig. 1.
A. Convolution Encoder
Convolution encoder is used to create redundancy for the
purpose of secured transmission of data. This helps the system
to recover from bit errors during the decoding process. The
802.11a standard recommends to producing two output bits for
each input. To achieve higher data rates, some of the redundant
bits are removed after the encoding process is completed.
B. QAM Modulation
QAM (Quadrature Amplitude Modulation) is widely used
in many digital radio and data communications. It also
considers the mixture of both amplitude and phase modulation.
In this paper we used 16 bit QAM and is used to refer the
number of points in constellation mapping. This is because of
QAM achieves a greater distance between adjacent points in
the I/Q plane by distributing the points more evenly. By this
way the points in the constellation are distinct and due to this,
data errors are reduced.
C. IFFT/FFT
The key kernel in an OFDM transceiver is the IFFT/FFT
processor. In WLAN standards it works with 64 carriers at a
sampling rate of 20 MHz, so a 64-point IFFT/FFT processor is
required. The Fast Fourier Transform (FFT) and Inverse Fast
Fourier Transform (IFFT) are derived from the main function
which is called Discrete Fourier Transform (DFT). The idea of
using FFT/IFFT instead of DFT is that the computation can be
made faster where this is the main criteria for implementation.
In direct computation of DFT the computation for N-point DFT
will be calculated one by one for each point. But for FFT/IFFT,
the computation is done simultaneously and this method helps
to save lot of time, and so this is similar to pipelining
method[4].
The derivation starts from the fundamental DFT equation
for an N point FFT. The equation of IFFT is given as shown in
(1) and the equation of FFT is given as shown in (2)

˲(n) =
1
N
` X(k)ˣ
-nk
, k = Ŵ,ŵ, .N - ŵ
N-1
k=0
(1)

˲(n) = ` X(k)ˣ
nk
, k = Ŵ,ŵ, .N - ŵ
N-1
k=0
(2)

where the quantity W
nk
N
(called Twiddle Factor) is defined as
W
nk
N
= e
-j2πnk¡N
(3)
This factor is calculated and put in a table in order to make the
computation easier and can run simultaneously. The Twiddle
Factor table is depending on the number of points used. During
the computation of FFT, this factor does not need to be
recalculated since it can refer to the Twiddle factor table, and
thus it saves time.





Figure 2. 2 Point Butterfly structure

D. Strength Reduction Transformation
Fig. 2 shows the 2 point Butterfly structure where
multiplication is performed with the twiddle factor after
subtraction. Consider the problem of computing the product of
two complex numbers R and W

X = RW = (R
r
+jR
i
)(W
r
+jW
i
)
=(R
r
W
r
-R
i
W
i
)+j(R
r
W
i
+R
i
W
r
) (4)

The direct architectural implementation requires a total of
four multiplications and two real additions to compute the
complex product as shown in (4). However, by applying the
Strength Reduction transformation we can reformulate (4) as

X
r
=(R
r
-R
i
)Wi+R
r
(W
r
-W
i
) (5)
X
i
=(R
r
-R
i
)W
i
+R
i
(W
r
+W
i
) (6)

It is clearly shown as given in (5) and (6), by using the
Strength Reduction transformation the total number of real
multiplications is reduced to only three. This however is at the
expense of having three additional adders. So in this paper the
above discussed strength reduction transformation technique is
used in the implementation of OFDM transceiver while
multiplying the transmitted/received signal by twiddle factor.


Figure 3. Cyclic Prefix

W
N

b
a
A=a+b
B=(a-b)W
N

(IJCSIS) International Journal of Computer Science and Information Security,
Vol. 8, No. 2, May 2010
119 http://sites.google.com/site/ijcsis/
ISSN 1947-5500

E. Cyclic Prefix
One of the most important properties of OFDM
transmission is its robustness against multi path delay. This is
especially important if the signal’s sub-carriers are to retain
their orthogonality through the transmission process. The
addition of a guard period between transmitted symbols can be
used to accomplish this. The guard period allows time for
multipath signals from the previous symbol to dissipate before
the information from the current symbol gets recorded. The
most effective guard period is a cyclic prefix, which is
appended at the front of every OFDM symbol. The cyclic
prefix is a copy of the last part of the OFDM symbol, and is of
equal or greater length than the maximum delay spread of the
channel as shown in Fig. 3.
III. SIMULATED METHODS AND RESULTS
In this paper the simulated blocks of OFDM transceiver are
explained and the results were analyzed. The blocks those are
simulated using ModelSim SE v6.5 are given in Fig. 4. The
blocks consist of OFDM transmitter which includes 16 QAM
modulator and IFFT and OFDM receiver which includes FFT
and 16 QAM demodulator.
In the initial stage the serial binary data value can be
applied to the transmitter block through convolution encoder
for the purpose of secured data transmission and modulated by
the 16-QAM because of its advantageous compared to other
modulations like BPSK, QPSK. An OFDM carrier signal is
the sum of a number of orthogonal sub-carriers, with baseband
data modulation (QAM) and it is demultiplexed into parallel
streams, and each one mapped to a complex symbol stream
using 16-QAM modulation.













Figure 4. Simulated Blocks of OFDM Transceiver
An inverse FFT is computed on each set of symbols,
delivering a set of complex symbols. The real and imaginary
components (I/Q) are used to modulate the cosine and sine
waves at the carrier frequency respectively, these signals are
summed to give the transmitted signal. The baseband signals
are sampled and passed through the OFDM receiver in FPGA
and a forward FFT is used to convert back to the frequency
domain. This returns of parallel streams, is converted to a
binary stream using an 16-QAM demodulator. These are re-
combined into a serial stream, is an estimate of the original
binary stream at the transmitter. The cyclic prefix is used in
OFDM Transceiver for the purpose of eliminating the ISI.
This overall simulation part is done by ModelSim SE v6.5
software with VHDL language and simulated results are
shown in Fig. 5.


Figure 5. Simulated Results
IV. PIPELINE PROCESS
Each block in this architecture is designed and tested
separately, and later those blocks are assembled and extra
modules are added to compose the complete system. The
design makes use of pipelining process and this is mainly
achieved through duplicating the memory elements like
registers or RAMs in simulation function processing and it will
buffer the incoming stream of bits while the previous stream is
being processed. The design environment is completely based
on the Xilinx Integrated Software Environment (ISE) and
IFFT
img
out
IFFT
Real
out
FFT
img
in
RESET CLK
QAM
OUT
QAM
IN









OFDM Transceiver







OFDM Receiver






OFDM Transmitter

Rectangular
QAM
modulation
I
F
F
T

F
F
T
Rectangular
QAM
demodulation
FFT
Real
in
(IJCSIS) International Journal of Computer Science and Information Security,
Vol. 8, No. 2, May 2010
120 http://sites.google.com/site/ijcsis/
ISSN 1947-5500









Figure 6. Mapper Architecture
implemented in the Xilinx Spartan-3E FPGA. As a first step,
the data stream is encoded using a convolution encoder, which
uses a number of delay elements by representing the D-type
Flip-flop for duplicating purpose. The final purpose of the
coding stage is to provide the receiver with the capability to
detect and correct errors through redundancy. By using this
design, the need of more number of multiplexers is avoided and
the abundant memory inside the FPGA is used. To perform the
Pipeline process, the bits are translated or mapped into two
components the In-phase and the Quadrature of (I/Q)
components, those are mapped as shown in Fig. 6.
The representation of these I and Q values is based on a
fixed point representation. Depending on the data rate
selected, the OFDM sub-carriers are modulated using 16-
QAM. This capability came from the pipelining provided by
the previous and the next stages, where each generated I/Q
pair is fed to the IFFT processor. The generated real and
imaginary Pairs are forwarded to the Cyclic Prefix block. The
last samples of the generated OFDM symbol are copied into
the beginning to form the cyclic prefix. In the 802.11a
standard, the last samples of the Pipelining IFFT output are
replicated at the beginning to form a complete samples of
OFDM symbol. These samples are considered as the
maximum delay in the multipath environment.
V. FFT/IFFT IMPLEMENTATION
FFT/IFFT computation is performed using strength
reduction transformation technique in this paper. Fig. 7 shows
the Processing Element(PE) and its resources used to perform
FFT/IFFT computation. This implementation is compared
with the direct computation of FFT/IFFT. It is demonstrated
that there are four multipliers used in the direct computation of
FFT/IFFT, but the number of multipliers used in the
implementation of strength reduction transformation technique
is reduce to only three.
VI. IMPLEMENTATION RESULTS
The work presented in this paper is to implement the
capability of an OFDM transceiver standard in a pure VHDL
code implementation, and to encourage the reduction in
hardware resources by utilizing the efficient techniques and
suitable reconfigurable platform. The approach of divide and
conquer is used to design and test each entity alone and helps
to make the complete system. The work has accomplished the















Figure 7. PE and its resources of FFT/IFFT block
task of designing the digital baseband part of an OFDM
transceiver that conforms to the IEEE 802.11a standard.
However, the implemented design supports only the data rates
6, 12 and 24 Mbps in the standards.
Table I shows the resources used for implementing the blocks
of OFDM system and also shows the percentage of device
utilization by this design from the available resources on
FPGA and the memory elements of estimated values. From
this table we understood that the number of multiplexers is
reduced by using the efficient pipelining and strength
reduction transformation methods, and the total number of
resources is also reduced remarkably.
TABLE I. COMPLETE SYSTEM RESOURCES
VII. CONCLUSION
Orthogonal Frequency Division Multiplexing is an
important technology because so many developing
Device Utilization Summary(Estimated Value)
Logic Utilization Used Available Utilization
Number of Slices 1521 3584 42%
Number of Slice
Flip-Flops
1682 7168 23%
Number of 4 input
LUTs
2549 7168 35%
Number of
bonded IOBs
66 141 46%
Number of
MULT16x16s
12 16 75%
Number of
GCLKs
1 8 12%
-
Х
+ -
- - +
Х Х
+ +
+
Registers
I
1b


2b


4bits


6 bits

Q
BPSK
ROM(2*16)
QPSK
ROM(4*16)
16 QAM
ROM(16*16)
64 QAM
ROM(64*16)
Bits
Grouping
(IJCSIS) International Journal of Computer Science and Information Security,
Vol. 8, No. 2, May 2010
121 http://sites.google.com/site/ijcsis/
ISSN 1947-5500

communication standards require OFDM because of its high
throughput and multi-path. Due to this time spreading analysis
and also the elimination of Inter-Symbol Interference (ISI),
OFDM has several unique properties that make it especially
well suited to mobile wireless data applications. In this paper
the simulated and implemented results of an OFDM
transceiver system through pipelining process is presented.
FFT/IFFT blocks of OFDM transceiver system is implemented
using strength reduction transformation method. From the
result presented in this paper, it is shown that the number of
hardware resources is reduced in this implementation by
exploiting the efficient reconfigurable architecture. The design
is implemented using a pure VHDL language in the XILINX
Spartan-3E Board, and the results showed that this
implementation is an efficient method in terms of Size and
Resources.
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AUTHORS PROFILE

T.Suresh received his BE and ME degrees in
Electronics and Communication Engineering
from Madras University and Alagappa
Chettiar College of Engineering and
Technology in 1991 and 1996, respectively,
and pursuing Ph.D from Anna University,
Chennai ,India. Currently, he is an Assistant
Professor in the Department of Electronics
and Communication Engineering at R.M.K
Engineering College, Chennai, India. His
Research interests include FPGA Design,
Reconfigurable Architecture, Multiagent
System.


Dr.K.L.Shanmuganathan B.E, M.E., M.S.,
Ph.D working as Professor & Head,
Department of Computer Science & Engg.,
RMK Engineering College, Chennai,
TamilNadu, India. He has more than 15
publications in National and International
Journals. He has more than 18 years of
teaching experience and his areas of
specializations are Artificial Intelligence,
Networks, Multiagent Systems, DBMS.
(IJCSIS) International Journal of Computer Science and Information Security,
Vol. 8, No. 2, May 2010
122 http://sites.google.com/site/ijcsis/
ISSN 1947-5500

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