P. 1
Modern Digital Electronics- R P Jain- Solution Manual

Modern Digital Electronics- R P Jain- Solution Manual

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1.1(a)Analog. The output of a pressure gauge is proportional to the pressure
being measured and can assume any value in the given range.
(b)Digital. An electric pulse is produced for every person entering the exhibi-
tion using a photoelectric device. These pulses are counted using a digital
circuit.

(c)Analog. The reading of the thermometer is proportional to the temperature
being measured and can assume any value in the given range.
(d)Digital. Inputs are given with the help of switches, which are converted
into digital signals 1 and 0 corresponding to the switch in the ON or OFF
position. These signals are processed using digital circuits and the results
are displayed using digital display devices.
(e)Analog. It receives modulated signals which are analog in nature. These
signals are processed by analog circuits and the output is again in the
analog form.
(f)Digital. It has only two possible positions (states), ON and OFF.
(g)Digital. An electric pulse is produced for every vote cast by pressing of
switch of a candidate. The pulses thus produced for each candidate are
counted separately and also the total number of votes polled are counted.

1.2 (a)

(i) S

1

S

2

Bulb

(ii) S

1

S

2

Bulb

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

ON

ON

ON

OFF

OFF

ON

OFF

ON

ON

ON

ON

ON

ON

ON

(iii) S

Bulb

(iv) S1

S2

Bulb

OFF

ON

OFF

OFF

OFF

ON

OFF

OFF

ON

ON

ON

OFF

ON

ON

ON

OFF

(b)

(i) S1

S2

Bulb

(ii) S1

S2

Bulb

0

0

0

0

0

0

0

1

0

0

1

1

1

0

0

1

0

1

1

1

1

1

1

1

(iii) S

Bulb

(iv) S

1

S

2

Bulb

0

1

0

0

0

1

0

0

1

1

1

0

1

1

1

0

(c) (i)AND

(ii)OR

(iii) NOT

(iv)EX-OR

2

1.3

1.4

Inputs

Outputs of

A

B

(a)

(b)

(c)

(d)

0

0

1

1

0

0

0

1

0

1

0

1

1

0

0

1

0

1

1

1

0

0

1

1

The operations performed are
(a)NOR

(b)NAND

(c)AND

(d)OR

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

1

2

3

4

5

t(ms)

0

1

2

3

4

5

t(ms)

Input B

AND

OR

NAND

NOR

EX-OR

Input A

3

1.5For Fig. 1.6

(a)

A

Y

(b) A

B

AB

Y

0

1

0

0

1

0

1

0

0

1

1

0

1

0

1

0

1

1

0

1

(c)

A

B

A

B

Y

0

0

1

1

0

0

1

1

0

1

1

0

0

1

1

1

1

0

0

1

For Fig. 1.8

(a)

A

Y

(b) A

B

A B

+

Y

0

1

0

0

1

0

1

0

0

1

0

1

1

0

0

1

1

1

0

1

(c)

A

B

A

B

Y

0

0

1

1

0

0

1

1

0

0

1

0

0

1

0

1

1

0

0

1

1.6

(a)NAND, NOR

(b)AND

(c)NAND

(d) OR

1.7

(a)

Inputs

AB

AB

Output

A

B

Y

0

0

0

0

0

0

1

0

1

1

1

0

1

0

1

1

1

0

0

0

(b)EX–OR
(c)

A

B

Y

4

(d)

Y= AB AB

+

\

Y = +

AB AB

= ⋅

AB AB

Y= Y = ⋅

AB AB

= ⋅

Y Y

1 2

where,

Y

1 = ABand Y

2 = AB

A

B

Y

Y

1

Y

2

1.8For simplicity, we shall consider 2-input gates, but the results are equally
valid for any number of inputs. In the positive logic system, the higher of the
two voltages is designated as 1 and the lower voltage as 0. On the other hand
in the negative logic system, the lower of the two voltage is designated as 1
and the higher voltage as 0. Therefore, if 1s and 0s are interchanged, the logic
system will change from positive to negative and vice-versa.
(a)In the truth table of positive logic AND gate replace all zeros by ones
and all ones by zeros. The resulting truth table is same as that of the OR
gate. Similarly, if all ones and zeros are interchanged in the truth table
of the OR gate, the resulting truth table will be same as that of the AND
gate.
(b)Repeat part (a) for NAND and NOR gates.

1.9

(a) A + AB + AB= (A + AB) + AB

= A (1 + B) + AB

= A × 1 + AB

= A + AB

= (A + A) (A + B) = A + B

(b) AB + AB + A B= (A + A) B + A B

= B + A B = (B + A) (B + B)

= A + B

(c) ABC + ABC + ABC + ABC

= ABC + ABC + AB (C + C)

= ABC + ABC + AB

= ABC + A (B + B C)

= ABC + A (B + B) (B + C)

5

= ABC + AB + AC

= C (A + AB) + AB

= C (A + A) (A + B) + AB

= C (A + B) + AB

= AB + BC + CA

1.10 (a)

A

B

A B

AB

A + AB + AB

A + B

0

0

0

0

0

0

0

1

1

0

1

1

1

0

0

1

1

1

1

1

0

0

1

1

(b)

A B AB A B A B AB + AB + A B

A + B

0

0

0

0

1

1

1

0

1

0

1

0

1

1

1

0

0

0

0

0

0

1

1

1

0

0

1

1

(c)

A B C ABC ABC ABC ABC LHS AB BC CA RHS

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

0

0

1

0

1

0

1

1

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

0

1

1

1

1

0

0

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

1

1

1

1

1

1.11(a)The realization of LHS requires, two inverters, two 2-input AND gates,
and one 3-input OR gate, whereas the realization of RHS requires only
one two input OR gate.

A

B

A

B

(ii)

(i)

6

(b)The realization of LHS requires two inverters, three 2-input AND gates
and one 3-input OR gate, whereas the realization of RHS requires only
one inverter and one 2-input OR gate.

A

B

A

B

(c)The realization of LHS requires three inverters, four 3-input AND gates
and one 4-input OR gate, whereas the realization of RHS requires only
three 2-input AND gates and one 3-input OR gate.

A

B

C

(i)

A

B

C

(ii)

1.12(a) AB + CD = + = ⋅

AB CD AB CD

(i)

(ii)

7

(b)(A + B) (C + D) = + ⋅ +

( ) ( )

A B C D

= + + +

( ) ( )

A B C D

(i)The left hand side of (a) can be realized by using two 2-input AND
gates followed by one 2-input OR gate, while the right hand side is
realizable by two 2-input NAND gates followed by another 2-input
NAND gate. Hence an AND-OR configuration is equivalent to a NAND-
NAND configuration.
(ii)The left hand side of (b) is realizable by two 2-input OR gatesfollowed
by a 2-input AND gate, while the right hand side is realizable by two
2-input NOR gates followed by another 2-input NOR gate. Hence an
OR-AND configuration is equivalent to a NOR-NOR configuration.

1.13

Y

A

B

C

D

Y

A

B

C

D

(i)

(ii)

A

B

C

D

A

B

C

D

(i)

(ii)

Y

Y

1.14(a)Since A × B = B × A
Therefore, the AND operation is commutative. If A × (B × C) = (A × B) × C, then the
AND operation is associative. This can be proved by making truth table as given
below:

A

B

C

(A × B) × C

A × (B × C)

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

1

1

0

0

1

0

0

0

0

1

0

1

0

0

1

1

0

0

0

1

1

1

1

1

(a)

(b)

8

Since the last two columns of the truth table are identical, which proves
that the AND operation is associative.
(b)Since, A + B = B + A, therefore, OR operation is commutative.
The associative property requires
A + (B + C) = (A + B) + C
which can be proved by making the truth table in a way similar to the
truthtable of (a) above
(c)Since, A Å B = B Å A, which means the EX-OR operation is commutative.
The associative property requires
(A Å B) Å C = A Å (B Å C)
This can be proved by making truth table

1.15(a)Since = ⋅ = ⋅

A B B A, therefore, the NAND operation is commutative.
To verify whether the NAND operation is associative or not, we prepare
the truth table as given below. From the Table we observe that the last
two columns are not identical, which means

A B C A B C

⋅ ⋅ ≠ ⋅ ⋅

( ) ( )

This shows that the NAND operation is not associative.

A

B

C

A B C

⋅ ⋅

( ) ( )

A B C

0

0

0

1

1

0

0

1

1

0

0

1

0

1

1

0

1

1

1

0

1

0

0

0

1

1

0

1

0

0

1

1

0

0

1

1

1

1

1

1

(b)Since, A B B A

+ = + , which means the NOR operation is commutative.
By making a truth table similar to the truth table of (a) above we can
verify that

( )

( )

A B C A B C

+ + ≠ + +

Therefore, the NOR operation is not associative.
1.16Two possible realizations are given on page 9:
1.17

(i)If only one of the variables is 1 and all others are zero, then
(1 Å 0) Å 0 Å 0 Å . . .= 1 Å 0 Å 0 Å . . .
= 1 Å 0 = 1
(ii)If only two of the variables are 1 and all others are zero, then (since EX-
OR operation is commutative and associative)
(1 Å 1) Å 0 Å 0 Å 0 Å . . . = 0 Å 0 Å 0 Å 0 Å . . . = 0
(iii)Similarly, if only three of the variables are 1, then
(1 Å 1) Å 1 Å 0 Å 0 Å . . .
= 0 Å 1 Å 0 Å 0 Å 0 Å . . .
= 1

9

A

B

C

D

A Å B

A ÅB ÅC

A Å B Å C Å D

Y

or

A

B

C

D

A Å B

C Å D

Y
A ÅB ÅCÅD

Fig. 1.17

In the same way we can try higher number of ones. It is obvious from
the above discussion that Z = 1, if an odd number of variables are 1 and
Z = 0 if an even number of variables are 1.

1.18

Since a logical variable can assume one of the two values (0 or 1) the
number of possible combinations is 2N
.
Take an N-bit binary number bN–1 bN–2 . . . b2b1b0 and write all combina-
tions from 00 . . . 000 to 11 . . . 111 in normal binary ascending order.
1.19(a)7402 is a quad 2-input NOR gate. This means there are four identical
2-input NOR gates. Each gate requires three pins, two for inputs and one
for output. Therefore, the four gates requires 3 ´ 4 = 12 pins. Two pins
are required for the power supply (V

CC and GND). Hence it is a 14-pin

IC.
(b)7404 is a hex inverter.
The number of pins = 2 ´ 6 + 2 = 14.
(c)7408 is a quad 2-input AND gate.
The number of pins = 3 ´ 4 + 2 = 14.
(d)7410 is a triple 3-input NAND gate.
The number of pins = 4 ´ 3 + 2 = 14.
(e)7411 is a triple 3-input AND gate.
The number of pins = 4 ´ 3 + 2 = 14.
(f)7420 is a dual 4-input NAND gate.
The number of pins = 5 ´ 2 + 2 = 12.
Since 12-pin IC package is not used, therefore, it is packaged as 14-pin IC.
Two pins are left free (NC).
(g)7427 is a triple 3-input NOR gate.
The number of pins = 4 ´ 3 + 2 = 14.
(h)7432 is a quad 2-input OR gate.
The number of pins = 3 ´ 4 + 2 = 14.

10

(i)7486 is a quad EX-OR gate.
The number of pins = 3 ´ 4 + 2 = 14.

1.20(a)(i)7408 and 7432
(ii)7400
(b)(i)7432 and 7408
(ii)7402
1.21 Logic Circuit A

0.4V= 0
2V= 1

Logic Circuit B

–0.75V= 1
–1.55V= 0

1.22

Inputs

Output

AND

OR

NAND

NOR

A

B

C

Y1

Y2

Y3

Y4

0

0

0

0

0

1

1

0

0

1

0

1

1

0

0

1

0

0

1

1

0

0

1

1

0

1

1

0

1

0

0

0

1

1

0

1

0

1

0

1

1

0

1

1

0

0

1

1

0

1

1

1

1

1

0

0

1.23

Yes.

A
B
C

Logic 1

or

Y

Y

A
B
C

(a)

Y

A
B
C

or

A
B
C

Y

Logic 0

(b)

A
B
C

A
B
C

or

Y

Y

Logic 1

(c)

A
B
C

A
B
C

or

Y

Y

Logic 0

(d)

11

1.24

Yes.

AND

—by connecting one of the inputs to logic 0

OR

—by connecting one of the inputs to logic 1
NAND—by connecting one of the inputs to logic 0
NOR

—by connecting one of the inputs to logic 1.

1.25(a)Active-high

(b)Active-low

(c)Active-high

(d)Active-low

1.26(a)Active-low

(b)Active-high

(c)Active-low

(d)Active-high

1.27(a)

(b)

A

B

C

Y

A

B

C

Y = A + B + C = (A + B) + (C)

(c)

A

B

C

Y

AB

C

Y = A × B × C = (A × B) × (C)

Y A B C

= ⋅ ⋅ = ⋅ +

( )

A B C

= ⋅ ⋅

( )

A B C

= ⋅ ⋅

A B C

(d)

A

B

C

Y

AB

Y

12

1.28(a) A Å B= AB + AB

A Å B= AB AB

+

= AB + AB = A Å B

(b) A B

= AB + AB

A Å B= AB A B

+

= AB + AB

A Å B= AB AB AB AB

+ = +

(c) B Å (B Å AC) = B Å B Å AC= 0 Å AC
= AC

13

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