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PLD

THIẾT BỊ LOGIC LẬP TRÌNH ĐƯỢC


(Programmable Logic Device)

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BOÄ NHÔÙ BAÙN DAÃN

Boä nhôù baùn daãn

Boä nhôù baûng Boä nhôù haøm

RAM ROM PLD

tónh ñoäng MROM PLA PAL LCA EPLD PEEL GAL


PROM PPAL
EPROM EPLPAL
EEPROM EEPPAL

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BOÄ NHÔÙ ROM

Input: caùc tín hieäu ñòa chæ (Address)


Output: caùc tín hieäu döõ lieäu (Data)

A0 D0
INPUT A1 D1 OUTPUT
(n ñöôøng) (m ñöôøng)

An-1 Dm-1

Kích thöôùc ROM: 2n x m (bit)

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Caáu truùc noäi ROM 8 x 4 (bit) Baûng naïp ROM
A2 A1 A0 D3 D2 D1 D0
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
1
0 1 1 0 1 1 1
1
1 0 0 0 0 0 1
1 1 0 1 0 0 1 0
1 1 1 1 0 0 1 0 0
0 1 1 1 1 1 0 0 0
1 0
1
1
1 0
0
word line 1
1
0
bit line 1 0
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ROM 128 x 1 (bit) giaûi maõ 2 chieàu

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ROM 32K x 8 (bit) = 32KB

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Caáu truùc ROM coù ngoõ vaøo ñieàu khieån

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Coång ñeäm ba traïng thaùi (Tristate Output Buffer):
- 3 traïng thaùi (tristate): LOW / HIGH / HIGH impedance
- Traïng thaùi toång trôû cao (HIGH impedance): ngoõ ra hôû maïch
- Ngoõ ñieàu khieån 3 traïng thaùi:
* HIGH: The buffer is Active
* LOW: HIGH impedance

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Caùc EPROM thoâng duïng

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PLA
(PROGRAMMABLE LOGIC ARRAY)

INPUT Daõy Daõy OUTPUT


(n bit) AND OR (m bit)

k product term (soá haïng tích)

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Daõy AND coù theå laäp trình

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Daõy OR coù theå laäp trình 11
A Caáu truùc PLA 3 x 2, 4 soá haïng tích

B F1 = A B + A C + A B C
F2 = A C + B C
C
AB

AC

BC

ABC
0
Baûng naïp PLA C C B B A A 1
A B C F2 (C) F1 (T) F1
AB 1 0 - 0 1
AC 1 - 1 1 1 F2
BC - 1 1 1 0
ABC 0 1 0 0 1
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PAL
(PROGRAMMABLE ARRAY LOGIC )

- Daõy AND laäp trình, daõy OR coá ñònh

- Moãi ngoõ ra laø coång OR coù soá ngoõ vaøo coá ñònh

- Soá haïng tích khoâng söû duïng chung cho caùc ngoõ ra

- Caáu truùc PLA: soá ngoõ vaøo, soá ngoõ ra vaø soá coång AND
treân 1 coång OR

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Caáu truùc PAL 3 ngoõ vaøo, 3 ngoõ ra, 3 coång AND / OR

1
2 F1
3
I1
4
5 F2
6
I2
7
8 F3
9
I3

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X=AB+BC Y=A+BC Z=AB+BC+BC+AC
=X+BC+AC
A A B B C C X X
1
2 X
3
A
4
5 Y
6
B
7
8 Z
9
C
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X=AB+BC Y=A+BC Z=AB+BC+BC+AC
=X+BC+AC

Baûng naïp PAL


A B C X OUTPUT
1 1 1 X = AB
2 1 1 + BC
3
4 0 Y = A
5 0 0 + BC
6
7 1 Z = X
8 0 0 + BC
9 0 1 + AC

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