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SystemVerilog Testbench

SystemVerilog Testbench

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Published by Vivek
Tutorial on testbench design with SystemVerilog.
Tutorial on testbench design with SystemVerilog.

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Published by: Vivek on Aug 10, 2010
Copyright:Attribution Non-commercial

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01/30/2015

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class Driver;
task send(Transaction tr);
tr.calc_crc();
// Drive interface signals

endtask
endclass

class Transaction;
virtualfunction voidcalc_crc();

endclass

class BadTr extends Transaction;
rand bit bad_crc;
virtualfunction voidcalc_crc();

endclass

programBadTest;
BadTr bt = new;
task main();
assert(bt.randomize());
my_driver.send(bt);

endtask
endprogram

77

SystemVerilog Testbench with VCS

05/07/2007

Transaction

BadTr

src

data

dst

crc

bad_crc

calc_crc

calc_crc

Overriding Methods

By default, a method is found using the handle type

What happens when extended object is referenced
by a base handle?

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