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SystemVerilog Testbench

SystemVerilog Testbench

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Published by Vivek
Tutorial on testbench design with SystemVerilog.
Tutorial on testbench design with SystemVerilog.

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Published by: Vivek on Aug 10, 2010
Copyright:Attribution Non-commercial

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01/30/2015

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initial begin
Transaction t = new();
s = t.randomize() with{src >= 50; src <= 1500; dst < 10;};
driveBus(t);

// force src to a specific value
s = t.randomize() with{ src == 2000; dst > 10;};
driveBus(t);

end

Constraints may be defined at the time of randomization

Allows test-specific constraints

Don’t modify the original class for just a single test

In-line constraints are additive with existing class constraints

Supports all SystemVerilog constraints and distributions

class Transaction;
rand bit [31:0] src, dst, data[1024];
constraint valid{src inside{[0:100], [1000:2000]}; }

endclass

src: 50-100,
1000-1500
dst<10

src==2000
dst>10

90

SystemVerilog Testbench with VCS

05/07/2007

Randomization

The solver has to handle algebraic factoring, complex Boolean

expressions, mixed integer and bit expressions and more

All constraints interact bidirectionally and are solved

concurrently

Keep in mind rules regarding precedence, sign extension,

truncation and wrap-around when creating constraints

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