ISE In-Depth Tutorial

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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring failsafe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. Copyright © 1995-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.

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Preface

About This Tutorial
About the In-Depth Tutorial
This tutorial gives a description of the features and additions to Xilinx® ISE™ 9.1i. The primary focus of this tutorial is to show the relationship among the design entry tools, Xilinx and third-party tools, and the design implementation tools. This guide is a learning tool for designers who are unfamiliar with the features of the ISE software or those wanting to refresh their skills and knowledge. You may choose to follow one of the three tutorial flows available in this document. For information about the tutorial flows, see “Tutorial Flows.”

Tutorial Contents
This guide covers the following topics. • • • Chapter 1, “Overview of ISE and Synthesis Tools,” introduces you to the ISE primary user interface, Project Navigator, and the synthesis tools available for your design. Chapter 2, “HDL-Based Design,” guides you through a typical HDL-based design procedure using a design of a runner’s stopwatch. Chapter 3, “Schematic-Based Design,” explains many different facets of a schematicbased ISE design flow using a design of a runner’s stopwatch. This chapter also shows how to use ISE accessories such as StateCAD, CORE Generator™, and ISE Text Editor. Chapter 4, “Behavioral Simulation,” explains how to simulate a design before design implementation to verify that the logic that you have created is correct. Chapter 5, “Design Implementation,” describes how to Translate, Map, Place, Route (Fit for CPLDs), and generate a Bit file for designs. Chapter 6, “Timing Simulation,” explains how to perform a timing simulation using the block and routing delay information from the routed design to give an accurate assessment of the behavior of the circuit under worst-case conditions. Chapter 7, “iMPACT Tutorial” explains how to program a device with a newly created design using the IMPACT configuration tool.

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ISE 9.1 In-Depth Tutorial

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R Preface: About This Tutorial Tutorial Flows This document contains three tutorial flows.xilinx. it is strongly recommended in this tutorial flow. “iMPACT Tutorial” • • • Schematic Design Flow The Schematic Design flow is as follows: • • Chapter 3. Chapter 7. “Design Implementation” Chapter 6. “Behavioral Simulation” Note that although behavioral simulation is optional. Chapter 5. “iMPACT Tutorial” • 4 www. it is strongly recommended. the three tutorial flows are outlined and briefly described. “Design Implementation” Chapter 6. “Timing Simulation” Note that although timing simulation is optional.“Timing Simulation” Note that although timing simulation is optional. Chapter 7. In this section. The tutorial flows include: • • • HDL Design Flow Schematic Design Flow Implementation-only Flow HDL Design Flow The HDL Design flow is as follows: • • Chapter 2. “Timing Simulation” Note that although timing simulation is optional. “Schematic-Based Design” Chapter 4. “iMPACT Tutorial” • • • Implementation-only Flow The Implementation-only flow is as follows: • • Chapter 5. Chapter 7. it is strongly recommended in this tutorial flow. “Behavioral Simulation” Note that although behavioral simulation is optional. Chapter 5. “HDL-Based Design” Chapter 4.com ISE 9.1 In-Depth Tutorial . “Design Implementation” Chapter 6. in order to help you determine which sequence of chapters applies to your needs. it is strongly recommended in this tutorial flow. it is strongly recommended in this tutorial flow.

1 In-Depth Tutorial www. ISE 9.xilinx.xilinx. To search the Answer Database of silicon. see the Xilinx website at: http://www. see the Xilinx website at: http://www. and IP questions and answers.Additional Resources R Additional Resources To find additional documentation. or to create a technical support WebCase.com 5 .com/literature. software.xilinx.com/support.

R Preface: About This Tutorial 6 www.com ISE 9.xilinx.1 In-Depth Tutorial .

. . . . . . . 19 ISE 9. . . . . . . . . . . . . Importing a Project . . . . 3 Tutorial Flows . . . . . . . . . . . . . . . . . . . . . Transcript Window . . . . . . . . . . . . . . . . . . . . . .1 In-Depth Tutorial www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processes Window . . . . . . . . . . . . . . . . . Precision Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sources Window . . . . . . . . . . . . . . . . . . . . . . . Schematic Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synplify/Synplify Pro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sources Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Synthesis Technology (XST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exporting a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISE Simulator / Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Tutorial Contents . Process Properties . . . . 4 Schematic Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processes Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an Archive . . . . . . . . . . . . . . .com 1-800-255-7778 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Navigation to Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Navigation to Answer Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Libraries Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Additional Resources . Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing a Snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Snapshot . 4 Implementation-only Flow . . . . . . . . . .Table of Contents Preface: About This Tutorial About the In-Depth Tutorial . . . . . . . . . . . . Design Summary . . . . . . . . . . . . . . . . . . . . . Using Project Archives . . Snapshots Tab . . . .xilinx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Overview of Synthesis Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 HDL Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chapter 1: Overview of ISE and Synthesis Tools Overview of ISE . . . . . . . . . . . . . . Restoring a Snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Workspace . . . . . . . . . . . . . . . . . 13 14 14 15 15 15 15 16 16 16 17 17 17 17 17 17 17 17 18 18 18 18 18 18 19 19 19 20 20 20 20 Using Revision Control Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Snapshots . . . . . . . . . . . . . . . Using Export/Import Source Control . . . . . 13 Project Navigator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restoring an Archive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . Using the Clocking Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding a Language Template to Your File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Installing the Tutorial Project Files . . . . Installing the Tutorial Project Files . . . . . . . . . . . . . . . . . . . . . . Stopping the Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The RTL/Technology Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 In-Depth Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instantiating the dcm1 Macro . . . . . . . . . . . . . . . . . . . . . . . . . . 51 52 52 52 53 8 www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Inputs . . . . . . . . . . The RTL / Technology Viewer . . . . . . . . . . . . . . . . . . . . . . . . . Creating a DCM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Required Software . . . . . . Using the Language Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizing the Design Using Precision Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a CORE Generator Module . . . . . . . . . Entering Synthesis Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Chapter 3: Schematic-Based Design Overview of Schematic-Based Design . . . . . . . . . . . . . . . . . . . . 28 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a New Project: Using the New Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .com 1-800-255-7778 ISE 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Verilog . . . . . . . . Creating a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Starting the ISE Software . . . . . . . . . . . . . . . . . . . . Entering Constraints . . . . . . . . 29 Adding Source Files . . . . . . . . . . . . . . . . . Creating a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering Synthesis Options through ISE . . . . . . . Examining Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . Creating a CORE Generator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a New Project: Using New Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optional Software Requirements . . . . . . . . . . . . . . . . . . . 24 24 24 24 25 25 25 27 27 Design Description . . . . . . 51 Required Software . . . . . . . . . . . . . . . . 30 30 31 32 32 34 35 36 36 38 39 39 41 42 44 44 45 45 45 47 47 48 49 49 Synthesizing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizing the Design using Synplify/Synplify Pro . . . . . . . . . . . . . . . . . . . Creating an HDL-Based Module . . . . . . . . . . . . . . . . . . . . . . . VHDL or Verilog? . Synthesizing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Starting the ISE Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking the Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizing the Design using XST . . . . . . . . . . . . Creating a New Project: Using a Tcl Script . . . . . . Using the New Source Wizard and ISE Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . .R Chapter 2: HDL-Based Design Overview of HDL-Based Design. . . . . . . . . . . . . . . .VHDL Design . . Instantiating the CORE Generator Module in the HDL Code. . .xilinx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Correcting HDL Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instantiating the dcm1 Macro . . . . . . . . . . . .

. . . . . . . . Changing Instance Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer_preset. . . . . . . . Creating a State Machine Module . . . . . . . . . . . . . . . . . . . . Adding Schematic Components . . . . . . . . . 57 Opening the Schematic File in the Xilinx Schematic Editor. . . . . . . . . . . . . . . . . . . . . . . . . Using the Clocking Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Stopping the Tutorial . . . . . . . . . . . . . . . . . . . . . 91 ISE 9. Placing the statmach. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .com 1-800-255-7778 9 . . . . . . . . . Adding Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a CORE Generator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a DCM Module . . . . . . . . . . . . . . . . . . . . . Adding a Language Template to Your File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Bus Taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Schematic-Based Macro . . . . . . . . . . . . . . . . Checking the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manipulating the Window View . . . . . . . . . . . . . . . . . Specifying Device Inputs/Outputs . . . . . . . . . . . . Adding Net Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dcm1 and debounce Symbols . . . . . . . . . . . . . Adding I/O Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Inputs . . . . . . . . . Adding New States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding I/O Markers and Net Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Design Description . . . . . . . . . . . . . . . . . . 91 ModelSim Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Placing the time_cnt Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assigning Pin Locations . . . . . . . . . Adding Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating the time_cnt symbol . . . . . . . . . . . . . . . . . . . . Defining the time_cnt Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an HDL-Based Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 In-Depth Tutorial www. . . . . . . . . Creating the dcm1 Symbol . . . . . . . . . . . . . . . . . . . .xilinx. . . . . . . . . . . . . . Adding a Transition . .R Creating a New Project: Using a Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating and Placing the time_cnt Symbol . . . . . . . . . . . . Adding a State Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Correcting Mistakes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating the State Machine HDL output file. . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Outputs . . . . . . . . . . . . . . 57 58 58 59 60 60 63 63 63 64 65 66 67 67 67 67 68 68 70 71 72 73 75 75 76 76 76 78 79 79 81 82 83 83 84 85 85 85 86 87 87 Chapter 4: Behavioral Simulation Overview of Behavioral Simulation Flow . . . . . . . . Using the Language Templates. . . . . . . . . . . . . . . . . . Drawing Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hierarchy Push/Pop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding a State Machine Reset Condition . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a CORE Generator Module . . . . . . . . . . . Creating the debounce Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating the State Machine Symbol . . . Completing the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the New Source Wizard and ISE Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Adding Tutorial Test Bench File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Simulation Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Continuing from Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Locating the Simulation Processes . . . . . . . . . Design Files (VHDL. . . . . . . . . 101 Locating the Simulation Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Simulation Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Bench File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 113 114 115 116 120 123 126 Estimating Timing Goals with the 50/50 Rule . . . . . . . . . 101 102 103 103 104 105 105 105 107 Chapter 5: Design Implementation Overview of Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xilinx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Required Files . . . . . . . . . Adding Signals . . . .com 1-800-255-7778 ISE 9. . . . . 109 Getting Started . Rerunning Simulation . . 95 Behavioral Simulation Using ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Behavioral Simulation Using ISE Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or Schematic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .R ModelSim PE and SE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Constraints Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Rerunning Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 92 92 92 93 93 93 Adding an HDL Test Bench . . . . . . . . . . .ini File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mapping Simulation Libraries in the Modelsim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Test Bench Waveform Using the Waveform Editor . . . . . . . . . . . . . . . . . . 97 Adding Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Starting from Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10 www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating Timing Constraints . . . . . . . . . . . 92 Getting Started . . . 100 Saving the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mapping the Design . . . . . . . . . . . . . . . 94 VHDL Simulation . . . . . . . . . . . . . . . . . . . . 92 ISE Simulator Setup . . . . . . . . . . Xilinx Simulation Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating Partitions . . . . . . . Creating a Test Bench Waveform Source . . . . . . . . . . . . 91 ModelSim Xilinx Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Floorplan Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Verilog Simulation . . . . . . .1 In-Depth Tutorial . 97 Adding Dividers . . . . . . . Updating the Xilinx Simulation Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Timing Analysis to Evaluate Block Delays After Mapping . . . . . . . . . . . . . . . . . . Translating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Specifying Simulation Properties . . . . . . . . . . . . . . . 110 Specifying Options . . . . . . . . . . . . . . . . Applying Stimulus . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . 156 Using Boundary Scan Configuration Mode . . . . . . . . . . . . . . . . . . . 156 Specifying Boundary Scan Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 129 131 132 134 135 138 Chapter 6: Timing Simulation Overview of Timing Simulation Flow . . . . . . . . . . . . . . Analyzing the Signals . . . . . . . . . . . 139 Required Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Required Files . . . . . . . . . . . . . . . . . . . 140 Specifying a Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Chapter 7: iMPACT Tutorial Device Support . . . . . . . . . . . . . . . . Starting the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .R Report Paths in Timing Constraints Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changing HDL with Partition . . . . . . . . . . . . . . . . . Opening iMPACT from Project Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Generating the Configuration Files . . . . . . . . . . . . . . . . Adding Signals . . . . . . . . . . . . . . . Rerunning Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Platform Cable USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Specifying Simulation Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Download Cable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opening iMPACT stand-alone . . . . . . . . . . . . . . . . . . . . . . . Saving the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 ISE 9. . .xilinx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 In-Depth Tutorial www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Dividers . . . . . . 154 155 155 155 155 Creating a iMPACT New Project File . Creating Configuration Data . . . . . . . . . . . . Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analyzing the Signals . . . 126 Placing and Routing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 MultiPRO Cable . . Specifying Simulation Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Simulation . . Viewing Full Signal Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . Evaluating Post-Layout Timing . . . . . . . . . . . . . . . . . .com 1-800-255-7778 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Assigning Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a PROM File with iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using FPGA Editor to Verify the Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 143 143 145 146 146 147 148 149 149 150 150 151 Timing Simulation Using Xilinx ISE Simulator . . . . . . . . . . . . . . 139 Getting Started . . . . . . . . . . . . . . . 154 Parallel Cable IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Configuration Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rerunning Simulation . . . . . . . . . . . Connecting the Cable . . . . . . . . . . . . 140 Timing Simulation Using ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xilinx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Editing Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Troubleshooting Boundary Scan Configuration . . . JTAG chain setup for SVF generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Verifying Chain Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Setting up Boundary Scan Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Playing back the SVF or XSVF file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .R Saving the Project File . . . . . . . . . . . . . . . . . . . . . . . . . . Manual JTAG chain setup for SVF generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 In-Depth Tutorial . . . . . . . . . . 163 Creating an SVF File . . . . Stop Writing to the SVF. . . . . . . . . . . . . . . Writing to the SVF File . . . . . . . . . . . . . . . . . . . . . .com 1-800-255-7778 ISE 9. . . . . . . . . . . . . . . . . . . . . . . 164 164 164 165 166 166 Other Configuration Modes . . . . . . 162 Verifying Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 SelectMAP Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Performing Boundary Scan Operations . . . . . . . . . . . . . . . . . 167 12 www. . . . . . . . . . . . . . . . . . . . . . 166 Slave Serial Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Beneath the Sources window is the Processes window. undocked from Project Navigator or moved to a new location within the main Project Navigator window. as seen in Figure 1-1. The default layout can always be restored by selecting View > Restore Default Layout. You can also access the files and documents associated with your project. and simulation waveforms. It enables you to view html reports. and warnings and also contains interactive tabs for Tcl scripting and the Find in Files function. which displays available processes for the currently selected source.1 In-Depth Tutorial www. ISE 9. The third window at the bottom of the Project Navigator is the Transcript window which displays status messages.xilinx. errors. These windows are discussed in more detail in the following sections. The fourth window to the right is a multi-document interface (MDI) window refered to as the Workspace. you can access all of the design entry and design implementation tools. Project Navigator Interface The Project Navigator Interface is divided into four main subwindows.R Chapter 1 Overview of ISE and Synthesis Tools This chapter includes the following sections: • • • “Overview of ISE” “Using Revision Control Features” “Overview of Synthesis Tools” Overview of ISE ISE controls all aspects of the design flow. On the top left is the Sources window which hierarchically displays the elements included in the project. schematics. ASCII text files.com 13 . Through the Project Navigator interface. Each window may be resized.

In the “Number of” drop-down list.1 In-Depth Tutorial . 14 www. The Design View (“Sources for”) drop-down list at the top of the Sources tab allows you to view only those source files associated with the selected Design View. “Design Implementation”. a Resources column and a Preserve Column are available for Designs that use Partitions. Sources Tab The Sources tab displays the project name. such as Synthesis/Implementation.R Chapter 1: Overview of ISE and Synthesis Tools Figure 1-1: Project Navigator Sources Window This window consists of three tabs which provide project and file information for the user. and user documents and design source files associated with the selected Design View. the specified device. The use of partitions is covered in Chapter 5.xilinx.com ISE 9. Each tab is discussed in further detail below.

All information displayed in the Snapshots tab is read-only. HDL files have this + to show the entities (VHDL) or modules (Verilog) within the file.” If a file contains lower levels of hierarchy. Processes Tab The Processes tab is context sensitive and it changes based upon the source type selected in the Sources tab and the Top-Level Source in your project. core. The Processes tab provides access to the following functions: • • • • Add an Existing Source Create New Source View Design Summary Design Utilities Provides access to symbol generation. schematic. The icon indicates the file type (HDL file. for example). Snapshots Tab The Snapshots tab displays all snapshots associated with the project currently open in Project Navigator.com 15 . viewing command line history.1 In-Depth Tutorial www. You can open a file for editing by double-clicking on the filename. A snapshot is stored with the project for which it was taken. instantiation templates. Available processes vary depending on the synthesis tools you use. run and view your design. and synthesis and simulation sub-directories. see the ISE™ Help. View RTL or Technology Schematic. A snapshot is a copy of the project including all files in the working directory. For a complete list of possible source types and their associated icons. From the Processes tab. Processes Window This window contains one default tab called the Processes tab. and the snapshot can be viewed in the Snapshots tab. enabling subteams to do simultaneous development on the same design. ISE 9. Select Help > ISE Help Contents. Synthesis. Libraries Tab The Libraries tab displays all libraries associated with the project open in Project Navigator. and synthesis reports. • • User Constraints Provides access to editing location and timing constraints. the icon has a + to the left of the name. you can run the functions necessary to define.xilinx. You can view the reports. Using snapshots provides an excellent version control system. or text file. select the Index tab and search for “Source file types. user documents. You can expand the hierarchy by clicking the +. Synthesis Provides access to Check Syntax.Overview of ISE R Each file in a Design View has an associated icon. and source files for all snapshots. and simulation library compilation.

Warnings. right-click the mouse. and information messages. expand Design Utilities and select View Command Line Log File. In addition to displaying errors. and select Go to Answer Record from the right-click menu. Generate Programming File Provides access to configuration tools and bitstream generation. Error Navigation to Answer Record You can navigate from an error or warning message in the Transcript window to relevant Answer Records on the www. The default web browser opens and displays all Answer Records applicable to this message. design flow reports.xilinx. right-click the mouse. Other console messages are filtered out. Tcl Shell Is a user interactive console. while warnings have a yellow exclamation mark (!).R Chapter 1: Overview of ISE and Synthesis Tools • • Implement Design Provides access to implementation tools. Note: To view a running log of command line arguments used on the current project. when you run the Implement Design process. select the error or warning message. warnings and informational messages. Find in Files. and select Go to Source from the right-click menu. Error Navigation to Source You can navigate from a synthesis error or warning message in the Transcript window to the location of the error in a source HDL file. • Find in Files Displays the results of the Edit > Find in Files function. the Tcl Shell allows a user to enter Project Navigator specific Tcl commands. To navigate to the Answer Record(s).com ISE 9. select the error or warning message. For more information on Tcl commands. Errors Displays only error messages. and point tools. • • • Warnings Displays only warning messages. To do so. Errors. See the Command Line Implementation section of Chapter 5. Other console messages are filtered out. Transcript Window The Transcript window contains five default tabs: Console. “Design Implementation” for further details.The HDL source file opens and the cursor moves to the line with the error. see the ISE Help.xilinx. This enables the user to select any process in the flow and the software automatically runs the processes necessary to get to the desired step.com/support website. • Console Displays errors.1 In-Depth Tutorial . 16 www. The Processes tab incorporates automake technology. Project Navigator also runs the Synthesis process because implementation is dependent on up-todate synthesis results. Errors are signified by a red (X) next to the message. warnings. Tcl Shell. For example.

enter the snapshot name and any comments associated with the snapshot. The snapshot containing all of the files in the project directory along with project settings is displayed in the Snapshots tab. Text Editor Source files and other text documents can be opened in a user designated editor. ISE 9. it replaces the project in your current session. The Schematic Editor can be used to graphically create and view logical designs. which is a catalog of ABEL. Restoring a Snapshot Since snapshots are read-only. a device utilization summary. The default editor is the ISE Text Editor. You can access the Language Templates. Tcl and User Constraints File templates that you can use and modify in your own design. VHDL. Select Project > Take Snapshot. For details. Verilog. Schematic Editor The Schematic Editor is integrated in the Project Navigator framework. A snapshot contains a copy of all of the files in the project directory. ISE Simulator / Waveform Editor ISE Simulator / Waveform Editor can be used to create and simulate test bench and test fixture within the Project Navigator framework.” Creating a Snapshot To create a snapshot: 1. refer to“Creating a Test Bench Waveform Using the Waveform Editor” in Chapter 4. ISE Text Editor enables you to edit source files and user documents. When you restore a snapshot. and summary information from all reports with links to the individual reports.com 17 . In the Take a Snapshot of the Project dialog box. Using Revision Control Features Using Snapshots Snapshots enable you to maintain revision control over the design.xilinx. Waveform Editor can be used to graphically enter stimuli and the expected response. including overview information. then generate a VHDL test bench or Verilog test fixture. expand ISE General and click Editors. See also “Snapshots Tab. 2. performance data gathered from the Place & Route (PAR) report.1 In-Depth Tutorial www. The editor is determined by the setting found by selecting Edit > Preferences. a snapshot must be restored in order to continue work.Using Revision Control Features R Workspace Design Summary The Design Summary lists high-level information about your project. constraints information.

Using Project Archives You can also archive the entire project into a single compressed file. Select Project > Source Contorl > Export 18 www.R Chapter 1: Overview of ISE and Synthesis Tools To restore a snapshot: 1. In the Snapshots tab. Note: Remote sources are copied with the snapshot and placed in a subdirectory named remote_sources. Restoring an Archive You cannot restore an archived file directly into Project Navigator. To review a process report or verify process status within a snapshot: 1.com ISE 9. see the ISE Help. Expand the snapshot source tree and select the desired source file. For more information. In the Create Zip Archive dialog box. Select Project > Make Snapshot Current. enter the archive name and location. 2. Before the snapshot replaces the current project. Select Project > Archive.” The Export/Import processes are typically used in conjunction with a 3rd party source control system but can be used independently as a valid means of backing up a design. 2. This allows for easier transfer over email and storage of numerous projects in a limited space. Remote sources are included in the archive under a folder named remote_sources . Right-click the mouse over the desired process report. select the snapshot from the drop-down list. Using Export/Import Source Control You can use this feature to export to and retrieve project files and sources from a “staging area. select Open Without Updating. These files will need to be manually copied to the original location or added to the project again in a new directory Viewing a Snapshot The Snapshots tab contains a list of all the snapshots available in the current project.xilinx.1 In-Depth Tutorial . Creating an Archive To create an archive: 1. Exporting a Project To export a project 1. From the menu. Note: The archive contains all of the files in the project directory along with project settings. 3. The compressed file can be extracted with any ZIP utility and you can then open the extracted file in Project Navigator. 2. you are given the option to place the current project in a snapshot so that your work is not lost.

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Follow the Export Project Wizard to dertermine which files to export, where to export the files to, and optionally create a Tcl script that can be used to regenerate the ISE project.

Importing a Project
To import a project 1. 2. Select Project > Source Contorl > Import Select the Project File (.ise or Tcl import script) and directory location to import the project file and sources.

Overview of Synthesis Tools
You can synthesize your design using various synthesis tools. The following section lists the supported synthesis tools and includes some process properties information.

Precision Synthesis
This synthesis tool is not part of the ISE package and is not available unless purchased separately. Two commonly used properties are Optimization Goal and Optimization Effort. With these properties you can control the synthesis results for area or speed and the amount of time the synthesizer runs.This synthesis tool is available for both an HDL- and Schematic-based design flow.

Process Properties
Process properties enable you to control the synthesis results of Precision. Most of the commonly used synthesis options available for the Precision stand-alone version are available for Precision synthesis through ISE. For more information, see the Precision online help.

Figure 1-2:

Precision Synthesis Process Properties

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Synplify/Synplify Pro
This synthesis tool is not part of the ISE package and is not available unless purchased separately. This synthesis tool is available for HDL-based designs, but it is not available for a schematic-based design.

Process Properties
Process properties enable you to control the synthesis results of Synplify/Synplify Pro. Most of the commonly used synthesis options available in the Synplify/Synplify Pro stand-alone version are available for Synplify/Synplify Pro synthesis through ISE. For more information, see the Synplify/Synplify Pro online help.

Figure 1-3:

Synplify/Synplify Pro Synthesis Process Properties

Xilinx Synthesis Technology (XST)
This synthesis tool is part of the ISE package and is available for both an HDL- and Schematic-based design flow.

Process Properties
Process properties enable you to control the synthesis results of XST. Two commonly used properties are Optimization Goal and Optimization Effort. With these properties you can control the synthesis results for area or speed, and the amount of time the synthesizer runs. More detailed information is available in the XST User Guide, available in the collection of software manuals. From ISE, select Help > Software Manuals, or go on the web at http://www.xilinx.com/support/sw_manuals/xilinx9/.

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Figure 1-4:

XST Synthesis Process Properties

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” After the design is successfully defined.1 In-Depth Tutorial www. “Design Implementation”). Synplify/Synplify Pro. and configure and download to the Spartan-3A demo board (Chapter 7.xilinx. software features. and design flow practices you can apply to your own design. “iMPACT Tutorial”). run implementation with the Xilinx Implementation Tools (Chapter 5. or Precision. The design is composed of HDL elements and two cores.com 23 . ISE 9. unless otherwise noted. This design targets a Spartan™-3A device. you will perform behavioral simulation (Chapter 4. You can synthesize the design using Xilinx Synthesis Technology (XST). all of the principles and flows taught are applicable to any Xilinx® device family. “Timing Simulation”).R Chapter 2 HDL-Based Design This chapter includes the following sections: • • • • • “Overview of HDL-Based Design” “Getting Started” “Design Description” “Design Entry” “Synthesizing the Design” Overview of HDL-Based Design This chapter guides you through a typical HDL-based design procedure using a design of a runner’s stopwatch. however. perform timing simulation (Chapter 6. “Behavioral Simulation”). The design example used in this tutorial demonstrates many device features. This chapter is the first chapter in the “HDL Design Flow.

htm. You will need to decide which HDL language you would like to work through for the tutorial. unzip the tutorial projects into the c:\xilinx\ISEexamples directory. substitute your installation path for c:\xilinx91i in the procedures that follow.com/support/techsup/tutorials/tutorials9. When you unzip the tutorial project files into c:\xilinx\ISEexamples.8. this tutorial does not go over the mixed language feature. This tutorial assumes that the software is installed in the default location c:\xilinx91i. and may be used in place of the Xilinx Synthesis Tool (XST): • • Synplicity Synplify/Synplify PRO 8. the directory wtut_vhd (for a VHDL design flow) or wtut_ver (for a Verilog design flow) is created within c:\xilinx\ISEexamples. and download the appropriate files for that language. replacing any existing files in that directory. noting differences where applicable. and applies to both designs simultaneously.xilinx.1i Spartan-3A libraries and device files Note: For detailed software installation instructions. Optional Software Requirements The following third-party synthesis tools are incorporated into this tutorial. 24 www. and the tutorial files are copied into the newlycreated directory. and may be used in place of the ISE Simulator: • ModelSim VHDL or Verilog? This tutorial supports both VHDL and Verilog designs.1 In-Depth Tutorial .R Chapter 2: HDL-Based Design Getting Started The following sections describe the basic requirements for running the tutorial. Installing the Tutorial Project Files The Stopwatch tutorial projects can be downloaded from http://www. refer to the ISE Release Notes and Installation Guide.xilinx.02 (or above) Mentor Precision Synthesis 2006a2.com ISE 9. Required Software To perform this tutorial. If you have installed the software in a different location. you must have the following software and software components installed: • • Xilinx Series ISE™ 9. After you have downloaded the tutorial project files from the Web. Download either the VHDL or the Verilog design flow project files.7 (or above) The following third-party simulation tool is optional for this tutorial. XST can synthesize a mixed-language design. However.

Table 2-1: Tutorial Directories Directory wtut_vhd wtut_ver wtut_vhd\wtut_vhd_comple ted wtut_ver\wtut_ver_comple ted Description Incomplete VHDL Source Files Incomplete Verilog Source Files Completed VHDL Source Files Completed Verilog Source Files Note: Do not overwrite any files in the solution directories. ISE 9. but you can unzip the source files into any directory with read-write permissions.xilinx.Getting Started R The following table lists the locations of tutorial source files. Creating a New Project: Using the New Project Wizard 1. The completed directories contain the finished HDL source files. The New Project Wizard appears. If you unzip the files into a different location. Figure 2-1: Project Navigator Desktop Icon Creating a New Project Note: Two methods are provided for creating a new project: Using the New Project Wizard and Using a Tcl Script. This tutorial assumes that the files are unzipped under c:\xilinx\ISEexamples. Starting the ISE Software To start ISE: Double-click the ISE Project Navigator icon on your desktop or select Start > All Programs > Xilinx ISE 9. substitute your project path for c:\xilinx\ISEexamples in the procedures that follow.1 In-Depth Tutorial www. Use either method provided below.1i > Project Navigator. select File > New Project. From Project Navigator.com 25 .

com ISE 9.R Chapter 2: HDL-Based Design Figure 2-2: New Project Wizard . Type wtut_vhd or wtut_ver in the Project Name field.xilinx.Device Properties 26 www.Create New Project 2. Verify that HDL is selected as the Top-Level Source Type and click Next.Device Properties window appears. The New Project Wizard . 4. 3. In the Project Location field.1 In-Depth Tutorial . browse to c:\xilinx\ISEexamples or to the directory in which you installed the project. Figure 2-3: New Project Wizard .

2. Change the current working directory to the directory where the tutorial source files were unzipped by typing cd c:/xilinx/ISEexamples/wtut_vhd (VHDL design entry) or cd c:/xilinx/ISEexamples/wtut_ver (Verilog design entry)..Getting Started R 5. select the Tcl Shell tab.xilinx. verify that all added HDL files are associated with Synthesis/Imp + Simulation. Browse to c:\xilinx\ISEexamples\wtut_vhd or c:\xilinx\ISEexamples\wtut_ver. 3. 8.v files for Verilog design entry) and click Open. and then click Add Source in the New Project Wizard .tcl (Verilog design entry). With Project Navigator open. right-click on the device line and select Properties.Add Existing Sources window. Change the Preferred Language: to VHDL. Click Next. (VHDL only) Once the project is created and opened. 6.. 7. ISE 9. Creating a New Project: Using a Tcl Script 1. In the Adding Source Files dialog box.1 In-Depth Tutorial www. Click Next. This will determine the default language for all processes that generate HDL files. then Finish to complete the New Project Wizard. ♦ ♦ ♦ ♦ clk_div_262k lcd_control statmach stopwatch 9.vhd files for VHDL design entry or . Select the following files (.com 27 . Select the following values in the New Project Wizard . This will determine the default language for all processes that generate HDL files. 4. then click OK. then Next.Device Properties window: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Product Category: All Family: Spartan3A and Spartan3AN Device: XC3S700A Package: FG484 Speed: -4 Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: VHDL or Verilog depending on preference. 10. Run the project creation Tcl script by typing source create_wtut_vhd.tcl (VHDL design entry) or source create_wtut_ver. Stopping the Tutorial You may stop the tutorial at any time and save your work by selecting File > Save All.

com ISE 9. Throughout the tutorial. In clocking mode it displays the current clock value in the ‘Lap’ display area. The following list summarizes the input and output signals of the design. • sf_d[7:0] Provides the data values for the LCD display. The lower-level macros are either HDL modules or IP modules. • • • reset Puts the stopwatch in clocking mode and resets the time to 0:00:00. Outputs The following are outputs signals for the design. clk Externally generated system clock. lcd_rs. This input is only functional while the clock or timer is not counting. In timer mode it loads the pre assigned values from the ROM to the timer display when the timer is not counting. This is an active low signal which acts like the start/stop button on a runner’s stopwatch. lcd_rw These outputs are the control signals for the LCD display of the Spartan-3A demo board used to display the stopwatch times.xilinx. mode Toggles between clocking and timer modes. When the design is complete. which means that the top-level design file is an HDL file that references several other lower-level macros. HDL-based design. • lcd_e. you will complete the design by generating some of the modules from scratch and by completing others from existing files. you will simulate it to verify the design’s functionality.R Chapter 2: HDL-Based Design Design Description The design used in this tutorial is a hierarchical.1 In-Depth Tutorial . The design begins as an unfinished design. there are five external inputs and four external output buses. Functional Blocks The completed design consists of the following functional blocks. The system clock is an externally generated signal. • lap_load This is a dual function signal. Inputs The following are input signals for the tutorial stopwatch design. In the runner’s stopwatch design. • clk_div_262k 28 www. • strtstop Starts and stops the stopwatch.

the Sources tab displays all of the source files currently added to the project.ise or wtut_ver.com 29 . and add a CORE Generator and a Clocking module. In the current project. • debounce Schematic module implementing a simplistic debounce circuit for the strtstop.2144 MHz clock into 100 Hz 50% duty cycle clock.1 In-Depth Tutorial www. statmach State Machine module defined and implemented in State Diagram Editor. correct syntax errors.144.2144 MHz. Controls the state of the stopwatch.xilinx. All procedures used in the tutorial can be used later for your own designs. ISE 9. The CLKFX_OUT output converts the 50 MHz clock of the Spartan-3A demo board to 26. you will examine HDL files. This macro has five 4-bit outputs. and lap_load input signals.ise project open in Project Navigator. • time_cnt Up/down counter module which counts between 0:00:00 to 9:59:99 decimal. • • lcd_control Module controlling the initialization of and output to the LCD display. This macro contains 64 preset times from 0:00:00 to 9:59:99 which can be loaded into the timer. which represent the digits of the stopwatch time. Design Entry For this hierarchical design. You will create and use each type of design macro. mode. • timer_preset CORE Generator™ 64x20 ROM. With the wtut_vhd. frequency controlled output. time_cnt is instantiated. with the associated entity or module names (see Figure 2-4). Converts 26. but the associated entity or module is not defined in the project. • dcm1 Clocking Wizard macro with internal feedback. create an HDL macro. and duty-cycle correction.Design Entry R Macro which divides a clock frequency by 262.

Select Project > Add Source.xilinx. 30 www. 3.v in the Sources tab. Checking the Syntax To check the syntax of source files: 1.R Chapter 2: HDL-Based Design Instantiated components with no entity or module declaration are displayed with a red question mark. 1. Select stopwatch.<architecture name> . 2. An additional file must be added.vhd or stopwatch.com ISE 9.vhd The red question-mark (?) for time_cnt should change to show the VHD file icon.1 In-Depth Tutorial . the Processes tab displays all processes available for this file.vhd file could be added to the project by entering the following command in the Tcl Shell tab. When you select the HDL file. Select time_cnt. In the Processes tab. Three HDL files have already been added to this project.<entity name> . Figure 2-4: Sources Tab Showing Completed Design Adding Source Files HDL files must be added to the project before they can be synthesized. xfile add time_cnt.v from the project directory and click Open.vhd File in Sources Tab Each source Design unit is represented under the sources tab using the following syntax: <instance name> . the time_cnt. Figure 2-5: time_cnt. In the Adding Source Files dialog box. verify that time_cnt is associated with Synthesis/Imp + Simulation and click OK.(<file name>). 2.vhd or time_cnt. click the + next to Synthesize to expand the process hierarchy. Note: Alternatively.

Double-click Check Syntax in the Synthesize hierarchy. Select File > Save to save the file. The red “x” beside the Check Syntax process indicates an error was found during the analysis. To display the error in the source file: 1. Correcting HDL Errors The time_cnt module contains a syntax error that must be corrected. Correct any errors in the HDL source file. Note: Check Syntax is not available when Synplify is selected as the synthesis tool.xilinx. ISE 9. 3.Design Entry R 3. The source code comes up in the main display tab. In the Console tab of the Transcript window.1 In-Depth Tutorial www. Project Navigator reports errors with a red (X) and warnings with a yellow (!). 2. Re-analyze the file by selecting the HDL file and double-clicking Check Syntax.com 31 . 4. The comments next to the error explain this simple fix. Click the file name in the error message in the Console or Errors tab.

Figure 2-6: New Source Wizard for Verilog 32 www. mode and lap_load inputs. 3. The dialog box New Source Wizard opens in which you specify the type of source you want to create. specifying the name and ports of the component. b. The resulting HDL file is then modified in the ISE Text Editor. With ISE. Using the New Source Wizard and ISE Text Editor In this section. c. Click Next. This macro will be used to debounce the strtstop. In the File Name field. clk and sig_out. Select VHDL Module or Verilog Module.1 In-Depth Tutorial . Select Project > New Source.xilinx.R Chapter 2: HDL-Based Design Creating an HDL-Based Module Next you will create a module from HDL code. 2. To create the source file: 1.com ISE 9. Set the Direction field to input for sig_in and clk and to output for sig_out. In the first three Port Name fields type sig_in. 4. Leave the Bus designation boxes unchecked. You will author a new HDL module. The HDL code is then connected to your toplevel HDL design through instantiation and is compiled with the rest of the design. you can easily create modules from HDL code using the ISE Text Editor. type debounce. Enter two input ports named sig_in and clk and an output port named sig_out for the debounce component in this way: a. you create a file using the New Source wizard. 5.

1 In-Depth Tutorial www. Figure 2-7: VHDL File in ISE Text Editor Figure 2-8: Verilog File in ISE Text Editor ISE 9.xilinx. Click Next to complete the Wizard session. 7.Design Entry R 6. A description of the module displays. The Verilog HDL file is displayed in Figure 2-8. Click Finish to open the empty HDL file in the ISE Text Editor.com 33 . The VHDL file is displayed in Figure 2-7.

Use the appropriate template for the language you are using.com ISE 9. the ports are already declared in the HDL file. expand the Misc hierarchy. Using the Language Templates The ISE Language Templates include HDL constructs and synthesis templates which represent commonly used logic components. Note: You can add your own templates to the Language Templates for components or constructs that you use often. and primitives. You will use the Debounce Circuit template for this exercise. Device Primitive Instantiation. and values are black.1 In-Depth Tutorial . Under either the VHDL or Verilog hierarchy. To invoke the Language Templates and select the template for this tutorial: 1. expand the Coding Examples hierarchy. select Edit > Language Templates. Synthesis Constructs and User Templates. The file is color-coded to enhance readability and help you recognize typographical errors.] Debounce Circuit. Keywords are displayed in blue. 2. D flip-flops. Each HDL language in the Language Templates is divided into five sections: Common Constructs. comments in green. 34 www.xilinx. such as counters. the HDL code for a debounce circuit is displayed in the right pane. multiplexers. click the + next to the section. expand the Synthesis Constructs hierarchy. Simulation Constructs.R Chapter 2: HDL-Based Design In the ISE Text Editor. and select the template called [One-shot. Click any of the listed templates to view the template contents in the right pane. and some of the basic file structure is already in place. Upon selection. From Project Navigator. To expand the view of any of these sections.

xilinx. (Verilog only) Complete the Verilog module by doing the following: a. b. 2. Select Window > Tile Vertically to show both the HDL file and the Language Templates window.com 35 . 3. Remove the reset logic (not used in this design) by deleting the three lines beginning with if and ending with else. Refer to “Working with Language Templates” in the ISE Help for additional usability options. ISE 9. Change <reg_name> to q in all six locations. 4.vhd file under the architecture begin statement.Design Entry R Figure 2-9: Language Templates Adding a Language Template to Your File You will now use the drag and drop method for adding templates to your HDL file. Close the Language Templates window.v file under the module and pin declarations. Click and drag the Debounce Circuit name from the Language Template topology into the debounce. or into the debounce.1 In-Depth Tutorial www. To add the template to your HDL file using the drag and drop method: 1.

c. 3. Change <clock> to clk. select Project > New Source. Depth: 64 . 5. math functions and communications and IO interface cores. Memory Type: ROM Click Next. b. Type timer_preset in the File name field. 9. you will create a CORE Generator module called timer_preset.Defines the width of the output bus.. 6. lines. Creating a CORE Generator Module CORE Generator is a graphical interactive design tool that enables you to create high-level modules such as memory elements. The module will be used to store a set of 64 values to load into the timer. 36 www. Move the line beginning with the word signal so that it is between the architecture and begin keywords. and <output> to sig_out. Use Edit > Replace to change <clock> to clk. then double-click RAMs & ROMs..xilinx. In the Processes tab. and ending with else and delete one of the end if. Select one of the debounce instances in the Sources tab. Remove the reset logic (not used in this design) by deleting the five lines beginning with if (<reset>.com ISE 9. Fill in the Distributed Memory Generator customization GUI with the following settings: ♦ ♦ ♦ ♦ ♦ ♦ 7. Click Next. (VHDL only) Complete the VHDL module by doing the following: You now have complete and functional HDL code.R Chapter 2: HDL-Based Design c. This customization GUI enables you to customize the memory to the design specifications. <input> to sig_in. Close the ISE Text Editor. Creating a CORE Generator Module To create a CORE Generator module: 1. 2. 8. 5. You can customize and pre-optimize the modules to take advantage of the inherent architectural features of the Xilinx FPGA architectures. then click Next and click Finish to open the Distributed Memory Generator customization GUI. Select IP (Coregen & Architecture Wizard). such as Fast Carry Logic. a. SRL16s. D_IN to sig_in. and Q_OUT to sig_out. Select Distributed Memory Generator. double-click Check Syntax. Leave Input and output options as Non Registered.Defines the name of the module. In Project Navigator. 7. Save the file by selecting File > Save. Click Next. 4.Defines the number of values to be stored Data Width: 20 . 6.1 In-Depth Tutorial . and distributed and block RAM. In this section. Double-click Memories & Storage Elements. Component Name: timer_preset .

Some of these files are: ♦ timer_preset.v These are HDL wrapper files for the core and are used only for simulation. CORE Generator .xilinx. timer_preset.veo These are the instantiation templates used to incorporate the CORE Generator module into your source HDL. timer_preset. Click Finish.coe. The module is created and automatically added to the project library. ♦ ♦ ♦ timer_preset.mif This file provides the initialization values of the ROM for simulation.vho or timer_preset.xco This file stores the configuration information for the timer_preset module and is used as a project source. ISE 9.1 In-Depth Tutorial www. Figure 2-10: 8.vhd or timer_preset. ♦ timer_preset.Design Entry R ♦ Coefficients File: Click the Browse button and select definition1_times.edn This file is the netlist that is used during the Translate phase of implementation.Distributed Memory Generator Customization GUI Check that only the following pins are used (used pins are highlighted on the symbol on the left side of the customization GUI): ♦ ♦ a[5:0] spo[19:0] 9.com 37 . Note: A number of files are added to the project directory.

6. instantiate the CORE Generator module in the HDL code using either a VHDL flow or a Verilog flow. 2. In Project Navigator.vho and click Open. Figure 2-12: VHDL Component Instantiation of CORE Generator Module 38 www. 9. double-click stopwatch. 8. Place your cursor after the line that states: -. Select Edit > Cut. then select timer_preset.vhd to open the file in ISE Text Editor.1 In-Depth Tutorial .Insert CORE Generator ROM component declaration here Select Edit > Insert File. Figure 2-11: 4. 3. VHDL Flow To instantiate the CORE Generator module using a VHDL flow: 1. 7.Begin Cut here for INSTANTIATION Template ---- to --INST_TAG_END -----.END INSTANTIATION Template ----- 5. VHDL Component Declaration for CORE Generator Module Highlight the inserted code from -. Edit this instantiated code to connect the signals in the Stopwatch design to the ports of the CORE Generator module as shown in Figure 2-12.R Chapter 2: HDL-Based Design Instantiating the CORE Generator Module in the HDL Code Next.xilinx.com ISE 9. Change the instance name from your_instance_name to t_preset. Place the cursor after the line that states: --Insert CORE Generator ROM Instantiation here Select Edit > Paste to place the core instantiation. The VHDL template file for the CORE Generator instantiation is inserted.

Edit this code to connect the signals in the Stopwatch design to the ports of the CORE Generator module as shown in Figure 2-13. 2. Delete these commented lines if desired. In this section you will create a basic DCM module with CLK0 feedback and duty-cycle correction. and close the ISE Text Editor. a part of the Xilinx Architecture Wizard. Creating a DCM Module The Clocking Wizard. 3. Delete these commented lines if desired.veo contains several lines of commented text for instruction and legal documentation. 4. select FPGA Features and Design > Clocking > Spartan3E. In the Select IP dialog box. select Project > New Source. select IP (CoreGen & Architecture Wizard) source and type dcm1 for the file name. enables you to graphically select Digital Clock Manager (DCM) features that you wish to use. 2. 6. 4. Spartan-3A > Single DCM SP.com 39 . double-click stopwatch.v in the ISE Text Editor. In the New Source dialog box.xilinx.veo. Figure 2-13: Verilog Component Instantiation of the CORE Generator Module 7. 3. and select timer_preset.vho contains several lines of commented text for instruction and legal documentation. Save the design using File > Save and close stopwatch. The inserted code of timer_preset. In Project Navigator. The inserted code of timer_preset.1 In-Depth Tutorial www. Verilog Flow To instantiate the CORE Generator module using a Verilog flow: 1. Using the Clocking Wizard To create the dcm1 module: 1.Design Entry R 10.v to open the file in the ISE Text Editor. In Project Navigator. Click Next. ISE 9. Save the design using File > Save. 5. 11. Change the instance name from YourInstanceName to t_preset. Place your cursor after the line that states: //Place the Coregen module instantiation for timer_preset here Select Edit > Insert File.

and then click Next again. 12. 13. 7. 9. 8. Select CLKFX port.1 In-Depth Tutorial .xaw file is added to the list of project source files in the Sources tab. Verify the following settings: ♦ ♦ ♦ ♦ ♦ Phase Shift: NONE CLKIN Source: External. Verify that RST. Click Next. Click OK. ( 26. 40 www. 11.2144Mhz ) ⁄ 2 18 = 100Hz 15.xilinx. then Finish.com ISE 9. Select Use output frequency and type 26. The Clocking Wizard is launched.2144 in the box and select MHz. CLK0 and LOCKED ports are selected. 14.R Chapter 2: HDL-Based Design Figure 2-14: Selecting Single DCM IP Type 5. Single Feedback Source: Internal Feedback Value: 1X Use Duty Cycle Correction: Selected 10. and then click Finish. Click the Advanced button. 6. Select Wait for DCM lock before DONE Signal goes high. Click Next. Type 50 and select MHz for the Input Clock Frequency. The dcm1. Click Next.

right-click View HDL Instantiation Template and select Properties. double-click View HDL Instantiation Template.Insert dcm1 component declaration here. 5. select dcm1. Highlight the instantiation template in the newly opened HDL Instantiation Template. 3.VHDL Design Next. In the Processes tab.vhd file in a section labeled -. 7.Design Entry R Instantiating the dcm1 Macro . Select Edit > Copy. shown below. Choose VHDL for the HDL Instantiation Template Target Language value and click OK. shown below. 9.xilinx. In Project Navigator. Figure 2-15: 6. you will instantiate the dcm1 macro for your VHDL or Verilog design. Place the cursor in the stopwatch.Insert dcm1 instantiation here”. Select Edit > Copy. Highlight the component declaration template in the newly opened HDL Instantiation Template (dcm1. VHDL DCM Component Declaration Place the cursor in the stopwatch.1 In-Depth Tutorial www. VHDL DCM Component Instantiation 11. Figure 2-16: 10. To instantiate the dcm1 macro for the VHDL design: 1. In the Processes tab. Select Edit > Paste to paste the component declaration.vhi).com 41 . in the Sources tab. 8. 4. ISE 9.vhd file below the line labeled “-.xaw. 2.

Make the necessary changes as shown in the figure below. 5.R Chapter 2: HDL-Based Design 12.com ISE 9.xaw. dcm1 Macro and Instantiation Templates Paste the instantiation template into the section in stopwatch. 2. in the Sources tab. Select File > Save to save the stopwatch. Figure 2-17: VHDL Instantiation for dcm1 14. Instantiating the dcm1 Macro .1 In-Depth Tutorial . Figure 2-18: 4. copy the instantiation template. Select Edit > Paste to paste the instantiation template. 3.Verilog To instantiate the dcm1 macro for your Verilog design: 1.v labeled //Insert dcm1 instantiation here. 42 www.vhd file.tfi). In the Processes tab. 13. In Project Navigator. shown below.v file. Select File > Save to save the stopwatch. From the newly opened HDL Instantiation Template (dcm1. Figure 2-19: Verilog Instantiation for dcm1 6. select dcm1. double-click View HDL Instantiation Template. Make the necessary changes as shown in the figure below.xilinx.

Synthesizing the Design R Synthesizing the Design So far you have been using XST (the Xilinx synthesis tool) for syntax checking. you may not have the software installed or may not have it configured in ISE. Changing the design flow results in the deletion of implementation data. Next. The synthesis tool performs three general steps (although all synthesis tools further break down these general steps) to create the netlist: • • Analyze / Check Syntax Checks the syntax of the source code. For projects that contain implementation data. Xilinx recommends that you take a snapshot of the project before changing the ISE 9. The synthesis tool can be changed at any time during the design flow. 2.1 In-Depth Tutorial www. • Map Translates the components from the compile stage into the target technology’s primitive components. Figure 2-20: Specifying Synthesis Tool Note: If you do not see your synthesis tool among the options in the list. you will synthesize the design using either XST. The Synthesis tools are configured in the Preferences dialog box (Edit > Preferences. Select the targeted part in the Sources tab. click on the Synthesis Tool value and use the pulldown arrow to select the desired synthesis tool from the list. Select Source > Properties. You have not yet created any implementation data in this tutorial. The synthesis tool uses the design’s HDL code and generates a supported netlist type (EDIF or NGC) for the Xilinx implementation tools. 3. In the Project Properties dialog box. Synplify/Synplify Pro or Precision. To change the synthesis tool: 1. Compile Translates and optimizes the HDL code into a set of components that the synthesis tool can recognize.com 43 . then click Integrated Tools). expand ISE General.xilinx.

xcf file: 44 www.xilinx. you may add the .xcf file extension.xcf 4.*) and then select and add stopwatch. the HDL files are translated into gates and optimized for the target architecture. Notice that stopwatch. Entering Constraints XST supports a User Constraint File (UCF) style syntax to define synthesis and timing constraints. To create a new Xilinx Constraint File: 1. XST uses the . Generate Post-Synthesis Simulation Model Creates HDL simulation models based on the synthesis netlist. Note: In place of the three steps above. the next step is to synthesize the design. View Technology Schematic Generates a schematic view of your Technology netlist.xcf.1 In-Depth Tutorial . For more information about taking a snapshot. In the Add Existing Sources dialog box. change the Files of type: to ‘All Files (*.xcf to open the file in the ISE Text Editor. The following constraints should exist in the stopwatch. Check Syntax Verifies that the HDL code is entered properly. and the file has an . • • • • View RTL Schematic Generates a schematic view of your RTL netlist. During synthesis. 2. 3.com ISE 9. Select Project > Add Source. A summary of available synthesis tools is available in “Overview of Synthesis Tools” in Chapter 1 Read the section for your synthesis tool: • • • “Synthesizing the Design using XST” “Synthesizing the Design using Synplify/Synplify Pro” “Synthesizing the Design Using Precision Synthesis” Synthesizing the Design using XST Now that you have created and analyzed the design.R Chapter 2: HDL-Based Design synthesis tool to preserve this data. using the following command and then selecting View > Refresh. xfile add stopwatch.xcf extension to determine if the file is a constraints file. Processes available for synthesis using XST are as follows: • View Synthesis Report Gives a synthesis mapping and timing summary as well as a list of optimizations that took place. Double-click stopwatch.xcf file through the Tcl Shell.xcf is added as a User Document. 5. This format is called the Xilinx Constraint File (XCF). see “Creating a Snapshot” in Chapter 1.

Double-click the Synthesize process in the Processes tab. 6. LOC = "Y16". LOC = "AB17". Select stopwatch. LOC = "AB18". Select stopwatch. BEGIN MODEL stopwatch NET "sf_d<7>" NET "sf_d<6>" NET "sf_d<5>" NET "sf_d<4>" NET "sf_d<3>" NET "sf_d<2>" NET "sf_d<1>" NET "sf_d<0>" END. LOC = "Y13". 3.v).Post-synthesis view of the HDL design mapped to the target technology. LOC = "AA12". LOC = "Y15".xcf. LOC = "AB12". Click OK. There are two forms of the schematic representation: • • RTL View . Other options include controlling the maximum fanout of a flip-flop output or setting the desired frequency of the design. 2. One commonly used option is to control synthesis to make optimizations based on area or speed.com 45 . ISE 9.xcf.Pre-optimization of the HDL code. click in the Synthesis Constraints File property field and enter stopwatch.v) in the Sources tab. right-click the Synthesize process and select Properties. Close stopwatch. Check the Write Timing Constraints box. see “Using the Constraints Editor” and “Using the Floorplan Editor” in Chapter 5.1 In-Depth Tutorial www. To enter synthesis options: 1. LOC = "AB16". Note: For more constraint options in the implementation tools. The RTL / Technology Viewer XST can generate a schematic representation of the HDL code that you have entered.vhd (or stopwatch.Synthesizing the Design R NET "CLK" TNM_NET = "CLK_GROUP". 4. 2. Technology View . Synthesizing the Design Now you are ready to synthesize your design. Under the Synthesis Options tab. TIMESPEC “TS_CLK”=PERIOD “CLK_GROUP” 20 ns.” Entering Synthesis Options Synthesis options enable you to modify the behavior of the synthesis tool to make optimizations according to the needs of the design.vhd (or stopwatch. A schematic view of the code helps you analyze your design by displaying a graphical connection between the various components that XST has inferred.xilinx. In the Processes tab. “Design Implementation. 5. To take the HDL code and generate a compatible netlist: 1.

” to place and route the design. options. click the + next to Synthesize to expand the process hierarchy. 46 www.com ISE 9. see the XST User Guide. or from the web at http://www. Double-click on the symbol to push into the schematic and view the various design elements and connectivity. reports. This guide is available in the collection of software manuals and is accessible from ISE by selecting Help > Software Manuals. Right-click the schematic to view the various operations that can be performed in the schematic viewer. Figure 2-21: RTL Viewer You have completed XST synthesis. “Design Implementation. 2.” to perform a pre-synthesis simulation of this design. An NGC file now exists for the Stopwatch design. or running XST from the command line. The RTL Viewer displays the top level schematic symbol for the design. Note: For more information about XST constraints. To continue with the HDL flow: • Go to Chapter 4.R Chapter 2: HDL-Based Design To view a schematic representation of your HDL code: 1. In the Processes tab.com/support/sw_manuals/xilinx9/. “Behavioral Simulation. Double-click View RTL Schematic or View Technology Schematic.xilinx. OR • Proceed to Chapter 5.1 In-Depth Tutorial .xilinx.

5.vhd (or stopwatch. the HDL files are translated into gates and optimized to the target architecture. inferred memory.v).v).xilinx.1 In-Depth Tutorial www. clicking Synthesize in the Processes tab. The report consists of the following four sections: • • • • “Compiler Report” “Mapper Report” “Timing Report” “Resource Utilization” Compiler Report The compiler report lists each HDL file that was compiled. Note: This step can also be done by selecting stopwatch. 2. the next step is to synthesize the design. • View RTL Schematic Accessible from the Launch Tools hierarchy. unused ports.edn) for a black box exists in the project directory. set the global synthesis options: 1. To access Synplify’s RTL viewer and constraints editor you must run Synplify outside of ISE. and removal of redundant logic. this process displays Synplify or Synplify Pro with a schematic view of your HDL code • View Technology Schematic Accessible from the Launch Tools hierarchy. the implementation tools merge the netlist into the design during the Translate phase. 3. Note: Black boxes (modules not read into a design environment) are always noted as unbound in the Synplify reports. 4. and displays the syntax checking result for each file that was compiled. The report also lists FSM extractions. Double-click the Synthesize process to run synthesis. Click OK to accept these values. In the Processes tab.com 47 .vhd (or stopwatch.ngc or . ISE 9. To synthesize the design. warnings on latches. Select stopwatch. and selecting Process > Run. Check the Write Vendor Constraint File box. As long as the underlying netlist (. this process displays Synplify or Synplify Pro with a schematic view of your HDL code mapped to the primitives associated with the target technology. double-click View Synthesis Report under the Synthesize process. names which file is the top level. In this step. Processes available in Synplify and Synplify Pro synthesis include: • View Synthesis Report Lists the synthesis optimizations that were performed on the design and gives a brief timing and mapping report.ngo.Synthesizing the Design R Synthesizing the Design using Synplify/Synplify Pro Now that you have entered and analyzed the design. . Examining Synthesis Results To view overall synthesis results. right-click the Synthesize process and select Properties.

The report lists the mapping results of flattened instances. and attributes set in the design.R Chapter 2: HDL-Based Design Mapper Report The mapper report lists the constraint files used. Figure 2-22: Synplify’s Estimated Timing Data Resource Utilization This section of the report lists all of the resources that Synplify uses for the given target technology. Processes available for Precision Synthesis include: • • Check Syntax Checks the syntax of the HDL code.” for the most accurate delay information. You have now completed Synplify synthesis. Synthesizing the Design Using Precision Synthesis Now that you have entered and analyzed the design.com ISE 9.” to perform a pre-synthesis simulation of this design. a netlist EDN file exists for the Stopwatch design. optimized flip-flops. At this point. Timing Report The timing report section provides detailed information on the constraints that you entered and on delays on parts of the design that had no constraints. “Behavioral Simulation. the HDL files are translated into gates and optimized to the target architecture. the next step is to synthesize the design. The delay values are based on wireload models and are considered preliminary. To continue with the HDL flow: • Go to Chapter 4. extracted counters.xilinx. In this step. and how FSMs were coded. “Design Implementation. View Log File 48 www. clock and buffered nets that were created. OR • Proceed to Chapter 5. the target technology.” to place and route the design.1 In-Depth Tutorial . “Design Implementation. Consult the post-place and route timing reports discussed in Chapter 5.

Synthesizing the Design

R

Lists the synthesis optimizations that were performed on the design and gives a brief timing and mapping report. • View RTL Schematic Accessible from the Launch Tools hierarchy, this process displays Precision with a schematic-like view of your HDL code • View Technology Schematic Accessible from the Launch Tools hierarchy, this process displays Precision with a schematic-like view of your HDL code mapped to the primitives associated with the target technology. • View Critical Path Schematic Accessible from the Launch Tools hierarchy, this process displays Precision with a schematic-like view of the critical path of your HDL code mapped to the primitives associated with the target technology.

Entering Synthesis Options through ISE
Synthesis options enable you to modify the behavior of the synthesis tool to optimize according to the needs of the design. For the tutorial, the default property settings will be used. 1. 2. Select stopwatch.vhd (or stopwatch.v) in the Sources tab. Double-click the Synthesize process in the Processes tab.

The RTL/Technology Viewer
Precision Synthesis can generate a schematic representation of the HDL code that you have entered. A schematic view of the code helps you analyze your design by seeing a graphical connection between the various components that Precision has inferred. To launch the design in the RTL viewer, double-click the View RTL Schematic process. The following figure displays the design in an RTL view.

Figure 2-23:

Stopwatch Design in Precision Synthesis RTL Viewer

You have now completed the design synthesis. At this point, an EDN netlist file exists for the Stopwatch design. To continue with the HDL flow:

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R

Chapter 2: HDL-Based Design

Go to Chapter 4, “Behavioral Simulation,” to perform a pre-synthesis simulation of this design. OR Proceed to Chapter 5, “Design Implementation,” to place and route the design.

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Chapter 3

Schematic-Based Design
This chapter includes the following sections: • • • • “Overview of Schematic-Based Design” “Getting Started” “Design Description” “Design Entry”

Overview of Schematic-Based Design
This chapter guides you through a typical FPGA schematic-based design procedure using the design of a runner’s stopwatch. The design example used in this tutorial demonstrates many device features, software features, and design flow practices that you can apply to your own designs. The stopwatch design targets a Spartan™-3A device; however, all of the principles and flows taught are applicable to any Xilinx® device family, unless otherwise noted. This chapter is the first in the “Schematic Design Flow.” In the first part of the tutorial, you will use the ISE™ design entry tools to complete the design. The design is composed of schematic elements, a state machine, a CORE Generator™ component, and HDL macros. After the design is successfully entered in the Schematic Editor, you will perform behavioral simulation (Chapter 4, “Behavioral Simulation”), run implementation with the Xilinx Implementation Tools (Chapter 5, “Design Implementation”), perform timing simulation (Chapter 6, “Timing Simulation”), and configure and download to the Spartan-3A (XC3S700A) demo board (see Chapter 7, “iMPACT Tutorial.”).

Getting Started
The following sections describe the basic requirements for running the tutorial.

Required Software
You must have Xilinx ISE 9.1i installed to follow this tutorial. For this design you must install the Spartan-3A libraries and device files. A schematic design flow is supported on Windows, Solaris, and Linux platforms.

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or select Start > All Programs > Xilinx ISE 9. at c:\xilinx.) • Unzip the tutorial design files in any directory with read-write permissions. Installing the Tutorial Project Files The tutorial project files can be downloaded to your local machine from http://www.com/support/techsup/tutorials/tutorials9. including schematic. If you have installed the software in a different location. Starting the ISE Software To launch the ISE software package: 1. This tutorial assumes that the files are unarchived under c:\xilinx\ISEexamples.com ISE 9. Note: For detailed instructions about installing the software.htm. The schematic tutorial project will be created in this directory). Download the Watch Schematic Design Files (wtut_sch. Figure 3-1: Project Navigator Desktop Icon Creating a New Project Two methods are provided for creating a new project: Using the New Project Wizard. 52 www. Double-click the ISE Project Navigator icon on your desktop. If you restore the files to a different location.1i > Project Navigator. HDL. substitute c:\xilinx for your installation path.1 In-Depth Tutorial . Do not overwrite files under this directory. wtut_sc\wtut_sc_completed\ (Contains the completed design files for the schematic-based tutorial design. The download contains two directories: • wtut_sc\ (Contains source files for schematic tutorial.1i Installation Guide and Release Notes. The schematic tutorial files are copied into the directories when you unzip the files.xilinx.xilinx. refer to the ISE 9. substitute c:\xilinx\ISEexamples with the project path.R Chapter 3: Schematic-Based Design This tutorial assumes that the software is installed in the default location. and State Machine files. and Using a Tcl Script.zip).

Getting Started R Creating a New Project: Using New Project Wizard 1.com 53 .Create New Project 2. Figure 3-2: New Project Wizard . Figure 3-3: New Project Wizard . Select Schematic as the Top-Level Source Type. and then click Next. 3. Type wtut_sc as the Project Name. From Project Navigator. select File > New Project. The New Project Wizard appears.1 In-Depth Tutorial www.xilinx. Notice that wtut_sc is appended to the Project Location value.Device Properties ISE 9. Browse to c:\xilinx\ISEexamples or enter the directory in the Project Location field. 4.

1. and that the .Device Properties window: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Product Category: All Family: Spartan3A and Spartan3AN Device: XC3S700A Package: FG484 Speed: -4 Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: VHDL or Verilog depending on preference. Stopping the Tutorial If you need to stop the tutorial at any time. and then click Add Source in the New Project Wizard . 11. Click OK.sch clk_div_262k. Type source create_wtut_sc. Creating a New Project: Using a Tcl Script With Project Navigator open. 54 www.dia file is associated with Synthesis/Implementation Only. select the Tcl Shell tab.R Chapter 3: Schematic-Based Design 5. This will determine the default language for all processes that generate HDL files.1 In-Depth Tutorial . 7.dia 9. Click Next twice. save your work by selecting File > Save All.Add Existing Sources window. then Finish to complete the New Project Wizard. a CORE Generator module. ♦ ♦ ♦ ♦ ♦ ♦ cd4rled.g. 8.vhd lcd_control.vhd stopwatch.tcl. a state machine module. (e. and HDL modules. Select the following files and click Open. 2.sch statmach. schematic-based design.xilinx. Type cd c:/xilinx/ISEexamples/wtut_sc). Change the current working directory to the directory where the tutorial source files were unzipped. Verify that all added schematic files are associated with Synthesis/Imp + Simulation. including schematicbased modules. Click Next. Design Description The design used in this tutorial is a hierarchical. an Architecture Wizard module. Browse to c:\xilinx\ISEexamples\wtut_sc. which means that the top-level design file is a schematic sheet that refers to several other lower-level macros. Select the following values in the New Project Wizard .sch ch4rled. 10. 6.com ISE 9. The lower-level macros are a variety of different types of modules.

Design Description R The runner’s stopwatch design begins as an unfinished design. After the design is complete. ISE 9. you will create these modules. instantiate them.xilinx. Throughout the tutorial. For more information about simulating your design. A schematic of the completed stopwatch design is shown in the following figure. see Chapter 4.1 In-Depth Tutorial www. you will complete the design by creating some of the modules and by completing others from existing files. you will simulate the design to verify its functionality. and their respective functions. and then connect them. “Behavioral Simulation.com 55 .” Figure 3-4: Completed Watch Schematic There are five external inputs and four external outputs in the completed design. The following sections summarize the inputs and outputs. Inputs The following are input signals for the tutorial stopwatch design. Through the course of this chapter.

statmach 56 www.R Chapter 3: Schematic-Based Design • strtstop Starts and stops the stopwatch.1 In-Depth Tutorial . In clocking mode it displays the current clock value in the ‘Lap’ display area. mode. frequency controlled output.144. In timer mode it will load the pre-assigned values from the ROM to the timer display when the timer is not counting. • sf_d[7:0] Provides the data values for the LCD display. lcd_rw These outputs are the control signals for the LCD display of the Spartan-3A demo board used to display the stopwatch times. • debounce Module implementing a simplistic debounce circuit for the strtstop. The CLKFX_OUT output converts the 50 MHz clock of the Spartan-3A demo board to 26.2144 MHz.com ISE 9. lcd_rs. Converts 26. mode Toggles between clocking and timer modes. The completed design consists of the following functional blocks. • lcd_e. • dcm1 Clocking Wizard macro with internal feedback. Most of these blocks do not appear on the schematic sheet in the project until after you create and add them to the schematic during this tutorial. and duty-cycle correction. • lap_load This is a dual function signal. • • lcd_control Module controlling the initialization of and output to the LCD display.2144 MHz clock into 100 Hz 50% duty cycle clock. This is an active low signal which acts like the start/stop button on a runner’s stopwatch. Outputs The following are outputs signals for the design. and lap_load input signals. • clk_div_262k Macro which divides a clock frequency by 262. This input is only functional while the clock or timer is not counting.xilinx. clk Externally generated system clock. Functional Blocks The completed design consists of the following functional blocks. • • • reset Puts the stopwatch in clocking mode and resets the time to 0:00:00.

1 In-Depth Tutorial www. Controls the state of the stopwatch. double-click stopwatch. To open the schematic file. You will learn the process for creating each of these types of macros. and you will connect the macros together to create the completed stopwatch design. This macro contains 64 preset times from 0:00:00 to 9:59:99 which can be loaded into the timer. • time_cnt Up/down counter module which counts between 0:00:00 to 9:59:99 decimal. including schematicbased macros. After you have created the project in ISE. Design Entry In this hierarchical design. state machine macros.Design Entry R State Machine module defined and implemented in State Diagram Editor. you will update the schematic in the Schematic Editor. which represent the digits of the stopwatch time.sch file for editing.com 57 . All procedures used in the tutorial can be used later for your own designs.sch in the Sources window. HDL-based macros. Opening the Schematic File in the Xilinx Schematic Editor The stopwatch schematic available in the wtut_sc project is incomplete. This macro has five 4-bit outputs.xilinx. and CORE Generator macros. In this tutorial. you will create various types of macros. • timer_preset CORE Generator™ 64X20 ROM. ISE 9. you can now open the stopwatch.

Select View > Zoom > In until you can comfortably view the schematic. 58 www.com ISE 9. the schematic window can be redocked by selecting Window > Dock.R Chapter 3: Schematic-Based Design The stopwatch schematic diagram opens in the Project Navigator Workspace. The corresponding symbol or schematic file can then be generated automatically. You can create either the underlying schematic or the symbol first. After being undocked. Creating a Schematic-Based Macro A schematic-based macro consists of a symbol and an underlying schematic.xilinx. The schematic window can be undocked from the Project Navigator framework by selecting Window > Float while the schematic is selected in the workspace.1 In-Depth Tutorial . Figure 3-5: Incomplete Stopwatch Schematic Manipulating the Window View The View menu commands enable you to manipulate how the schematic is displayed. You will see the unfinished design with elements in the lower right corner as shown in the figure below.

The created macro is then automatically added to the project’s library. 4. The next step is to add the components that make up the time_cnt macro. ♦ ♦ ♦ Right-click on the schematic page and select Object Properties. This macro is a binary counter with five. Click OK and then click Yes to acknowledge that changing the sheet size cannot be undone with the Edit > Undo option. Click Next and click Finish.xilinx. added to the project. The New Source dialog box opens: Figure 3-6: New Source Dialog Box The New Source dialog displays a list of all of the available source types. and opened for editing. and you can define the appropriate logic. The macro you will create is called time_cnt. 3. In Project Navigator.com 59 . ISE 9. You can then reference this macro symbol by placing it on a schematic sheet. Enter time_cnt as the file name.1 In-Depth Tutorial www. 4bit outputs. Change the size of the schematic sheet by doing the following. 2. An empty schematic file is then created. 5. To create a schematic-based macro: 1. you will create a schematic-based macro by using the New Source Wizard in Project Navigator. representing the digits of the stopwatch. Defining the time_cnt Schematic You have now created an empty schematic for time_cnt.Design Entry R In the following steps. select Project > New Source. Click on the down arrow next to the sheet size value and select D = 34 x 22. Select Schematic as the source type. A new schematic called time_cnt is created.

1. or the top-level schematic.R Chapter 3: Schematic-Based Design Adding I/O Markers I/O markers are used to determine the ports on a macro. Select Tools > Create I/O Markers. Figure 3-7: 4.up. I/O markers may be added to nets at any time by selecting Add > I/O Marker and selecting the desired net.sec_msb(3:0). enter q(19:0). Adding Schematic Components Components from the device and project libraries for the given project are available from the Symbol Browser.clr.com ISE 9. Add I/O markers to the time_cnt schematic to determine the macro ports. enter hundredths(3:0). The name of each pin on the symbol must have a corresponding connector in the underlying schematic. The eleven I/O markers are added to the schematic sheet. Figure 3-8: Add Symbol Icon 60 www. and the component symbol can be placed on the schematic. 2.clk. Note: The Options window changes depending on which tool you have selected in the Tools toolbar. select Add > Symbol or click the Add Symbol icon from the Tools toolbar.xilinx. However.1 In-Depth Tutorial . 3. Note: The Create I/O Marker function is available only for an empty schematic sheet. In the Inputs box. In the Outputs box. Creating I/O Markers Click OK. To add the I/O markers: 1. The available components listed in the Symbol Browser are arranged alphabetically within each library. From the menu bar.ce. The Create I/O Markers dialog box opens.sec_lsb(3:0).minutes(3:0).load.tenths(3:0).

Design Entry

R

This opens the Symbol Browser to the left of the schematic editor, displaying the libraries and their corresponding components.

Figure 3-9:

Symbol Browser

The first component you will place is a cd4rled, a 4-bit, loadable, bi-directional, BCD counter with clock enable and synchronous clear. 2. Select the cd4rled component, using one of two ways:

Highlight the project directory category from the Symbol Browser dialog box and select the component cd4rled from the symbols list. or Select All Symbols and type cd4rled in the Symbol Name Filter at the bottom of the Symbol Browser window.

3. 4.

Move the mouse back into the schematic window. You will notice that the cursor has changed to represent the cd4rled symbol. Move the symbol outline near the top and center of the sheet and click the left mouse button to place the object. Note: You can rotate new components being added to a schematic by selecting Ctrl+R. You
can rotate existing components by selecting the component, and then selecting Ctrl+R.

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R

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5.

Place three more cd4rled symbols on the schematic by moving the cursor with attached symbol outline to the desired location, and clicking the left mouse button. See Figure 3-10

Figure 3-10: 6. • • •

Partially Completed time_cnt Schematic

Follow the procedure outlined in steps 1 through 4 above to place the following components on the schematic sheet: AND2b1 ch4rled AND5

Refer to Figure 3-10 for placement locations. To exit the Symbols Mode, press the Esc key on the keyboard.

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Design Entry

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For a detailed description of the functionality of Xilinx Library components, right-click on the component and select Object Properties. In the Object Properties window, select Symbol Info. Symbol information is also available in the Libraries Guides, accessible from the collection of software manuals on the web at http://www.xilinx.com/support/sw_manuals/xilinx9/.

Correcting Mistakes
If you make a mistake when placing a component, you can easily move or delete the component. To move the component, click the component and drag the mouse around the window. Delete a placed component in one of two ways: • • Click the component and press the Delete key on your keyboard. or Right-click the component and select Delete.

Drawing Wires
Use the Add Wire icon in the Tools toolbar to draw wires (also called nets) to connect the components placed in the schematic. Perform the following steps to draw a net between the AND2b1 and top cd4rled components on the time_cnt schematic. 1. Select Add > Wire or click the Add Wire icon in the Tools toolbar.

Figure 3-11: 2. 3.

Add Wire Icon

Click the output pin of the AND2b1 and then click the destination pin CE on the cd4rled component. The Schematic Editor draws a net between the two pins. Draw a net to connect the output of the AND5 component to the inverted input of the AND2b1 component. Connect the other input of the AND2b1 to the ce input IO marker. Connect the load, up, clk, and clr input IO markers respectively to the L, UP, C, and R pins of each of the five counter blocks and connect the CEO pin of the first four counters to the CE pin of the next counter as shown in Figure 3-10.

4.

To specify the shape of the net: 1. 2. Move the mouse in the direction you want to draw the net. Click the mouse to create a 90-degree bend in the wire.

To draw a net between an already existing net and a pin, click once on the component pin and once on the existing net. A junction point is drawn on the existing net.

Adding Buses
In the Schematic Editor, a bus is simply a wire that has been given a multi-bit name. To add a bus, use the methodology for adding wires and then add a multi-bit name. Once a bus

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Select all of the output IO markers by drawing a box around them and then drag the group so that minutes(3:0) is below the Q3 output of the bottom counter block. perform the following steps: 1. Adding Bus Taps Next. choose the --< Right orientation for the bus tap. The thick line should automatically be drawn to represent a bus with the name matching that of the I/O marker. The results can be found in the completed schematic.1 In-Depth Tutorial . 5. Figure 3-13: Add Bus Tap Icon The cursor changes. 64 www. 2.R Chapter 3: Schematic-Based Design has been created.com ISE 9. Figure 3-12: 4. After adding the five buses. Select Add > Wire or click the Add Wire icon in the Tools toolbar. sec_lsb(3:0). To add the buses hundredths(3:0). tenths(3:0). 2. Note: Zooming in on the schematic enables greater precision when drawing the nets. add nets to attach the appropriate pins from the cd4rled and ch4rled counters to the buses. indicating that you are now in Draw Bus Tap mode. 3. you have the option of “tapping” this bus off to use each signal individually. press Esc or right-click at the end of the bus to exit the Add Wire mode.xilinx. Adding a Bus Repeat Steps 2 and 3 for the four remaining buses. Click in the open space just above and to the right of the top cd4rled and then click again on the pin of the hundredths(3:0) I/O marker. Select Add > Bus Tap or click the Add Bus Tap icon in the Tools toolbar. The next step is to create three buses for each of the five outputs of the time_cnt schematic. From the Options tab to the left of the schematic. Use Bus Taps to tap off a single bit of a bus and connect it to another component. sec_msb(3:0) and minutes(3:0) to the schematic. To tap off a single bit of each bus: 1.

and tc_out4 to these nets.xilinx. The bus tap figure is for visual purposes only. Click successively on pins Q2. tc_out1. Q1.com 65 . With hundredths(3) as the Net Name value. The Schematic Editor increments the net Name as each name is placed on a net.Design Entry R 3. The net name tc_out0 is now attached to the cursor. add a hanging wire to each of the five inputs of the AND5 component and to the TC pin of each of the counter blocks. Click on the remaining input nets of the AND5 to add tc_out1. and Q0 to create taps for the remaining bits of the hundredths(3:0) bus. 8. To add the net names: 1. 7. The net name appears above the net if the name is placed on any point of the net other than an end point. and nets are named from the bottom up. Note: It is the name of the wire that makes the electrical connection between the bus and the wire (e. tc_out3. tc_out2. Repeat Steps 3 to 6 to tap off four bits from each of the five buses. The Selected Bus Name and the Net Name values of the options window are now populated. Repeat step 2 and then click successively on the nets connected to the TC output to add tc_out0. Note: The indexes of the Net Name may be incremented or decremented by clicking the arrow buttons next to the Net Name box. Next.g sec_msb(2) connects to the third bit of sec(3:0)). 3. Adding Net Names First. Select Add > Net Name or click the Add Net Name icon in the Tools toolbar. 5. Add Net Name Icon Type tc_out0 in the Name box and select Increase the Name in the Add Net Names Options dialog box. Note: Four selection squares appear around the pin when the cursor is in the correct position. tc_out2. Compare your time_cnt schematic with Figure 3-15 to ensure that all connections are made properly. The name is then attached to the net. 5. Click once when the cursor is in the correct position. tc_out3 and tc_out4. The following section shows additional electrical connections by name association. 4. A tap is connected to the hundredths(3:0) bus and a wire named hundreths(3) is drawn between the tap and the Q3 pin. Alternatively. Press Esc to exit the Add Net Name mode. add net names to the wires. move the cursor so the tip of the attached tap touches the Q3 pin of the top cd4rled component. 4. Click the net attached to the first input of the AND5 component. Figure 3-14: 2. Click on the hundreths(3:0) bus with the center bar of the cursor. ISE 9.1 In-Depth Tutorial www. 6. name the first net tc_out4 and select Decrease the name in the Add Net Names Options dialog box.

In this case. fix the reported problem before proceeding. 5. 1.xilinx. 4. 66 www. select View > Refresh to refresh the screen. Note: If the nets appear disconnected. Figure 3-15: Completed time_cnt Schematic Checking the Schematic The time_cnt schematic is now complete.com ISE 9. Click successively on each of the nets connected to data inputs.1 In-Depth Tutorial . The Console window should report that no errors or warnings are detected. Verify that the schematic does not contain logical errors by running a design rule check (DRC). Select Add > Wire or click the Add Wire icon and add a hanging net to the four data pins of each of the five counters. select Tools > Check Schematic. connect the input pins of the counters through net name association. Refer to Figure 3-15.R Chapter 3: Schematic-Based Design Note: Each of the wires with identical names are now electrically connected. 3. The net name q(0) is now attached to the cursor. Finally. the nets do not need to be physically connected on the schematic to make the logical connection. 2. Select Add > Net Name or click the Add Net Name icon in the Tools toolbar. starting from the top so that the net named q(0) is attached to the D0 pin of the top counter and the net named q(19) is attached to the D3 pin of the bottom counter. Select Increase the name in the Add Net Name options dialog box. Type q(0) in the Name box of the Add Net Name options dialog box. To do this. If an error or warning is displayed.

Placing the time_cnt Symbol Next. View and then close the time_cnt symbol. In the Processes window. 2. Figure 3-16: 2. To create a symbol that represents the time_cnt schematic using a Project Navigator process: 1. In the Symbol Wizard. Creating the time_cnt symbol You can create a symbol using either a Project Navigator process or a Tools menu command. select Using Schematic. Double-click Create Schematic Symbol. In the top-level schematic.com 67 . Click Next.Design Entry R Saving the Schematic 1. the symbol of the time_cnt macro will be connected to other components in a later section in this chapter. 3. select time_cnt. The symbol is an instantiation of the macro. Close the time_cnt schematic. 2. place the symbol that represents the macro on the top-level schematic (stopwatch. In the Sources window. Save Icon Creating and Placing the time_cnt Symbol The next step is to create a “symbol” that represents the time_cnt macro. and then select time_cnt in the schematic value field. you will add the symbol to a top-level schematic of the stopwatch design. Figure 3-17: Add Symbol Icon ISE 9.sch to open the schematic. select Tools > Symbol Wizard. and then Finish to use the wizard defaults. After you create a symbol for time_cnt. Select the Add Symbol icon.sch). or by clicking the Save icon in the toolbar. click the + beside Design Utilities to expand the hierarchy.xilinx. With the time_cnt schematic sheet open. double-click stopwatch.sch. 2. In the Sources window.1 In-Depth Tutorial www. then Next. 3. then Next again. 1. Save the schematic by selecting File > Save. To create a symbol that represents the time_cnt schematic using a Tools menu command: 1.

select Project > New Source. Select Distributed Memory Generator. Depth: 64 . Grid position is shown at the bottom right corner of the Project Navigator window.com ISE 9. Type timer_preset in the File name field. This should be close to grid position [1612. and is updated as the cursor is moved around the schematic. 3. Double-click Memories & Storage Elements. and then select the newly created time_cnt symbol. Component Name: timer_preset . 68 www. then double-click RAMs & ROMs. Select IP (Coregen & Architecture Wizard). and distributed and block RAM. In this section. Creating a CORE Generator Module To create a CORE Generator module: 1.Defines the number of values to be stored Data Width: 20 . Fill in the Distributed Memory Generator customization GUI with the following settings: ♦ ♦ ♦ ♦ ♦ ♦ 7. In the Symbol Browser. 6. then click Next and click Finish to open the Distributed Memory Generator customization GUI. You will do this after adding other components to the stopwatch schematic. Leave Input and Output options as Non Registered. 4.Defines the width of the output bus. In Project Navigator. 4. such as Fast Carry Logic. math functions. Creating a CORE Generator Module CORE Generator is a graphical interactive design tool that enables you to create high-level modules such as memory elements. communications. SRL16s.xilinx. Save the changes and close stopwatch. 5. Click Next.1 In-Depth Tutorial .sch. 5. You can customize and pre-optimize the modules to take advantage of the inherent architectural features of the Xilinx FPGA architectures. you will create a CORE Generator module called timer_preset. The module is used to store a set of 64 values to load into the timer. Place the time_cnt symbol in the schematic so that the output pins line up with the five buses driving inputs to the lcd_control component. Note: Do not worry about connecting nets to the input pins of the time_cnt symbol. This customization GUI enables you to customize the memory to the design specifications. 2. select the local symbols library (c:\xilinx\ISEexamples\wtut_sc).R Chapter 3: Schematic-Based Design 3.Defines the name of the module. Memory Type: ROM Click Next.1728]. and IO interface cores. Click Next.

vhd or timer_preset.xco This file stores the configuration information for the timer_preset module and is used as a project source.xilinx. timer_preset. timer_preset. timer_preset. CORE Generator . Figure 3-18: 8. ISE 9. Click Finish. The module is created and automatically added to the project library.com 69 .Design Entry R ♦ Coefficients File: Click the Browse button and select definition1_times. Note: A number of files are added to the project directory.ngc This file is the netlist that is used during the Translate phase of implementation.mif This file provides the initialization values of the ROM for simulation.Distributed Memory Generator Customization GUI Check that only the following pins are used (used pins are highlighted on the symbol on the left side of the customization GUI): ♦ ♦ a[5:0] spo[19:0] 9.coe.1 In-Depth Tutorial www. ♦ timer_preset.sym This file is a schematic symbol file.v These are HDL wrapper files for the core and are used only for simulation. Some of these files are: ♦ ♦ ♦ ♦ timer_preset.

The State Diagram Editor then exports the diagram to either VHDL. In the next section.com ISE 9. The State Diagram Editor is launched with the partially completed state machine diagram.dia file to the project by selecting Project > Add Source and selecting statmach. a partially complete state machine diagram is provided. The output expressions for each state are found in the circles representing the states. first add the statmach. copy either statmach. Verilog or ABEL code. you can graphically create finite state machines that include states. The black expressions are the transition conditions. then proceed to “Creating the State Machine Symbol. A completed VHDL and Verilog file for the State Machine diagram in this section has been provided for you in the wtut_sc\wtut_sc_completed directory. double-click statmach. inputs/outputs. defining how you move between states. you will complete the diagram. or ABEL. VHDL. The transition conditions and the state actions are written in language-independent syntax and are then exported to Verilog. synthesize the module into a macro and place it on the stopwatch schematic.1 In-Depth Tutorial .R Chapter 3: Schematic-Based Design Creating a State Machine Module With the State Diagram Editor.v or stamach. In the incomplete state machine diagram below: • • • • The circles represent the various states.” To open the partially complete diagram. 70 www. and state transition conditions.dia.xilinx. Transition conditions and state actions are typed into the diagram using language independent syntax. To skip this section. For this tutorial. The resulting HDL file is finally synthesized to create a netlist and a macro symbol is created for you to place on a schematic sheet.vhd from the c:\xilinx\ISEexamples\stut_sc\wtut_sc_completed directory to the c:\xilinx\ISEexamples\stut_sc directory.dia in the Sources tab. Note: The State Diagram Editor is only available for Windows operating systems. Then.

Place the new state on the left-hand side of the diagram.xilinx. ISE 9.1 In-Depth Tutorial www. as shown in Figure 3-21.Design Entry R Figure 3-19: Incomplete State Machine Diagram In the following section. transitions. Figure 3-20: Add State Icon The state bubble is now attached to the cursor. 2. To do so: 1. and a reset condition to complete the state machine. Click the Add State icon in the vertical toolbar.com 71 . add the remaining states. 3. Adding New States Complete the state machine by adding a new state called clear. actions. Click the mouse to place the state bubble.

Any name is fine. Transitions are represented by arrows in the editor.com ISE 9.R Chapter 3: Schematic-Based Design The state is given the default name. To change the shape of the state bubble. Click OK. click one of the four squares surrounding the bubble and drag it in the direction you wish to stretch the bubble. Click the Add Transition icon in the vertical toolbar. Figure 3-21: 4.1 In-Depth Tutorial . Adding a Transition A transition defines the movement between states of the state machine. there is no transition condition associated with it. Figure 3-22: 2. Add Transitions Icon Click on the clear state to start the transition. 5. 3.xilinx. Because this transition is unconditional. Click on the zero state to complete the transition arrow. 72 www. 1. STATE0. and change the name of the state to clear. You will add a transition from the clear state to the zero state in the following steps. Adding the CLEAR State Double-click STATE0 in the state bubble. Note: The name of the state is for your use only and does not affect synthesis.

com 73 . To add a state action: 1.Design Entry R 4.1 In-Depth Tutorial www.xilinx. ISE 9. Double-click the clear state. To manipulate the arrow’s shape. Figure 3-24: Select Objects Icon Adding a State Action A state action dictates how the outputs should behave in a given state. Figure 3-23: 5. Adding State Transition Click the Select Objects (or Pointer) icon in the vertical toolbar to exit the Add Transition mode. click and drag it in any directory. You will add a state action to the clear state to drive the RST output to 1.

R Chapter 3: Schematic-Based Design The Edit State dialog box opens and you can begin to create the desired outputs. Click OK to exit the Edit State dialog box. 5. enter the following values: DOUT = rst. Figure 3-26: Adding State Outputs 74 www.1 In-Depth Tutorial . CONSTANT = ‘1’.xilinx. 4. Figure 3-25: 2. Select the Output Wizard button. 3.com ISE 9. Edit State Dialog Box In the Logic Wizard. The output is now added to the state. Click OK to enter each individual value.

1. Select Options > Configuration. 2. double-click on the value and edit the condition appropriately. In the Language section. Move the cursor to the clear state. add a reset condition that sends the state machine to the clear state whenever either the reset signal is asserted high.xilinx. specify a reset condition for the state machine. 3. In the Language Vendor section select Xilinx XST. In this design. Figure 3-27: 2. Adding a Reset Condition Verify that ‘state_reset’ is added as the reset condition. Click the Add Reset icon in the vertical toolbar. Click OK. ISE 9. If another value is listed for the reset condition. The cursor is automatically attached to the transition arrow for this reset. Click OK. A Results window is displayed listing the compile status. and click the state bubble.Design Entry R Adding a State Machine Reset Condition Using the State Machine Reset feature. 3. select the Generate HDL icon in the toolbar. Add Reset Icon Click the diagram near the clear state. or the DCM_lock signal is de-asserted low. Figure 3-28: 5. 5. To generate the HDL file.1 In-Depth Tutorial www. 6.com 75 . as shown in the diagram below. 4. When you see the question being asked: “Should this reset be asynchronous(Yes) or synchronous (No)?” Answer Yes. 4. select either Verilog or VHDL as desired. The state machine initializes to this specified state and enters the specified state whenever the reset condition is met. Creating the State Machine HDL output file 1.

A browser opens displaying the generated HDL file. 3. In the New Source dialog box. select statmach.R Chapter 3: Schematic-Based Design 7. The macro symbol is added to the project library. Select statmach.1 In-Depth Tutorial . 5. Examine the code and then close the browser. Close the State Diagram Editor. Save your changes by selecting File > Save. 8. you will create a basic DCM module with CLK0 feedback and duty-cycle correction. Using the Clocking Wizard Create the dcm1 module as follows: 1. click the + beside Design Utilities to expand the hierarchy.v or statmach. 9.v(hd) is added to the project in Project Navigator. Creating a DCM Module The Clocking Wizard.vhd or statmach. The file statmach.com ISE 9. Double-click Create Schematic Symbol.v. In Project Navigator. 4. and type the filename dcm1. In the Sources tab. 2. 2.vhd (this is the HDL file generated by State Diagram Editor) and click Open. enables you to graphically select Digital Clock Manager (DCM) features that you wish to use. In the Processes tab. Select Project > New Source. Click Next. a Xilinx Architecture Wizard. you will create a macro symbol for the state machine that you can place on the stopwatch schematic.xilinx. In this section. Creating the State Machine Symbol In this section. 1. select Project > Add Source. select the IP (Coregen & Architecture Wizard) source type. 76 www. 3.

Figure 3-29: 5.xilinx. 8.1 In-Depth Tutorial www. 6.Design Entry R 4. Spartan-3A > Single DCM SP. The Clocking Wizard is launched. Verify the following settings: ♦ ♦ ♦ ♦ ♦ Phase Shift: NONE CLKIN Source: External. Select CLKFX port. select FPGA Features and Design > Clocking > Spartan3E. Verify that RST. 9. then click Finish. Type 50 and select MHz for the Input Clock Frequency. In the Select IP dialog box. CLK0 and LOCKED ports are selected. Selecting Single DCM Core Type Click Next. Single Feedback Source: Internal Feedback Value: 1X Use Duty Cycle Correction: Selected ISE 9.com 77 . 7.

( 26. Select the Wait for DCM Lock before DONE Signal goes high option. 1. Select Use output frequency and type 26.R Chapter 3: Schematic-Based Design Figure 3-30: Xilinx Clocking Wizard .1 In-Depth Tutorial . Click the Advanced button. 12. Click Next. in the Sources tab. In the Processes tab. Click Next twice to advance to the Clock Frequency Synthesizer page. create a symbol representing the dcm1 macro.2144Mhz ) ⁄ 2 18 = 100Hz 15. select dcm1. and then click Finish. In Project Navigator.xaw.General Setup 10. Click OK. 78 www. This symbol will be added to the toplevel schematic (stopwatch.xaw file is created and added to the list of project source files in the Sources tab. 11.2144 in the box and select MHz. Creating the dcm1 Symbol Next.xilinx. 13. The dcm1.sch) later in the tutorial. double-click Create Schematic Symbol. 14. 2.com ISE 9.

Figure 3-31: New Source Wizard for Verilog 6. specifying the name and ports of the component. A description of the module displays. clk and sig_out. In the first three Port Name fields type sig_in. you can easily create modules from HDL code.Design Entry R Creating an HDL-Based Module With ISE. A dialog box opens in which you specify the type of source you want to create. Click Finish to open the empty HDL file in the ISE Text Editor.xilinx. mode and lap_load inputs. 2. 5. 7. Enter two input ports named sig_in and clk and an output port named sig_out for the debounce component as follows: a. To create the source file: 1. You will author a new HDL module. Set the Direction field to input for sig_in and clk and to output for sig_out. 4.com 79 . ISE 9. The VHDL file is displayed in Figure 3-32. The resulting HDL file is then modified in the ISE Text Editor. Using the New Source Wizard and ISE Text Editor In this section. c. In the File Name field. Click Next to complete the Wizard session.1 In-Depth Tutorial www. you create a file using the New Source wizard. 3. Leave the Bus designation boxes unchecked. The HDL code is connected to your top-level schematic design through instantiation and compiled with the rest of the design. Select VHDL Module or Verilog Module. This macro will be used to debounce the strtstop. type debounce. b. Click Next. The Verilog HDL file is displayed in Figure 3-33. Select Project > New Source.

xilinx.1 In-Depth Tutorial .R Chapter 3: Schematic-Based Design Figure 3-32: VHDL File in ISE Text Editor Figure 3-33: Verilog File in ISE Text Editor 80 www.com ISE 9.

Use the appropriate template for the language you are using. and primitives.1 In-Depth Tutorial www. D flip-flops. Debounce Circuit. and some of the basic file structure is already in place. When the template is selected in the hierarchy. and values are black. Click any of the listed templates to view the template contents in the right pane. 2. expand the Synthesis Constructs hierarchy. ISE 9. Keywords are displayed in blue.com 81 .xilinx. To invoke the Language Templates and select the template for this tutorial: 1. the contents display in the right pane. Using the Language Templates The ISE Language Templates include HDL constructs and synthesis templates which represent commonly used logic components. select Edit > Language Templates. the ports are already declared in the HDL file. You will use the Debounce Circuit template for this exercise. Under either the VHDL or Verilog hierarchy. From Project Navigator. Synthesis Constructs and User Templates. Each HDL language in the Language Templates is divided into five sections: Common Constructs. comments in green. Device Primitive Instantiation. click the + next to the section. multiplexers. expand the Misc hierarchy. and select the template called One-Shot.Design Entry R In the ISE Text Editor. The file is color-coded to enhance readability and help you recognize typographical errors. such as counters. Simulation Constructs. Note: You can add your own templates to the Language Templates for components or constructs that you use often. To expand the view of any of these sections. expand the Coding Examples hierarchy.

3.v file under the module and pin declarations. Remove the reset logic (not used in this design) by deleting the three lines beginning with if and ending with else. Close the Language Templates window. 82 www.com ISE 9.vhd file under the architecture begin statement. b.xilinx.R Chapter 3: Schematic-Based Design Figure 3-34: Language Templates Adding a Language Template to Your File You will now use the drag and drop method for adding templates to your HDL file.1 In-Depth Tutorial . 2. Click and drag the Debounce Circuit name from the Language Template topology into the debounce. Change <reg_name> to q in all six locations. Refer to “Working with Language Templates” in the ISE Help for additional usability options. 4. To add the template to your HDL file using the drag and drop method: 1. Select Window > Tile Vertically to show both the HDL file and the Language Templates window. or into the debounce. (Verilog only) Complete the Verilog module by doing the following: a.

Change <clock> to clk. You now have complete and functional HDL code. 2. Select the appropriate symbol. Save the file by selecting File > Save. 1. as shown in Figure 3-36. You will connect components in the schematic later in the tutorial.com 83 . timer_preset.vhd or debounce. In the Processes tab. In the Sources tab. 1. Figure 3-35: Add Symbol Icon This opens the Symbol Browser to the left of the Schematic Editor. Double-click Create Schematic Symbol.1 In-Depth Tutorial www. lines. and debounce symbols on the stopwatch schematic (stopwatch. select debounce. 4. View the list of available library components in the Symbol Browser.v. and ending with else and delete one of the end if. and add it to the stopwatch schematic in the approximate location. In Project Navigator. double-click stopwatch. Remove the reset logic (not used in this design) by deleting the five lines beginning with if (<reset>. Move the line beginning with the word signal so that it is between the architecture and begin keywords.sch. 9. c. In the Processes tab. The schematic file opens in the Workspace. dcm1. click the + beside Design Utilities to expand the hierarchy. create the schematic symbol representing the debounce HDL in Project Navigator. Close the ISE Text Editor. Select Add > Symbol or click the Add Symbol icon from the Tools toolbar.Design Entry R c. D_IN to sig_in.. 6.xilinx. 2. Locate the project-specific macros by selecting the project directory name in the Categories window. 5. Creating the debounce Symbol Next. (VHDL only) Complete the VHDL module by doing the following: b. You are now ready to place the debounce symbol on the stopwatch schematic. Note: Do not worry about drawing the wires to connect the symbols. <input> to sig_in. Select debounce in the Sources tab. 3. double-click Check Syntax. timer_preset. 8.. ISE 9. 7. a. and Q_OUT to sig_out.sch). Placing the statmach. 3. and <output> to sig_out. Change <clock> to clk. which displays the libraries and their corresponding components. dcm1 and debounce Symbols You can now place the statmach.

• • • Right-click on the dcm1 symbol instance and select Object Properties from the rightclick menu Change the value of the InstName field to dcm_inst and then click OK. Name the statmach instance timer_state. 84 www. change the names of the added symbol instances as follows.R Chapter 3: Schematic-Based Design 5. Save the schematic. Repeat steps 1 and 2 to change the following symbol instance names.1 In-Depth Tutorial .xilinx. To help make the hierarchy more readable in the Project Navigator Sources window.com ISE 9. 1. Name the top debounce instance lap_load_debounce Name the middle debounce instance mode_debounce. 2. Figure 3-36: Placing Design Macros Changing Instance Names When a symbol is placed on a schematic sheet it is given a unique instance name beginning with the prefix XLXI_.

If a user pushes into a symbol that has an underlying HDL or IP core file. lap_load. perform a hierarchy “push down. Figure 3-37: Hierarchy Push Icon In the time_cnt schematic. clk. All of the Schematic Editor schematics are netlisted to VHDL or Verilog and then synthesized by the synthesis tool of choice. return to the top-level schematic by selecting View > Pop to Calling Schematic. add five input pins to the stopwatch schematic: reset. Adding Input Pins Next. Name the time_cnt instance timer_cnt.” which enables you to focus in on a lower-level of the schematic hierarchy to view the underlying file. To push down into time_cnt from the top-level. Push down into the time_cnt macro. You can also right-click the macro and select Symbol > Push into Symbol.xilinx. Push into any of the counter blocks by selecting the block and clicking on the Hierarchy Push icon. which is a schematic-based macro created earlier in this tutorial. and examine its components. ISE 9. stopwatch. the appropriate text editor or customization GUI will open and be ready to edit the file.Design Entry R • • • Name the bottom debounce instance strtstop_debounce. 2.com 85 . schematic: 1. the I/O markers are replaced with the appropriate pads and buffers. and select the Hierarchy Push icon. You can also right-click in an open space of the schematic and select Pop to Calling Schematic. To add these components: • Draw a hanging wire to the two inputs of dcm1 and to the sig_in pin of each debounce symbol Refer to “Drawing Wires” for detailed instructions. After examining the macro. This process may be repeated until the schematic page contains only Xilinx primitive components. When the synthesis tool synthesizes the top-level schematic’s HDL.1 In-Depth Tutorial www. you see five counter blocks. Name the timer_preset instance t_preset. mode and strtstop. or select the Hierarchy Pop icon when nothing in the schematic is selected. Hierarchy Push/Pop First. Figure 3-38: Hierarchy Pop Icon Specifying Device Inputs/Outputs Use the I/O marker to specify device I/O on a schematic sheet. Click time_cnt symbol in the schematic.

Click and drag a box around the name of the five labeled nets.R Chapter 3: Schematic-Based Design Adding I/O Markers and Net Names It is important to label nets and buses for several reasons: • • • It aids in debugging and simulation. 2. Place the name on the leftmost end of the net. Label the five input nets you just drew. Once all of the nets have been labeled. 3. to place an input port on each net. Any nets that remain unnamed in the design will be given generated names that will mean nothing to you later in the implementation process. Refer to the completed schematic below. add the I/O marker. Type reset into the Name box. mode.1 In-Depth Tutorial . Figure 3-39: Adding I/O Markers to Labeled Nets 86 www.xilinx. Naming nets also enhances readability and aids in documenting your design. as illustrated in Figure 3-39. Repeat Steps 1 through 3 for the clk. To label the reset net: 1. 6. Select Add > I/O Marker. as you can more easily trace nets back to your original design. as illustrated in Figure 3-39. Select Add > Net Name.com ISE 9. 5. lap_load. and strtstop pins. The net name is now attached to the cursor. 4.

select Add and then OK. However. 3. Figure 3-40: 5. Select VHDL or Verilog and select Ignore this attribute. The above procedure constrains clk to pin E12. Enter LOC for the Attribute Name and E12 for the Attribute Value. adding any additional necessary logic. the example pin assignments will not adversely affect the ability of PAR to place and route the design. The following steps guide you through the process of completing the schematic. For this tutorial. select the loc attribute. Completing the Schematic Complete the schematic by wiring the components you have created and placed. select the Add button adjacent to the LOC attribute in the Attribute window.com 87 . Click the New button under Net Attributes to add a new property. Click OK to return to the Object Properties dialog box. Note: To turn off the Location constraint without deleting it. Assign a LOC parameter to the output nets on the stopwatch schematic. Pre-assigning locations to the pins can sometimes degrade the performance of the place-and-route tools. Because the tutorial stopwatch design is simple and timing is not critical. and click Edit Traits. Notice that the LOC property has already been added to the sf_d(7:0) bus. 4. 6. Click OK to close the Object properties window. it may be necessary at some point to lock the pinout of a design so that it can be integrated into a Printed Circuit Board (PCB).Design Entry R Assigning Pin Locations Xilinx recommends that you let the automatic placement and routing (PAR) program define the pinout of your design. 2. the inputs and outputs will be locked to specific pins in order to place and download the design to the Spartan-3A demo board.1 In-Depth Tutorial www. “Design Implementation”. and labeling nets appropriately. You may also want to use the completed schematic shown below to complete the schematic. The remaining pin location constraints will be added in “Using the Constraints Editor” and “Using the Floorplan Editor” of Chapter 5. as follows: 1. Assigning Pin Locations To make the LOC attribute visible.xilinx. Right-click on the clk net and select Object Properties from the right-click menu. This will display the LOC attribute on the schematic above the clk net. Each of the actions referred ISE 9. In the Net Attribute Visibility window.

1 In-Depth Tutorial . (See “Drawing Wires.com ISE 9.” Draw a hanging wire to the clk input of both the time_cnt and statmach macros. Draw a hanging wire to the LOCKED_OUT pin of DCM1 and name the wire locked. Figure 3-41: Completed Stopwatch Schematic To complete the schematic diagram: 1.”) 88 www. See “Drawing Wires” and “Adding Net Names.R Chapter 3: Schematic-Based Design to in this section has been discussed in detail in earlier sections of the tutorial. Please see the earlier sections for detailed instructions. 2.xilinx.

“Behavioral Simulation.” to perform a pre-synthesis simulation of this design. 6. Draw a hanging wire to the clken output of the statmach component and another hanging wire to the ce pin of the time_cnt component.1 In-Depth Tutorial www. ISE 9. (See “Adding Net Names. Name both wires clk_en_int.Design Entry R 3. “Design Implementation. 8. Draw hanging wires from the rst output pin of the statmach macro and the clr pin of the time_cnt macro. See “Drawing Wires. do the following: • • Go to Chapter 4. 11. Draw wires from the lap_trigger and mode outputs of the statmach macro to the lap and mode inputs of the lcd_control macro.” Notice how the wire is automatically converted to a bus. See “Drawing Wires. Name both wires clk_100. 10. Draw hanging wires from the load output of the statmach macro and the load input of the time_cnt macro. mode_debounced. Draw a hanging bus on the input of the timer_preset macro and name the bus address(5:0).” Label both wires rst_int. See “Drawing Wires. respectively.” Name the wire mode_control. The schematic is now complete.com 89 .” to place and route the design. 7.xilinx. 9. You have now completed the schematic design. Draw a wire from the bus output of the timer_preset to the q(19:0) input of the time_cnt macro. This method is used to make the logical connection of clk_100 and several other signals. See “Drawing Wires” and “Adding Net Names. 12. Save the design by selecting File > Save. 4. Label the nets ll_debounced. See “Drawing Wires. See “Drawing Wires. Draw a hanging wire to the up input time_cnt macro. To continue with the schematic flow. mode_in and strtstop pin of the statmach macro.” Name both wires load. Draw a wire to connect the clk inputs of the three debounce macros and name the wire clk_26214k.”) Note: Remember that nets are logically connected if their names are the same. Proceed to Chapter 5. 5. even if the net is not physically drawn as a connection in the schematic. Draw wires between the sig_out pins of the debounce components and the lap_load.” Add hanging wires to the dcm_lock pin and the reset pin of the statmach macro.” Name the nets lap and mode_control respectively. and strtstop_debounced. Name them locked and reset.

xilinx.1 In-Depth Tutorial .R Chapter 3: Schematic-Based Design 90 www.com ISE 9.

you will achieve the same results. please contact Mentor Graphics. ModelSim SE. see Chapter 6 of the Synthesis and Simulation Design Guide.xilinx. For more information about ModelSim PE or SE. Older versions may work but are not supported. and from the web at http://www. use ModelSim 6. Whether you use the ModelSim simulator or the ISE Simulator with this tutorial.com/support/sw_manuals/xilinx9/. The examples in this tutorial demonstrate how to use the integrated flow. ModelSim Setup In order to use this tutorial. ISE 9. and for a list of other supported simulators. you must install ModelSim on your computer.R Chapter 4 Behavioral Simulation This chapter contains the following sections. ModelSim PE and SE ModelSim PE and ModelSim SE are full versions of ModelSim available for purchase directly from Mentor Graphics. • • • • • • • “Overview of Behavioral Simulation Flow” “ModelSim Setup” “ISE Simulator Setup” “Getting Started” “Adding an HDL Test Bench” “Behavioral Simulation Using ModelSim” “Behavioral Simulation Using ISE Simulator” Overview of Behavioral Simulation Flow Xilinx® ISE™ provides an integrated flow with the Mentor ModelSim simulator and the Xilinx ISE Simulator that allows simulations to be run from the Xilinx Project Navigator. and ModelSim XE. For additional information about simulation. This Guide is accessible from within ISE by selecting Help > Software Manuals.xilinx.0 or later.1 In-Depth Tutorial www. The following sections discuss requirements and setup for ModelSim PE. In order to simulate with the ISE 9 libraries.com 91 .

Windows XP. and Red Hat Enterprise Linux 3 or 4 platforms only. The design in this tutorial requires the use of simulation libraries because it contains instantiations of a digital clock manager (DCM) and a CORE Generator™ component. For instructions.1i installer.1 In-Depth Tutorial .” Xilinx Simulation Libraries Xilinx simulation libraries are required when a Xilinx primitive or IP core is instantiated in the design.xilinx.” or Chapter 3. For information on simulation libraries and how to compile them.htm. http://www.1i as the ISE version. go to the Download Center page.com/xlnx/xil_sw_updates_home. The ISE Simulator is available on Windows 2000.xilinx. and a full version. Be sure to select 9. For more information about MXE III including how to purchase the software.xilinx. please visit: http://www. and Xilinx simulation libraries. You may also create your own test bench file. your design includes the required design files. or Schematic) This chapter assumes that you have completed the design entry tutorial in either Chapter 2.jsp?update=mxe_libs ISE Simulator Setup ISE Simulator is automatically installed and set up with the ISE 9.com/ise/optional_prod/mxe. “Xilinx Simulation Libraries. Verilog. VHDL and Verilog test bench files are available with the tutorial files. Required Files The behavioral simulation flow requires design files. “Schematic-Based Design. “HDL-Based Design. see “Creating a Test Bench Waveform Using the Waveform Editor.com ISE 9. a test bench file. Design Files (VHDL. Getting Started The following sections outline the requirements for performing behavioral simulation in this tutorial. a test bench file is required to provide stimulus to the design. To obtain the correct MXE III simulation libraries. Test Bench File In order to simulate the design. see the next section.” 92 www. and is ready for simulation.” After you have completed one of these chapters.R Chapter 4: Behavioral Simulation ModelSim Xilinx Edition ModelSim Xilinx Edition III (MXE III) is the Xilinx version of ModelSim which is based on ModelSim PE. There are two versions of MXE III available for purchase from Xilinx: a free “starter” version.

ISE 9. Download the latest precompiled models from the Download Center at http://www. Mapping Simulation Libraries in the Modelsim. These libraries contain models for each component. and provide the simulator with the information required to perform simulation.xilinx. ModelSim Xilinx Edition III Updated models for ModelSim Xilinx Edition III (MXE III) are precompiled and available on the Xilinx support website. This Guide is accessible from within ISE by selecting Help > Software Manuals. if you compiled the UNISIM library to c:\lib\UNISIM. ModelSim PE or SE If you are using ModelSim PE or SE.1 In-Depth Tutorial www.ini file in the directory where ModelSim or MXE is installed.com/xlnx/xil_sw_updates_home.ini file: UNISIM = c:\lib\UNISIM Note: The modelsim. or from the web at http://www.ini file to determine the location of the compiled libraries. ModelSim searches for a modelsim. The modelsim. The compiled Xilinx simulation libraries are then available during the simulation of any design. This Guide is accessible from within ISE by selecting Help > Software Manuals. See Chapter 6 of the Synthesis and Simulation Design Guide. see Chapter 5 of the Synthesis and Simulation Design Guide. you must compile the simulation libraries with the updated models.com/support/sw_manuals/xilinx9/. These models reflect the functions of each component. All other models are updated each time a service pack is installed. and other Xilinx IP cores you must use the Xilinx simulation libraries.xilinx. When the models are updated. Updating the Xilinx Simulation Libraries The Xilinx simulation libraries contain models that are updated on a regular basis.com/support/sw_manuals/xilinx9/.com 93 .ini file in the current working directory.xilinx.ini file pointed to by the MODELSIM environment variable. and from the web at http://www.Getting Started R Xilinx Simulation Libraries To simulate designs that contain instantiated Xilinx primitives. For a detailed description of each library.xilinx.ini is not applicable to the ISE Simulator. you must recompile the libraries. CORE Generator components.jsp?update=mxe_libs. For instance. • • The XilinxCoreLib models are updated each time an IP Update is installed. Xilinx ISE Simulator Updated simulation libraries for the ISE Simulator are precompiled and installed with ISE installations and service packs. The modelsim.ini File ModelSim uses the modelsim.ini file in the following locations until one is found: • • • The modelsim. the following mapping appears in the modelsim.

A VHDL test bench and Verilog test fixture are provided with this tutorial. ModelSim PE or SE If you are using ModelSim PE or SE.ini file is not applicable to the ISE Simulator. ModelSim Xilinx Edition III If you are using ModelSim Xilinx Edition III (MXE III). you can either add a test bench file provided with this tutorial. you can copy the modelsim. Select the test bench file stopwatch_tb.ini file in the directory where MXE III was installed. 5. select VHDL Test Bench File.ini file to the working directory and make changes that are specific to that project. and the modelsim. and adds the test bench in the correct order.ini file with the correct mapping. Note: To create your own test bench file in ISE.vhd. You must define the test bench in a text editor. add the tutorial VHDL test bench to the project: 1.ini file. Adding an HDL Test Bench In order to add an HDL test bench to your design project. 3.ini file has not been copied to the working directory. While compiling the libraries. Adding Tutorial Test Bench File This section demonstrates how to add pre-existing test bench file to the project.ini file in the installation directory is used. Click OK. Select Project > Add Source.com ISE 9. 4. select Project > New Source. ISE recognizes the top-level design file associated with the test bench. ISE Simulator The modelsim. Click Open. In the Choose Source Type dialog box. Open the modelsim. open the modelsim. refer to the Development System Reference Guide and use COMPXLIB to compile the libraries. VHDL Simulation After downloading the file to your project directory. COMPXLIB also updates the modelsim. All of the Xilinx simulation libraries are already mapped to the proper location. the modelsim.ini file and make sure that the library mappings are correct.xilinx.1 In-Depth Tutorial . and select either VHDL Test Bench or Verilog Text Fixture in the New Source Wizard. 94 www. An empty stimulus file is added to your project.R Chapter 4: Behavioral Simulation If the MODELSIM environment variable is not set. For future projects. 2. or create your own test bench file and add it to your project. or you can use the MODELSIM environment variable to point to the desired modelsim.

3. Select the test bench file (stopwatch_tb). 5. the Project Navigator preferences may not be set correctly. compile the source files. ISE has full integration with the ModelSim Simulator. Behavioral Simulation Using ModelSim Now that you have a test bench in your project. Click Open. ISE 9. In the Processes tab. 2.exe.v. Select the file stopwatch_tb. click the + beside ModelSim Simulator to expand the process hierarchy. select Behavioral Simulation in the Sources for field. Locating the Simulation Processes The simulation processes in ISE enable you to run simulation on the design using ModelSim. In the Simulator field of the Project Properties dialog box. In the Sources tab. To simulate with the ISE Simulator. In the Choose Source Type dialog box. If ModelSim is installed but the processes are not available. the end result is the same. Click the + next to ISE General to expand the ISE preferences Click Integrated Tools in the left pane. and adds the test fixture in the correct order. Select Edit > Preferences. Select Properties. or Project Navigator cannot find modelsim. To select ModelSim as your project simulator: 1. To locate the ModelSim simulator processes: 1. Click OK. ISE recognizes the top-level design file associated with the test fixture. 2.Behavioral Simulation Using ModelSim R Verilog Simulation After downloading the file to your project directory. select Verilog Test Fixture File.com 95 . 4. you can perform behavioral simulation on the design using the ModelSim simulator. select the Modelsim type and HDL language combination you are using. either ModelSim is not selected as the Simulator in the Project Properties dialog box. 3.” Whether you choose to use the ModelSim simulator or the ISE Simulator for this tutorial. right-click the device line (xc3s700A-4fg484).1 In-Depth Tutorial www. load the design. In the Sources tab. ISE enables ModelSim to create the work directory. add the tutorial Verilog test fixture to the project: 1. and perform simulation based on simulation properties. 3.xilinx. 2. If the ModelSim Simulator processes do not appear. skip to “Behavioral Simulation Using ISE Simulator. 3. Select Project > Add Source. 2. To set the ModelSim location: 1.

com ISE 9.xilinx. If you double-click this process. 4. Generate a self-checking HDL test bench This process enables you to generate a self-checking HDL test bench equivalent to a test bench waveform (TBW) file and add the test bench to your project. browse to the location of the modelsim. select the test bench file (stopwatch_tb). c:\modeltech_xe\win32xoem\modelsim.exe file. ISE allows you to set several ModelSim Simulator properties in addition to the simulation netlist properties. To see the behavioral simulation properties. (Figure 4-1) set the Property display level to Advanced. In the Sources tab. You can also use this process to update an existing self-checking test bench. This global setting enables you to now see all available properties. See “Creating a Test Bench Waveform Using the Waveform Editor.” Specifying Simulation Properties You will perform a behavioral simulation on the stopwatch design after you have set some process properties for simulation.exe The following simulation processes are available: • • Simulate Behavioral Model This process starts the design simulation. Select Properties. In the Process Properties dialog box. The test bench generated by this process contains output data and self-checking code that can be used to compare the data from later simulation runs. and to modify the properties for this tutorial: 1. Note: This process is available only if you have a test bench waveform file from the ISE Simulator’s Test Bench Waveform Editor. 2. ModelSim runs in the background to generate expected results and displays them in the ISE Simulator’s Test Bench Waveform Editor. In the right pane. 3. Click the + sign next to ModelSim Simulator to expand the hierarchy in the Processes tab. under Model Tech Simulator.1 In-Depth Tutorial . Right-click Simulate Behavioral Model. For example.R Chapter 4: Behavioral Simulation 4. 96 www. 5.

The first outputs to transition after RESET is released are the SF_D and LCD_E control signals at around 33 mS. compiles the source files. To start the behavioral simulation. Figure 4-1: Behavioral Simulation Process Properties 7. click Help. Adding Signals To view internal signals during the simulation. ModelSim creates the work directory. loads the design. only the DCM signals are monitored to verify that they work correctly. ISE 9. Performing Simulation Once the process properties have been set. For the purpose of this tutorial. and performs simulation for the time specified. • • Drag and drop from the Signal/Object window. you are ready to run ModelSim. There are two basic methods for adding signals to the Simulator Wave window. Click OK. double-click Simulate Behavioral Model. Change the Simulation Run Time to 2000 ns. Highlight signals in the Signal/Object window. The majority of this design runs at 100 Hz and would take a significant amount of time to simulate. This is why the counter may seem like it is not working in a short simulation.Behavioral Simulation Using ModelSim R 6.1 In-Depth Tutorial www. you must add them to the Wave window.xilinx.com 97 . ISE automatically adds all the top-level ports to the Wave window. For a detailed description of each property available in the Process Properties dialog box. and select Add > Wave > Selected Signals. Additional signals are displayed in the Signal window based on the selected structure in the Structure window.

click the Undock icon. Figure 4-3: 2.com ISE 9. In the Signal/Object window.xilinx. select the following signals. Figure 4-3 shows the Structure/Instance window for the Verilog flow. The graphics and the layout of the Structure/Instance window for a schematic or VHDL flow may be different. Structure/Instance Window . ♦ ♦ ♦ ♦ RST_IN CLKFX_OUT CLK0_OUT LOCKED_OUT 98 www. The signals listed in the Signal/Object window are updated. 4. all the windows are docked by default. you will be adding the DCM signals to the waveform. click the + next to uut to expand the hierarchy.R Chapter 4: Behavioral Simulation The following procedure explains how to add additional signals in the design hierarchy.Verilog flow Select dcm1 in the Structure/Instance window. hold down the Ctrl key. To undock the windows.0 or higher. In the Structure/Instance window. Click and drag CLKIN_IN from the Signal/Object window to the Wave window. If you are using ModelSim version 6. To select multiple signals.1 In-Depth Tutorial . Figure 4-2: Undock icon To add additional signals in the design hierarchy: 1. 3. In this tutorial.

you must rerun the simulation for the desired amount of time. After new signals are added to the Wave window. Figure 4-4: Waveform After Adding DCM Signals Divider The waveforms have not been drawn for any of the newly added signals. ModelSim records data only for the signals that have been added to the Wave window while the simulation is running. This is because ModelSim did not record the data for these signals. Select Insert Divider. Right click anywhere in the signal section of the Wave window.com 99 . you can add dividers in the Wave window to make it easier to differentiate the signals.1 In-Depth Tutorial www. If necessary. Adding Dividers In ModelSim. Click the Restart Simulation icon.xilinx. Click OK. 2. 4. To add a divider called DCM Signals: 1. 6. undock the window and maximize the window for a larger view of the waveform. Figure 4-5: Restart Simulation Icon ISE 9. 5. Rerunning Simulation To rerun simulation in ModelSim: 1. Right-click in the Signal/Object window. Enter DCM Signals in the Divider Name box.Behavioral Simulation Using ModelSim R 5. Select Add to Wave > Selected Signals. Click and drag the newly created divider to above the CLKIN_IN signal. After adding the DCM Signals divider. 3. the waveform will look like Figure 4-4. By default.

4. At the ModelSim command prompt. Restart Dialog Box In the Restart dialog box. Press Enter. Click and drag one cursor to the first rising edge transition on the CLK0_OUT signal after the LOCKED_OUT signal has gone high.R Chapter 4: Behavioral Simulation Figure 4-6: 2. Click the Find Next Transition icon twice to move the cursor to the next rising edge on the CLK0_OUT signal. the DCM signals are analyzed only after the LOCKED_OUT signal has gone high. enter run 2000 ns. 3.com ISE 9. 3. Click and drag the second cursor just to the right of the first. Select Add > Wave > Cursor twice to add two cursors. click Restart.1 In-Depth Tutorial . Analyzing the Signals The DCM signals can be analyzed to verify that they work as expected. 4. 2. To measure the CLK0_OUT: 1. The CLK0_OUT needs to be 50 MHz and the CLKFX_OUT should be ~26 MHz.xilinx. ModelSim enables you to add cursors to measure the distance between signals. Figure 4-7: Entering the Run Command The simulation runs for 2000 ns. The waveforms for the DCM are now visible in the Wave window. The DCM outputs are valid only after the LOCKED_OUT signal is high. Figure 4-8: Find Next Transition Icon 100 www. therefore.

2. ISE 9. To select ISE Simulator as your project simulator: 1. select Behavioral Simulation in the Sources for field. which is the input frequency from the test bench. you can perform behavioral simulation on the design using the ISE Simulator. Measure CLKFX_OUT using the same steps as above. In the Sources tab. select ISE Simulator in the Simulator field. In the Wave window. 2. Select Properties.1 In-Depth Tutorial www. To save the signals list: 1. Click the + beside Xilinx ISE Simulator to expand the process hierarchy. “Behavioral Simulation Using ModelSim.com 101 . right-click the device line (xc3s700A-4fg484). ISE has full integration with the ISE Simulator. In the Sources tab. The saved signals list can easily be opened each time the simulation is started. 2. “Design Implementation. 3. rename the file name from the default wave. In the Project Properties dialog box. 6. and after simulation is rerun. follow the steps in Chapter 5. This comes out to approximately 26 MHz. This converts to 50 MHz. To implement the design. Select the test bench file (stopwatch_tb). Your behavioral simulation is complete.” Behavioral Simulation Using ISE Simulator Follow this section of the tutorial if you have skipped the previous section. select File > Save as. In the Save Format dialog box.” Now that you have a test bench in your project. which in turn should be the DCM CLK0 output. Locating the Simulation Processes The simulation processes in ISE enable you to run simulation on the design using ISE Simulator.Behavioral Simulation Using ISE Simulator R 5. ISE enables ISE Simulator to create the work directory.do. select File > Load in the Wave window to load this file.xilinx. and perform simulation based on simulation properties. After restarting the simulation. compile the source files. 3. 3. load the design. The measurement should read 38462 ps. To locate the ISE Simulator processes: 1. The measurement should read 20000 ps. Click Save.do to dcm_signal. Saving the Simulation The ModelSim simulator enables you to save the signals list in the Wave window after new signals or stimuli are added. Look at the bottom of the waveform for the distance between the two cursors.

com ISE 9. Generate a self-checking HDL test bench This process enables you to generate a self-checking HDL test bench equivalent to a test bench waveform (TBW) file and add the test bench to your project. See “Creating a Test Bench Waveform Using the Waveform Editor. ModelSim runs in the background to generate expected results and displays them in the ISE Simulator’s Test Bench Waveform Editor. 4. Right-click the Simulate Behavioral Model process. In the Process Properties dialog box (Figure 4-9). Note: For a detailed description of each property available in the Process Property dialog box.” Specifying Simulation Properties You will perform a behavioral simulation on the stopwatch design after you set some process properties for simulation. 6. Click the + sign next to ISE Simulator to expand the hierarchy in the Processes tab. Change the Simulation Run Time to 2000 ns. Click Apply and click OK. Simulate Behavioral Model This process starts the design simulation. This global setting enables you to now see all available properties. select the test bench file (stopwatch_tb). click Help. and to modify the properties for this tutorial: 1. 3. To see the behavioral simulation properties. 5. 7. In the Sources tab.xilinx. set the Property display level to Advanced. If you double-click this process.1 In-Depth Tutorial . ISE allows you to set several ISE Simulator properties in addition to the simulation netlist properties. 2. Select Properties.R Chapter 4: Behavioral Simulation The following simulation processes are available: • • • Check Syntax This process checks for syntax errors in the test bench. The test bench generated by this process contains output data and self-checking code that can be used to compare the data from later simulation runs. Note: This process is available only if you have a test bench waveform file from the ISE Simulator’s Test Bench Waveform Editor. You can also use this process to update an existing self-checking test bench. 102 www.

2. ISE automatically adds all the top-level ports to the Waveform window. Adding Signals To view signals during the simulation. double-click Simulate Behavioral Model. only the DCM signals are monitored to verify that they work correctly. you must add them to the Waveform window. Click the + next to uut stopwatch to expand the hierarchy. This is why the counter may seem like it is not working in a short simulation. add the DCM signals to the waveform. To start the behavioral simulation. In the Sim Hierarchy window.Behavioral Simulation Using ISE Simulator R Figure 4-9: Behavioral Simulation Process Properties Performing Simulation Once the process properties have been set. The following procedure explains how to add additional signals in the design hierarchy. and performs simulation for the time specified.xilinx.com 103 . ISE 9. compiles the source files.1 In-Depth Tutorial www. The first outputs to transition after RESET is released are SF_D and LCD_E at around 33 mS. you are ready to run the ISE Simulator. click the + next to stopwatch_tb to expand the hierarchy. For the purpose of this tutorial. To add additional signals in the design hierarchy: 1. The majority of this design runs at 100 Hz and would take a significant amount of time to simulate. loads the design. For the purpose of this tutorial. ISE Simulator creates the work directory. Additional signals are displayed in the Sim Hierarchy window.

Notice that the waveforms have not been drawn for the newly added signals. The graphics and the layout of the window for a schematic or VHDL flow may be different.com ISE 9.R Chapter 4: Behavioral Simulation Figure 4-10 shows the Sim hierarchy window for the Verilog flow. Therefore. By default.xilinx. hold down the Ctrl key. when new signals are added to the waveform window. Click and drag CLKIN_IN from the Sim Hierarchy window to the Waveform window. you must rerun the simulation for the desired amount of time.1 In-Depth Tutorial . 4. This is because ISE Simulator did not record the data for these signals. Select the following signals: ♦ ♦ ♦ ♦ RST_IN CLKFX_OUT CLK0_OUT LOCKED_OUT To select multiple signals. Click the Restart Simulation icon.Verilog flow 3. Figure 4-11: ISE Simulator Restart Simulation Icon 104 www. Figure 4-10: Sim Hierarchy Window . Drag all the selected signals to the waveform. right click on a selected signal and select Add To Waveform. 5. Click the + next to dcm1 in the Sim Hierarchy window. Rerunning Simulation To rerun the simulation in ISE Simulation: 1. ISE Simulator records data only for the signals that have been added to the waveform window while the simulation is running. Alternatively. 6.

It is not necessary to follow this section if you have added the tutorial test bench to the project already.xilinx. 2. This equals approximately 26 MHz. In the New Source Wizard. To measure the CLK0_OUT: 1. 5.Behavioral Simulation Using ISE Simulator R 2. If necessary. Type time_cnt_tb. ISE Simulator can add markers to measure the distance between signals. Figure 4-12: 3. At the ISE Simulator command prompt in the Sim Console. therefore. Measure CLKFX_OUT using the same steps as above.0 ns. ISE 9. The measurement should read 38. Click and drag the other end of the marker to the next rising edge.com 105 . This converts to 50 MHz. 4. Look at the top of the waveform for the distance between the marker. Click the Measure Marker icon. Select time_cnt in the Sources tab. enter run 2000 ns and press Enter. The Waveform Editor can be used to generate stimuli for top-level designs as well. To implement the design. The DCM outputs are valid only after the LOCKED_OUT signal is high.5 ns. follow the steps in Chapter 5. create the test bench waveform for a sub-module only. The CLK0_OUT should be 50 MHz and the CLKFX_OUT should be ~26 MHz. which is the input frequency from the test bench. Creating a Test Bench Waveform Source In this tutorial.1 In-Depth Tutorial www. The Waveform Editor is a test bench creation tool in ISE. The waveforms for the DCM are now visible in the Waveform window. Select Project > New Source. 3. 4. the DCM signals are analyzed only after the LOCKED_OUT signal has gone high.” Creating a Test Bench Waveform Using the Waveform Editor This section demonstrates how to use the Waveform Editor. select Test Bench Waveform as the source type. and to generate a VHDL test bench or Verilog test fixture. which in turn is the DCM CLK0 output. To create a test bench with the ISE Simulator Waveform Editor: 1. 2. Analyzing the Signals Now the DCM signals can be analyzed to verify that they work as expected. 6. The measurement should read 20. Your behavioral simulation is complete. The simulation runs for 2000 ns. “Design Implementation. Measure Marker Icon Place the marker on the first rising edge transition on the CLK0_OUT signal after the LOCKED_OUT signal has gone high. You can use the Waveform Editor to graphically enter stimuli. zoom in on the waveform.

The Waveform Editor opens in ISE. The Initialize Timing dialog box displays. fill in the fields as follows: ♦ ♦ ♦ ♦ Clock Time High: 10 Clock Time Low: 10 Input Setup Time: 5 Output Valid Delay: 5 9. 6. The Input Setup Time field defines when inputs must be valid. Click Next. and enables you to specify the timing parameters used during simulation. Click Next.R Chapter 4: Behavioral Simulation 5. Note: In the Select dialog box. Click Finish. The Clock Time High and Clock Time Low fields together define the clock period for which the design must operate. 8.Initialize Timing Dialog Box 106 www.com ISE 9. 10. 11. Click Finish.xilinx. the time_cnt file is the default source file because it is selected in the Sources tab (step 1). Figure 4-13: Waveform Editor . 7. Change the Initial Length of Test Bench to 3000.1 In-Depth Tutorial . In the Initialize Timing dialog box. The Output Valid Delay field defines the time after active clock edge when the outputs must be valid. Select the GSR (FPGA) from the Global Signals section.

The new test bench waveform source (time_cnt_tb.tbw in the Sources tab. 5.1 In-Depth Tutorial www. Applying Stimulus in the Waveform Editor View Click the Save icon in the toolbar. Click the CE cell at time 110 ns to set it high (CE is active high). Select time_cnt_tb. The width of this cell is determined by the Input setup delay and the Output valid delay. Enter the following input stimuli: 1.xilinx. The created test bench can be used to compare data from later simulation.tbw) is automatically added to the project.com 107 . 3. ISE 9. 6. Figure 4-14: 4. Click the CLR cell at time 150 ns to set it high. Double-click Generate Self-Checking Test Bench in the Process tab. 2. Click the CLR cell at time 230 ns to set it low. you can apply a transition (high/low).Behavioral Simulation Using ISE Simulator R The ISE Simulator’s Waveform Editor View opens in ISE. in the blue cell. Applying Stimulus In the Waveform Editor. A test bench containing output data and self checking code is generated and added to the project.

1 In-Depth Tutorial .R Chapter 4: Behavioral Simulation 108 www.xilinx.com ISE 9.

placing. The front-end design has already been compiled in an EDA interface tool.” In this chapter.1 In-Depth Tutorial www. The Design Implementation tools are embedded in the ISE™ software for easy access and project management. “Schematic-Based Design. NGC) from the front-end tool to the back-end Design Implementation tools. you will be passing an input netlist (EDN. routing. see Chapter 2.com 109 . This chapter demonstrates the ISE Implementation flow.xilinx. and generating a BIT file for your design. ISE 9. You will add timing constraints later through the Floorplan Editor. For details about compiling the design. and you will be incorporating placement constraints through a User Constraints File (UCF). • • • • • • • • • • • • • • • • • “Overview of Design Implementation” “Getting Started” “Specifying Options” “Creating Partitions” “Creating Timing Constraints” “Translating the Design” “Using the Constraints Editor” “Using the Floorplan Editor” “Mapping the Design” “Using Timing Analysis to Evaluate Block Delays After Mapping” “Placing and Routing the Design” “Using FPGA Editor to Verify the Place and Route” “Evaluating Post-Layout Timing” “Changing HDL with Partition” “Creating Configuration Data” “Creating a PROM File with iMPACT” “Command Line Implementation” Overview of Design Implementation Design Implementation is the process of translating. mapping.R Chapter 5 Design Implementation This chapter contains the following sections. “HDL-Based Design” or Chapter 3. This chapter is the first in the “Implementation-only Flow” and is an important chapter for the “HDL Design Flow” and the “Schematic Design Flow”.

xilinx. There are five inputs to the system: CLK. RESET. and an EDIF netlist file. Required Tutorial Files File Name stopwatch. 2. you will need to download the presynthesized design files provided on the Xilinx® web-site. Go to http://www. and SRTSTP.R Chapter 5: Design Implementation Getting Started The tutorial design emulates a runner’s stopwatch with actual and lap times. This system generates a traditional stopwatch with lap times and a traditional timer on a LCD display. design entry source files.xilinx. Click Next.ucf Description Input netlist file (EDIF) Table 5-1: Timer netlist file (NGC) User Constraints File 110 www.ucf file in your project. 1. select the top-level source file stopwatch.com ISE 9. MODE.com/support/techsup/tutorials/tutorial9. Skip to the “Specifying Options” section. Select stopwatch from the list. LAP_LOAD. With a UCF in the project. If you do not have a stopwatch.ucf as the file name.edn. and copy the pre-synthesized tutorial files (see Table 5-1) to your newly created working directory. Click Next.1 In-Depth Tutorial . Select Implementation Constraints File.htm. stopwatch. create a project in ISE and then add the downloaded source files to the project. 8. 7. 5.ngc timer_preset.edf or stopwatch. In the Sources tab. create one as follows: 1. 3. 6. you have created a project. 4. Starting from Design Implementation If you are beginning the tutorial from this chapter. Type stopwatch. Continuing from Design Entry If you have followed the tutorial using either the HDL Design flow or the Schematic Design flow. Select Project > New Source. you are now ready to begin this chapter. 2.ngc stopwatch. Create an empty working directory named Watch. Click Finish.

Select EDIF for the top_level SourceType. b. a. c. Map. e. This enables the design to be implemented. In the Processes tab. stopwatch. Ensure that you have set the Property display level to Advanced. The implementation properties control how the software maps. i. Select Properties from the right-click menu. j. Create a new project and add the EDIF netlist as follows: a. 2. enter ise &. g. In the Sources tab. routes. 4. right-click the Implement Design process. Click the Post-Map Static Timing Report Properties category. Click Finish. Click Next. places. h. The Process Properties dialog box provides access to the Translate. k.1i > Project Navigator. Copy the timer_preset. ISE 9. Click Next. 6. On a PC. 8. d. Change Report Type to Verbose Report. and optimizes a design.ngc file into the EDIF_Flow directory. select Start > Programs > Xilinx ISE 9. b.edn for the Input Design file. Change Report Type to Verbose Report. This report will be generated after the Map process is completed.com 111 . f. right-hand corner of the dialog box. Simulation.Specifying Options R 3. You will notice a series of categories.xilinx. select the stopwatch top-level file. Click the Post-Place & Route Static Timing Report Properties category.ucf for the Constraints file. 3.edn. This setting is in the lower. In the Sources tab. This global setting enables you to see all available properties. Place and Route. fg484 for the Package 4. 5. Select stopwatch. each contains properties for a different aspect of design implementation. Specifying Options This section describes how to set some properties for design implementation. Select stopwatch. Type EDIF_Flow for the Project Name.1 In-Depth Tutorial www. Select the following: Click Next. To set the implementation property options for this tutorial: 1. Open ISE. select the top-level module. Select File > New Project.edf or stopwatch. and Timing Report properties. Spartan3a for the Device Family xc3s700a for the Device -4 for the Speed Grade. On a workstation. 7.

Change the Place & Route Effort Level (Overall) to High. Figure 5-1: Post-Place & Route Static Timing Report Properties 9.1 In-Depth Tutorial . Click the Place & Route Properties category.R Chapter 5: Design Implementation This report will be generated after Place and Route is completed.com ISE 9. 10.xilinx. 112 www.

Creating Partitions R This option increases the overall effort level of Place and Route during implementation. such as effort levels on implementation tools. Please proceed to the next section. and logic can be at the top level partition. Figure 5-2: Place & Route Properties 11. To enable partitions for this design: ISE 9. and only the effected partitions are re-implemented. Partitions can be nested hierarchically and be defined on any HDL module instance in the design. Partitions also detect command line changes.com 113 . If you are doing the EDIF flow. the partition is set on the module instance and for VHDL. Partitions automatically detect input source changes. the partition is set on the entity architecture. A module with multiple instances can have multiple partitions—a partition on each instance. The creation of Partitions was done through the synthesis tool. Click OK to exit the Process Properties dialog box. including HDL changes and certain constraint changes. Partitions do not need ranges for implementation re-use. In Verilog. The top level of the HDL design has a default partition.1 In-Depth Tutorial www. you will not get the option to create Partitions in Project Navigator. Creating Partitions A partition is created for an instance in your logical design to indicate that the implementation for that instance should be reused when possible.xilinx.

1 In-Depth Tutorial . To launch the Constraints Editor: 1. without the design entry tools. 3. The top level partition is set to routing by default. Note: In ISE 9. select Stopwatch In the Processes tab.R Chapter 5: Design Implementation 1. To do this. expand the User Constraints hierarchy.com ISE 9. Select New Partition from the menu. or Synthesis. Repeat steps 1 and 2 for the timer_state module. The Constraints Editor and Floorplan Editor are graphical tools that enable you to enter timing and pin location constraints. Repeat steps 1 and 2 for the timer_inst module in VHDL and Verilog designs only. Creating Timing Constraints The User Constraints File (UCF) provides a mechanism for constraining a logical design without returning to the design entry tools. you must understand the exact syntax needed to define constraints. 2. 2. In the Sources tab. The preserve status can be changed to Routing. which gets the status from the top level partition.xilinx. right click on a partitioned source file and select Partition Properties. select lcd_cntrl_inst module and right-click on it. 114 www. However. Figure 5-3: New Partitions on LCD_CNTRL_INST module The Preserve status is set to inherit. In the Sources tab. Placement. 4.1i there is a known issue that will not allow MAP to complete a second iteration if a Partition is placed on a schematic module.

This gives you complete control over how a design is processed. The merged netlist describes the logic in the design as well as any location and timing constraints. Translating the Design ISE manages the files created during implementation. • • ISE 9. Double-click Create Timing Constraints. Adds constraints from the User Constraints File (UCF) to the merged netlist.1 In-Depth Tutorial www. Performs timing specification and logical design rule checks.xilinx. the NGDBuild program performs the following functions: • Converts input design netlists and writes results to a single merged NGD netlist. You then run through the entire flow by double-clicking Implement Design. Figure 5-4: Create Timing Constraints Process This automatically runs the Translate step. Typically.Translating the Design R 3. During translation. you set your options first. one step at a time. Then the Constraints Editor opens. The ISE tools use the settings that you specified in the Process Properties dialog box.com 115 . which is discussed in the following section. This tutorial illustrates the implementation.

to produce a newer NGD file. The Translate step (NGDBuild) uses the UCF file. Add new constraints to your design. a PERIOD.xilinx. Alternatively. and enables you to define the associated period. which incorporates the changes made. the stopwatch. Input files to the Constraints Editor are: NGD (Native Generic Database) File The NGD file serves as input to the mapper. The Map program (the next section in the design flow) then reads the NGD. Global OFFSET OUT.ucf files are automatically read into the Constraints Editor.ngd and stopwatch. Translate is run and ISE launches the Constraints Editor. pad to 116 www.1 In-Depth Tutorial .com ISE 9. The Global branch of the Timing Constraints tab automatically displays all the clock nets in your design.R Chapter 5: Design Implementation Using the Constraints Editor When you run the Create Timing Constraints process. The Constraints Editor generates a valid UCF file. In this design. and TIMEGRP OFFSET IN constraint will be written in the UCF and used during implementation. along with design source netlists. which then outputs the physical design database. when the NGD file is opened. an existing UCF file with the same base name as the NGD file is used. In the following section. an NCD (Native Circuit Description) file. The Constraints Editor enables you to: • • • Edit constraints previously defined in a UCF file. Global OFFSET IN. you can specify the name of the UCF file. • Corresponding UCF (User Constraint File) By default.

verify that Specify Time is selected.Global Branch Figure 5-6: Constraints Editor .xilinx.Using the Constraints Editor R setup.1 In-Depth Tutorial www.0 in the Time field. 2.Global Branch In the Constraints Editor. Enter a value of 7. 3. Note that many of the internal names will vary depending on the design flow and synthesis tool used. Figure 5-5: Constraints Editor in Project Navigator . This enables you to define an explicit period for the clock. and clock to pad values.com 117 . Double-click the Period cell on the row associated with the clock net CLK. The Clock Period dialog box opens. For the Clock Signal Definition. edit the constraints as follows: 1. ISE 9.

This selects the elements for creating a grouped offset. This creates a Global OFFSET OUT constraint for the CLK signal Figure 5-9: Completed Global constraints in Constraints Editor 10. 6. Hold down the Shift key and select SF_D<7>. 11. enter a value of 60 in the Time field. A listing of the current ports is displayed on the left. INPUT JITTER Constraint Value The period cell is updated with the global clock period constraint that you just defined (with a default 50% duty cycle). Single click the Pad to Setup cell for clock signal CLK and type 6. 118 www. PERIOD Constraint Values For the Input Jitter section. Verify that ns is selected from the Units drop-down list. Verify that ps is selected from the Units drop-down list. Click OK.com ISE 9.1 In-Depth Tutorial . This creates a Global OFFSET IN constraints for the CLK signal. Figure 5-8: 7. Single click the Clock to Pad cell for clock signal CLK and type 38. Select SF_D<0> in the Port Name Column. 9. 8. Select the Ports branch from the Timing Constraints tab of the Sources panel. Figure 5-7: 5.R Chapter 5: Design Implementation 4. 12.xilinx.

Figure 5-10: Creating a Grouped OFFSET 14. 16. In the Select Group drop-down list.Using the Constraints Editor R 13. and click Create Group to create the group. In the Group Name field. 15. type display_grp. Figure 5-11: Setting Constraints for the Grouped OFFSET The Clock to Pad dialog box opens. Enter 32 for the Timing Requirement. Click Clock to Pad.com 119 .xilinx. select the group you just created. ISE 9.1 In-Depth Tutorial www.

ucf file in your current working directory. 2. and BUFGs.xilinx. Double-click Assign Package Pins Post-Translate. Close the Constraints Editor by selecting File > Close. to produce a newer NGD file. 3. Select the stopwatch module in the Sources window. Select CLK in the Relative to Clock Pad Net field. Click OK 19. Clock to Pad Dialog Box The changes are now saved in the stopwatch. 4. Gigabit Transceivers (GTs). click the + next to Implement Design to expand the process hierarchy in the Processes window. Digital Clock Managers (DCMs).1 In-Depth Tutorial . Floorplan Editor also places Global Logic at the Slice level with Block Ram. located under the Translate process. 1. 120 www.com ISE 9. The NGD file incorporates the changes made in the design and the UCF file from the previous section. Figure 5-12: 18. along with the design source netlists. 20.R Chapter 5: Design Implementation 17. The Translate step uses this UCF file. Floorplan Editor generates a valid UCF file. Select File > Save. Using the Floorplan Editor Use the Floorplan Editor to add and edit the pin locations and area group constraints defined in the NGD file. This section describes the creation of IOB assignments for several signals. Floorplan Editor edits the UCF file by adding the newly created placement constraints. Click the + next to Translate.

Figure 5-13: Edit Package Pin Placement This process launches Floorplan Editor. 8. located under the User Constraints process. Figure 5-14: 5. enter pin locations using the following values: ♦ ♦ ♦ LCD_E → AB4 LCD_RS → Y14 LCD_RW → W13 ISE 9. Floorplan Editor Select the Package tab in the work space.xilinx. This view shows the graphical representation of the device package. change the center filter from ALL to IOs.Using the Floorplan Editor R Note: For an EDIF project. 7. This window displays all the objects in the design. Select the Design Object tab in Processes panel. double-click Assign Package Pins. In the Design Object tab. then scroll down to the nets that begin with “LCD_”.com 121 .1 In-Depth Tutorial www. 6. In the LOC column.

1 In-Depth Tutorial .R Chapter 5: Design Implementation Figure 5-15: Pin Locations To place IOs in the Package Pin view using the drag and drop method: 9.com ISE 9. From the Design Object tab.xilinx. click and drag the following signals to the associated location in the Package Pin window: ♦ ♦ ♦ ♦ LAP_LOAD → T16 RESET → U15 MODE → T14 STRTSTOP → T15 122 www.

right-click on Map and select Run. 11. Once the pins are locked down. In the Processes tab. Mapping the Design Now that all implementation strategies have been defined (properties and constraints).com 123 . Select the stopwatch module in the Sources window. Note: This can also be accomplished by double-clicking Map.1 In-Depth Tutorial www. Close Floorplan Editor by selecting File > Close. continue with the implementation of the design.xilinx. 1. 2. ISE 9.ucf file in your current working directory.Mapping the Design R Figure 5-16: Drag and Drop IOs in the Package Pins View 10. The changes are saved in the stopwatch. select File > Save.

Figure 5-17: Mapping the Design The design is mapped into CLBs and IOBs. Map performs the following functions: • • Allocates CLB and IOB resources for all basic logic elements in the design.1 In-Depth Tutorial .R Chapter 5: Design Implementation 3.com ISE 9. Table 5-2: Reports Generated by Map Includes warning and error messages from the translation process. and device utilization. Each step generates its own report as shown in the following table.xilinx. Includes information on how the target device resources are allocated. refer to the Development System Reference Guide. This Guide is available All NGDBUILD and with the collection of software manuals and is accessible from ISE by selecting Help > Software Manuals. Expand the Implement Design hierarchy to see the progress through implementation. Processes all location and timing constraints. performs target device optimizations. and runs a design rule check on the resulting mapped netlist.com/support/sw_manuals/xilinx9/.xilinx. Translation Report Map Report For detailed information on the Map reports. references to trimmed logic. 124 www. or from the MAP Reports web at http://www.

Errors. Look for Warnings. such as Translation Report or Map Report. Figure 5-18: 3. Figure 5-19: Implementation Reports shown in Design Summary ISE 9. Double-click a report. Expand the Translate or Map hierarchy.xilinx.1 In-Depth Tutorial www. The Design Summary also contains these reports. Translation Report and Map Report Processes Review the report. and Information (INFO).com 125 . 2.Mapping the Design R To view a report: 1.

Timing Analyzer automatically launches and displays the report. Since you defined timing constraints for the stopwatch design. Because the design is not yet placed and routed. If your design is extremely dense. the timing report will display the path for each of the timing constraints. evaluate the design after the map stage. the Post-Map Static Timing Report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. To view the Post-Map Static Timing Report and review the PERIOD Constraints that were entered earlier: 1. The timing report describes the logical block delays and estimated routing delays.com ISE 9. Figure 5-20: Post-Map Static Timing Report Process 126 www. evaluate the Logic Level details in the Post-Map Static Timing Report to evaluate the logical paths in the design. Double-click Generate Post-Map Static Timing.1 In-Depth Tutorial . a path with 10 ns of block delay should meet a 20 ns timing constraint after it is placed and routed. double-click Analyze Post-Map Static Timing Report. A rough guideline (known as the 50/50 rule) specifies that the block delays in any single path make up approximately 50% of the total path delay after the design is routed. To open the Post-Map Static Timing Report. This analysis can help to determine if your timing constraints are going to be met. In the Processes tab. Evaluation verifies that block delays are reasonable given the design specifications.xilinx. This report is produced after Map and prior to Place and Route (PAR). 2.R Chapter 5: Design Implementation Using Timing Analysis to Evaluate Block Delays After Mapping After the design is mapped. Estimating Timing Goals with the 50/50 Rule For a preliminary indication of how realistic your timing goals are. Report Paths in Timing Constraints Option Use the Post-Map Static Timing Report to determine timing violations that may occur prior to running PAR. 3. The net delays provided are based on an optimal distance between blocks (also referred to as unplaced floors). actual routing delay information is not available. click the + next to Map to expand the process hierarchy. For example.

Figure 5-21: Selecting Post-Map Static Timing constraint The work space shows the report for the selected constraint. For example. floors. After viewing the report. Selecting one of the three paths allows you to see a breakdown of the path which contains the component and routing delays. One of two place-and-route algorithms is performed during the Place & Route (PAR) process: • Timing Driven PAR PAR is run with the timing constraints specified in the input netlist and/or in the constraints file.g. PAR still processes a design based on the relationship between the block delays. The Post-Map Static Timing Report will list any pre-PAR timing violations. At the top of this report. the Place & Route (PAR) process performs timing driven placement and routing. and timing specifications for the design. the design can be placed and routed. PAR stops and generates an error message. and there are block delays of 7 ns and unplaced floor net delays of 3 ns. Since you defined timing constraints earlier in this chapter. • Non-Timing Driven PAR PAR is run. 88. double-click Place & Route.1 In-Depth Tutorial www. To run PAR. close the Timing Analyzer by selecting File > Close. In this example.0% logic. 12. ISE 9.com 127 . 1. only three paths per timing constraint will be shown. ignoring all timing constraints. if a PERIOD constraint of 8 ns is specified for a path. PAR fails because it determines that the total delay (10 ns) is greater than the constraint placed on the design (8 ns). Placing and Routing the Design After the mapped design is evaluated. in the Processes tab.xilinx.0% route).Placing and Routing the Design R 4. 5. The unplaced floors listed are estimates (indicated by the letter “e” next to the net delay) based on optimal placement of blocks. you will find the selected period constraint and the minimum period obtained by the tools after mapping. Note: Even if you do not generate a timing report. Notice that the report displays the percentage of logic versus the percentage of routing at the end of each path (e. Select the TS_dcm_inst_CLKX_BUF timing constraint under the Timing tab. By default.

Double-click Place & Route Report. 3. Lists all nets in the design and the delays of all loads on the net. Use this report to verify that pins locked down were placed in the correct location. Table 5-3: Reports Generated by PAR Report Place & Route Report Description Provides a device utilization and delay summary. Note: You can also display and examine the Pad Report and Asynchronous Delay Report.xilinx. This Guide is available with the collection of software manuals and is accessible from ISE by selecting Help > Online Documentation. Click the + next to Place & Route to expand the process hierarchy.xilinx. Pad Report Asynchronous Delay Report All PAR Reports The Design Summary also displays the Place and Route Reports.com ISE 9. For detailed information on the PAR reports. Use this report to verify that the design successfully routed and that all timing constraints were met.com/support/sw_manuals/xi linx9/.1 In-Depth Tutorial . Figure 5-22: Design Summary of the Place & Route Report 128 www. Contains a report of the location of the device pins. or from the web at http://www. refer to the Development System Reference Guide.R Chapter 5: Design Implementation To review the reports that are generated after the Place & Route process is completed: 2.

and double-click View/Edit Routed Design (FPGA Editor). Click the + next to Place & Route to expand the process hierarchy.1 In-Depth Tutorial www. Figure 5-23: View/Edit Routed Design (FPGA Editor) Process ISE 9. View and change the nets connected to the capture units of an Integrated Logic Analyzer (ILA) core in your design.com 129 .Using FPGA Editor to Verify the Place and Route R Using FPGA Editor to Verify the Place and Route Use the FPGA Editor to display and configure Field Programmable Gate Arrays (FPGAs). • • To view the actual design layout of the FPGA: 1. Use FPGA Editor to: • • • Place and route critical components before running the automatic place-and-route tools. Macro files (NMC) and Physical Constraints Files (PCF). Add probes to your design to examine the signal states of the targeted device. The FPGA Editor reads and writes Native Circuit Description (NCD) files.xilinx. Run the BitGen program and download the resulting bitstream file to the targeted device. Finish placement and routing if the routing program does not completely route your design. Probes are used to route the value of internal nets to an IOB (Input/Output Block) for analysis during debugging of a device.

This enables you to view all of the possible nets in the design. Figure 5-24: 3.R Chapter 5: Design Implementation 2.xilinx. change the List Window from All Components to All Nets.1 In-Depth Tutorial . Clock Net 130 www.com ISE 9. To exit FPGA Editor. List Window in FPGA Editor Select the clk_262144K (Clock) net to see the fanout of the clock net. In FPGA Editor. select File > Exit. Figure 5-25: 4.

This launches the Floorplan Implemented window and highlights the corresponding data path. The net delays are now reported as actual routing delays after the Place and Route process. This report evaluates the logical block delays and the routing delays. ISE 9. With the TS_DCM_INST_CLKFX_BUF constraint highlighted in the Timing Analyzer tab. This changes the routing view for the highlighted data path from a simplified view to the actual routing 5. The post-layout report indicates that the logical delay value now equals between 30% and 40% of the period.1 In-Depth Tutorial www.Evaluating Post-Layout Timing R Evaluating Post-Layout Timing After the design is placed and routed. In general. 4. the worst case path is mainly made up of logic delay. you can reduce excessive block delays and improve design performance by decreasing the number of logic levels in the design.com 131 . ♦ ♦ The post-layout result does not necessarily follow the 50/50 rule previously described because the worst case path primarily includes component delays. a Post Layout Timing Report is generated by default to verify that the design meets your specified timing goals. Expand the Generate Post-Place & Route Static Timing hierarchy. The following is a summary of the Post-Place & Route Static Timing Report for the stopwatch design: ♦ The minimum period value increased due to the actual routing delays. Select the Timing tab in the Sources panel and select the Timing Objects tab in the Processes panel. select the first hyperlink beginning with Maximum Data Path. The Post-Map timing report showed logic delays contributed to 80% to 90% of the minimum period attained. Double-click Analyze Post-Place & Route Static Timing Report to open the report in Timing Analyzer. 2. Or you can select the Timing Constraint in the Design Summary and then a timing constraint hyperlink to launch Timing Analyzer.xilinx. 3. For some hard to meet timing constraints. expecting the timing of these paths to be reduced any further is unrealistic. The total unplaced floors estimate changed as well. To display this report: 1. Since total routing delay makes up only a small percentage of the total path delay spread out across two or three nets. Select View > Overlays > Toggle Simplified and Actual Views.

com ISE 9. 7. The change will be in the LCD_CNTRL_INST module.xilinx.1 In-Depth Tutorial .R Chapter 5: Design Implementation Figure 5-26: Floorplan Implemented . and PAR reports will show which partitions are updated and which ones are preserved.Data Path with Actual Routing 6. The Synthesis. you will not be able to do this section.Data Path with Simplified Routing Figure 5-27: Floorplan Implemented . Changing HDL with Partition Now that the design has been implemented. the next step is to update the design with an HDL change. If you are doing the EDIF flow. Select File > Close to exit the Floorplan Implemented view. Please proceed to the next section. MAP. Hold the cursor over different nets or objects in the outlined path to observe timing delay and other information about that portion of the path. 132 www. Select File > Close again to close the Post-Place & Route Static Timing report. so only that partition will need to be re-synthesized and re-implemented. 8.

Select Run from the menu. Notice which partitions were preserved and which partitions were re-used. 2. since the implementation tools only need to re-implement the LCD_CNTRL_INST module. select File > Save. To save the changes to LCD_CNTRL_INST. select the top-level source file stopwatch and in the Processes tab. The rest of the design is re-used. Make the following change according to your HDL language: ♦ ♦ If you are using Verilog: On line 377 and 564. then select Partitions Report. then select Partition Status.[period] 3. Select the MAP Report. -. ISE 9. Notice which partitions were preserved and which partitions were re-used. // [period] If you are using VHDL: On line 326 and 514. -.1 In-Depth Tutorial www.[colon] to sf_d_temp <= “00101110”. In the Design Summary view. Notice which partitions were preserved and which partitions were re-used. Select the Place and Route Report.Changing HDL with Partition R 1. change the code from sf_d_temp = 8’b00111010. change the code from sf_d_temp <= “00111010”. 4. view the following reports: ♦ ♦ ♦ Select the Synthesis Report.xilinx.com 133 . // [colon] to sf_d_temp = 8’b00101110. In the Sources tab. Notice that the implementation is faster with partitions. Open the LCD_CNTRL_INST module in the text editor by double-clicking it in the Sources tab. 5. then select Guide Report. right-click on Place & Route. Figure 5-28: LCD_CNTRL_INST Partition is Out of Date 6.

In this tutorial. 134 www. you will create configuration data for a Xilinx Serial PROM. Change the FGPA Start-Up Clock property from CCLK to JTAG Clock. Figure 5-29: 3. Right-click the Generate Programming File process. Select Properties. The Process Properties dialog box opens. Process Properties Startup Options Click the Startup Options category. you need to create configuration data.xilinx.1 In-Depth Tutorial .R Chapter 5: Design Implementation Creating Configuration Data After analyzing the design through timing constraints in Timing Analyzer. set the properties and run configuration as follows: 1.com ISE 9. 4. A configuration bitstream is created for downloading to a target device or for formatting into a PROM programming file. To create a bitstream for the target device. 2.

Click OK to apply the new properties. Figure 5-30: 5. which contains the actual configuration data. double-click Generate Programming File to create a bitstream of this design. all you need is a bitstream file. Figure 5-31: Programming File Generation Report Process Creating a PROM File with iMPACT To program a single device using iMPACT. Change the Security property to Enable Readback and Reconfiguration. 6. you must use iMPACT to create a PROM file.Creating a PROM File with iMPACT R Note: You can use CCLK if you are configuring Select Map or Serial Slave. To program several devices in a daisy chain configuration. Click the + next to Generate Programming File to expand the process hierarchy. 7. Process Properties Readback Options Click the Readback Options category. or to program your devices using a PROM.xilinx. To review the Programming File Generation Report. iMPACT accepts any number of bitstreams and creates one or more PROM files containing one or more daisy chain configurations. 9.1 In-Depth Tutorial www. the stopwatch. In the Processes tab.bit file).com 135 . 8. Verify that the specified options were used when creating the configuration data. a wizard enables you to do the following: ISE 9. In iMPACT. The BitGen program creates the bitstream file (in this tutorial. double-click Programming File Generation Report. 10.

R Chapter 5: Design Implementation • • • • Create a PROM file. located under the Generated Programming File process hierarchy. Add additional bitstreams to the daisy chain. Figure 5-32: Welcome to iMPACT Dialog Box 136 www.com ISE 9. ACE. For this tutorial. double-click Generate PROM. Create additional daisy chains. In the Processes tab.xilinx. 2.1 In-Depth Tutorial . select Prepare a PROM File. 3. or immediately save the current PROM file configuration. Click Next. JTAG File. create a PROM file in iMPACT as follows: 1. Remove the current bitstream and start over. In the Welcome to iMPACT dialog box.

com 137 . Note: You will receive a warning that the startup clock is being changed from jtag to CCLK. select Auto Select PROM. Specify Xilinx PROM Device Dialog Box In the File Generation Summary dialog box. type stopwatch1. select MCS. Figure 5-33: Prepare PROM Files Dialog Box 5. click Finish. In the Prepare PROM Files dialog box. click OK and then select the stopwatch. Click Next. In the Specify Xilinx Serial PROM Device dialog box. For PROM File Name. 10.1 In-Depth Tutorial www.bit file. select Xilinx PROM. 6. In the Add Device File dialog box. 9. Under PROM File Format. Click Next. ISE 9. set the following values: ♦ ♦ ♦ Under “I want to target a:”. Figure 5-34: 8.xilinx. 7. Click No when you are asked if you would like to add another design file to the datastream.Creating a PROM File with iMPACT R 4.

To create an editable batch file. Command line options may also be obtained by typing the executable name followed by the -h option at a command prompt.cmd_log in read-only mode. 138 www. refer to the “XFLOW” section in the Development System Reference Guide. XFLOW is a Xilinx command line tool that automates the Xilinx implementation and simulation flows. select File > Close. XFLOW reads a design file as input. This Guide is available with the collection of software manuals and is accessible from ISE by selecting Help > Software Manuals. This completes the Design Implementation chapter of the tutorial. For more information on XFLOW. Select Operations > Generate File. With the resulting stopwatch. iMPACT displays the PROM associated with your bit file. see the ISE Help. stopwatch1. or from the web at http://www. refer to the Development System Reference Guide. This allows a user to verify the options being used or to create a command batch file to replicate the design flow. see the iMPACT Help. you are ready for programming your device using iMPACT.xilinx. 12.1 In-Depth Tutorial . available from the iMPACT application by selecting Help > Help Topics. To close iMPACT. Another useful tool for automating design implementation is XFLOW.bit.cmd_log using either the copy-and-paste method or the drag-anddrop method into a text file. For more information on programming a device. This process opens a file named <source_name>. available from the ISE application by selecting Help > Help Topics. flow and option files. At any stage of the design flow you can look at the command line arguments for completed processes by double-clicking View Command Line Log File from the Design Entry Utilities process hierarchy in the Processes tab.com ISE 9.com/support/sw_manuals/xilinx9/. Command line options are organized according to implementation tools. For more information on this design flow and implementation methodologies.xilinx. select File > Save As and enter the desired file name. Command Line Implementation ISE allows a user to easily view and extract the command line arguments for the various steps of the implementation process.mcs and a MSK file generated along with the BIT file.R Chapter 5: Design Implementation 11. For a complete listing of command line options for most Xilinx executables. Sections of the Command Line Log File may also be copied from <source_name>.

“Behavioral Simulation” for information on installing and setting up ModelSim. Performing a timing simulation in addition to a static timing analysis will help to uncover issues that cannot be found in a static timing analysis alone.1i and ModelSim simulator installed. Timing simulation uses the detailed timing and design layout information that is available after place and route.com 139 . you will perform a timing simulation using either the ModelSim simulator or the Xilinx ISE Simulator.1 In-Depth Tutorial www.R Chapter 6 Timing Simulation This chapter includes the following sections. For this reason. which closely matches the actual device operation.xilinx. you must have Xilinx ISE™ 9. Getting Started The following sections outline the requirements to perform this part of the tutorial flow. Timing (post-place and route) simulation is a highly recommended part of the HDL design flow for Xilinx® devices. timing simulation is performed after the design has been placed and routed. Required Software To simulate with ModelSim. • • • • “Overview of Timing Simulation Flow” “Getting Started” “Timing Simulation Using ModelSim” “Timing Simulation Using Xilinx ISE Simulator” Overview of Timing Simulation Flow Timing simulation uses the block and routing delay information from a routed design to give a more accurate assessment of the behavior of the circuit under worst-case conditions. In this chapter. This enables simulation of the design. Simulating with the Xilinx ISE simulator requires that the ISE 9. the design should be analyzed both statically and dynamically. Refer to Chapter 4. To verify the design.1i software is installed ISE 9.

This Guide is accessible from within ISE by selecting Help > Software Manuals. and control simulation properties for ModelSim. Specifying a Simulator To select either the desired simulator to simulate the stopwatch design. have a placed and routed design. • Test Bench File (VHDL or Verilog) In order to simulate the design. see to “Xilinx Simulation Libraries” in Chapter 4. complete the following: 1. “Behavioral Simulation”. In the Sources tab. which are modeled in the SIMPRIM library. compile source files. Please refer to the “Adding an HDL Test Bench” in Chapter 4 if you do not already have a test bench in your project. For more information on compiling and setting up Xilinx simulation libraries. To perform timing simulation of Xilinx designs in any HDL simulator. Selecting a different simulator (e. Select ISE Simulator (VHDL/Verilog) or Modelsim with the appropriate version and language in the Simulator value field.1 In-Depth Tutorial .com/support/sw_manuals/xilinx9/.xilinx. Note: To simulate with the ISE Simulator. the SIMPRIM library should already be compiled.R Chapter 6: Timing Simulation Required Files The timing simulation flow requires the following files: • Design Files (VHDL or Verilog) This chapter assumes that you have completed Chapter 5. initialize simulation. 140 www. the SIMPRIM library is needed to simulate the design. For additional information about simulation. You should use the same test bench that was used to perform the behavioral simulation. and from the web at http://www. If you completed Chapter 4. NC-Sim or VCS) will set the correct options for Netgen to create a simulation netlist for that simulator but Project Navigator will not directly open the simulator. the end result is the same. “Design Implementation.” and thus.com ISE 9. ISE enables you to create work directories. In the Project Properties dialog box click the down arrow in the Simulator value field to display a list of simulators. see Chapter 5 of the Synthesis and Verification Guide. 3. the SIMPRIM library must be set up correctly. and for a list of other supported simulators. right-click the device line (xc3s700A-4fg484) and select Properties. Whether you choose to use the ModelSim simulator or the ISE Simulator for this tutorial. a test bench is needed to provide stimulus to the design. The timing simulation netlist created by Xilinx is composed entirely of instantiated primitives.xilinx. skip to “Timing Simulation Using Xilinx ISE Simulator”. 2. Note: ModelSim simulators and the ISE Simulator are the only simulators that are integrated with Project Navigator.g. The NetGen tool will be used in this chapter to create a simulation netlist from the placed and routed design which will be used to represent the design during the Timing Simulation. Timing Simulation Using ModelSim Xilinx ISE provides an integrated flow with the Mentor ModelSim simulator. • Xilinx Simulation Libraries For timing simulation.

These properties set the options that NetGen uses when generating the simulation netlist. 5.xilinx. 2. For a description of each property. If ModelSim is installed but the processes are not available. The Process Properties dialog box displays. Select the Simulation Model Properties category. click the + next to ModelSim Simulator to expand the process hierarchy. click the Help button. select Edit > Preferences. In the right pane. Select the test bench file (stopwatch_tb). under Model Tech Simulator. or Project Navigator cannot find modelsim. 6. Note: If the ModelSim Simulator processes do not appear. Ensure that you have set the Property display level to Advanced. click the + next to ISE General to expand the ISE preferences.Timing Simulation Using ModelSim R Specifying Simulation Process Properties To set the simulation process properties: 1. 7. and click Integrated Tools in the left pane. In the Sources tab.com 141 . Select Properties. 4. ISE 9. For example. browse to the location of modelsim. it means that either ModelSim is not selected as the Simulator in the Project Properties dialog box.exe file. The properties should appear as shown in Figure 6-1. 3.exe. c:\modeltech_xe\win32xoem\modelsim. select Post-Route Simulation in the Sources for field. Right-click Simulate Post-Place & Route Model. the Project Navigator preferences may not be set correctly.exe.1 In-Depth Tutorial www. To set the ModelSim location. This global setting enables you to see all available properties. In the Processes tab.

the Structure window. 142 www. three windows open when timing simulation is launched from ISE. This tab gives you control over the ModelSim simulation windows.com ISE 9. Select the Simulation Properties category.1 In-Depth Tutorial .xilinx. They are the Signal window. These properties set the options that ModelSim uses to run the timing simulation. For more details on ModelSim Simulator windows. click the Help button. and the Wave window. refer to the ModelSim User Guide. the default Simulation Model Properties are used. The properties should appear as shown in Figure 6-2. Figure 6-1: 8. By default.R Chapter 6: Timing Simulation For this tutorial. 9. Simulation Model Properties Select the Display Properties category. For a description of each property.

There are two basic methods for adding signals to the Simulator Wave window. ISE automatically adds all the top-level ports to the Wave window. In the Simulation Properties tab. Note: The majority of this design runs at 100 Hz and would take a significant amount of time to simulate. you must add them to the Wave window.Timing Simulation Using ModelSim R 10. This is why the counter will seem like it is not working in a short simulation. double-click Simulate Post-Place and Route Model in the Processes tab. Additional signals are displayed in the Signal window based on the selected structure in the Structure window. load the design. Figure 6-2: Simulation Properties 11. ISE 9. For the purpose of this tutorial.com 143 . only the DCM signals will be monitored to verify that they work correctly. ISE will then call ModelSim and create the working directory. Performing Simulation To start the timing simulation. Click OK to close the Process Properties dialog box.1 In-Depth Tutorial www.xilinx. Adding Signals To view signals during the simulation. set the Simulation Run Time property to 2000 ns. ISE will run NetGen to create the timing simulation model. compile the source files. and run the simulation for the time specified. Highlight signals in the Signal/Object window and then select Add > Wave > Selected Signals. • • Drag and drop from the Signal/Object window.

Figure 6-3: 1. you will be adding the DCM signals to the waveform. All the signal names for the DCM will be listed.Schematic Flow Click the Structure/Instance window and select Edit > Find. The graphics and the layout of the Structure/Instance window for a Verilog or VHDL flow may appear different. 3. 4. 144 www. Select the Signal/Object window and select Edit > Find. select X_DCM and click on the signals/objects window. all the windows are docked by default. 6. All windows can be undocked by clicking the Undock icon.1 In-Depth Tutorial . Type in X_DCM in the search box and select Entity/Module in the Field section. Structure/Instance Window . 5. Figure 6-4: 2. Click and drag CLKIN from the Signal/Object window to the Wave window.R Chapter 6: Timing Simulation The following procedure explains how to add additional signals in the design hierarchy.0 or higher. Once ModelSim locates X_DCM. 7.com ISE 9. Note: If you are using ModelSim version 6.xilinx. Type CLKIN in the search box and select the Exact checkbox. Figure 6-4 shows the Structure/Instance window for the Schematic flow. In this tutorial. click the + next to uut to expand the hierarchy. Undock icon In the Structure/Instance window.

Click anywhere in the Wave window. The waveform should look as shown in Figure 6-5. Note: Stretch the first column in the waveform to see the signals clearly. Click and drag the following signals from the Signal/Object window to the Wave window: ♦ ♦ ♦ ♦ RST CLKFX CLK0 LOCKED Note: Multiple signals can be selected by holding down the Ctrl key. To add a divider called DCM Signals: 1. Right-click the Wave window and click Insert > Divider.1 In-Depth Tutorial www. The hierarchy in the signal name can also be turned off by selecting Tools > Options > Wave Preferences. 2. 3. Enter DCM Signals in the Divider Name box. Figure 6-5: The Resulting Waveform ISE 9. 5. Click and drag the newly created divider to above the CLKIN signal. Adding Dividers Modelsim has the capability to add dividers in the Wave window to make it easier to differentiate the signals. enter 2 and click OK. undock the window and then maximize the window for a larger view of the waveform.Timing Simulation Using ModelSim R 8. In the Display Signal Path box. If necessary.xilinx. In place of using the drag and drop method select Add to Wave > Selected Signals.com 145 . 4.

3. Modelsim has the capability to add cursors to carefully measure the distance between signals. To measure the CLK0: 146 www. The DCM signals should only be analyzed after the LOCKED signal has gone high. ModelSim will only record data for the signals that have been added to the Wave window while the simulation is running. The CLK0 needs to be 50 Mhz and the CLKFX should be ~26 Mhz. By default. Figure 6-8: Entering the Run Command The simulation will run for 2000 ns. This is because ModelSim did not record the data for these signals. Rerunning Simulation To restart and re-run the simulation: 1. Therefore.xilinx. Analyzing the Signals Now the DCM signals can be analyzed to verify that it works as expected. Until the LOCKED signal is high the DCM outputs are not valid.1 In-Depth Tutorial . after new signals are added to the Wave window. you need to rerun the simulation for the desired amount of time. enter run 2000 ns and hit the Enter key.R Chapter 6: Timing Simulation Notice that the waveforms have not been drawn for the newly added signals. The waveforms for the DCM should now be visible in the Wave window. Click Restart. Figure 6-6: The Restart dialog box opens. Restart Simulation Icon Figure 6-7: 2. Restart Dialog Box At the ModelSim command prompt.com ISE 9. Click the Restart Simulation icon.

Click and drag the second cursor to a position just right of the first cursor on the CLK0 signal. 4. Click the Find Next Transition icon twice to move the cursor to the next rising edge on the CLK0 signal. 1. This converts to 50 Mhz. 2. Your timing simulation is complete and you are ready to program your device by following Chapter 7. Figure 6-10: 3.do.do to dcm_signal_tim. The saved signals list can easily be loaded each time the simulation is started. “iMPACT Tutorial. 2.” ISE 9. This equals approximately 26 Mhz. which is the input frequency from the test bench. and after simulation is rerun. select File > Save Format.com 147 .Timing Simulation Using ModelSim R 1. In the Wave window. Measure CLKFX using the same steps as above. which in turn should be the DCM CLK0 output. Save Format Dialog Box After restarting the simulation. Saving the Simulation The ModelSim Simulator provides the capability of saving the signals list in the Wave window.xilinx. Select Add > Cursor twice to place two cursors on the wave view. you can select File > Load in the Wave window to reload this file. rename the filename from the default wave. Click Save. The measurement should read 38462 ps. Click and drag the first cursor to the rising edge transition on the CLK0 signal after the LOCKED signal has gone high. The measurement should read 20000 ps. 3. Save the signals list after new signals or stimuli are added.1 In-Depth Tutorial www. Figure 6-9: Find Next Transition Icon Look at the bottom of the waveform to view the distance between the two cursors. In the Save Format dialog box.

4. the default Simulation Model Properties are used. Figure 6-11: Simulation Properties 10. click the Help button. In the Sources tab. 8. click the Help button. These properties set the options that NetGen uses when generating the simulation netlist. Ensure that you have set the Property display level to Advanced. set the Simulation Run Time property to 2000 ns. Select Properties. Select the test bench file (stopwatch_tb). In the Processes tab. select Post-Route Simulation in the Sources for field. Select the ISE Simulator Properties category.” Specifying Simulation Process Properties To set the simulation process properties: 1. 9. click the + next to Xilinx ISE Simulator to expand the process hierarchy. 3. 148 www. The properties should appear as shown in Figure 6-11. “Timing Simulation Using ModelSim. 2. In the Simulation Properties tab.xilinx.1 In-Depth Tutorial . For this tutorial. For a description of each property.com ISE 9. Click OK to close the Process Properties dialog box. The Process Properties dialog box displays.R Chapter 6: Timing Simulation Timing Simulation Using Xilinx ISE Simulator Follow this section of the tutorial if you have skipped the previous section. For a description of each property. 5. Right-click Simulate Post-Place & Route Model. 7. Select the Simulation Model Properties category. This global setting enables you to now see all available properties. 6. These properties set the options the simulator uses to run the timing simulation.

2. Sim Hierarchy Window . The signal names and layout in the Sim Hierarchy window for a schematic or VHDL flow may appear different. The following procedure explains how to add additional signals in the design hierarchy. 1. 3. In the Sim Hierarchy window. Note: The majority of this design runs at 100 Hz and would take a significant amount of time to simulate. click the + next to uut to expand the hierarchy. and run the simulation for the time specified. This is why the counter will seem like it is not working in a short simulation. 4. Type the locked in the Find Signal dialog box and click on OK. only the DCM signals will be monitored to verify that they work correctly. double-click Simulate Post-Place and Route Model in the Processes tab. For the purpose of this tutorial. Right click in the Sim Hierarchy window and select Find. you must add them to the waveform window.VHDL Flow Click and drag LOCKED from the Sim Hierarchy window to the waveform window. The ISE Simulator will then compile the source files. Adding Signals To view signals during the simulation.Timing Simulation Using Xilinx ISE Simulator R Performing Simulation To start the timing simulation. In this tutorial. Select DCM_SP_INST/LOCKED signal and click on OK. Figure 6-12: 5. Figure 6-12 shows the Sim Hierarchy window for the VHDL flow. ISE 9. load the design.com 149 .xilinx.1 In-Depth Tutorial www. Project Navigator automatically runs NetGen to generate a timing simulation model from the placed and routed design. All available external (top-level ports) and internal signals are displayed in the Sim Hierarchy window. ISE automatically adds all the top-level ports to the waveform window. you will be adding the DCM signals to the waveform. When a simulation process is run.

xilinx. Viewing Full Signal Names A signal name may be viewed with either the complete hierarchical name or by the short name which omits hierarchy information. The ISE Simulator will only record data for the signals that have been added to the waveform window while the simulation is running. Therefore.R Chapter 6: Timing Simulation 6. Select Long Name or Short Name as desired. after new signals are added to the waveform window. 1. Right click the desired signal in the waveform window. Rerunning Simulation To restart and re-run the simulation: 150 www. Note: Stretch the first column in the waveform to see the signals clearly. you need to rerun the simulation for the desired amount of time. The waveform should appear as shown in Figure 6-13.com ISE 9. To change the signal name display. 2. This is because the ISE Simulator did not record the data for these signals.1 In-Depth Tutorial . Figure 6-13: The Resulting Waveform Notice that the waveforms have not been drawn for the newly added signals. Click and drag the following X_DCM_SP signals from the SIM Hierarchy window to the waveform window: ♦ ♦ ♦ ♦ RST CLKFX CLK0 CLKIN Note: Multiple signals can be selected by holding down the Ctrl key.

Figure 6-15: Entering the Run Command The simulation will run for 2000 ns. Two vertical markers are placed one the waveform. ISE 9.Timing Simulation Using Xilinx ISE Simulator R 1. Restart Simulation Icon At the Sim Console command prompt. 2. The waveforms for the DCM should now be visible in the Simulation window.com 151 . Click a rising edge transition on the CLK0 signal after the LOCKED signal has gone high. Right click the wave window and select Add Measure. Click and drag the second marker to the next rising edge on the CLK0 signal. Until the LOCKED signal is high the DCM outputs are not valid. The CLK0 needs to be 50 Mhz and the CLKFX should be ~26 Mhz. Click the Restart Simulation icon. 3. enter run 2000 ns and hit the Enter key. Figure 6-16: Adding Timing Markers Note: You may need to Zoom In to place the markers precisely on the clock edge. Figure 6-14: 2. Analyzing the Signals Now the DCM signals can be analyzed to verify that it does work as expected.1 In-Depth Tutorial www. The DCM signals should only be analyzed after the LOCKED signal has gone high. To measure the CLK0: 1. The cursor changes to an uparrow pointer.xilinx. ISE Simulator has the capability to add cursors to carefully measure the distance between signals.

This converts to 50 Mhz. The measurement should read 38.com ISE 9. Your timing simulation is complete and you are ready to program your device by following Chapter 7.1 In-Depth Tutorial .R Chapter 6: Timing Simulation View the time value between the two markers to see the distance between the two clock edges. “iMPACT Tutorial. Measure CLKFX using the same steps as above.0 ns.5 ns. which is the input frequency from the test bench. The measurement should read 20. this equals approximately 26 Mhz.” 152 www.xilinx. which in turn should be the DCM CLK0 output.

com 153 . and SVF/XSVF files.xilinx. System ACE files.1 In-Depth Tutorial www. iMPACT enables you to program through several parallel cables. • • • • • • • • Virtex™/-E/-II/-II PRO/4/5 Spartan™/-II/-IIE/XL/3/3E/3A XC4000™/E/L/EX/XL/XLA/XV CoolRunner™XPLA3/-II XC9500™/XL/XV XC18V00P XCF00S XCF00P ISE 9. The SVF/XSVF files can be played backed without having to recreate the chain. a file generation and device programming tool. This tutorial contains the following sections: • • • • • • • • • “Device Support” “Download Cable Support” “Configuration Mode Support” “Getting Started” “Creating a iMPACT New Project File” “Using Boundary Scan Configuration Mode” “Troubleshooting Boundary Scan Configuration” “Creating an SVF File” “Other Configuration Modes” Device Support The following devices are supported. PROM files. iMPACT can create bit files. including the Platform Cable USB.R Chapter 7 iMPACT Tutorial This chapter takes you on a tour of iMPACT.

com ISE 9.XCFP) Slave Serial—FPGAs (Virtex™/-II/-II PRO/E/4/5 and Spartan™/-II/-IIE/3/3E/3A) SelectMAP—FPGAs (Virtex™/-II/-II PRO/E/4/5 and Spartan™/-II/-IIE/3/3E/3A) Desktop —FPGAs (Virtex™/-II/-II PRO/E/4/5 and Spartan™/-II/-IIE/3/3E/3A) Getting Started Generating the Configuration Files In order to follow this chapter.R Chapter 7: iMPACT Tutorial Download Cable Support Parallel Cable IV The Parallel Cable connects to the parallel port and can be used to facilitate Slave Serial and Boundary-Scan functionality. and PROMs(18V00.xilinx. but that has mask data in place of configuration data.com/support. If a mask bit is 1. This file generated along with the BIT file.com/support. but is used for verification. and Boundary Scan functionality. go to http://www. you must have the following files for the stopwatch design: • • • a BIT file—a binary file that contains proprietary header information as well as configuration data. select Documentation > Data Sheets > Configuration Solutions > Configuration Hardware > Xilinx Parallel Cable IV. a MCS file—an ASCII file that contains PROM configuration information. CPLDs. For more information.xilinx. the bit should not be verified. select Documentation > Data Sheets > Configuration Solutions > Configuration Hardware > MultiPRO Desktop Tool. the bit should be verified against the bit stream data. Configuration Mode Support Impact currently supports the following configuration modes: • • • • Boundary Scan —FPGAs.xilinx. For more information. select Documentation > Data Sheets > Configuration Solutions > Configuration Hardware > Platform Cable USB. go to http://www. If a mask bit is 0. go to http://www. a MSK file—a binary file that contains the same configuration commands as a BIT file.com/support.XCFS. MultiPRO Cable The MultiPRO cable connects to the parallel port and can be used to facilitate Desktop Configuration Mode functionality. For more information. This data is not used to configure the device.1 In-Depth Tutorial . 154 www. Platform Cable USB The Platform Cable connects to the USB port and can be used to facilitate Slave Serial.xilinx.

or Linux — Type impact at a command prompt. Download the project files for either the VHDL. Be sure that the board is powered. Opening iMPACT from Project Navigator To start iMPACT from Project Navigator.xilinx. Starting the Software This section describes how to start the iMPACT software from ISE™ and how to run it stand-alone.htm. and connect the cable to the Spartan-3 Starter Kit demo board. Figure 7-1: Opening iMPACT from ISE Opening iMPACT stand-alone To open iMPACT without going through an ISE project. “Design Implementation.1 In-Depth Tutorial www.1i > Accessories > iMPACT.com 155 . Verilog or Schematic design flow. PC. UNIX. ISE 9. Connecting the Cable Prior to launching iMPACT.” • The Stopwatch tutorial projects can be downloaded from http://www.com/support/techsup/tutorials/tutorials9. double-click Configure Device (iMPACT) in the Processes tab in the Processes window (see Figure 7-1). use one of the following methods.xilinx. • • PC — Click Start > All Programs > Xilinx® ISE 9. connect the parallel side of the cable to your computer’s parallel port.Getting Started R These files are generated in Chapter 5.

You are prompted to define the project. however. and is discussed in a later section in this chapter. To perform operations.1 In-Depth Tutorial . Click the Browse button.ipf). 5. 4. In the iMPACT Project dialog box. 2. you will be using the Boundary Scan Configuration Mode. Click OK.R Chapter 7: iMPACT Tutorial Creating a iMPACT New Project File When iMPACT is initially opened. which enables you to then manually add devices to create chain. Figure 7-2: Creating an iMPACT Project To create a new project for this tutorial: 1. Boundary Scan Configuration Mode enables you to perform Boundary Scan Operations on any chain comprising JTAG compliant devices. you are prompted to specify the configuration mode and which device you would like to program. Note: The selection box also gives you the option to Enter a Boundary Scan Chain. the cable must be connected and the JTAG pins. as described in the next section. To select Boundary Scan Mode: 1. TMS. Automatically detecting and initializing the chain should be performed whenever possible. Using Boundary Scan Configuration Mode For this tutorial. Click Save. limited operations will be available for non-Xilinx devices.com ISE 9. and TDO need to be connected from the cable to the board. Specifying Boundary Scan Configuration Mode After opening iMPACT. 156 www. TCK. This option enables you to generate an SVF/XSVF programming file. select create a new project (.xilinx. the iMPACT Project dialog box displays. This creates a new project file in iMPACT. TDI. Select Configure Devices using Boundary-Scan (JTAG) and leave the selection box value of Automatically connect to a cable and identify Boundary-Scan chain. This dialog box enables you to load a recent project or to create a new project. The chain can consist of both Xilinx® and non-Xilinx devices. Browse to the project directory and then enter stopwatch in the File Name field. 3.

Note: If you were not prompted to select a configuration mode or automatic boundary scan mode. Figure 7-3: Selecting automatic boundary scan from Wizard iMPACT will pass data through the devices and automatically identify the size and composition of the boundary scan chain. Any supported Xilinx device will be recognized and labeled in iMPACT. Click Finish. right-click in the iMPACT window and select Initialize Chain.Using Boundary Scan Configuration Mode R 2. ISE 9.xilinx. The software will then highlight each device in the chain and prompt you to assign a configuration file or BSDL file.com 157 . Go to “Troubleshooting Boundary Scan Configuration” if you are having problems. Any other device will be labeled as unknown. The software will identify the chain if the connections to the board are working.1 In-Depth Tutorial www.

You should receive a warning stating that the startup clock has been changed to JtagClk.tek) is used to configure a PROM.mcs. a Boundary Scan Description File (BSDL or BSD) file can be applied instead.isc) is used to configure an FPGA. or . .com ISE 9.xilinx. A JEDEC file (*. A PROM file (*. The configuration file is used to program the device.R Chapter 7: iMPACT Tutorial Assigning Configuration Files After initializing a chain. select Bypass in the Assign New Configuration File dialog box. .isc) is used to configure a CPLD. Figure 7-4: Selecting a Configuration File Note: If a configuration file is not available. Click Open. The BSDL file provides the software with the necessary Boundary Scan information that allows a subset of the Boundary Scan Operations to be available for that device. 3.jed. To have ISE automatically select a BSDL file (for both Xilinx and non-Xilinx devices). *.rbt. Click OK. 158 www. Select the BIT file from your project working directory. 2.1 In-Depth Tutorial .exo. • • • A Bitstream file (*.hex.bit.*. When the software prompts you to select a configuration file for the first device (XC3S200): 1. *. the software prompts you for a configuration file (see Figure 7-4). There are several types of configuration files.

depending on your iMPACT Preferences setting.1 In-Depth Tutorial www.Using Boundary Scan Configuration Mode R 4. To restore the chain after reopening iMPACT. see “Editing Preferences. Figure 7-5: Edit Preferences Performing Boundary Scan Operations You can perform Boundary Scan operations on one device at a time. When the software prompts you to select a configuration file for the second device (XCF02S): Select the MCS file from your project working directory. select File > Open Project and browse to the IPF.”) ISE 9. you should save your iMPACT Project File (IPF) for later use. Note: Previous versions of ISE use Configuration Data Files (CDF). Editing Preferences To edit the preferences for the Boundary Scan Configuration. Saving the Project File Once the chain has been fully described and configuration files are assigned. right-click on any device in the chain. This selection opens the window shown in Figure 7-5. all other devices in the chain are automatically placed in BYPASS or HIGHZ. To see a list of the available options. 6. The Save As dialog box appears and you can browse and save your project file accordingly. The available Boundary Scan operations vary based on the device and the configuration file that was applied to the device. iMPACT Project Files can also be exported to a CDF.com 159 . Click Open. select File > Save Project As. When you select a device and perform an operation on that device. In this tutorial. To do this. keep the default values and click OK.xilinx. 5. This brings up a window with all of the available options. Click Help for a description of the Preferences. select Edit > Preferences. These files can still be opened and used in iMPACT. (For more information about Preferences.

Figure 7-6: Available Boundary Scan Operations for an XC3S200 Device The software accesses the IDCODE for this Spartan-3 device. 4.1 In-Depth Tutorial . The result is displayed in the log window (see Figure 7-7). Log Window Showing Result of Get Device ID Right-click on the XC3S200 device Select Program from the right-click menu. Figure 7-7: 3. Right-click on the XC3S200 device. Select Get Device ID from the right-click menu. In this section.xilinx. 160 www.R Chapter 7: iMPACT Tutorial To perform an operation.com ISE 9. 1. 2. right-click on a device and select one of the options. you will retrieve the device ID and run the programming option to verify the first device. The Program Options Dialog Box appears (see Figure 7-8).

Using Boundary Scan Configuration Mode

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5.

Select the Verify option. The Verify option enables the device to be readback and compared to the BIT file using the MSK file that was created earlier.

6.

Click OK to begin programming.

Figure 7-8:

Program Options for XC3S200 Device

Note: The options available in the Program Options dialog box vary based on the device you have selected. After clicking OK, the Program operation begins and an operation status window displays. At the same time, the log window reports all of the operations being performed.

Figure 7-9:

Operation Status

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When the Program operation completes, a large blue message appears showing that programming was successful (see Figure 7-10). This message disappears after a couple of seconds.

Figure 7-10:

Programming Operation Complete

Your design has been programmed and has been verified. The board should now be working and should allow you to start, stop and reset the runner’s stopwatch.

Troubleshooting Boundary Scan Configuration
Verifying Cable Connection
When an error occurs during a Boundary Scan operation, first verify that the cable connection is established and that the software autodetect function is working. If a connection is still not established after plugging the cable into the board and into your machine, right-click in a blank portion of the iMPACT window and select either Cable Auto Connect or Cable Setup. Cable Auto Connect will force the software to search every port for a connection. Cable Setup enables you to select the cable and the port to which the cable is connected.

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Troubleshooting Boundary Scan Configuration

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When a connection is found, the bottom of the iMPACT window will display the type of cable connected, the port attached to the cable, and the cable speed (see Figure 7-11).

Figure 7-11:

Cable Connection Successful

If a cable is connected to the system and the cable autodetection fails, refer to Xilinx Answer Record #15742. Go to http://www.xilinx.com/support and search for “15742”.

Verifying Chain Setup
When an error occurs during a Boundary Scan operation, verify that the chain is set up correctly and verify that the software can communicate with the devices. The easiest way to do this is to initialize the chain. To do so, right-click in the iMPACT window and select Initialize Chain. The software will identify the chain if the connections to the board are working. If the chain cannot be initialized, it is likely that the hardware is not set up correctly or the cable is not properly connected. If the chain can be initialized, try performing simple operations. For instance, try getting the Device ID of every device in the chain. If this can be done, then the hardware is set up correctly and the cable is properly connected. The debug chain can also be used to manually enter JTAG commands (see Figure 7-12). This can be used for testing commands and verifying that the chain is set up correctly. To use this feature, select Debug > Start/Stop Debug Chain in iMPACT.

Figure 7-12:

Debug Chain

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XSVF.mcs file to the chain.com ISE 9. skip to “Manual JTAG chain setup for SVF generation” to define the chain manually. The device is added where the large cursor is positioned. To add a device between existing devices. A cable normally does not need to be connected because no operations are being performed on devices.xilinx. Note: The boundary scan chain that you manually create in the software must match the chain on the board. All devices must be represented in the iMPACT window. Ensure that you are in Boundary Scan Mode (click the Boundary-Scan tab). The Boundary-Scan chain can be manually created or modified as well. you may need to set up your Boundary Scan chain manually and then create a device programming file. 3. You can now add one device at a time.R Chapter 7: iMPACT Tutorial For help using iMPACT Boundary-Scan Debug. Repeat steps 2 and 3 to add the stopwatch.svf file. 1.xilinx. or file a Web case at http://www. 3.1 In-Depth Tutorial . An Add Device dialog box appears allowing you to select a configuration file. To do this. Right-click on an empty space in the iMPACT Boundary-Scan window and select Add Xilinx Device or Add Non-Xilinx device. Select Output > SVF File > Create SVF File to indicate that you are creating a programming file. 2. and they are used by ATE machines and embedded controllers to perform Boundary Scan operations. SVF. These programming files contain both programming instructions and configuration data. Creating an SVF File This section is optional and assumes that you have followed the “Using Boundary Scan Configuration Mode” section and have successfully programmed to a board. Click OK. Enter getid in the File Name field of the Create a New SVF File dialog box and click Save. even if you intend to program only some of the devices. all of the configuration information is written to the SVF file. click on the line between them and then add the new device. 164 www. If you are using third-party programming solutions. Manual JTAG chain setup for SVF generation For this tutorial.bit and then click Open.com/support.” section. An informational message appears stating that all device operations will be directed to the . Setting up Boundary Scan Chain This section assumes that you are continuing from the previous sections of this chapter and already have the chain detected. you may skip this section if you completed the “Using Boundary Scan Configuration Mode. If not. JTAG chain setup for SVF generation 1. 2. iMPACT supports the creation of device programming files in three formats. Select stopwatch. use the iMPACT Help (accessible from Help > Help Topics). In this section. and STAPL.

Select Get Device ID from the right-click menu. select View > View SVF-STAPL File. 2.com 165 . Figure 7-14: SVF File that Gets a Device ID from the First Device in the Chain ISE 9.1 In-Depth Tutorial www. Figure 7-13: Selecting a Boundary Scan Operation The instructions that are necessary to perform a Get Device ID operation are then written to the file. You simply right-click on a device and select an operation. Right-click the first device (XC3S200). you will be writing the device ID to the programming file for the first device.xilinx.Creating an SVF File R Writing to the SVF File The process of writing to an SVF file is identical to performing Boundary Scan operations with a cable. 3. and performing further instructions for the second device. To see the results. To write the device ID: 1. Any number of operations can be written to an SVF file. In this section. Figure 7-14 shows what the SVF file looks like after the Get Device ID operation is performed.

you can select Output > SVF File > Append to SVF File. Select Program from the right-click menu. Playing back the SVF or XSVF file To play back the SVF file that you created to verify the instructions.R Chapter 7: iMPACT Tutorial To write further instructions to the SVF for the second device: 1. 166 www. Available Boundary Scan Operations for a XCF02S Device Click OK in the Programming Properties window.1 In-Depth Tutorial . To stop writing to the programming file: Select Output > SVF File > Stop Writing to SVF File. Right-click the second device (XCF02S). The instructions and configuration data needed to program the second device are added to the SVF file. Figure 7-15: 3.com ISE 9. To use the Slave Serial Configuration Mode. Assign the SVF file to the chain by right clicking and selecting Add Xilinx Device and selecting the SVF file in the search window. double-click Slave Serial in the Configuration Modes tab. select the SVF file and click Save. you will • • • Manually create a new chain. 2. Stop Writing to the SVF After all the desired operations have been performed.. you must add an instruction to close the file from further instructions. Right-click on the SVF file in the Boundary-Scan chain and select Execute XSVF/SVF.xilinx. Other Configuration Modes Slave Serial Configuration Mode Slave Serial Configuration mode allows you to program a single Xilinx device or a serial chain of Xilinx devices. To add other operations in the future.

1 In-Depth Tutorial www. The devices are programmed one at a time and are selected by the assertion of the correct CS pin. Only the MultiPRO cable can be used for SelectMAP Configuration.Other Configuration Modes R SelectMAP Configuration Mode With iMPACT. Note: These modes cannot be used with the Spartan-3 Starter Kit. To use the SelectMAP Configuration Mode. double click SelectMAP in the Configuration Modes tab. ISE 9.com 167 . SelectMAP Configuration mode allows you to program up to three Xilinx devices.xilinx.

com ISE 9.1 In-Depth Tutorial .xilinx.R Chapter 7: iMPACT Tutorial 168 www.

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