ISE In-Depth Tutorial

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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring failsafe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. Copyright © 1995-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.

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Preface

About This Tutorial
About the In-Depth Tutorial
This tutorial gives a description of the features and additions to Xilinx® ISE™ 9.1i. The primary focus of this tutorial is to show the relationship among the design entry tools, Xilinx and third-party tools, and the design implementation tools. This guide is a learning tool for designers who are unfamiliar with the features of the ISE software or those wanting to refresh their skills and knowledge. You may choose to follow one of the three tutorial flows available in this document. For information about the tutorial flows, see “Tutorial Flows.”

Tutorial Contents
This guide covers the following topics. • • • Chapter 1, “Overview of ISE and Synthesis Tools,” introduces you to the ISE primary user interface, Project Navigator, and the synthesis tools available for your design. Chapter 2, “HDL-Based Design,” guides you through a typical HDL-based design procedure using a design of a runner’s stopwatch. Chapter 3, “Schematic-Based Design,” explains many different facets of a schematicbased ISE design flow using a design of a runner’s stopwatch. This chapter also shows how to use ISE accessories such as StateCAD, CORE Generator™, and ISE Text Editor. Chapter 4, “Behavioral Simulation,” explains how to simulate a design before design implementation to verify that the logic that you have created is correct. Chapter 5, “Design Implementation,” describes how to Translate, Map, Place, Route (Fit for CPLDs), and generate a Bit file for designs. Chapter 6, “Timing Simulation,” explains how to perform a timing simulation using the block and routing delay information from the routed design to give an accurate assessment of the behavior of the circuit under worst-case conditions. Chapter 7, “iMPACT Tutorial” explains how to program a device with a newly created design using the IMPACT configuration tool.

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“iMPACT Tutorial” • 4 www. it is strongly recommended in this tutorial flow. the three tutorial flows are outlined and briefly described. Chapter 7. “Behavioral Simulation” Note that although behavioral simulation is optional. “iMPACT Tutorial” • • • Implementation-only Flow The Implementation-only flow is as follows: • • Chapter 5. “Design Implementation” Chapter 6.1 In-Depth Tutorial . “Schematic-Based Design” Chapter 4. Chapter 7. Chapter 5. in order to help you determine which sequence of chapters applies to your needs. Chapter 7. “HDL-Based Design” Chapter 4. In this section.com ISE 9. “Timing Simulation” Note that although timing simulation is optional.xilinx. it is strongly recommended in this tutorial flow. it is strongly recommended in this tutorial flow. “Design Implementation” Chapter 6. The tutorial flows include: • • • HDL Design Flow Schematic Design Flow Implementation-only Flow HDL Design Flow The HDL Design flow is as follows: • • Chapter 2. Chapter 5. it is strongly recommended in this tutorial flow. “iMPACT Tutorial” • • • Schematic Design Flow The Schematic Design flow is as follows: • • Chapter 3.“Timing Simulation” Note that although timing simulation is optional. “Behavioral Simulation” Note that although behavioral simulation is optional. “Timing Simulation” Note that although timing simulation is optional. it is strongly recommended. “Design Implementation” Chapter 6.R Preface: About This Tutorial Tutorial Flows This document contains three tutorial flows.

com/support.Additional Resources R Additional Resources To find additional documentation. or to create a technical support WebCase.xilinx.com 5 . see the Xilinx website at: http://www. ISE 9. To search the Answer Database of silicon. software.1 In-Depth Tutorial www. and IP questions and answers. see the Xilinx website at: http://www.xilinx.com/literature.xilinx.

R Preface: About This Tutorial 6 www.xilinx.com ISE 9.1 In-Depth Tutorial .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Navigation to Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 HDL Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processes Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Schematic Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Properties . . . . . . . . . . . . . Processes Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an Archive . . . . . . . . . . . . . . . . . 19 ISE 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Workspace . . . . . . . . . . . 4 Implementation-only Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exporting a Project . . . . . . . . . . . . . . . . . . . . . . . Sources Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Snapshots Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Navigation to Answer Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing a Snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sources Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Project Archives . . . . . . . . Restoring a Snapshot . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 14 15 15 15 15 16 16 16 17 17 17 17 17 17 17 17 18 18 18 18 18 18 19 19 19 20 20 20 20 Using Revision Control Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transcript Window . . . . . . .1 In-Depth Tutorial www. . . . . . . . . . . . . . . . . Using Snapshots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Tutorial Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Tutorial Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precision Synthesis. . . . . . . . . . . . . . . Design Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Synthesis Technology (XST) . . . . Restoring an Archive . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Export/Import Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Libraries Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synplify/Synplify Pro . . . . . . . . . . . . . . . . . . . . . . . 17 Overview of Synthesis Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic Editor . . . . . . . . . . . . . . . . . . . . . . . . .xilinx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .com 1-800-255-7778 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Project Navigator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Importing a Project . . . . . . . . . . . . . . .Table of Contents Preface: About This Tutorial About the In-Depth Tutorial . . 4 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chapter 1: Overview of ISE and Synthesis Tools Overview of ISE . . . . . . . . . . . . . . . . . . . . . . . . . ISE Simulator / Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Text Editor . . . . . . . . . . . . . .

. . . . . . Entering Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stopping the Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The RTL / Technology Viewer . . . . . . . . . . . . . . . . . . . . . Entering Synthesis Options . . . . Creating a DCM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .com 1-800-255-7778 ISE 9.1 In-Depth Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 31 32 32 34 35 36 36 38 39 39 41 42 44 44 45 45 45 47 47 48 49 49 Synthesizing the Design . . . . . . . . . . . . . . . . . Creating a New Project: Using the New Project Wizard .Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 24 24 25 25 25 27 27 Design Description . . . . . . . . . . . . . . . . . . 29 Adding Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an HDL-Based Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VHDL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Language Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Chapter 3: Schematic-Based Design Overview of Schematic-Based Design . . 28 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . .R Chapter 2: HDL-Based Design Overview of HDL-Based Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a New Project: Using New Project Wizard . . . 51 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizing the Design . . . . . . . . . . . . . . . . . . . Creating a New Project . . . . . . . . . . . . . Installing the Tutorial Project Files . . . . . . . . . . . . . 28 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The RTL/Technology Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Starting the ISE Software . . . . . . Starting the ISE Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Correcting HDL Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a CORE Generator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizing the Design using XST . . . . . . . . . . . . . . . Optional Software Requirements . . . . . . . . . . . . . . Using the Clocking Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instantiating the dcm1 Macro . . . . . . . . . . . . . . . . . 51 Required Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a New Project . . . Creating a New Project: Using a Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instantiating the CORE Generator Module in the HDL Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering Synthesis Options through ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding a Language Template to Your File . . . . . . . . Creating a CORE Generator Module . . . . . . . . . . Checking the Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Required Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL or Verilog? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizing the Design Using Precision Synthesis . . . . Using the New Source Wizard and ISE Text Editor . . . . . . . . . . . . . . . . . . . Installing the Tutorial Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examining Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizing the Design using Synplify/Synplify Pro . . . . . . . . . . . . . . . . . 23 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xilinx. . . . . 28 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instantiating the dcm1 Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Inputs . . . . 51 52 52 52 53 8 www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating the State Machine HDL output file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving the Schematic . . . . . . . . . . . . . . . . 57 Opening the Schematic File in the Xilinx Schematic Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Completing the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Schematic-Based Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dcm1 and debounce Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Device Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Inputs . . . . 54 Stopping the Tutorial . . . . . . . . . . . . . . Creating the debounce Symbol . . . . . . . . . . . 56 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the New Source Wizard and ISE Text Editor . . . . . . . Creating a DCM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . Changing Instance Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hierarchy Push/Pop . . . . . . . . . . . . . . . Adding I/O Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a CORE Generator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Language Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating the time_cnt symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manipulating the Window View . . . . . . . . . . . . . . Adding Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding New States . . . . . . . . . . . .1 In-Depth Tutorial www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating the dcm1 Symbol . . . . . . . . . . . . . . . . . timer_preset. . . . . . Placing the time_cnt Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Bus Taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 58 58 59 60 60 63 63 63 64 65 66 67 67 67 67 68 68 70 71 72 73 75 75 76 76 76 78 79 79 81 82 83 83 84 85 85 85 86 87 87 Chapter 4: Behavioral Simulation Overview of Behavioral Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Functional Blocks . . . . . . . . . . . . . . . Adding a State Action . . . . . . . . . . . . . . . . . . . .R Creating a New Project: Using a Tcl Script . . . . . . . . . . . . Adding a State Machine Reset Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ModelSim Setup . . . . . . . . . . . . . . . . . Adding Schematic Components . . .xilinx. . . 55 Outputs . . . . . . . . . . . . . Defining the time_cnt Schematic . . . . . . . . Creating the State Machine Symbol . . . . . . .com 1-800-255-7778 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding a Language Template to Your File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Clocking Wizard . . . Adding Net Names . . . . . . . . . Creating an HDL-Based Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a State Machine Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding I/O Markers and Net Names. . . . . . . . . . . . . . . . . . . . Adding a Transition . . . . . . . . . . . . . . . . . . . . . . Placing the statmach. . . Assigning Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ISE 9. . . Correcting Mistakes . . . . . . . . . . Drawing Wires . . . . . . . . . . . . . . . . . Creating a CORE Generator Module . . . . . . . . . . . . . . . . . . . . . . . . . Adding Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating and Placing the time_cnt Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .com 1-800-255-7778 ISE 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Translating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Simulation Libraries . . . . . . . . Mapping the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applying Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 113 114 115 116 120 123 126 Estimating Timing Goals with the 50/50 Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Locating the Simulation Processes . . . . . . . . . . . . . . . . . 110 Specifying Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 In-Depth Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Adding Signals . . . . . . . . . . . . Xilinx Simulation Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Starting from Design Implementation . . . . . . . . . . . . . . Using the Constraints Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rerunning Simulation . Analyzing the Signals . . . . 95 Behavioral Simulation Using ModelSim . . . . . . . . . . . . . . . . . . . . . 101 Behavioral Simulation Using ISE Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10 www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Locating the Simulation Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Test Bench Waveform Using the Waveform Editor . . . Verilog. . . . . . . . . . . . . . . . . . 94 VHDL Simulation . . . . . . . . . . . . . . Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Saving the Simulation . . . . . . . . . . . . . . Design Files (VHDL. . . . . . . . . . . 92 ISE Simulator Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Adding Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .R ModelSim PE and SE . . . . . . . . . . . . . . . . . . . . Creating a Test Bench Waveform Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Simulation Properties . . . . . . or Schematic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Verilog Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Specifying Simulation Properties . . . . . . . . . . . . Using Timing Analysis to Evaluate Block Delays After Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Floorplan Editor . . 91 ModelSim Xilinx Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Signals . . 92 Required Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xilinx. . . . . . . . . . . . . . . 109 Getting Started . . . . . . . . . . . . Creating Partitions . . . . . . . . . . . . . . . . . . . . . . 110 Continuing from Design Entry . . . . . .ini File . . . . . . . . . . . . . . . . . . . . . . 92 Getting Started . . . . . . . . . . . . . . 99 Rerunning Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mapping Simulation Libraries in the Modelsim. . . . . . . . Updating the Xilinx Simulation Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 102 103 103 104 105 105 105 107 Chapter 5: Design Implementation Overview of Design Implementation . Test Bench File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Adding Tutorial Test Bench File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 92 92 92 93 93 93 Adding an HDL Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . .R Report Paths in Timing Constraints Option . . . . . . . . . . . . . . . 140 Specifying a Simulator . Saving the Simulation . . . . . 154 Parallel Cable IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 129 131 132 134 135 138 Chapter 6: Timing Simulation Overview of Timing Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Signals . . . . . . . . . . . . . . . . . . . . . .1 In-Depth Tutorial www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Full Signal Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 MultiPRO Cable . . . . . . . . . . . . . . . . . . . . . . . 140 Timing Simulation Using ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Configuration Mode Support . . . . . . . . . . . . . . . . . . . . . . . 154 Platform Cable USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rerunning Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 ISE 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rerunning Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Evaluating Post-Layout Timing . . . Connecting the Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using FPGA Editor to Verify the Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Simulation . . . . Opening iMPACT stand-alone . . . . . . .com 1-800-255-7778 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Placing and Routing the Design . . Creating Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a PROM File with iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Generating the Configuration Files . . . . . . . . . . . . . . . 154 Getting Started . . . . . . . . . . . . . . . . . . . 148 Chapter 7: iMPACT Tutorial Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 143 143 145 146 146 147 148 149 149 150 150 151 Timing Simulation Using Xilinx ISE Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Specifying Boundary Scan Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . Starting the Software . . . . . . . 139 Required Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Specifying Simulation Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Download Cable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Required Files . . . . . . . . . . . . . Opening iMPACT from Project Navigator . . . . . . . . . . . . . 154 155 155 155 155 Creating a iMPACT New Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changing HDL with Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Assigning Configuration Files . . . . . . . . . . . . . . . . . . . . . . Specifying Simulation Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xilinx. . . . . . . . . . . . . . . . . . . . . . . . . 156 Using Boundary Scan Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writing to the SVF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12 www. .1 In-Depth Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Performing Boundary Scan Operations . . . . . . . . . . . . . . . . . .R Saving the Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Verifying Chain Setup . . . . . . . . . . .com 1-800-255-7778 ISE 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 SelectMAP Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Verifying Cable Connection . . . . . . . . Playing back the SVF or XSVF file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Writing to the SVF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Setting up Boundary Scan Chain . . . . . . . . . . . . . . . . . . . . . . . Manual JTAG chain setup for SVF generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Troubleshooting Boundary Scan Configuration . . . . . . . . . . . . 163 Creating an SVF File . . . . . . . . . . . . . . . . .xilinx. . . . . . . . . . . . JTAG chain setup for SVF generation . . . . 164 164 164 165 166 166 Other Configuration Modes . . . . . . . . . . . . . . . 166 Slave Serial Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Editing Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

undocked from Project Navigator or moved to a new location within the main Project Navigator window. ISE 9. Each window may be resized. You can also access the files and documents associated with your project. as seen in Figure 1-1.xilinx. and simulation waveforms.1 In-Depth Tutorial www. ASCII text files. and warnings and also contains interactive tabs for Tcl scripting and the Find in Files function. On the top left is the Sources window which hierarchically displays the elements included in the project. The fourth window to the right is a multi-document interface (MDI) window refered to as the Workspace. you can access all of the design entry and design implementation tools.R Chapter 1 Overview of ISE and Synthesis Tools This chapter includes the following sections: • • • “Overview of ISE” “Using Revision Control Features” “Overview of Synthesis Tools” Overview of ISE ISE controls all aspects of the design flow. schematics. Beneath the Sources window is the Processes window. It enables you to view html reports. The third window at the bottom of the Project Navigator is the Transcript window which displays status messages. The default layout can always be restored by selecting View > Restore Default Layout. which displays available processes for the currently selected source. These windows are discussed in more detail in the following sections.com 13 . Through the Project Navigator interface. errors. Project Navigator Interface The Project Navigator Interface is divided into four main subwindows.

com ISE 9. 14 www.1 In-Depth Tutorial . the specified device. “Design Implementation”. Sources Tab The Sources tab displays the project name. such as Synthesis/Implementation. and user documents and design source files associated with the selected Design View.xilinx. a Resources column and a Preserve Column are available for Designs that use Partitions. In the “Number of” drop-down list.R Chapter 1: Overview of ISE and Synthesis Tools Figure 1-1: Project Navigator Sources Window This window consists of three tabs which provide project and file information for the user. The Design View (“Sources for”) drop-down list at the top of the Sources tab allows you to view only those source files associated with the selected Design View. Each tab is discussed in further detail below. The use of partitions is covered in Chapter 5.

Snapshots Tab The Snapshots tab displays all snapshots associated with the project currently open in Project Navigator. and source files for all snapshots. select the Index tab and search for “Source file types. Synthesis. Available processes vary depending on the synthesis tools you use. You can expand the hierarchy by clicking the +. and the snapshot can be viewed in the Snapshots tab. All information displayed in the Snapshots tab is read-only. and synthesis reports. The icon indicates the file type (HDL file. You can open a file for editing by double-clicking on the filename. core. You can view the reports. Libraries Tab The Libraries tab displays all libraries associated with the project open in Project Navigator. user documents. and simulation library compilation. ISE 9. • • User Constraints Provides access to editing location and timing constraints.Overview of ISE R Each file in a Design View has an associated icon.xilinx. and synthesis and simulation sub-directories. instantiation templates. A snapshot is a copy of the project including all files in the working directory. see the ISE™ Help. schematic. The Processes tab provides access to the following functions: • • • • Add an Existing Source Create New Source View Design Summary Design Utilities Provides access to symbol generation. From the Processes tab. for example).” If a file contains lower levels of hierarchy.1 In-Depth Tutorial www. Processes Window This window contains one default tab called the Processes tab. you can run the functions necessary to define. For a complete list of possible source types and their associated icons. run and view your design. View RTL or Technology Schematic.com 15 . or text file. HDL files have this + to show the entities (VHDL) or modules (Verilog) within the file. Using snapshots provides an excellent version control system. A snapshot is stored with the project for which it was taken. Select Help > ISE Help Contents. viewing command line history. the icon has a + to the left of the name. Synthesis Provides access to Check Syntax. Processes Tab The Processes tab is context sensitive and it changes based upon the source type selected in the Sources tab and the Top-Level Source in your project. enabling subteams to do simultaneous development on the same design.

Generate Programming File Provides access to configuration tools and bitstream generation. the Tcl Shell allows a user to enter Project Navigator specific Tcl commands. • Console Displays errors. 16 www. right-click the mouse. and select Go to Answer Record from the right-click menu. warnings. when you run the Implement Design process. The Processes tab incorporates automake technology. design flow reports. expand Design Utilities and select View Command Line Log File. This enables the user to select any process in the flow and the software automatically runs the processes necessary to get to the desired step.R Chapter 1: Overview of ISE and Synthesis Tools • • Implement Design Provides access to implementation tools. Transcript Window The Transcript window contains five default tabs: Console. For more information on Tcl commands. Tcl Shell. Errors Displays only error messages. Warnings. select the error or warning message. For example.xilinx. • • • Warnings Displays only warning messages. • Find in Files Displays the results of the Edit > Find in Files function.xilinx. “Design Implementation” for further details. Errors are signified by a red (X) next to the message. Project Navigator also runs the Synthesis process because implementation is dependent on up-todate synthesis results. Errors. Other console messages are filtered out.1 In-Depth Tutorial . select the error or warning message.com ISE 9.com/support website. and information messages.The HDL source file opens and the cursor moves to the line with the error. To navigate to the Answer Record(s). warnings and informational messages. and select Go to Source from the right-click menu. Find in Files. see the ISE Help. right-click the mouse. The default web browser opens and displays all Answer Records applicable to this message. Other console messages are filtered out. Error Navigation to Source You can navigate from a synthesis error or warning message in the Transcript window to the location of the error in a source HDL file. Error Navigation to Answer Record You can navigate from an error or warning message in the Transcript window to relevant Answer Records on the www. and point tools. To do so. Note: To view a running log of command line arguments used on the current project. In addition to displaying errors. See the Command Line Implementation section of Chapter 5. while warnings have a yellow exclamation mark (!). Tcl Shell Is a user interactive console.

The editor is determined by the setting found by selecting Edit > Preferences. Using Revision Control Features Using Snapshots Snapshots enable you to maintain revision control over the design.1 In-Depth Tutorial www. refer to“Creating a Test Bench Waveform Using the Waveform Editor” in Chapter 4. Text Editor Source files and other text documents can be opened in a user designated editor. 2. then generate a VHDL test bench or Verilog test fixture. expand ISE General and click Editors. which is a catalog of ABEL. it replaces the project in your current session. Schematic Editor The Schematic Editor is integrated in the Project Navigator framework. See also “Snapshots Tab.xilinx. In the Take a Snapshot of the Project dialog box. ISE Text Editor enables you to edit source files and user documents. performance data gathered from the Place & Route (PAR) report. The Schematic Editor can be used to graphically create and view logical designs. VHDL. a device utilization summary. Tcl and User Constraints File templates that you can use and modify in your own design. including overview information. The snapshot containing all of the files in the project directory along with project settings is displayed in the Snapshots tab.com 17 . and summary information from all reports with links to the individual reports. Restoring a Snapshot Since snapshots are read-only. ISE 9. Select Project > Take Snapshot. For details. A snapshot contains a copy of all of the files in the project directory.Using Revision Control Features R Workspace Design Summary The Design Summary lists high-level information about your project. When you restore a snapshot. constraints information.” Creating a Snapshot To create a snapshot: 1. a snapshot must be restored in order to continue work. You can access the Language Templates. ISE Simulator / Waveform Editor ISE Simulator / Waveform Editor can be used to create and simulate test bench and test fixture within the Project Navigator framework. enter the snapshot name and any comments associated with the snapshot. Waveform Editor can be used to graphically enter stimuli and the expected response. Verilog. The default editor is the ISE Text Editor.

To review a process report or verify process status within a snapshot: 1.R Chapter 1: Overview of ISE and Synthesis Tools To restore a snapshot: 1. Expand the snapshot source tree and select the desired source file. In the Snapshots tab. 2. These files will need to be manually copied to the original location or added to the project again in a new directory Viewing a Snapshot The Snapshots tab contains a list of all the snapshots available in the current project. select the snapshot from the drop-down list. 2.com ISE 9. 2. Before the snapshot replaces the current project. For more information.1 In-Depth Tutorial .” The Export/Import processes are typically used in conjunction with a 3rd party source control system but can be used independently as a valid means of backing up a design. Using Export/Import Source Control You can use this feature to export to and retrieve project files and sources from a “staging area. Select Project > Archive. Restoring an Archive You cannot restore an archived file directly into Project Navigator. Exporting a Project To export a project 1. 3. Note: The archive contains all of the files in the project directory along with project settings. The compressed file can be extracted with any ZIP utility and you can then open the extracted file in Project Navigator. select Open Without Updating. From the menu.xilinx. Select Project > Source Contorl > Export 18 www. Creating an Archive To create an archive: 1. see the ISE Help. Right-click the mouse over the desired process report. In the Create Zip Archive dialog box. you are given the option to place the current project in a snapshot so that your work is not lost. Note: Remote sources are copied with the snapshot and placed in a subdirectory named remote_sources. This allows for easier transfer over email and storage of numerous projects in a limited space. Select Project > Make Snapshot Current. Remote sources are included in the archive under a folder named remote_sources . Using Project Archives You can also archive the entire project into a single compressed file. enter the archive name and location.

Overview of Synthesis Tools

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Follow the Export Project Wizard to dertermine which files to export, where to export the files to, and optionally create a Tcl script that can be used to regenerate the ISE project.

Importing a Project
To import a project 1. 2. Select Project > Source Contorl > Import Select the Project File (.ise or Tcl import script) and directory location to import the project file and sources.

Overview of Synthesis Tools
You can synthesize your design using various synthesis tools. The following section lists the supported synthesis tools and includes some process properties information.

Precision Synthesis
This synthesis tool is not part of the ISE package and is not available unless purchased separately. Two commonly used properties are Optimization Goal and Optimization Effort. With these properties you can control the synthesis results for area or speed and the amount of time the synthesizer runs.This synthesis tool is available for both an HDL- and Schematic-based design flow.

Process Properties
Process properties enable you to control the synthesis results of Precision. Most of the commonly used synthesis options available for the Precision stand-alone version are available for Precision synthesis through ISE. For more information, see the Precision online help.

Figure 1-2:

Precision Synthesis Process Properties

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Synplify/Synplify Pro
This synthesis tool is not part of the ISE package and is not available unless purchased separately. This synthesis tool is available for HDL-based designs, but it is not available for a schematic-based design.

Process Properties
Process properties enable you to control the synthesis results of Synplify/Synplify Pro. Most of the commonly used synthesis options available in the Synplify/Synplify Pro stand-alone version are available for Synplify/Synplify Pro synthesis through ISE. For more information, see the Synplify/Synplify Pro online help.

Figure 1-3:

Synplify/Synplify Pro Synthesis Process Properties

Xilinx Synthesis Technology (XST)
This synthesis tool is part of the ISE package and is available for both an HDL- and Schematic-based design flow.

Process Properties
Process properties enable you to control the synthesis results of XST. Two commonly used properties are Optimization Goal and Optimization Effort. With these properties you can control the synthesis results for area or speed, and the amount of time the synthesizer runs. More detailed information is available in the XST User Guide, available in the collection of software manuals. From ISE, select Help > Software Manuals, or go on the web at http://www.xilinx.com/support/sw_manuals/xilinx9/.

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Figure 1-4:

XST Synthesis Process Properties

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and design flow practices you can apply to your own design. unless otherwise noted. software features. The design example used in this tutorial demonstrates many device features. Synplify/Synplify Pro. and configure and download to the Spartan-3A demo board (Chapter 7. or Precision.R Chapter 2 HDL-Based Design This chapter includes the following sections: • • • • • “Overview of HDL-Based Design” “Getting Started” “Design Description” “Design Entry” “Synthesizing the Design” Overview of HDL-Based Design This chapter guides you through a typical HDL-based design procedure using a design of a runner’s stopwatch. ISE 9. all of the principles and flows taught are applicable to any Xilinx® device family. This design targets a Spartan™-3A device. perform timing simulation (Chapter 6. however.xilinx.” After the design is successfully defined. “Behavioral Simulation”). The design is composed of HDL elements and two cores. You can synthesize the design using Xilinx Synthesis Technology (XST). “iMPACT Tutorial”). “Timing Simulation”).com 23 . “Design Implementation”). run implementation with the Xilinx Implementation Tools (Chapter 5. you will perform behavioral simulation (Chapter 4.1 In-Depth Tutorial www. This chapter is the first chapter in the “HDL Design Flow.

8. XST can synthesize a mixed-language design. This tutorial assumes that the software is installed in the default location c:\xilinx91i. Optional Software Requirements The following third-party synthesis tools are incorporated into this tutorial. You will need to decide which HDL language you would like to work through for the tutorial. 24 www.htm.R Chapter 2: HDL-Based Design Getting Started The following sections describe the basic requirements for running the tutorial. However.com/support/techsup/tutorials/tutorials9. refer to the ISE Release Notes and Installation Guide. and applies to both designs simultaneously. substitute your installation path for c:\xilinx91i in the procedures that follow. and may be used in place of the Xilinx Synthesis Tool (XST): • • Synplicity Synplify/Synplify PRO 8.1 In-Depth Tutorial .xilinx. Download either the VHDL or the Verilog design flow project files. Required Software To perform this tutorial. you must have the following software and software components installed: • • Xilinx Series ISE™ 9. the directory wtut_vhd (for a VHDL design flow) or wtut_ver (for a Verilog design flow) is created within c:\xilinx\ISEexamples.1i Spartan-3A libraries and device files Note: For detailed software installation instructions.com ISE 9.xilinx. When you unzip the tutorial project files into c:\xilinx\ISEexamples. and the tutorial files are copied into the newlycreated directory. and download the appropriate files for that language. After you have downloaded the tutorial project files from the Web.7 (or above) The following third-party simulation tool is optional for this tutorial. noting differences where applicable. this tutorial does not go over the mixed language feature. Installing the Tutorial Project Files The Stopwatch tutorial projects can be downloaded from http://www. If you have installed the software in a different location. replacing any existing files in that directory. and may be used in place of the ISE Simulator: • ModelSim VHDL or Verilog? This tutorial supports both VHDL and Verilog designs. unzip the tutorial projects into the c:\xilinx\ISEexamples directory.02 (or above) Mentor Precision Synthesis 2006a2.

If you unzip the files into a different location.Getting Started R The following table lists the locations of tutorial source files. Starting the ISE Software To start ISE: Double-click the ISE Project Navigator icon on your desktop or select Start > All Programs > Xilinx ISE 9. From Project Navigator. select File > New Project. The New Project Wizard appears.1 In-Depth Tutorial www. Figure 2-1: Project Navigator Desktop Icon Creating a New Project Note: Two methods are provided for creating a new project: Using the New Project Wizard and Using a Tcl Script. The completed directories contain the finished HDL source files. Table 2-1: Tutorial Directories Directory wtut_vhd wtut_ver wtut_vhd\wtut_vhd_comple ted wtut_ver\wtut_ver_comple ted Description Incomplete VHDL Source Files Incomplete Verilog Source Files Completed VHDL Source Files Completed Verilog Source Files Note: Do not overwrite any files in the solution directories.1i > Project Navigator. Creating a New Project: Using the New Project Wizard 1. ISE 9. Use either method provided below. but you can unzip the source files into any directory with read-write permissions.xilinx. This tutorial assumes that the files are unzipped under c:\xilinx\ISEexamples. substitute your project path for c:\xilinx\ISEexamples in the procedures that follow.com 25 .

Create New Project 2. Verify that HDL is selected as the Top-Level Source Type and click Next. The New Project Wizard . 3. Type wtut_vhd or wtut_ver in the Project Name field.com ISE 9.xilinx.Device Properties 26 www.1 In-Depth Tutorial . In the Project Location field.Device Properties window appears. Figure 2-3: New Project Wizard . browse to c:\xilinx\ISEexamples or to the directory in which you installed the project. 4.R Chapter 2: HDL-Based Design Figure 2-2: New Project Wizard .

2.1 In-Depth Tutorial www.tcl (Verilog design entry). Change the Preferred Language: to VHDL. right-click on the device line and select Properties. Change the current working directory to the directory where the tutorial source files were unzipped by typing cd c:/xilinx/ISEexamples/wtut_vhd (VHDL design entry) or cd c:/xilinx/ISEexamples/wtut_ver (Verilog design entry). 4. This will determine the default language for all processes that generate HDL files..com 27 . With Project Navigator open. then Finish to complete the New Project Wizard.. 8. then click OK. In the Adding Source Files dialog box. 10. This will determine the default language for all processes that generate HDL files. 7. Run the project creation Tcl script by typing source create_wtut_vhd. Creating a New Project: Using a Tcl Script 1. ♦ ♦ ♦ ♦ clk_div_262k lcd_control statmach stopwatch 9. Browse to c:\xilinx\ISEexamples\wtut_vhd or c:\xilinx\ISEexamples\wtut_ver.Add Existing Sources window. then Next.tcl (VHDL design entry) or source create_wtut_ver. select the Tcl Shell tab. and then click Add Source in the New Project Wizard . Click Next.v files for Verilog design entry) and click Open. Stopping the Tutorial You may stop the tutorial at any time and save your work by selecting File > Save All. (VHDL only) Once the project is created and opened. 3.vhd files for VHDL design entry or . 6.Getting Started R 5. Select the following files (.xilinx. verify that all added HDL files are associated with Synthesis/Imp + Simulation. Click Next.Device Properties window: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Product Category: All Family: Spartan3A and Spartan3AN Device: XC3S700A Package: FG484 Speed: -4 Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: VHDL or Verilog depending on preference. ISE 9. Select the following values in the New Project Wizard .

lcd_rs. you will complete the design by generating some of the modules from scratch and by completing others from existing files. The lower-level macros are either HDL modules or IP modules. Throughout the tutorial. The following list summarizes the input and output signals of the design. Outputs The following are outputs signals for the design. The design begins as an unfinished design. In clocking mode it displays the current clock value in the ‘Lap’ display area. you will simulate it to verify the design’s functionality. Inputs The following are input signals for the tutorial stopwatch design.R Chapter 2: HDL-Based Design Design Description The design used in this tutorial is a hierarchical.com ISE 9.xilinx. This is an active low signal which acts like the start/stop button on a runner’s stopwatch. HDL-based design. clk Externally generated system clock. mode Toggles between clocking and timer modes. The system clock is an externally generated signal. This input is only functional while the clock or timer is not counting. there are five external inputs and four external output buses. • • • reset Puts the stopwatch in clocking mode and resets the time to 0:00:00.1 In-Depth Tutorial . • lap_load This is a dual function signal. • lcd_e. which means that the top-level design file is an HDL file that references several other lower-level macros. When the design is complete. In timer mode it loads the pre assigned values from the ROM to the timer display when the timer is not counting. • sf_d[7:0] Provides the data values for the LCD display. lcd_rw These outputs are the control signals for the LCD display of the Spartan-3A demo board used to display the stopwatch times. • strtstop Starts and stops the stopwatch. In the runner’s stopwatch design. Functional Blocks The completed design consists of the following functional blocks. • clk_div_262k 28 www.

2144 MHz clock into 100 Hz 50% duty cycle clock.com 29 . The CLKFX_OUT output converts the 50 MHz clock of the Spartan-3A demo board to 26. create an HDL macro.ise project open in Project Navigator. Controls the state of the stopwatch.144.ise or wtut_ver.1 In-Depth Tutorial www. and lap_load input signals. All procedures used in the tutorial can be used later for your own designs. time_cnt is instantiated. the Sources tab displays all of the source files currently added to the project. statmach State Machine module defined and implemented in State Diagram Editor. but the associated entity or module is not defined in the project. Converts 26. and add a CORE Generator and a Clocking module. mode. correct syntax errors. • debounce Schematic module implementing a simplistic debounce circuit for the strtstop. This macro has five 4-bit outputs.Design Entry R Macro which divides a clock frequency by 262. frequency controlled output. • time_cnt Up/down counter module which counts between 0:00:00 to 9:59:99 decimal. with the associated entity or module names (see Figure 2-4). ISE 9. which represent the digits of the stopwatch time. and duty-cycle correction. • • lcd_control Module controlling the initialization of and output to the LCD display. • dcm1 Clocking Wizard macro with internal feedback. you will examine HDL files. This macro contains 64 preset times from 0:00:00 to 9:59:99 which can be loaded into the timer.2144 MHz. With the wtut_vhd. In the current project. You will create and use each type of design macro. • timer_preset CORE Generator™ 64x20 ROM.xilinx. Design Entry For this hierarchical design.

Figure 2-4: Sources Tab Showing Completed Design Adding Source Files HDL files must be added to the project before they can be synthesized. In the Processes tab. 2.(<file name>).1 In-Depth Tutorial . verify that time_cnt is associated with Synthesis/Imp + Simulation and click OK.vhd File in Sources Tab Each source Design unit is represented under the sources tab using the following syntax: <instance name> . xfile add time_cnt. An additional file must be added.vhd or time_cnt. In the Adding Source Files dialog box.<architecture name> .v in the Sources tab.<entity name> . 1. Note: Alternatively.vhd or stopwatch. 3. Select time_cnt. Checking the Syntax To check the syntax of source files: 1.xilinx. click the + next to Synthesize to expand the process hierarchy. 30 www.com ISE 9. the time_cnt.R Chapter 2: HDL-Based Design Instantiated components with no entity or module declaration are displayed with a red question mark. Figure 2-5: time_cnt. 2. Three HDL files have already been added to this project. Select stopwatch.vhd file could be added to the project by entering the following command in the Tcl Shell tab.vhd The red question-mark (?) for time_cnt should change to show the VHD file icon. Select Project > Add Source. the Processes tab displays all processes available for this file. When you select the HDL file.v from the project directory and click Open.

In the Console tab of the Transcript window. The comments next to the error explain this simple fix.com 31 . Select File > Save to save the file. ISE 9. The source code comes up in the main display tab.Design Entry R 3. 2. Re-analyze the file by selecting the HDL file and double-clicking Check Syntax. The red “x” beside the Check Syntax process indicates an error was found during the analysis. 3. Project Navigator reports errors with a red (X) and warnings with a yellow (!). Note: Check Syntax is not available when Synplify is selected as the synthesis tool. 4. Double-click Check Syntax in the Synthesize hierarchy. Correcting HDL Errors The time_cnt module contains a syntax error that must be corrected. Correct any errors in the HDL source file. To display the error in the source file: 1.1 In-Depth Tutorial www.xilinx. Click the file name in the error message in the Console or Errors tab.

xilinx. Figure 2-6: New Source Wizard for Verilog 32 www. You will author a new HDL module. Enter two input ports named sig_in and clk and an output port named sig_out for the debounce component in this way: a. Set the Direction field to input for sig_in and clk and to output for sig_out. clk and sig_out. The resulting HDL file is then modified in the ISE Text Editor. This macro will be used to debounce the strtstop.com ISE 9. specifying the name and ports of the component. The HDL code is then connected to your toplevel HDL design through instantiation and is compiled with the rest of the design. type debounce. you create a file using the New Source wizard.R Chapter 2: HDL-Based Design Creating an HDL-Based Module Next you will create a module from HDL code.1 In-Depth Tutorial . The dialog box New Source Wizard opens in which you specify the type of source you want to create. To create the source file: 1. 3. Select Project > New Source. Click Next. c. 2. 5. 4. In the File Name field. In the first three Port Name fields type sig_in. b. Select VHDL Module or Verilog Module. Leave the Bus designation boxes unchecked. Using the New Source Wizard and ISE Text Editor In this section. With ISE. you can easily create modules from HDL code using the ISE Text Editor. mode and lap_load inputs.

xilinx.1 In-Depth Tutorial www. Click Finish to open the empty HDL file in the ISE Text Editor. A description of the module displays. 7. The Verilog HDL file is displayed in Figure 2-8.com 33 . Click Next to complete the Wizard session. The VHDL file is displayed in Figure 2-7. Figure 2-7: VHDL File in ISE Text Editor Figure 2-8: Verilog File in ISE Text Editor ISE 9.Design Entry R 6.

expand the Synthesis Constructs hierarchy. and values are black. and some of the basic file structure is already in place. Keywords are displayed in blue. To expand the view of any of these sections.xilinx. and primitives. Using the Language Templates The ISE Language Templates include HDL constructs and synthesis templates which represent commonly used logic components. expand the Misc hierarchy. such as counters. D flip-flops. the HDL code for a debounce circuit is displayed in the right pane. select Edit > Language Templates. Device Primitive Instantiation. Click any of the listed templates to view the template contents in the right pane.1 In-Depth Tutorial .] Debounce Circuit. comments in green. Upon selection. expand the Coding Examples hierarchy. Note: You can add your own templates to the Language Templates for components or constructs that you use often. Simulation Constructs. and select the template called [One-shot. Under either the VHDL or Verilog hierarchy.R Chapter 2: HDL-Based Design In the ISE Text Editor. To invoke the Language Templates and select the template for this tutorial: 1. Synthesis Constructs and User Templates. multiplexers. You will use the Debounce Circuit template for this exercise. From Project Navigator. 34 www. Use the appropriate template for the language you are using. The file is color-coded to enhance readability and help you recognize typographical errors.com ISE 9. click the + next to the section. the ports are already declared in the HDL file. 2. Each HDL language in the Language Templates is divided into five sections: Common Constructs.

Change <reg_name> to q in all six locations.com 35 . ISE 9.1 In-Depth Tutorial www.v file under the module and pin declarations. 3. Remove the reset logic (not used in this design) by deleting the three lines beginning with if and ending with else. Select Window > Tile Vertically to show both the HDL file and the Language Templates window.Design Entry R Figure 2-9: Language Templates Adding a Language Template to Your File You will now use the drag and drop method for adding templates to your HDL file.xilinx. Refer to “Working with Language Templates” in the ISE Help for additional usability options. b. Close the Language Templates window.vhd file under the architecture begin statement. or into the debounce. To add the template to your HDL file using the drag and drop method: 1. (Verilog only) Complete the Verilog module by doing the following: a. Click and drag the Debounce Circuit name from the Language Template topology into the debounce. 4. 2.

Defines the name of the module. 5.. and distributed and block RAM. Change <clock> to clk. double-click Check Syntax. Memory Type: ROM Click Next. and Q_OUT to sig_out. This customization GUI enables you to customize the memory to the design specifications. 7. and ending with else and delete one of the end if. then click Next and click Finish to open the Distributed Memory Generator customization GUI.Defines the width of the output bus.Defines the number of values to be stored Data Width: 20 . Creating a CORE Generator Module To create a CORE Generator module: 1. 4. Select Distributed Memory Generator. Click Next. SRL16s. <input> to sig_in. such as Fast Carry Logic. 36 www. The module will be used to store a set of 64 values to load into the timer. Depth: 64 .. lines. b. 3. c. Leave Input and output options as Non Registered. 9. Select one of the debounce instances in the Sources tab. In the Processes tab. Double-click Memories & Storage Elements.xilinx. Click Next. a. 8. (VHDL only) Complete the VHDL module by doing the following: You now have complete and functional HDL code. 6. Remove the reset logic (not used in this design) by deleting the five lines beginning with if (<reset>. Use Edit > Replace to change <clock> to clk. math functions and communications and IO interface cores. select Project > New Source. You can customize and pre-optimize the modules to take advantage of the inherent architectural features of the Xilinx FPGA architectures.R Chapter 2: HDL-Based Design c. Type timer_preset in the File name field. Fill in the Distributed Memory Generator customization GUI with the following settings: ♦ ♦ ♦ ♦ ♦ ♦ 7. Creating a CORE Generator Module CORE Generator is a graphical interactive design tool that enables you to create high-level modules such as memory elements.com ISE 9. and <output> to sig_out. then double-click RAMs & ROMs. Save the file by selecting File > Save. 2. D_IN to sig_in. In Project Navigator. In this section. Move the line beginning with the word signal so that it is between the architecture and begin keywords.1 In-Depth Tutorial . 5. 6. Select IP (Coregen & Architecture Wizard). you will create a CORE Generator module called timer_preset. Component Name: timer_preset . Close the ISE Text Editor.

edn This file is the netlist that is used during the Translate phase of implementation.veo These are the instantiation templates used to incorporate the CORE Generator module into your source HDL.Distributed Memory Generator Customization GUI Check that only the following pins are used (used pins are highlighted on the symbol on the left side of the customization GUI): ♦ ♦ a[5:0] spo[19:0] 9. timer_preset.xilinx. CORE Generator .xco This file stores the configuration information for the timer_preset module and is used as a project source. ♦ timer_preset.Design Entry R ♦ Coefficients File: Click the Browse button and select definition1_times.vhd or timer_preset. timer_preset. Some of these files are: ♦ timer_preset.coe.com 37 .1 In-Depth Tutorial www.mif This file provides the initialization values of the ROM for simulation. Click Finish.vho or timer_preset. Note: A number of files are added to the project directory. ISE 9.v These are HDL wrapper files for the core and are used only for simulation. The module is created and automatically added to the project library. Figure 2-10: 8. ♦ ♦ ♦ timer_preset.

In Project Navigator. VHDL Flow To instantiate the CORE Generator module using a VHDL flow: 1. Figure 2-11: 4.com ISE 9. 2.R Chapter 2: HDL-Based Design Instantiating the CORE Generator Module in the HDL Code Next. 3. Change the instance name from your_instance_name to t_preset.xilinx. The VHDL template file for the CORE Generator instantiation is inserted. Place your cursor after the line that states: -. double-click stopwatch.END INSTANTIATION Template ----- 5. 6.Begin Cut here for INSTANTIATION Template ---- to --INST_TAG_END -----. 7. then select timer_preset. Select Edit > Cut.vho and click Open. 8. Place the cursor after the line that states: --Insert CORE Generator ROM Instantiation here Select Edit > Paste to place the core instantiation. 9.1 In-Depth Tutorial .Insert CORE Generator ROM component declaration here Select Edit > Insert File. VHDL Component Declaration for CORE Generator Module Highlight the inserted code from -. instantiate the CORE Generator module in the HDL code using either a VHDL flow or a Verilog flow. Figure 2-12: VHDL Component Instantiation of CORE Generator Module 38 www.vhd to open the file in ISE Text Editor. Edit this instantiated code to connect the signals in the Stopwatch design to the ports of the CORE Generator module as shown in Figure 2-12.

Save the design using File > Save and close stopwatch. 11. In this section you will create a basic DCM module with CLK0 feedback and duty-cycle correction. Spartan-3A > Single DCM SP. In Project Navigator.Design Entry R 10. and close the ISE Text Editor. select IP (CoreGen & Architecture Wizard) source and type dcm1 for the file name. select Project > New Source. Verilog Flow To instantiate the CORE Generator module using a Verilog flow: 1. Edit this code to connect the signals in the Stopwatch design to the ports of the CORE Generator module as shown in Figure 2-13. ISE 9. select FPGA Features and Design > Clocking > Spartan3E. 6. Click Next. The inserted code of timer_preset. 2. 3. In Project Navigator. Figure 2-13: Verilog Component Instantiation of the CORE Generator Module 7. The inserted code of timer_preset. Delete these commented lines if desired. 2. Using the Clocking Wizard To create the dcm1 module: 1. Save the design using File > Save. double-click stopwatch.veo. Change the instance name from YourInstanceName to t_preset.1 In-Depth Tutorial www.v to open the file in the ISE Text Editor.veo contains several lines of commented text for instruction and legal documentation.com 39 . In the New Source dialog box. 3. Delete these commented lines if desired.vho contains several lines of commented text for instruction and legal documentation. and select timer_preset. Creating a DCM Module The Clocking Wizard. a part of the Xilinx Architecture Wizard. enables you to graphically select Digital Clock Manager (DCM) features that you wish to use.v in the ISE Text Editor.xilinx. 5. 4. 4. In the Select IP dialog box. Place your cursor after the line that states: //Place the Coregen module instantiation for timer_preset here Select Edit > Insert File.

and then click Next again.R Chapter 2: HDL-Based Design Figure 2-14: Selecting Single DCM IP Type 5. 11.xaw file is added to the list of project source files in the Sources tab. 7. Single Feedback Source: Internal Feedback Value: 1X Use Duty Cycle Correction: Selected 10. Click the Advanced button. 8. then Finish.com ISE 9.2144Mhz ) ⁄ 2 18 = 100Hz 15.1 In-Depth Tutorial . Select Wait for DCM lock before DONE Signal goes high. Verify that RST. Select Use output frequency and type 26. The Clocking Wizard is launched. Click OK. The dcm1. ( 26. 40 www.xilinx. 6. and then click Finish. 13. 9. 14. Verify the following settings: ♦ ♦ ♦ ♦ ♦ Phase Shift: NONE CLKIN Source: External. 12. Type 50 and select MHz for the Input Clock Frequency. Click Next. Select CLKFX port. Click Next. Click Next. CLK0 and LOCKED ports are selected.2144 in the box and select MHz.

VHDL DCM Component Declaration Place the cursor in the stopwatch.VHDL Design Next. Select Edit > Copy. 9. 5. Place the cursor in the stopwatch.Insert dcm1 component declaration here.vhd file below the line labeled “-. Figure 2-15: 6. double-click View HDL Instantiation Template. To instantiate the dcm1 macro for the VHDL design: 1.com 41 . select dcm1. shown below. In Project Navigator. you will instantiate the dcm1 macro for your VHDL or Verilog design. In the Processes tab. right-click View HDL Instantiation Template and select Properties.1 In-Depth Tutorial www. 2.xilinx. ISE 9.vhi). Select Edit > Paste to paste the component declaration. In the Processes tab. 3. Select Edit > Copy. VHDL DCM Component Instantiation 11. 8.xaw. in the Sources tab. Choose VHDL for the HDL Instantiation Template Target Language value and click OK. 4. shown below. Figure 2-16: 10. 7.Insert dcm1 instantiation here”.Design Entry R Instantiating the dcm1 Macro .vhd file in a section labeled -. Highlight the component declaration template in the newly opened HDL Instantiation Template (dcm1. Highlight the instantiation template in the newly opened HDL Instantiation Template.

in the Sources tab. 42 www. Make the necessary changes as shown in the figure below. 2. 5. dcm1 Macro and Instantiation Templates Paste the instantiation template into the section in stopwatch.com ISE 9. In the Processes tab. Make the necessary changes as shown in the figure below.vhd file. select dcm1. copy the instantiation template. Select File > Save to save the stopwatch. In Project Navigator. Figure 2-17: VHDL Instantiation for dcm1 14. double-click View HDL Instantiation Template.xilinx. From the newly opened HDL Instantiation Template (dcm1.v file. Figure 2-19: Verilog Instantiation for dcm1 6. Select Edit > Paste to paste the instantiation template.1 In-Depth Tutorial . 13. Select File > Save to save the stopwatch.v labeled //Insert dcm1 instantiation here.Verilog To instantiate the dcm1 macro for your Verilog design: 1.tfi).R Chapter 2: HDL-Based Design 12. shown below. Figure 2-18: 4.xaw. 3. Instantiating the dcm1 Macro .

Next. For projects that contain implementation data.com 43 . To change the synthesis tool: 1. Select Source > Properties. Select the targeted part in the Sources tab. Compile Translates and optimizes the HDL code into a set of components that the synthesis tool can recognize.xilinx. 3. you will synthesize the design using either XST. Changing the design flow results in the deletion of implementation data. click on the Synthesis Tool value and use the pulldown arrow to select the desired synthesis tool from the list. Figure 2-20: Specifying Synthesis Tool Note: If you do not see your synthesis tool among the options in the list. Synplify/Synplify Pro or Precision. • Map Translates the components from the compile stage into the target technology’s primitive components. expand ISE General.Synthesizing the Design R Synthesizing the Design So far you have been using XST (the Xilinx synthesis tool) for syntax checking.1 In-Depth Tutorial www. The synthesis tool can be changed at any time during the design flow. Xilinx recommends that you take a snapshot of the project before changing the ISE 9. 2. then click Integrated Tools). The synthesis tool performs three general steps (although all synthesis tools further break down these general steps) to create the netlist: • • Analyze / Check Syntax Checks the syntax of the source code. In the Project Properties dialog box. you may not have the software installed or may not have it configured in ISE. You have not yet created any implementation data in this tutorial. The Synthesis tools are configured in the Preferences dialog box (Edit > Preferences. The synthesis tool uses the design’s HDL code and generates a supported netlist type (EDIF or NGC) for the Xilinx implementation tools.

View Technology Schematic Generates a schematic view of your Technology netlist. 3. In the Add Existing Sources dialog box. Check Syntax Verifies that the HDL code is entered properly. using the following command and then selecting View > Refresh. This format is called the Xilinx Constraint File (XCF). the HDL files are translated into gates and optimized for the target architecture. A summary of available synthesis tools is available in “Overview of Synthesis Tools” in Chapter 1 Read the section for your synthesis tool: • • • “Synthesizing the Design using XST” “Synthesizing the Design using Synplify/Synplify Pro” “Synthesizing the Design Using Precision Synthesis” Synthesizing the Design using XST Now that you have created and analyzed the design. Double-click stopwatch.xcf is added as a User Document.xcf file extension.xcf 4. 2.xcf extension to determine if the file is a constraints file. During synthesis. and the file has an .xcf.xcf file: 44 www.R Chapter 2: HDL-Based Design synthesis tool to preserve this data. 5.xilinx. xfile add stopwatch. Entering Constraints XST supports a User Constraint File (UCF) style syntax to define synthesis and timing constraints.com ISE 9. To create a new Xilinx Constraint File: 1. the next step is to synthesize the design. Generate Post-Synthesis Simulation Model Creates HDL simulation models based on the synthesis netlist. see “Creating a Snapshot” in Chapter 1. Processes available for synthesis using XST are as follows: • View Synthesis Report Gives a synthesis mapping and timing summary as well as a list of optimizations that took place. Note: In place of the three steps above.xcf file through the Tcl Shell. XST uses the . For more information about taking a snapshot.1 In-Depth Tutorial .*) and then select and add stopwatch. Select Project > Add Source. you may add the . The following constraints should exist in the stopwatch. change the Files of type: to ‘All Files (*. • • • • View RTL Schematic Generates a schematic view of your RTL netlist.xcf to open the file in the ISE Text Editor. Notice that stopwatch.

xcf.v) in the Sources tab. To take the HDL code and generate a compatible netlist: 1. In the Processes tab. 2.xcf. There are two forms of the schematic representation: • • RTL View .Post-synthesis view of the HDL design mapped to the target technology. Double-click the Synthesize process in the Processes tab. 4. Note: For more constraint options in the implementation tools. right-click the Synthesize process and select Properties. LOC = "AA12". 5. Click OK.vhd (or stopwatch. Select stopwatch. Technology View . LOC = "Y15". ISE 9. click in the Synthesis Constraints File property field and enter stopwatch. 6.Synthesizing the Design R NET "CLK" TNM_NET = "CLK_GROUP". TIMESPEC “TS_CLK”=PERIOD “CLK_GROUP” 20 ns. One commonly used option is to control synthesis to make optimizations based on area or speed. Select stopwatch.com 45 . The RTL / Technology Viewer XST can generate a schematic representation of the HDL code that you have entered. LOC = "AB16". LOC = "AB18".v). Under the Synthesis Options tab. BEGIN MODEL stopwatch NET "sf_d<7>" NET "sf_d<6>" NET "sf_d<5>" NET "sf_d<4>" NET "sf_d<3>" NET "sf_d<2>" NET "sf_d<1>" NET "sf_d<0>" END.1 In-Depth Tutorial www. “Design Implementation.vhd (or stopwatch.” Entering Synthesis Options Synthesis options enable you to modify the behavior of the synthesis tool to make optimizations according to the needs of the design. 3. LOC = "AB12". LOC = "Y16". Other options include controlling the maximum fanout of a flip-flop output or setting the desired frequency of the design.Pre-optimization of the HDL code.xilinx. To enter synthesis options: 1. Synthesizing the Design Now you are ready to synthesize your design. see “Using the Constraints Editor” and “Using the Floorplan Editor” in Chapter 5. LOC = "AB17". LOC = "Y13". Check the Write Timing Constraints box. Close stopwatch. A schematic view of the code helps you analyze your design by displaying a graphical connection between the various components that XST has inferred. 2.

com ISE 9. An NGC file now exists for the Stopwatch design. The RTL Viewer displays the top level schematic symbol for the design. Right-click the schematic to view the various operations that can be performed in the schematic viewer. see the XST User Guide. reports.1 In-Depth Tutorial .com/support/sw_manuals/xilinx9/. or running XST from the command line. Note: For more information about XST constraints. Double-click on the symbol to push into the schematic and view the various design elements and connectivity.xilinx.xilinx. click the + next to Synthesize to expand the process hierarchy. This guide is available in the collection of software manuals and is accessible from ISE by selecting Help > Software Manuals.R Chapter 2: HDL-Based Design To view a schematic representation of your HDL code: 1. Figure 2-21: RTL Viewer You have completed XST synthesis. or from the web at http://www. “Behavioral Simulation. OR • Proceed to Chapter 5. options. “Design Implementation.” to perform a pre-synthesis simulation of this design. 2.” to place and route the design. In the Processes tab. 46 www. Double-click View RTL Schematic or View Technology Schematic. To continue with the HDL flow: • Go to Chapter 4.

xilinx. In the Processes tab. Note: Black boxes (modules not read into a design environment) are always noted as unbound in the Synplify reports. clicking Synthesize in the Processes tab. double-click View Synthesis Report under the Synthesize process. 5. and displays the syntax checking result for each file that was compiled. and selecting Process > Run.ngo. Check the Write Vendor Constraint File box. names which file is the top level. Processes available in Synplify and Synplify Pro synthesis include: • View Synthesis Report Lists the synthesis optimizations that were performed on the design and gives a brief timing and mapping report. the HDL files are translated into gates and optimized to the target architecture. • View RTL Schematic Accessible from the Launch Tools hierarchy.vhd (or stopwatch. Double-click the Synthesize process to run synthesis. In this step.vhd (or stopwatch. Examining Synthesis Results To view overall synthesis results.v). this process displays Synplify or Synplify Pro with a schematic view of your HDL code mapped to the primitives associated with the target technology.v). ISE 9. As long as the underlying netlist (. right-click the Synthesize process and select Properties. the implementation tools merge the netlist into the design during the Translate phase. . To access Synplify’s RTL viewer and constraints editor you must run Synplify outside of ISE. warnings on latches. inferred memory.ngc or .com 47 . unused ports. The report also lists FSM extractions. To synthesize the design. Note: This step can also be done by selecting stopwatch. 2. Select stopwatch. this process displays Synplify or Synplify Pro with a schematic view of your HDL code • View Technology Schematic Accessible from the Launch Tools hierarchy. 3. set the global synthesis options: 1. the next step is to synthesize the design. 4.Synthesizing the Design R Synthesizing the Design using Synplify/Synplify Pro Now that you have entered and analyzed the design. and removal of redundant logic. The report consists of the following four sections: • • • • “Compiler Report” “Mapper Report” “Timing Report” “Resource Utilization” Compiler Report The compiler report lists each HDL file that was compiled. Click OK to accept these values.1 In-Depth Tutorial www.edn) for a black box exists in the project directory.

In this step. At this point. the HDL files are translated into gates and optimized to the target architecture. the target technology.com ISE 9. and how FSMs were coded.” for the most accurate delay information. clock and buffered nets that were created.xilinx. “Design Implementation. and attributes set in the design. OR • Proceed to Chapter 5. “Behavioral Simulation. View Log File 48 www. Timing Report The timing report section provides detailed information on the constraints that you entered and on delays on parts of the design that had no constraints.1 In-Depth Tutorial . Consult the post-place and route timing reports discussed in Chapter 5.” to place and route the design. Synthesizing the Design Using Precision Synthesis Now that you have entered and analyzed the design. Processes available for Precision Synthesis include: • • Check Syntax Checks the syntax of the HDL code.R Chapter 2: HDL-Based Design Mapper Report The mapper report lists the constraint files used. optimized flip-flops. The delay values are based on wireload models and are considered preliminary.” to perform a pre-synthesis simulation of this design. The report lists the mapping results of flattened instances. a netlist EDN file exists for the Stopwatch design. “Design Implementation. Figure 2-22: Synplify’s Estimated Timing Data Resource Utilization This section of the report lists all of the resources that Synplify uses for the given target technology. the next step is to synthesize the design. To continue with the HDL flow: • Go to Chapter 4. extracted counters. You have now completed Synplify synthesis.

Synthesizing the Design

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Lists the synthesis optimizations that were performed on the design and gives a brief timing and mapping report. • View RTL Schematic Accessible from the Launch Tools hierarchy, this process displays Precision with a schematic-like view of your HDL code • View Technology Schematic Accessible from the Launch Tools hierarchy, this process displays Precision with a schematic-like view of your HDL code mapped to the primitives associated with the target technology. • View Critical Path Schematic Accessible from the Launch Tools hierarchy, this process displays Precision with a schematic-like view of the critical path of your HDL code mapped to the primitives associated with the target technology.

Entering Synthesis Options through ISE
Synthesis options enable you to modify the behavior of the synthesis tool to optimize according to the needs of the design. For the tutorial, the default property settings will be used. 1. 2. Select stopwatch.vhd (or stopwatch.v) in the Sources tab. Double-click the Synthesize process in the Processes tab.

The RTL/Technology Viewer
Precision Synthesis can generate a schematic representation of the HDL code that you have entered. A schematic view of the code helps you analyze your design by seeing a graphical connection between the various components that Precision has inferred. To launch the design in the RTL viewer, double-click the View RTL Schematic process. The following figure displays the design in an RTL view.

Figure 2-23:

Stopwatch Design in Precision Synthesis RTL Viewer

You have now completed the design synthesis. At this point, an EDN netlist file exists for the Stopwatch design. To continue with the HDL flow:

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Chapter 2: HDL-Based Design

Go to Chapter 4, “Behavioral Simulation,” to perform a pre-synthesis simulation of this design. OR Proceed to Chapter 5, “Design Implementation,” to place and route the design.

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Chapter 3

Schematic-Based Design
This chapter includes the following sections: • • • • “Overview of Schematic-Based Design” “Getting Started” “Design Description” “Design Entry”

Overview of Schematic-Based Design
This chapter guides you through a typical FPGA schematic-based design procedure using the design of a runner’s stopwatch. The design example used in this tutorial demonstrates many device features, software features, and design flow practices that you can apply to your own designs. The stopwatch design targets a Spartan™-3A device; however, all of the principles and flows taught are applicable to any Xilinx® device family, unless otherwise noted. This chapter is the first in the “Schematic Design Flow.” In the first part of the tutorial, you will use the ISE™ design entry tools to complete the design. The design is composed of schematic elements, a state machine, a CORE Generator™ component, and HDL macros. After the design is successfully entered in the Schematic Editor, you will perform behavioral simulation (Chapter 4, “Behavioral Simulation”), run implementation with the Xilinx Implementation Tools (Chapter 5, “Design Implementation”), perform timing simulation (Chapter 6, “Timing Simulation”), and configure and download to the Spartan-3A (XC3S700A) demo board (see Chapter 7, “iMPACT Tutorial.”).

Getting Started
The following sections describe the basic requirements for running the tutorial.

Required Software
You must have Xilinx ISE 9.1i installed to follow this tutorial. For this design you must install the Spartan-3A libraries and device files. A schematic design flow is supported on Windows, Solaris, and Linux platforms.

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This tutorial assumes that the files are unarchived under c:\xilinx\ISEexamples.xilinx. If you restore the files to a different location. Figure 3-1: Project Navigator Desktop Icon Creating a New Project Two methods are provided for creating a new project: Using the New Project Wizard.htm.xilinx. and State Machine files. 52 www. If you have installed the software in a different location. including schematic. Do not overwrite files under this directory. substitute c:\xilinx for your installation path. Double-click the ISE Project Navigator icon on your desktop. Installing the Tutorial Project Files The tutorial project files can be downloaded to your local machine from http://www.1i Installation Guide and Release Notes.R Chapter 3: Schematic-Based Design This tutorial assumes that the software is installed in the default location. Download the Watch Schematic Design Files (wtut_sch. Note: For detailed instructions about installing the software.1i > Project Navigator. at c:\xilinx. refer to the ISE 9. substitute c:\xilinx\ISEexamples with the project path. and Using a Tcl Script. Starting the ISE Software To launch the ISE software package: 1. The download contains two directories: • wtut_sc\ (Contains source files for schematic tutorial. or select Start > All Programs > Xilinx ISE 9. The schematic tutorial project will be created in this directory).zip).com/support/techsup/tutorials/tutorials9.com ISE 9. wtut_sc\wtut_sc_completed\ (Contains the completed design files for the schematic-based tutorial design. The schematic tutorial files are copied into the directories when you unzip the files.) • Unzip the tutorial design files in any directory with read-write permissions. HDL.1 In-Depth Tutorial .

com 53 .Getting Started R Creating a New Project: Using New Project Wizard 1. Figure 3-2: New Project Wizard .Create New Project 2.xilinx. Notice that wtut_sc is appended to the Project Location value. Select Schematic as the Top-Level Source Type. Type wtut_sc as the Project Name. and then click Next.Device Properties ISE 9. 3.1 In-Depth Tutorial www. From Project Navigator. Figure 3-3: New Project Wizard . select File > New Project. Browse to c:\xilinx\ISEexamples or enter the directory in the Project Location field. 4. The New Project Wizard appears.

schematic-based design. including schematicbased modules. an Architecture Wizard module.com ISE 9.xilinx.dia 9.R Chapter 3: Schematic-Based Design 5. 2. Click OK. and then click Add Source in the New Project Wizard .1 In-Depth Tutorial . Click Next. Select the following values in the New Project Wizard . which means that the top-level design file is a schematic sheet that refers to several other lower-level macros.g. ♦ ♦ ♦ ♦ ♦ ♦ cd4rled. 10. Type cd c:/xilinx/ISEexamples/wtut_sc). Verify that all added schematic files are associated with Synthesis/Imp + Simulation.sch clk_div_262k.vhd lcd_control. This will determine the default language for all processes that generate HDL files.sch statmach. a CORE Generator module. 1. The lower-level macros are a variety of different types of modules.Device Properties window: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Product Category: All Family: Spartan3A and Spartan3AN Device: XC3S700A Package: FG484 Speed: -4 Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: VHDL or Verilog depending on preference. then Finish to complete the New Project Wizard. save your work by selecting File > Save All.Add Existing Sources window. and that the . 54 www. 7. Creating a New Project: Using a Tcl Script With Project Navigator open. a state machine module. Stopping the Tutorial If you need to stop the tutorial at any time. Change the current working directory to the directory where the tutorial source files were unzipped.sch ch4rled. 11. Design Description The design used in this tutorial is a hierarchical. (e. Type source create_wtut_sc.tcl. select the Tcl Shell tab. Click Next twice. Select the following files and click Open. 6. Browse to c:\xilinx\ISEexamples\wtut_sc. and HDL modules.vhd stopwatch. 8.dia file is associated with Synthesis/Implementation Only.

you will complete the design by creating some of the modules and by completing others from existing files. After the design is complete.com 55 . For more information about simulating your design. Throughout the tutorial. ISE 9.Design Description R The runner’s stopwatch design begins as an unfinished design. you will create these modules. you will simulate the design to verify its functionality. “Behavioral Simulation. A schematic of the completed stopwatch design is shown in the following figure. and their respective functions.xilinx.” Figure 3-4: Completed Watch Schematic There are five external inputs and four external outputs in the completed design. see Chapter 4. Inputs The following are input signals for the tutorial stopwatch design. instantiate them.1 In-Depth Tutorial www. and then connect them. The following sections summarize the inputs and outputs. Through the course of this chapter.

The completed design consists of the following functional blocks. • • • reset Puts the stopwatch in clocking mode and resets the time to 0:00:00. Functional Blocks The completed design consists of the following functional blocks. lcd_rs.xilinx. Most of these blocks do not appear on the schematic sheet in the project until after you create and add them to the schematic during this tutorial.1 In-Depth Tutorial . statmach 56 www. • dcm1 Clocking Wizard macro with internal feedback.R Chapter 3: Schematic-Based Design • strtstop Starts and stops the stopwatch. and duty-cycle correction. • lap_load This is a dual function signal. lcd_rw These outputs are the control signals for the LCD display of the Spartan-3A demo board used to display the stopwatch times. This input is only functional while the clock or timer is not counting.2144 MHz. mode. and lap_load input signals. Outputs The following are outputs signals for the design. This is an active low signal which acts like the start/stop button on a runner’s stopwatch. clk Externally generated system clock. • • lcd_control Module controlling the initialization of and output to the LCD display. • debounce Module implementing a simplistic debounce circuit for the strtstop.144. • lcd_e.2144 MHz clock into 100 Hz 50% duty cycle clock.com ISE 9. The CLKFX_OUT output converts the 50 MHz clock of the Spartan-3A demo board to 26. • sf_d[7:0] Provides the data values for the LCD display. mode Toggles between clocking and timer modes. Converts 26. • clk_div_262k Macro which divides a clock frequency by 262. In clocking mode it displays the current clock value in the ‘Lap’ display area. frequency controlled output. In timer mode it will load the pre-assigned values from the ROM to the timer display when the timer is not counting.

Opening the Schematic File in the Xilinx Schematic Editor The stopwatch schematic available in the wtut_sc project is incomplete. state machine macros. which represent the digits of the stopwatch time. double-click stopwatch.Design Entry R State Machine module defined and implemented in State Diagram Editor.1 In-Depth Tutorial www. you can now open the stopwatch. You will learn the process for creating each of these types of macros. and CORE Generator macros. After you have created the project in ISE.com 57 . you will update the schematic in the Schematic Editor. To open the schematic file. you will create various types of macros. ISE 9. Design Entry In this hierarchical design. • timer_preset CORE Generator™ 64X20 ROM. HDL-based macros.sch in the Sources window.sch file for editing. This macro contains 64 preset times from 0:00:00 to 9:59:99 which can be loaded into the timer. All procedures used in the tutorial can be used later for your own designs.xilinx. Controls the state of the stopwatch. including schematicbased macros. This macro has five 4-bit outputs. • time_cnt Up/down counter module which counts between 0:00:00 to 9:59:99 decimal. and you will connect the macros together to create the completed stopwatch design. In this tutorial.

58 www. the schematic window can be redocked by selecting Window > Dock.R Chapter 3: Schematic-Based Design The stopwatch schematic diagram opens in the Project Navigator Workspace. Select View > Zoom > In until you can comfortably view the schematic.1 In-Depth Tutorial .xilinx. You will see the unfinished design with elements in the lower right corner as shown in the figure below. The corresponding symbol or schematic file can then be generated automatically. After being undocked. The schematic window can be undocked from the Project Navigator framework by selecting Window > Float while the schematic is selected in the workspace. You can create either the underlying schematic or the symbol first. Creating a Schematic-Based Macro A schematic-based macro consists of a symbol and an underlying schematic. Figure 3-5: Incomplete Stopwatch Schematic Manipulating the Window View The View menu commands enable you to manipulate how the schematic is displayed.com ISE 9.

This macro is a binary counter with five. The next step is to add the components that make up the time_cnt macro.com 59 . Enter time_cnt as the file name. 4. 4bit outputs. 5. Click OK and then click Yes to acknowledge that changing the sheet size cannot be undone with the Edit > Undo option. 2. Click Next and click Finish. 3. The macro you will create is called time_cnt. ISE 9. added to the project. You can then reference this macro symbol by placing it on a schematic sheet. representing the digits of the stopwatch. and opened for editing. Select Schematic as the source type.Design Entry R In the following steps. A new schematic called time_cnt is created. you will create a schematic-based macro by using the New Source Wizard in Project Navigator. and you can define the appropriate logic. select Project > New Source. An empty schematic file is then created. In Project Navigator. Change the size of the schematic sheet by doing the following. The New Source dialog box opens: Figure 3-6: New Source Dialog Box The New Source dialog displays a list of all of the available source types.1 In-Depth Tutorial www. The created macro is then automatically added to the project’s library. Click on the down arrow next to the sheet size value and select D = 34 x 22. To create a schematic-based macro: 1. Defining the time_cnt Schematic You have now created an empty schematic for time_cnt. ♦ ♦ ♦ Right-click on the schematic page and select Object Properties.xilinx.

3. Figure 3-8: Add Symbol Icon 60 www. In the Inputs box. Adding Schematic Components Components from the device and project libraries for the given project are available from the Symbol Browser. The available components listed in the Symbol Browser are arranged alphabetically within each library.xilinx.R Chapter 3: Schematic-Based Design Adding I/O Markers I/O markers are used to determine the ports on a macro. enter q(19:0). Creating I/O Markers Click OK. From the menu bar. The eleven I/O markers are added to the schematic sheet. The name of each pin on the symbol must have a corresponding connector in the underlying schematic.ce.clk.load. Select Tools > Create I/O Markers. Add I/O markers to the time_cnt schematic to determine the macro ports. I/O markers may be added to nets at any time by selecting Add > I/O Marker and selecting the desired net.sec_msb(3:0).tenths(3:0).clr. 2. 1. To add the I/O markers: 1.minutes(3:0).up. The Create I/O Markers dialog box opens.sec_lsb(3:0). enter hundredths(3:0). However.1 In-Depth Tutorial . Note: The Create I/O Marker function is available only for an empty schematic sheet. Figure 3-7: 4. In the Outputs box. Note: The Options window changes depending on which tool you have selected in the Tools toolbar.com ISE 9. and the component symbol can be placed on the schematic. select Add > Symbol or click the Add Symbol icon from the Tools toolbar. or the top-level schematic.

Design Entry

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This opens the Symbol Browser to the left of the schematic editor, displaying the libraries and their corresponding components.

Figure 3-9:

Symbol Browser

The first component you will place is a cd4rled, a 4-bit, loadable, bi-directional, BCD counter with clock enable and synchronous clear. 2. Select the cd4rled component, using one of two ways:

Highlight the project directory category from the Symbol Browser dialog box and select the component cd4rled from the symbols list. or Select All Symbols and type cd4rled in the Symbol Name Filter at the bottom of the Symbol Browser window.

3. 4.

Move the mouse back into the schematic window. You will notice that the cursor has changed to represent the cd4rled symbol. Move the symbol outline near the top and center of the sheet and click the left mouse button to place the object. Note: You can rotate new components being added to a schematic by selecting Ctrl+R. You
can rotate existing components by selecting the component, and then selecting Ctrl+R.

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R

Chapter 3: Schematic-Based Design

5.

Place three more cd4rled symbols on the schematic by moving the cursor with attached symbol outline to the desired location, and clicking the left mouse button. See Figure 3-10

Figure 3-10: 6. • • •

Partially Completed time_cnt Schematic

Follow the procedure outlined in steps 1 through 4 above to place the following components on the schematic sheet: AND2b1 ch4rled AND5

Refer to Figure 3-10 for placement locations. To exit the Symbols Mode, press the Esc key on the keyboard.

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Design Entry

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For a detailed description of the functionality of Xilinx Library components, right-click on the component and select Object Properties. In the Object Properties window, select Symbol Info. Symbol information is also available in the Libraries Guides, accessible from the collection of software manuals on the web at http://www.xilinx.com/support/sw_manuals/xilinx9/.

Correcting Mistakes
If you make a mistake when placing a component, you can easily move or delete the component. To move the component, click the component and drag the mouse around the window. Delete a placed component in one of two ways: • • Click the component and press the Delete key on your keyboard. or Right-click the component and select Delete.

Drawing Wires
Use the Add Wire icon in the Tools toolbar to draw wires (also called nets) to connect the components placed in the schematic. Perform the following steps to draw a net between the AND2b1 and top cd4rled components on the time_cnt schematic. 1. Select Add > Wire or click the Add Wire icon in the Tools toolbar.

Figure 3-11: 2. 3.

Add Wire Icon

Click the output pin of the AND2b1 and then click the destination pin CE on the cd4rled component. The Schematic Editor draws a net between the two pins. Draw a net to connect the output of the AND5 component to the inverted input of the AND2b1 component. Connect the other input of the AND2b1 to the ce input IO marker. Connect the load, up, clk, and clr input IO markers respectively to the L, UP, C, and R pins of each of the five counter blocks and connect the CEO pin of the first four counters to the CE pin of the next counter as shown in Figure 3-10.

4.

To specify the shape of the net: 1. 2. Move the mouse in the direction you want to draw the net. Click the mouse to create a 90-degree bend in the wire.

To draw a net between an already existing net and a pin, click once on the component pin and once on the existing net. A junction point is drawn on the existing net.

Adding Buses
In the Schematic Editor, a bus is simply a wire that has been given a multi-bit name. To add a bus, use the methodology for adding wires and then add a multi-bit name. Once a bus

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64 www. To tap off a single bit of each bus: 1. The thick line should automatically be drawn to represent a bus with the name matching that of the I/O marker. tenths(3:0). Select Add > Wire or click the Add Wire icon in the Tools toolbar. Use Bus Taps to tap off a single bit of a bus and connect it to another component. indicating that you are now in Draw Bus Tap mode. sec_lsb(3:0). 5. Figure 3-12: 4. Select all of the output IO markers by drawing a box around them and then drag the group so that minutes(3:0) is below the Q3 output of the bottom counter block. The results can be found in the completed schematic. Click in the open space just above and to the right of the top cd4rled and then click again on the pin of the hundredths(3:0) I/O marker. press Esc or right-click at the end of the bus to exit the Add Wire mode. 2. sec_msb(3:0) and minutes(3:0) to the schematic. After adding the five buses. add nets to attach the appropriate pins from the cd4rled and ch4rled counters to the buses.xilinx. Note: Zooming in on the schematic enables greater precision when drawing the nets. you have the option of “tapping” this bus off to use each signal individually. From the Options tab to the left of the schematic. choose the --< Right orientation for the bus tap.R Chapter 3: Schematic-Based Design has been created.1 In-Depth Tutorial . To add the buses hundredths(3:0). The next step is to create three buses for each of the five outputs of the time_cnt schematic. 2. Adding Bus Taps Next. Adding a Bus Repeat Steps 2 and 3 for the four remaining buses. Select Add > Bus Tap or click the Add Bus Tap icon in the Tools toolbar.com ISE 9. Figure 3-13: Add Bus Tap Icon The cursor changes. 3. perform the following steps: 1.

The bus tap figure is for visual purposes only. 6. Add Net Name Icon Type tc_out0 in the Name box and select Increase the Name in the Add Net Names Options dialog box. Compare your time_cnt schematic with Figure 3-15 to ensure that all connections are made properly. Repeat step 2 and then click successively on the nets connected to the TC output to add tc_out0. and nets are named from the bottom up. Adding Net Names First. tc_out3 and tc_out4. The following section shows additional electrical connections by name association.xilinx. Click the net attached to the first input of the AND5 component. Next. Note: It is the name of the wire that makes the electrical connection between the bus and the wire (e. Press Esc to exit the Add Net Name mode. The Selected Bus Name and the Net Name values of the options window are now populated. Repeat Steps 3 to 6 to tap off four bits from each of the five buses. Note: Four selection squares appear around the pin when the cursor is in the correct position. 8. Click once when the cursor is in the correct position. ISE 9. Figure 3-14: 2. To add the net names: 1. move the cursor so the tip of the attached tap touches the Q3 pin of the top cd4rled component. Note: The indexes of the Net Name may be incremented or decremented by clicking the arrow buttons next to the Net Name box.g sec_msb(2) connects to the third bit of sec(3:0)). The name is then attached to the net. Select Add > Net Name or click the Add Net Name icon in the Tools toolbar. 3.1 In-Depth Tutorial www. 5. 4. Q1. and tc_out4 to these nets. add net names to the wires.Design Entry R 3. tc_out2. and Q0 to create taps for the remaining bits of the hundredths(3:0) bus. The net name appears above the net if the name is placed on any point of the net other than an end point. tc_out3. A tap is connected to the hundredths(3:0) bus and a wire named hundreths(3) is drawn between the tap and the Q3 pin. With hundredths(3) as the Net Name value. Click successively on pins Q2. The Schematic Editor increments the net Name as each name is placed on a net. Alternatively.com 65 . 4. name the first net tc_out4 and select Decrease the name in the Add Net Names Options dialog box. Click on the hundreths(3:0) bus with the center bar of the cursor. 5. tc_out2. The net name tc_out0 is now attached to the cursor. add a hanging wire to each of the five inputs of the AND5 component and to the TC pin of each of the counter blocks. Click on the remaining input nets of the AND5 to add tc_out1. 7. tc_out1.

The net name q(0) is now attached to the cursor. The Console window should report that no errors or warnings are detected. If an error or warning is displayed. select View > Refresh to refresh the screen. connect the input pins of the counters through net name association. Click successively on each of the nets connected to data inputs. the nets do not need to be physically connected on the schematic to make the logical connection. 1. 66 www. 5. Finally. To do this. starting from the top so that the net named q(0) is attached to the D0 pin of the top counter and the net named q(19) is attached to the D3 pin of the bottom counter. 3. fix the reported problem before proceeding.xilinx. 2. Note: If the nets appear disconnected. select Tools > Check Schematic. Type q(0) in the Name box of the Add Net Name options dialog box. Select Add > Net Name or click the Add Net Name icon in the Tools toolbar. Refer to Figure 3-15. Figure 3-15: Completed time_cnt Schematic Checking the Schematic The time_cnt schematic is now complete. Select Add > Wire or click the Add Wire icon and add a hanging net to the four data pins of each of the five counters.1 In-Depth Tutorial . Select Increase the name in the Add Net Name options dialog box.R Chapter 3: Schematic-Based Design Note: Each of the wires with identical names are now electrically connected. 4.com ISE 9. In this case. Verify that the schematic does not contain logical errors by running a design rule check (DRC).

xilinx.1 In-Depth Tutorial www. With the time_cnt schematic sheet open. double-click stopwatch. and then Finish to use the wizard defaults. In the Processes window. In the Sources window. and then select time_cnt in the schematic value field. In the top-level schematic. Save the schematic by selecting File > Save. Figure 3-16: 2. Close the time_cnt schematic.com 67 . or by clicking the Save icon in the toolbar. place the symbol that represents the macro on the top-level schematic (stopwatch. 2. To create a symbol that represents the time_cnt schematic using a Project Navigator process: 1. Placing the time_cnt Symbol Next. 2. View and then close the time_cnt symbol. In the Symbol Wizard. Figure 3-17: Add Symbol Icon ISE 9. select Tools > Symbol Wizard.Design Entry R Saving the Schematic 1. Save Icon Creating and Placing the time_cnt Symbol The next step is to create a “symbol” that represents the time_cnt macro. click the + beside Design Utilities to expand the hierarchy. then Next again. Click Next. Select the Add Symbol icon. select Using Schematic.sch. The symbol is an instantiation of the macro. you will add the symbol to a top-level schematic of the stopwatch design. Double-click Create Schematic Symbol. 3. After you create a symbol for time_cnt. select time_cnt. 2. 1.sch).sch to open the schematic. In the Sources window. then Next. Creating the time_cnt symbol You can create a symbol using either a Project Navigator process or a Tools menu command. the symbol of the time_cnt macro will be connected to other components in a later section in this chapter. To create a symbol that represents the time_cnt schematic using a Tools menu command: 1. 3.

such as Fast Carry Logic. Leave Input and Output options as Non Registered. 6. Select Distributed Memory Generator. 3. Note: Do not worry about connecting nets to the input pins of the time_cnt symbol. This customization GUI enables you to customize the memory to the design specifications. and IO interface cores. 68 www. select Project > New Source. then click Next and click Finish to open the Distributed Memory Generator customization GUI. 5. 5. 4. SRL16s. Click Next. communications. Double-click Memories & Storage Elements.Defines the number of values to be stored Data Width: 20 .R Chapter 3: Schematic-Based Design 3. you will create a CORE Generator module called timer_preset.xilinx. select the local symbols library (c:\xilinx\ISEexamples\wtut_sc). In the Symbol Browser. and is updated as the cursor is moved around the schematic. and then select the newly created time_cnt symbol.Defines the width of the output bus. You will do this after adding other components to the stopwatch schematic.com ISE 9.1 In-Depth Tutorial . In this section. The module is used to store a set of 64 values to load into the timer. This should be close to grid position [1612. Component Name: timer_preset . 4. Type timer_preset in the File name field. 2. Save the changes and close stopwatch.Defines the name of the module. and distributed and block RAM. Place the time_cnt symbol in the schematic so that the output pins line up with the five buses driving inputs to the lcd_control component. Creating a CORE Generator Module CORE Generator is a graphical interactive design tool that enables you to create high-level modules such as memory elements.1728]. Depth: 64 . then double-click RAMs & ROMs. Grid position is shown at the bottom right corner of the Project Navigator window. Memory Type: ROM Click Next. In Project Navigator. math functions. You can customize and pre-optimize the modules to take advantage of the inherent architectural features of the Xilinx FPGA architectures. Fill in the Distributed Memory Generator customization GUI with the following settings: ♦ ♦ ♦ ♦ ♦ ♦ 7. Creating a CORE Generator Module To create a CORE Generator module: 1. Click Next. Select IP (Coregen & Architecture Wizard).sch.

vhd or timer_preset.v These are HDL wrapper files for the core and are used only for simulation.Distributed Memory Generator Customization GUI Check that only the following pins are used (used pins are highlighted on the symbol on the left side of the customization GUI): ♦ ♦ a[5:0] spo[19:0] 9. Figure 3-18: 8. timer_preset.xilinx.xco This file stores the configuration information for the timer_preset module and is used as a project source. ♦ timer_preset. The module is created and automatically added to the project library. Some of these files are: ♦ ♦ ♦ ♦ timer_preset. Note: A number of files are added to the project directory.coe.sym This file is a schematic symbol file. timer_preset.com 69 . CORE Generator .1 In-Depth Tutorial www. Click Finish. timer_preset.mif This file provides the initialization values of the ROM for simulation.Design Entry R ♦ Coefficients File: Click the Browse button and select definition1_times. ISE 9.ngc This file is the netlist that is used during the Translate phase of implementation.

The output expressions for each state are found in the circles representing the states. synthesize the module into a macro and place it on the stopwatch schematic. To skip this section. or ABEL. Transition conditions and state actions are typed into the diagram using language independent syntax.dia file to the project by selecting Project > Add Source and selecting statmach. A completed VHDL and Verilog file for the State Machine diagram in this section has been provided for you in the wtut_sc\wtut_sc_completed directory. you can graphically create finite state machines that include states. then proceed to “Creating the State Machine Symbol. you will complete the diagram.R Chapter 3: Schematic-Based Design Creating a State Machine Module With the State Diagram Editor. The State Diagram Editor then exports the diagram to either VHDL. 70 www. For this tutorial. In the incomplete state machine diagram below: • • • • The circles represent the various states. and state transition conditions.dia.” To open the partially complete diagram. The transition conditions and the state actions are written in language-independent syntax and are then exported to Verilog. first add the statmach. VHDL. The black expressions are the transition conditions. a partially complete state machine diagram is provided. inputs/outputs.dia in the Sources tab.vhd from the c:\xilinx\ISEexamples\stut_sc\wtut_sc_completed directory to the c:\xilinx\ISEexamples\stut_sc directory. Then.1 In-Depth Tutorial . Verilog or ABEL code. copy either statmach. The resulting HDL file is finally synthesized to create a netlist and a macro symbol is created for you to place on a schematic sheet. The State Diagram Editor is launched with the partially completed state machine diagram. defining how you move between states.com ISE 9. In the next section.xilinx.v or stamach. double-click statmach. Note: The State Diagram Editor is only available for Windows operating systems.

com 71 . Click the mouse to place the state bubble. ISE 9. add the remaining states. actions. Place the new state on the left-hand side of the diagram.xilinx.Design Entry R Figure 3-19: Incomplete State Machine Diagram In the following section. Adding New States Complete the state machine by adding a new state called clear.1 In-Depth Tutorial www. transitions. 3. Figure 3-20: Add State Icon The state bubble is now attached to the cursor. 2. as shown in Figure 3-21. Click the Add State icon in the vertical toolbar. To do so: 1. and a reset condition to complete the state machine.

1. and change the name of the state to clear. You will add a transition from the clear state to the zero state in the following steps. click one of the four squares surrounding the bubble and drag it in the direction you wish to stretch the bubble. Figure 3-22: 2.com ISE 9. Transitions are represented by arrows in the editor. 3.xilinx. Note: The name of the state is for your use only and does not affect synthesis. Add Transitions Icon Click on the clear state to start the transition. Click the Add Transition icon in the vertical toolbar.1 In-Depth Tutorial . Adding a Transition A transition defines the movement between states of the state machine. To change the shape of the state bubble. 72 www. there is no transition condition associated with it. Figure 3-21: 4. Because this transition is unconditional. 5. Any name is fine. STATE0. Click OK.R Chapter 3: Schematic-Based Design The state is given the default name. Click on the zero state to complete the transition arrow. Adding the CLEAR State Double-click STATE0 in the state bubble.

com 73 . Figure 3-23: 5. click and drag it in any directory. Figure 3-24: Select Objects Icon Adding a State Action A state action dictates how the outputs should behave in a given state.xilinx. To manipulate the arrow’s shape. Double-click the clear state. You will add a state action to the clear state to drive the RST output to 1. Adding State Transition Click the Select Objects (or Pointer) icon in the vertical toolbar to exit the Add Transition mode.Design Entry R 4. To add a state action: 1. ISE 9.1 In-Depth Tutorial www.

enter the following values: DOUT = rst.1 In-Depth Tutorial . CONSTANT = ‘1’. 4.R Chapter 3: Schematic-Based Design The Edit State dialog box opens and you can begin to create the desired outputs. Figure 3-25: 2. Select the Output Wizard button.com ISE 9.xilinx. The output is now added to the state. Edit State Dialog Box In the Logic Wizard. 3. Figure 3-26: Adding State Outputs 74 www. Click OK to enter each individual value. 5. Click OK to exit the Edit State dialog box.

Click OK. Figure 3-28: 5.com 75 . add a reset condition that sends the state machine to the clear state whenever either the reset signal is asserted high.Design Entry R Adding a State Machine Reset Condition Using the State Machine Reset feature.xilinx. Adding a Reset Condition Verify that ‘state_reset’ is added as the reset condition. To generate the HDL file. Select Options > Configuration. Click the Add Reset icon in the vertical toolbar. and click the state bubble. If another value is listed for the reset condition. In the Language Vendor section select Xilinx XST. 1. The state machine initializes to this specified state and enters the specified state whenever the reset condition is met. specify a reset condition for the state machine. Figure 3-27: 2. The cursor is automatically attached to the transition arrow for this reset. 2. ISE 9. 4. or the DCM_lock signal is de-asserted low. In this design. 3. 6. double-click on the value and edit the condition appropriately. Click OK. A Results window is displayed listing the compile status. When you see the question being asked: “Should this reset be asynchronous(Yes) or synchronous (No)?” Answer Yes. 4. Add Reset Icon Click the diagram near the clear state. 3. select the Generate HDL icon in the toolbar. select either Verilog or VHDL as desired. as shown in the diagram below. Move the cursor to the clear state. 5.1 In-Depth Tutorial www. In the Language section. Creating the State Machine HDL output file 1.

v. Save your changes by selecting File > Save. A browser opens displaying the generated HDL file.R Chapter 3: Schematic-Based Design 7. 9. 4. 3. Examine the code and then close the browser. The macro symbol is added to the project library. 2. In this section. In the New Source dialog box. you will create a macro symbol for the state machine that you can place on the stopwatch schematic. Select Project > New Source. Select statmach. In the Sources tab.v or statmach. 76 www. In Project Navigator. Double-click Create Schematic Symbol. and type the filename dcm1. 8.xilinx.com ISE 9.1 In-Depth Tutorial . Creating a DCM Module The Clocking Wizard. click the + beside Design Utilities to expand the hierarchy. select Project > Add Source. select the IP (Coregen & Architecture Wizard) source type. Close the State Diagram Editor. 1. The file statmach. select statmach. a Xilinx Architecture Wizard. Using the Clocking Wizard Create the dcm1 module as follows: 1. 3. 5. you will create a basic DCM module with CLK0 feedback and duty-cycle correction. Click Next. Creating the State Machine Symbol In this section.v(hd) is added to the project in Project Navigator. In the Processes tab. 2.vhd or statmach. enables you to graphically select Digital Clock Manager (DCM) features that you wish to use.vhd (this is the HDL file generated by State Diagram Editor) and click Open.

In the Select IP dialog box. 7. Select CLKFX port. 9.Design Entry R 4. 8. Spartan-3A > Single DCM SP. Figure 3-29: 5. Selecting Single DCM Core Type Click Next. Type 50 and select MHz for the Input Clock Frequency.1 In-Depth Tutorial www.xilinx. then click Finish. 6. Single Feedback Source: Internal Feedback Value: 1X Use Duty Cycle Correction: Selected ISE 9. Verify the following settings: ♦ ♦ ♦ ♦ ♦ Phase Shift: NONE CLKIN Source: External. Verify that RST. select FPGA Features and Design > Clocking > Spartan3E. CLK0 and LOCKED ports are selected. The Clocking Wizard is launched.com 77 .

Select Use output frequency and type 26. Click Next twice to advance to the Clock Frequency Synthesizer page. This symbol will be added to the toplevel schematic (stopwatch. 2. 12.2144 in the box and select MHz. select dcm1. and then click Finish. create a symbol representing the dcm1 macro.sch) later in the tutorial. Creating the dcm1 Symbol Next.R Chapter 3: Schematic-Based Design Figure 3-30: Xilinx Clocking Wizard .com ISE 9.2144Mhz ) ⁄ 2 18 = 100Hz 15. double-click Create Schematic Symbol.xaw. 78 www.xilinx. In the Processes tab. Select the Wait for DCM Lock before DONE Signal goes high option. in the Sources tab.1 In-Depth Tutorial . 11. 13. Click the Advanced button. ( 26. 1.xaw file is created and added to the list of project source files in the Sources tab. Click OK. 14. The dcm1. In Project Navigator.General Setup 10. Click Next.

The resulting HDL file is then modified in the ISE Text Editor. The HDL code is connected to your top-level schematic design through instantiation and compiled with the rest of the design. Select Project > New Source. To create the source file: 1. In the first three Port Name fields type sig_in. You will author a new HDL module. type debounce. Enter two input ports named sig_in and clk and an output port named sig_out for the debounce component as follows: a. 7. 2. A description of the module displays. Click Next to complete the Wizard session. The Verilog HDL file is displayed in Figure 3-33. Click Next. mode and lap_load inputs.xilinx. ISE 9. clk and sig_out. 4. 3. Select VHDL Module or Verilog Module.com 79 . c. Set the Direction field to input for sig_in and clk and to output for sig_out. you can easily create modules from HDL code. Using the New Source Wizard and ISE Text Editor In this section. Leave the Bus designation boxes unchecked. you create a file using the New Source wizard.1 In-Depth Tutorial www. b. Click Finish to open the empty HDL file in the ISE Text Editor.Design Entry R Creating an HDL-Based Module With ISE. The VHDL file is displayed in Figure 3-32. In the File Name field. A dialog box opens in which you specify the type of source you want to create. 5. specifying the name and ports of the component. Figure 3-31: New Source Wizard for Verilog 6. This macro will be used to debounce the strtstop.

R Chapter 3: Schematic-Based Design Figure 3-32: VHDL File in ISE Text Editor Figure 3-33: Verilog File in ISE Text Editor 80 www.xilinx.com ISE 9.1 In-Depth Tutorial .

comments in green. expand the Misc hierarchy. Synthesis Constructs and User Templates. 2. expand the Coding Examples hierarchy. expand the Synthesis Constructs hierarchy. Note: You can add your own templates to the Language Templates for components or constructs that you use often. You will use the Debounce Circuit template for this exercise.Design Entry R In the ISE Text Editor. multiplexers. To invoke the Language Templates and select the template for this tutorial: 1. ISE 9. and primitives. the contents display in the right pane. Use the appropriate template for the language you are using. click the + next to the section.com 81 . select Edit > Language Templates.1 In-Depth Tutorial www. Under either the VHDL or Verilog hierarchy. Debounce Circuit. To expand the view of any of these sections. and some of the basic file structure is already in place. Using the Language Templates The ISE Language Templates include HDL constructs and synthesis templates which represent commonly used logic components. and values are black. D flip-flops. From Project Navigator. such as counters. the ports are already declared in the HDL file. When the template is selected in the hierarchy. Click any of the listed templates to view the template contents in the right pane. Keywords are displayed in blue. and select the template called One-Shot. Simulation Constructs. Device Primitive Instantiation. The file is color-coded to enhance readability and help you recognize typographical errors. Each HDL language in the Language Templates is divided into five sections: Common Constructs.xilinx.

1 In-Depth Tutorial . Refer to “Working with Language Templates” in the ISE Help for additional usability options. Remove the reset logic (not used in this design) by deleting the three lines beginning with if and ending with else.R Chapter 3: Schematic-Based Design Figure 3-34: Language Templates Adding a Language Template to Your File You will now use the drag and drop method for adding templates to your HDL file. To add the template to your HDL file using the drag and drop method: 1.vhd file under the architecture begin statement. Change <reg_name> to q in all six locations. 2. 4. or into the debounce.xilinx. 3. (Verilog only) Complete the Verilog module by doing the following: a.v file under the module and pin declarations. 82 www. Close the Language Templates window. Click and drag the Debounce Circuit name from the Language Template topology into the debounce.com ISE 9. b. Select Window > Tile Vertically to show both the HDL file and the Language Templates window.

Note: Do not worry about drawing the wires to connect the symbols.1 In-Depth Tutorial www. 9. In the Processes tab. select debounce. double-click Check Syntax. 2. Change <clock> to clk.xilinx. You now have complete and functional HDL code. Change <clock> to clk. ISE 9. c.. 1. Select debounce in the Sources tab. timer_preset. Double-click Create Schematic Symbol. Select Add > Symbol or click the Add Symbol icon from the Tools toolbar. 2. <input> to sig_in. View the list of available library components in the Symbol Browser. You will connect components in the schematic later in the tutorial. In the Processes tab. double-click stopwatch. Save the file by selecting File > Save. dcm1 and debounce Symbols You can now place the statmach. In the Sources tab.v. timer_preset. and Q_OUT to sig_out. In Project Navigator. lines. Locate the project-specific macros by selecting the project directory name in the Categories window.vhd or debounce. 3. 7. 3. Placing the statmach. (VHDL only) Complete the VHDL module by doing the following: b.. D_IN to sig_in.sch).sch. as shown in Figure 3-36.Design Entry R c.com 83 . dcm1. The schematic file opens in the Workspace. create the schematic symbol representing the debounce HDL in Project Navigator. Figure 3-35: Add Symbol Icon This opens the Symbol Browser to the left of the Schematic Editor. Select the appropriate symbol. click the + beside Design Utilities to expand the hierarchy. Creating the debounce Symbol Next. 6. and ending with else and delete one of the end if. which displays the libraries and their corresponding components. You are now ready to place the debounce symbol on the stopwatch schematic. 8. 5. Close the ISE Text Editor. Remove the reset logic (not used in this design) by deleting the five lines beginning with if (<reset>. and <output> to sig_out. and debounce symbols on the stopwatch schematic (stopwatch. Move the line beginning with the word signal so that it is between the architecture and begin keywords. 4. a. and add it to the stopwatch schematic in the approximate location. 1.

1 In-Depth Tutorial .xilinx. change the names of the added symbol instances as follows. Figure 3-36: Placing Design Macros Changing Instance Names When a symbol is placed on a schematic sheet it is given a unique instance name beginning with the prefix XLXI_. Repeat steps 1 and 2 to change the following symbol instance names. 2. 1. Save the schematic.com ISE 9.R Chapter 3: Schematic-Based Design 5. To help make the hierarchy more readable in the Project Navigator Sources window. • • • Right-click on the dcm1 symbol instance and select Object Properties from the rightclick menu Change the value of the InstName field to dcm_inst and then click OK. 84 www. Name the statmach instance timer_state. Name the top debounce instance lap_load_debounce Name the middle debounce instance mode_debounce.

You can also right-click in an open space of the schematic and select Pop to Calling Schematic. You can also right-click the macro and select Symbol > Push into Symbol. the appropriate text editor or customization GUI will open and be ready to edit the file. Figure 3-37: Hierarchy Push Icon In the time_cnt schematic. If a user pushes into a symbol that has an underlying HDL or IP core file.” which enables you to focus in on a lower-level of the schematic hierarchy to view the underlying file.com 85 . 2.xilinx.1 In-Depth Tutorial www. stopwatch. When the synthesis tool synthesizes the top-level schematic’s HDL. clk. add five input pins to the stopwatch schematic: reset. Name the time_cnt instance timer_cnt. perform a hierarchy “push down. the I/O markers are replaced with the appropriate pads and buffers. lap_load. ISE 9. Click time_cnt symbol in the schematic.Design Entry R • • • Name the bottom debounce instance strtstop_debounce. After examining the macro. mode and strtstop. return to the top-level schematic by selecting View > Pop to Calling Schematic. which is a schematic-based macro created earlier in this tutorial. To push down into time_cnt from the top-level. and examine its components. Figure 3-38: Hierarchy Pop Icon Specifying Device Inputs/Outputs Use the I/O marker to specify device I/O on a schematic sheet. or select the Hierarchy Pop icon when nothing in the schematic is selected. Push into any of the counter blocks by selecting the block and clicking on the Hierarchy Push icon. Adding Input Pins Next. Push down into the time_cnt macro. To add these components: • Draw a hanging wire to the two inputs of dcm1 and to the sig_in pin of each debounce symbol Refer to “Drawing Wires” for detailed instructions. and select the Hierarchy Push icon. Hierarchy Push/Pop First. This process may be repeated until the schematic page contains only Xilinx primitive components. Name the timer_preset instance t_preset. All of the Schematic Editor schematics are netlisted to VHDL or Verilog and then synthesized by the synthesis tool of choice. you see five counter blocks. schematic: 1.

R Chapter 3: Schematic-Based Design Adding I/O Markers and Net Names It is important to label nets and buses for several reasons: • • • It aids in debugging and simulation. 2. as illustrated in Figure 3-39. Click and drag a box around the name of the five labeled nets. to place an input port on each net. To label the reset net: 1. as you can more easily trace nets back to your original design. 6. 5. Type reset into the Name box. 3. Figure 3-39: Adding I/O Markers to Labeled Nets 86 www. Naming nets also enhances readability and aids in documenting your design. as illustrated in Figure 3-39. Repeat Steps 1 through 3 for the clk. Label the five input nets you just drew. lap_load. Select Add > Net Name.xilinx. mode. add the I/O marker. Any nets that remain unnamed in the design will be given generated names that will mean nothing to you later in the implementation process. 4. Select Add > I/O Marker. Once all of the nets have been labeled.1 In-Depth Tutorial . Place the name on the leftmost end of the net.com ISE 9. and strtstop pins. Refer to the completed schematic below. The net name is now attached to the cursor.

For this tutorial.xilinx. This will display the LOC attribute on the schematic above the clk net.Design Entry R Assigning Pin Locations Xilinx recommends that you let the automatic placement and routing (PAR) program define the pinout of your design. Enter LOC for the Attribute Name and E12 for the Attribute Value. Click OK to return to the Object Properties dialog box. Click OK to close the Object properties window. and click Edit Traits. The following steps guide you through the process of completing the schematic.com 87 .1 In-Depth Tutorial www. 4. the example pin assignments will not adversely affect the ability of PAR to place and route the design. it may be necessary at some point to lock the pinout of a design so that it can be integrated into a Printed Circuit Board (PCB). Assigning Pin Locations To make the LOC attribute visible. and labeling nets appropriately. Assign a LOC parameter to the output nets on the stopwatch schematic. Click the New button under Net Attributes to add a new property. the inputs and outputs will be locked to specific pins in order to place and download the design to the Spartan-3A demo board. 6. Pre-assigning locations to the pins can sometimes degrade the performance of the place-and-route tools. Each of the actions referred ISE 9. The remaining pin location constraints will be added in “Using the Constraints Editor” and “Using the Floorplan Editor” of Chapter 5. Note: To turn off the Location constraint without deleting it. select the Add button adjacent to the LOC attribute in the Attribute window. as follows: 1. select the loc attribute. In the Net Attribute Visibility window. 2. Because the tutorial stopwatch design is simple and timing is not critical. adding any additional necessary logic. “Design Implementation”. However. 3. You may also want to use the completed schematic shown below to complete the schematic. Right-click on the clk net and select Object Properties from the right-click menu. Figure 3-40: 5. select Add and then OK. Select VHDL or Verilog and select Ignore this attribute. The above procedure constrains clk to pin E12. Notice that the LOC property has already been added to the sf_d(7:0) bus. Completing the Schematic Complete the schematic by wiring the components you have created and placed.

1 In-Depth Tutorial .” Draw a hanging wire to the clk input of both the time_cnt and statmach macros. Please see the earlier sections for detailed instructions.”) 88 www. (See “Drawing Wires.xilinx.com ISE 9. Draw a hanging wire to the LOCKED_OUT pin of DCM1 and name the wire locked. See “Drawing Wires” and “Adding Net Names.R Chapter 3: Schematic-Based Design to in this section has been discussed in detail in earlier sections of the tutorial. 2. Figure 3-41: Completed Stopwatch Schematic To complete the schematic diagram: 1.

Proceed to Chapter 5.” Name the nets lap and mode_control respectively.” to perform a pre-synthesis simulation of this design. Draw hanging wires from the load output of the statmach macro and the load input of the time_cnt macro. Draw a wire to connect the clk inputs of the three debounce macros and name the wire clk_26214k.” Notice how the wire is automatically converted to a bus. Draw a hanging wire to the clken output of the statmach component and another hanging wire to the ce pin of the time_cnt component.” Label both wires rst_int.com 89 . Label the nets ll_debounced. and strtstop_debounced. Draw a wire from the bus output of the timer_preset to the q(19:0) input of the time_cnt macro. See “Drawing Wires. See “Drawing Wires” and “Adding Net Names. Draw hanging wires from the rst output pin of the statmach macro and the clr pin of the time_cnt macro. even if the net is not physically drawn as a connection in the schematic. Save the design by selecting File > Save. 7.xilinx. “Design Implementation. Draw a hanging wire to the up input time_cnt macro. respectively.” Name the wire mode_control. See “Drawing Wires.Design Entry R 3. See “Drawing Wires. 10. See “Drawing Wires. mode_in and strtstop pin of the statmach macro. You have now completed the schematic design. 9. 4. Name them locked and reset. Draw wires from the lap_trigger and mode outputs of the statmach macro to the lap and mode inputs of the lcd_control macro. 8. mode_debounced. The schematic is now complete.” Name both wires load. To continue with the schematic flow. 12. 11. Name both wires clk_en_int. Draw wires between the sig_out pins of the debounce components and the lap_load. (See “Adding Net Names. Draw a hanging bus on the input of the timer_preset macro and name the bus address(5:0). 6.” to place and route the design.” Add hanging wires to the dcm_lock pin and the reset pin of the statmach macro. do the following: • • Go to Chapter 4. Name both wires clk_100. See “Drawing Wires. ISE 9. 5.”) Note: Remember that nets are logically connected if their names are the same.1 In-Depth Tutorial www. “Behavioral Simulation. This method is used to make the logical connection of clk_100 and several other signals.

R Chapter 3: Schematic-Based Design 90 www.1 In-Depth Tutorial .xilinx.com ISE 9.

The following sections discuss requirements and setup for ModelSim PE. see Chapter 6 of the Synthesis and Simulation Design Guide. In order to simulate with the ISE 9 libraries. This Guide is accessible from within ISE by selecting Help > Software Manuals.com 91 . you will achieve the same results. Older versions may work but are not supported. you must install ModelSim on your computer. For more information about ModelSim PE or SE.0 or later. ModelSim Setup In order to use this tutorial. and for a list of other supported simulators. The examples in this tutorial demonstrate how to use the integrated flow. For additional information about simulation. • • • • • • • “Overview of Behavioral Simulation Flow” “ModelSim Setup” “ISE Simulator Setup” “Getting Started” “Adding an HDL Test Bench” “Behavioral Simulation Using ModelSim” “Behavioral Simulation Using ISE Simulator” Overview of Behavioral Simulation Flow Xilinx® ISE™ provides an integrated flow with the Mentor ModelSim simulator and the Xilinx ISE Simulator that allows simulations to be run from the Xilinx Project Navigator. use ModelSim 6. ISE 9.com/support/sw_manuals/xilinx9/. ModelSim SE. Whether you use the ModelSim simulator or the ISE Simulator with this tutorial.xilinx. ModelSim PE and SE ModelSim PE and ModelSim SE are full versions of ModelSim available for purchase directly from Mentor Graphics.xilinx. and ModelSim XE. and from the web at http://www. please contact Mentor Graphics.R Chapter 4 Behavioral Simulation This chapter contains the following sections.1 In-Depth Tutorial www.

Required Files The behavioral simulation flow requires design files.” Xilinx Simulation Libraries Xilinx simulation libraries are required when a Xilinx primitive or IP core is instantiated in the design.xilinx. please visit: http://www. go to the Download Center page. There are two versions of MXE III available for purchase from Xilinx: a free “starter” version. Design Files (VHDL.” 92 www.htm. Test Bench File In order to simulate the design.1i as the ISE version. Verilog. You may also create your own test bench file. your design includes the required design files. For instructions.” After you have completed one of these chapters. “HDL-Based Design. see “Creating a Test Bench Waveform Using the Waveform Editor.com ISE 9. see the next section. For more information about MXE III including how to purchase the software. Windows XP.xilinx. or Schematic) This chapter assumes that you have completed the design entry tutorial in either Chapter 2. Getting Started The following sections outline the requirements for performing behavioral simulation in this tutorial. and Xilinx simulation libraries. For information on simulation libraries and how to compile them. a test bench file is required to provide stimulus to the design.R Chapter 4: Behavioral Simulation ModelSim Xilinx Edition ModelSim Xilinx Edition III (MXE III) is the Xilinx version of ModelSim which is based on ModelSim PE. and a full version.1 In-Depth Tutorial .jsp?update=mxe_libs ISE Simulator Setup ISE Simulator is automatically installed and set up with the ISE 9. Be sure to select 9.com/ise/optional_prod/mxe. and Red Hat Enterprise Linux 3 or 4 platforms only.1i installer. and is ready for simulation. “Xilinx Simulation Libraries. To obtain the correct MXE III simulation libraries.xilinx. http://www.com/xlnx/xil_sw_updates_home.” or Chapter 3. a test bench file. The ISE Simulator is available on Windows 2000. VHDL and Verilog test bench files are available with the tutorial files. “Schematic-Based Design. The design in this tutorial requires the use of simulation libraries because it contains instantiations of a digital clock manager (DCM) and a CORE Generator™ component.

ini file pointed to by the MODELSIM environment variable. ModelSim searches for a modelsim.Getting Started R Xilinx Simulation Libraries To simulate designs that contain instantiated Xilinx primitives. Mapping Simulation Libraries in the Modelsim. This Guide is accessible from within ISE by selecting Help > Software Manuals. When the models are updated.xilinx.com 93 .ini file to determine the location of the compiled libraries.com/xlnx/xil_sw_updates_home. and from the web at http://www. All other models are updated each time a service pack is installed. and other Xilinx IP cores you must use the Xilinx simulation libraries. These libraries contain models for each component. you must recompile the libraries.jsp?update=mxe_libs. see Chapter 5 of the Synthesis and Simulation Design Guide. ISE 9.ini file: UNISIM = c:\lib\UNISIM Note: The modelsim. CORE Generator components. The modelsim.ini file in the following locations until one is found: • • • The modelsim. if you compiled the UNISIM library to c:\lib\UNISIM. See Chapter 6 of the Synthesis and Simulation Design Guide. the following mapping appears in the modelsim. • • The XilinxCoreLib models are updated each time an IP Update is installed. you must compile the simulation libraries with the updated models. This Guide is accessible from within ISE by selecting Help > Software Manuals. The modelsim.com/support/sw_manuals/xilinx9/. For instance. Xilinx ISE Simulator Updated simulation libraries for the ISE Simulator are precompiled and installed with ISE installations and service packs. ModelSim PE or SE If you are using ModelSim PE or SE.1 In-Depth Tutorial www. or from the web at http://www. Updating the Xilinx Simulation Libraries The Xilinx simulation libraries contain models that are updated on a regular basis.ini file in the directory where ModelSim or MXE is installed. and provide the simulator with the information required to perform simulation. For a detailed description of each library.xilinx.com/support/sw_manuals/xilinx9/. These models reflect the functions of each component. The compiled Xilinx simulation libraries are then available during the simulation of any design.ini File ModelSim uses the modelsim. Download the latest precompiled models from the Download Center at http://www.xilinx.xilinx.ini is not applicable to the ISE Simulator.ini file in the current working directory. ModelSim Xilinx Edition III Updated models for ModelSim Xilinx Edition III (MXE III) are precompiled and available on the Xilinx support website.

ini file with the correct mapping. Note: To create your own test bench file in ISE. or create your own test bench file and add it to your project.ini file in the installation directory is used. Click Open.R Chapter 4: Behavioral Simulation If the MODELSIM environment variable is not set. Adding an HDL Test Bench In order to add an HDL test bench to your design project. ISE recognizes the top-level design file associated with the test bench. 94 www. Open the modelsim.vhd. you can either add a test bench file provided with this tutorial. you can copy the modelsim. add the tutorial VHDL test bench to the project: 1. ModelSim Xilinx Edition III If you are using ModelSim Xilinx Edition III (MXE III). open the modelsim. the modelsim. You must define the test bench in a text editor. 3. select Project > New Source.ini file. 2. While compiling the libraries. Adding Tutorial Test Bench File This section demonstrates how to add pre-existing test bench file to the project.ini file to the working directory and make changes that are specific to that project. and adds the test bench in the correct order. and select either VHDL Test Bench or Verilog Text Fixture in the New Source Wizard. 4.ini file in the directory where MXE III was installed. VHDL Simulation After downloading the file to your project directory. ModelSim PE or SE If you are using ModelSim PE or SE. An empty stimulus file is added to your project. In the Choose Source Type dialog box. and the modelsim. ISE Simulator The modelsim. 5. For future projects.ini file has not been copied to the working directory. select VHDL Test Bench File. Select Project > Add Source. refer to the Development System Reference Guide and use COMPXLIB to compile the libraries.xilinx.com ISE 9. or you can use the MODELSIM environment variable to point to the desired modelsim. Select the test bench file stopwatch_tb. Click OK.ini file is not applicable to the ISE Simulator. A VHDL test bench and Verilog test fixture are provided with this tutorial. All of the Xilinx simulation libraries are already mapped to the proper location.ini file and make sure that the library mappings are correct.1 In-Depth Tutorial . COMPXLIB also updates the modelsim.

select Verilog Test Fixture File. Click OK.com 95 . 3. Select Properties. 3. ISE 9. select Behavioral Simulation in the Sources for field. Select the file stopwatch_tb. ISE recognizes the top-level design file associated with the test fixture. In the Simulator field of the Project Properties dialog box. or Project Navigator cannot find modelsim.1 In-Depth Tutorial www. skip to “Behavioral Simulation Using ISE Simulator. you can perform behavioral simulation on the design using the ModelSim simulator. and perform simulation based on simulation properties. 5. 2. either ModelSim is not selected as the Simulator in the Project Properties dialog box. In the Sources tab. To locate the ModelSim simulator processes: 1. and adds the test fixture in the correct order. 3. In the Sources tab. 2. Select the test bench file (stopwatch_tb). right-click the device line (xc3s700A-4fg484). 2. To simulate with the ISE Simulator. add the tutorial Verilog test fixture to the project: 1.xilinx. ISE enables ModelSim to create the work directory. If the ModelSim Simulator processes do not appear.” Whether you choose to use the ModelSim simulator or the ISE Simulator for this tutorial. 3. To select ModelSim as your project simulator: 1. In the Processes tab. Select Project > Add Source. 2. ISE has full integration with the ModelSim Simulator. Select Edit > Preferences. compile the source files. load the design. To set the ModelSim location: 1. Click Open. click the + beside ModelSim Simulator to expand the process hierarchy. the end result is the same. Behavioral Simulation Using ModelSim Now that you have a test bench in your project. If ModelSim is installed but the processes are not available. 4.exe. the Project Navigator preferences may not be set correctly.Behavioral Simulation Using ModelSim R Verilog Simulation After downloading the file to your project directory.v. In the Choose Source Type dialog box. select the Modelsim type and HDL language combination you are using. Click the + next to ISE General to expand the ISE preferences Click Integrated Tools in the left pane. Locating the Simulation Processes The simulation processes in ISE enable you to run simulation on the design using ModelSim.

ModelSim runs in the background to generate expected results and displays them in the ISE Simulator’s Test Bench Waveform Editor. In the Sources tab. The test bench generated by this process contains output data and self-checking code that can be used to compare the data from later simulation runs. under Model Tech Simulator. This global setting enables you to now see all available properties. 3.exe file. 5. Generate a self-checking HDL test bench This process enables you to generate a self-checking HDL test bench equivalent to a test bench waveform (TBW) file and add the test bench to your project. ISE allows you to set several ModelSim Simulator properties in addition to the simulation netlist properties. and to modify the properties for this tutorial: 1. In the Process Properties dialog box. (Figure 4-1) set the Property display level to Advanced. 96 www.com ISE 9. Note: This process is available only if you have a test bench waveform file from the ISE Simulator’s Test Bench Waveform Editor. If you double-click this process.xilinx. select the test bench file (stopwatch_tb).1 In-Depth Tutorial . Right-click Simulate Behavioral Model. Click the + sign next to ModelSim Simulator to expand the hierarchy in the Processes tab. For example.” Specifying Simulation Properties You will perform a behavioral simulation on the stopwatch design after you have set some process properties for simulation. c:\modeltech_xe\win32xoem\modelsim. See “Creating a Test Bench Waveform Using the Waveform Editor. browse to the location of the modelsim. You can also use this process to update an existing self-checking test bench. Select Properties. To see the behavioral simulation properties.exe The following simulation processes are available: • • Simulate Behavioral Model This process starts the design simulation. 2. 4.R Chapter 4: Behavioral Simulation 4. In the right pane.

ISE automatically adds all the top-level ports to the Wave window. only the DCM signals are monitored to verify that they work correctly. Change the Simulation Run Time to 2000 ns. Adding Signals To view internal signals during the simulation.Behavioral Simulation Using ModelSim R 6. and select Add > Wave > Selected Signals.com 97 .xilinx. ModelSim creates the work directory. compiles the source files. The majority of this design runs at 100 Hz and would take a significant amount of time to simulate. and performs simulation for the time specified. For the purpose of this tutorial. you are ready to run ModelSim. For a detailed description of each property available in the Process Properties dialog box. This is why the counter may seem like it is not working in a short simulation.1 In-Depth Tutorial www. Figure 4-1: Behavioral Simulation Process Properties 7. you must add them to the Wave window. The first outputs to transition after RESET is released are the SF_D and LCD_E control signals at around 33 mS. click Help. There are two basic methods for adding signals to the Simulator Wave window. Click OK. Performing Simulation Once the process properties have been set. Highlight signals in the Signal/Object window. double-click Simulate Behavioral Model. ISE 9. loads the design. Additional signals are displayed in the Signal window based on the selected structure in the Structure window. • • Drag and drop from the Signal/Object window. To start the behavioral simulation.

Figure 4-2: Undock icon To add additional signals in the design hierarchy: 1. click the Undock icon. all the windows are docked by default. you will be adding the DCM signals to the waveform. select the following signals. To undock the windows. Figure 4-3 shows the Structure/Instance window for the Verilog flow. In the Signal/Object window.xilinx. If you are using ModelSim version 6.com ISE 9. 4. 3. The graphics and the layout of the Structure/Instance window for a schematic or VHDL flow may be different.Verilog flow Select dcm1 in the Structure/Instance window.0 or higher. Structure/Instance Window . hold down the Ctrl key. Click and drag CLKIN_IN from the Signal/Object window to the Wave window. ♦ ♦ ♦ ♦ RST_IN CLKFX_OUT CLK0_OUT LOCKED_OUT 98 www. To select multiple signals. In the Structure/Instance window.1 In-Depth Tutorial . In this tutorial. click the + next to uut to expand the hierarchy.R Chapter 4: Behavioral Simulation The following procedure explains how to add additional signals in the design hierarchy. Figure 4-3: 2. The signals listed in the Signal/Object window are updated.

If necessary. Figure 4-4: Waveform After Adding DCM Signals Divider The waveforms have not been drawn for any of the newly added signals. 6. Select Insert Divider. you must rerun the simulation for the desired amount of time. To add a divider called DCM Signals: 1. Right click anywhere in the signal section of the Wave window. 2. Adding Dividers In ModelSim. 3.xilinx. ModelSim records data only for the signals that have been added to the Wave window while the simulation is running. After new signals are added to the Wave window. 5. 4.Behavioral Simulation Using ModelSim R 5. Enter DCM Signals in the Divider Name box. This is because ModelSim did not record the data for these signals. Click the Restart Simulation icon. Figure 4-5: Restart Simulation Icon ISE 9.com 99 . By default. Click OK. Click and drag the newly created divider to above the CLKIN_IN signal. Select Add to Wave > Selected Signals.1 In-Depth Tutorial www. Rerunning Simulation To rerun simulation in ModelSim: 1. Right-click in the Signal/Object window. undock the window and maximize the window for a larger view of the waveform. you can add dividers in the Wave window to make it easier to differentiate the signals. After adding the DCM Signals divider. the waveform will look like Figure 4-4.

R Chapter 4: Behavioral Simulation Figure 4-6: 2. To measure the CLK0_OUT: 1. At the ModelSim command prompt.1 In-Depth Tutorial . The DCM outputs are valid only after the LOCKED_OUT signal is high.xilinx. Figure 4-7: Entering the Run Command The simulation runs for 2000 ns. 3. Restart Dialog Box In the Restart dialog box. 2. ModelSim enables you to add cursors to measure the distance between signals. 3. Analyzing the Signals The DCM signals can be analyzed to verify that they work as expected. Click and drag the second cursor just to the right of the first. The waveforms for the DCM are now visible in the Wave window. therefore. the DCM signals are analyzed only after the LOCKED_OUT signal has gone high.com ISE 9. Select Add > Wave > Cursor twice to add two cursors. Figure 4-8: Find Next Transition Icon 100 www. Click and drag one cursor to the first rising edge transition on the CLK0_OUT signal after the LOCKED_OUT signal has gone high. 4. Press Enter. click Restart. Click the Find Next Transition icon twice to move the cursor to the next rising edge on the CLK0_OUT signal. enter run 2000 ns. The CLK0_OUT needs to be 50 MHz and the CLKFX_OUT should be ~26 MHz. 4.

Click the + beside Xilinx ISE Simulator to expand the process hierarchy. “Behavioral Simulation Using ModelSim.Behavioral Simulation Using ISE Simulator R 5. 2. ISE has full integration with the ISE Simulator.1 In-Depth Tutorial www. 2. “Design Implementation. 6. The measurement should read 20000 ps. ISE 9. select Behavioral Simulation in the Sources for field. compile the source files. follow the steps in Chapter 5. After restarting the simulation. In the Sources tab. select File > Save as. Locating the Simulation Processes The simulation processes in ISE enable you to run simulation on the design using ISE Simulator. 3. select File > Load in the Wave window to load this file. 3. rename the file name from the default wave. which in turn should be the DCM CLK0 output. ISE enables ISE Simulator to create the work directory. To implement the design. The measurement should read 38462 ps. In the Project Properties dialog box.do to dcm_signal. Saving the Simulation The ModelSim simulator enables you to save the signals list in the Wave window after new signals or stimuli are added. Look at the bottom of the waveform for the distance between the two cursors. 3. To save the signals list: 1. Select the test bench file (stopwatch_tb). you can perform behavioral simulation on the design using the ISE Simulator.do. Select Properties. This comes out to approximately 26 MHz. which is the input frequency from the test bench. 2. To select ISE Simulator as your project simulator: 1. Measure CLKFX_OUT using the same steps as above. select ISE Simulator in the Simulator field. In the Sources tab. and perform simulation based on simulation properties. load the design. To locate the ISE Simulator processes: 1. This converts to 50 MHz.” Behavioral Simulation Using ISE Simulator Follow this section of the tutorial if you have skipped the previous section.com 101 .” Now that you have a test bench in your project. right-click the device line (xc3s700A-4fg484). Your behavioral simulation is complete. In the Wave window. Click Save. In the Save Format dialog box. The saved signals list can easily be opened each time the simulation is started.xilinx. and after simulation is rerun.

com ISE 9. ISE allows you to set several ISE Simulator properties in addition to the simulation netlist properties. Click the + sign next to ISE Simulator to expand the hierarchy in the Processes tab. 7. 4. select the test bench file (stopwatch_tb). and to modify the properties for this tutorial: 1. Simulate Behavioral Model This process starts the design simulation. This global setting enables you to now see all available properties. Note: For a detailed description of each property available in the Process Property dialog box. ModelSim runs in the background to generate expected results and displays them in the ISE Simulator’s Test Bench Waveform Editor. 6. You can also use this process to update an existing self-checking test bench. click Help.R Chapter 4: Behavioral Simulation The following simulation processes are available: • • • Check Syntax This process checks for syntax errors in the test bench. Click Apply and click OK. Generate a self-checking HDL test bench This process enables you to generate a self-checking HDL test bench equivalent to a test bench waveform (TBW) file and add the test bench to your project. Change the Simulation Run Time to 2000 ns. In the Process Properties dialog box (Figure 4-9). To see the behavioral simulation properties. 5. 3. Select Properties.xilinx. If you double-click this process. The test bench generated by this process contains output data and self-checking code that can be used to compare the data from later simulation runs. 2. In the Sources tab. set the Property display level to Advanced.” Specifying Simulation Properties You will perform a behavioral simulation on the stopwatch design after you set some process properties for simulation. 102 www. Right-click the Simulate Behavioral Model process. See “Creating a Test Bench Waveform Using the Waveform Editor. Note: This process is available only if you have a test bench waveform file from the ISE Simulator’s Test Bench Waveform Editor.1 In-Depth Tutorial .

2. click the + next to stopwatch_tb to expand the hierarchy. To add additional signals in the design hierarchy: 1. Adding Signals To view signals during the simulation. you are ready to run the ISE Simulator. and performs simulation for the time specified. This is why the counter may seem like it is not working in a short simulation. ISE automatically adds all the top-level ports to the Waveform window. add the DCM signals to the waveform. loads the design.1 In-Depth Tutorial www.com 103 . Additional signals are displayed in the Sim Hierarchy window. In the Sim Hierarchy window. For the purpose of this tutorial. ISE 9. The following procedure explains how to add additional signals in the design hierarchy. Click the + next to uut stopwatch to expand the hierarchy. ISE Simulator creates the work directory.xilinx. double-click Simulate Behavioral Model. you must add them to the Waveform window.Behavioral Simulation Using ISE Simulator R Figure 4-9: Behavioral Simulation Process Properties Performing Simulation Once the process properties have been set. The majority of this design runs at 100 Hz and would take a significant amount of time to simulate. compiles the source files. The first outputs to transition after RESET is released are SF_D and LCD_E at around 33 mS. To start the behavioral simulation. For the purpose of this tutorial. only the DCM signals are monitored to verify that they work correctly.

4. Notice that the waveforms have not been drawn for the newly added signals. The graphics and the layout of the window for a schematic or VHDL flow may be different. Figure 4-11: ISE Simulator Restart Simulation Icon 104 www. Click the + next to dcm1 in the Sim Hierarchy window.R Chapter 4: Behavioral Simulation Figure 4-10 shows the Sim hierarchy window for the Verilog flow.com ISE 9. By default.xilinx. This is because ISE Simulator did not record the data for these signals. Alternatively. you must rerun the simulation for the desired amount of time. Select the following signals: ♦ ♦ ♦ ♦ RST_IN CLKFX_OUT CLK0_OUT LOCKED_OUT To select multiple signals. when new signals are added to the waveform window.1 In-Depth Tutorial . Figure 4-10: Sim Hierarchy Window . 5. ISE Simulator records data only for the signals that have been added to the waveform window while the simulation is running. right click on a selected signal and select Add To Waveform. Drag all the selected signals to the waveform.Verilog flow 3. Therefore. 6. hold down the Ctrl key. Click the Restart Simulation icon. Rerunning Simulation To rerun the simulation in ISE Simulation: 1. Click and drag CLKIN_IN from the Sim Hierarchy window to the Waveform window.

To measure the CLK0_OUT: 1. follow the steps in Chapter 5. 5. The Waveform Editor is a test bench creation tool in ISE.5 ns. 4. which in turn is the DCM CLK0 output.xilinx. Creating a Test Bench Waveform Source In this tutorial. Figure 4-12: 3. Click the Measure Marker icon. This converts to 50 MHz. 6. “Design Implementation. Your behavioral simulation is complete. which is the input frequency from the test bench. zoom in on the waveform. If necessary. The measurement should read 38. In the New Source Wizard. The Waveform Editor can be used to generate stimuli for top-level designs as well. Click and drag the other end of the marker to the next rising edge. ISE 9. 3. Select Project > New Source. The DCM outputs are valid only after the LOCKED_OUT signal is high. This equals approximately 26 MHz. It is not necessary to follow this section if you have added the tutorial test bench to the project already. The measurement should read 20.1 In-Depth Tutorial www. the DCM signals are analyzed only after the LOCKED_OUT signal has gone high. 4. and to generate a VHDL test bench or Verilog test fixture. The waveforms for the DCM are now visible in the Waveform window. At the ISE Simulator command prompt in the Sim Console.Behavioral Simulation Using ISE Simulator R 2. enter run 2000 ns and press Enter.” Creating a Test Bench Waveform Using the Waveform Editor This section demonstrates how to use the Waveform Editor. Measure Marker Icon Place the marker on the first rising edge transition on the CLK0_OUT signal after the LOCKED_OUT signal has gone high. create the test bench waveform for a sub-module only. You can use the Waveform Editor to graphically enter stimuli. Type time_cnt_tb. The simulation runs for 2000 ns. Look at the top of the waveform for the distance between the marker. Measure CLKFX_OUT using the same steps as above. To create a test bench with the ISE Simulator Waveform Editor: 1. therefore. Select time_cnt in the Sources tab.com 105 . ISE Simulator can add markers to measure the distance between signals. Analyzing the Signals Now the DCM signals can be analyzed to verify that they work as expected. To implement the design. The CLK0_OUT should be 50 MHz and the CLKFX_OUT should be ~26 MHz.0 ns. 2. 2. select Test Bench Waveform as the source type.

7. Click Next. 8. The Input Setup Time field defines when inputs must be valid. The Clock Time High and Clock Time Low fields together define the clock period for which the design must operate. 10. The Initialize Timing dialog box displays. Change the Initial Length of Test Bench to 3000. Click Finish.1 In-Depth Tutorial . and enables you to specify the timing parameters used during simulation. Figure 4-13: Waveform Editor . the time_cnt file is the default source file because it is selected in the Sources tab (step 1). 11. 6.Initialize Timing Dialog Box 106 www.R Chapter 4: Behavioral Simulation 5. Select the GSR (FPGA) from the Global Signals section. Click Finish.xilinx. The Waveform Editor opens in ISE. The Output Valid Delay field defines the time after active clock edge when the outputs must be valid.com ISE 9. Note: In the Select dialog box. Click Next. fill in the fields as follows: ♦ ♦ ♦ ♦ Clock Time High: 10 Clock Time Low: 10 Input Setup Time: 5 Output Valid Delay: 5 9. In the Initialize Timing dialog box.

The new test bench waveform source (time_cnt_tb. Click the CE cell at time 110 ns to set it high (CE is active high). you can apply a transition (high/low). Double-click Generate Self-Checking Test Bench in the Process tab.tbw in the Sources tab. ISE 9. Click the CLR cell at time 230 ns to set it low.1 In-Depth Tutorial www. in the blue cell.com 107 . 3. 5. The width of this cell is determined by the Input setup delay and the Output valid delay. Enter the following input stimuli: 1.tbw) is automatically added to the project. Applying Stimulus In the Waveform Editor.Behavioral Simulation Using ISE Simulator R The ISE Simulator’s Waveform Editor View opens in ISE. A test bench containing output data and self checking code is generated and added to the project. The created test bench can be used to compare data from later simulation. Click the CLR cell at time 150 ns to set it high. Figure 4-14: 4. Select time_cnt_tb. Applying Stimulus in the Waveform Editor View Click the Save icon in the toolbar. 6. 2.xilinx.

com ISE 9.1 In-Depth Tutorial .xilinx.R Chapter 4: Behavioral Simulation 108 www.

The front-end design has already been compiled in an EDA interface tool. This chapter is the first in the “Implementation-only Flow” and is an important chapter for the “HDL Design Flow” and the “Schematic Design Flow”. and generating a BIT file for your design. see Chapter 2.” In this chapter. you will be passing an input netlist (EDN. mapping.xilinx. For details about compiling the design.1 In-Depth Tutorial www. “HDL-Based Design” or Chapter 3. and you will be incorporating placement constraints through a User Constraints File (UCF).R Chapter 5 Design Implementation This chapter contains the following sections. You will add timing constraints later through the Floorplan Editor. NGC) from the front-end tool to the back-end Design Implementation tools.com 109 . placing. ISE 9. • • • • • • • • • • • • • • • • • “Overview of Design Implementation” “Getting Started” “Specifying Options” “Creating Partitions” “Creating Timing Constraints” “Translating the Design” “Using the Constraints Editor” “Using the Floorplan Editor” “Mapping the Design” “Using Timing Analysis to Evaluate Block Delays After Mapping” “Placing and Routing the Design” “Using FPGA Editor to Verify the Place and Route” “Evaluating Post-Layout Timing” “Changing HDL with Partition” “Creating Configuration Data” “Creating a PROM File with iMPACT” “Command Line Implementation” Overview of Design Implementation Design Implementation is the process of translating. “Schematic-Based Design. The Design Implementation tools are embedded in the ISE™ software for easy access and project management. This chapter demonstrates the ISE Implementation flow. routing.

1. stopwatch. There are five inputs to the system: CLK. Click Next.com ISE 9. If you do not have a stopwatch. create a project in ISE and then add the downloaded source files to the project. Required Tutorial Files File Name stopwatch. Select Project > New Source. Click Next.ucf Description Input netlist file (EDIF) Table 5-1: Timer netlist file (NGC) User Constraints File 110 www.htm.edn.ngc stopwatch.xilinx. LAP_LOAD. 6. RESET. and copy the pre-synthesized tutorial files (see Table 5-1) to your newly created working directory. 5. Starting from Design Implementation If you are beginning the tutorial from this chapter. 7. you are now ready to begin this chapter. Type stopwatch.ucf as the file name. select the top-level source file stopwatch.R Chapter 5: Design Implementation Getting Started The tutorial design emulates a runner’s stopwatch with actual and lap times.com/support/techsup/tutorials/tutorial9. you will need to download the presynthesized design files provided on the Xilinx® web-site. MODE.ucf file in your project. Skip to the “Specifying Options” section. 3. 4. Create an empty working directory named Watch.edf or stopwatch. 8.xilinx.ngc timer_preset. and SRTSTP. you have created a project. Select stopwatch from the list. This system generates a traditional stopwatch with lap times and a traditional timer on a LCD display. and an EDIF netlist file. Continuing from Design Entry If you have followed the tutorial using either the HDL Design flow or the Schematic Design flow. Select Implementation Constraints File. Go to http://www. Click Finish.1 In-Depth Tutorial . In the Sources tab. 2. design entry source files. With a UCF in the project. create one as follows: 1. 2.

Change Report Type to Verbose Report. select Start > Programs > Xilinx ISE 9. Click the Post-Map Static Timing Report Properties category. stopwatch. Select EDIF for the top_level SourceType.edn for the Input Design file. Specifying Options This section describes how to set some properties for design implementation. c. b. Select Properties from the right-click menu.xilinx. On a PC. This enables the design to be implemented.Specifying Options R 3. i. Select stopwatch. Place and Route. Select File > New Project. 6. The implementation properties control how the software maps. b. In the Sources tab. select the stopwatch top-level file. Click Next. Select stopwatch. select the top-level module.ngc file into the EDIF_Flow directory. 5. Click the Post-Place & Route Static Timing Report Properties category. 3.1 In-Depth Tutorial www.com 111 . 7. Copy the timer_preset. d. 2.1i > Project Navigator. This global setting enables you to see all available properties. Map. and Timing Report properties. Ensure that you have set the Property display level to Advanced. The Process Properties dialog box provides access to the Translate. To set the implementation property options for this tutorial: 1.edn. Type EDIF_Flow for the Project Name. Change Report Type to Verbose Report. j. Click Next. f. right-click the Implement Design process. a. ISE 9.ucf for the Constraints file. Select the following: Click Next. In the Sources tab. This setting is in the lower.edf or stopwatch. Open ISE. In the Processes tab. e. Click Finish. On a workstation. 4. h. 8. k. right-hand corner of the dialog box. You will notice a series of categories. Spartan3a for the Device Family xc3s700a for the Device -4 for the Speed Grade. This report will be generated after the Map process is completed. and optimizes a design. Create a new project and add the EDIF netlist as follows: a. fg484 for the Package 4. Simulation. places. enter ise &. routes. g. each contains properties for a different aspect of design implementation.

com ISE 9. Click the Place & Route Properties category. Change the Place & Route Effort Level (Overall) to High. 112 www.R Chapter 5: Design Implementation This report will be generated after Place and Route is completed. Figure 5-1: Post-Place & Route Static Timing Report Properties 9.1 In-Depth Tutorial . 10.xilinx.

A module with multiple instances can have multiple partitions—a partition on each instance. and logic can be at the top level partition. the partition is set on the entity architecture. such as effort levels on implementation tools. The top level of the HDL design has a default partition.xilinx. Partitions automatically detect input source changes. Figure 5-2: Place & Route Properties 11. Please proceed to the next section. If you are doing the EDIF flow. To enable partitions for this design: ISE 9.com 113 . you will not get the option to create Partitions in Project Navigator. Partitions do not need ranges for implementation re-use. and only the effected partitions are re-implemented. Click OK to exit the Process Properties dialog box. including HDL changes and certain constraint changes. the partition is set on the module instance and for VHDL. The creation of Partitions was done through the synthesis tool.Creating Partitions R This option increases the overall effort level of Place and Route during implementation.1 In-Depth Tutorial www. In Verilog. Partitions also detect command line changes. Creating Partitions A partition is created for an instance in your logical design to indicate that the implementation for that instance should be reused when possible. Partitions can be nested hierarchically and be defined on any HDL module instance in the design.

select lcd_cntrl_inst module and right-click on it. The preserve status can be changed to Routing. In the Sources tab. or Synthesis.1 In-Depth Tutorial . To launch the Constraints Editor: 1.1i there is a known issue that will not allow MAP to complete a second iteration if a Partition is placed on a schematic module. 2. Repeat steps 1 and 2 for the timer_state module. Repeat steps 1 and 2 for the timer_inst module in VHDL and Verilog designs only. expand the User Constraints hierarchy. Note: In ISE 9. In the Sources tab. To do this.R Chapter 5: Design Implementation 1. Creating Timing Constraints The User Constraints File (UCF) provides a mechanism for constraining a logical design without returning to the design entry tools. Figure 5-3: New Partitions on LCD_CNTRL_INST module The Preserve status is set to inherit. The Constraints Editor and Floorplan Editor are graphical tools that enable you to enter timing and pin location constraints. right click on a partitioned source file and select Partition Properties. select Stopwatch In the Processes tab. which gets the status from the top level partition. you must understand the exact syntax needed to define constraints. 3. Placement. 114 www. 4. 2. However. without the design entry tools. The top level partition is set to routing by default.com ISE 9.xilinx. Select New Partition from the menu.

Adds constraints from the User Constraints File (UCF) to the merged netlist. you set your options first. which is discussed in the following section. the NGDBuild program performs the following functions: • Converts input design netlists and writes results to a single merged NGD netlist. Double-click Create Timing Constraints. The ISE tools use the settings that you specified in the Process Properties dialog box.1 In-Depth Tutorial www. one step at a time. Figure 5-4: Create Timing Constraints Process This automatically runs the Translate step. This gives you complete control over how a design is processed. Typically. • • ISE 9. Translating the Design ISE manages the files created during implementation. This tutorial illustrates the implementation.xilinx. The merged netlist describes the logic in the design as well as any location and timing constraints.com 115 . Performs timing specification and logical design rule checks.Translating the Design R 3. Then the Constraints Editor opens. During translation. You then run through the entire flow by double-clicking Implement Design.

an NCD (Native Circuit Description) file. Global OFFSET OUT. and enables you to define the associated period. when the NGD file is opened. In the following section. a PERIOD.R Chapter 5: Design Implementation Using the Constraints Editor When you run the Create Timing Constraints process. Add new constraints to your design. an existing UCF file with the same base name as the NGD file is used.ucf files are automatically read into the Constraints Editor. you can specify the name of the UCF file.1 In-Depth Tutorial . The Map program (the next section in the design flow) then reads the NGD. Input files to the Constraints Editor are: NGD (Native Generic Database) File The NGD file serves as input to the mapper. The Constraints Editor generates a valid UCF file. Translate is run and ISE launches the Constraints Editor. The Global branch of the Timing Constraints tab automatically displays all the clock nets in your design. In this design. The Translate step (NGDBuild) uses the UCF file.ngd and stopwatch. Global OFFSET IN. the stopwatch. along with design source netlists. to produce a newer NGD file. which then outputs the physical design database. which incorporates the changes made. Alternatively.xilinx. pad to 116 www. • Corresponding UCF (User Constraint File) By default. and TIMEGRP OFFSET IN constraint will be written in the UCF and used during implementation.com ISE 9. The Constraints Editor enables you to: • • • Edit constraints previously defined in a UCF file.

Figure 5-5: Constraints Editor in Project Navigator .Using the Constraints Editor R setup.com 117 . 3. 2.0 in the Time field.xilinx. ISE 9. Note that many of the internal names will vary depending on the design flow and synthesis tool used. and clock to pad values. This enables you to define an explicit period for the clock. Double-click the Period cell on the row associated with the clock net CLK. Enter a value of 7.Global Branch Figure 5-6: Constraints Editor . For the Clock Signal Definition. The Clock Period dialog box opens.1 In-Depth Tutorial www. verify that Specify Time is selected.Global Branch In the Constraints Editor. edit the constraints as follows: 1.

Verify that ns is selected from the Units drop-down list. Click OK. PERIOD Constraint Values For the Input Jitter section.com ISE 9. 9. 8. A listing of the current ports is displayed on the left. 6. This creates a Global OFFSET OUT constraint for the CLK signal Figure 5-9: Completed Global constraints in Constraints Editor 10. Verify that ps is selected from the Units drop-down list. Single click the Clock to Pad cell for clock signal CLK and type 38. This creates a Global OFFSET IN constraints for the CLK signal.1 In-Depth Tutorial . 118 www. INPUT JITTER Constraint Value The period cell is updated with the global clock period constraint that you just defined (with a default 50% duty cycle). Figure 5-7: 5. Select SF_D<0> in the Port Name Column. enter a value of 60 in the Time field. Hold down the Shift key and select SF_D<7>. Single click the Pad to Setup cell for clock signal CLK and type 6. 11. Select the Ports branch from the Timing Constraints tab of the Sources panel. Figure 5-8: 7.R Chapter 5: Design Implementation 4.xilinx. This selects the elements for creating a grouped offset. 12.

In the Select Group drop-down list.Using the Constraints Editor R 13. Enter 32 for the Timing Requirement. In the Group Name field. and click Create Group to create the group. 15. ISE 9.1 In-Depth Tutorial www. Figure 5-10: Creating a Grouped OFFSET 14. Click Clock to Pad. Figure 5-11: Setting Constraints for the Grouped OFFSET The Clock to Pad dialog box opens. type display_grp.xilinx. 16. select the group you just created.com 119 .

Click OK 19. Select the stopwatch module in the Sources window. along with the design source netlists. 4. Gigabit Transceivers (GTs).xilinx. The Translate step uses this UCF file. located under the Translate process. Select File > Save. Close the Constraints Editor by selecting File > Close. to produce a newer NGD file.1 In-Depth Tutorial .ucf file in your current working directory.R Chapter 5: Design Implementation 17. 2. Using the Floorplan Editor Use the Floorplan Editor to add and edit the pin locations and area group constraints defined in the NGD file. 1.com ISE 9. Click the + next to Translate. Select CLK in the Relative to Clock Pad Net field. Floorplan Editor also places Global Logic at the Slice level with Block Ram. 120 www. Clock to Pad Dialog Box The changes are now saved in the stopwatch. and BUFGs. Floorplan Editor edits the UCF file by adding the newly created placement constraints. This section describes the creation of IOB assignments for several signals. Double-click Assign Package Pins Post-Translate. The NGD file incorporates the changes made in the design and the UCF file from the previous section. 3. 20. click the + next to Implement Design to expand the process hierarchy in the Processes window. Figure 5-12: 18. Floorplan Editor generates a valid UCF file. Digital Clock Managers (DCMs).

change the center filter from ALL to IOs. 6.com 121 . 7. 8. In the Design Object tab. This window displays all the objects in the design.1 In-Depth Tutorial www. Floorplan Editor Select the Package tab in the work space.xilinx. This view shows the graphical representation of the device package. Figure 5-14: 5. located under the User Constraints process. then scroll down to the nets that begin with “LCD_”. In the LOC column. enter pin locations using the following values: ♦ ♦ ♦ LCD_E → AB4 LCD_RS → Y14 LCD_RW → W13 ISE 9. Select the Design Object tab in Processes panel.Using the Floorplan Editor R Note: For an EDIF project. Figure 5-13: Edit Package Pin Placement This process launches Floorplan Editor. double-click Assign Package Pins.

click and drag the following signals to the associated location in the Package Pin window: ♦ ♦ ♦ ♦ LAP_LOAD → T16 RESET → U15 MODE → T14 STRTSTOP → T15 122 www.xilinx.R Chapter 5: Design Implementation Figure 5-15: Pin Locations To place IOs in the Package Pin view using the drag and drop method: 9. From the Design Object tab.1 In-Depth Tutorial .com ISE 9.

select File > Save. ISE 9. 1. continue with the implementation of the design. 11. Once the pins are locked down. 2.ucf file in your current working directory.xilinx.Mapping the Design R Figure 5-16: Drag and Drop IOs in the Package Pins View 10. Note: This can also be accomplished by double-clicking Map. right-click on Map and select Run. Mapping the Design Now that all implementation strategies have been defined (properties and constraints).com 123 . Select the stopwatch module in the Sources window.1 In-Depth Tutorial www. Close Floorplan Editor by selecting File > Close. The changes are saved in the stopwatch. In the Processes tab.

Expand the Implement Design hierarchy to see the progress through implementation. Figure 5-17: Mapping the Design The design is mapped into CLBs and IOBs.com ISE 9. Each step generates its own report as shown in the following table. references to trimmed logic. or from the MAP Reports web at http://www. refer to the Development System Reference Guide.xilinx. and device utilization. performs target device optimizations.R Chapter 5: Design Implementation 3.1 In-Depth Tutorial . 124 www.com/support/sw_manuals/xilinx9/. This Guide is available All NGDBUILD and with the collection of software manuals and is accessible from ISE by selecting Help > Software Manuals. and runs a design rule check on the resulting mapped netlist. Table 5-2: Reports Generated by Map Includes warning and error messages from the translation process. Includes information on how the target device resources are allocated.xilinx. Map performs the following functions: • • Allocates CLB and IOB resources for all basic logic elements in the design. Processes all location and timing constraints. Translation Report Map Report For detailed information on the Map reports.

Mapping the Design R To view a report: 1. Look for Warnings. Figure 5-18: 3. Translation Report and Map Report Processes Review the report.1 In-Depth Tutorial www. such as Translation Report or Map Report.xilinx. and Information (INFO).com 125 . The Design Summary also contains these reports. 2. Expand the Translate or Map hierarchy. Double-click a report. Figure 5-19: Implementation Reports shown in Design Summary ISE 9. Errors.

Estimating Timing Goals with the 50/50 Rule For a preliminary indication of how realistic your timing goals are. Since you defined timing constraints for the stopwatch design. Figure 5-20: Post-Map Static Timing Report Process 126 www. evaluate the design after the map stage. To view the Post-Map Static Timing Report and review the PERIOD Constraints that were entered earlier: 1. Timing Analyzer automatically launches and displays the report. In the Processes tab. The net delays provided are based on an optimal distance between blocks (also referred to as unplaced floors). This analysis can help to determine if your timing constraints are going to be met. Because the design is not yet placed and routed. Evaluation verifies that block delays are reasonable given the design specifications.1 In-Depth Tutorial . click the + next to Map to expand the process hierarchy.R Chapter 5: Design Implementation Using Timing Analysis to Evaluate Block Delays After Mapping After the design is mapped. Double-click Generate Post-Map Static Timing. the timing report will display the path for each of the timing constraints. actual routing delay information is not available. 2. Report Paths in Timing Constraints Option Use the Post-Map Static Timing Report to determine timing violations that may occur prior to running PAR.xilinx. This report is produced after Map and prior to Place and Route (PAR). If your design is extremely dense. double-click Analyze Post-Map Static Timing Report. To open the Post-Map Static Timing Report. 3. A rough guideline (known as the 50/50 rule) specifies that the block delays in any single path make up approximately 50% of the total path delay after the design is routed. evaluate the Logic Level details in the Post-Map Static Timing Report to evaluate the logical paths in the design. For example. a path with 10 ns of block delay should meet a 20 ns timing constraint after it is placed and routed. the Post-Map Static Timing Report provides a summary analysis of your timing constraints based on block delays and estimates of route delays.com ISE 9. The timing report describes the logical block delays and estimated routing delays.

only three paths per timing constraint will be shown. PAR fails because it determines that the total delay (10 ns) is greater than the constraint placed on the design (8 ns).xilinx. The Post-Map Static Timing Report will list any pre-PAR timing violations. In this example. Placing and Routing the Design After the mapped design is evaluated. and timing specifications for the design. and there are block delays of 7 ns and unplaced floor net delays of 3 ns. PAR still processes a design based on the relationship between the block delays. close the Timing Analyzer by selecting File > Close. Note: Even if you do not generate a timing report. Selecting one of the three paths allows you to see a breakdown of the path which contains the component and routing delays. you will find the selected period constraint and the minimum period obtained by the tools after mapping. 1. Figure 5-21: Selecting Post-Map Static Timing constraint The work space shows the report for the selected constraint. After viewing the report. To run PAR. in the Processes tab. Select the TS_dcm_inst_CLKX_BUF timing constraint under the Timing tab. The unplaced floors listed are estimates (indicated by the letter “e” next to the net delay) based on optimal placement of blocks. 12.Placing and Routing the Design R 4. floors. At the top of this report. For example. 5.0% logic.0% route). Since you defined timing constraints earlier in this chapter. PAR stops and generates an error message.com 127 .1 In-Depth Tutorial www. ISE 9. • Non-Timing Driven PAR PAR is run. By default. double-click Place & Route.g. 88. One of two place-and-route algorithms is performed during the Place & Route (PAR) process: • Timing Driven PAR PAR is run with the timing constraints specified in the input netlist and/or in the constraints file. ignoring all timing constraints. the design can be placed and routed. the Place & Route (PAR) process performs timing driven placement and routing. Notice that the report displays the percentage of logic versus the percentage of routing at the end of each path (e. if a PERIOD constraint of 8 ns is specified for a path.

or from the web at http://www. This Guide is available with the collection of software manuals and is accessible from ISE by selecting Help > Online Documentation. Use this report to verify that pins locked down were placed in the correct location. Note: You can also display and examine the Pad Report and Asynchronous Delay Report. Pad Report Asynchronous Delay Report All PAR Reports The Design Summary also displays the Place and Route Reports.R Chapter 5: Design Implementation To review the reports that are generated after the Place & Route process is completed: 2.com/support/sw_manuals/xi linx9/.1 In-Depth Tutorial . Double-click Place & Route Report. Lists all nets in the design and the delays of all loads on the net. Use this report to verify that the design successfully routed and that all timing constraints were met. Table 5-3: Reports Generated by PAR Report Place & Route Report Description Provides a device utilization and delay summary.com ISE 9. 3. Click the + next to Place & Route to expand the process hierarchy. refer to the Development System Reference Guide.xilinx. Figure 5-22: Design Summary of the Place & Route Report 128 www. Contains a report of the location of the device pins.xilinx. For detailed information on the PAR reports.

1 In-Depth Tutorial www. • • To view the actual design layout of the FPGA: 1. Run the BitGen program and download the resulting bitstream file to the targeted device. View and change the nets connected to the capture units of an Integrated Logic Analyzer (ILA) core in your design. Probes are used to route the value of internal nets to an IOB (Input/Output Block) for analysis during debugging of a device.Using FPGA Editor to Verify the Place and Route R Using FPGA Editor to Verify the Place and Route Use the FPGA Editor to display and configure Field Programmable Gate Arrays (FPGAs). Use FPGA Editor to: • • • Place and route critical components before running the automatic place-and-route tools. Figure 5-23: View/Edit Routed Design (FPGA Editor) Process ISE 9. The FPGA Editor reads and writes Native Circuit Description (NCD) files. Add probes to your design to examine the signal states of the targeted device. and double-click View/Edit Routed Design (FPGA Editor). Macro files (NMC) and Physical Constraints Files (PCF).com 129 .xilinx. Click the + next to Place & Route to expand the process hierarchy. Finish placement and routing if the routing program does not completely route your design.

R Chapter 5: Design Implementation 2.com ISE 9. In FPGA Editor. Figure 5-24: 3. List Window in FPGA Editor Select the clk_262144K (Clock) net to see the fanout of the clock net. Clock Net 130 www. This enables you to view all of the possible nets in the design.1 In-Depth Tutorial . Figure 5-25: 4. change the List Window from All Components to All Nets. To exit FPGA Editor. select File > Exit.xilinx.

a Post Layout Timing Report is generated by default to verify that the design meets your specified timing goals. Double-click Analyze Post-Place & Route Static Timing Report to open the report in Timing Analyzer. The net delays are now reported as actual routing delays after the Place and Route process. The Post-Map timing report showed logic delays contributed to 80% to 90% of the minimum period attained. This launches the Floorplan Implemented window and highlights the corresponding data path. With the TS_DCM_INST_CLKFX_BUF constraint highlighted in the Timing Analyzer tab.xilinx. ISE 9. The following is a summary of the Post-Place & Route Static Timing Report for the stopwatch design: ♦ The minimum period value increased due to the actual routing delays. Select View > Overlays > Toggle Simplified and Actual Views. you can reduce excessive block delays and improve design performance by decreasing the number of logic levels in the design.com 131 . This changes the routing view for the highlighted data path from a simplified view to the actual routing 5. The post-layout report indicates that the logical delay value now equals between 30% and 40% of the period. the worst case path is mainly made up of logic delay. This report evaluates the logical block delays and the routing delays. Expand the Generate Post-Place & Route Static Timing hierarchy. Or you can select the Timing Constraint in the Design Summary and then a timing constraint hyperlink to launch Timing Analyzer. 3. Select the Timing tab in the Sources panel and select the Timing Objects tab in the Processes panel.Evaluating Post-Layout Timing R Evaluating Post-Layout Timing After the design is placed and routed. ♦ ♦ The post-layout result does not necessarily follow the 50/50 rule previously described because the worst case path primarily includes component delays.1 In-Depth Tutorial www. The total unplaced floors estimate changed as well. select the first hyperlink beginning with Maximum Data Path. In general. For some hard to meet timing constraints. To display this report: 1. expecting the timing of these paths to be reduced any further is unrealistic. 2. Since total routing delay makes up only a small percentage of the total path delay spread out across two or three nets. 4.

Hold the cursor over different nets or objects in the outlined path to observe timing delay and other information about that portion of the path. the next step is to update the design with an HDL change. and PAR reports will show which partitions are updated and which ones are preserved. Please proceed to the next section. you will not be able to do this section. 8. 7. The Synthesis. MAP.com ISE 9. 132 www. Select File > Close again to close the Post-Place & Route Static Timing report. The change will be in the LCD_CNTRL_INST module.Data Path with Simplified Routing Figure 5-27: Floorplan Implemented .1 In-Depth Tutorial . If you are doing the EDIF flow. so only that partition will need to be re-synthesized and re-implemented.R Chapter 5: Design Implementation Figure 5-26: Floorplan Implemented . Changing HDL with Partition Now that the design has been implemented.Data Path with Actual Routing 6. Select File > Close to exit the Floorplan Implemented view.xilinx.

-. Select the Place and Route Report. Notice which partitions were preserved and which partitions were re-used. Notice that the implementation is faster with partitions. // [colon] to sf_d_temp = 8’b00101110. select the top-level source file stopwatch and in the Processes tab. Make the following change according to your HDL language: ♦ ♦ If you are using Verilog: On line 377 and 564. change the code from sf_d_temp = 8’b00111010. 5. 2. Notice which partitions were preserved and which partitions were re-used. Figure 5-28: LCD_CNTRL_INST Partition is Out of Date 6. Select Run from the menu. since the implementation tools only need to re-implement the LCD_CNTRL_INST module. -.1 In-Depth Tutorial www. Open the LCD_CNTRL_INST module in the text editor by double-clicking it in the Sources tab. In the Design Summary view. 4.xilinx. ISE 9.com 133 . select File > Save. then select Partition Status.Changing HDL with Partition R 1. Notice which partitions were preserved and which partitions were re-used. // [period] If you are using VHDL: On line 326 and 514. change the code from sf_d_temp <= “00111010”.[period] 3. view the following reports: ♦ ♦ ♦ Select the Synthesis Report. To save the changes to LCD_CNTRL_INST. then select Guide Report. then select Partitions Report. In the Sources tab.[colon] to sf_d_temp <= “00101110”. The rest of the design is re-used. right-click on Place & Route. Select the MAP Report.

Process Properties Startup Options Click the Startup Options category. A configuration bitstream is created for downloading to a target device or for formatting into a PROM programming file. Figure 5-29: 3.1 In-Depth Tutorial .xilinx. Change the FGPA Start-Up Clock property from CCLK to JTAG Clock. you will create configuration data for a Xilinx Serial PROM. 2. In this tutorial. 134 www. Right-click the Generate Programming File process.com ISE 9. Select Properties. set the properties and run configuration as follows: 1. To create a bitstream for the target device.R Chapter 5: Design Implementation Creating Configuration Data After analyzing the design through timing constraints in Timing Analyzer. 4. The Process Properties dialog box opens. you need to create configuration data.

all you need is a bitstream file. The BitGen program creates the bitstream file (in this tutorial. Verify that the specified options were used when creating the configuration data.bit file).xilinx. which contains the actual configuration data. In the Processes tab. Process Properties Readback Options Click the Readback Options category.Creating a PROM File with iMPACT R Note: You can use CCLK if you are configuring Select Map or Serial Slave. 7. the stopwatch. Figure 5-31: Programming File Generation Report Process Creating a PROM File with iMPACT To program a single device using iMPACT. Change the Security property to Enable Readback and Reconfiguration. double-click Programming File Generation Report.com 135 . 6. double-click Generate Programming File to create a bitstream of this design. Click the + next to Generate Programming File to expand the process hierarchy. you must use iMPACT to create a PROM file. iMPACT accepts any number of bitstreams and creates one or more PROM files containing one or more daisy chain configurations. a wizard enables you to do the following: ISE 9. 10. In iMPACT. Figure 5-30: 5. 8. 9. or to program your devices using a PROM.1 In-Depth Tutorial www. Click OK to apply the new properties. To review the Programming File Generation Report. To program several devices in a daisy chain configuration.

select Prepare a PROM File. In the Welcome to iMPACT dialog box. JTAG File. ACE.R Chapter 5: Design Implementation • • • • Create a PROM file. Figure 5-32: Welcome to iMPACT Dialog Box 136 www. located under the Generated Programming File process hierarchy. or immediately save the current PROM file configuration. Click Next.1 In-Depth Tutorial . Add additional bitstreams to the daisy chain. Remove the current bitstream and start over. 3.com ISE 9.xilinx. In the Processes tab. 2. create a PROM file in iMPACT as follows: 1. double-click Generate PROM. Create additional daisy chains. For this tutorial.

ISE 9. 9. Specify Xilinx PROM Device Dialog Box In the File Generation Summary dialog box. select MCS. In the Specify Xilinx Serial PROM Device dialog box. click OK and then select the stopwatch.bit file. 6. select Auto Select PROM. type stopwatch1. Figure 5-33: Prepare PROM Files Dialog Box 5. In the Prepare PROM Files dialog box. Click Next. 10. Click No when you are asked if you would like to add another design file to the datastream. For PROM File Name. select Xilinx PROM. Under PROM File Format. click Finish. Note: You will receive a warning that the startup clock is being changed from jtag to CCLK. set the following values: ♦ ♦ ♦ Under “I want to target a:”. Figure 5-34: 8.1 In-Depth Tutorial www.xilinx.Creating a PROM File with iMPACT R 4. In the Add Device File dialog box. Click Next. 7.com 137 .

138 www. available from the iMPACT application by selecting Help > Help Topics. For more information on XFLOW. With the resulting stopwatch. For more information on programming a device.com ISE 9.cmd_log using either the copy-and-paste method or the drag-anddrop method into a text file. Command line options may also be obtained by typing the executable name followed by the -h option at a command prompt. To close iMPACT.cmd_log in read-only mode.xilinx. see the ISE Help. or from the web at http://www. available from the ISE application by selecting Help > Help Topics.1 In-Depth Tutorial . XFLOW reads a design file as input. This Guide is available with the collection of software manuals and is accessible from ISE by selecting Help > Software Manuals. This completes the Design Implementation chapter of the tutorial. stopwatch1. refer to the “XFLOW” section in the Development System Reference Guide. Command line options are organized according to implementation tools. This process opens a file named <source_name>.com/support/sw_manuals/xilinx9/. select File > Save As and enter the desired file name.mcs and a MSK file generated along with the BIT file. Another useful tool for automating design implementation is XFLOW. This allows a user to verify the options being used or to create a command batch file to replicate the design flow.R Chapter 5: Design Implementation 11. iMPACT displays the PROM associated with your bit file. To create an editable batch file. Command Line Implementation ISE allows a user to easily view and extract the command line arguments for the various steps of the implementation process. you are ready for programming your device using iMPACT. Sections of the Command Line Log File may also be copied from <source_name>.bit. For a complete listing of command line options for most Xilinx executables. For more information on this design flow and implementation methodologies. At any stage of the design flow you can look at the command line arguments for completed processes by double-clicking View Command Line Log File from the Design Entry Utilities process hierarchy in the Processes tab. Select Operations > Generate File. flow and option files. refer to the Development System Reference Guide. see the iMPACT Help. XFLOW is a Xilinx command line tool that automates the Xilinx implementation and simulation flows. 12. select File > Close.xilinx.

• • • • “Overview of Timing Simulation Flow” “Getting Started” “Timing Simulation Using ModelSim” “Timing Simulation Using Xilinx ISE Simulator” Overview of Timing Simulation Flow Timing simulation uses the block and routing delay information from a routed design to give a more accurate assessment of the behavior of the circuit under worst-case conditions. Timing simulation uses the detailed timing and design layout information that is available after place and route. In this chapter. you must have Xilinx ISE™ 9. Getting Started The following sections outline the requirements to perform this part of the tutorial flow. “Behavioral Simulation” for information on installing and setting up ModelSim. This enables simulation of the design. Timing (post-place and route) simulation is a highly recommended part of the HDL design flow for Xilinx® devices. Simulating with the Xilinx ISE simulator requires that the ISE 9.com 139 .1i and ModelSim simulator installed. Refer to Chapter 4.R Chapter 6 Timing Simulation This chapter includes the following sections. the design should be analyzed both statically and dynamically. Performing a timing simulation in addition to a static timing analysis will help to uncover issues that cannot be found in a static timing analysis alone.1 In-Depth Tutorial www. Required Software To simulate with ModelSim. To verify the design. which closely matches the actual device operation.xilinx. you will perform a timing simulation using either the ModelSim simulator or the Xilinx ISE Simulator.1i software is installed ISE 9. For this reason. timing simulation is performed after the design has been placed and routed.

a test bench is needed to provide stimulus to the design. The timing simulation netlist created by Xilinx is composed entirely of instantiated primitives. This Guide is accessible from within ISE by selecting Help > Software Manuals. and from the web at http://www. Select ISE Simulator (VHDL/Verilog) or Modelsim with the appropriate version and language in the Simulator value field. initialize simulation.” and thus. You should use the same test bench that was used to perform the behavioral simulation. Whether you choose to use the ModelSim simulator or the ISE Simulator for this tutorial.1 In-Depth Tutorial . To perform timing simulation of Xilinx designs in any HDL simulator. “Design Implementation. compile source files. • Test Bench File (VHDL or Verilog) In order to simulate the design. 3.com/support/sw_manuals/xilinx9/. If you completed Chapter 4. • Xilinx Simulation Libraries For timing simulation. 2.com ISE 9. In the Project Properties dialog box click the down arrow in the Simulator value field to display a list of simulators. The NetGen tool will be used in this chapter to create a simulation netlist from the placed and routed design which will be used to represent the design during the Timing Simulation. and for a list of other supported simulators. right-click the device line (xc3s700A-4fg484) and select Properties. Selecting a different simulator (e. the SIMPRIM library must be set up correctly. Note: ModelSim simulators and the ISE Simulator are the only simulators that are integrated with Project Navigator. skip to “Timing Simulation Using Xilinx ISE Simulator”.g. see to “Xilinx Simulation Libraries” in Chapter 4. Specifying a Simulator To select either the desired simulator to simulate the stopwatch design. the SIMPRIM library should already be compiled. For more information on compiling and setting up Xilinx simulation libraries. 140 www. For additional information about simulation.xilinx.xilinx. complete the following: 1. which are modeled in the SIMPRIM library.R Chapter 6: Timing Simulation Required Files The timing simulation flow requires the following files: • Design Files (VHDL or Verilog) This chapter assumes that you have completed Chapter 5. In the Sources tab. and control simulation properties for ModelSim. Timing Simulation Using ModelSim Xilinx ISE provides an integrated flow with the Mentor ModelSim simulator. have a placed and routed design. Note: To simulate with the ISE Simulator. “Behavioral Simulation”. see Chapter 5 of the Synthesis and Verification Guide. the end result is the same. ISE enables you to create work directories. the SIMPRIM library is needed to simulate the design. NC-Sim or VCS) will set the correct options for Netgen to create a simulation netlist for that simulator but Project Navigator will not directly open the simulator. Please refer to the “Adding an HDL Test Bench” in Chapter 4 if you do not already have a test bench in your project.

exe. or Project Navigator cannot find modelsim. click the Help button. Note: If the ModelSim Simulator processes do not appear. Right-click Simulate Post-Place & Route Model. Select Properties. If ModelSim is installed but the processes are not available. This global setting enables you to see all available properties. For a description of each property. and click Integrated Tools in the left pane.exe file. select Post-Route Simulation in the Sources for field. 3. In the right pane.xilinx. 6.Timing Simulation Using ModelSim R Specifying Simulation Process Properties To set the simulation process properties: 1. click the + next to ISE General to expand the ISE preferences. Select the test bench file (stopwatch_tb). 2. 7. Select the Simulation Model Properties category. click the + next to ModelSim Simulator to expand the process hierarchy. select Edit > Preferences. the Project Navigator preferences may not be set correctly.com 141 . under Model Tech Simulator. In the Processes tab. browse to the location of modelsim. To set the ModelSim location. Ensure that you have set the Property display level to Advanced. The Process Properties dialog box displays. In the Sources tab.1 In-Depth Tutorial www. The properties should appear as shown in Figure 6-1. 4. ISE 9.exe. These properties set the options that NetGen uses when generating the simulation netlist. For example. 5. c:\modeltech_xe\win32xoem\modelsim. it means that either ModelSim is not selected as the Simulator in the Project Properties dialog box.

These properties set the options that ModelSim uses to run the timing simulation.xilinx. Figure 6-1: 8. three windows open when timing simulation is launched from ISE. 9. the Structure window.com ISE 9.1 In-Depth Tutorial . click the Help button. For more details on ModelSim Simulator windows. This tab gives you control over the ModelSim simulation windows. For a description of each property. Simulation Model Properties Select the Display Properties category. The properties should appear as shown in Figure 6-2. refer to the ModelSim User Guide. and the Wave window. Select the Simulation Properties category. 142 www. They are the Signal window. the default Simulation Model Properties are used.R Chapter 6: Timing Simulation For this tutorial. By default.

1 In-Depth Tutorial www. • • Drag and drop from the Signal/Object window. Note: The majority of this design runs at 100 Hz and would take a significant amount of time to simulate. ISE 9. ISE will run NetGen to create the timing simulation model. Highlight signals in the Signal/Object window and then select Add > Wave > Selected Signals. you must add them to the Wave window. In the Simulation Properties tab. compile the source files. Figure 6-2: Simulation Properties 11. There are two basic methods for adding signals to the Simulator Wave window. Click OK to close the Process Properties dialog box. load the design. only the DCM signals will be monitored to verify that they work correctly. and run the simulation for the time specified. ISE automatically adds all the top-level ports to the Wave window. double-click Simulate Post-Place and Route Model in the Processes tab.xilinx. Adding Signals To view signals during the simulation. set the Simulation Run Time property to 2000 ns. ISE will then call ModelSim and create the working directory. This is why the counter will seem like it is not working in a short simulation. Additional signals are displayed in the Signal window based on the selected structure in the Structure window.Timing Simulation Using ModelSim R 10. Performing Simulation To start the timing simulation.com 143 . For the purpose of this tutorial.

4. you will be adding the DCM signals to the waveform. Figure 6-3: 1.1 In-Depth Tutorial . All windows can be undocked by clicking the Undock icon. Click and drag CLKIN from the Signal/Object window to the Wave window. Figure 6-4 shows the Structure/Instance window for the Schematic flow. Undock icon In the Structure/Instance window. The graphics and the layout of the Structure/Instance window for a Verilog or VHDL flow may appear different.0 or higher. All the signal names for the DCM will be listed.Schematic Flow Click the Structure/Instance window and select Edit > Find. 6. 7. Structure/Instance Window . Type CLKIN in the search box and select the Exact checkbox.com ISE 9. 3. 144 www. click the + next to uut to expand the hierarchy. In this tutorial. all the windows are docked by default. 5. Type in X_DCM in the search box and select Entity/Module in the Field section.xilinx. Note: If you are using ModelSim version 6.R Chapter 6: Timing Simulation The following procedure explains how to add additional signals in the design hierarchy. select X_DCM and click on the signals/objects window. Select the Signal/Object window and select Edit > Find. Once ModelSim locates X_DCM. Figure 6-4: 2.

undock the window and then maximize the window for a larger view of the waveform. Click and drag the newly created divider to above the CLKIN signal.com 145 .Timing Simulation Using ModelSim R 8. Adding Dividers Modelsim has the capability to add dividers in the Wave window to make it easier to differentiate the signals. Enter DCM Signals in the Divider Name box. Click and drag the following signals from the Signal/Object window to the Wave window: ♦ ♦ ♦ ♦ RST CLKFX CLK0 LOCKED Note: Multiple signals can be selected by holding down the Ctrl key. 5.1 In-Depth Tutorial www.xilinx. 4. The waveform should look as shown in Figure 6-5. To add a divider called DCM Signals: 1. Figure 6-5: The Resulting Waveform ISE 9. If necessary. In the Display Signal Path box. Click anywhere in the Wave window. 2. Note: Stretch the first column in the waveform to see the signals clearly. In place of using the drag and drop method select Add to Wave > Selected Signals. Right-click the Wave window and click Insert > Divider. enter 2 and click OK. 3. The hierarchy in the signal name can also be turned off by selecting Tools > Options > Wave Preferences.

To measure the CLK0: 146 www.R Chapter 6: Timing Simulation Notice that the waveforms have not been drawn for the newly added signals. Restart Dialog Box At the ModelSim command prompt. Therefore. Figure 6-8: Entering the Run Command The simulation will run for 2000 ns.com ISE 9. Click Restart. This is because ModelSim did not record the data for these signals.xilinx. Modelsim has the capability to add cursors to carefully measure the distance between signals. The DCM signals should only be analyzed after the LOCKED signal has gone high. you need to rerun the simulation for the desired amount of time. ModelSim will only record data for the signals that have been added to the Wave window while the simulation is running.1 In-Depth Tutorial . The CLK0 needs to be 50 Mhz and the CLKFX should be ~26 Mhz. Rerunning Simulation To restart and re-run the simulation: 1. By default. Restart Simulation Icon Figure 6-7: 2. The waveforms for the DCM should now be visible in the Wave window. after new signals are added to the Wave window. Until the LOCKED signal is high the DCM outputs are not valid. Figure 6-6: The Restart dialog box opens. Analyzing the Signals Now the DCM signals can be analyzed to verify that it works as expected. 3. enter run 2000 ns and hit the Enter key. Click the Restart Simulation icon.

Save the signals list after new signals or stimuli are added. which is the input frequency from the test bench. Save Format Dialog Box After restarting the simulation. you can select File > Load in the Wave window to reload this file. 1.1 In-Depth Tutorial www. 2. This converts to 50 Mhz.Timing Simulation Using ModelSim R 1. The measurement should read 38462 ps. select File > Save Format. Saving the Simulation The ModelSim Simulator provides the capability of saving the signals list in the Wave window.xilinx. Your timing simulation is complete and you are ready to program your device by following Chapter 7. rename the filename from the default wave. Measure CLKFX using the same steps as above. 3. In the Wave window. Figure 6-9: Find Next Transition Icon Look at the bottom of the waveform to view the distance between the two cursors. Click the Find Next Transition icon twice to move the cursor to the next rising edge on the CLK0 signal. and after simulation is rerun. Click Save.” ISE 9.com 147 . Click and drag the second cursor to a position just right of the first cursor on the CLK0 signal. 4.do.do to dcm_signal_tim. In the Save Format dialog box. which in turn should be the DCM CLK0 output. “iMPACT Tutorial. Select Add > Cursor twice to place two cursors on the wave view. Figure 6-10: 3. The measurement should read 20000 ps. The saved signals list can easily be loaded each time the simulation is started. Click and drag the first cursor to the rising edge transition on the CLK0 signal after the LOCKED signal has gone high. This equals approximately 26 Mhz. 2.

2. Select the ISE Simulator Properties category. For this tutorial. The Process Properties dialog box displays. 5. select Post-Route Simulation in the Sources for field.R Chapter 6: Timing Simulation Timing Simulation Using Xilinx ISE Simulator Follow this section of the tutorial if you have skipped the previous section. These properties set the options the simulator uses to run the timing simulation. click the Help button. Right-click Simulate Post-Place & Route Model. “Timing Simulation Using ModelSim. In the Simulation Properties tab. Select the Simulation Model Properties category. 148 www. the default Simulation Model Properties are used. 4. 6. In the Sources tab. set the Simulation Run Time property to 2000 ns. Select Properties.com ISE 9.xilinx. For a description of each property. For a description of each property.” Specifying Simulation Process Properties To set the simulation process properties: 1. Click OK to close the Process Properties dialog box. The properties should appear as shown in Figure 6-11.1 In-Depth Tutorial . 3. In the Processes tab. Ensure that you have set the Property display level to Advanced. Figure 6-11: Simulation Properties 10. 7. This global setting enables you to now see all available properties. Select the test bench file (stopwatch_tb). 9. click the + next to Xilinx ISE Simulator to expand the process hierarchy. 8. These properties set the options that NetGen uses when generating the simulation netlist. click the Help button.

Sim Hierarchy Window . ISE 9. Select DCM_SP_INST/LOCKED signal and click on OK. Adding Signals To view signals during the simulation. load the design. In this tutorial. For the purpose of this tutorial. This is why the counter will seem like it is not working in a short simulation. ISE automatically adds all the top-level ports to the waveform window. In the Sim Hierarchy window.VHDL Flow Click and drag LOCKED from the Sim Hierarchy window to the waveform window. Type the locked in the Find Signal dialog box and click on OK. you will be adding the DCM signals to the waveform. 2. Project Navigator automatically runs NetGen to generate a timing simulation model from the placed and routed design. 3. only the DCM signals will be monitored to verify that they work correctly.1 In-Depth Tutorial www.xilinx. double-click Simulate Post-Place and Route Model in the Processes tab. The ISE Simulator will then compile the source files.Timing Simulation Using Xilinx ISE Simulator R Performing Simulation To start the timing simulation. you must add them to the waveform window. When a simulation process is run. The following procedure explains how to add additional signals in the design hierarchy. 1. All available external (top-level ports) and internal signals are displayed in the Sim Hierarchy window. Figure 6-12: 5. 4. and run the simulation for the time specified. click the + next to uut to expand the hierarchy. The signal names and layout in the Sim Hierarchy window for a schematic or VHDL flow may appear different. Figure 6-12 shows the Sim Hierarchy window for the VHDL flow.com 149 . Note: The majority of this design runs at 100 Hz and would take a significant amount of time to simulate. Right click in the Sim Hierarchy window and select Find.

com ISE 9. you need to rerun the simulation for the desired amount of time. Figure 6-13: The Resulting Waveform Notice that the waveforms have not been drawn for the newly added signals. To change the signal name display. 2. Viewing Full Signal Names A signal name may be viewed with either the complete hierarchical name or by the short name which omits hierarchy information.xilinx. Click and drag the following X_DCM_SP signals from the SIM Hierarchy window to the waveform window: ♦ ♦ ♦ ♦ RST CLKFX CLK0 CLKIN Note: Multiple signals can be selected by holding down the Ctrl key. The ISE Simulator will only record data for the signals that have been added to the waveform window while the simulation is running.1 In-Depth Tutorial . 1. Right click the desired signal in the waveform window. Therefore. This is because the ISE Simulator did not record the data for these signals. The waveform should appear as shown in Figure 6-13. Rerunning Simulation To restart and re-run the simulation: 150 www. Select Long Name or Short Name as desired.R Chapter 6: Timing Simulation 6. Note: Stretch the first column in the waveform to see the signals clearly. after new signals are added to the waveform window.

Click and drag the second marker to the next rising edge on the CLK0 signal. The DCM signals should only be analyzed after the LOCKED signal has gone high. Click the Restart Simulation icon. The waveforms for the DCM should now be visible in the Simulation window. Figure 6-16: Adding Timing Markers Note: You may need to Zoom In to place the markers precisely on the clock edge. ISE 9. Analyzing the Signals Now the DCM signals can be analyzed to verify that it does work as expected.xilinx. Until the LOCKED signal is high the DCM outputs are not valid. Restart Simulation Icon At the Sim Console command prompt. The cursor changes to an uparrow pointer. Two vertical markers are placed one the waveform.1 In-Depth Tutorial www. Right click the wave window and select Add Measure. The CLK0 needs to be 50 Mhz and the CLKFX should be ~26 Mhz. Click a rising edge transition on the CLK0 signal after the LOCKED signal has gone high. Figure 6-15: Entering the Run Command The simulation will run for 2000 ns.com 151 . 2. To measure the CLK0: 1. Figure 6-14: 2. ISE Simulator has the capability to add cursors to carefully measure the distance between signals. enter run 2000 ns and hit the Enter key. 3.Timing Simulation Using Xilinx ISE Simulator R 1.

This converts to 50 Mhz. which in turn should be the DCM CLK0 output. Your timing simulation is complete and you are ready to program your device by following Chapter 7. Measure CLKFX using the same steps as above. “iMPACT Tutorial. The measurement should read 20. The measurement should read 38.0 ns. this equals approximately 26 Mhz.com ISE 9.1 In-Depth Tutorial .R Chapter 6: Timing Simulation View the time value between the two markers to see the distance between the two clock edges. which is the input frequency from the test bench.xilinx.” 152 www.5 ns.

PROM files. a file generation and device programming tool. • • • • • • • • Virtex™/-E/-II/-II PRO/4/5 Spartan™/-II/-IIE/XL/3/3E/3A XC4000™/E/L/EX/XL/XLA/XV CoolRunner™XPLA3/-II XC9500™/XL/XV XC18V00P XCF00S XCF00P ISE 9.1 In-Depth Tutorial www.xilinx. and SVF/XSVF files.com 153 . iMPACT can create bit files. System ACE files. including the Platform Cable USB. iMPACT enables you to program through several parallel cables.R Chapter 7 iMPACT Tutorial This chapter takes you on a tour of iMPACT. The SVF/XSVF files can be played backed without having to recreate the chain. This tutorial contains the following sections: • • • • • • • • • “Device Support” “Download Cable Support” “Configuration Mode Support” “Getting Started” “Creating a iMPACT New Project File” “Using Boundary Scan Configuration Mode” “Troubleshooting Boundary Scan Configuration” “Creating an SVF File” “Other Configuration Modes” Device Support The following devices are supported.

If a mask bit is 1.com/support.com/support. a MCS file—an ASCII file that contains PROM configuration information. Configuration Mode Support Impact currently supports the following configuration modes: • • • • Boundary Scan —FPGAs. the bit should not be verified. the bit should be verified against the bit stream data. select Documentation > Data Sheets > Configuration Solutions > Configuration Hardware > Platform Cable USB. go to http://www. For more information.com/support.1 In-Depth Tutorial . and Boundary Scan functionality. MultiPRO Cable The MultiPRO cable connects to the parallel port and can be used to facilitate Desktop Configuration Mode functionality. 154 www. CPLDs.xilinx. This file generated along with the BIT file. and PROMs(18V00.XCFP) Slave Serial—FPGAs (Virtex™/-II/-II PRO/E/4/5 and Spartan™/-II/-IIE/3/3E/3A) SelectMAP—FPGAs (Virtex™/-II/-II PRO/E/4/5 and Spartan™/-II/-IIE/3/3E/3A) Desktop —FPGAs (Virtex™/-II/-II PRO/E/4/5 and Spartan™/-II/-IIE/3/3E/3A) Getting Started Generating the Configuration Files In order to follow this chapter. Platform Cable USB The Platform Cable connects to the USB port and can be used to facilitate Slave Serial. but is used for verification. If a mask bit is 0. but that has mask data in place of configuration data. go to http://www. go to http://www. This data is not used to configure the device. For more information. you must have the following files for the stopwatch design: • • • a BIT file—a binary file that contains proprietary header information as well as configuration data.com ISE 9.xilinx.XCFS.R Chapter 7: iMPACT Tutorial Download Cable Support Parallel Cable IV The Parallel Cable connects to the parallel port and can be used to facilitate Slave Serial and Boundary-Scan functionality.xilinx.xilinx. For more information. select Documentation > Data Sheets > Configuration Solutions > Configuration Hardware > MultiPRO Desktop Tool. a MSK file—a binary file that contains the same configuration commands as a BIT file. select Documentation > Data Sheets > Configuration Solutions > Configuration Hardware > Xilinx Parallel Cable IV.

Be sure that the board is powered.com 155 . ISE 9. Opening iMPACT from Project Navigator To start iMPACT from Project Navigator. and connect the cable to the Spartan-3 Starter Kit demo board. double-click Configure Device (iMPACT) in the Processes tab in the Processes window (see Figure 7-1).xilinx.xilinx.” • The Stopwatch tutorial projects can be downloaded from http://www. • • PC — Click Start > All Programs > Xilinx® ISE 9. “Design Implementation. or Linux — Type impact at a command prompt.1 In-Depth Tutorial www. Verilog or Schematic design flow. PC. Starting the Software This section describes how to start the iMPACT software from ISE™ and how to run it stand-alone.htm. Figure 7-1: Opening iMPACT from ISE Opening iMPACT stand-alone To open iMPACT without going through an ISE project.Getting Started R These files are generated in Chapter 5.com/support/techsup/tutorials/tutorials9. use one of the following methods. Connecting the Cable Prior to launching iMPACT.1i > Accessories > iMPACT. Download the project files for either the VHDL. UNIX. connect the parallel side of the cable to your computer’s parallel port.

Figure 7-2: Creating an iMPACT Project To create a new project for this tutorial: 1.com ISE 9. 5. Click OK.1 In-Depth Tutorial . Using Boundary Scan Configuration Mode For this tutorial. TCK. 3. To perform operations. In the iMPACT Project dialog box. you will be using the Boundary Scan Configuration Mode. This dialog box enables you to load a recent project or to create a new project. which enables you to then manually add devices to create chain. Click the Browse button. limited operations will be available for non-Xilinx devices. Click Save.ipf). Browse to the project directory and then enter stopwatch in the File Name field.R Chapter 7: iMPACT Tutorial Creating a iMPACT New Project File When iMPACT is initially opened. as described in the next section. and is discussed in a later section in this chapter. Note: The selection box also gives you the option to Enter a Boundary Scan Chain.xilinx. This option enables you to generate an SVF/XSVF programming file. You are prompted to define the project. 2. and TDO need to be connected from the cable to the board. you are prompted to specify the configuration mode and which device you would like to program. TMS. select create a new project (. To select Boundary Scan Mode: 1. TDI. the iMPACT Project dialog box displays. This creates a new project file in iMPACT. Select Configure Devices using Boundary-Scan (JTAG) and leave the selection box value of Automatically connect to a cable and identify Boundary-Scan chain. 4. Specifying Boundary Scan Configuration Mode After opening iMPACT. however. the cable must be connected and the JTAG pins. The chain can consist of both Xilinx® and non-Xilinx devices. Automatically detecting and initializing the chain should be performed whenever possible. Boundary Scan Configuration Mode enables you to perform Boundary Scan Operations on any chain comprising JTAG compliant devices. 156 www.

Using Boundary Scan Configuration Mode R 2. Note: If you were not prompted to select a configuration mode or automatic boundary scan mode. Any other device will be labeled as unknown.com 157 . ISE 9. Figure 7-3: Selecting automatic boundary scan from Wizard iMPACT will pass data through the devices and automatically identify the size and composition of the boundary scan chain. right-click in the iMPACT window and select Initialize Chain. Click Finish.xilinx. The software will then highlight each device in the chain and prompt you to assign a configuration file or BSDL file. The software will identify the chain if the connections to the board are working. Go to “Troubleshooting Boundary Scan Configuration” if you are having problems.1 In-Depth Tutorial www. Any supported Xilinx device will be recognized and labeled in iMPACT.

or .mcs. Select the BIT file from your project working directory. . the software prompts you for a configuration file (see Figure 7-4). *.isc) is used to configure an FPGA. *. .bit. You should receive a warning stating that the startup clock has been changed to JtagClk.exo. select Bypass in the Assign New Configuration File dialog box. 2.com ISE 9. When the software prompts you to select a configuration file for the first device (XC3S200): 1. Figure 7-4: Selecting a Configuration File Note: If a configuration file is not available. There are several types of configuration files.isc) is used to configure a CPLD. The configuration file is used to program the device. To have ISE automatically select a BSDL file (for both Xilinx and non-Xilinx devices).1 In-Depth Tutorial . Click Open. • • • A Bitstream file (*.R Chapter 7: iMPACT Tutorial Assigning Configuration Files After initializing a chain. A JEDEC file (*.jed.rbt.tek) is used to configure a PROM. Click OK.xilinx. a Boundary Scan Description File (BSDL or BSD) file can be applied instead. A PROM file (*.hex. The BSDL file provides the software with the necessary Boundary Scan information that allows a subset of the Boundary Scan Operations to be available for that device.*. 3. 158 www.

Using Boundary Scan Configuration Mode R 4. depending on your iMPACT Preferences setting. To see a list of the available options. Click Open. (For more information about Preferences. When the software prompts you to select a configuration file for the second device (XCF02S): Select the MCS file from your project working directory. Editing Preferences To edit the preferences for the Boundary Scan Configuration. To do this. Note: Previous versions of ISE use Configuration Data Files (CDF). you should save your iMPACT Project File (IPF) for later use. This selection opens the window shown in Figure 7-5. Click Help for a description of the Preferences. Saving the Project File Once the chain has been fully described and configuration files are assigned. select File > Open Project and browse to the IPF. The available Boundary Scan operations vary based on the device and the configuration file that was applied to the device. When you select a device and perform an operation on that device. 5.xilinx. These files can still be opened and used in iMPACT. This brings up a window with all of the available options. see “Editing Preferences. right-click on any device in the chain. Figure 7-5: Edit Preferences Performing Boundary Scan Operations You can perform Boundary Scan operations on one device at a time.com 159 . In this tutorial. The Save As dialog box appears and you can browse and save your project file accordingly. select File > Save Project As. iMPACT Project Files can also be exported to a CDF. 6. To restore the chain after reopening iMPACT. keep the default values and click OK. select Edit > Preferences.1 In-Depth Tutorial www. all other devices in the chain are automatically placed in BYPASS or HIGHZ.”) ISE 9.

com ISE 9. Log Window Showing Result of Get Device ID Right-click on the XC3S200 device Select Program from the right-click menu.1 In-Depth Tutorial . Figure 7-6: Available Boundary Scan Operations for an XC3S200 Device The software accesses the IDCODE for this Spartan-3 device. 1. right-click on a device and select one of the options. Right-click on the XC3S200 device. In this section. The result is displayed in the log window (see Figure 7-7). 4.R Chapter 7: iMPACT Tutorial To perform an operation. The Program Options Dialog Box appears (see Figure 7-8). 2. 160 www. you will retrieve the device ID and run the programming option to verify the first device. Figure 7-7: 3. Select Get Device ID from the right-click menu.xilinx.

Using Boundary Scan Configuration Mode

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Select the Verify option. The Verify option enables the device to be readback and compared to the BIT file using the MSK file that was created earlier.

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Click OK to begin programming.

Figure 7-8:

Program Options for XC3S200 Device

Note: The options available in the Program Options dialog box vary based on the device you have selected. After clicking OK, the Program operation begins and an operation status window displays. At the same time, the log window reports all of the operations being performed.

Figure 7-9:

Operation Status

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When the Program operation completes, a large blue message appears showing that programming was successful (see Figure 7-10). This message disappears after a couple of seconds.

Figure 7-10:

Programming Operation Complete

Your design has been programmed and has been verified. The board should now be working and should allow you to start, stop and reset the runner’s stopwatch.

Troubleshooting Boundary Scan Configuration
Verifying Cable Connection
When an error occurs during a Boundary Scan operation, first verify that the cable connection is established and that the software autodetect function is working. If a connection is still not established after plugging the cable into the board and into your machine, right-click in a blank portion of the iMPACT window and select either Cable Auto Connect or Cable Setup. Cable Auto Connect will force the software to search every port for a connection. Cable Setup enables you to select the cable and the port to which the cable is connected.

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Troubleshooting Boundary Scan Configuration

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When a connection is found, the bottom of the iMPACT window will display the type of cable connected, the port attached to the cable, and the cable speed (see Figure 7-11).

Figure 7-11:

Cable Connection Successful

If a cable is connected to the system and the cable autodetection fails, refer to Xilinx Answer Record #15742. Go to http://www.xilinx.com/support and search for “15742”.

Verifying Chain Setup
When an error occurs during a Boundary Scan operation, verify that the chain is set up correctly and verify that the software can communicate with the devices. The easiest way to do this is to initialize the chain. To do so, right-click in the iMPACT window and select Initialize Chain. The software will identify the chain if the connections to the board are working. If the chain cannot be initialized, it is likely that the hardware is not set up correctly or the cable is not properly connected. If the chain can be initialized, try performing simple operations. For instance, try getting the Device ID of every device in the chain. If this can be done, then the hardware is set up correctly and the cable is properly connected. The debug chain can also be used to manually enter JTAG commands (see Figure 7-12). This can be used for testing commands and verifying that the chain is set up correctly. To use this feature, select Debug > Start/Stop Debug Chain in iMPACT.

Figure 7-12:

Debug Chain

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3. You can now add one device at a time. 3. All devices must be represented in the iMPACT window. An Add Device dialog box appears allowing you to select a configuration file. Manual JTAG chain setup for SVF generation For this tutorial. SVF. Note: The boundary scan chain that you manually create in the software must match the chain on the board. 164 www. XSVF. JTAG chain setup for SVF generation 1. 2.com/support. 1. 2. Repeat steps 2 and 3 to add the stopwatch. Creating an SVF File This section is optional and assumes that you have followed the “Using Boundary Scan Configuration Mode” section and have successfully programmed to a board. iMPACT supports the creation of device programming files in three formats.1 In-Depth Tutorial . An informational message appears stating that all device operations will be directed to the . Setting up Boundary Scan Chain This section assumes that you are continuing from the previous sections of this chapter and already have the chain detected.mcs file to the chain. A cable normally does not need to be connected because no operations are being performed on devices. and they are used by ATE machines and embedded controllers to perform Boundary Scan operations.R Chapter 7: iMPACT Tutorial For help using iMPACT Boundary-Scan Debug.xilinx. all of the configuration information is written to the SVF file.bit and then click Open. you may skip this section if you completed the “Using Boundary Scan Configuration Mode. These programming files contain both programming instructions and configuration data.svf file. Select Output > SVF File > Create SVF File to indicate that you are creating a programming file. or file a Web case at http://www. Right-click on an empty space in the iMPACT Boundary-Scan window and select Add Xilinx Device or Add Non-Xilinx device.com ISE 9. use the iMPACT Help (accessible from Help > Help Topics).xilinx. To add a device between existing devices. click on the line between them and then add the new device. In this section. The device is added where the large cursor is positioned. The Boundary-Scan chain can be manually created or modified as well. Enter getid in the File Name field of the Create a New SVF File dialog box and click Save. Select stopwatch. skip to “Manual JTAG chain setup for SVF generation” to define the chain manually. If you are using third-party programming solutions. If not. To do this. Ensure that you are in Boundary Scan Mode (click the Boundary-Scan tab). you may need to set up your Boundary Scan chain manually and then create a device programming file. even if you intend to program only some of the devices. and STAPL.” section. Click OK.

1 In-Depth Tutorial www. Any number of operations can be written to an SVF file. Select Get Device ID from the right-click menu. You simply right-click on a device and select an operation. Right-click the first device (XC3S200). In this section. To write the device ID: 1. To see the results. Figure 7-13: Selecting a Boundary Scan Operation The instructions that are necessary to perform a Get Device ID operation are then written to the file. select View > View SVF-STAPL File. 2. you will be writing the device ID to the programming file for the first device. 3. and performing further instructions for the second device. Figure 7-14 shows what the SVF file looks like after the Get Device ID operation is performed. Figure 7-14: SVF File that Gets a Device ID from the First Device in the Chain ISE 9.com 165 .xilinx.Creating an SVF File R Writing to the SVF File The process of writing to an SVF file is identical to performing Boundary Scan operations with a cable.

R Chapter 7: iMPACT Tutorial To write further instructions to the SVF for the second device: 1. Available Boundary Scan Operations for a XCF02S Device Click OK in the Programming Properties window. Playing back the SVF or XSVF file To play back the SVF file that you created to verify the instructions. Figure 7-15: 3.com ISE 9. Assign the SVF file to the chain by right clicking and selecting Add Xilinx Device and selecting the SVF file in the search window.1 In-Depth Tutorial . 166 www. To stop writing to the programming file: Select Output > SVF File > Stop Writing to SVF File. Right-click the second device (XCF02S). Right-click on the SVF file in the Boundary-Scan chain and select Execute XSVF/SVF. you can select Output > SVF File > Append to SVF File. Stop Writing to the SVF After all the desired operations have been performed. select the SVF file and click Save. you must add an instruction to close the file from further instructions. double-click Slave Serial in the Configuration Modes tab. you will • • • Manually create a new chain. To add other operations in the future. To use the Slave Serial Configuration Mode. Other Configuration Modes Slave Serial Configuration Mode Slave Serial Configuration mode allows you to program a single Xilinx device or a serial chain of Xilinx devices.xilinx. 2. Select Program from the right-click menu.. The instructions and configuration data needed to program the second device are added to the SVF file.

To use the SelectMAP Configuration Mode. double click SelectMAP in the Configuration Modes tab.com 167 .1 In-Depth Tutorial www. Note: These modes cannot be used with the Spartan-3 Starter Kit. SelectMAP Configuration mode allows you to program up to three Xilinx devices. The devices are programmed one at a time and are selected by the assertion of the correct CS pin.Other Configuration Modes R SelectMAP Configuration Mode With iMPACT.xilinx. ISE 9. Only the MultiPRO cable can be used for SelectMAP Configuration.

R Chapter 7: iMPACT Tutorial 168 www.com ISE 9.xilinx.1 In-Depth Tutorial .

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