ISE In-Depth Tutorial

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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring failsafe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. Copyright © 1995-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.

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Preface

About This Tutorial
About the In-Depth Tutorial
This tutorial gives a description of the features and additions to Xilinx® ISE™ 9.1i. The primary focus of this tutorial is to show the relationship among the design entry tools, Xilinx and third-party tools, and the design implementation tools. This guide is a learning tool for designers who are unfamiliar with the features of the ISE software or those wanting to refresh their skills and knowledge. You may choose to follow one of the three tutorial flows available in this document. For information about the tutorial flows, see “Tutorial Flows.”

Tutorial Contents
This guide covers the following topics. • • • Chapter 1, “Overview of ISE and Synthesis Tools,” introduces you to the ISE primary user interface, Project Navigator, and the synthesis tools available for your design. Chapter 2, “HDL-Based Design,” guides you through a typical HDL-based design procedure using a design of a runner’s stopwatch. Chapter 3, “Schematic-Based Design,” explains many different facets of a schematicbased ISE design flow using a design of a runner’s stopwatch. This chapter also shows how to use ISE accessories such as StateCAD, CORE Generator™, and ISE Text Editor. Chapter 4, “Behavioral Simulation,” explains how to simulate a design before design implementation to verify that the logic that you have created is correct. Chapter 5, “Design Implementation,” describes how to Translate, Map, Place, Route (Fit for CPLDs), and generate a Bit file for designs. Chapter 6, “Timing Simulation,” explains how to perform a timing simulation using the block and routing delay information from the routed design to give an accurate assessment of the behavior of the circuit under worst-case conditions. Chapter 7, “iMPACT Tutorial” explains how to program a device with a newly created design using the IMPACT configuration tool.

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ISE 9.1 In-Depth Tutorial

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“Timing Simulation” Note that although timing simulation is optional. “Behavioral Simulation” Note that although behavioral simulation is optional. Chapter 7.R Preface: About This Tutorial Tutorial Flows This document contains three tutorial flows. “HDL-Based Design” Chapter 4. it is strongly recommended in this tutorial flow. in order to help you determine which sequence of chapters applies to your needs. “Timing Simulation” Note that although timing simulation is optional. “Design Implementation” Chapter 6. Chapter 5. it is strongly recommended in this tutorial flow. it is strongly recommended. The tutorial flows include: • • • HDL Design Flow Schematic Design Flow Implementation-only Flow HDL Design Flow The HDL Design flow is as follows: • • Chapter 2. Chapter 7. the three tutorial flows are outlined and briefly described. “iMPACT Tutorial” • • • Implementation-only Flow The Implementation-only flow is as follows: • • Chapter 5. Chapter 7. Chapter 5. “iMPACT Tutorial” • • • Schematic Design Flow The Schematic Design flow is as follows: • • Chapter 3. “Behavioral Simulation” Note that although behavioral simulation is optional.xilinx. “iMPACT Tutorial” • 4 www.com ISE 9. “Design Implementation” Chapter 6.1 In-Depth Tutorial . it is strongly recommended in this tutorial flow. In this section. “Timing Simulation” Note that although timing simulation is optional. it is strongly recommended in this tutorial flow. “Design Implementation” Chapter 6. “Schematic-Based Design” Chapter 4.

see the Xilinx website at: http://www. ISE 9.com/literature. To search the Answer Database of silicon.xilinx. and IP questions and answers.Additional Resources R Additional Resources To find additional documentation.1 In-Depth Tutorial www.xilinx.xilinx.com/support.com 5 . software. see the Xilinx website at: http://www. or to create a technical support WebCase.

xilinx.R Preface: About This Tutorial 6 www.1 In-Depth Tutorial .com ISE 9.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restoring an Archive . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic Editor . . . . . . . . . . . . . . . 5 Chapter 1: Overview of ISE and Synthesis Tools Overview of ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Tutorial Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precision Synthesis. . . . . . . . . . . . . . . . Creating a Snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISE Simulator / Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Project Archives . . . . . . . . Sources Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Navigation to Answer Record . . . . . . . . . . 4 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processes Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Snapshots Tab . . . . . . . . . Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Navigation to Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synplify/Synplify Pro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restoring a Snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Text Editor . . . . . . . . . . . . . . . . . . Xilinx Synthesis Technology (XST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Table of Contents Preface: About This Tutorial About the In-Depth Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Importing a Project . . . . . . . . . 3 HDL Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Snapshots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 In-Depth Tutorial www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Properties . . . . . . . Exporting a Project . . . . . . . . . . . . . . . . . . . . . . . . . .com 1-800-255-7778 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing a Snapshot . . . . . . . . . . . . . 13 14 14 15 15 15 15 16 16 16 17 17 17 17 17 17 17 17 18 18 18 18 18 18 19 19 19 20 20 20 20 Using Revision Control Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Implementation-only Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sources Window . . . . . . . . . . Creating an Archive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transcript Window . . . . . . . . . . . . . . . . . . . . Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Export/Import Source Control . . . . . . . . . . . . . . 4 Schematic Design Flow . . . . . 13 Project Navigator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processes Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ISE 9. . . . . . . . . . . . . . Libraries Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Tutorial Contents . 17 Overview of Synthesis Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xilinx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . 24 24 24 24 25 25 25 27 27 Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Getting Started . . . . . . . . . . . . . .R Chapter 2: HDL-Based Design Overview of HDL-Based Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a New Project: Using a Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Design Entry . Examining Synthesis Results . . . . . . . . . . . . . . . . . . 29 Adding Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Correcting HDL Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Required Software . . Optional Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Functional Blocks . . 51 Required Software . . . . 43 Chapter 3: Schematic-Based Design Overview of Schematic-Based Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instantiating the dcm1 Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Installing the Tutorial Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Clocking Wizard . . . . . . . . Entering Synthesis Options . Synthesizing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a CORE Generator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .com 1-800-255-7778 ISE 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizing the Design using XST . . . . . . . . . . . . . . . . . . . . . . . . 23 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Starting the ISE Software . . . . . . . . . . . . . The RTL / Technology Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a New Project: Using New Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an HDL-Based Module . . . . . . . Entering Constraints . . . . . . . . . . . . . . . . . . . . . . . 30 30 31 32 32 34 35 36 36 38 39 39 41 42 44 44 45 45 45 47 47 48 49 49 Synthesizing the Design . . . . Adding a Language Template to Your File . . . . . . . . . . . . . . . . . . . . 51 52 52 52 53 8 www. . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizing the Design Using Precision Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instantiating the dcm1 Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The RTL/Technology Viewer . . . . . . . . . . . . . . . VHDL or Verilog? . . . . . . . Creating a New Project: Using the New Project Wizard . . . . . . . . . . . . . . . . . . . .Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking the Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the New Source Wizard and ISE Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 In-Depth Tutorial . . . .VHDL Design . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a CORE Generator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Language Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Starting the ISE Software . . . . . . . . Installing the Tutorial Project Files . . Entering Synthesis Options through ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xilinx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizing the Design using Synplify/Synplify Pro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instantiating the CORE Generator Module in the HDL Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a DCM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stopping the Tutorial . . . . . . . . . . . . . . . . . . .

. . . . . . . . Drawing Wires . . . . Adding I/O Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a State Machine Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Clocking Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dcm1 and debounce Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Stopping the Tutorial . . . . . . . . Adding Bus Taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking the Schematic . Completing the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Schematic Components . . . . . . . . . . . . . . . . . . Defining the time_cnt Schematic . . . . . . . . . . . . . . Creating and Placing the time_cnt Symbol . . . . . . . . . . . . . Creating the debounce Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xilinx. . . . . . . . Adding Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding a State Machine Reset Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding a Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the New Source Wizard and ISE Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Schematic-Based Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Correcting Mistakes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Opening the Schematic File in the Xilinx Schematic Editor. . . .R Creating a New Project: Using a Tcl Script . . . Adding New States . . . . . . . . . . . . . . . . . Using the Language Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 In-Depth Tutorial www. . . . . . . . . . . . . . . . Assigning Pin Locations . 56 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Placing the statmach. . . . . . . . . . Creating a DCM Module . . . . . . . . . . . . . . . . . . . . . 91 ModelSim Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding I/O Markers and Net Names. . . . . . . . . . . . . . . . . . . . . 91 ISE 9. . . . . . . . . . . . . . Adding Net Names . . . 57 58 58 59 60 60 63 63 63 64 65 66 67 67 67 67 68 68 70 71 72 73 75 75 76 76 76 78 79 79 81 82 83 83 84 85 85 85 86 87 87 Chapter 4: Behavioral Simulation Overview of Behavioral Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating the State Machine HDL output file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating the State Machine Symbol . . . . . . . . . Hierarchy Push/Pop . . . . . . . . . . . . . . . . . . . . . . . . . . timer_preset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manipulating the Window View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Placing the time_cnt Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding a State Action . . . . . . . . . . . . . . . . . . . . . . . . . . . Changing Instance Names . . . . . . . . . . . . . . . . . Adding a Language Template to Your File . . . . . Creating the time_cnt symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Device Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an HDL-Based Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a CORE Generator Module . . . . . . . . . . . . . . . . . . . 55 Outputs . . .com 1-800-255-7778 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a CORE Generator Module . . . . . . . . . . . . . . . . . . . . . . . Creating the dcm1 Symbol . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .com 1-800-255-7778 ISE 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Behavioral Simulation Using ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ModelSim Xilinx Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Analyzing the Signals . . . . . . . . . . . . . . . . . . Using Timing Analysis to Evaluate Block Delays After Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Locating the Simulation Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Continuing from Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Bench File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Simulation . . . . . 92 92 92 92 93 93 93 Adding an HDL Test Bench . . . . . . . . . . . . . . . . . . . . . 96 Performing Simulation . . . . . . . . 111 113 114 115 116 120 123 126 Estimating Timing Goals with the 50/50 Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Saving the Simulation . . 94 Adding Tutorial Test Bench File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .R ModelSim PE and SE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xilinx. . . . . . . . . . . .ini File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Signals . . . . . . . 94 Verilog Simulation . . . . . . . . . 97 Adding Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mapping the Design . . . . . . . . 101 Behavioral Simulation Using ISE Simulator . . . . Design Files (VHDL. 97 Adding Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Simulation Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 In-Depth Tutorial . . . . . . . . . 94 VHDL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ISE Simulator Setup . . . . . . . . . . . . . . . . . . . . . Updating the Xilinx Simulation Libraries . . . . . . . . . . . . . . . . . . . . . . 110 Starting from Design Implementation . . . 101 Locating the Simulation Processes . . . . . 99 Rerunning Simulation . . . . . . . 92 Required Files . . . . . . . . . . . . . . . . Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Test Bench Waveform Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or Schematic) . . . . . . . . . . . . . . . . . . . . . . . . . . . Rerunning Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Constraints Editor . . . . . . . . . . . . . . . . . . . . . . . . 101 102 103 103 104 105 105 105 107 Chapter 5: Design Implementation Overview of Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Specifying Simulation Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10 www. . . Translating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mapping Simulation Libraries in the Modelsim. . . Xilinx Simulation Libraries . . . . . . . . . . . . . . . . Xilinx Simulation Libraries . . . . . . . . . . 109 Getting Started . . . . . . . . . . . . . . . . . . . . . Using the Floorplan Editor . . . . . . . . . . Applying Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Specifying Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Getting Started . . . . . . . . . . . . . . . . . Creating a Test Bench Waveform Using the Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 139 Required Software . . . . . . . . . . . . . . . . . . . . . . . . . .R Report Paths in Timing Constraints Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 143 143 145 146 146 147 148 149 149 150 150 151 Timing Simulation Using Xilinx ISE Simulator . . . Creating Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 155 155 155 155 Creating a iMPACT New Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Platform Cable USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opening iMPACT stand-alone . . . . . . . . . . . . . . . . . . . . . . . . . 156 Specifying Boundary Scan Configuration Mode . . . . . . . . . . . . . . . . . . 154 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting the Cable . . . . . . . . . . . . . . . . . . 127 129 131 132 134 135 138 Chapter 6: Timing Simulation Overview of Timing Simulation Flow . . . . . . . . . . . . . . . . . 139 Getting Started . . . . . . . . . . . . . . . . . . . . . . Adding Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analyzing the Signals . . . . . . . 158 ISE 9. . . . . . . . . . . . . . . . . . . . . . Starting the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .com 1-800-255-7778 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Download Cable Support . . . . . . Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opening iMPACT from Project Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Generating the Configuration Files . . . . . . Specifying Simulation Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using FPGA Editor to Verify the Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Configuration Mode Support . . . . . . . . . . . . 156 Assigning Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Required Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Full Signal Names. . . . . . . . . . . . . . . . 154 Parallel Cable IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rerunning Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Placing and Routing the Design . . . . . . . . . . . . . . . . . .xilinx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Timing Simulation Using ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rerunning Simulation . . . . . . . .1 In-Depth Tutorial www. . . . . . . . . 154 MultiPRO Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Chapter 7: iMPACT Tutorial Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a PROM File with iMPACT . . . . . . . . . . . . . . . . . . . . . . . . Changing HDL with Partition . Saving the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Specifying a Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Specifying Simulation Process Properties . . . . . . . . Evaluating Post-Layout Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Using Boundary Scan Configuration Mode . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Verifying Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG chain setup for SVF generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Slave Serial Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Editing Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Setting up Boundary Scan Chain . . . . . . . . . . . . . . . . .1 In-Depth Tutorial . . . . . . . . 159 Performing Boundary Scan Operations . . . . . . . . . . . . . . 166 SelectMAP Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . Writing to the SVF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .com 1-800-255-7778 ISE 9. . . 162 Verifying Chain Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .R Saving the Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12 www. . . . . . . . . . . . . . Playing back the SVF or XSVF file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Troubleshooting Boundary Scan Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manual JTAG chain setup for SVF generation . . . . . . . .xilinx. . . . . . . . . . . . . . . . . . . . . . . . . . 163 Creating an SVF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Writing to the SVF. . 164 164 164 165 166 166 Other Configuration Modes . . . .

xilinx. errors. ISE 9. you can access all of the design entry and design implementation tools. and simulation waveforms. which displays available processes for the currently selected source. schematics. These windows are discussed in more detail in the following sections.R Chapter 1 Overview of ISE and Synthesis Tools This chapter includes the following sections: • • • “Overview of ISE” “Using Revision Control Features” “Overview of Synthesis Tools” Overview of ISE ISE controls all aspects of the design flow. Through the Project Navigator interface. Each window may be resized. You can also access the files and documents associated with your project. The third window at the bottom of the Project Navigator is the Transcript window which displays status messages. Beneath the Sources window is the Processes window. and warnings and also contains interactive tabs for Tcl scripting and the Find in Files function. On the top left is the Sources window which hierarchically displays the elements included in the project.1 In-Depth Tutorial www. Project Navigator Interface The Project Navigator Interface is divided into four main subwindows. The fourth window to the right is a multi-document interface (MDI) window refered to as the Workspace.com 13 . It enables you to view html reports. undocked from Project Navigator or moved to a new location within the main Project Navigator window. as seen in Figure 1-1. The default layout can always be restored by selecting View > Restore Default Layout. ASCII text files.

com ISE 9. “Design Implementation”. The Design View (“Sources for”) drop-down list at the top of the Sources tab allows you to view only those source files associated with the selected Design View. such as Synthesis/Implementation. 14 www. In the “Number of” drop-down list.xilinx. the specified device. Each tab is discussed in further detail below. Sources Tab The Sources tab displays the project name.1 In-Depth Tutorial .R Chapter 1: Overview of ISE and Synthesis Tools Figure 1-1: Project Navigator Sources Window This window consists of three tabs which provide project and file information for the user. The use of partitions is covered in Chapter 5. and user documents and design source files associated with the selected Design View. a Resources column and a Preserve Column are available for Designs that use Partitions.

” If a file contains lower levels of hierarchy. and the snapshot can be viewed in the Snapshots tab. ISE 9. and source files for all snapshots. Select Help > ISE Help Contents. run and view your design. viewing command line history. and synthesis and simulation sub-directories. Snapshots Tab The Snapshots tab displays all snapshots associated with the project currently open in Project Navigator. and synthesis reports. Using snapshots provides an excellent version control system. and simulation library compilation. the icon has a + to the left of the name. For a complete list of possible source types and their associated icons. or text file. Available processes vary depending on the synthesis tools you use.com 15 . see the ISE™ Help. schematic. View RTL or Technology Schematic. A snapshot is stored with the project for which it was taken.xilinx. You can expand the hierarchy by clicking the +. The icon indicates the file type (HDL file. You can view the reports. • • User Constraints Provides access to editing location and timing constraints. Synthesis Provides access to Check Syntax. you can run the functions necessary to define. You can open a file for editing by double-clicking on the filename. select the Index tab and search for “Source file types. The Processes tab provides access to the following functions: • • • • Add an Existing Source Create New Source View Design Summary Design Utilities Provides access to symbol generation. Processes Tab The Processes tab is context sensitive and it changes based upon the source type selected in the Sources tab and the Top-Level Source in your project. core. All information displayed in the Snapshots tab is read-only. enabling subteams to do simultaneous development on the same design.1 In-Depth Tutorial www. Processes Window This window contains one default tab called the Processes tab. From the Processes tab. for example). A snapshot is a copy of the project including all files in the working directory.Overview of ISE R Each file in a Design View has an associated icon. HDL files have this + to show the entities (VHDL) or modules (Verilog) within the file. Synthesis. instantiation templates. user documents. Libraries Tab The Libraries tab displays all libraries associated with the project open in Project Navigator.

and select Go to Answer Record from the right-click menu.1 In-Depth Tutorial . warnings.The HDL source file opens and the cursor moves to the line with the error. Transcript Window The Transcript window contains five default tabs: Console. Error Navigation to Source You can navigate from a synthesis error or warning message in the Transcript window to the location of the error in a source HDL file. • • • Warnings Displays only warning messages. when you run the Implement Design process. 16 www. Tcl Shell. see the ISE Help. Find in Files. Note: To view a running log of command line arguments used on the current project. This enables the user to select any process in the flow and the software automatically runs the processes necessary to get to the desired step. Generate Programming File Provides access to configuration tools and bitstream generation. Errors Displays only error messages. To navigate to the Answer Record(s). and point tools. Errors are signified by a red (X) next to the message. In addition to displaying errors. warnings and informational messages. select the error or warning message. expand Design Utilities and select View Command Line Log File. The default web browser opens and displays all Answer Records applicable to this message. the Tcl Shell allows a user to enter Project Navigator specific Tcl commands. For more information on Tcl commands. right-click the mouse. • Console Displays errors. and select Go to Source from the right-click menu.com ISE 9.xilinx. design flow reports. right-click the mouse. Error Navigation to Answer Record You can navigate from an error or warning message in the Transcript window to relevant Answer Records on the www. while warnings have a yellow exclamation mark (!). The Processes tab incorporates automake technology. For example. Project Navigator also runs the Synthesis process because implementation is dependent on up-todate synthesis results. Warnings.R Chapter 1: Overview of ISE and Synthesis Tools • • Implement Design Provides access to implementation tools. select the error or warning message. Errors.xilinx. Other console messages are filtered out. Other console messages are filtered out. “Design Implementation” for further details. • Find in Files Displays the results of the Edit > Find in Files function. Tcl Shell Is a user interactive console. See the Command Line Implementation section of Chapter 5. To do so. and information messages.com/support website.

In the Take a Snapshot of the Project dialog box. The Schematic Editor can be used to graphically create and view logical designs. Using Revision Control Features Using Snapshots Snapshots enable you to maintain revision control over the design. When you restore a snapshot.1 In-Depth Tutorial www. a snapshot must be restored in order to continue work. enter the snapshot name and any comments associated with the snapshot. Schematic Editor The Schematic Editor is integrated in the Project Navigator framework. Text Editor Source files and other text documents can be opened in a user designated editor. Verilog. 2. See also “Snapshots Tab. You can access the Language Templates.” Creating a Snapshot To create a snapshot: 1. Waveform Editor can be used to graphically enter stimuli and the expected response. VHDL. including overview information. constraints information. then generate a VHDL test bench or Verilog test fixture. which is a catalog of ABEL.xilinx. Restoring a Snapshot Since snapshots are read-only. For details. ISE 9. A snapshot contains a copy of all of the files in the project directory. ISE Simulator / Waveform Editor ISE Simulator / Waveform Editor can be used to create and simulate test bench and test fixture within the Project Navigator framework. Select Project > Take Snapshot. The editor is determined by the setting found by selecting Edit > Preferences. performance data gathered from the Place & Route (PAR) report. expand ISE General and click Editors. it replaces the project in your current session. The snapshot containing all of the files in the project directory along with project settings is displayed in the Snapshots tab. The default editor is the ISE Text Editor. and summary information from all reports with links to the individual reports. refer to“Creating a Test Bench Waveform Using the Waveform Editor” in Chapter 4. Tcl and User Constraints File templates that you can use and modify in your own design. a device utilization summary.Using Revision Control Features R Workspace Design Summary The Design Summary lists high-level information about your project.com 17 . ISE Text Editor enables you to edit source files and user documents.

Remote sources are included in the archive under a folder named remote_sources . Using Project Archives You can also archive the entire project into a single compressed file. Select Project > Source Contorl > Export 18 www. enter the archive name and location.1 In-Depth Tutorial . Select Project > Make Snapshot Current. Before the snapshot replaces the current project. These files will need to be manually copied to the original location or added to the project again in a new directory Viewing a Snapshot The Snapshots tab contains a list of all the snapshots available in the current project. 2.” The Export/Import processes are typically used in conjunction with a 3rd party source control system but can be used independently as a valid means of backing up a design. To review a process report or verify process status within a snapshot: 1. Right-click the mouse over the desired process report. Using Export/Import Source Control You can use this feature to export to and retrieve project files and sources from a “staging area. you are given the option to place the current project in a snapshot so that your work is not lost. see the ISE Help. Expand the snapshot source tree and select the desired source file. From the menu. select the snapshot from the drop-down list. For more information. Restoring an Archive You cannot restore an archived file directly into Project Navigator. 3. In the Create Zip Archive dialog box.R Chapter 1: Overview of ISE and Synthesis Tools To restore a snapshot: 1. Exporting a Project To export a project 1. Select Project > Archive.com ISE 9. This allows for easier transfer over email and storage of numerous projects in a limited space. 2. Creating an Archive To create an archive: 1. select Open Without Updating. 2.xilinx. Note: Remote sources are copied with the snapshot and placed in a subdirectory named remote_sources. The compressed file can be extracted with any ZIP utility and you can then open the extracted file in Project Navigator. In the Snapshots tab. Note: The archive contains all of the files in the project directory along with project settings.

Overview of Synthesis Tools

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Follow the Export Project Wizard to dertermine which files to export, where to export the files to, and optionally create a Tcl script that can be used to regenerate the ISE project.

Importing a Project
To import a project 1. 2. Select Project > Source Contorl > Import Select the Project File (.ise or Tcl import script) and directory location to import the project file and sources.

Overview of Synthesis Tools
You can synthesize your design using various synthesis tools. The following section lists the supported synthesis tools and includes some process properties information.

Precision Synthesis
This synthesis tool is not part of the ISE package and is not available unless purchased separately. Two commonly used properties are Optimization Goal and Optimization Effort. With these properties you can control the synthesis results for area or speed and the amount of time the synthesizer runs.This synthesis tool is available for both an HDL- and Schematic-based design flow.

Process Properties
Process properties enable you to control the synthesis results of Precision. Most of the commonly used synthesis options available for the Precision stand-alone version are available for Precision synthesis through ISE. For more information, see the Precision online help.

Figure 1-2:

Precision Synthesis Process Properties

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Chapter 1: Overview of ISE and Synthesis Tools

Synplify/Synplify Pro
This synthesis tool is not part of the ISE package and is not available unless purchased separately. This synthesis tool is available for HDL-based designs, but it is not available for a schematic-based design.

Process Properties
Process properties enable you to control the synthesis results of Synplify/Synplify Pro. Most of the commonly used synthesis options available in the Synplify/Synplify Pro stand-alone version are available for Synplify/Synplify Pro synthesis through ISE. For more information, see the Synplify/Synplify Pro online help.

Figure 1-3:

Synplify/Synplify Pro Synthesis Process Properties

Xilinx Synthesis Technology (XST)
This synthesis tool is part of the ISE package and is available for both an HDL- and Schematic-based design flow.

Process Properties
Process properties enable you to control the synthesis results of XST. Two commonly used properties are Optimization Goal and Optimization Effort. With these properties you can control the synthesis results for area or speed, and the amount of time the synthesizer runs. More detailed information is available in the XST User Guide, available in the collection of software manuals. From ISE, select Help > Software Manuals, or go on the web at http://www.xilinx.com/support/sw_manuals/xilinx9/.

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Figure 1-4:

XST Synthesis Process Properties

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1 In-Depth Tutorial .R Chapter 1: Overview of ISE and Synthesis Tools 22 www.com ISE 9.xilinx.

You can synthesize the design using Xilinx Synthesis Technology (XST). “Design Implementation”). This chapter is the first chapter in the “HDL Design Flow. run implementation with the Xilinx Implementation Tools (Chapter 5.1 In-Depth Tutorial www. software features. and design flow practices you can apply to your own design. however. or Precision.com 23 . This design targets a Spartan™-3A device. you will perform behavioral simulation (Chapter 4. and configure and download to the Spartan-3A demo board (Chapter 7. Synplify/Synplify Pro. ISE 9. unless otherwise noted. “iMPACT Tutorial”). all of the principles and flows taught are applicable to any Xilinx® device family. The design is composed of HDL elements and two cores.xilinx.” After the design is successfully defined.R Chapter 2 HDL-Based Design This chapter includes the following sections: • • • • • “Overview of HDL-Based Design” “Getting Started” “Design Description” “Design Entry” “Synthesizing the Design” Overview of HDL-Based Design This chapter guides you through a typical HDL-based design procedure using a design of a runner’s stopwatch. perform timing simulation (Chapter 6. “Behavioral Simulation”). “Timing Simulation”). The design example used in this tutorial demonstrates many device features.

7 (or above) The following third-party simulation tool is optional for this tutorial.R Chapter 2: HDL-Based Design Getting Started The following sections describe the basic requirements for running the tutorial.com/support/techsup/tutorials/tutorials9. substitute your installation path for c:\xilinx91i in the procedures that follow. and the tutorial files are copied into the newlycreated directory.1 In-Depth Tutorial .8. Installing the Tutorial Project Files The Stopwatch tutorial projects can be downloaded from http://www. 24 www. After you have downloaded the tutorial project files from the Web. noting differences where applicable. You will need to decide which HDL language you would like to work through for the tutorial. and may be used in place of the ISE Simulator: • ModelSim VHDL or Verilog? This tutorial supports both VHDL and Verilog designs.xilinx. XST can synthesize a mixed-language design. and may be used in place of the Xilinx Synthesis Tool (XST): • • Synplicity Synplify/Synplify PRO 8. and download the appropriate files for that language.02 (or above) Mentor Precision Synthesis 2006a2. refer to the ISE Release Notes and Installation Guide. This tutorial assumes that the software is installed in the default location c:\xilinx91i. you must have the following software and software components installed: • • Xilinx Series ISE™ 9. this tutorial does not go over the mixed language feature. Optional Software Requirements The following third-party synthesis tools are incorporated into this tutorial. and applies to both designs simultaneously. However. unzip the tutorial projects into the c:\xilinx\ISEexamples directory.1i Spartan-3A libraries and device files Note: For detailed software installation instructions. Download either the VHDL or the Verilog design flow project files.xilinx.com ISE 9. Required Software To perform this tutorial. If you have installed the software in a different location. When you unzip the tutorial project files into c:\xilinx\ISEexamples. the directory wtut_vhd (for a VHDL design flow) or wtut_ver (for a Verilog design flow) is created within c:\xilinx\ISEexamples.htm. replacing any existing files in that directory.

Table 2-1: Tutorial Directories Directory wtut_vhd wtut_ver wtut_vhd\wtut_vhd_comple ted wtut_ver\wtut_ver_comple ted Description Incomplete VHDL Source Files Incomplete Verilog Source Files Completed VHDL Source Files Completed Verilog Source Files Note: Do not overwrite any files in the solution directories.com 25 .1i > Project Navigator. ISE 9. Use either method provided below.1 In-Depth Tutorial www. The New Project Wizard appears. The completed directories contain the finished HDL source files.xilinx. From Project Navigator. Starting the ISE Software To start ISE: Double-click the ISE Project Navigator icon on your desktop or select Start > All Programs > Xilinx ISE 9. If you unzip the files into a different location. but you can unzip the source files into any directory with read-write permissions. Figure 2-1: Project Navigator Desktop Icon Creating a New Project Note: Two methods are provided for creating a new project: Using the New Project Wizard and Using a Tcl Script. This tutorial assumes that the files are unzipped under c:\xilinx\ISEexamples. substitute your project path for c:\xilinx\ISEexamples in the procedures that follow. Creating a New Project: Using the New Project Wizard 1.Getting Started R The following table lists the locations of tutorial source files. select File > New Project.

Verify that HDL is selected as the Top-Level Source Type and click Next. In the Project Location field.1 In-Depth Tutorial .Device Properties 26 www.Device Properties window appears.xilinx. The New Project Wizard .R Chapter 2: HDL-Based Design Figure 2-2: New Project Wizard . 3.Create New Project 2. browse to c:\xilinx\ISEexamples or to the directory in which you installed the project. Figure 2-3: New Project Wizard . 4.com ISE 9. Type wtut_vhd or wtut_ver in the Project Name field.

tcl (VHDL design entry) or source create_wtut_ver. Click Next. right-click on the device line and select Properties. Change the Preferred Language: to VHDL. In the Adding Source Files dialog box. then click OK. Creating a New Project: Using a Tcl Script 1. then Next.xilinx. (VHDL only) Once the project is created and opened.1 In-Depth Tutorial www. Stopping the Tutorial You may stop the tutorial at any time and save your work by selecting File > Save All. 3. This will determine the default language for all processes that generate HDL files.Device Properties window: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Product Category: All Family: Spartan3A and Spartan3AN Device: XC3S700A Package: FG484 Speed: -4 Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: VHDL or Verilog depending on preference. 7. Change the current working directory to the directory where the tutorial source files were unzipped by typing cd c:/xilinx/ISEexamples/wtut_vhd (VHDL design entry) or cd c:/xilinx/ISEexamples/wtut_ver (Verilog design entry). With Project Navigator open. 4. Run the project creation Tcl script by typing source create_wtut_vhd. then Finish to complete the New Project Wizard. 6. 8. Select the following values in the New Project Wizard . select the Tcl Shell tab.. 2. Select the following files (.Add Existing Sources window.v files for Verilog design entry) and click Open. 10. ♦ ♦ ♦ ♦ clk_div_262k lcd_control statmach stopwatch 9. and then click Add Source in the New Project Wizard .Getting Started R 5.tcl (Verilog design entry). verify that all added HDL files are associated with Synthesis/Imp + Simulation.com 27 . Browse to c:\xilinx\ISEexamples\wtut_vhd or c:\xilinx\ISEexamples\wtut_ver. This will determine the default language for all processes that generate HDL files..vhd files for VHDL design entry or . ISE 9. Click Next.

you will simulate it to verify the design’s functionality. This is an active low signal which acts like the start/stop button on a runner’s stopwatch. The design begins as an unfinished design. there are five external inputs and four external output buses. lcd_rs. you will complete the design by generating some of the modules from scratch and by completing others from existing files. Functional Blocks The completed design consists of the following functional blocks. • strtstop Starts and stops the stopwatch.1 In-Depth Tutorial . In clocking mode it displays the current clock value in the ‘Lap’ display area. The lower-level macros are either HDL modules or IP modules. • • • reset Puts the stopwatch in clocking mode and resets the time to 0:00:00.com ISE 9.xilinx. This input is only functional while the clock or timer is not counting. Throughout the tutorial. HDL-based design. Outputs The following are outputs signals for the design. In timer mode it loads the pre assigned values from the ROM to the timer display when the timer is not counting. The system clock is an externally generated signal. • lap_load This is a dual function signal. The following list summarizes the input and output signals of the design. lcd_rw These outputs are the control signals for the LCD display of the Spartan-3A demo board used to display the stopwatch times. Inputs The following are input signals for the tutorial stopwatch design.R Chapter 2: HDL-Based Design Design Description The design used in this tutorial is a hierarchical. clk Externally generated system clock. • lcd_e. • sf_d[7:0] Provides the data values for the LCD display. which means that the top-level design file is an HDL file that references several other lower-level macros. mode Toggles between clocking and timer modes. In the runner’s stopwatch design. When the design is complete. • clk_div_262k 28 www.

the Sources tab displays all of the source files currently added to the project. You will create and use each type of design macro. you will examine HDL files. Converts 26. All procedures used in the tutorial can be used later for your own designs. frequency controlled output. With the wtut_vhd.Design Entry R Macro which divides a clock frequency by 262. In the current project.144. This macro contains 64 preset times from 0:00:00 to 9:59:99 which can be loaded into the timer. mode. Design Entry For this hierarchical design. time_cnt is instantiated. correct syntax errors. • • lcd_control Module controlling the initialization of and output to the LCD display. create an HDL macro. ISE 9. • dcm1 Clocking Wizard macro with internal feedback. with the associated entity or module names (see Figure 2-4). • time_cnt Up/down counter module which counts between 0:00:00 to 9:59:99 decimal. statmach State Machine module defined and implemented in State Diagram Editor.xilinx. and add a CORE Generator and a Clocking module. This macro has five 4-bit outputs.1 In-Depth Tutorial www.2144 MHz.2144 MHz clock into 100 Hz 50% duty cycle clock.com 29 . and lap_load input signals. Controls the state of the stopwatch. The CLKFX_OUT output converts the 50 MHz clock of the Spartan-3A demo board to 26. • timer_preset CORE Generator™ 64x20 ROM. which represent the digits of the stopwatch time. but the associated entity or module is not defined in the project. • debounce Schematic module implementing a simplistic debounce circuit for the strtstop.ise or wtut_ver.ise project open in Project Navigator. and duty-cycle correction.

xfile add time_cnt. Three HDL files have already been added to this project. An additional file must be added. In the Processes tab.1 In-Depth Tutorial .com ISE 9.R Chapter 2: HDL-Based Design Instantiated components with no entity or module declaration are displayed with a red question mark. 3.<architecture name> . click the + next to Synthesize to expand the process hierarchy. Select time_cnt.xilinx. Checking the Syntax To check the syntax of source files: 1.<entity name> . Select stopwatch. 2. Figure 2-5: time_cnt. In the Adding Source Files dialog box. 2.vhd The red question-mark (?) for time_cnt should change to show the VHD file icon. 30 www. When you select the HDL file.vhd or stopwatch. verify that time_cnt is associated with Synthesis/Imp + Simulation and click OK. Select Project > Add Source. the Processes tab displays all processes available for this file.vhd File in Sources Tab Each source Design unit is represented under the sources tab using the following syntax: <instance name> . Figure 2-4: Sources Tab Showing Completed Design Adding Source Files HDL files must be added to the project before they can be synthesized.v from the project directory and click Open.vhd or time_cnt. the time_cnt. 1.vhd file could be added to the project by entering the following command in the Tcl Shell tab. Note: Alternatively.(<file name>).v in the Sources tab.

The source code comes up in the main display tab. In the Console tab of the Transcript window.xilinx.1 In-Depth Tutorial www. Project Navigator reports errors with a red (X) and warnings with a yellow (!). Re-analyze the file by selecting the HDL file and double-clicking Check Syntax. Correct any errors in the HDL source file.com 31 .Design Entry R 3. The comments next to the error explain this simple fix. Double-click Check Syntax in the Synthesize hierarchy. 3. Correcting HDL Errors The time_cnt module contains a syntax error that must be corrected. Click the file name in the error message in the Console or Errors tab. Select File > Save to save the file. 2. ISE 9. Note: Check Syntax is not available when Synplify is selected as the synthesis tool. The red “x” beside the Check Syntax process indicates an error was found during the analysis. 4. To display the error in the source file: 1.

With ISE. you create a file using the New Source wizard. 3. Click Next. This macro will be used to debounce the strtstop. The dialog box New Source Wizard opens in which you specify the type of source you want to create. In the first three Port Name fields type sig_in. clk and sig_out. b. Select Project > New Source. To create the source file: 1. You will author a new HDL module. Using the New Source Wizard and ISE Text Editor In this section.xilinx. In the File Name field. Leave the Bus designation boxes unchecked. type debounce. you can easily create modules from HDL code using the ISE Text Editor. c. Set the Direction field to input for sig_in and clk and to output for sig_out. Figure 2-6: New Source Wizard for Verilog 32 www. Enter two input ports named sig_in and clk and an output port named sig_out for the debounce component in this way: a.R Chapter 2: HDL-Based Design Creating an HDL-Based Module Next you will create a module from HDL code. mode and lap_load inputs. The HDL code is then connected to your toplevel HDL design through instantiation and is compiled with the rest of the design. specifying the name and ports of the component.com ISE 9. The resulting HDL file is then modified in the ISE Text Editor. 5.1 In-Depth Tutorial . Select VHDL Module or Verilog Module. 2. 4.

xilinx.com 33 .1 In-Depth Tutorial www. The Verilog HDL file is displayed in Figure 2-8. A description of the module displays. Figure 2-7: VHDL File in ISE Text Editor Figure 2-8: Verilog File in ISE Text Editor ISE 9.Design Entry R 6. Click Finish to open the empty HDL file in the ISE Text Editor. 7. Click Next to complete the Wizard session. The VHDL file is displayed in Figure 2-7.

Simulation Constructs. and primitives.] Debounce Circuit. Click any of the listed templates to view the template contents in the right pane. Synthesis Constructs and User Templates. and values are black.R Chapter 2: HDL-Based Design In the ISE Text Editor. select Edit > Language Templates. such as counters. To invoke the Language Templates and select the template for this tutorial: 1. 34 www. click the + next to the section.1 In-Depth Tutorial .com ISE 9. The file is color-coded to enhance readability and help you recognize typographical errors. You will use the Debounce Circuit template for this exercise. the HDL code for a debounce circuit is displayed in the right pane. comments in green. multiplexers. expand the Misc hierarchy. Note: You can add your own templates to the Language Templates for components or constructs that you use often. 2. Under either the VHDL or Verilog hierarchy. and some of the basic file structure is already in place. From Project Navigator. Keywords are displayed in blue. expand the Synthesis Constructs hierarchy. Using the Language Templates The ISE Language Templates include HDL constructs and synthesis templates which represent commonly used logic components. Device Primitive Instantiation. To expand the view of any of these sections. Use the appropriate template for the language you are using.xilinx. the ports are already declared in the HDL file. expand the Coding Examples hierarchy. Upon selection. and select the template called [One-shot. Each HDL language in the Language Templates is divided into five sections: Common Constructs. D flip-flops.

Change <reg_name> to q in all six locations. 3.com 35 . 4. Close the Language Templates window.xilinx. Click and drag the Debounce Circuit name from the Language Template topology into the debounce. b. ISE 9.vhd file under the architecture begin statement. Remove the reset logic (not used in this design) by deleting the three lines beginning with if and ending with else. or into the debounce. Select Window > Tile Vertically to show both the HDL file and the Language Templates window. 2. Refer to “Working with Language Templates” in the ISE Help for additional usability options.v file under the module and pin declarations. To add the template to your HDL file using the drag and drop method: 1.Design Entry R Figure 2-9: Language Templates Adding a Language Template to Your File You will now use the drag and drop method for adding templates to your HDL file. (Verilog only) Complete the Verilog module by doing the following: a.1 In-Depth Tutorial www.

Creating a CORE Generator Module To create a CORE Generator module: 1. 6. Close the ISE Text Editor.Defines the number of values to be stored Data Width: 20 . Leave Input and output options as Non Registered. Save the file by selecting File > Save. Use Edit > Replace to change <clock> to clk. Remove the reset logic (not used in this design) by deleting the five lines beginning with if (<reset>. 9. a. Move the line beginning with the word signal so that it is between the architecture and begin keywords. Select IP (Coregen & Architecture Wizard). you will create a CORE Generator module called timer_preset. Component Name: timer_preset . In Project Navigator.xilinx. math functions and communications and IO interface cores. 8. <input> to sig_in.Defines the width of the output bus. The module will be used to store a set of 64 values to load into the timer. then click Next and click Finish to open the Distributed Memory Generator customization GUI. Click Next. and <output> to sig_out. and ending with else and delete one of the end if. Click Next. 6. In the Processes tab. 5.Defines the name of the module. and Q_OUT to sig_out. lines. such as Fast Carry Logic. Memory Type: ROM Click Next. SRL16s. Change <clock> to clk. Fill in the Distributed Memory Generator customization GUI with the following settings: ♦ ♦ ♦ ♦ ♦ ♦ 7.. c. 5. and distributed and block RAM. then double-click RAMs & ROMs. Double-click Memories & Storage Elements.com ISE 9.R Chapter 2: HDL-Based Design c.. You can customize and pre-optimize the modules to take advantage of the inherent architectural features of the Xilinx FPGA architectures. Depth: 64 .1 In-Depth Tutorial . 3. 2. In this section. 36 www. select Project > New Source. 7. Select one of the debounce instances in the Sources tab. Type timer_preset in the File name field. This customization GUI enables you to customize the memory to the design specifications. Creating a CORE Generator Module CORE Generator is a graphical interactive design tool that enables you to create high-level modules such as memory elements. b. (VHDL only) Complete the VHDL module by doing the following: You now have complete and functional HDL code. D_IN to sig_in. 4. double-click Check Syntax. Select Distributed Memory Generator.

Distributed Memory Generator Customization GUI Check that only the following pins are used (used pins are highlighted on the symbol on the left side of the customization GUI): ♦ ♦ a[5:0] spo[19:0] 9. Note: A number of files are added to the project directory.xco This file stores the configuration information for the timer_preset module and is used as a project source.mif This file provides the initialization values of the ROM for simulation. timer_preset.v These are HDL wrapper files for the core and are used only for simulation. The module is created and automatically added to the project library. ♦ timer_preset.vhd or timer_preset.com 37 .veo These are the instantiation templates used to incorporate the CORE Generator module into your source HDL. ♦ ♦ ♦ timer_preset.xilinx. timer_preset. Click Finish.Design Entry R ♦ Coefficients File: Click the Browse button and select definition1_times.1 In-Depth Tutorial www. ISE 9. Some of these files are: ♦ timer_preset.edn This file is the netlist that is used during the Translate phase of implementation.vho or timer_preset. Figure 2-10: 8.coe. CORE Generator .

vho and click Open. 7.vhd to open the file in ISE Text Editor. Place your cursor after the line that states: -. instantiate the CORE Generator module in the HDL code using either a VHDL flow or a Verilog flow. Figure 2-11: 4. VHDL Component Declaration for CORE Generator Module Highlight the inserted code from -. In Project Navigator.END INSTANTIATION Template ----- 5. The VHDL template file for the CORE Generator instantiation is inserted. 2. Figure 2-12: VHDL Component Instantiation of CORE Generator Module 38 www.Begin Cut here for INSTANTIATION Template ---- to --INST_TAG_END -----. Change the instance name from your_instance_name to t_preset. VHDL Flow To instantiate the CORE Generator module using a VHDL flow: 1. 9.xilinx.Insert CORE Generator ROM component declaration here Select Edit > Insert File. 6. then select timer_preset. 3. 8. Edit this instantiated code to connect the signals in the Stopwatch design to the ports of the CORE Generator module as shown in Figure 2-12.1 In-Depth Tutorial . Place the cursor after the line that states: --Insert CORE Generator ROM Instantiation here Select Edit > Paste to place the core instantiation.com ISE 9. double-click stopwatch.R Chapter 2: HDL-Based Design Instantiating the CORE Generator Module in the HDL Code Next. Select Edit > Cut.

and select timer_preset. The inserted code of timer_preset. select Project > New Source. 2. 5. Spartan-3A > Single DCM SP. 4. Figure 2-13: Verilog Component Instantiation of the CORE Generator Module 7. Delete these commented lines if desired. enables you to graphically select Digital Clock Manager (DCM) features that you wish to use.1 In-Depth Tutorial www. 11. Place your cursor after the line that states: //Place the Coregen module instantiation for timer_preset here Select Edit > Insert File. Edit this code to connect the signals in the Stopwatch design to the ports of the CORE Generator module as shown in Figure 2-13. 3.xilinx. select FPGA Features and Design > Clocking > Spartan3E. select IP (CoreGen & Architecture Wizard) source and type dcm1 for the file name. Change the instance name from YourInstanceName to t_preset.vho contains several lines of commented text for instruction and legal documentation.veo contains several lines of commented text for instruction and legal documentation.Design Entry R 10. Delete these commented lines if desired. 2. double-click stopwatch. Using the Clocking Wizard To create the dcm1 module: 1. In the Select IP dialog box. 4. Verilog Flow To instantiate the CORE Generator module using a Verilog flow: 1.com 39 . Click Next. and close the ISE Text Editor.v in the ISE Text Editor. In this section you will create a basic DCM module with CLK0 feedback and duty-cycle correction. In the New Source dialog box. The inserted code of timer_preset. a part of the Xilinx Architecture Wizard. Save the design using File > Save. 3. Creating a DCM Module The Clocking Wizard. In Project Navigator.veo.v to open the file in the ISE Text Editor. Save the design using File > Save and close stopwatch. In Project Navigator. 6. ISE 9.

( 26. Type 50 and select MHz for the Input Clock Frequency. 9. 40 www. and then click Next again. Click the Advanced button. The Clocking Wizard is launched.2144 in the box and select MHz. 8.xaw file is added to the list of project source files in the Sources tab. Single Feedback Source: Internal Feedback Value: 1X Use Duty Cycle Correction: Selected 10. Select Use output frequency and type 26. Select Wait for DCM lock before DONE Signal goes high. Verify that RST. Click Next. Select CLKFX port. 11. The dcm1. then Finish.com ISE 9.xilinx. Click Next. 13. 7.2144Mhz ) ⁄ 2 18 = 100Hz 15. and then click Finish. 6.R Chapter 2: HDL-Based Design Figure 2-14: Selecting Single DCM IP Type 5. Verify the following settings: ♦ ♦ ♦ ♦ ♦ Phase Shift: NONE CLKIN Source: External. 12. 14. Click Next. Click OK.1 In-Depth Tutorial . CLK0 and LOCKED ports are selected.

Design Entry R Instantiating the dcm1 Macro .vhi). double-click View HDL Instantiation Template. you will instantiate the dcm1 macro for your VHDL or Verilog design. Select Edit > Copy. 4. In Project Navigator. ISE 9.VHDL Design Next. Choose VHDL for the HDL Instantiation Template Target Language value and click OK. shown below. In the Processes tab.vhd file in a section labeled -. shown below.1 In-Depth Tutorial www. To instantiate the dcm1 macro for the VHDL design: 1. right-click View HDL Instantiation Template and select Properties. 8. 2.Insert dcm1 component declaration here.vhd file below the line labeled “-. 9. Highlight the component declaration template in the newly opened HDL Instantiation Template (dcm1. VHDL DCM Component Instantiation 11. Place the cursor in the stopwatch.com 41 .Insert dcm1 instantiation here”.xilinx.xaw. select dcm1. 3. 5. In the Processes tab. Select Edit > Copy. Select Edit > Paste to paste the component declaration. Figure 2-15: 6. in the Sources tab. 7. Figure 2-16: 10. VHDL DCM Component Declaration Place the cursor in the stopwatch. Highlight the instantiation template in the newly opened HDL Instantiation Template.

From the newly opened HDL Instantiation Template (dcm1. Make the necessary changes as shown in the figure below.1 In-Depth Tutorial .xilinx. 5.tfi). In Project Navigator. Instantiating the dcm1 Macro .Verilog To instantiate the dcm1 macro for your Verilog design: 1. dcm1 Macro and Instantiation Templates Paste the instantiation template into the section in stopwatch.xaw. 3. Select File > Save to save the stopwatch.R Chapter 2: HDL-Based Design 12. 13.v labeled //Insert dcm1 instantiation here. Figure 2-18: 4.v file.vhd file. copy the instantiation template. 2. Select Edit > Paste to paste the instantiation template. in the Sources tab. Select File > Save to save the stopwatch. 42 www. double-click View HDL Instantiation Template. Figure 2-19: Verilog Instantiation for dcm1 6. select dcm1. shown below.com ISE 9. In the Processes tab. Make the necessary changes as shown in the figure below. Figure 2-17: VHDL Instantiation for dcm1 14.

Synthesizing the Design R Synthesizing the Design So far you have been using XST (the Xilinx synthesis tool) for syntax checking. Xilinx recommends that you take a snapshot of the project before changing the ISE 9. 3. The synthesis tool performs three general steps (although all synthesis tools further break down these general steps) to create the netlist: • • Analyze / Check Syntax Checks the syntax of the source code. Select the targeted part in the Sources tab. • Map Translates the components from the compile stage into the target technology’s primitive components.com 43 . The synthesis tool uses the design’s HDL code and generates a supported netlist type (EDIF or NGC) for the Xilinx implementation tools. expand ISE General. click on the Synthesis Tool value and use the pulldown arrow to select the desired synthesis tool from the list. Next. To change the synthesis tool: 1. you will synthesize the design using either XST.1 In-Depth Tutorial www. Synplify/Synplify Pro or Precision. Changing the design flow results in the deletion of implementation data. For projects that contain implementation data. Compile Translates and optimizes the HDL code into a set of components that the synthesis tool can recognize. 2. then click Integrated Tools). The Synthesis tools are configured in the Preferences dialog box (Edit > Preferences. In the Project Properties dialog box. Select Source > Properties. You have not yet created any implementation data in this tutorial. you may not have the software installed or may not have it configured in ISE.xilinx. Figure 2-20: Specifying Synthesis Tool Note: If you do not see your synthesis tool among the options in the list. The synthesis tool can be changed at any time during the design flow.

Select Project > Add Source.R Chapter 2: HDL-Based Design synthesis tool to preserve this data. Note: In place of the three steps above.xcf is added as a User Document. Entering Constraints XST supports a User Constraint File (UCF) style syntax to define synthesis and timing constraints. A summary of available synthesis tools is available in “Overview of Synthesis Tools” in Chapter 1 Read the section for your synthesis tool: • • • “Synthesizing the Design using XST” “Synthesizing the Design using Synplify/Synplify Pro” “Synthesizing the Design Using Precision Synthesis” Synthesizing the Design using XST Now that you have created and analyzed the design. This format is called the Xilinx Constraint File (XCF).xcf extension to determine if the file is a constraints file. the HDL files are translated into gates and optimized for the target architecture. you may add the . Processes available for synthesis using XST are as follows: • View Synthesis Report Gives a synthesis mapping and timing summary as well as a list of optimizations that took place. Notice that stopwatch. using the following command and then selecting View > Refresh.*) and then select and add stopwatch. see “Creating a Snapshot” in Chapter 1. View Technology Schematic Generates a schematic view of your Technology netlist.xcf.xcf 4. Double-click stopwatch. In the Add Existing Sources dialog box. XST uses the .xilinx. The following constraints should exist in the stopwatch.xcf to open the file in the ISE Text Editor. To create a new Xilinx Constraint File: 1. Check Syntax Verifies that the HDL code is entered properly.xcf file through the Tcl Shell. Generate Post-Synthesis Simulation Model Creates HDL simulation models based on the synthesis netlist. xfile add stopwatch.1 In-Depth Tutorial .com ISE 9. 2. • • • • View RTL Schematic Generates a schematic view of your RTL netlist. For more information about taking a snapshot.xcf file extension. 3. the next step is to synthesize the design.xcf file: 44 www. 5. change the Files of type: to ‘All Files (*. During synthesis. and the file has an .

5.Post-synthesis view of the HDL design mapped to the target technology.v) in the Sources tab.1 In-Depth Tutorial www. LOC = "Y13". Select stopwatch. LOC = "AB18". To take the HDL code and generate a compatible netlist: 1. TIMESPEC “TS_CLK”=PERIOD “CLK_GROUP” 20 ns. click in the Synthesis Constraints File property field and enter stopwatch. A schematic view of the code helps you analyze your design by displaying a graphical connection between the various components that XST has inferred. LOC = "AB16". LOC = "AB12". 6. 2. Click OK.xcf. 3.Pre-optimization of the HDL code. The RTL / Technology Viewer XST can generate a schematic representation of the HDL code that you have entered. LOC = "Y15". see “Using the Constraints Editor” and “Using the Floorplan Editor” in Chapter 5.vhd (or stopwatch. In the Processes tab. “Design Implementation. Synthesizing the Design Now you are ready to synthesize your design. Close stopwatch.Synthesizing the Design R NET "CLK" TNM_NET = "CLK_GROUP". right-click the Synthesize process and select Properties. ISE 9. Under the Synthesis Options tab. LOC = "AB17". LOC = "Y16". Other options include controlling the maximum fanout of a flip-flop output or setting the desired frequency of the design. Check the Write Timing Constraints box. Note: For more constraint options in the implementation tools.” Entering Synthesis Options Synthesis options enable you to modify the behavior of the synthesis tool to make optimizations according to the needs of the design. LOC = "AA12". Select stopwatch. 4.com 45 . One commonly used option is to control synthesis to make optimizations based on area or speed.xilinx.xcf.vhd (or stopwatch. There are two forms of the schematic representation: • • RTL View . To enter synthesis options: 1. BEGIN MODEL stopwatch NET "sf_d<7>" NET "sf_d<6>" NET "sf_d<5>" NET "sf_d<4>" NET "sf_d<3>" NET "sf_d<2>" NET "sf_d<1>" NET "sf_d<0>" END.v). 2. Technology View . Double-click the Synthesize process in the Processes tab.

The RTL Viewer displays the top level schematic symbol for the design. 46 www. Note: For more information about XST constraints. options. 2. Figure 2-21: RTL Viewer You have completed XST synthesis.” to place and route the design. Right-click the schematic to view the various operations that can be performed in the schematic viewer. This guide is available in the collection of software manuals and is accessible from ISE by selecting Help > Software Manuals. An NGC file now exists for the Stopwatch design. or running XST from the command line. Double-click on the symbol to push into the schematic and view the various design elements and connectivity. To continue with the HDL flow: • Go to Chapter 4.1 In-Depth Tutorial . In the Processes tab. Double-click View RTL Schematic or View Technology Schematic. “Behavioral Simulation.com/support/sw_manuals/xilinx9/.xilinx. OR • Proceed to Chapter 5. “Design Implementation.” to perform a pre-synthesis simulation of this design. reports. click the + next to Synthesize to expand the process hierarchy.com ISE 9.R Chapter 2: HDL-Based Design To view a schematic representation of your HDL code: 1.xilinx. see the XST User Guide. or from the web at http://www.

names which file is the top level.1 In-Depth Tutorial www. Check the Write Vendor Constraint File box. warnings on latches. double-click View Synthesis Report under the Synthesize process. inferred memory. 4. and removal of redundant logic. the implementation tools merge the netlist into the design during the Translate phase. right-click the Synthesize process and select Properties. As long as the underlying netlist (.ngo. Double-click the Synthesize process to run synthesis. • View RTL Schematic Accessible from the Launch Tools hierarchy. Select stopwatch. 3.ngc or . Examining Synthesis Results To view overall synthesis results. and displays the syntax checking result for each file that was compiled. Note: This step can also be done by selecting stopwatch. The report also lists FSM extractions. The report consists of the following four sections: • • • • “Compiler Report” “Mapper Report” “Timing Report” “Resource Utilization” Compiler Report The compiler report lists each HDL file that was compiled. 5. To access Synplify’s RTL viewer and constraints editor you must run Synplify outside of ISE.vhd (or stopwatch. unused ports.Synthesizing the Design R Synthesizing the Design using Synplify/Synplify Pro Now that you have entered and analyzed the design. and selecting Process > Run. 2.v).edn) for a black box exists in the project directory. this process displays Synplify or Synplify Pro with a schematic view of your HDL code • View Technology Schematic Accessible from the Launch Tools hierarchy. Click OK to accept these values. Processes available in Synplify and Synplify Pro synthesis include: • View Synthesis Report Lists the synthesis optimizations that were performed on the design and gives a brief timing and mapping report. this process displays Synplify or Synplify Pro with a schematic view of your HDL code mapped to the primitives associated with the target technology. set the global synthesis options: 1. the next step is to synthesize the design. ISE 9. In the Processes tab. To synthesize the design.vhd (or stopwatch. clicking Synthesize in the Processes tab.xilinx.v). In this step. .com 47 . Note: Black boxes (modules not read into a design environment) are always noted as unbound in the Synplify reports. the HDL files are translated into gates and optimized to the target architecture.

“Design Implementation. extracted counters. “Behavioral Simulation. OR • Proceed to Chapter 5. Timing Report The timing report section provides detailed information on the constraints that you entered and on delays on parts of the design that had no constraints.” to perform a pre-synthesis simulation of this design. the target technology. At this point.” to place and route the design. The delay values are based on wireload models and are considered preliminary. View Log File 48 www. optimized flip-flops. To continue with the HDL flow: • Go to Chapter 4. clock and buffered nets that were created.xilinx. the HDL files are translated into gates and optimized to the target architecture.1 In-Depth Tutorial . “Design Implementation. You have now completed Synplify synthesis. In this step. a netlist EDN file exists for the Stopwatch design. and attributes set in the design. and how FSMs were coded. Processes available for Precision Synthesis include: • • Check Syntax Checks the syntax of the HDL code.com ISE 9. The report lists the mapping results of flattened instances. Consult the post-place and route timing reports discussed in Chapter 5. the next step is to synthesize the design.” for the most accurate delay information.R Chapter 2: HDL-Based Design Mapper Report The mapper report lists the constraint files used. Synthesizing the Design Using Precision Synthesis Now that you have entered and analyzed the design. Figure 2-22: Synplify’s Estimated Timing Data Resource Utilization This section of the report lists all of the resources that Synplify uses for the given target technology.

Synthesizing the Design

R

Lists the synthesis optimizations that were performed on the design and gives a brief timing and mapping report. • View RTL Schematic Accessible from the Launch Tools hierarchy, this process displays Precision with a schematic-like view of your HDL code • View Technology Schematic Accessible from the Launch Tools hierarchy, this process displays Precision with a schematic-like view of your HDL code mapped to the primitives associated with the target technology. • View Critical Path Schematic Accessible from the Launch Tools hierarchy, this process displays Precision with a schematic-like view of the critical path of your HDL code mapped to the primitives associated with the target technology.

Entering Synthesis Options through ISE
Synthesis options enable you to modify the behavior of the synthesis tool to optimize according to the needs of the design. For the tutorial, the default property settings will be used. 1. 2. Select stopwatch.vhd (or stopwatch.v) in the Sources tab. Double-click the Synthesize process in the Processes tab.

The RTL/Technology Viewer
Precision Synthesis can generate a schematic representation of the HDL code that you have entered. A schematic view of the code helps you analyze your design by seeing a graphical connection between the various components that Precision has inferred. To launch the design in the RTL viewer, double-click the View RTL Schematic process. The following figure displays the design in an RTL view.

Figure 2-23:

Stopwatch Design in Precision Synthesis RTL Viewer

You have now completed the design synthesis. At this point, an EDN netlist file exists for the Stopwatch design. To continue with the HDL flow:

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Chapter 2: HDL-Based Design

Go to Chapter 4, “Behavioral Simulation,” to perform a pre-synthesis simulation of this design. OR Proceed to Chapter 5, “Design Implementation,” to place and route the design.

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Chapter 3

Schematic-Based Design
This chapter includes the following sections: • • • • “Overview of Schematic-Based Design” “Getting Started” “Design Description” “Design Entry”

Overview of Schematic-Based Design
This chapter guides you through a typical FPGA schematic-based design procedure using the design of a runner’s stopwatch. The design example used in this tutorial demonstrates many device features, software features, and design flow practices that you can apply to your own designs. The stopwatch design targets a Spartan™-3A device; however, all of the principles and flows taught are applicable to any Xilinx® device family, unless otherwise noted. This chapter is the first in the “Schematic Design Flow.” In the first part of the tutorial, you will use the ISE™ design entry tools to complete the design. The design is composed of schematic elements, a state machine, a CORE Generator™ component, and HDL macros. After the design is successfully entered in the Schematic Editor, you will perform behavioral simulation (Chapter 4, “Behavioral Simulation”), run implementation with the Xilinx Implementation Tools (Chapter 5, “Design Implementation”), perform timing simulation (Chapter 6, “Timing Simulation”), and configure and download to the Spartan-3A (XC3S700A) demo board (see Chapter 7, “iMPACT Tutorial.”).

Getting Started
The following sections describe the basic requirements for running the tutorial.

Required Software
You must have Xilinx ISE 9.1i installed to follow this tutorial. For this design you must install the Spartan-3A libraries and device files. A schematic design flow is supported on Windows, Solaris, and Linux platforms.

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R Chapter 3: Schematic-Based Design This tutorial assumes that the software is installed in the default location.1 In-Depth Tutorial . If you restore the files to a different location. Double-click the ISE Project Navigator icon on your desktop. and State Machine files. refer to the ISE 9. Starting the ISE Software To launch the ISE software package: 1. wtut_sc\wtut_sc_completed\ (Contains the completed design files for the schematic-based tutorial design.1i > Project Navigator.com/support/techsup/tutorials/tutorials9. Download the Watch Schematic Design Files (wtut_sch. Figure 3-1: Project Navigator Desktop Icon Creating a New Project Two methods are provided for creating a new project: Using the New Project Wizard. at c:\xilinx.xilinx. substitute c:\xilinx\ISEexamples with the project path. 52 www. The schematic tutorial files are copied into the directories when you unzip the files. or select Start > All Programs > Xilinx ISE 9. Do not overwrite files under this directory. Installing the Tutorial Project Files The tutorial project files can be downloaded to your local machine from http://www. This tutorial assumes that the files are unarchived under c:\xilinx\ISEexamples. If you have installed the software in a different location. including schematic.) • Unzip the tutorial design files in any directory with read-write permissions.htm. and Using a Tcl Script.zip).1i Installation Guide and Release Notes. substitute c:\xilinx for your installation path. The download contains two directories: • wtut_sc\ (Contains source files for schematic tutorial. Note: For detailed instructions about installing the software. The schematic tutorial project will be created in this directory).com ISE 9.xilinx. HDL.

Type wtut_sc as the Project Name.xilinx. and then click Next. Browse to c:\xilinx\ISEexamples or enter the directory in the Project Location field. From Project Navigator.Create New Project 2. Notice that wtut_sc is appended to the Project Location value. 3. Figure 3-2: New Project Wizard . The New Project Wizard appears.Device Properties ISE 9.com 53 .1 In-Depth Tutorial www. 4. Figure 3-3: New Project Wizard .Getting Started R Creating a New Project: Using New Project Wizard 1. Select Schematic as the Top-Level Source Type. select File > New Project.

Verify that all added schematic files are associated with Synthesis/Imp + Simulation. a CORE Generator module. 7.R Chapter 3: Schematic-Based Design 5. (e. Select the following values in the New Project Wizard . 8. Creating a New Project: Using a Tcl Script With Project Navigator open.vhd lcd_control. select the Tcl Shell tab. This will determine the default language for all processes that generate HDL files.Device Properties window: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Product Category: All Family: Spartan3A and Spartan3AN Device: XC3S700A Package: FG484 Speed: -4 Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: VHDL or Verilog depending on preference. 10. then Finish to complete the New Project Wizard. including schematicbased modules.dia file is associated with Synthesis/Implementation Only. 11. Type cd c:/xilinx/ISEexamples/wtut_sc). an Architecture Wizard module. Click OK. Browse to c:\xilinx\ISEexamples\wtut_sc.dia 9.Add Existing Sources window. Select the following files and click Open.sch clk_div_262k. ♦ ♦ ♦ ♦ ♦ ♦ cd4rled.vhd stopwatch. Design Description The design used in this tutorial is a hierarchical. 2. Click Next. a state machine module.sch ch4rled. save your work by selecting File > Save All. and that the . 1. and HDL modules. and then click Add Source in the New Project Wizard . which means that the top-level design file is a schematic sheet that refers to several other lower-level macros. Click Next twice.xilinx. Change the current working directory to the directory where the tutorial source files were unzipped. Type source create_wtut_sc.tcl. 6.1 In-Depth Tutorial . The lower-level macros are a variety of different types of modules.g. 54 www. schematic-based design.sch statmach.com ISE 9. Stopping the Tutorial If you need to stop the tutorial at any time.

xilinx.com 55 . After the design is complete. Throughout the tutorial. see Chapter 4. Inputs The following are input signals for the tutorial stopwatch design.” Figure 3-4: Completed Watch Schematic There are five external inputs and four external outputs in the completed design. For more information about simulating your design. A schematic of the completed stopwatch design is shown in the following figure. and their respective functions. you will create these modules. you will complete the design by creating some of the modules and by completing others from existing files. Through the course of this chapter.Design Description R The runner’s stopwatch design begins as an unfinished design. instantiate them. and then connect them.1 In-Depth Tutorial www. you will simulate the design to verify its functionality. ISE 9. “Behavioral Simulation. The following sections summarize the inputs and outputs.

144. Functional Blocks The completed design consists of the following functional blocks. and lap_load input signals. frequency controlled output. • • • reset Puts the stopwatch in clocking mode and resets the time to 0:00:00. • lap_load This is a dual function signal. This input is only functional while the clock or timer is not counting. • clk_div_262k Macro which divides a clock frequency by 262. Outputs The following are outputs signals for the design. clk Externally generated system clock.2144 MHz. and duty-cycle correction.R Chapter 3: Schematic-Based Design • strtstop Starts and stops the stopwatch. • lcd_e. lcd_rs. • • lcd_control Module controlling the initialization of and output to the LCD display. In timer mode it will load the pre-assigned values from the ROM to the timer display when the timer is not counting.2144 MHz clock into 100 Hz 50% duty cycle clock. • debounce Module implementing a simplistic debounce circuit for the strtstop. lcd_rw These outputs are the control signals for the LCD display of the Spartan-3A demo board used to display the stopwatch times. In clocking mode it displays the current clock value in the ‘Lap’ display area. • sf_d[7:0] Provides the data values for the LCD display.com ISE 9. statmach 56 www. This is an active low signal which acts like the start/stop button on a runner’s stopwatch.xilinx. • dcm1 Clocking Wizard macro with internal feedback.1 In-Depth Tutorial . The CLKFX_OUT output converts the 50 MHz clock of the Spartan-3A demo board to 26. Converts 26. Most of these blocks do not appear on the schematic sheet in the project until after you create and add them to the schematic during this tutorial. The completed design consists of the following functional blocks. mode Toggles between clocking and timer modes. mode.

you will update the schematic in the Schematic Editor. and you will connect the macros together to create the completed stopwatch design.xilinx. This macro contains 64 preset times from 0:00:00 to 9:59:99 which can be loaded into the timer. Controls the state of the stopwatch. • timer_preset CORE Generator™ 64X20 ROM. This macro has five 4-bit outputs. After you have created the project in ISE. state machine macros. which represent the digits of the stopwatch time.sch file for editing. you can now open the stopwatch. • time_cnt Up/down counter module which counts between 0:00:00 to 9:59:99 decimal. All procedures used in the tutorial can be used later for your own designs. You will learn the process for creating each of these types of macros. HDL-based macros. ISE 9. including schematicbased macros. you will create various types of macros. Design Entry In this hierarchical design.Design Entry R State Machine module defined and implemented in State Diagram Editor. and CORE Generator macros. Opening the Schematic File in the Xilinx Schematic Editor The stopwatch schematic available in the wtut_sc project is incomplete. To open the schematic file. In this tutorial.sch in the Sources window. double-click stopwatch.com 57 .1 In-Depth Tutorial www.

Creating a Schematic-Based Macro A schematic-based macro consists of a symbol and an underlying schematic. The corresponding symbol or schematic file can then be generated automatically. The schematic window can be undocked from the Project Navigator framework by selecting Window > Float while the schematic is selected in the workspace.R Chapter 3: Schematic-Based Design The stopwatch schematic diagram opens in the Project Navigator Workspace.1 In-Depth Tutorial . After being undocked. Select View > Zoom > In until you can comfortably view the schematic.com ISE 9. Figure 3-5: Incomplete Stopwatch Schematic Manipulating the Window View The View menu commands enable you to manipulate how the schematic is displayed. 58 www. the schematic window can be redocked by selecting Window > Dock. You will see the unfinished design with elements in the lower right corner as shown in the figure below. You can create either the underlying schematic or the symbol first.xilinx.

2. Enter time_cnt as the file name. ISE 9. Click OK and then click Yes to acknowledge that changing the sheet size cannot be undone with the Edit > Undo option. 4. The macro you will create is called time_cnt. The New Source dialog box opens: Figure 3-6: New Source Dialog Box The New Source dialog displays a list of all of the available source types. select Project > New Source. representing the digits of the stopwatch. The next step is to add the components that make up the time_cnt macro. Defining the time_cnt Schematic You have now created an empty schematic for time_cnt. Change the size of the schematic sheet by doing the following. An empty schematic file is then created.1 In-Depth Tutorial www. To create a schematic-based macro: 1. ♦ ♦ ♦ Right-click on the schematic page and select Object Properties.Design Entry R In the following steps. Click on the down arrow next to the sheet size value and select D = 34 x 22. The created macro is then automatically added to the project’s library. and you can define the appropriate logic. This macro is a binary counter with five. 5.com 59 . A new schematic called time_cnt is created. 4bit outputs. and opened for editing. 3. added to the project.xilinx. Click Next and click Finish. Select Schematic as the source type. you will create a schematic-based macro by using the New Source Wizard in Project Navigator. In Project Navigator. You can then reference this macro symbol by placing it on a schematic sheet.

Add I/O markers to the time_cnt schematic to determine the macro ports. Adding Schematic Components Components from the device and project libraries for the given project are available from the Symbol Browser.clr. From the menu bar.sec_lsb(3:0).up. In the Inputs box. The name of each pin on the symbol must have a corresponding connector in the underlying schematic.clk. I/O markers may be added to nets at any time by selecting Add > I/O Marker and selecting the desired net. In the Outputs box. The eleven I/O markers are added to the schematic sheet. and the component symbol can be placed on the schematic. Creating I/O Markers Click OK.tenths(3:0). However. The Create I/O Markers dialog box opens. To add the I/O markers: 1.R Chapter 3: Schematic-Based Design Adding I/O Markers I/O markers are used to determine the ports on a macro. or the top-level schematic.com ISE 9. 3. 1.sec_msb(3:0).load. select Add > Symbol or click the Add Symbol icon from the Tools toolbar.minutes(3:0). The available components listed in the Symbol Browser are arranged alphabetically within each library. 2. enter hundredths(3:0).xilinx. Figure 3-7: 4.ce. Note: The Create I/O Marker function is available only for an empty schematic sheet. Note: The Options window changes depending on which tool you have selected in the Tools toolbar.1 In-Depth Tutorial . Select Tools > Create I/O Markers. enter q(19:0). Figure 3-8: Add Symbol Icon 60 www.

Design Entry

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This opens the Symbol Browser to the left of the schematic editor, displaying the libraries and their corresponding components.

Figure 3-9:

Symbol Browser

The first component you will place is a cd4rled, a 4-bit, loadable, bi-directional, BCD counter with clock enable and synchronous clear. 2. Select the cd4rled component, using one of two ways:

Highlight the project directory category from the Symbol Browser dialog box and select the component cd4rled from the symbols list. or Select All Symbols and type cd4rled in the Symbol Name Filter at the bottom of the Symbol Browser window.

3. 4.

Move the mouse back into the schematic window. You will notice that the cursor has changed to represent the cd4rled symbol. Move the symbol outline near the top and center of the sheet and click the left mouse button to place the object. Note: You can rotate new components being added to a schematic by selecting Ctrl+R. You
can rotate existing components by selecting the component, and then selecting Ctrl+R.

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R

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5.

Place three more cd4rled symbols on the schematic by moving the cursor with attached symbol outline to the desired location, and clicking the left mouse button. See Figure 3-10

Figure 3-10: 6. • • •

Partially Completed time_cnt Schematic

Follow the procedure outlined in steps 1 through 4 above to place the following components on the schematic sheet: AND2b1 ch4rled AND5

Refer to Figure 3-10 for placement locations. To exit the Symbols Mode, press the Esc key on the keyboard.

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Design Entry

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For a detailed description of the functionality of Xilinx Library components, right-click on the component and select Object Properties. In the Object Properties window, select Symbol Info. Symbol information is also available in the Libraries Guides, accessible from the collection of software manuals on the web at http://www.xilinx.com/support/sw_manuals/xilinx9/.

Correcting Mistakes
If you make a mistake when placing a component, you can easily move or delete the component. To move the component, click the component and drag the mouse around the window. Delete a placed component in one of two ways: • • Click the component and press the Delete key on your keyboard. or Right-click the component and select Delete.

Drawing Wires
Use the Add Wire icon in the Tools toolbar to draw wires (also called nets) to connect the components placed in the schematic. Perform the following steps to draw a net between the AND2b1 and top cd4rled components on the time_cnt schematic. 1. Select Add > Wire or click the Add Wire icon in the Tools toolbar.

Figure 3-11: 2. 3.

Add Wire Icon

Click the output pin of the AND2b1 and then click the destination pin CE on the cd4rled component. The Schematic Editor draws a net between the two pins. Draw a net to connect the output of the AND5 component to the inverted input of the AND2b1 component. Connect the other input of the AND2b1 to the ce input IO marker. Connect the load, up, clk, and clr input IO markers respectively to the L, UP, C, and R pins of each of the five counter blocks and connect the CEO pin of the first four counters to the CE pin of the next counter as shown in Figure 3-10.

4.

To specify the shape of the net: 1. 2. Move the mouse in the direction you want to draw the net. Click the mouse to create a 90-degree bend in the wire.

To draw a net between an already existing net and a pin, click once on the component pin and once on the existing net. A junction point is drawn on the existing net.

Adding Buses
In the Schematic Editor, a bus is simply a wire that has been given a multi-bit name. To add a bus, use the methodology for adding wires and then add a multi-bit name. Once a bus

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you have the option of “tapping” this bus off to use each signal individually. Select Add > Bus Tap or click the Add Bus Tap icon in the Tools toolbar. Select all of the output IO markers by drawing a box around them and then drag the group so that minutes(3:0) is below the Q3 output of the bottom counter block.R Chapter 3: Schematic-Based Design has been created. perform the following steps: 1. Figure 3-12: 4. 5. 2. choose the --< Right orientation for the bus tap. Figure 3-13: Add Bus Tap Icon The cursor changes. tenths(3:0). After adding the five buses. Use Bus Taps to tap off a single bit of a bus and connect it to another component. To add the buses hundredths(3:0). 64 www.com ISE 9.1 In-Depth Tutorial . sec_lsb(3:0). 3. indicating that you are now in Draw Bus Tap mode. Adding Bus Taps Next. press Esc or right-click at the end of the bus to exit the Add Wire mode. The results can be found in the completed schematic. Click in the open space just above and to the right of the top cd4rled and then click again on the pin of the hundredths(3:0) I/O marker. To tap off a single bit of each bus: 1. 2. The thick line should automatically be drawn to represent a bus with the name matching that of the I/O marker. add nets to attach the appropriate pins from the cd4rled and ch4rled counters to the buses. sec_msb(3:0) and minutes(3:0) to the schematic.xilinx. The next step is to create three buses for each of the five outputs of the time_cnt schematic. From the Options tab to the left of the schematic. Note: Zooming in on the schematic enables greater precision when drawing the nets. Adding a Bus Repeat Steps 2 and 3 for the four remaining buses. Select Add > Wire or click the Add Wire icon in the Tools toolbar.

6. tc_out2. The net name appears above the net if the name is placed on any point of the net other than an end point. 4. With hundredths(3) as the Net Name value. ISE 9. Note: It is the name of the wire that makes the electrical connection between the bus and the wire (e. Note: The indexes of the Net Name may be incremented or decremented by clicking the arrow buttons next to the Net Name box. name the first net tc_out4 and select Decrease the name in the Add Net Names Options dialog box.Design Entry R 3. The following section shows additional electrical connections by name association. add a hanging wire to each of the five inputs of the AND5 component and to the TC pin of each of the counter blocks. To add the net names: 1. Note: Four selection squares appear around the pin when the cursor is in the correct position. 4. Q1. The Selected Bus Name and the Net Name values of the options window are now populated. 5. and tc_out4 to these nets. The Schematic Editor increments the net Name as each name is placed on a net.g sec_msb(2) connects to the third bit of sec(3:0)). tc_out3 and tc_out4. Next. Add Net Name Icon Type tc_out0 in the Name box and select Increase the Name in the Add Net Names Options dialog box. A tap is connected to the hundredths(3:0) bus and a wire named hundreths(3) is drawn between the tap and the Q3 pin. Click the net attached to the first input of the AND5 component.1 In-Depth Tutorial www. Select Add > Net Name or click the Add Net Name icon in the Tools toolbar. 8. and Q0 to create taps for the remaining bits of the hundredths(3:0) bus.com 65 . Figure 3-14: 2. Adding Net Names First. The name is then attached to the net. Click on the remaining input nets of the AND5 to add tc_out1. Repeat step 2 and then click successively on the nets connected to the TC output to add tc_out0. tc_out3. and nets are named from the bottom up.xilinx. move the cursor so the tip of the attached tap touches the Q3 pin of the top cd4rled component. Compare your time_cnt schematic with Figure 3-15 to ensure that all connections are made properly. 5. tc_out2. add net names to the wires. The bus tap figure is for visual purposes only. Click successively on pins Q2. Repeat Steps 3 to 6 to tap off four bits from each of the five buses. Alternatively. tc_out1. The net name tc_out0 is now attached to the cursor. Click once when the cursor is in the correct position. 7. Click on the hundreths(3:0) bus with the center bar of the cursor. Press Esc to exit the Add Net Name mode. 3.

Finally. Click successively on each of the nets connected to data inputs. fix the reported problem before proceeding. Note: If the nets appear disconnected. Select Add > Net Name or click the Add Net Name icon in the Tools toolbar. Select Add > Wire or click the Add Wire icon and add a hanging net to the four data pins of each of the five counters. Verify that the schematic does not contain logical errors by running a design rule check (DRC). Figure 3-15: Completed time_cnt Schematic Checking the Schematic The time_cnt schematic is now complete. select Tools > Check Schematic. 5. starting from the top so that the net named q(0) is attached to the D0 pin of the top counter and the net named q(19) is attached to the D3 pin of the bottom counter. 4.1 In-Depth Tutorial . Type q(0) in the Name box of the Add Net Name options dialog box. 1. Select Increase the name in the Add Net Name options dialog box. the nets do not need to be physically connected on the schematic to make the logical connection.com ISE 9. 3. 66 www. If an error or warning is displayed. The Console window should report that no errors or warnings are detected. connect the input pins of the counters through net name association. In this case.R Chapter 3: Schematic-Based Design Note: Each of the wires with identical names are now electrically connected. To do this. select View > Refresh to refresh the screen.xilinx. 2. The net name q(0) is now attached to the cursor. Refer to Figure 3-15.

Click Next. Creating the time_cnt symbol You can create a symbol using either a Project Navigator process or a Tools menu command. 2. With the time_cnt schematic sheet open. and then select time_cnt in the schematic value field. you will add the symbol to a top-level schematic of the stopwatch design. select Tools > Symbol Wizard. In the Sources window. In the Processes window.1 In-Depth Tutorial www. To create a symbol that represents the time_cnt schematic using a Project Navigator process: 1. 1. Placing the time_cnt Symbol Next. then Next again. 2. Close the time_cnt schematic. or by clicking the Save icon in the toolbar. Save the schematic by selecting File > Save.sch). In the top-level schematic. select time_cnt. View and then close the time_cnt symbol.xilinx. and then Finish to use the wizard defaults. In the Sources window.com 67 . The symbol is an instantiation of the macro. Save Icon Creating and Placing the time_cnt Symbol The next step is to create a “symbol” that represents the time_cnt macro. 2.sch to open the schematic. the symbol of the time_cnt macro will be connected to other components in a later section in this chapter. click the + beside Design Utilities to expand the hierarchy.Design Entry R Saving the Schematic 1. Double-click Create Schematic Symbol. Figure 3-17: Add Symbol Icon ISE 9. double-click stopwatch. After you create a symbol for time_cnt. place the symbol that represents the macro on the top-level schematic (stopwatch. 3. 3. Figure 3-16: 2.sch. Select the Add Symbol icon. then Next. In the Symbol Wizard. select Using Schematic. To create a symbol that represents the time_cnt schematic using a Tools menu command: 1.

Click Next. and is updated as the cursor is moved around the schematic. This customization GUI enables you to customize the memory to the design specifications. then click Next and click Finish to open the Distributed Memory Generator customization GUI. 4. Depth: 64 . Note: Do not worry about connecting nets to the input pins of the time_cnt symbol.xilinx. Select IP (Coregen & Architecture Wizard). and then select the newly created time_cnt symbol. such as Fast Carry Logic. communications. Fill in the Distributed Memory Generator customization GUI with the following settings: ♦ ♦ ♦ ♦ ♦ ♦ 7. In Project Navigator. and IO interface cores. Save the changes and close stopwatch.Defines the number of values to be stored Data Width: 20 . You will do this after adding other components to the stopwatch schematic. select the local symbols library (c:\xilinx\ISEexamples\wtut_sc). Memory Type: ROM Click Next. 4. You can customize and pre-optimize the modules to take advantage of the inherent architectural features of the Xilinx FPGA architectures. 2. Component Name: timer_preset . math functions.sch. you will create a CORE Generator module called timer_preset. SRL16s. 5. Creating a CORE Generator Module CORE Generator is a graphical interactive design tool that enables you to create high-level modules such as memory elements. Click Next. The module is used to store a set of 64 values to load into the timer. then double-click RAMs & ROMs. Creating a CORE Generator Module To create a CORE Generator module: 1. 6.Defines the width of the output bus.Defines the name of the module. 3.1728]. This should be close to grid position [1612. 68 www. In this section. and distributed and block RAM. Type timer_preset in the File name field. Double-click Memories & Storage Elements. Place the time_cnt symbol in the schematic so that the output pins line up with the five buses driving inputs to the lcd_control component. 5.1 In-Depth Tutorial . select Project > New Source. Grid position is shown at the bottom right corner of the Project Navigator window.R Chapter 3: Schematic-Based Design 3. Leave Input and Output options as Non Registered. In the Symbol Browser. Select Distributed Memory Generator.com ISE 9.

timer_preset. Note: A number of files are added to the project directory.xco This file stores the configuration information for the timer_preset module and is used as a project source. Some of these files are: ♦ ♦ ♦ ♦ timer_preset.v These are HDL wrapper files for the core and are used only for simulation.sym This file is a schematic symbol file.ngc This file is the netlist that is used during the Translate phase of implementation. CORE Generator .Design Entry R ♦ Coefficients File: Click the Browse button and select definition1_times.com 69 . timer_preset.vhd or timer_preset. Click Finish. timer_preset. The module is created and automatically added to the project library. Figure 3-18: 8. ISE 9.coe.mif This file provides the initialization values of the ROM for simulation.xilinx.1 In-Depth Tutorial www.Distributed Memory Generator Customization GUI Check that only the following pins are used (used pins are highlighted on the symbol on the left side of the customization GUI): ♦ ♦ a[5:0] spo[19:0] 9. ♦ timer_preset.

The State Diagram Editor is launched with the partially completed state machine diagram. defining how you move between states. or ABEL. Verilog or ABEL code. Then. A completed VHDL and Verilog file for the State Machine diagram in this section has been provided for you in the wtut_sc\wtut_sc_completed directory.dia file to the project by selecting Project > Add Source and selecting statmach. you can graphically create finite state machines that include states. In the next section. To skip this section. Transition conditions and state actions are typed into the diagram using language independent syntax. The State Diagram Editor then exports the diagram to either VHDL.R Chapter 3: Schematic-Based Design Creating a State Machine Module With the State Diagram Editor. 70 www. Note: The State Diagram Editor is only available for Windows operating systems. For this tutorial. and state transition conditions. VHDL. inputs/outputs. then proceed to “Creating the State Machine Symbol. The output expressions for each state are found in the circles representing the states. copy either statmach. a partially complete state machine diagram is provided. In the incomplete state machine diagram below: • • • • The circles represent the various states. The transition conditions and the state actions are written in language-independent syntax and are then exported to Verilog.vhd from the c:\xilinx\ISEexamples\stut_sc\wtut_sc_completed directory to the c:\xilinx\ISEexamples\stut_sc directory. The black expressions are the transition conditions.dia in the Sources tab. first add the statmach.1 In-Depth Tutorial .v or stamach. double-click statmach.xilinx. you will complete the diagram. The resulting HDL file is finally synthesized to create a netlist and a macro symbol is created for you to place on a schematic sheet.” To open the partially complete diagram.dia. synthesize the module into a macro and place it on the stopwatch schematic.com ISE 9.

Place the new state on the left-hand side of the diagram.Design Entry R Figure 3-19: Incomplete State Machine Diagram In the following section. ISE 9. Click the mouse to place the state bubble. Click the Add State icon in the vertical toolbar.com 71 .xilinx. To do so: 1. actions. Figure 3-20: Add State Icon The state bubble is now attached to the cursor. 3. as shown in Figure 3-21. add the remaining states. transitions. 2. and a reset condition to complete the state machine.1 In-Depth Tutorial www. Adding New States Complete the state machine by adding a new state called clear.

1 In-Depth Tutorial . 3. and change the name of the state to clear.com ISE 9. 1. Because this transition is unconditional. Note: The name of the state is for your use only and does not affect synthesis. Add Transitions Icon Click on the clear state to start the transition. Adding a Transition A transition defines the movement between states of the state machine. Transitions are represented by arrows in the editor. 5. You will add a transition from the clear state to the zero state in the following steps.xilinx. there is no transition condition associated with it. Click the Add Transition icon in the vertical toolbar. click one of the four squares surrounding the bubble and drag it in the direction you wish to stretch the bubble. Click on the zero state to complete the transition arrow. Figure 3-21: 4. STATE0. Figure 3-22: 2. Click OK.R Chapter 3: Schematic-Based Design The state is given the default name. Adding the CLEAR State Double-click STATE0 in the state bubble. To change the shape of the state bubble. 72 www. Any name is fine.

Double-click the clear state. Adding State Transition Click the Select Objects (or Pointer) icon in the vertical toolbar to exit the Add Transition mode. To manipulate the arrow’s shape.Design Entry R 4. click and drag it in any directory. Figure 3-23: 5. ISE 9.1 In-Depth Tutorial www. Figure 3-24: Select Objects Icon Adding a State Action A state action dictates how the outputs should behave in a given state. You will add a state action to the clear state to drive the RST output to 1.xilinx. To add a state action: 1.com 73 .

Figure 3-26: Adding State Outputs 74 www. 5.1 In-Depth Tutorial . enter the following values: DOUT = rst. 3.xilinx. Click OK to enter each individual value.com ISE 9. 4. Edit State Dialog Box In the Logic Wizard. Select the Output Wizard button. CONSTANT = ‘1’.R Chapter 3: Schematic-Based Design The Edit State dialog box opens and you can begin to create the desired outputs. Click OK to exit the Edit State dialog box. Figure 3-25: 2. The output is now added to the state.

4. 5.Design Entry R Adding a State Machine Reset Condition Using the State Machine Reset feature. select either Verilog or VHDL as desired. 6. 2. 1. double-click on the value and edit the condition appropriately.com 75 . A Results window is displayed listing the compile status. as shown in the diagram below. In the Language section. Adding a Reset Condition Verify that ‘state_reset’ is added as the reset condition. Select Options > Configuration. In the Language Vendor section select Xilinx XST. Move the cursor to the clear state. Add Reset Icon Click the diagram near the clear state. Click the Add Reset icon in the vertical toolbar. If another value is listed for the reset condition.1 In-Depth Tutorial www. To generate the HDL file. Click OK. select the Generate HDL icon in the toolbar. 4. or the DCM_lock signal is de-asserted low. In this design. ISE 9. Figure 3-28: 5. Creating the State Machine HDL output file 1. 3. Figure 3-27: 2. and click the state bubble. Click OK. 3. specify a reset condition for the state machine. add a reset condition that sends the state machine to the clear state whenever either the reset signal is asserted high. The state machine initializes to this specified state and enters the specified state whenever the reset condition is met. The cursor is automatically attached to the transition arrow for this reset.xilinx. When you see the question being asked: “Should this reset be asynchronous(Yes) or synchronous (No)?” Answer Yes.

In Project Navigator. select Project > Add Source. 8.v(hd) is added to the project in Project Navigator. Creating the State Machine Symbol In this section. In this section. 1. 5. 4. Close the State Diagram Editor. In the Sources tab. Examine the code and then close the browser. The file statmach.vhd (this is the HDL file generated by State Diagram Editor) and click Open. Creating a DCM Module The Clocking Wizard.v. Using the Clocking Wizard Create the dcm1 module as follows: 1.1 In-Depth Tutorial . enables you to graphically select Digital Clock Manager (DCM) features that you wish to use. Select statmach.xilinx. click the + beside Design Utilities to expand the hierarchy. 9. 2.R Chapter 3: Schematic-Based Design 7. you will create a macro symbol for the state machine that you can place on the stopwatch schematic. select the IP (Coregen & Architecture Wizard) source type. 3. Double-click Create Schematic Symbol.vhd or statmach. The macro symbol is added to the project library. Click Next. In the Processes tab. In the New Source dialog box. 76 www. you will create a basic DCM module with CLK0 feedback and duty-cycle correction. A browser opens displaying the generated HDL file.com ISE 9. 3. Save your changes by selecting File > Save. select statmach.v or statmach. 2. and type the filename dcm1. a Xilinx Architecture Wizard. Select Project > New Source.

9. In the Select IP dialog box. Single Feedback Source: Internal Feedback Value: 1X Use Duty Cycle Correction: Selected ISE 9.xilinx. CLK0 and LOCKED ports are selected.Design Entry R 4.com 77 . Type 50 and select MHz for the Input Clock Frequency. 6. 8. Figure 3-29: 5. Select CLKFX port. Verify the following settings: ♦ ♦ ♦ ♦ ♦ Phase Shift: NONE CLKIN Source: External. then click Finish. Verify that RST. The Clocking Wizard is launched.1 In-Depth Tutorial www. 7. Selecting Single DCM Core Type Click Next. Spartan-3A > Single DCM SP. select FPGA Features and Design > Clocking > Spartan3E.

14. In the Processes tab. create a symbol representing the dcm1 macro. 13. select dcm1.General Setup 10.2144Mhz ) ⁄ 2 18 = 100Hz 15. Select Use output frequency and type 26.sch) later in the tutorial. and then click Finish. 11. This symbol will be added to the toplevel schematic (stopwatch. Select the Wait for DCM Lock before DONE Signal goes high option.com ISE 9. 12.2144 in the box and select MHz. Click Next twice to advance to the Clock Frequency Synthesizer page. ( 26. 2. Click Next. Click the Advanced button. 1. in the Sources tab. In Project Navigator. double-click Create Schematic Symbol.R Chapter 3: Schematic-Based Design Figure 3-30: Xilinx Clocking Wizard . Creating the dcm1 Symbol Next. The dcm1.xilinx. 78 www. Click OK.xaw.1 In-Depth Tutorial .xaw file is created and added to the list of project source files in the Sources tab.

The Verilog HDL file is displayed in Figure 3-33. mode and lap_load inputs. A description of the module displays. Click Next to complete the Wizard session. In the File Name field.Design Entry R Creating an HDL-Based Module With ISE. type debounce. Set the Direction field to input for sig_in and clk and to output for sig_out. The resulting HDL file is then modified in the ISE Text Editor.xilinx. Select VHDL Module or Verilog Module. ISE 9. You will author a new HDL module. In the first three Port Name fields type sig_in. Click Finish to open the empty HDL file in the ISE Text Editor. Click Next. This macro will be used to debounce the strtstop. To create the source file: 1. A dialog box opens in which you specify the type of source you want to create. Leave the Bus designation boxes unchecked. 5. b. Using the New Source Wizard and ISE Text Editor In this section. Select Project > New Source. The VHDL file is displayed in Figure 3-32. specifying the name and ports of the component. The HDL code is connected to your top-level schematic design through instantiation and compiled with the rest of the design. you create a file using the New Source wizard. Enter two input ports named sig_in and clk and an output port named sig_out for the debounce component as follows: a. 7. 2. clk and sig_out. Figure 3-31: New Source Wizard for Verilog 6. 4.1 In-Depth Tutorial www. you can easily create modules from HDL code.com 79 . c. 3.

1 In-Depth Tutorial .R Chapter 3: Schematic-Based Design Figure 3-32: VHDL File in ISE Text Editor Figure 3-33: Verilog File in ISE Text Editor 80 www.xilinx.com ISE 9.

Simulation Constructs. and select the template called One-Shot. Click any of the listed templates to view the template contents in the right pane. Using the Language Templates The ISE Language Templates include HDL constructs and synthesis templates which represent commonly used logic components. From Project Navigator. Each HDL language in the Language Templates is divided into five sections: Common Constructs. Use the appropriate template for the language you are using. You will use the Debounce Circuit template for this exercise. When the template is selected in the hierarchy. Keywords are displayed in blue. D flip-flops. and primitives. the ports are already declared in the HDL file. multiplexers. comments in green. click the + next to the section. ISE 9.Design Entry R In the ISE Text Editor. Note: You can add your own templates to the Language Templates for components or constructs that you use often. The file is color-coded to enhance readability and help you recognize typographical errors. and some of the basic file structure is already in place. Synthesis Constructs and User Templates. Under either the VHDL or Verilog hierarchy.com 81 . and values are black.xilinx. select Edit > Language Templates. To invoke the Language Templates and select the template for this tutorial: 1. To expand the view of any of these sections. Debounce Circuit. expand the Misc hierarchy. expand the Synthesis Constructs hierarchy. 2. such as counters. the contents display in the right pane. Device Primitive Instantiation.1 In-Depth Tutorial www. expand the Coding Examples hierarchy.

Click and drag the Debounce Circuit name from the Language Template topology into the debounce. 82 www.vhd file under the architecture begin statement. (Verilog only) Complete the Verilog module by doing the following: a.1 In-Depth Tutorial . 3.xilinx. Close the Language Templates window.com ISE 9. To add the template to your HDL file using the drag and drop method: 1.v file under the module and pin declarations. Select Window > Tile Vertically to show both the HDL file and the Language Templates window. Refer to “Working with Language Templates” in the ISE Help for additional usability options. Change <reg_name> to q in all six locations. or into the debounce. b. 4.R Chapter 3: Schematic-Based Design Figure 3-34: Language Templates Adding a Language Template to Your File You will now use the drag and drop method for adding templates to your HDL file. Remove the reset logic (not used in this design) by deleting the three lines beginning with if and ending with else. 2.

1.xilinx. Figure 3-35: Add Symbol Icon This opens the Symbol Browser to the left of the Schematic Editor. Double-click Create Schematic Symbol. 3. <input> to sig_in.sch). You now have complete and functional HDL code. In the Processes tab. The schematic file opens in the Workspace. 1. a. You will connect components in the schematic later in the tutorial. and <output> to sig_out. In the Processes tab. 5. ISE 9. and Q_OUT to sig_out.1 In-Depth Tutorial www. Placing the statmach. In the Sources tab. c. click the + beside Design Utilities to expand the hierarchy. 7. Save the file by selecting File > Save.vhd or debounce. Close the ISE Text Editor.. Select Add > Symbol or click the Add Symbol icon from the Tools toolbar. You are now ready to place the debounce symbol on the stopwatch schematic. double-click Check Syntax. dcm1 and debounce Symbols You can now place the statmach. as shown in Figure 3-36. In Project Navigator. 8. Move the line beginning with the word signal so that it is between the architecture and begin keywords. Change <clock> to clk. Change <clock> to clk. and debounce symbols on the stopwatch schematic (stopwatch. Remove the reset logic (not used in this design) by deleting the five lines beginning with if (<reset>. select debounce. Note: Do not worry about drawing the wires to connect the symbols. (VHDL only) Complete the VHDL module by doing the following: b. lines. Creating the debounce Symbol Next. Select debounce in the Sources tab. Select the appropriate symbol. create the schematic symbol representing the debounce HDL in Project Navigator. D_IN to sig_in.. 3. dcm1. 9. 2. 6.v. timer_preset. 4.sch. Locate the project-specific macros by selecting the project directory name in the Categories window. and add it to the stopwatch schematic in the approximate location.com 83 . View the list of available library components in the Symbol Browser. which displays the libraries and their corresponding components. 2.Design Entry R c. double-click stopwatch. and ending with else and delete one of the end if. timer_preset.

Save the schematic. Name the top debounce instance lap_load_debounce Name the middle debounce instance mode_debounce. • • • Right-click on the dcm1 symbol instance and select Object Properties from the rightclick menu Change the value of the InstName field to dcm_inst and then click OK. Repeat steps 1 and 2 to change the following symbol instance names. Name the statmach instance timer_state. 84 www.R Chapter 3: Schematic-Based Design 5.com ISE 9. 1. Figure 3-36: Placing Design Macros Changing Instance Names When a symbol is placed on a schematic sheet it is given a unique instance name beginning with the prefix XLXI_.1 In-Depth Tutorial . To help make the hierarchy more readable in the Project Navigator Sources window.xilinx. change the names of the added symbol instances as follows. 2.

or select the Hierarchy Pop icon when nothing in the schematic is selected. ISE 9. Adding Input Pins Next. After examining the macro.com 85 . Name the time_cnt instance timer_cnt. You can also right-click in an open space of the schematic and select Pop to Calling Schematic. mode and strtstop. and select the Hierarchy Push icon. lap_load. When the synthesis tool synthesizes the top-level schematic’s HDL. Click time_cnt symbol in the schematic.xilinx.” which enables you to focus in on a lower-level of the schematic hierarchy to view the underlying file. Figure 3-38: Hierarchy Pop Icon Specifying Device Inputs/Outputs Use the I/O marker to specify device I/O on a schematic sheet. 2. Figure 3-37: Hierarchy Push Icon In the time_cnt schematic. schematic: 1.Design Entry R • • • Name the bottom debounce instance strtstop_debounce. Name the timer_preset instance t_preset. Push into any of the counter blocks by selecting the block and clicking on the Hierarchy Push icon. return to the top-level schematic by selecting View > Pop to Calling Schematic. To push down into time_cnt from the top-level. Hierarchy Push/Pop First. you see five counter blocks. This process may be repeated until the schematic page contains only Xilinx primitive components. Push down into the time_cnt macro. the appropriate text editor or customization GUI will open and be ready to edit the file. the I/O markers are replaced with the appropriate pads and buffers. clk. add five input pins to the stopwatch schematic: reset. stopwatch.1 In-Depth Tutorial www. You can also right-click the macro and select Symbol > Push into Symbol. and examine its components. perform a hierarchy “push down. If a user pushes into a symbol that has an underlying HDL or IP core file. To add these components: • Draw a hanging wire to the two inputs of dcm1 and to the sig_in pin of each debounce symbol Refer to “Drawing Wires” for detailed instructions. which is a schematic-based macro created earlier in this tutorial. All of the Schematic Editor schematics are netlisted to VHDL or Verilog and then synthesized by the synthesis tool of choice.

xilinx. Label the five input nets you just drew. Click and drag a box around the name of the five labeled nets. as you can more easily trace nets back to your original design. 5. To label the reset net: 1. as illustrated in Figure 3-39.com ISE 9. lap_load. Any nets that remain unnamed in the design will be given generated names that will mean nothing to you later in the implementation process. and strtstop pins. Place the name on the leftmost end of the net. Once all of the nets have been labeled. Refer to the completed schematic below.1 In-Depth Tutorial . 6. Type reset into the Name box. to place an input port on each net. Repeat Steps 1 through 3 for the clk. as illustrated in Figure 3-39. 2. Select Add > I/O Marker. add the I/O marker. mode.R Chapter 3: Schematic-Based Design Adding I/O Markers and Net Names It is important to label nets and buses for several reasons: • • • It aids in debugging and simulation. Figure 3-39: Adding I/O Markers to Labeled Nets 86 www. Select Add > Net Name. Naming nets also enhances readability and aids in documenting your design. The net name is now attached to the cursor. 3. 4.

Design Entry R Assigning Pin Locations Xilinx recommends that you let the automatic placement and routing (PAR) program define the pinout of your design. 2. Note: To turn off the Location constraint without deleting it. You may also want to use the completed schematic shown below to complete the schematic. “Design Implementation”. Click the New button under Net Attributes to add a new property. select Add and then OK. select the Add button adjacent to the LOC attribute in the Attribute window. Notice that the LOC property has already been added to the sf_d(7:0) bus. and labeling nets appropriately. Each of the actions referred ISE 9. 6. The following steps guide you through the process of completing the schematic. Click OK to return to the Object Properties dialog box. adding any additional necessary logic. For this tutorial. The above procedure constrains clk to pin E12.com 87 . The remaining pin location constraints will be added in “Using the Constraints Editor” and “Using the Floorplan Editor” of Chapter 5. 3. it may be necessary at some point to lock the pinout of a design so that it can be integrated into a Printed Circuit Board (PCB). the example pin assignments will not adversely affect the ability of PAR to place and route the design. Enter LOC for the Attribute Name and E12 for the Attribute Value. Completing the Schematic Complete the schematic by wiring the components you have created and placed. the inputs and outputs will be locked to specific pins in order to place and download the design to the Spartan-3A demo board. Pre-assigning locations to the pins can sometimes degrade the performance of the place-and-route tools. Assign a LOC parameter to the output nets on the stopwatch schematic. Figure 3-40: 5. as follows: 1.1 In-Depth Tutorial www. select the loc attribute. In the Net Attribute Visibility window. Click OK to close the Object properties window. Select VHDL or Verilog and select Ignore this attribute. This will display the LOC attribute on the schematic above the clk net.xilinx. However. and click Edit Traits. Assigning Pin Locations To make the LOC attribute visible. 4. Right-click on the clk net and select Object Properties from the right-click menu. Because the tutorial stopwatch design is simple and timing is not critical.

” Draw a hanging wire to the clk input of both the time_cnt and statmach macros. See “Drawing Wires” and “Adding Net Names. Figure 3-41: Completed Stopwatch Schematic To complete the schematic diagram: 1. (See “Drawing Wires. Draw a hanging wire to the LOCKED_OUT pin of DCM1 and name the wire locked.”) 88 www.1 In-Depth Tutorial .R Chapter 3: Schematic-Based Design to in this section has been discussed in detail in earlier sections of the tutorial. Please see the earlier sections for detailed instructions.com ISE 9.xilinx. 2.

See “Drawing Wires. Name both wires clk_100. 11. This method is used to make the logical connection of clk_100 and several other signals. ISE 9.com 89 . 10.”) Note: Remember that nets are logically connected if their names are the same. 6.1 In-Depth Tutorial www. See “Drawing Wires. See “Drawing Wires” and “Adding Net Names. See “Drawing Wires. (See “Adding Net Names. See “Drawing Wires.” Name the nets lap and mode_control respectively. “Behavioral Simulation.” Notice how the wire is automatically converted to a bus. Draw a hanging wire to the clken output of the statmach component and another hanging wire to the ce pin of the time_cnt component. Name them locked and reset. Proceed to Chapter 5.” Label both wires rst_int.” Add hanging wires to the dcm_lock pin and the reset pin of the statmach macro. Name both wires clk_en_int. mode_debounced. mode_in and strtstop pin of the statmach macro. Save the design by selecting File > Save. 9. 12. 5.xilinx.” to perform a pre-synthesis simulation of this design. To continue with the schematic flow. Draw hanging wires from the load output of the statmach macro and the load input of the time_cnt macro.” Name the wire mode_control. 7. Draw a wire from the bus output of the timer_preset to the q(19:0) input of the time_cnt macro. See “Drawing Wires. do the following: • • Go to Chapter 4. Draw a hanging bus on the input of the timer_preset macro and name the bus address(5:0).Design Entry R 3. respectively. “Design Implementation. 8.” Name both wires load. 4. The schematic is now complete. Draw a wire to connect the clk inputs of the three debounce macros and name the wire clk_26214k.” to place and route the design. even if the net is not physically drawn as a connection in the schematic. and strtstop_debounced. Draw hanging wires from the rst output pin of the statmach macro and the clr pin of the time_cnt macro. Label the nets ll_debounced. Draw a hanging wire to the up input time_cnt macro. You have now completed the schematic design. Draw wires between the sig_out pins of the debounce components and the lap_load. Draw wires from the lap_trigger and mode outputs of the statmach macro to the lap and mode inputs of the lcd_control macro.

com ISE 9.R Chapter 3: Schematic-Based Design 90 www.xilinx.1 In-Depth Tutorial .

Older versions may work but are not supported. This Guide is accessible from within ISE by selecting Help > Software Manuals. please contact Mentor Graphics.com 91 . and from the web at http://www. For more information about ModelSim PE or SE. Whether you use the ModelSim simulator or the ISE Simulator with this tutorial. In order to simulate with the ISE 9 libraries. • • • • • • • “Overview of Behavioral Simulation Flow” “ModelSim Setup” “ISE Simulator Setup” “Getting Started” “Adding an HDL Test Bench” “Behavioral Simulation Using ModelSim” “Behavioral Simulation Using ISE Simulator” Overview of Behavioral Simulation Flow Xilinx® ISE™ provides an integrated flow with the Mentor ModelSim simulator and the Xilinx ISE Simulator that allows simulations to be run from the Xilinx Project Navigator.0 or later. see Chapter 6 of the Synthesis and Simulation Design Guide. and ModelSim XE.R Chapter 4 Behavioral Simulation This chapter contains the following sections.xilinx.1 In-Depth Tutorial www. you must install ModelSim on your computer.com/support/sw_manuals/xilinx9/. ModelSim Setup In order to use this tutorial. The examples in this tutorial demonstrate how to use the integrated flow. For additional information about simulation. The following sections discuss requirements and setup for ModelSim PE. you will achieve the same results. ModelSim SE. ModelSim PE and SE ModelSim PE and ModelSim SE are full versions of ModelSim available for purchase directly from Mentor Graphics. use ModelSim 6.xilinx. and for a list of other supported simulators. ISE 9.

a test bench file is required to provide stimulus to the design. The design in this tutorial requires the use of simulation libraries because it contains instantiations of a digital clock manager (DCM) and a CORE Generator™ component. Be sure to select 9. and a full version.jsp?update=mxe_libs ISE Simulator Setup ISE Simulator is automatically installed and set up with the ISE 9. “Xilinx Simulation Libraries.1i installer. go to the Download Center page.1i as the ISE version. see “Creating a Test Bench Waveform Using the Waveform Editor. see the next section. Getting Started The following sections outline the requirements for performing behavioral simulation in this tutorial.” 92 www. Test Bench File In order to simulate the design.com ISE 9.1 In-Depth Tutorial . “HDL-Based Design. To obtain the correct MXE III simulation libraries. or Schematic) This chapter assumes that you have completed the design entry tutorial in either Chapter 2. For information on simulation libraries and how to compile them. Windows XP. For instructions.com/ise/optional_prod/mxe. your design includes the required design files. and is ready for simulation.xilinx. and Xilinx simulation libraries.com/xlnx/xil_sw_updates_home. Verilog.” or Chapter 3.xilinx. VHDL and Verilog test bench files are available with the tutorial files.” Xilinx Simulation Libraries Xilinx simulation libraries are required when a Xilinx primitive or IP core is instantiated in the design. Required Files The behavioral simulation flow requires design files. The ISE Simulator is available on Windows 2000.htm. For more information about MXE III including how to purchase the software. “Schematic-Based Design. You may also create your own test bench file.” After you have completed one of these chapters. Design Files (VHDL. and Red Hat Enterprise Linux 3 or 4 platforms only. There are two versions of MXE III available for purchase from Xilinx: a free “starter” version.R Chapter 4: Behavioral Simulation ModelSim Xilinx Edition ModelSim Xilinx Edition III (MXE III) is the Xilinx version of ModelSim which is based on ModelSim PE.xilinx. a test bench file. please visit: http://www. http://www.

xilinx.1 In-Depth Tutorial www. and provide the simulator with the information required to perform simulation.ini file to determine the location of the compiled libraries.com 93 .com/support/sw_manuals/xilinx9/. CORE Generator components. ISE 9. All other models are updated each time a service pack is installed. see Chapter 5 of the Synthesis and Simulation Design Guide. See Chapter 6 of the Synthesis and Simulation Design Guide. ModelSim searches for a modelsim.ini file in the directory where ModelSim or MXE is installed. The modelsim. if you compiled the UNISIM library to c:\lib\UNISIM. This Guide is accessible from within ISE by selecting Help > Software Manuals. and from the web at http://www.com/xlnx/xil_sw_updates_home.xilinx.ini file pointed to by the MODELSIM environment variable. Updating the Xilinx Simulation Libraries The Xilinx simulation libraries contain models that are updated on a regular basis.ini file in the following locations until one is found: • • • The modelsim. Download the latest precompiled models from the Download Center at http://www. or from the web at http://www.ini is not applicable to the ISE Simulator.com/support/sw_manuals/xilinx9/. and other Xilinx IP cores you must use the Xilinx simulation libraries. For instance. ModelSim Xilinx Edition III Updated models for ModelSim Xilinx Edition III (MXE III) are precompiled and available on the Xilinx support website. you must compile the simulation libraries with the updated models. Mapping Simulation Libraries in the Modelsim. the following mapping appears in the modelsim. These libraries contain models for each component. These models reflect the functions of each component. you must recompile the libraries. ModelSim PE or SE If you are using ModelSim PE or SE. For a detailed description of each library.ini File ModelSim uses the modelsim.jsp?update=mxe_libs. This Guide is accessible from within ISE by selecting Help > Software Manuals. The compiled Xilinx simulation libraries are then available during the simulation of any design.ini file: UNISIM = c:\lib\UNISIM Note: The modelsim. • • The XilinxCoreLib models are updated each time an IP Update is installed. Xilinx ISE Simulator Updated simulation libraries for the ISE Simulator are precompiled and installed with ISE installations and service packs.xilinx.xilinx.Getting Started R Xilinx Simulation Libraries To simulate designs that contain instantiated Xilinx primitives. The modelsim.ini file in the current working directory. When the models are updated.

While compiling the libraries. A VHDL test bench and Verilog test fixture are provided with this tutorial. and adds the test bench in the correct order. Adding Tutorial Test Bench File This section demonstrates how to add pre-existing test bench file to the project. Select the test bench file stopwatch_tb. COMPXLIB also updates the modelsim. ISE Simulator The modelsim. Note: To create your own test bench file in ISE. All of the Xilinx simulation libraries are already mapped to the proper location.R Chapter 4: Behavioral Simulation If the MODELSIM environment variable is not set. select VHDL Test Bench File. or you can use the MODELSIM environment variable to point to the desired modelsim. open the modelsim. select Project > New Source.1 In-Depth Tutorial .ini file is not applicable to the ISE Simulator.com ISE 9. Click Open. VHDL Simulation After downloading the file to your project directory.ini file with the correct mapping. Select Project > Add Source. or create your own test bench file and add it to your project.xilinx. Adding an HDL Test Bench In order to add an HDL test bench to your design project. 3. ISE recognizes the top-level design file associated with the test bench. ModelSim Xilinx Edition III If you are using ModelSim Xilinx Edition III (MXE III). Click OK.ini file.vhd.ini file has not been copied to the working directory. 94 www. and the modelsim. ModelSim PE or SE If you are using ModelSim PE or SE. you can copy the modelsim. refer to the Development System Reference Guide and use COMPXLIB to compile the libraries. you can either add a test bench file provided with this tutorial. Open the modelsim. add the tutorial VHDL test bench to the project: 1. 5. and select either VHDL Test Bench or Verilog Text Fixture in the New Source Wizard.ini file in the installation directory is used.ini file to the working directory and make changes that are specific to that project. You must define the test bench in a text editor. 2.ini file in the directory where MXE III was installed. For future projects.ini file and make sure that the library mappings are correct. 4. An empty stimulus file is added to your project. In the Choose Source Type dialog box. the modelsim.

ISE 9.v. In the Processes tab. 2. To simulate with the ISE Simulator. Select Project > Add Source. 2. or Project Navigator cannot find modelsim. compile the source files.1 In-Depth Tutorial www. ISE recognizes the top-level design file associated with the test fixture. load the design. 3. To locate the ModelSim simulator processes: 1. 2. the Project Navigator preferences may not be set correctly. In the Sources tab. either ModelSim is not selected as the Simulator in the Project Properties dialog box. and adds the test fixture in the correct order. 4. and perform simulation based on simulation properties. To select ModelSim as your project simulator: 1. Select the test bench file (stopwatch_tb). the end result is the same. select the Modelsim type and HDL language combination you are using. ISE has full integration with the ModelSim Simulator. select Behavioral Simulation in the Sources for field. 2. ISE enables ModelSim to create the work directory. skip to “Behavioral Simulation Using ISE Simulator. Click the + next to ISE General to expand the ISE preferences Click Integrated Tools in the left pane. right-click the device line (xc3s700A-4fg484). If the ModelSim Simulator processes do not appear. Select the file stopwatch_tb. To set the ModelSim location: 1. Behavioral Simulation Using ModelSim Now that you have a test bench in your project. Click OK. select Verilog Test Fixture File. 5. In the Choose Source Type dialog box.xilinx. click the + beside ModelSim Simulator to expand the process hierarchy.com 95 . Select Edit > Preferences. 3. 3.Behavioral Simulation Using ModelSim R Verilog Simulation After downloading the file to your project directory.exe. Click Open. you can perform behavioral simulation on the design using the ModelSim simulator. Select Properties. If ModelSim is installed but the processes are not available.” Whether you choose to use the ModelSim simulator or the ISE Simulator for this tutorial. In the Simulator field of the Project Properties dialog box. In the Sources tab. add the tutorial Verilog test fixture to the project: 1. Locating the Simulation Processes The simulation processes in ISE enable you to run simulation on the design using ModelSim. 3.

under Model Tech Simulator. select the test bench file (stopwatch_tb). ISE allows you to set several ModelSim Simulator properties in addition to the simulation netlist properties. browse to the location of the modelsim. You can also use this process to update an existing self-checking test bench. Select Properties. Note: This process is available only if you have a test bench waveform file from the ISE Simulator’s Test Bench Waveform Editor. 4.com ISE 9. If you double-click this process.xilinx. ModelSim runs in the background to generate expected results and displays them in the ISE Simulator’s Test Bench Waveform Editor.exe file. and to modify the properties for this tutorial: 1. To see the behavioral simulation properties. c:\modeltech_xe\win32xoem\modelsim. In the Process Properties dialog box. 5.” Specifying Simulation Properties You will perform a behavioral simulation on the stopwatch design after you have set some process properties for simulation. For example.1 In-Depth Tutorial . (Figure 4-1) set the Property display level to Advanced. 2. Generate a self-checking HDL test bench This process enables you to generate a self-checking HDL test bench equivalent to a test bench waveform (TBW) file and add the test bench to your project.R Chapter 4: Behavioral Simulation 4. 96 www. Right-click Simulate Behavioral Model. See “Creating a Test Bench Waveform Using the Waveform Editor.exe The following simulation processes are available: • • Simulate Behavioral Model This process starts the design simulation. 3. This global setting enables you to now see all available properties. Click the + sign next to ModelSim Simulator to expand the hierarchy in the Processes tab. In the right pane. The test bench generated by this process contains output data and self-checking code that can be used to compare the data from later simulation runs. In the Sources tab.

loads the design. Additional signals are displayed in the Signal window based on the selected structure in the Structure window. Adding Signals To view internal signals during the simulation.Behavioral Simulation Using ModelSim R 6. There are two basic methods for adding signals to the Simulator Wave window. ISE 9. Figure 4-1: Behavioral Simulation Process Properties 7. Performing Simulation Once the process properties have been set. For the purpose of this tutorial. only the DCM signals are monitored to verify that they work correctly. For a detailed description of each property available in the Process Properties dialog box. Click OK. and performs simulation for the time specified. The majority of this design runs at 100 Hz and would take a significant amount of time to simulate. click Help. To start the behavioral simulation. The first outputs to transition after RESET is released are the SF_D and LCD_E control signals at around 33 mS. Change the Simulation Run Time to 2000 ns. ModelSim creates the work directory.com 97 . Highlight signals in the Signal/Object window. and select Add > Wave > Selected Signals. you must add them to the Wave window. ISE automatically adds all the top-level ports to the Wave window.xilinx. double-click Simulate Behavioral Model. This is why the counter may seem like it is not working in a short simulation. you are ready to run ModelSim. compiles the source files. • • Drag and drop from the Signal/Object window.1 In-Depth Tutorial www.

R Chapter 4: Behavioral Simulation The following procedure explains how to add additional signals in the design hierarchy. ♦ ♦ ♦ ♦ RST_IN CLKFX_OUT CLK0_OUT LOCKED_OUT 98 www. Click and drag CLKIN_IN from the Signal/Object window to the Wave window. The graphics and the layout of the Structure/Instance window for a schematic or VHDL flow may be different. Figure 4-3 shows the Structure/Instance window for the Verilog flow. 4. Structure/Instance Window . To select multiple signals. Figure 4-3: 2.com ISE 9. In the Structure/Instance window. Figure 4-2: Undock icon To add additional signals in the design hierarchy: 1. hold down the Ctrl key. If you are using ModelSim version 6. In this tutorial. To undock the windows.0 or higher.xilinx. you will be adding the DCM signals to the waveform. click the + next to uut to expand the hierarchy.Verilog flow Select dcm1 in the Structure/Instance window. select the following signals. The signals listed in the Signal/Object window are updated. In the Signal/Object window.1 In-Depth Tutorial . click the Undock icon. 3. all the windows are docked by default.

5. Select Add to Wave > Selected Signals. To add a divider called DCM Signals: 1. 3. Click OK. This is because ModelSim did not record the data for these signals. ModelSim records data only for the signals that have been added to the Wave window while the simulation is running.com 99 . By default.xilinx. Rerunning Simulation To rerun simulation in ModelSim: 1. After adding the DCM Signals divider. undock the window and maximize the window for a larger view of the waveform. the waveform will look like Figure 4-4. If necessary.1 In-Depth Tutorial www. you can add dividers in the Wave window to make it easier to differentiate the signals. Right-click in the Signal/Object window. you must rerun the simulation for the desired amount of time.Behavioral Simulation Using ModelSim R 5. Click the Restart Simulation icon. 4. Select Insert Divider. Right click anywhere in the signal section of the Wave window. 2. Adding Dividers In ModelSim. 6. Figure 4-4: Waveform After Adding DCM Signals Divider The waveforms have not been drawn for any of the newly added signals. Enter DCM Signals in the Divider Name box. After new signals are added to the Wave window. Click and drag the newly created divider to above the CLKIN_IN signal. Figure 4-5: Restart Simulation Icon ISE 9.

2.com ISE 9.xilinx. Click the Find Next Transition icon twice to move the cursor to the next rising edge on the CLK0_OUT signal. At the ModelSim command prompt. 4. Press Enter. The waveforms for the DCM are now visible in the Wave window. 3. Figure 4-7: Entering the Run Command The simulation runs for 2000 ns. Restart Dialog Box In the Restart dialog box.1 In-Depth Tutorial . Analyzing the Signals The DCM signals can be analyzed to verify that they work as expected. The CLK0_OUT needs to be 50 MHz and the CLKFX_OUT should be ~26 MHz. 3. The DCM outputs are valid only after the LOCKED_OUT signal is high. the DCM signals are analyzed only after the LOCKED_OUT signal has gone high. click Restart. therefore. enter run 2000 ns. Figure 4-8: Find Next Transition Icon 100 www. Click and drag the second cursor just to the right of the first. Click and drag one cursor to the first rising edge transition on the CLK0_OUT signal after the LOCKED_OUT signal has gone high. ModelSim enables you to add cursors to measure the distance between signals. To measure the CLK0_OUT: 1. 4. Select Add > Wave > Cursor twice to add two cursors.R Chapter 4: Behavioral Simulation Figure 4-6: 2.

3. and perform simulation based on simulation properties. ISE has full integration with the ISE Simulator.” Now that you have a test bench in your project. select Behavioral Simulation in the Sources for field. To select ISE Simulator as your project simulator: 1. and after simulation is rerun. After restarting the simulation. 2. To implement the design.” Behavioral Simulation Using ISE Simulator Follow this section of the tutorial if you have skipped the previous section. This converts to 50 MHz. In the Sources tab. which is the input frequency from the test bench. Measure CLKFX_OUT using the same steps as above. 3.1 In-Depth Tutorial www.xilinx. In the Save Format dialog box. Select the test bench file (stopwatch_tb). rename the file name from the default wave. “Behavioral Simulation Using ModelSim. 2.do to dcm_signal. “Design Implementation. 2. Click the + beside Xilinx ISE Simulator to expand the process hierarchy. load the design. ISE enables ISE Simulator to create the work directory. In the Sources tab.com 101 . you can perform behavioral simulation on the design using the ISE Simulator. The measurement should read 38462 ps.Behavioral Simulation Using ISE Simulator R 5. This comes out to approximately 26 MHz. follow the steps in Chapter 5. Your behavioral simulation is complete. Saving the Simulation The ModelSim simulator enables you to save the signals list in the Wave window after new signals or stimuli are added. Locating the Simulation Processes The simulation processes in ISE enable you to run simulation on the design using ISE Simulator. In the Project Properties dialog box. Look at the bottom of the waveform for the distance between the two cursors. Click Save. To locate the ISE Simulator processes: 1.do. To save the signals list: 1. 3. right-click the device line (xc3s700A-4fg484). In the Wave window. ISE 9. select ISE Simulator in the Simulator field. compile the source files. The saved signals list can easily be opened each time the simulation is started. select File > Save as. Select Properties. which in turn should be the DCM CLK0 output. select File > Load in the Wave window to load this file. The measurement should read 20000 ps. 6.

3. set the Property display level to Advanced. Note: This process is available only if you have a test bench waveform file from the ISE Simulator’s Test Bench Waveform Editor. click Help. ModelSim runs in the background to generate expected results and displays them in the ISE Simulator’s Test Bench Waveform Editor. Generate a self-checking HDL test bench This process enables you to generate a self-checking HDL test bench equivalent to a test bench waveform (TBW) file and add the test bench to your project. To see the behavioral simulation properties.R Chapter 4: Behavioral Simulation The following simulation processes are available: • • • Check Syntax This process checks for syntax errors in the test bench. Select Properties. 7. Change the Simulation Run Time to 2000 ns.” Specifying Simulation Properties You will perform a behavioral simulation on the stopwatch design after you set some process properties for simulation. ISE allows you to set several ISE Simulator properties in addition to the simulation netlist properties. 2. 6. 102 www. The test bench generated by this process contains output data and self-checking code that can be used to compare the data from later simulation runs. Simulate Behavioral Model This process starts the design simulation. This global setting enables you to now see all available properties. See “Creating a Test Bench Waveform Using the Waveform Editor. Note: For a detailed description of each property available in the Process Property dialog box. In the Process Properties dialog box (Figure 4-9). Right-click the Simulate Behavioral Model process.1 In-Depth Tutorial .com ISE 9. Click the + sign next to ISE Simulator to expand the hierarchy in the Processes tab. 4. and to modify the properties for this tutorial: 1. You can also use this process to update an existing self-checking test bench. Click Apply and click OK. select the test bench file (stopwatch_tb). 5. In the Sources tab. If you double-click this process.xilinx.

2. Click the + next to uut stopwatch to expand the hierarchy. In the Sim Hierarchy window. only the DCM signals are monitored to verify that they work correctly. The majority of this design runs at 100 Hz and would take a significant amount of time to simulate. compiles the source files. double-click Simulate Behavioral Model. you are ready to run the ISE Simulator. ISE automatically adds all the top-level ports to the Waveform window. Adding Signals To view signals during the simulation.xilinx.1 In-Depth Tutorial www. Additional signals are displayed in the Sim Hierarchy window. ISE Simulator creates the work directory.com 103 . and performs simulation for the time specified. For the purpose of this tutorial. The following procedure explains how to add additional signals in the design hierarchy. you must add them to the Waveform window. add the DCM signals to the waveform. To add additional signals in the design hierarchy: 1. The first outputs to transition after RESET is released are SF_D and LCD_E at around 33 mS. To start the behavioral simulation.Behavioral Simulation Using ISE Simulator R Figure 4-9: Behavioral Simulation Process Properties Performing Simulation Once the process properties have been set. loads the design. click the + next to stopwatch_tb to expand the hierarchy. This is why the counter may seem like it is not working in a short simulation. ISE 9. For the purpose of this tutorial.

Click the Restart Simulation icon. By default. This is because ISE Simulator did not record the data for these signals. Notice that the waveforms have not been drawn for the newly added signals. The graphics and the layout of the window for a schematic or VHDL flow may be different. Figure 4-11: ISE Simulator Restart Simulation Icon 104 www.1 In-Depth Tutorial . Select the following signals: ♦ ♦ ♦ ♦ RST_IN CLKFX_OUT CLK0_OUT LOCKED_OUT To select multiple signals. Drag all the selected signals to the waveform. Figure 4-10: Sim Hierarchy Window . 5. when new signals are added to the waveform window. right click on a selected signal and select Add To Waveform.R Chapter 4: Behavioral Simulation Figure 4-10 shows the Sim hierarchy window for the Verilog flow. Click the + next to dcm1 in the Sim Hierarchy window. Rerunning Simulation To rerun the simulation in ISE Simulation: 1. hold down the Ctrl key. ISE Simulator records data only for the signals that have been added to the waveform window while the simulation is running. Alternatively. 4. Therefore.Verilog flow 3.xilinx. 6. Click and drag CLKIN_IN from the Sim Hierarchy window to the Waveform window.com ISE 9. you must rerun the simulation for the desired amount of time.

which is the input frequency from the test bench.xilinx. Click the Measure Marker icon.0 ns.Behavioral Simulation Using ISE Simulator R 2. To create a test bench with the ISE Simulator Waveform Editor: 1. The simulation runs for 2000 ns. enter run 2000 ns and press Enter. 6. If necessary. Select time_cnt in the Sources tab. ISE Simulator can add markers to measure the distance between signals. It is not necessary to follow this section if you have added the tutorial test bench to the project already. 4. You can use the Waveform Editor to graphically enter stimuli. At the ISE Simulator command prompt in the Sim Console. To measure the CLK0_OUT: 1. Look at the top of the waveform for the distance between the marker. which in turn is the DCM CLK0 output. This equals approximately 26 MHz. Creating a Test Bench Waveform Source In this tutorial. The measurement should read 20. This converts to 50 MHz. In the New Source Wizard. follow the steps in Chapter 5. Analyzing the Signals Now the DCM signals can be analyzed to verify that they work as expected.com 105 . Measure Marker Icon Place the marker on the first rising edge transition on the CLK0_OUT signal after the LOCKED_OUT signal has gone high. Your behavioral simulation is complete. 3. The Waveform Editor is a test bench creation tool in ISE. The measurement should read 38. The Waveform Editor can be used to generate stimuli for top-level designs as well. Measure CLKFX_OUT using the same steps as above. Click and drag the other end of the marker to the next rising edge. 4. The waveforms for the DCM are now visible in the Waveform window. select Test Bench Waveform as the source type. ISE 9. 5. The CLK0_OUT should be 50 MHz and the CLKFX_OUT should be ~26 MHz. zoom in on the waveform. therefore. 2.5 ns. Type time_cnt_tb. “Design Implementation. The DCM outputs are valid only after the LOCKED_OUT signal is high. Select Project > New Source.1 In-Depth Tutorial www. create the test bench waveform for a sub-module only. and to generate a VHDL test bench or Verilog test fixture. To implement the design. the DCM signals are analyzed only after the LOCKED_OUT signal has gone high. 2.” Creating a Test Bench Waveform Using the Waveform Editor This section demonstrates how to use the Waveform Editor. Figure 4-12: 3.

In the Initialize Timing dialog box. 8. Figure 4-13: Waveform Editor . fill in the fields as follows: ♦ ♦ ♦ ♦ Clock Time High: 10 Clock Time Low: 10 Input Setup Time: 5 Output Valid Delay: 5 9. the time_cnt file is the default source file because it is selected in the Sources tab (step 1). Change the Initial Length of Test Bench to 3000. Click Finish. The Initialize Timing dialog box displays.xilinx.R Chapter 4: Behavioral Simulation 5.1 In-Depth Tutorial . The Output Valid Delay field defines the time after active clock edge when the outputs must be valid. 7. 11. and enables you to specify the timing parameters used during simulation. Select the GSR (FPGA) from the Global Signals section. The Waveform Editor opens in ISE. Click Next. 6. Click Next.com ISE 9. Click Finish.Initialize Timing Dialog Box 106 www. The Input Setup Time field defines when inputs must be valid. Note: In the Select dialog box. 10. The Clock Time High and Clock Time Low fields together define the clock period for which the design must operate.

The new test bench waveform source (time_cnt_tb.xilinx. Click the CLR cell at time 230 ns to set it low. 5. 3. Applying Stimulus In the Waveform Editor. Enter the following input stimuli: 1.1 In-Depth Tutorial www. Figure 4-14: 4. ISE 9. Select time_cnt_tb. Click the CE cell at time 110 ns to set it high (CE is active high). Double-click Generate Self-Checking Test Bench in the Process tab.tbw) is automatically added to the project. A test bench containing output data and self checking code is generated and added to the project.com 107 . in the blue cell.tbw in the Sources tab. 2. you can apply a transition (high/low). 6.Behavioral Simulation Using ISE Simulator R The ISE Simulator’s Waveform Editor View opens in ISE. The created test bench can be used to compare data from later simulation. Applying Stimulus in the Waveform Editor View Click the Save icon in the toolbar. Click the CLR cell at time 150 ns to set it high. The width of this cell is determined by the Input setup delay and the Output valid delay.

1 In-Depth Tutorial .xilinx.com ISE 9.R Chapter 4: Behavioral Simulation 108 www.

NGC) from the front-end tool to the back-end Design Implementation tools. mapping. placing. and you will be incorporating placement constraints through a User Constraints File (UCF). For details about compiling the design. “Schematic-Based Design. The front-end design has already been compiled in an EDA interface tool.1 In-Depth Tutorial www. ISE 9. see Chapter 2.R Chapter 5 Design Implementation This chapter contains the following sections. and generating a BIT file for your design. • • • • • • • • • • • • • • • • • “Overview of Design Implementation” “Getting Started” “Specifying Options” “Creating Partitions” “Creating Timing Constraints” “Translating the Design” “Using the Constraints Editor” “Using the Floorplan Editor” “Mapping the Design” “Using Timing Analysis to Evaluate Block Delays After Mapping” “Placing and Routing the Design” “Using FPGA Editor to Verify the Place and Route” “Evaluating Post-Layout Timing” “Changing HDL with Partition” “Creating Configuration Data” “Creating a PROM File with iMPACT” “Command Line Implementation” Overview of Design Implementation Design Implementation is the process of translating. you will be passing an input netlist (EDN. “HDL-Based Design” or Chapter 3. You will add timing constraints later through the Floorplan Editor.com 109 . This chapter is the first in the “Implementation-only Flow” and is an important chapter for the “HDL Design Flow” and the “Schematic Design Flow”. This chapter demonstrates the ISE Implementation flow.xilinx.” In this chapter. routing. The Design Implementation tools are embedded in the ISE™ software for easy access and project management.

In the Sources tab. you have created a project.htm. 6. 5. Skip to the “Specifying Options” section.xilinx. Click Finish. 3.edn. MODE. Required Tutorial Files File Name stopwatch. you will need to download the presynthesized design files provided on the Xilinx® web-site. 2. If you do not have a stopwatch. 4. 7. 1. 2. LAP_LOAD. create a project in ISE and then add the downloaded source files to the project. stopwatch. you are now ready to begin this chapter.ucf Description Input netlist file (EDIF) Table 5-1: Timer netlist file (NGC) User Constraints File 110 www.com ISE 9.ngc timer_preset. There are five inputs to the system: CLK. Click Next.ucf as the file name. Go to http://www. Type stopwatch.xilinx.R Chapter 5: Design Implementation Getting Started The tutorial design emulates a runner’s stopwatch with actual and lap times.1 In-Depth Tutorial . Continuing from Design Entry If you have followed the tutorial using either the HDL Design flow or the Schematic Design flow. and an EDIF netlist file. Select Project > New Source.edf or stopwatch.ucf file in your project. Create an empty working directory named Watch. Select stopwatch from the list. create one as follows: 1. 8. This system generates a traditional stopwatch with lap times and a traditional timer on a LCD display. RESET. Select Implementation Constraints File. design entry source files. and copy the pre-synthesized tutorial files (see Table 5-1) to your newly created working directory. select the top-level source file stopwatch. Click Next.com/support/techsup/tutorials/tutorial9.ngc stopwatch. With a UCF in the project. Starting from Design Implementation If you are beginning the tutorial from this chapter. and SRTSTP.

ISE 9. and optimizes a design. f. places. 6. Map. This setting is in the lower.Specifying Options R 3. On a PC. In the Sources tab. Change Report Type to Verbose Report. h. Select EDIF for the top_level SourceType. 2. Click Next. This enables the design to be implemented. Select the following: Click Next. Click the Post-Map Static Timing Report Properties category. select Start > Programs > Xilinx ISE 9. Open ISE. Click Next. Click the Post-Place & Route Static Timing Report Properties category. In the Processes tab. c. 8. On a workstation. 4. In the Sources tab.ucf for the Constraints file. fg484 for the Package 4. k. Type EDIF_Flow for the Project Name. To set the implementation property options for this tutorial: 1. i. Create a new project and add the EDIF netlist as follows: a. stopwatch. a. routes. Ensure that you have set the Property display level to Advanced. Spartan3a for the Device Family xc3s700a for the Device -4 for the Speed Grade. 3. Select stopwatch. select the stopwatch top-level file.xilinx. Place and Route.1i > Project Navigator.ngc file into the EDIF_Flow directory. Copy the timer_preset. The Process Properties dialog box provides access to the Translate. The implementation properties control how the software maps. e.edf or stopwatch. You will notice a series of categories. Simulation.edn. This report will be generated after the Map process is completed. each contains properties for a different aspect of design implementation. 5. d. j. enter ise &. Select stopwatch. and Timing Report properties. This global setting enables you to see all available properties. right-hand corner of the dialog box. Click Finish. Select Properties from the right-click menu. b. select the top-level module. Specifying Options This section describes how to set some properties for design implementation. g. Change Report Type to Verbose Report. b.1 In-Depth Tutorial www. right-click the Implement Design process.com 111 . 7.edn for the Input Design file. Select File > New Project.

com ISE 9. Figure 5-1: Post-Place & Route Static Timing Report Properties 9.1 In-Depth Tutorial . 10. Click the Place & Route Properties category.xilinx. 112 www. Change the Place & Route Effort Level (Overall) to High.R Chapter 5: Design Implementation This report will be generated after Place and Route is completed.

If you are doing the EDIF flow. including HDL changes and certain constraint changes. The top level of the HDL design has a default partition. the partition is set on the entity architecture.xilinx. Partitions do not need ranges for implementation re-use. Partitions automatically detect input source changes. In Verilog. The creation of Partitions was done through the synthesis tool. To enable partitions for this design: ISE 9. Creating Partitions A partition is created for an instance in your logical design to indicate that the implementation for that instance should be reused when possible. such as effort levels on implementation tools.1 In-Depth Tutorial www. Partitions can be nested hierarchically and be defined on any HDL module instance in the design. A module with multiple instances can have multiple partitions—a partition on each instance. Click OK to exit the Process Properties dialog box. the partition is set on the module instance and for VHDL.Creating Partitions R This option increases the overall effort level of Place and Route during implementation. and only the effected partitions are re-implemented. Figure 5-2: Place & Route Properties 11. you will not get the option to create Partitions in Project Navigator. Partitions also detect command line changes.com 113 . and logic can be at the top level partition. Please proceed to the next section.

R Chapter 5: Design Implementation 1. you must understand the exact syntax needed to define constraints. 4. 3. 2. The preserve status can be changed to Routing. However. select lcd_cntrl_inst module and right-click on it. right click on a partitioned source file and select Partition Properties.com ISE 9.1i there is a known issue that will not allow MAP to complete a second iteration if a Partition is placed on a schematic module. Select New Partition from the menu. Creating Timing Constraints The User Constraints File (UCF) provides a mechanism for constraining a logical design without returning to the design entry tools. select Stopwatch In the Processes tab. Placement. or Synthesis. The Constraints Editor and Floorplan Editor are graphical tools that enable you to enter timing and pin location constraints.xilinx. The top level partition is set to routing by default. 114 www. without the design entry tools.1 In-Depth Tutorial . To launch the Constraints Editor: 1. Note: In ISE 9. In the Sources tab. Figure 5-3: New Partitions on LCD_CNTRL_INST module The Preserve status is set to inherit. expand the User Constraints hierarchy. 2. To do this. which gets the status from the top level partition. In the Sources tab. Repeat steps 1 and 2 for the timer_inst module in VHDL and Verilog designs only. Repeat steps 1 and 2 for the timer_state module.

• • ISE 9. The merged netlist describes the logic in the design as well as any location and timing constraints.Translating the Design R 3. During translation. Typically.xilinx. Then the Constraints Editor opens. the NGDBuild program performs the following functions: • Converts input design netlists and writes results to a single merged NGD netlist. Adds constraints from the User Constraints File (UCF) to the merged netlist. Performs timing specification and logical design rule checks. Translating the Design ISE manages the files created during implementation. This gives you complete control over how a design is processed. This tutorial illustrates the implementation. one step at a time. The ISE tools use the settings that you specified in the Process Properties dialog box. You then run through the entire flow by double-clicking Implement Design. you set your options first. Figure 5-4: Create Timing Constraints Process This automatically runs the Translate step. Double-click Create Timing Constraints.com 115 .1 In-Depth Tutorial www. which is discussed in the following section.

to produce a newer NGD file. pad to 116 www. Global OFFSET OUT.xilinx. a PERIOD. which then outputs the physical design database.1 In-Depth Tutorial . The Map program (the next section in the design flow) then reads the NGD. you can specify the name of the UCF file.com ISE 9. Alternatively. and TIMEGRP OFFSET IN constraint will be written in the UCF and used during implementation. In this design. • Corresponding UCF (User Constraint File) By default. which incorporates the changes made. The Constraints Editor enables you to: • • • Edit constraints previously defined in a UCF file. Global OFFSET IN. Translate is run and ISE launches the Constraints Editor. and enables you to define the associated period. along with design source netlists. In the following section.ucf files are automatically read into the Constraints Editor. Add new constraints to your design. The Global branch of the Timing Constraints tab automatically displays all the clock nets in your design. The Translate step (NGDBuild) uses the UCF file. the stopwatch. when the NGD file is opened.ngd and stopwatch.R Chapter 5: Design Implementation Using the Constraints Editor When you run the Create Timing Constraints process. an NCD (Native Circuit Description) file. Input files to the Constraints Editor are: NGD (Native Generic Database) File The NGD file serves as input to the mapper. an existing UCF file with the same base name as the NGD file is used. The Constraints Editor generates a valid UCF file.

Global Branch Figure 5-6: Constraints Editor .Global Branch In the Constraints Editor. Double-click the Period cell on the row associated with the clock net CLK. This enables you to define an explicit period for the clock.Using the Constraints Editor R setup. 2. Enter a value of 7. verify that Specify Time is selected.1 In-Depth Tutorial www.xilinx. and clock to pad values.0 in the Time field. Note that many of the internal names will vary depending on the design flow and synthesis tool used. 3. Figure 5-5: Constraints Editor in Project Navigator . The Clock Period dialog box opens. For the Clock Signal Definition.com 117 . edit the constraints as follows: 1. ISE 9.

This selects the elements for creating a grouped offset. PERIOD Constraint Values For the Input Jitter section. Hold down the Shift key and select SF_D<7>. 12. Select SF_D<0> in the Port Name Column.1 In-Depth Tutorial . INPUT JITTER Constraint Value The period cell is updated with the global clock period constraint that you just defined (with a default 50% duty cycle). enter a value of 60 in the Time field.xilinx. 8. 11. This creates a Global OFFSET OUT constraint for the CLK signal Figure 5-9: Completed Global constraints in Constraints Editor 10. Click OK. Single click the Pad to Setup cell for clock signal CLK and type 6. 6. Verify that ps is selected from the Units drop-down list. This creates a Global OFFSET IN constraints for the CLK signal. 118 www. Verify that ns is selected from the Units drop-down list.R Chapter 5: Design Implementation 4. Figure 5-8: 7. Single click the Clock to Pad cell for clock signal CLK and type 38. 9. Select the Ports branch from the Timing Constraints tab of the Sources panel. Figure 5-7: 5.com ISE 9. A listing of the current ports is displayed on the left.

Using the Constraints Editor R 13. 15. select the group you just created. type display_grp. Enter 32 for the Timing Requirement. and click Create Group to create the group.1 In-Depth Tutorial www. In the Select Group drop-down list. Click Clock to Pad. 16. Figure 5-11: Setting Constraints for the Grouped OFFSET The Clock to Pad dialog box opens.com 119 . ISE 9. In the Group Name field.xilinx. Figure 5-10: Creating a Grouped OFFSET 14.

Floorplan Editor generates a valid UCF file. Double-click Assign Package Pins Post-Translate. Select CLK in the Relative to Clock Pad Net field. Figure 5-12: 18.ucf file in your current working directory. along with the design source netlists. The NGD file incorporates the changes made in the design and the UCF file from the previous section. to produce a newer NGD file. Select File > Save.R Chapter 5: Design Implementation 17. Clock to Pad Dialog Box The changes are now saved in the stopwatch. 4. and BUFGs. 3. Select the stopwatch module in the Sources window. Click OK 19.1 In-Depth Tutorial . click the + next to Implement Design to expand the process hierarchy in the Processes window. located under the Translate process. Gigabit Transceivers (GTs). Digital Clock Managers (DCMs). 1. Close the Constraints Editor by selecting File > Close. The Translate step uses this UCF file. Floorplan Editor edits the UCF file by adding the newly created placement constraints. This section describes the creation of IOB assignments for several signals. 20. 120 www. Floorplan Editor also places Global Logic at the Slice level with Block Ram.xilinx. Using the Floorplan Editor Use the Floorplan Editor to add and edit the pin locations and area group constraints defined in the NGD file. Click the + next to Translate. 2.com ISE 9.

xilinx. 7. located under the User Constraints process. In the Design Object tab. Figure 5-13: Edit Package Pin Placement This process launches Floorplan Editor. double-click Assign Package Pins.1 In-Depth Tutorial www. 8. This view shows the graphical representation of the device package.com 121 . then scroll down to the nets that begin with “LCD_”. 6. Figure 5-14: 5. enter pin locations using the following values: ♦ ♦ ♦ LCD_E → AB4 LCD_RS → Y14 LCD_RW → W13 ISE 9. This window displays all the objects in the design. change the center filter from ALL to IOs. In the LOC column. Select the Design Object tab in Processes panel. Floorplan Editor Select the Package tab in the work space.Using the Floorplan Editor R Note: For an EDIF project.

From the Design Object tab.1 In-Depth Tutorial .xilinx. click and drag the following signals to the associated location in the Package Pin window: ♦ ♦ ♦ ♦ LAP_LOAD → T16 RESET → U15 MODE → T14 STRTSTOP → T15 122 www.R Chapter 5: Design Implementation Figure 5-15: Pin Locations To place IOs in the Package Pin view using the drag and drop method: 9.com ISE 9.

continue with the implementation of the design.Mapping the Design R Figure 5-16: Drag and Drop IOs in the Package Pins View 10.com 123 . In the Processes tab. Mapping the Design Now that all implementation strategies have been defined (properties and constraints). The changes are saved in the stopwatch.ucf file in your current working directory. right-click on Map and select Run. 2. Note: This can also be accomplished by double-clicking Map. select File > Save. Select the stopwatch module in the Sources window. 1.xilinx. ISE 9.1 In-Depth Tutorial www. Close Floorplan Editor by selecting File > Close. Once the pins are locked down. 11.

Map performs the following functions: • • Allocates CLB and IOB resources for all basic logic elements in the design.com ISE 9.com/support/sw_manuals/xilinx9/. Includes information on how the target device resources are allocated. or from the MAP Reports web at http://www.xilinx. This Guide is available All NGDBUILD and with the collection of software manuals and is accessible from ISE by selecting Help > Software Manuals. 124 www. Translation Report Map Report For detailed information on the Map reports.1 In-Depth Tutorial . performs target device optimizations. Table 5-2: Reports Generated by Map Includes warning and error messages from the translation process. and device utilization. Processes all location and timing constraints.xilinx. and runs a design rule check on the resulting mapped netlist. Expand the Implement Design hierarchy to see the progress through implementation.R Chapter 5: Design Implementation 3. references to trimmed logic. Figure 5-17: Mapping the Design The design is mapped into CLBs and IOBs. refer to the Development System Reference Guide. Each step generates its own report as shown in the following table.

Expand the Translate or Map hierarchy.xilinx. Errors.Mapping the Design R To view a report: 1. Figure 5-19: Implementation Reports shown in Design Summary ISE 9. and Information (INFO). such as Translation Report or Map Report. Translation Report and Map Report Processes Review the report. Double-click a report.1 In-Depth Tutorial www. The Design Summary also contains these reports. Figure 5-18: 3. Look for Warnings. 2.com 125 .

This report is produced after Map and prior to Place and Route (PAR). Timing Analyzer automatically launches and displays the report. the Post-Map Static Timing Report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. If your design is extremely dense. double-click Analyze Post-Map Static Timing Report. the timing report will display the path for each of the timing constraints. Report Paths in Timing Constraints Option Use the Post-Map Static Timing Report to determine timing violations that may occur prior to running PAR. Because the design is not yet placed and routed. This analysis can help to determine if your timing constraints are going to be met. A rough guideline (known as the 50/50 rule) specifies that the block delays in any single path make up approximately 50% of the total path delay after the design is routed.R Chapter 5: Design Implementation Using Timing Analysis to Evaluate Block Delays After Mapping After the design is mapped. 2. Double-click Generate Post-Map Static Timing. In the Processes tab.1 In-Depth Tutorial . For example. 3.com ISE 9. evaluate the design after the map stage. click the + next to Map to expand the process hierarchy. evaluate the Logic Level details in the Post-Map Static Timing Report to evaluate the logical paths in the design.xilinx. To view the Post-Map Static Timing Report and review the PERIOD Constraints that were entered earlier: 1. a path with 10 ns of block delay should meet a 20 ns timing constraint after it is placed and routed. The net delays provided are based on an optimal distance between blocks (also referred to as unplaced floors). The timing report describes the logical block delays and estimated routing delays. Figure 5-20: Post-Map Static Timing Report Process 126 www. actual routing delay information is not available. Estimating Timing Goals with the 50/50 Rule For a preliminary indication of how realistic your timing goals are. To open the Post-Map Static Timing Report. Evaluation verifies that block delays are reasonable given the design specifications. Since you defined timing constraints for the stopwatch design.

The unplaced floors listed are estimates (indicated by the letter “e” next to the net delay) based on optimal placement of blocks. By default. the design can be placed and routed. Notice that the report displays the percentage of logic versus the percentage of routing at the end of each path (e. ISE 9. close the Timing Analyzer by selecting File > Close. After viewing the report.0% route). Figure 5-21: Selecting Post-Map Static Timing constraint The work space shows the report for the selected constraint. Since you defined timing constraints earlier in this chapter.com 127 . In this example. and timing specifications for the design. PAR stops and generates an error message. • Non-Timing Driven PAR PAR is run.g. 5. 88. ignoring all timing constraints. you will find the selected period constraint and the minimum period obtained by the tools after mapping. Placing and Routing the Design After the mapped design is evaluated. 12.0% logic. double-click Place & Route. the Place & Route (PAR) process performs timing driven placement and routing. Note: Even if you do not generate a timing report. To run PAR. One of two place-and-route algorithms is performed during the Place & Route (PAR) process: • Timing Driven PAR PAR is run with the timing constraints specified in the input netlist and/or in the constraints file. if a PERIOD constraint of 8 ns is specified for a path. floors. Select the TS_dcm_inst_CLKX_BUF timing constraint under the Timing tab.1 In-Depth Tutorial www. PAR fails because it determines that the total delay (10 ns) is greater than the constraint placed on the design (8 ns). The Post-Map Static Timing Report will list any pre-PAR timing violations. in the Processes tab. PAR still processes a design based on the relationship between the block delays.xilinx. only three paths per timing constraint will be shown. For example. At the top of this report.Placing and Routing the Design R 4. and there are block delays of 7 ns and unplaced floor net delays of 3 ns. 1. Selecting one of the three paths allows you to see a breakdown of the path which contains the component and routing delays.

xilinx. Double-click Place & Route Report. For detailed information on the PAR reports. Table 5-3: Reports Generated by PAR Report Place & Route Report Description Provides a device utilization and delay summary. refer to the Development System Reference Guide. Pad Report Asynchronous Delay Report All PAR Reports The Design Summary also displays the Place and Route Reports.xilinx. Click the + next to Place & Route to expand the process hierarchy. Lists all nets in the design and the delays of all loads on the net. This Guide is available with the collection of software manuals and is accessible from ISE by selecting Help > Online Documentation.R Chapter 5: Design Implementation To review the reports that are generated after the Place & Route process is completed: 2. Use this report to verify that pins locked down were placed in the correct location. or from the web at http://www. Contains a report of the location of the device pins. Figure 5-22: Design Summary of the Place & Route Report 128 www.com/support/sw_manuals/xi linx9/.1 In-Depth Tutorial .com ISE 9. Note: You can also display and examine the Pad Report and Asynchronous Delay Report. 3. Use this report to verify that the design successfully routed and that all timing constraints were met.

Figure 5-23: View/Edit Routed Design (FPGA Editor) Process ISE 9.com 129 .Using FPGA Editor to Verify the Place and Route R Using FPGA Editor to Verify the Place and Route Use the FPGA Editor to display and configure Field Programmable Gate Arrays (FPGAs).1 In-Depth Tutorial www. Use FPGA Editor to: • • • Place and route critical components before running the automatic place-and-route tools. and double-click View/Edit Routed Design (FPGA Editor). Add probes to your design to examine the signal states of the targeted device. Click the + next to Place & Route to expand the process hierarchy. The FPGA Editor reads and writes Native Circuit Description (NCD) files. • • To view the actual design layout of the FPGA: 1.xilinx. Macro files (NMC) and Physical Constraints Files (PCF). Run the BitGen program and download the resulting bitstream file to the targeted device. Probes are used to route the value of internal nets to an IOB (Input/Output Block) for analysis during debugging of a device. Finish placement and routing if the routing program does not completely route your design. View and change the nets connected to the capture units of an Integrated Logic Analyzer (ILA) core in your design.

change the List Window from All Components to All Nets. To exit FPGA Editor. This enables you to view all of the possible nets in the design.xilinx.1 In-Depth Tutorial .com ISE 9. Figure 5-24: 3. Clock Net 130 www. List Window in FPGA Editor Select the clk_262144K (Clock) net to see the fanout of the clock net. Figure 5-25: 4. In FPGA Editor.R Chapter 5: Design Implementation 2. select File > Exit.

Or you can select the Timing Constraint in the Design Summary and then a timing constraint hyperlink to launch Timing Analyzer. This changes the routing view for the highlighted data path from a simplified view to the actual routing 5. In general. ISE 9. select the first hyperlink beginning with Maximum Data Path. Double-click Analyze Post-Place & Route Static Timing Report to open the report in Timing Analyzer. the worst case path is mainly made up of logic delay.xilinx. Since total routing delay makes up only a small percentage of the total path delay spread out across two or three nets. This report evaluates the logical block delays and the routing delays. 4. The post-layout report indicates that the logical delay value now equals between 30% and 40% of the period. With the TS_DCM_INST_CLKFX_BUF constraint highlighted in the Timing Analyzer tab. Expand the Generate Post-Place & Route Static Timing hierarchy. The total unplaced floors estimate changed as well. ♦ ♦ The post-layout result does not necessarily follow the 50/50 rule previously described because the worst case path primarily includes component delays. To display this report: 1.1 In-Depth Tutorial www. Select the Timing tab in the Sources panel and select the Timing Objects tab in the Processes panel. For some hard to meet timing constraints. a Post Layout Timing Report is generated by default to verify that the design meets your specified timing goals. 3. 2. expecting the timing of these paths to be reduced any further is unrealistic. The Post-Map timing report showed logic delays contributed to 80% to 90% of the minimum period attained. Select View > Overlays > Toggle Simplified and Actual Views.com 131 . you can reduce excessive block delays and improve design performance by decreasing the number of logic levels in the design. The net delays are now reported as actual routing delays after the Place and Route process.Evaluating Post-Layout Timing R Evaluating Post-Layout Timing After the design is placed and routed. This launches the Floorplan Implemented window and highlights the corresponding data path. The following is a summary of the Post-Place & Route Static Timing Report for the stopwatch design: ♦ The minimum period value increased due to the actual routing delays.

Data Path with Simplified Routing Figure 5-27: Floorplan Implemented . and PAR reports will show which partitions are updated and which ones are preserved.xilinx. 132 www. the next step is to update the design with an HDL change. If you are doing the EDIF flow. so only that partition will need to be re-synthesized and re-implemented. 7.R Chapter 5: Design Implementation Figure 5-26: Floorplan Implemented . Select File > Close to exit the Floorplan Implemented view.com ISE 9.Data Path with Actual Routing 6. MAP. Select File > Close again to close the Post-Place & Route Static Timing report. The change will be in the LCD_CNTRL_INST module. Changing HDL with Partition Now that the design has been implemented. The Synthesis. 8. Hold the cursor over different nets or objects in the outlined path to observe timing delay and other information about that portion of the path. you will not be able to do this section. Please proceed to the next section.1 In-Depth Tutorial .

then select Partition Status. ISE 9. In the Sources tab. Make the following change according to your HDL language: ♦ ♦ If you are using Verilog: On line 377 and 564.com 133 . Notice which partitions were preserved and which partitions were re-used.1 In-Depth Tutorial www. Figure 5-28: LCD_CNTRL_INST Partition is Out of Date 6. Select Run from the menu. 5. In the Design Summary view.xilinx. select File > Save. // [colon] to sf_d_temp = 8’b00101110. -. -. Select the MAP Report. Notice which partitions were preserved and which partitions were re-used. right-click on Place & Route. Notice which partitions were preserved and which partitions were re-used.[period] 3. 2. Notice that the implementation is faster with partitions. 4. change the code from sf_d_temp <= “00111010”. Open the LCD_CNTRL_INST module in the text editor by double-clicking it in the Sources tab.[colon] to sf_d_temp <= “00101110”. change the code from sf_d_temp = 8’b00111010. then select Guide Report. since the implementation tools only need to re-implement the LCD_CNTRL_INST module. then select Partitions Report. // [period] If you are using VHDL: On line 326 and 514. To save the changes to LCD_CNTRL_INST.Changing HDL with Partition R 1. Select the Place and Route Report. The rest of the design is re-used. view the following reports: ♦ ♦ ♦ Select the Synthesis Report. select the top-level source file stopwatch and in the Processes tab.

Figure 5-29: 3. In this tutorial. 134 www.xilinx. you need to create configuration data. 4. Select Properties. Change the FGPA Start-Up Clock property from CCLK to JTAG Clock. Process Properties Startup Options Click the Startup Options category.1 In-Depth Tutorial . set the properties and run configuration as follows: 1. To create a bitstream for the target device. A configuration bitstream is created for downloading to a target device or for formatting into a PROM programming file. The Process Properties dialog box opens. you will create configuration data for a Xilinx Serial PROM.R Chapter 5: Design Implementation Creating Configuration Data After analyzing the design through timing constraints in Timing Analyzer. Right-click the Generate Programming File process.com ISE 9. 2.

Verify that the specified options were used when creating the configuration data. To program several devices in a daisy chain configuration. which contains the actual configuration data. double-click Programming File Generation Report.com 135 . 9.bit file). Click OK to apply the new properties. 7. the stopwatch. In the Processes tab. To review the Programming File Generation Report. a wizard enables you to do the following: ISE 9. 10. The BitGen program creates the bitstream file (in this tutorial.Creating a PROM File with iMPACT R Note: You can use CCLK if you are configuring Select Map or Serial Slave. iMPACT accepts any number of bitstreams and creates one or more PROM files containing one or more daisy chain configurations. Figure 5-31: Programming File Generation Report Process Creating a PROM File with iMPACT To program a single device using iMPACT. 8. or to program your devices using a PROM. In iMPACT.1 In-Depth Tutorial www. Figure 5-30: 5. Process Properties Readback Options Click the Readback Options category. Change the Security property to Enable Readback and Reconfiguration. double-click Generate Programming File to create a bitstream of this design. Click the + next to Generate Programming File to expand the process hierarchy. you must use iMPACT to create a PROM file.xilinx. all you need is a bitstream file. 6.

1 In-Depth Tutorial . Click Next. or immediately save the current PROM file configuration. located under the Generated Programming File process hierarchy.R Chapter 5: Design Implementation • • • • Create a PROM file. create a PROM file in iMPACT as follows: 1.xilinx. JTAG File. For this tutorial. Create additional daisy chains. In the Welcome to iMPACT dialog box. In the Processes tab. ACE. 3.com ISE 9. Remove the current bitstream and start over. Figure 5-32: Welcome to iMPACT Dialog Box 136 www. select Prepare a PROM File. double-click Generate PROM. 2. Add additional bitstreams to the daisy chain.

select Auto Select PROM. type stopwatch1. select MCS.xilinx. Figure 5-33: Prepare PROM Files Dialog Box 5. click Finish. Under PROM File Format. 9.bit file. Note: You will receive a warning that the startup clock is being changed from jtag to CCLK.1 In-Depth Tutorial www. 10. Click Next. 7. Specify Xilinx PROM Device Dialog Box In the File Generation Summary dialog box. click OK and then select the stopwatch. Click No when you are asked if you would like to add another design file to the datastream. Figure 5-34: 8. Click Next. For PROM File Name. In the Prepare PROM Files dialog box. In the Specify Xilinx Serial PROM Device dialog box. In the Add Device File dialog box.com 137 .Creating a PROM File with iMPACT R 4. ISE 9. 6. select Xilinx PROM. set the following values: ♦ ♦ ♦ Under “I want to target a:”.

This process opens a file named <source_name>.R Chapter 5: Design Implementation 11. you are ready for programming your device using iMPACT. stopwatch1. 138 www.bit. Select Operations > Generate File. This allows a user to verify the options being used or to create a command batch file to replicate the design flow.cmd_log using either the copy-and-paste method or the drag-anddrop method into a text file. refer to the Development System Reference Guide. Command Line Implementation ISE allows a user to easily view and extract the command line arguments for the various steps of the implementation process. Another useful tool for automating design implementation is XFLOW. see the ISE Help. Sections of the Command Line Log File may also be copied from <source_name>. see the iMPACT Help. For more information on XFLOW. Command line options are organized according to implementation tools. iMPACT displays the PROM associated with your bit file. For more information on this design flow and implementation methodologies. available from the iMPACT application by selecting Help > Help Topics. XFLOW reads a design file as input. select File > Save As and enter the desired file name.xilinx.cmd_log in read-only mode.com/support/sw_manuals/xilinx9/.com ISE 9. This completes the Design Implementation chapter of the tutorial.1 In-Depth Tutorial . refer to the “XFLOW” section in the Development System Reference Guide. With the resulting stopwatch. select File > Close.xilinx. XFLOW is a Xilinx command line tool that automates the Xilinx implementation and simulation flows. Command line options may also be obtained by typing the executable name followed by the -h option at a command prompt. For more information on programming a device. This Guide is available with the collection of software manuals and is accessible from ISE by selecting Help > Software Manuals. available from the ISE application by selecting Help > Help Topics. For a complete listing of command line options for most Xilinx executables. To close iMPACT. flow and option files. To create an editable batch file. At any stage of the design flow you can look at the command line arguments for completed processes by double-clicking View Command Line Log File from the Design Entry Utilities process hierarchy in the Processes tab.mcs and a MSK file generated along with the BIT file. or from the web at http://www. 12.

the design should be analyzed both statically and dynamically. you will perform a timing simulation using either the ModelSim simulator or the Xilinx ISE Simulator. For this reason.1i and ModelSim simulator installed. timing simulation is performed after the design has been placed and routed. “Behavioral Simulation” for information on installing and setting up ModelSim.R Chapter 6 Timing Simulation This chapter includes the following sections. Required Software To simulate with ModelSim. Timing simulation uses the detailed timing and design layout information that is available after place and route. This enables simulation of the design.xilinx.com 139 . Getting Started The following sections outline the requirements to perform this part of the tutorial flow. Timing (post-place and route) simulation is a highly recommended part of the HDL design flow for Xilinx® devices. Simulating with the Xilinx ISE simulator requires that the ISE 9. • • • • “Overview of Timing Simulation Flow” “Getting Started” “Timing Simulation Using ModelSim” “Timing Simulation Using Xilinx ISE Simulator” Overview of Timing Simulation Flow Timing simulation uses the block and routing delay information from a routed design to give a more accurate assessment of the behavior of the circuit under worst-case conditions. you must have Xilinx ISE™ 9. Performing a timing simulation in addition to a static timing analysis will help to uncover issues that cannot be found in a static timing analysis alone.1i software is installed ISE 9. In this chapter.1 In-Depth Tutorial www. To verify the design. Refer to Chapter 4. which closely matches the actual device operation.

3. For more information on compiling and setting up Xilinx simulation libraries. 2. Selecting a different simulator (e. You should use the same test bench that was used to perform the behavioral simulation.com ISE 9. initialize simulation. This Guide is accessible from within ISE by selecting Help > Software Manuals.” and thus. and control simulation properties for ModelSim. • Test Bench File (VHDL or Verilog) In order to simulate the design. The NetGen tool will be used in this chapter to create a simulation netlist from the placed and routed design which will be used to represent the design during the Timing Simulation. right-click the device line (xc3s700A-4fg484) and select Properties. have a placed and routed design. If you completed Chapter 4. compile source files. NC-Sim or VCS) will set the correct options for Netgen to create a simulation netlist for that simulator but Project Navigator will not directly open the simulator. a test bench is needed to provide stimulus to the design. In the Project Properties dialog box click the down arrow in the Simulator value field to display a list of simulators.R Chapter 6: Timing Simulation Required Files The timing simulation flow requires the following files: • Design Files (VHDL or Verilog) This chapter assumes that you have completed Chapter 5.1 In-Depth Tutorial . Please refer to the “Adding an HDL Test Bench” in Chapter 4 if you do not already have a test bench in your project. complete the following: 1. Select ISE Simulator (VHDL/Verilog) or Modelsim with the appropriate version and language in the Simulator value field. Note: ModelSim simulators and the ISE Simulator are the only simulators that are integrated with Project Navigator. “Design Implementation. 140 www. For additional information about simulation. Specifying a Simulator To select either the desired simulator to simulate the stopwatch design. Timing Simulation Using ModelSim Xilinx ISE provides an integrated flow with the Mentor ModelSim simulator.xilinx. In the Sources tab. • Xilinx Simulation Libraries For timing simulation. see Chapter 5 of the Synthesis and Verification Guide. The timing simulation netlist created by Xilinx is composed entirely of instantiated primitives. the SIMPRIM library is needed to simulate the design.xilinx. “Behavioral Simulation”. which are modeled in the SIMPRIM library. see to “Xilinx Simulation Libraries” in Chapter 4. the SIMPRIM library should already be compiled. To perform timing simulation of Xilinx designs in any HDL simulator. Note: To simulate with the ISE Simulator. ISE enables you to create work directories. the SIMPRIM library must be set up correctly.com/support/sw_manuals/xilinx9/. and for a list of other supported simulators. and from the web at http://www. the end result is the same. skip to “Timing Simulation Using Xilinx ISE Simulator”. Whether you choose to use the ModelSim simulator or the ISE Simulator for this tutorial.g.

exe. 4. For example. To set the ModelSim location. 5. c:\modeltech_xe\win32xoem\modelsim. Select the Simulation Model Properties category. or Project Navigator cannot find modelsim.1 In-Depth Tutorial www. Select the test bench file (stopwatch_tb). Note: If the ModelSim Simulator processes do not appear. select Edit > Preferences. In the Processes tab. This global setting enables you to see all available properties. and click Integrated Tools in the left pane. 2.com 141 . browse to the location of modelsim. The properties should appear as shown in Figure 6-1. In the Sources tab. 3. it means that either ModelSim is not selected as the Simulator in the Project Properties dialog box. 6. The Process Properties dialog box displays. Ensure that you have set the Property display level to Advanced. click the + next to ISE General to expand the ISE preferences. click the Help button. For a description of each property.xilinx. under Model Tech Simulator.exe.exe file. If ModelSim is installed but the processes are not available. 7. click the + next to ModelSim Simulator to expand the process hierarchy. ISE 9. These properties set the options that NetGen uses when generating the simulation netlist. In the right pane. Right-click Simulate Post-Place & Route Model.Timing Simulation Using ModelSim R Specifying Simulation Process Properties To set the simulation process properties: 1. select Post-Route Simulation in the Sources for field. Select Properties. the Project Navigator preferences may not be set correctly.

For more details on ModelSim Simulator windows. Simulation Model Properties Select the Display Properties category. By default. the default Simulation Model Properties are used. They are the Signal window. three windows open when timing simulation is launched from ISE. click the Help button. Select the Simulation Properties category.R Chapter 6: Timing Simulation For this tutorial. These properties set the options that ModelSim uses to run the timing simulation. the Structure window. and the Wave window. Figure 6-1: 8. 9.xilinx. 142 www. refer to the ModelSim User Guide.com ISE 9. This tab gives you control over the ModelSim simulation windows.1 In-Depth Tutorial . For a description of each property. The properties should appear as shown in Figure 6-2.

For the purpose of this tutorial. In the Simulation Properties tab. ISE will run NetGen to create the timing simulation model. Highlight signals in the Signal/Object window and then select Add > Wave > Selected Signals. There are two basic methods for adding signals to the Simulator Wave window. Note: The majority of this design runs at 100 Hz and would take a significant amount of time to simulate. only the DCM signals will be monitored to verify that they work correctly. Adding Signals To view signals during the simulation.Timing Simulation Using ModelSim R 10. you must add them to the Wave window. set the Simulation Run Time property to 2000 ns. ISE 9. This is why the counter will seem like it is not working in a short simulation. Figure 6-2: Simulation Properties 11. Performing Simulation To start the timing simulation.com 143 . and run the simulation for the time specified. Additional signals are displayed in the Signal window based on the selected structure in the Structure window. ISE will then call ModelSim and create the working directory.xilinx. load the design. • • Drag and drop from the Signal/Object window. double-click Simulate Post-Place and Route Model in the Processes tab. compile the source files. Click OK to close the Process Properties dialog box.1 In-Depth Tutorial www. ISE automatically adds all the top-level ports to the Wave window.

com ISE 9. select X_DCM and click on the signals/objects window. 6. Type in X_DCM in the search box and select Entity/Module in the Field section. The graphics and the layout of the Structure/Instance window for a Verilog or VHDL flow may appear different. all the windows are docked by default. Figure 6-4: 2. Note: If you are using ModelSim version 6. 4. click the + next to uut to expand the hierarchy. you will be adding the DCM signals to the waveform. Undock icon In the Structure/Instance window.R Chapter 6: Timing Simulation The following procedure explains how to add additional signals in the design hierarchy. Select the Signal/Object window and select Edit > Find. Once ModelSim locates X_DCM. 5. Click and drag CLKIN from the Signal/Object window to the Wave window.Schematic Flow Click the Structure/Instance window and select Edit > Find. All windows can be undocked by clicking the Undock icon. 144 www.xilinx. Type CLKIN in the search box and select the Exact checkbox. In this tutorial. 3. Figure 6-3: 1. Structure/Instance Window . 7. Figure 6-4 shows the Structure/Instance window for the Schematic flow.1 In-Depth Tutorial . All the signal names for the DCM will be listed.0 or higher.

Right-click the Wave window and click Insert > Divider. undock the window and then maximize the window for a larger view of the waveform. To add a divider called DCM Signals: 1. In place of using the drag and drop method select Add to Wave > Selected Signals. Click and drag the following signals from the Signal/Object window to the Wave window: ♦ ♦ ♦ ♦ RST CLKFX CLK0 LOCKED Note: Multiple signals can be selected by holding down the Ctrl key. 4. 2. The hierarchy in the signal name can also be turned off by selecting Tools > Options > Wave Preferences.Timing Simulation Using ModelSim R 8. Adding Dividers Modelsim has the capability to add dividers in the Wave window to make it easier to differentiate the signals. In the Display Signal Path box.com 145 .xilinx. Note: Stretch the first column in the waveform to see the signals clearly. Figure 6-5: The Resulting Waveform ISE 9. Click anywhere in the Wave window. enter 2 and click OK.1 In-Depth Tutorial www. If necessary. 3. 5. The waveform should look as shown in Figure 6-5. Click and drag the newly created divider to above the CLKIN signal. Enter DCM Signals in the Divider Name box.

3. Restart Simulation Icon Figure 6-7: 2. Click Restart. The CLK0 needs to be 50 Mhz and the CLKFX should be ~26 Mhz. The DCM signals should only be analyzed after the LOCKED signal has gone high. Figure 6-6: The Restart dialog box opens. enter run 2000 ns and hit the Enter key.1 In-Depth Tutorial . ModelSim will only record data for the signals that have been added to the Wave window while the simulation is running. To measure the CLK0: 146 www.com ISE 9.R Chapter 6: Timing Simulation Notice that the waveforms have not been drawn for the newly added signals. you need to rerun the simulation for the desired amount of time. Analyzing the Signals Now the DCM signals can be analyzed to verify that it works as expected. Figure 6-8: Entering the Run Command The simulation will run for 2000 ns.xilinx. Therefore. The waveforms for the DCM should now be visible in the Wave window. Click the Restart Simulation icon. By default. Until the LOCKED signal is high the DCM outputs are not valid. Modelsim has the capability to add cursors to carefully measure the distance between signals. Rerunning Simulation To restart and re-run the simulation: 1. after new signals are added to the Wave window. Restart Dialog Box At the ModelSim command prompt. This is because ModelSim did not record the data for these signals.

Save the signals list after new signals or stimuli are added. rename the filename from the default wave. The measurement should read 20000 ps. In the Save Format dialog box.com 147 . which is the input frequency from the test bench. 4. Click the Find Next Transition icon twice to move the cursor to the next rising edge on the CLK0 signal. Saving the Simulation The ModelSim Simulator provides the capability of saving the signals list in the Wave window.Timing Simulation Using ModelSim R 1.do. Your timing simulation is complete and you are ready to program your device by following Chapter 7. and after simulation is rerun. Save Format Dialog Box After restarting the simulation. The saved signals list can easily be loaded each time the simulation is started. In the Wave window. 2. 3. Figure 6-10: 3. Measure CLKFX using the same steps as above. The measurement should read 38462 ps. which in turn should be the DCM CLK0 output. Figure 6-9: Find Next Transition Icon Look at the bottom of the waveform to view the distance between the two cursors. This equals approximately 26 Mhz.xilinx. 1.1 In-Depth Tutorial www. Click Save. Click and drag the first cursor to the rising edge transition on the CLK0 signal after the LOCKED signal has gone high. Click and drag the second cursor to a position just right of the first cursor on the CLK0 signal. Select Add > Cursor twice to place two cursors on the wave view. 2. “iMPACT Tutorial. This converts to 50 Mhz. select File > Save Format. you can select File > Load in the Wave window to reload this file.” ISE 9.do to dcm_signal_tim.

1 In-Depth Tutorial . Select the ISE Simulator Properties category. 4. This global setting enables you to now see all available properties. click the + next to Xilinx ISE Simulator to expand the process hierarchy. For a description of each property. select Post-Route Simulation in the Sources for field. Select the test bench file (stopwatch_tb). 7. In the Sources tab. set the Simulation Run Time property to 2000 ns. The properties should appear as shown in Figure 6-11. Select the Simulation Model Properties category.com ISE 9. In the Simulation Properties tab. These properties set the options that NetGen uses when generating the simulation netlist. 2.xilinx. In the Processes tab. 6.R Chapter 6: Timing Simulation Timing Simulation Using Xilinx ISE Simulator Follow this section of the tutorial if you have skipped the previous section. For a description of each property. Click OK to close the Process Properties dialog box. the default Simulation Model Properties are used. “Timing Simulation Using ModelSim. These properties set the options the simulator uses to run the timing simulation. 8. 148 www. Ensure that you have set the Property display level to Advanced.” Specifying Simulation Process Properties To set the simulation process properties: 1. click the Help button. click the Help button. Right-click Simulate Post-Place & Route Model. For this tutorial. Select Properties. 3. The Process Properties dialog box displays. 5. Figure 6-11: Simulation Properties 10. 9.

This is why the counter will seem like it is not working in a short simulation. Right click in the Sim Hierarchy window and select Find. click the + next to uut to expand the hierarchy. 1. only the DCM signals will be monitored to verify that they work correctly. For the purpose of this tutorial. 3.Timing Simulation Using Xilinx ISE Simulator R Performing Simulation To start the timing simulation. Note: The majority of this design runs at 100 Hz and would take a significant amount of time to simulate. 4. you will be adding the DCM signals to the waveform.1 In-Depth Tutorial www. and run the simulation for the time specified. Type the locked in the Find Signal dialog box and click on OK. When a simulation process is run.com 149 . All available external (top-level ports) and internal signals are displayed in the Sim Hierarchy window. The following procedure explains how to add additional signals in the design hierarchy. you must add them to the waveform window. Sim Hierarchy Window .xilinx. Figure 6-12: 5. double-click Simulate Post-Place and Route Model in the Processes tab. Project Navigator automatically runs NetGen to generate a timing simulation model from the placed and routed design. Adding Signals To view signals during the simulation. 2. Select DCM_SP_INST/LOCKED signal and click on OK. ISE automatically adds all the top-level ports to the waveform window. ISE 9. load the design. In this tutorial. The signal names and layout in the Sim Hierarchy window for a schematic or VHDL flow may appear different. In the Sim Hierarchy window. Figure 6-12 shows the Sim Hierarchy window for the VHDL flow. The ISE Simulator will then compile the source files.VHDL Flow Click and drag LOCKED from the Sim Hierarchy window to the waveform window.

To change the signal name display. The ISE Simulator will only record data for the signals that have been added to the waveform window while the simulation is running. Rerunning Simulation To restart and re-run the simulation: 150 www.xilinx. Note: Stretch the first column in the waveform to see the signals clearly. you need to rerun the simulation for the desired amount of time. 2.com ISE 9.R Chapter 6: Timing Simulation 6. Select Long Name or Short Name as desired. This is because the ISE Simulator did not record the data for these signals. The waveform should appear as shown in Figure 6-13.1 In-Depth Tutorial . Therefore. 1. after new signals are added to the waveform window. Click and drag the following X_DCM_SP signals from the SIM Hierarchy window to the waveform window: ♦ ♦ ♦ ♦ RST CLKFX CLK0 CLKIN Note: Multiple signals can be selected by holding down the Ctrl key. Viewing Full Signal Names A signal name may be viewed with either the complete hierarchical name or by the short name which omits hierarchy information. Right click the desired signal in the waveform window. Figure 6-13: The Resulting Waveform Notice that the waveforms have not been drawn for the newly added signals.

To measure the CLK0: 1. enter run 2000 ns and hit the Enter key. The cursor changes to an uparrow pointer. Click the Restart Simulation icon.com 151 . The waveforms for the DCM should now be visible in the Simulation window. ISE 9. Right click the wave window and select Add Measure.xilinx. Figure 6-16: Adding Timing Markers Note: You may need to Zoom In to place the markers precisely on the clock edge.Timing Simulation Using Xilinx ISE Simulator R 1. Until the LOCKED signal is high the DCM outputs are not valid. Click a rising edge transition on the CLK0 signal after the LOCKED signal has gone high. 2. Figure 6-14: 2.1 In-Depth Tutorial www. ISE Simulator has the capability to add cursors to carefully measure the distance between signals. Analyzing the Signals Now the DCM signals can be analyzed to verify that it does work as expected. Restart Simulation Icon At the Sim Console command prompt. The DCM signals should only be analyzed after the LOCKED signal has gone high. Click and drag the second marker to the next rising edge on the CLK0 signal. The CLK0 needs to be 50 Mhz and the CLKFX should be ~26 Mhz. Figure 6-15: Entering the Run Command The simulation will run for 2000 ns. 3. Two vertical markers are placed one the waveform.

R Chapter 6: Timing Simulation View the time value between the two markers to see the distance between the two clock edges. This converts to 50 Mhz. The measurement should read 38.com ISE 9. Your timing simulation is complete and you are ready to program your device by following Chapter 7. which in turn should be the DCM CLK0 output.0 ns.1 In-Depth Tutorial . this equals approximately 26 Mhz.” 152 www. Measure CLKFX using the same steps as above. which is the input frequency from the test bench.5 ns. The measurement should read 20.xilinx. “iMPACT Tutorial.

R Chapter 7 iMPACT Tutorial This chapter takes you on a tour of iMPACT. a file generation and device programming tool.1 In-Depth Tutorial www. PROM files. and SVF/XSVF files.com 153 . iMPACT enables you to program through several parallel cables.xilinx. This tutorial contains the following sections: • • • • • • • • • “Device Support” “Download Cable Support” “Configuration Mode Support” “Getting Started” “Creating a iMPACT New Project File” “Using Boundary Scan Configuration Mode” “Troubleshooting Boundary Scan Configuration” “Creating an SVF File” “Other Configuration Modes” Device Support The following devices are supported. including the Platform Cable USB. System ACE files. • • • • • • • • Virtex™/-E/-II/-II PRO/4/5 Spartan™/-II/-IIE/XL/3/3E/3A XC4000™/E/L/EX/XL/XLA/XV CoolRunner™XPLA3/-II XC9500™/XL/XV XC18V00P XCF00S XCF00P ISE 9. The SVF/XSVF files can be played backed without having to recreate the chain. iMPACT can create bit files.

the bit should be verified against the bit stream data.com ISE 9. For more information.com/support. select Documentation > Data Sheets > Configuration Solutions > Configuration Hardware > Platform Cable USB.R Chapter 7: iMPACT Tutorial Download Cable Support Parallel Cable IV The Parallel Cable connects to the parallel port and can be used to facilitate Slave Serial and Boundary-Scan functionality. select Documentation > Data Sheets > Configuration Solutions > Configuration Hardware > Xilinx Parallel Cable IV. Configuration Mode Support Impact currently supports the following configuration modes: • • • • Boundary Scan —FPGAs. This file generated along with the BIT file.xilinx.xilinx.XCFP) Slave Serial—FPGAs (Virtex™/-II/-II PRO/E/4/5 and Spartan™/-II/-IIE/3/3E/3A) SelectMAP—FPGAs (Virtex™/-II/-II PRO/E/4/5 and Spartan™/-II/-IIE/3/3E/3A) Desktop —FPGAs (Virtex™/-II/-II PRO/E/4/5 and Spartan™/-II/-IIE/3/3E/3A) Getting Started Generating the Configuration Files In order to follow this chapter. select Documentation > Data Sheets > Configuration Solutions > Configuration Hardware > MultiPRO Desktop Tool. and Boundary Scan functionality. go to http://www.xilinx. For more information. This data is not used to configure the device.com/support. For more information. 154 www. a MSK file—a binary file that contains the same configuration commands as a BIT file.com/support. If a mask bit is 0. go to http://www. Platform Cable USB The Platform Cable connects to the USB port and can be used to facilitate Slave Serial.1 In-Depth Tutorial . CPLDs. and PROMs(18V00. go to http://www. MultiPRO Cable The MultiPRO cable connects to the parallel port and can be used to facilitate Desktop Configuration Mode functionality. the bit should not be verified. you must have the following files for the stopwatch design: • • • a BIT file—a binary file that contains proprietary header information as well as configuration data.XCFS. If a mask bit is 1. a MCS file—an ASCII file that contains PROM configuration information.xilinx. but that has mask data in place of configuration data. but is used for verification.

and connect the cable to the Spartan-3 Starter Kit demo board.com 155 . “Design Implementation.com/support/techsup/tutorials/tutorials9. Starting the Software This section describes how to start the iMPACT software from ISE™ and how to run it stand-alone. connect the parallel side of the cable to your computer’s parallel port. • • PC — Click Start > All Programs > Xilinx® ISE 9. PC.xilinx. UNIX. Download the project files for either the VHDL.Getting Started R These files are generated in Chapter 5.htm. Opening iMPACT from Project Navigator To start iMPACT from Project Navigator. Be sure that the board is powered.1i > Accessories > iMPACT.xilinx. use one of the following methods. ISE 9.1 In-Depth Tutorial www. double-click Configure Device (iMPACT) in the Processes tab in the Processes window (see Figure 7-1).” • The Stopwatch tutorial projects can be downloaded from http://www. or Linux — Type impact at a command prompt. Figure 7-1: Opening iMPACT from ISE Opening iMPACT stand-alone To open iMPACT without going through an ISE project. Connecting the Cable Prior to launching iMPACT. Verilog or Schematic design flow.

and is discussed in a later section in this chapter. Boundary Scan Configuration Mode enables you to perform Boundary Scan Operations on any chain comprising JTAG compliant devices. TMS. This option enables you to generate an SVF/XSVF programming file. The chain can consist of both Xilinx® and non-Xilinx devices. which enables you to then manually add devices to create chain. Click Save.xilinx. Note: The selection box also gives you the option to Enter a Boundary Scan Chain. 156 www. however. To select Boundary Scan Mode: 1. This creates a new project file in iMPACT. the cable must be connected and the JTAG pins. 3. limited operations will be available for non-Xilinx devices. and TDO need to be connected from the cable to the board. Click the Browse button. Click OK. 4. select create a new project (. Select Configure Devices using Boundary-Scan (JTAG) and leave the selection box value of Automatically connect to a cable and identify Boundary-Scan chain. Specifying Boundary Scan Configuration Mode After opening iMPACT. you will be using the Boundary Scan Configuration Mode. TCK.R Chapter 7: iMPACT Tutorial Creating a iMPACT New Project File When iMPACT is initially opened.ipf). 5. You are prompted to define the project. you are prompted to specify the configuration mode and which device you would like to program.1 In-Depth Tutorial . as described in the next section. TDI.com ISE 9. Browse to the project directory and then enter stopwatch in the File Name field. In the iMPACT Project dialog box. This dialog box enables you to load a recent project or to create a new project. To perform operations. Automatically detecting and initializing the chain should be performed whenever possible. Using Boundary Scan Configuration Mode For this tutorial. Figure 7-2: Creating an iMPACT Project To create a new project for this tutorial: 1. 2. the iMPACT Project dialog box displays.

Figure 7-3: Selecting automatic boundary scan from Wizard iMPACT will pass data through the devices and automatically identify the size and composition of the boundary scan chain. Click Finish. ISE 9.1 In-Depth Tutorial www. Note: If you were not prompted to select a configuration mode or automatic boundary scan mode.xilinx.Using Boundary Scan Configuration Mode R 2. Any supported Xilinx device will be recognized and labeled in iMPACT. Go to “Troubleshooting Boundary Scan Configuration” if you are having problems.com 157 . Any other device will be labeled as unknown. The software will then highlight each device in the chain and prompt you to assign a configuration file or BSDL file. right-click in the iMPACT window and select Initialize Chain. The software will identify the chain if the connections to the board are working.

or . When the software prompts you to select a configuration file for the first device (XC3S200): 1.isc) is used to configure a CPLD. *. • • • A Bitstream file (*. Click OK. select Bypass in the Assign New Configuration File dialog box.xilinx.jed. There are several types of configuration files.1 In-Depth Tutorial . A JEDEC file (*. *. The configuration file is used to program the device.*.isc) is used to configure an FPGA.mcs.R Chapter 7: iMPACT Tutorial Assigning Configuration Files After initializing a chain. 2. To have ISE automatically select a BSDL file (for both Xilinx and non-Xilinx devices).rbt.com ISE 9. a Boundary Scan Description File (BSDL or BSD) file can be applied instead. .tek) is used to configure a PROM. . Figure 7-4: Selecting a Configuration File Note: If a configuration file is not available.hex. 3.bit.exo. 158 www. You should receive a warning stating that the startup clock has been changed to JtagClk. the software prompts you for a configuration file (see Figure 7-4). Select the BIT file from your project working directory. Click Open. The BSDL file provides the software with the necessary Boundary Scan information that allows a subset of the Boundary Scan Operations to be available for that device. A PROM file (*.

Using Boundary Scan Configuration Mode R 4. In this tutorial. Editing Preferences To edit the preferences for the Boundary Scan Configuration. This selection opens the window shown in Figure 7-5. (For more information about Preferences. Click Open. keep the default values and click OK. This brings up a window with all of the available options. 6. select File > Open Project and browse to the IPF. The available Boundary Scan operations vary based on the device and the configuration file that was applied to the device. select Edit > Preferences. see “Editing Preferences. all other devices in the chain are automatically placed in BYPASS or HIGHZ. Saving the Project File Once the chain has been fully described and configuration files are assigned. To do this.1 In-Depth Tutorial www. These files can still be opened and used in iMPACT. you should save your iMPACT Project File (IPF) for later use.”) ISE 9. To restore the chain after reopening iMPACT. When the software prompts you to select a configuration file for the second device (XCF02S): Select the MCS file from your project working directory. Note: Previous versions of ISE use Configuration Data Files (CDF). iMPACT Project Files can also be exported to a CDF. depending on your iMPACT Preferences setting. Figure 7-5: Edit Preferences Performing Boundary Scan Operations You can perform Boundary Scan operations on one device at a time. The Save As dialog box appears and you can browse and save your project file accordingly.com 159 . 5.xilinx. select File > Save Project As. To see a list of the available options. When you select a device and perform an operation on that device. Click Help for a description of the Preferences. right-click on any device in the chain.

you will retrieve the device ID and run the programming option to verify the first device. The result is displayed in the log window (see Figure 7-7). Figure 7-6: Available Boundary Scan Operations for an XC3S200 Device The software accesses the IDCODE for this Spartan-3 device. Figure 7-7: 3.xilinx. 2. 4. 1. 160 www.R Chapter 7: iMPACT Tutorial To perform an operation. Log Window Showing Result of Get Device ID Right-click on the XC3S200 device Select Program from the right-click menu. right-click on a device and select one of the options.com ISE 9. Right-click on the XC3S200 device. Select Get Device ID from the right-click menu. The Program Options Dialog Box appears (see Figure 7-8). In this section.1 In-Depth Tutorial .

Using Boundary Scan Configuration Mode

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5.

Select the Verify option. The Verify option enables the device to be readback and compared to the BIT file using the MSK file that was created earlier.

6.

Click OK to begin programming.

Figure 7-8:

Program Options for XC3S200 Device

Note: The options available in the Program Options dialog box vary based on the device you have selected. After clicking OK, the Program operation begins and an operation status window displays. At the same time, the log window reports all of the operations being performed.

Figure 7-9:

Operation Status

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When the Program operation completes, a large blue message appears showing that programming was successful (see Figure 7-10). This message disappears after a couple of seconds.

Figure 7-10:

Programming Operation Complete

Your design has been programmed and has been verified. The board should now be working and should allow you to start, stop and reset the runner’s stopwatch.

Troubleshooting Boundary Scan Configuration
Verifying Cable Connection
When an error occurs during a Boundary Scan operation, first verify that the cable connection is established and that the software autodetect function is working. If a connection is still not established after plugging the cable into the board and into your machine, right-click in a blank portion of the iMPACT window and select either Cable Auto Connect or Cable Setup. Cable Auto Connect will force the software to search every port for a connection. Cable Setup enables you to select the cable and the port to which the cable is connected.

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Troubleshooting Boundary Scan Configuration

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When a connection is found, the bottom of the iMPACT window will display the type of cable connected, the port attached to the cable, and the cable speed (see Figure 7-11).

Figure 7-11:

Cable Connection Successful

If a cable is connected to the system and the cable autodetection fails, refer to Xilinx Answer Record #15742. Go to http://www.xilinx.com/support and search for “15742”.

Verifying Chain Setup
When an error occurs during a Boundary Scan operation, verify that the chain is set up correctly and verify that the software can communicate with the devices. The easiest way to do this is to initialize the chain. To do so, right-click in the iMPACT window and select Initialize Chain. The software will identify the chain if the connections to the board are working. If the chain cannot be initialized, it is likely that the hardware is not set up correctly or the cable is not properly connected. If the chain can be initialized, try performing simple operations. For instance, try getting the Device ID of every device in the chain. If this can be done, then the hardware is set up correctly and the cable is properly connected. The debug chain can also be used to manually enter JTAG commands (see Figure 7-12). This can be used for testing commands and verifying that the chain is set up correctly. To use this feature, select Debug > Start/Stop Debug Chain in iMPACT.

Figure 7-12:

Debug Chain

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Setting up Boundary Scan Chain This section assumes that you are continuing from the previous sections of this chapter and already have the chain detected.xilinx. all of the configuration information is written to the SVF file. Click OK. even if you intend to program only some of the devices. SVF. iMPACT supports the creation of device programming files in three formats. Select Output > SVF File > Create SVF File to indicate that you are creating a programming file.xilinx. Manual JTAG chain setup for SVF generation For this tutorial.com ISE 9. Right-click on an empty space in the iMPACT Boundary-Scan window and select Add Xilinx Device or Add Non-Xilinx device. All devices must be represented in the iMPACT window. Select stopwatch.mcs file to the chain. The device is added where the large cursor is positioned. Note: The boundary scan chain that you manually create in the software must match the chain on the board. you may skip this section if you completed the “Using Boundary Scan Configuration Mode. Enter getid in the File Name field of the Create a New SVF File dialog box and click Save. click on the line between them and then add the new device. and they are used by ATE machines and embedded controllers to perform Boundary Scan operations. 3. or file a Web case at http://www. Repeat steps 2 and 3 to add the stopwatch. To do this. XSVF. These programming files contain both programming instructions and configuration data. You can now add one device at a time. In this section. and STAPL.com/support. The Boundary-Scan chain can be manually created or modified as well. A cable normally does not need to be connected because no operations are being performed on devices. An informational message appears stating that all device operations will be directed to the .1 In-Depth Tutorial . 2. use the iMPACT Help (accessible from Help > Help Topics). Creating an SVF File This section is optional and assumes that you have followed the “Using Boundary Scan Configuration Mode” section and have successfully programmed to a board. you may need to set up your Boundary Scan chain manually and then create a device programming file. skip to “Manual JTAG chain setup for SVF generation” to define the chain manually. 1. 164 www. 3.bit and then click Open. To add a device between existing devices.” section. 2. An Add Device dialog box appears allowing you to select a configuration file.R Chapter 7: iMPACT Tutorial For help using iMPACT Boundary-Scan Debug. JTAG chain setup for SVF generation 1. Ensure that you are in Boundary Scan Mode (click the Boundary-Scan tab). If not. If you are using third-party programming solutions.svf file.

Figure 7-14: SVF File that Gets a Device ID from the First Device in the Chain ISE 9. 2. select View > View SVF-STAPL File.1 In-Depth Tutorial www. You simply right-click on a device and select an operation. Figure 7-13: Selecting a Boundary Scan Operation The instructions that are necessary to perform a Get Device ID operation are then written to the file.com 165 . and performing further instructions for the second device. To see the results. 3. Right-click the first device (XC3S200).Creating an SVF File R Writing to the SVF File The process of writing to an SVF file is identical to performing Boundary Scan operations with a cable. Figure 7-14 shows what the SVF file looks like after the Get Device ID operation is performed. In this section. Select Get Device ID from the right-click menu. you will be writing the device ID to the programming file for the first device.xilinx. To write the device ID: 1. Any number of operations can be written to an SVF file.

To stop writing to the programming file: Select Output > SVF File > Stop Writing to SVF File.. you can select Output > SVF File > Append to SVF File.com ISE 9. 166 www. Available Boundary Scan Operations for a XCF02S Device Click OK in the Programming Properties window. Playing back the SVF or XSVF file To play back the SVF file that you created to verify the instructions. To use the Slave Serial Configuration Mode. The instructions and configuration data needed to program the second device are added to the SVF file.xilinx. Right-click on the SVF file in the Boundary-Scan chain and select Execute XSVF/SVF. Stop Writing to the SVF After all the desired operations have been performed. To add other operations in the future. 2. Assign the SVF file to the chain by right clicking and selecting Add Xilinx Device and selecting the SVF file in the search window. double-click Slave Serial in the Configuration Modes tab.1 In-Depth Tutorial . Right-click the second device (XCF02S). Figure 7-15: 3. you must add an instruction to close the file from further instructions. you will • • • Manually create a new chain. select the SVF file and click Save.R Chapter 7: iMPACT Tutorial To write further instructions to the SVF for the second device: 1. Select Program from the right-click menu. Other Configuration Modes Slave Serial Configuration Mode Slave Serial Configuration mode allows you to program a single Xilinx device or a serial chain of Xilinx devices.

The devices are programmed one at a time and are selected by the assertion of the correct CS pin. double click SelectMAP in the Configuration Modes tab.xilinx.Other Configuration Modes R SelectMAP Configuration Mode With iMPACT.1 In-Depth Tutorial www. ISE 9. To use the SelectMAP Configuration Mode.com 167 . Note: These modes cannot be used with the Spartan-3 Starter Kit. Only the MultiPRO cable can be used for SelectMAP Configuration. SelectMAP Configuration mode allows you to program up to three Xilinx devices.

xilinx.com ISE 9.R Chapter 7: iMPACT Tutorial 168 www.1 In-Depth Tutorial .

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