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Spring 2008

Poras T. Balsara Center for Integrated Circuits and Systems Department of Electrical Engineering University of Texas at Dallas

Outline

MOSFET structure Threshold voltage concept I-V characteristics and different regions of operation Secondary effects Short-channel devices SPICE model

© ptb (January 7, 2008)

MOS Transistor

2

1

The MOSFET

N areas have been doped with donor ions (arsenic) with concentration ND - electrons are majority carriers. P areas have been doped with acceptor ions (boron) with concentration NA - holes are majority carriers.

Cross-section of an NMOSFET

© ptb (January 7, 2008)

MOS Transistor

3

N-Channel MOSFET (NMOSFET)

Conducting channel is formed between drain and source when the gate-source voltage, VGS ≥ VTn VTn is the NMOSFET Threshold Voltage

© ptb (January 7, 2008) MOS Transistor 4

2

Depletion Mode Enhancement Mode Devices: In these devices. application of VGS forms a conducting channel between drain and source. Channel does not exist under zero gate bias. 2008) MOS Transistor 5 Enhancement vs.P-Channel MOSFET (PMOSFET) Conducting channel is formed between drain and source when the gate-source voltage. Application of VGS turns these devices off. 2008) MOS Transistor 6 3 . VGS ≤ VTp VTp is the PMOSFET Threshold Voltage © ptb (January 7. channel exists under zero gate bias. Depletion Mode Devices: In these devices. MOSFET Symbols: © ptb (January 7.

2008) MOS Transistor 7 NMOSFET – Threshold Voltage Accumulation Region: VGS < 0 Flat-band Condition: VGS = VFB © ptb (January 7.Cross-section of CMOS Technology © ptb (January 7. 2008) MOS Transistor 8 4 .

MOS Transistor 10 © ptb (January 7. ( −2φ F + VSB − −2φ F ) The body-effect coefficient: it expresses impact of changes in VBS = ( 2qε si N A ) C ox Substrate Bias (bulk source voltage) Note: The threshold voltage has a positive value for a typical NMOSFET.NMOSFET – Threshold Voltage Depletion Region: VGS > VFB Surface Inversion: VGS ≥ VTn © ptb (January 7. 2008) MOS Transistor 9 Threshold Voltage VT = VT 0 + γ Threshold voltage at VBS=0 and is mostly a function of manufacturing process. while it is negative for a normal PMOSFET. 2008) 5 .

(VTn is positive for a normal NMOSFET with body tied to ground).The Body Effect Effect of well bias on an NMOSFET is plotted here. Negative bias on well or substrate causes VTn to increase from 0. 2008) MOS Transistor 11 Body Effect in a Logic Gate n2 strong inversion: VT2 VT1 n1 VSB2=0 V =0 SB1 VG VGS > VT V > V S T body effect: VT2 > VT1 © ptb (January 7.85V © ptb (January 7. 2008) MOS Transistor 12 6 .45V to 0.

NMOSFET V-I : Cut-off Region VGS < V Tn G S n+ pB n+ D VDS VGS < VTn IDS ≈ 0 IDS is due to diode reverse-bias leakage current and/or sub-threshold conduction. 2008) V2 ⎤ W⎡ (VGS − VTn )VDS − DS ⎥ ⎢ L ⎣ 2 ⎦ MOS Transistor 14 7 . © ptb (January 7. 2008) MOS Transistor 13 NMOSFET in Linear (Resistive) Region VGS > V Tn G S n+ pB n+ VDS < V GS I DS D V Tn VGS ≥ VTn and VDS < VGS – VTn ′ I DS = kn © ptb (January 7.

2008) 8 . 2008) MOS Transistor Carrier Mobility µ n ≈ 1350 cm 2 / V sec µ p ≈ 480 cm 2 / V sec 15 NMOSFET V-I: Saturation Region > > VGS > VTn and VDS ≥ VGS – VTn I DS = ′ kn W 2 (VGS − VTn ) 2 L MOS Transistor 16 Why is this equation not entirely correct? © ptb (January 7.97 × ε 0 = 3.5 × 10 −11 F / m © ptb (January 7.NMOSFET V-I: Linear Region V2 ⎤ W⎡ (VGS − VTn )VDS − DS ⎥ ⎢ L ⎣ 2 ⎦ Process Transconductance Parameter MOSFET Gain Factor 2 ′ kn = kn W L ′ kn =µ n C ox = µ n ε ox / tox in A / V ′ I DS = kn ( ) Oxide Perm ittivity: ε ox = 3.

I DS = ′ kn W 2 (VGS − VTn ) (1 + λVDS ) 2 L λ is an empirical constant parameter.tox the dielectric of the gate insulator (SiO2) . IDS is increased when the effective length is decreased.e. Consequently. called the channel-length modulation coefficient (varies roughly with the inverse of the channel length) © ptb (January 7. IDS is a function of the distance between the source and drain .Channel Length Modulation The position of the pinch-off point shifts as VDS is increased.VT the thickness of the oxide . 2008) MOS Transistor 18 9 . the effective channel length (i.W the threshold voltage . 2008) MOS Transistor 17 Current Determinates For a fixed VDS and VGS (≥ VTn). L’ = L – ∆L) is modulated by VDS.L the channel width .εox the carrier mobility: for NMOSFETs: µn ≈ 1350 cm2/V-sec for PMOSFETs: µp ≈ 480 cm2/V-sec © ptb (January 7..

VDD=2. 2008) MOS Transistor 19 I-V Characteristics: Summary Region Cutoff IDS ≈ 0 VGS ≥ VTn VDS < VGS – VTn ′ I DS = kn 2 VDS ⎤ W⎡ ⎢(VGS − VTn ) VDS − ⎥ 2 ⎦ L ⎣ NMOSFET VGS < VTn IDS ≈ 0 PMOSFET VGS > VTp VGS ≤ VTp VDS > VGS – VTp I DS = k ′ p 2 VDS ⎤ W⎡ ⎢(VGS − VTp ) VDS − ⎥ 2 ⎦ L ⎣ Linear Saturation VGS ≥ VTn VDS ≥ VGS – VTn I DS = ′ kn W 2 (VGS − VTn ) (1 + λVDS ) 2 L MOS Transistor VGS ≤ VTp VDS ≤ VGS – VTp k′ W 2 I DS = p (VGS − VTp ) (1 + λVDS ) 2 L 20 © ptb (January 7.5V.5 © ptb (January 7. VTn=0. 2008) 10 .5V Ld=10µm W/L=1.Long Channel NMOS I-V Curves Quadratic dependence NMOSFET: 0.25µm CMOS.

© ptb (January 7. only a couple of volts difference between D and S is needed to reach velocity saturation. ξc NMOS PMOS ξc ξ 1. 2008) MOS Transistor 22 11 .Short Channel Effects The behavior of MOSFET with sub-micron channel length deviates considerably from the first-order long channel models discussed earlier. 2008) MOS Transistor 21 Velocity Saturation Carrier velocity saturates when the electric field along the channel reaches a critical value ξc. Some short channel effects for sub-micron transistors: Velocity saturation and mobility degradation Sub-threshold conduction and gate leakage Threshold voltage variations Parasitic resistance Secondary effects: Temperature effects Hot carrier effects Latchup © ptb (January 7.5x104 V/cm (or 1. This is due to scattering (collisions suffered by the carriers).5 V/µm) ≥ 105 V/cm vsat 107 cm/s 107 cm/s For an NMOSFET with L=1µm.

v = µn ξ and for ξ < ξc Lv sat µn = v sat = µn ξc for ξ ≥ ξc VDSAT = L ξc = IDSAT can be obtained by plugging in the saturation voltage. I DSAT = I DS (VDS = VDSAT ) = µnCox W ⎡ V2 ⎤ (VGS − VTn )VDSAT − DSAT ⎥ L ⎢ 2 ⎦ ⎣ ⎛ ⎞ V = v satCoxW ⎜VGS − VTn − DSAT ⎟ 2 ⎠ ⎝ © ptb (January 7. 2008) MOS Transistor 23 IDSAT Approximation For first-order analysis the current equations for velocity saturated devices can be approximated by assuming. 2008) MOS Transistor 24 12 .V-I Relation: Velocity Saturation NMOS Linear Region: VDS < VGS – VTn ′ I DS = κ (VDS ) kn where. W ⎡ V2 ⎤ VGS − VTn )VDS − DS ⎥ ( L ⎢ 2 ⎦ ⎣ κ (V ) = 1 (1 + (V ξc L ) ) is a measure of the degree of velocity saturation. NMOS Saturation Region: VDS = VDSAT ≥ VGS – VTn ′ I DSAT = κ (VDSAT ) kn 2 W ⎡ VDSAT ⎤ ⎢(VGS − VTn )VDSAT − 2 ⎥ L ⎣ ⎦ VDSAT = κ (VGS − VTn )(VGS − VTn ) © ptb (January 7.

5V.Effects of Velocity Saturation For short-channel devices with large enough (VGS-VT). κ<<1 VDSAT < VGS-VT Device enters saturation before VDS reaches VGS-VT extended saturation device operates more often in saturation. 2008) MOS Transistor 26 13 .5V Ld=0. VTn=0. © ptb (January 7.25µm CMOS. 2008) MOS Transistor 25 Short Channel NMOS I-V Curves Linear dependence NMOSFET: 0.5 © ptb (January 7. IDSAT has a linear dependence with respect to VGS reduction in the amount of current for a given control voltage.25µm W/L=1. VDD=2.

25µm CMOS.5 © ptb (January 7. VDD=2.5V Ld=0.Short Channel PMOS I-V Curves For PMOSFETs polarities of all voltages and currents are reversed NMOSFET: 0. VDSn . VDSATn } ⎛W ⎞⎡ V2 ⎤ ′ I Dn = kn ⎜ n ⎟ ⎢(VGSn − VTn )Vmin − min ⎥ (1+ λ VDSn ) … for VGSn ≥ VTn 2 ⎦ ⎝ Ln ⎠ ⎣ (use max. VGSn > VTp if Vmax = VDSATp ⇒ velocity saturated Vmax = VDSp VDSp ≥ (VGSp − VTp ) ⇒ linear region: VDSn ≥ (VGSn − VTn ) ⇒ saturation region: Vmin = (VGSn − VTn ) VDSp < (VGSp − VTp ) ⇒ saturation region: Vmax = (VGSp − VTp ) © ptb (January 7. VTn=0. 2008) MOS Transistor 27 Unified Model Vmin = min {(VGSn − VTn ) .25µm W/L=1. VDSn < (VGSn − VTn ) ⇒ linear region: if Vmin = VDSATn ⇒ velocity saturated Vmin = VDSn For PMOSFETs ⇒ cutoff region.5V. value for PMOSFETs) For NMOSFETs VGSn < VTn ⇒ cutoff region. 2008) MOS Transistor 28 14 .

Current roll-off is adversely affected by increase in temp.. 2008) −1 ⎞ ⎟ ln (10 ) ⎠ MOS Transistor MOSFET Modeled as a Switch Modeled as a switch with infinite off resistance and a finite on resistance. Ron. 2008) MOS Transistor 32 15 . typically around 1.e. 31 Subthreshold Slope Factor: ⎡ d log ( I DS ) ⎤ ⎛ kT S =⎢ ⎥ = n⎜ dVGS ⎦ ⎝ q ⎣ © ptb (January 7.Subthreshold Conduction For VGS < VTn NMOSFET conducts partially and the current decays exponentially (does not switch abruptly) – subthreshold conduction or weak inversion For ideal device (n = 1). © ptb (January 7. higher S. the subthreshold slope factor. i. use average of resistance at the end-points of the transition. A simple model: use average value of resistance over operation region of interest or even simpler.5 relatively larger voltage is required to drop the current. S at room temperature is 60 mV/decade For actual devices n > 1.

5 35 115 MOS Transistor 19 55 15 38 13 31 33 Threshold Voltage Variation VT is a function of technology and the substrate bias.25µm CMOS. Ron becomes independent of VDD Once VDD approaches VT. with W/L=1 and L=Lmin VDD(V) NMOS (kΩ) PMOS (kΩ) © ptb (January 7.5 2 2. © ptb (January 7. 2008) MOS Transistor 34 16 . 2008) 1 1. Ron increases dramatically. Ron for 0. W/L For VDD >> VT+VDSAT/2. For high enough VDS the depletion region around drain may extend to the source IDS flows regardless of VGS.Ron for a MOSFET Plot for average Ron for VGS= VDD and VDS = VDD → VDD/2 Ron is inversely proportional to the ratio. For short channel devices it is also a function of L and VDS VT decreases with L VT decreases with increasing VDS (DIBL).

titanium or tungsten) to effectively reduce parasitic resistance – silicidation. µ ⎡ 295 ⎤ µ (T ) = µ ( 295o K ) ⎢ ⎣ T ⎥ ⎦ where.5 for electrons and 1 for holes. Deterioration in performance since IDS for a given voltage is reduced.. 2008) MOS Transistor 36 α 17 .Source Drain Resistance For scaled MOSFETs. α ≈ 1. -4mV/oC for high substrate doping levels and -2mV/oC for low doping levels IDS should increase with increase in temperature. Improvements: cover drain source regions with low-ρ material (e. Variation is approx. T However. increase in IDS is overwhelmingly offset by the degradation of mobility. © ptb (January 7. 2008) MOS Transistor 35 Temperature Effects Absolute value of VT decreases with an increase in temperature.g. make the device wider than needed. ⇒ I DS ∝ T −α © ptb (January 7. junctions are shallower. and contact openings become smaller parasitic resistance in series with the drain and source regions increases.

© ptb (January 7. Improvements done in present day devices: specially engineered source drain regions to bound peaks in elect. Hot electrons can leave silicon and tunnel into the gate oxide and get trapped therein. usually resulting in a destruction of the chip. increasing VTn for NMOSFET and decreasing VTp for PMOSFETs Electric fields of at least 104V/cm is needed for electrons to become hot. 2008) MOS Transistor 38 18 . Long-term reliability problems leading to circuit failure due to the degradation of device parameters. fields. 2008) MOS Transistor 37 Latchup in CMOS Parasitic bipolar transistors exist in CMOS – a couple of them form an SCR (thyristor) structure. the electric field at the drain of a MOSFET in saturation increases (for a fixed VDS) electrons are imparted high enough energy to become “hot”. reduced supply voltages.Hot Carrier Effects As L is reduced. VDD Triggering of this parasitic SCR leads to a short between VDD and GND. © ptb (January 7. or a system failure that can only be resolved by power-down.

1p + as=6.Prevention of Latchup To avoid latchup. High current or highly susceptible devices like I/O drivers should be surrounded by guard rings.6u L=0. Minimum of one plug per well. Provide numerous well and substrate contacts (plugs). © ptb (January 7.5p + as=1. Rwell and Rsub should be minimized.2u MOS Transistor 41 19 . One plug for every 5-8 devices in a well. 2008) MOS Transistor 39 MOSFET Description in SPICE3 d1 g1 g2 n1 g1 g2 GND x1 d1 x1 n2 GND Mn1 d1 g1 + ad=6.1p Mn2 x1 g2 + ad=1. placed close to the source connections of the devices.6u GND GND nenh W=3.6u ps=7.6u pd=7.5p © ptb (January 7.6u pd=0.2u ps=0. 2008) x1 GND nenh W=3.6u L=0.

Addison Wesley. Y. J. McGraw Hill. Weste & Eshraghian: “Principles of CMOS VLSI Design”.Bibliography 1. 3. 4. Tsividis: “Mixed Analog-Digital VLSI Devices and Technology”. © ptb (January 7. Prentice Hall S-M. 2008) MOS Transistor 42 20 . McGraw Hill. 2. Kang & Y. Rabaey: “Digital Integrated Circuits”. Leblebici: “CMOS Integrated Circuits: Analysis and Design”.

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