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**Pin Diagram Bottom view of BC107
**

B E C

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EC2208 - Electronic Circuits – I LAB

Ex. no: Date: Aim

1. COMMON EMITTER AMPLIFIER WITH FIXED BIAS

To design and construct BJT Common Emitter Amplifier using fixed bias . To measure the gain and to plot the frequency response and to determine the Gain Bandwidth product (GBW). Apparatus Required S.No 1. 2. 3. 4. 5. 6. Equipments / Components Power Supply Resistor Capacitor Transistor AFO CRO Range / Details (0 – 30) V 5.1 K , 3M 1 µF BC 107 (0 – 1) MHz (0 – 20) MHz Qty 1 1 1 1 1 1

Fixed Bias with Emitter Resistor

The fixed bias circuit is modified by attaching an external resistor to the emitter. This resistor introduces negative feedback that stabilizes the Q-point. From Kirchhoff's voltage law, the voltage across the base resistor is VRb = VCC - IeRe - Vbe

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EC2208 - Electronic Circuits – I LAB

Tabulation

Frequency (Hz)

Vo (V)

Gain = Vo / Vs

Gain = 20log(Vo/Vs)dB

Model Graph

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EC2208 - Electronic Circuits – I LAB

From Ohm's law, the base current is Ib = VRb / Rb. The way feedback controls the bias point is as follows. If Vbe is held constant and temperature increases, emitter current increases. However, a larger Ie increases the emitter voltage Ve = IeRe, which in turn reduces the voltage VRb across the base resistor. A lower baseresistor voltage drop reduces the base current, which results in less collector current because Ic = ß IB. Collector current and emitter current are related by Ic = α Ie with α ≈ 1, so increase in emitter current with temperature is opposed, and operating point is kept stable. Similarly, if the transistor is replaced by another, there may be a change in IC (corresponding to change in β-value, for example). By similar process as above, the change is negated and operating point kept stable. For the given circuit, IB = (VCC - Vbe)/(RB + (β+1)RE). Merits: The circuit has the tendency to stabilize operating point against changes in temperature and βvalue. Demerits: In this circuit, to keep IC independent of β the following condition must be met:

**which is approximately the case if ( β + 1 )RE >> RB.
**

• • • •

As β-value is fixed for a given transistor, this relation can be satisfied either by keeping RE very large, or making RB very low. If RE is of large value, high VCC is necessary. This increases cost as well as precautions necessary while handling. If RB is low, a separate low voltage supply should be used in the base circuit. Using two supplies of different voltages is impractical. In addition to the above, RE causes ac feedback which reduces the voltage gain of the amplifier.

Usage: The feedback also increases the input impedance of the amplifier when seen from the base, which can be advantageous. Due to the above disadvantages, this type of biasing circuit is used only with careful consideration of the trade-offs involved.

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EC2208 - Electronic Circuits – I LAB

1 By applying KVL to the input side. VCC – IBRB – VBE = 0 IB = IC/ β = 1mA/250 = 4µA RB = (VCC – VBE) / IB = (12 – 0. IC = 1 mA By applying KVL to output side.fL ~5~ EC2208 . ICRC = 6V RC = 6V/10-3 = 6K Choosing a standard value for RC as 5.6 K X 100) = 0.6 K C1 = 1/ (2π X 1.Design Choose β = 250.7)/4x10-6 = 2.9µF ≈ 1µF Calculation Bandwidth = fH .825M ≈ 3M Design of input capacitor F = 1/2πhieC Take F = 100Hz and hie = 1. VCC – ICRC – VCE = 0 VCC = ICRC – VCE Assume equal drops across RC and VCE VRC = VCE = 6V.Electronic Circuits – I LAB . VCC = 12V.

fL Result Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and the frequency response curve is plotted. 3) The high frequency point is called the upper 3dB point. 5) The difference between the upper 3dB point and the lower 3dB point in the frequency scale gives the bandwidth of the amplifier. The bandwidth is found to be __________________ ~6~ EC2208 . 3) Note down the corresponding output voltage. 5) Calculate the Bandwidth from the Frequency response graph To plot the Frequency Response 1) The frequency response curve is plotted on a semi-log scale. (i. 6) From the plotted graph the bandwidth is obtained.e) Bandwidth = fH . 2) The mid frequency voltage gain is divided by √2 and these points are marked in the frequency response curve. 4) Plot the graph: Gain in dB Vs Frequency in Hz.Electronic Circuits – I LAB . 4) The lower frequency point is called the lower 3dB point. vary the frequency from 1Hz to 1MHzin regular steps.Procedure 1) Connect the circuit as per the circuit diagram 2) Set Vin = 50mV in the signal generator. Keeping input voltage constant.

Circuit Diagram CE Amplifier with Self Bias Ex.Electronic Circuits – I LAB . COMMON EMITTER AMPLIFIER WITH SELF BIAS ~7~ EC2208 . no: 2.

and at the same time. In this circuit. Operating point is almost independent of β variation. the voltage divider holds the base voltage fixed independent of base current provided the divider current is large compared to the base current.No 1. ~8~ EC2208 . Merits • • • Unlike above circuits. However.Date: Frequency (Hz) Aim Vo (V) Gain = Vo / Vs Gain = 20log(Vo/Vs)dB To design and construct BJT Common Emitter Amplifier using voltage bias (self bias) with and without bypassed emitter resistor. By proper selection of resistors R1 and R2. Equipments / Components Power Supply Resistor Capacitor Transistor AFO CRO Range / Details (0 – 30) V 1K . One of the most widely used combination-bias systems is the voltage-divider type. However. collector current varies with temperature (for example) so an emitter resistor is added to stabilize the Q-point. only one dc supply is necessary.7K 1 µF BC 107 (0 – 1) MHz (0 – 20) MHz Qty 1 1 1 1 1 1 Theory Voltage divider bias (Self bias) A combination of fixed and self-bias can be used to improve stability and at the same time overcome some of the disadvantages of the other two biasing methods.Electronic Circuits – I LAB . to provide long-term or dc thermal stability. allow minimal ac signal degeneration. To measure the gain and to plot the frequency response and to determine the Gain Bandwidth product (GBW). If Cbp is large enough. Operating point stabilized against shift in temperature. Apparatus Required S. The voltage across R2 forward biases the emitter junction. 6. 3. even with a fixed base voltage. The voltage divider is formed using external resistors R1 and R2. the bypass capacitor (Cbp) is placed across R3. 4. rapid signal variations will not change its charge materially and no degeneration of the signal will occur. the operating point of the transistor can be made independent of β. 2. 10K . 4. 5. 61K .

Tabulation Model Graph Design ~9~ EC2208 .Electronic Circuits – I LAB .

7V Assume R2 = 10 K VR2 = VCC.7V Drop across R2 (VR2) = VBE + VRE = 1. Drop across VCE with the supply of 12V is given by 12V – 1V = 11V Assume equal drops across ICRC and VCE So ICRC = VRC = 11/2 = 5.5V / 1mA = 5.Drop across RE (VRE) is assumed to be 1V. we can use a standard value of 4.R2/ (R1+R2) R1 = (12 X 10) / (1.5 K Instead of using 5.6 K C1 = 1/ (2π X 1.6 K X 100) = 0.7 – 10) = 60.5V Assume IC = 1 mA. IE ≈ IC = 1mA RE = VRE/IE = 1V/1mA = 1K Design of R1 and R2 Drop across VBE = 0.5 K R1 is assumed to be 61 K Design of input capacitor F = 1/2πhieC Take F = 100Hz and hie = 1.Electronic Circuits – I LAB . Then RC = VRC / IC = 5.7 K VRE = 1V.5 K .9µF ≈ 1µF Calculation ~ 10 ~ EC2208 .

fL Procedure To plot the Frequency Response ~ 11 ~ EC2208 .Bandwidth = fH .Electronic Circuits – I LAB .

e) Bandwidth = fH . Bandwidth = Circuit diagram: ~ 12 ~ EC2208 . (i. 6) From the plotted graph the bandwidth is obtained. 2) The mid frequency voltage gain is divided by √2 and these points are marked in the frequency response curve.1) The frequency response curve is plotted on a semi-log scale. 5) The difference between the upper 3dB point and the lower 3dB point in the frequency scale gives the bandwidth of the amplifier.Electronic Circuits – I LAB . 3) The high frequency point is called the upper 3dB point.fL Result Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency response curve is plotted. 4) The lower frequency point is called the lower 3dB point.

Electronic Circuits – I LAB .+ BC 107 47 µF AFO 5 mV a R2 10 KΩ RE 6 KΩ + 47 µF VO (CRO) ~ 13 ~ EC2208 .VCC = 12 V R1 8 KΩ .

6V R1 + 10 X 103 120 X 103 = R1 + 10 X 103 6. COMMON COLLECTOR TRANSISTOR AMPLIFIER To design and construct BJT Common Collector Amplifier using voltage divider bias (self-bias).Ex. we assume equal drops across VCE and Emitter Resistance RE.6V Drop across the resistance R2 is VR2 = VBE + VRE =6. no: Date: Aim: 3. 6KΩ. Transistors Regulated Power Supply Audio Frequency Oscillator Resistors Capacitors CRO BC107 1. The quiescent current of 1mA is assumed.18 X 103 = R1 + 10 X 103 R1 = 8 KΩ (3. 8KΩ.3 K + 4. 2.7 K) ~ 14 ~ EC2208 . 3.6 18. Drop across RE is assumed to be VRE =6V Drop across VCE is VCC –VRE =6V We know that ICQ =IE. 4. We assume a standard supply of Vcc = 12V. 10KΩ (all are ¼ W) 47µF Design: Since voltage amplification is done in the transistor amplifier circuit.6V Assume R2 =10KΩ VCC R2 = 6. 6.Electronic Circuits – I LAB . 5. To measure the gain and to plot the frequency response & to determination of Gain Bandwidth Product Apparatus required: 1.6 V R1 + R2 12 X 10 X 103 = 6. 2. VRE = 6V. Now RE = VRE = 6V = 6KΩ IE 1X 10-3 Design of R1 & R2 Drop across RE is 6V Drop across VBE is 0.

Tabular column Vs = Frequency (Hz) VO (Volts) Gain = VO / VS Gain = 20 log (VO/VS) (dB) Model graph (frequency response) Gain dB A/max 3dB Line fL fH frequency (Hz) EC2208 .Electronic Circuits – I LAB ~ 15 ~ .

Calculate bandwidth from the graph. 50V – 1A. Transistor BC107. Result Thus a BJT Common Collector Amplifier is designed and implemented and the frequency response curve is plotted. Set VS = 5 mV using AFO. Plot the graph gain Vs frequency.Electronic Circuits – I LAB .Procedure 1. 300 MHz 2. Regulated Power Supply (0. 1A ~ 16 ~ EC2208 . 3. 4. 2. 3W. vary the frequency from 0 Hz to 1 MHz in regular steps and note down the corresponding output voltage. Connect the circuit as per the circuit diagram.30). Bandwidth = Specifications: 1. Keeping the input voltage constant. 5.

Circuit diagram: VCC = 12 V R1 47 KΩ RC 4.100 µF ~ 17 ~ EC2208 .+ BC 107 47 µF AFO 5 mV a R2 10 KΩ RE1 4.Electronic Circuits – I LAB .7 KΩ RE 1 KΩ BC 107 VO (CRO) + CE .7 KΩ + 47 µF .

Ex.7 KΩ) IC Design of R1 & R2: Drop across RE is 1V. 4. Biasing Design: Assume R2 = 10KΩ and Ic = 1mA. It is equal to VRC & VCE = 5. Capacitors 47µF. The drop across VCE with a supply of 1. So to reduce the effect of ICBO the 1st stage ICBO flowing through the emitter of the 1st stage is not allowing to enter the 2nd stage by paralleling a resistor between B & E of the 2nd stage T2.5 KΩ (4.5V RC = VRC = 5. IE = (101)2 X 10 nA IE ≅ 105 nA ≅ 0. DARLINGTON COMMON EMITTER AMPLIFIER To design a Darlington amplifier using BJT and to measure the gain and input resistance. 10KΩ (all are ¼ W) 3. Hence the 2nd stage IE current will be IE = (β+1)2ICO For silicon transistor ICBO is the order of 10nA at room temperature β = 100. AFO 6. CRO 5. Transistors BC 107 2. Since voltage amplification is done in the Darlington transistor amplifier circuit. Drop across VBE1 & VBE2 is 0. Apparatus required: 1.7 KΩ.7KΩ. To plot the frequency response and to calculate the Gain Bandwidth Product (GBW). RPS 7. no: Date: Aim: 1. Drop across Re is assumed to be 1V. This shunting resistance will be the range of 1 to 4. Resistors 1KΩ.2 V is given by 12 – 1 = 1V. Drop across the resistance R2 is VRE + VBE1 + VBE2 Tabular column: ~ 18 ~ EC2208 . 4. 100µF 4. Now. we assume equal drops across VCE and load resistance RC. 2. So the ICBO(β+1) will flow through this resistance and a part of this current might flow through hie + βdcRE. The ICQ = 1mA is assumed.1mA This current will get double with every 100 rise in temperature.6V. 47KΩ.Electronic Circuits – I LAB . Connecting wires & Breadboard Design: Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base current for the 2nd stage. We assume standard supply of 12V.

Electronic Circuits – I LAB .Vs = Frequency (Hz) VO (Volts) Gain = VO / VS Gain = 20 log (VO/VS) (dB) Model graph (frequency response): Gain dB A/max 3dB Line fL fH frequency (Hz) ~ 19 ~ EC2208 .

6 VR2 = 2. 2.30). 2. 1A Circuit diagram: ~ 20 ~ EC2208 . 3.2V R1 + R2 1.2 54. 300 MHz 2.= 1 + 0.Electronic Circuits – I LAB . 4. 5. Result: 1.5 X 103 = R1+ 10 X 103 R1 = 54. Keeping the input voltage constant. The frequency response curve is plotted on a log scale.2 R1 + 10 X 10 3 120 X 103 = R1 + 10 X 103 2.fL = Specifications: 1. Set VS = 5 mV using AFO. 50V – 1A. Transistor BC107.2 X 10 X 103 = 2.5 X 103Ω R1 is rounded to be 47 KΩ Procedure: 1. vary the frequency from 0 Hz to 1 MHz in regular steps and note down the corresponding output voltage.2V R2 is assumed to be 10 KΩ VCC R2 = 2.6 + 0. Plot the graph gain Vs frequency. Connect the circuit as per the circuit diagram. Calculate bandwidth from the graph.5 X 103 – 10 X 103 R1 = 44. 3W. From the graph the bandwidth is obtained Bandwidth = fH . Regulated Power Supply (0.

no: 5.Electronic Circuits – I LAB .Pin Details Ex. COMMON DRAIN AMPLIFIER ~ 21 ~ EC2208 .

Apparatus required: 1.Date: Aim: To design a common drain amplifier and to measure the gain. input resistance and output resistance with and without Bootstrapping. IDSS = 9. When a signal is applied to JFET gate via Cin.7KΩ . So choose the value of resistance RG very large with in The range of 1MΩ to 10MΩ Theory: Here input is applied between gate and source & output between source and Drain. VP = -4V. Ci = 1µF VGS = ID RS .4.7V VRD + VDS = VDD-VRS = 12-2. CRO 7.Electronic Circuits – I LAB . As VGS is fairly constant and Vs varies with Vi.5mA. Audio Frequency Oscillator 4.7=9. Here output voltage follows the change in the signal voltage applied to the gate. 2. the circuit is also called as Source follower Tabulation ~ 22 ~ EC2208 . Bread board and connecting wires Bias design: VDD = 12 V. Transistor .VG varies with the signal.1µ F 6.3V. Assume equal drops across VRD & VDS VRD = VDS = 4. Capacitor . Regulated Power supply 3. we can select standard value = 4.7KΩ FET input is always reverse bias.65V RD = VRD/ID = 4. Voltage drop across R S = 2. Here Vs = VG + VGS. 1MΩ 5.7KΩ.65KΩ.7KΩ.BC-107 2. Resistors .ID = IDSS{1-(VGS/VP)}2 RS = 2. ID = 1mA.65KΩ Instead of 4.

Electronic Circuits – I LAB .Frequency (Hz) Vo (V) Gain = Vo / Vs Gain = 20log(Vo/Vs)dB Model Graph Procedure: ~ 23 ~ EC2208 .

input resistance and output resistance are calculated using the measured parameters.Electronic Circuits – I LAB . Circuit Diagram – Differential Amplifier ~ 24 ~ EC2208 . 4. Connect the circuit as shown in the circuit diagram 2.1. Keeping the input voltage constant. Set Vs= 50 mv in AFO 3. Plot the graph: gain Vs Frequency 5. Calculate the bandwidth from the Graph Result: Thus a common drain amplifier is designed and the gain. vary the frequency from 0 Hz to1MHz in regular steps and note down the corresponding output voltage.

Electronic Circuits – I LAB .Common mode Configuration Differential mode Configuration Ex. DIFFERENTIAL AMPLIFIER ~ 25 ~ EC2208 . no: 6.

M.M. Hence it is called differential amplifier. -1 no. Power Supply CRO Function Generator Transistors Resistors - BC107 1KΩ 470Ω -1 no . 4.2 nos.R. better the performance of the differential amplifier. Such an average level of two input signals is called common mode signal Higher the value of C. To improve C. 3.M. Formula C. Vo is proportional to difference between two input signals.R. Apparatus required 1.R.R we have to increase differential mode gain and decrease common mode gain ~ 26 ~ EC2208 .V1 and V2 are input voltages. and to find the common mode rejection ratio (CMRR).M.Date: Aim To construct the Differential Amplifier in a) Common mode and b) Differential mode.R. If we apply two input voltages equal in all respects then in ideal case output should be zero. 2.Electronic Circuits – I LAB . But output voltage depends on the average common level of the inputs. 5.R in dB = 20 log Ad/Ac Ad = Differential mode gain Ac = Common mode gain Theory The Differential amplifier amplifies the difference between two input voltage signals.R.R = Ad/Ac C.

Model Calculation For common mode signal Gain Ac = Vo / Vi Ac = For differential mode signal Gain Ad = Vo / Vi Ad = CMRR = 20 log (Ad / Ac) = ~ 27 ~ EC2208 .Electronic Circuits – I LAB .

Set Vi=5mV and note down Vo in both differential mode & common mode 3. Calculate C. Connections are given as per the circuit diagram 2.R.Electronic Circuits – I LAB .R Formulae For common mode signal: Gain Ac = Vo / Vi For differential mode signal: Gain Ad = Vo / Vi Common Mode Rejection Ratio: CMRR = 20 log (Ad / Ac) Result Thus a differential amplifier is constructed in both common mode and differential mode and the corresponding gains are obtained and the CMRR is calculated. Calculate the gain for both the modes 4. CMRR = ~ 28 ~ EC2208 .Procedure 1.M.

+ CRO Vi= 10mv ` R2= 10KΩ RE 1KΩ + 100µF - Pin Diagram Bottom view of BC 107 B E C 3-d view ~ 29 ~ EC2208 .Electronic Circuits – I LAB .7KΩ R1 = 61KΩ 1µF .Circuit diagram: Vcc=12V Rc = 4.

CLASS . To observe the output waveform and to measure the maximum power output and to determine the efficiency Apparatus required: 1. no: Date: Aim 7.5V/1mA = 5.5KΩ .5KΩ Instead of using 5. We can use a standard value of 4.A AMPLIFIER To design and construct a Class – A power amplifier.Ex. Hence VBB = IERE+VBE Hence VBE is neglected when compared to IERE Hence IE = VBB / RE. Transistor BC107 1 Resistors 1KΩ.5V VC = 5. 2. we assume a standard supply of 12V.4. 6.Electronic Circuits – I LAB .5V≅61KΩ Model graph: ~ 30 ~ EC2208 .7V . 5.7V R1=60. It is assumed that RBB / (βdc+1) = RE / 10 Hence RBB / (βdc+1) is neglected when compared RE.100µf(all are electrolytic) CRO (0-20MHz) AFO (0-1MHz) Regulated Power Supply Breadboard & Connecting Wires Bias design: Since voltage amplification is done in the transistor amplifier circuit.5V Now the voltage across the resistance RE is 5.10KΩ(all are ¼ watts) Capacitors 1µf. DESIGN OF R1 & R2: Voltage drop across RE = VRE = 1V Drop across VBE = 0.61KΩ. R2 is assumed to be 10KΩ VCCR2 / (R1 + R2 ) = VR2 10*12KΩ/(R1+10KΩ)=1. 3. Drop across RE is assumed to be 1V.the drop across VCE with a supply of 12V is given by 12V1V=11V It is equal to 11/2=5.7KΩ.7V Drop across the resistance R2 = VBE +VRE = VR2 VR2=1. The quiescent current of 1mA is assumed. 7.7KΩ.5V VCE = 5. We as equal drops across VCE & load resistance RE. 4.5V IC = 1mA RC = 5.

gain (dB) A 0.707 A fL Tabular column: VI = Frequency (KHz) V0 (mV) fh f (Hz) Gain = V0 / Vi Gain (dB) = 20 log V0 / Vi dB ~ 31 ~ EC2208 .Electronic Circuits – I LAB .

The maximum power output and the efficiency are determined. Keeping the input voltage constant. one full cycle. Set VS=10mV using AFO. For all the values of input signal.Theory: The Power amplifier is said to be class-A amplifier if the Q-point & the input signal are selected such that the output signal is obtained for a full input cycle. 3.Electronic Circuits – I LAB . 5. the angle of the collector current flow is 360° i. The collector current flows for 360°(full cycle)of the input signal. Procedure: 1. Plot the graph: gain Vs frequency. When an a. Connect the circuit as per the circuit diagram. For this.c input signal is applied. Result: The class-A amplifier is designed. In other words. constructed and the output waveform is observed.e. position of the Qpoint is approximately at the midpoint of the load line. 4. vary the frequency from few Hz to 1MHz in regular steps & note down the correspondingly output voltage. Calculate bandwidth from the graph. 2. the transistor remains in the active region &never enters into cut-off or saturation region. ~ 32 ~ EC2208 . the collector voltage varies sinusoidally hence the collector current also varies sinusoidally.

Electronic Circuits – I LAB .Circuit diagram Pin Diagram Bottom view of BC 107 / BC 178 B E C 3-d view Ex. CLASS – B POWER AMPLIFIER ~ 33 ~ EC2208 . no: 8.

When the signal voltage is positive. Transistors (0 – 30) V (0 – 20) MHz (0 – 1) MHz 47 KΩ 1 KΩ BC 107 BC 178 - 1No 1No 1No 1No Theory: The figure illustrates a Class – B Power Amplifier. i. T2 conducts while T1 is cut off. Set VS = 50mV(say) using the signal generator..e.. T1 (the NPN transistor) conducts. The load current is iL = ic1 – ic2 some advantages of the circuit are that the transformer less operation saves on weight and cost and balanced push – pull input signals are not required.e. The disadvantage is obtaining pause of transistor matched closely enough to achieve low distortion. Its operation can be explained by referring to the figure.Date: Aim: To design and construct a Class – B (complementary symmetry) power amplifier. This type of amplifier uses complementary symmetry. the two transistor have identical characteristics but one is PNP and the other NPN. and one NPN transistor and require no transformed. Resistor 5. When the signal voltage is negative. Apparatus required: 1. Keeping the input voltage constant. Procedure: 1. which employs one PNP. Power Supply 2. Plot the graph i. while T2 (the PNP transistor) is cut off. gain (dB) Vs frequency (on a semi – log graph) ~ 34 ~ EC2208 . vary the frequency from 0Hz to 1MHz. In regular steps. 3. Function Generator 4. 2.To observe the output waveform with crossover Distortion and to measure the maximum power output and to determine the efficiency. 4. Connect the circuit as per the diagram.Electronic Circuits – I LAB . Note down the corresponding output voltage. CRO 3.

Electronic Circuits – I LAB .Model graph: Tabular column: VI = 50 mV Frequency (KHz) V0 (mV) Gain = V0 / Vi I = 1 mA Gain (dB) = 20 log V0 / Vi dB ~ 35 ~ EC2208 .

η = Π V min 1− 4 Vcc Powergain = 1 Vcc 2 2 Π 2 RL Result Thus a Class – B (complementary symmetry) power amplifier is constructed and the output waveforms are observed and the maximum power output and efficiency is calculated.Formulae Efficiency.Electronic Circuits – I LAB . Circuit diagram: ~ 36 ~ EC2208 .

Electronic Circuits – I LAB .25 V Vac 12 ~ 37 ~ EC2208 .Half Wave Rectifier without filter 12 1N 4007 230 V 0 12 500Ω R a + Vdc - + -100 µF /25V a Vac Half Wave Rectifier with filter 12 1N 4007 230 V 0 500Ω R + 100 µF CRO .

Electronic Circuits – I LAB . Capacitor 1N4007 230V / 12 – 0. 2. Compare the theoretical ripple factor with the practical ripple factor. Connect the half wave rectifier as shown in figure. ~ 38 ~ EC2208 . Transformer 5. To design a Half wave rectifier with simple capacitor filter. Connecting Wires and Bread Board Procedure Half wave rectifier (i) Without Capacitor 1.12v. 4. 2. CRO 2. Apparatus Required 1. Test your transformer: Give 230v.Ex. 3. To measure the DC voltage under load and ripple factor and to compare with calculated values. no: Date: Aim 9. Calculate the Ripple factor r = Vac Vdc Note: The rectifier output consists of both AC & DC components. HALF WAVE RECTIFIER 1. 50Hz source to the primary coil of the transformer and observe the AC waveform of rated value without any distortion at the secondary of the transformer. 5. To block DC component 100µf (Electrolytic) Condenser is used. Diode 4. Measure the Vdc & Vac using DC and AC Voltmeters. Multimeter 3. Resistor 6. 200 mA 500Ω-1/4W(carbon film resistors) 100µF /25V (0-20 MHz) 7.

Electronic Circuits – I LAB .Model Graph VI(v) T(m sec) Input Wave Form Vo (V) With filter Without filter T(m sec) Half Wave Rectifier Output ~ 39 ~ EC2208 .

5. Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the X-axis. Calculate C using the formula r = 1/2√3fRC 3. Idc = 1A) (0-30). 4.1A ~ 40 ~ EC2208 . Connect the half wave rectifier with filter circuit as shown in fig. RPS (700V. Ripple Factor Theoretical Practical Specifications: 1. Connect CRO across load. 2.Electronic Circuits – I LAB . Assume r= 10% of ripple peak-to-peak voltage for R= 500Ω. Switch the CRO into DC mode and observe the waveform.(ii) With capacitor 1. Diode 1N4007 2. Result Thus the Full wave rectifier is designed with and without capacitor filter and the corresponding dc output voltages and the ripple factors are measured and verified with the theoretical values.PIV.

Electronic Circuits – I LAB .Circuit diagram: Full Wave Rectifier without filter 12V D1 230 V D3 1N 4007 D4 R 500Ω + Vdc + 100 µF .25 V a D2 a Vac Full Wave Rectifier with filter 12V D1 230 V D3 1N 4007 D4 R + 100 µF CRO 25 V D2 ~ 41 ~ EC2208 .

Test your transformer: Give 230v. 2. no: Date: Aim 10. Connect the full wave rectifier as shown in figure. FULL WAVE RECTIFIER 1. ~ 42 ~ EC2208 . Connecting Wires and Bread Board Procedure Full wave rectifier (i) Without Capacitor 1. Diode 4. Apparatus Required 1. 3. 2. Capacitor 1N4007 230V / 12 – 0. To measure the DC voltage under load and ripple factor and to compare with calculated values. Compare the theoretical ripple factor with the practical ripple factor. Transformer 5.Ex. To block DC component 100µf (Electrolytic) Condenser is used. CRO 2. Measure the Vdc & Vac using DC and AC Voltmeters. 200 mA 500Ω-1/4W(carbon film resistors) 100µF /25V (0-20 MHz) 7.Electronic Circuits – I LAB . 5. 4. Resistor 6. To design a Full wave rectifier with and without simple capacitor filter. Multimeter 3.12v. 50Hz source to the primary coil of the transformer and observe the AC waveform of rated value without any distortion at the secondary of the transformer. Calculate the Ripple factor r = Vac Vdc Note: The rectifier output consists of both AC&DC components.

Electronic Circuits – I LAB .Model graph: VI(v) t (m sec) Input Wave Form VO (V) With filter Without filter t (m sec) Full Wave Rectifier Output ~ 43 ~ EC2208 .

Result Thus the Full wave rectifier is designed with and without capacitor filter and the corresponding dc output voltages and the ripple factors are measured and verified with the theoretical values. RPS (700V. Idc = 1A) (0-30).Electronic Circuits – I LAB . To plot ripple peak-to-peak voltage Vs. 1A ~ 44 ~ EC2208 . 3. 4. To get a variable load resistance a number of 500Ω. Idc to choose C a ripple factor of 0.PIV. Diode 1N4007 2.15 is assumed. Plot the graph Idc Vs ripple peak to peak. Ripple Factor Theoretical Practical Specifications: 1. Where N is number of 500Ω resistances connected in parallel. 5W of resistance are to be connected in parallel. 2.(ii) With capacitor: 1. The above steps are repeated for the various values of capacitance. Hence Idc = Vdc /( N X 500).

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