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SystemVerilog Update Part1 Cummings

SystemVerilog Update Part1 Cummings

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DAC 2009 SystemVerilog-2009 Presentation

by Sunburst Design, Beaverton, Oregon, © 2009

5 of 59

The SystemVerilog Mantis Database
• The Mantis database contains corrections, clarifications & enhancement descriptions for SystemVerilog-2009 • www.eda.org/svdb
Current errata & proposed enhancements Current errata & proposed enhancements guest Login: guest Login: Password: guest Password: guest

• Mantis Item numbers are noted on appropriate slides • Mantis items details can be viewed in the Mantis database
After logging in ... After logging in ... Enter Issue # ... Enter Issue # ... ... then select the ... then select the Jump button Jump button

890
© 2009, Sunburst Design, Inc.

Scheduling of New SV Commands
Mantis 890
From previous From previous time slot time slot #1step #1step Preponed Preponed Region for new Region for new SV commands SV commands

6 of 59

Active Active Inactive Inactive Active region Active region set set Evaluate concurrent Evaluate concurrent assertions assertions Trigger clocking blocks Trigger clocking blocks Reactive region Reactive region set set Execute Execute pass/fail assertion code pass/fail assertion code program block code program block code

Used for sampling & Used for sampling & verifying DUT outputs verifying DUT outputs
(testbench inputs) (testbench inputs)

NBA NBA Observed Observed

Regions for new Regions for new SV commands SV commands

Reactive Reactive Re-Inactive Re-Inactive

Update to IEEE1800-2005 Standard

Re-NBA Re-NBA

New event scheduling New event scheduling
© 2009, Sunburst Design, Inc.

(already implemented) (already implemented)

Postponed Postponed

To next To next time slot time slot
Sunburst

3 of 30

Rev 1.1

DAC 2009 SystemVerilog-2009 Presentation
by Sunburst Design, Beaverton, Oregon, © 2009

7 of 59

SystemVerilog-2009 Display Enhancements

© 2009, Sunburst Design, Inc.

8 of 59

Field Widths in Print Formats
Mantis 1175
program print; int a, b; initial repeat (8) begin ... randcase 3: a = 2: a = 2: a = 2: a = endcase randcase 1: b = 2: b = 2: b = 1: b = endcase $urandom_range( 5'h10); $urandom_range( 9'h100); $urandom_range(13'h1000); $urandom_range(17'h10000);

$display("a=%h
end endprogram
$display

b=%h", a, b);

$urandom_range( 5'h10); $urandom_range( 9'h100); $urandom_range(13'h1000); $urandom_range(17'h10000);
$display

Show all Show all leading 0's leading 0's
$display

("a=%h

b=%h" , a, b);
b=000000fb b=00000048 b=000000f4 b=00000860 b=0000003a b=00004895 b=0000007c b=000000da

("a=%0h

b=%0h" , a, b);

("a=%4h

b=%4h" , a, b);
a=71ec a=0003 a=0ed4 a=8fbb a=0003 a=00b1 a=0010 a=097a b=00fb b=0048 b=00f4 b=0860 b=003a b=4895 b=007c b=00da

a=000071ec a=00000003 a=00000ed4 a=00008fbb a=00000003 a=000000b1 a=00000010 a=0000097a

a=71ec b=fb a=3 b=48 a=ed4 b=f4 a=8fbb b=860 a=3 b=3a a=b1 b=4895 a=10 b=7c a=97a b=da

Remove leading Remove leading 0's (ragged display) 0's (ragged display)

4-character field 4-character field with leading 0's with leading 0's
(orderly display) (orderly display)

© 2009, Sunburst Design, Inc.

4 of 30

Rev 1.1

$urandom_range(13'h1000). 180. b. a.. $urandom_range(13'h1000). im: 80} b='{re: 72.1 . b).. endmodule Sized format Sized format specifier %4p for specifier %4p for orderly printing orderly printing initial $monitor(.*). im: 187} b='{re: 182. 158. a. sum. im: 41} b='{re: x. logic [7:0] im. Sunburst Design. typedef struct { logic [7:0] re. Sunburst Design. $display("a=%4x end endprogram b=%4x". b). int a. $urandom_range( 5'h10). forever #(`CYCLE/2) clk = ~clk. Inc. im: x} a='{re: 193. 216. $urandom_range(17'h10000).. complex_s a. end cplx_adder u1 (.. randcase 3: a = 2: a = 2: a = 2: a = endcase randcase 1: b = 2: b = 2: b = 1: b = endcase $urandom_range( 5'h10). sum. b). b). module structprint.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. b. assign sum = add(a.). sum. 10 of 59 Print Format Specifier %p (%4p) Mantis 331 package complex. 5 of 30 Rev 1. b). im: 92} b='{re: 20.. $urandom_range( 9'h100). Inc. Oregon. Same orderly printout Same orderly printout a=71ec a=0003 a=0ed4 a=8fbb a=0003 a=00b1 a=0010 a=097a b=00fb b=0048 b=00f4 b=0860 b=003a b=4895 b=007c b=00da %x is just "syntactic sugar" %x is just "syntactic sugar" (C-like . initial begin clk <= '0. $urandom_range(17'h10000). module cplx_adder ( output complex_s sum. $urandom_range( 9'h100). input complex_s a. . 218. endmodule $monitor("sum=%4p a=%4p b=%4p ". im: 148} a='{re: 138. sum='{re: sum='{re: sum='{re: sum='{re: sum='{re: x. Beaverton. © 2009 9 of 59 Print Format Specifier %x Mantis 1749 program print. a.. im: 219} © 2009.. %x is aasynonym for %h %x is synonym for %h initial repeat (8) begin .. endpackage import complex::*. im: 160} a='{re: 108. im: 154} a='{re: 36. . im: x} b='{re: 23. im: x} im: 240} im: 85} im: 240} im: 4} a='{re: x. logic clk. } complex_s.-not really needed) (C-like not really needed) © 2009. $monitor("sum=%4p a=%4p b=%4p ".

In SystemVerilog2009 In SystemVerilog2009 function void check_output. . 6 of 30 Rev 1. SystemVerilog2009 adds SystemVerilog2009 adds $sformatf function $sformatf function that returns aastring that returns string initial begin s = $sformatf("\nThe value of b = %0d'h%h\n". Inc.y===exp) $info ("PASS: y=%h else $fatal("FAIL: y=%h endfunction . a. $display("%s". y. . exp=%h".. endmodule © 2009. exp). exp).1 . logic [31:0] b = 32'haabbccdd. Oregon. a. Sunburst Design. if (cb1.. endmodule module tb. exp=%h". Mantis 1651: Mantis 1651: end $psprintf was rejected $psprintf was rejected endmodule (Proposed synonym for $sformatf ) © 2009.. "\nThe value of b = %0d'h%h\n".DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. SystemVerilog2005 SystemVerilog2005 $sformat task assigns $sformat task assigns string to output argument (s) ) string to output argument (s initial begin $sformat(s. exp=%h".. b). © 2009 11 of 59 $sformatf Returns a Formatted String Mantis 1589 & 1651 module test1.. Sunburst Design. Inc. s). (Proposed synonym for $sformatf ) 12 of 59 $fatal/$error/$warning/$info Display Tasks Mantis 1641 module tb.y===exp) $display("PASS: y=%h else $display("FAIL: y=%h endfunction . string s. y. $fatal / /$error / /$warning / /$info $fatal $error $warning $info could only be used in assertions could only be used in assertions In SystemVerilog2005 In SystemVerilog2005 function void check_output. exp). if (cb1. s). y. string s.. $display("%s". exp). $fatal / /$error / /$warning / /$info $fatal $error $warning $info can be used anywhere $display can be used can be used anywhere $display can be used exp=%h".. y. b). Output display Output display end endmodule The value of b = 32'haabbccdd module test2. logic [31:0] b = 32'haabbccdd. int a = 32.. int a = 32. Beaverton.

Inc. Oregon. Sunburst Design. Sunburst Design. endmodule Correct sensitivity Correct sensitivity list list © 2009. else q <= d. rst_n). input bit_t d. 7 of 30 Rev 1.1 . negedge rst_n) if (!rst_n) q <= 0. 14 of 59 always_ff Logic-Specific Process • always_ff – Conveys designer's intent to infer clocked logic module dff1 ( output bit_t q. clk.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. © 2009 13 of 59 SystemVerilog-2009 Design Enhancements © 2009. Beaverton. Inc. always_ff @(posedge clk.

v ain 8 bin 8 opcode[2:0] 3 alu (8-bit) alu_out[7] alu_out 1 8 1 1 zero ones 8 xtend accum 8 Dangling zero Dangling zero & ones outputs & ones outputs . © 2009 15 of 59 Edge Event . rst_n).name 8 of 30 Rev 1.For DDR Logic Mantis 2396 • SV2009 adds edge keyword Currently illegal syntax Currently illegal syntax for synthesis for synthesis module ddrff ( output bit_t q. Sunburst Design. Sunburst 16 of 59 .name allows unconnected ports to be omitted ports to be omitted clk rst_n dataout[15:8] 8 dataout[7:0] 16 dataout © 2009.name intent for .v alu_accum.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. negedge rst_n) Could this synthesize to aaDDR flip-flop Could this synthesize to DDR flip-flop in an ASIC vendor library ?? in an ASIC vendor library ?? © 2009.name allows unconnected . always_ff @(clk. Sunburst Design. else q <= d. Inc.1 . Beaverton. Inc. negedge rst_n) if (!rst_n) q <= 0. Not the original Not the original intent for . endmodule Equivalent to both Equivalent to both posedge / /negedge posedge negedge No posedge (clk) No posedge (clk) No negedge (clk) No negedge (clk) Remove posedge to permit Remove posedge to permit triggering on both edges triggering on both edges ?? ?? always_ff shows always_ff shows designer's intent designer's intent always_ff @(edge clk.name Instantiation & Unconnected Ports Mantis 1660 SystemVerilog-2009 SystemVerilog-2009 clarification clarification alu_accum. clk. Oregon. input bit_t d.

. . .. . .. xtend xtend (.a}) 3'b100: y[a]=1. . Legal (but not required): Legal (but not required): list unconnected ports list unconnected ports alu alu (.bin..one().. 9 of 30 Rev 1.ain. . .opcode).din(alu_out[7]).name 18 of 59 2-to-4 Decoder w/ Enable SystemVerilog-2005 Style module dec2_4a ( output logic [3:0] y.dout(dataout[15:8]). 3'b101: y[a]=1.alu_out.dataout(dataout[7:0]).opcode).bin.clk.rst_n). input logic [1:0] a. rst_n). omit design port (alu_out) ) omit design port (alu_out alu alu (. . . Legal (but WRONG!): Legal (but WRONG!): Another good reason to avoid using . .dataout(dataout[7:0]). Legal: Legal: . Inc.name Instantiation & Unconnected Ports Mantis 1660 module alu_accum ( output [15:0] dataout.ain. . . Oregon. 3'b111: y[a]=1. .zero(). . unique case ({en.bin.clk.datain(alu_out).opcode). Beaverton. input clk. . bin. accum accum (.datain(alu_out). .dataout(dataout[7:0]). omit unconnected ports omit unconnected ports alu alu (...rst_n). input [7:0] ain. . endmodule .alu_out.name Another good reason to avoid using . input [2:0] opcode.clk.clk. endcase end endmodule unique case unique case with initial default with initial default assignment assignment ============================ | Line | full/parallel | ============================ | # | user/user | ============================ unique unique Same as full_case Same as full_case parallel_case parallel_case SystemVerilog simulators are required SystemVerilog simulators are required to give a run-time warning when en=0 to give a run-time warning when en=0 parallel_case parallel_case (uniqueness) (uniqueness) full_case full_case all possible cases are defined all possible cases are defined (others are "don't cares") (others are "don't cares") unique means: unique means: (1) case expression can only match 11case item (1) case expression can only match case item (2) case expression MUST match 11case item (2) case expression MUST match case item © 2009. © 2009 17 of 59 .datain(alu_out). wire [7:0] alu_out. always_comb begin y = 0. Inc. Sunburst Design. accum accum (.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. input logic en). Sunburst Design. . . © 2009. ... accum accum (.1 . 3'b110: y[a]=1. . .ain.rst_n). .rst_n).

input logic [1:0] a.a}) 3'b100: y[a]=1. 10 of 30 Rev 1. but fixes the Ugly. always_comb begin y = 0. Inc. 3'b101: y[a]=1. Sunburst Design. input logic en). 3'b110: y[a]=1. Oregon. 3'b111: y[a]=1.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. 20 of 59 2-to-4 Decoder w/ Enable SystemVerilog-2005 Current Work-Around module dec2_4b ( output logic [3:0] y. Sunburst Design. Beaverton. Inc. © 2009 19 of 59 2-to-4 Decoder with Enable WRONG Synthesis Results! Dangling enable! Dangling enable! en unique case unique case dec2_4a dec2_4a unique unique infers the infers the wrong logic wrong logic SystemVerilog simulation SystemVerilog simulation should warn about this error should warn about this error y[3] y[2] y[1] a[1] a[0] y[0] © 2009. unique case ({en.1 . endcase end endmodule unique case unique case with initial default with initial default assignment assignment ============================ | Line | full/parallel | ============================ | # | auto/user | ============================ unique with empty default unique with empty default same as parallel_case same as parallel_case Empty default Empty default kills full_case kills full_case Ugly. but fixes the synthesis results synthesis results © 2009. default: .

input logic en).a}) 3'b100: y[a]=1. 11 of 30 Rev 1. always_comb begin y = 0.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. Inc. Inc. Beaverton.parallel_case Equivalent Mantis 2131 module dec2_4c ( output logic [3:0] y. 3'b110: y[a]=1. 3'b101: y[a]=1. 3'b111: y[a]=1.1 . Sunburst Design. endcase end endmodule unique0 case unique0 case with initial default with initial default assignment assignment ============================ | Line | full/parallel | ============================ | # | auto/user | ============================ unique0 unique0 same as same as parallel_case parallel_case Simulation is correct when en=0 Simulation is correct when en=0 parallel_case parallel_case (uniqueness) (uniqueness) unique0 means: unique0 means: (1) case expression can only match 11case item (1) case expression can only match case item (2) case expression can match 11or 00case items (2) case expression can match or case items © 2009. NOT full_case NOT full_case (others covered by initial (others covered by initial default assignment) default assignment) 22 of 59 2-to-4 Decoder with Enable Correct Synthesis Results a[1] SystemVerilog SystemVerilog dec2_4b dec2_4b dec2_4c dec2_4c a[0] en y[3] y[2] y[1] y[0] © 2009. © 2009 21 of 59 Unique0 . unique0 case ({en. Oregon. Sunburst Design. input logic [1:0] a.

negedge rst_n) if (!rst_n) q <= '0. input logic clk. else q <= d. Inc. input logic [7:0] d. else if (!set_n) q <= '1. negedge rst_n. Oregon. Sunburst Design. not_a : z = c. (vendors did not want (vendors did not want to report false-errors) to report false-errors) Reported as violations Reported as violations Ask vendors to provide Ask vendors to provide fatal-on-violation option fatal-on-violation option Simulation scenario: Simulation scenario: (1) a goes to 1 (1) a goes to 1 (2) always_comb (a1) triggers (2) always_comb (a1) triggers (3) unique case detects violation (3) unique case detects violation (a & not_a both match 1'b1) (a & not_a both match 1'b1) (4) violation report generated (4) violation report generated (scheduled into Observed Region) (scheduled into Observed Region) (5) always_comb (a2) triggers (5) always_comb (a2) triggers (6) not_a goes to 0 (6) not_a goes to 0 (7) always_comb (a1) re-triggers (7) always_comb (a1) re-triggers (8) unique case detects NO violation (8) unique case detects NO violation (9) violation report cleared (9) violation report cleared (before entering Observed Region) (before entering Observed Region) 24 of 59 Default Inputs For Module/Interface Ports Mantis 2399 (Corrects Mantis1619 Enhancement) register module module register ( register module output logic [7:0] q. end © 2009. CAUTION: instantiation rules can be confusing endmodule can be confusing 12 of 30 Rev 1. Inc. always_ff @(posedge clk. rst_n). Sunburst Design.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. negedge set_n) if (!rst_n) q <= '0. © 2009 23 of 59 priority/unique/unique0 Violations Mantis 2008 Reported as warnings Reported as warnings • SV-2005: priority/unique warnings • SV-2009: priority/unique/unique0 violations unique: Only one case unique: Only one case item should match the item should match the case expression case expression always_comb begin: a1 unique case (1’b1) a : z = b.1 . endcase end always_comb begin: a2 not_a = !a. always_ff @(posedge clk. register module register module with set_n input with set_n input New input has New input has aadefault value default value © 2009. rst_n. endmodule module register ( output logic [7:0] input logic [7:0] input logic input logic New version of New version of Old version of Old version of Default values might be useful Default values might be useful for infrequently used inputs for infrequently used inputs Default values only legal Default values only legal with ANSI-style port list with ANSI-style port list q. Beaverton. d. set_n='1 ). CAUTION: instantiation rules else q <= d. clk.

clk. d.clk(clk).set_n)). . . . .q. ERROR: set_n not ERROR: set_n not declared in tb declared in tb 13 of 30 Rev 1..q(q).d. .rst_n(rst_n).q(q). . © 2009. rst_n.set_n(set_n)). register keeps default register keeps default set_n // rst_n values set_n rst_n values tb only overrides tb only overrides default rst_n value default rst_n value CAUTION: this can be confusing CAUTION: this can be confusing register r1 (.clk. © 2009. rst_n. input logic clk. . input logic rst_n='1 .d. . set_n. © 2009 25 of 59 Default Inputs For Module/Interface Ports Mantis 2399 (Corrects Mantis1619 Enhancement) set_n / /rst_n set_n rst_n module register ( output logic [7:0] q. input logic set_n='1 ).q(q).d. logic [7:0] logic [7:0] set_n logic set_n assigned logic assigned declared declared q.. tb only overrides tb only overrides default rst_n value default rst_n value register r1 (.d(d). . . input logic clk.clk. . .rst_n. logic [7:0] logic [7:0] logic logic both declared both declared q. clk. . Oregon.clk(clk). register r1 (. . ..clk(clk). register r1 (.rst_n). . register r1 (. Inc..clk(clk). .DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design.q. . tb overrides default tb overrides default set_n // rst_n values set_n rst_n values register r1 (.d(d). Inc.q(q).d(d). assign set_n = d[7]. .rst_n).set_n). . input logic [7:0] d. input logic [7:0] d. . .d(d). tb overrides default set_n // rst_n values tb overrides default set_n rst_n values register r1 (. .q.rst_n(rst_n). .set_n(. .clk.rst_n(rst_n)). . 26 of 59 Default Inputs For Module/Interface Ports Mantis 2399 (Corrects Mantis1619 Enhancement) set_n NOT set_n NOT module register ( output logic [7:0] q. // register .set_n). . .d.. d. Beaverton.rst_n(rst_n)).q. // register . . . set_n and rst_n inputs endmodule set_n and rst_n inputs have default values have default values module tb.... clk.1 . register instantiation register instantiation endmodule register r1 (. Sunburst Design. register instantiation register instantiation endmodule register r1 (. Sunburst Design.rst_n. input logic rst_n='1 . input logic set_n='1 ).*). set_n and rst_n inputs endmodule set_n and rst_n inputs have default values have default values module tb.

assign tmp = (a & b) | c. 28 of 59 SystemVerilog-2009 Packages. ..DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. Verilog only allows bit Verilog only allows bit and part selects of and part selects of nets and variables nets and variables ILLEGAL . logic [2:0] y. 14 of 30 Rev 1.-to reference aapart ILLEGAL to reference part select on the LHS expression select on the LHS expression Might require Might require extra code extra code © 2009. logic [2:0] y. Beaverton. logic [7:0] tmp. b. c.1 . Inc. endmodule SystemVerilog-2009 SystemVerilog-2009 allows bit and part selects allows bit and part selects on RHS concatenations on RHS concatenations NOTE: {concatenation} braces NOTE: {concatenation} braces are required to do aapart select are required to do part select on the result of the expression on the result of the expression CAUTION: more concise but CAUTION: more concise but perhaps more confusing(?) perhaps more confusing(?) = {(a & b) | c}[4:2]. endmodule Correction to DAC2009 Correction to DAC2009 presentation presentation module expr_range. logic [7:0] a... Sunburst Design. Oregon. logic [7:0] a. b. Parameters. Sunburst Design. Compiler Directives © 2009.. c. assign y . assign y = tmp[4:2]. Inc. © 2009 27 of 59 Bit Selects & Part Selects of Expressions Mantis 1197 module expr_range.

30 of 59 Package Import in Design Element Header Mantis 329 SystemVerilog-2005 SystemVerilog-2005 package usage style #2 package usage style #2 Declare the data_pkg Declare the data_pkg and bit_pkg and bit_pkg bit_pkg::clk_t bit_pkg::clk_t not used not used Use the data_t and clk_t Use the data_t and clk_t from the data_pkg from the data_pkg Use the rst_t from Use the rst_t from the bit_pkg the bit_pkg package data_pkg.. import bit_pkg::rst_t. rst_n). Inc. typedef bit clk_t. module register output data_t input data_t input clk_t input rst_t . typedef logic clk_t. endpackage package bit_pkg. endmodule q. typedef logic [7:0] data_t. Sunburst Design.. endmodule ( q. packages have been imported into the $unit/$root space into the $unit/$root space (depending upon the simulator) (depending upon the simulator) © 2009. typedef bit rst_t. Sunburst Design.. clk.. typedef bit clk_t. endpackage package bit_pkg. Use the data_t and clk_t Use the data_t and clk_t from the data_pkg from the data_pkg Use the rst_t from Use the rst_t from the bit_pkg the bit_pkg . © 2009 29 of 59 Package Import in Design Element Header Mantis 329 SystemVerilog-2005 SystemVerilog-2005 package usage style #1 package usage style #1 Declare the data_pkg Declare the data_pkg and bit_pkg and bit_pkg bit_pkg::clk_t bit_pkg::clk_t not used not used package data_pkg... Inc.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design.. typedef logic clk_t. packages have been imported . somewhat verbose © 2009. d. d.1 . endpackage import data_pkg::*. Beaverton.. typedef logic [7:0] data_t. rst_n). somewhat verbose .. typedef bit rst_t. 15 of 30 Rev 1. Oregon. clk. endpackage module register ( output data_pkg::data_t input data_pkg::data_t input data_pkg::clk_t input bit_pkg::rst_t .. ...

input pkt_t d. Beaverton. typedef logic [2:0] src1_t.. data_t fld5. 16 of 30 Rev 1. typedef logic [15:0] data_t.. [2:0] dst1_t. dst2_t fld4. (output data_t q. typedef logic [2:0] src2_t. endpackage module register ( output pkt_t q. endpackage package bit_pkg. dst1_t fld2. input logic clk.. typedef logic [7:0] data_t. input logic rst_n). endpackage SystemVerilog-2009 adds import of SystemVerilog-2009 adds import of local package declarations in module. Sunburst Design. typedef logic [2:0] dst1_t. packages have been imported locally into the register module locally into the register module 32 of 59 Package Chaining . endmodule © 2009. local package declarations in module. typedef logic typedef logic typedef logic typedef struct src1_t fld1. .. import pkg2a::*. input rst_t rst_n). [7:0] data_t.. typedef bit clk_t.Export in a Package Mantis 1323 package pkg1. packages have been imported . . . Inc. re-declaration of src1_t and dst1_t was required and dst1_t was required import and use the import and use the expanded pkg2a package expanded pkg2a package © 2009. } pkt_t.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. typedef bit rst_t. data_t fld3. input clk_t clk. { package pkg2a.1 . input data_t d. Oregon. Inc. data_pkg::*... endpackage SystemVerilog-2005 did not permit SystemVerilog-2005 did not permit package nesting/import package nesting/import [2:0] src1_t. © 2009 31 of 59 Package Import in Design Element Header Mantis 329 package data_pkg. } pkt_t. typedef struct packed { src1_t fld1. re-declaration of src1_t If used. interface and program headers interface and program headers Declare the data_pkg Declare the data_pkg and bit_pkg and bit_pkg bit_pkg::clk_t bit_pkg::clk_t not used not used Packages are available Packages are available to the module header to the module header Use the data_t and clk_t Use the data_t and clk_t from the data_pkg from the data_pkg Use the rst_t from Use the rst_t from the bit_pkg the bit_pkg module register import bit_pkg::rst_t. typedef logic clk_t. endmodule If used. src2_t fld3.. dst1_t fld2. Sunburst Design. typedef logic [2:0] dst2_t.

with multiple inheritance !! inheritance !! 17 of 30 Rev 1.. and dst2_t types and dst2_t types dst2_t fld4.. .. typedef logic [2:0] src1_t. typedef struct { typedef logic [2:0] dst2_t. input logic clk. Sunburst Design. src1_t fld1.. . © 2009. and dst1_t types endpackage Override the data_t Override the data_t and pkt_t types and pkt_t types import and use the import and use the expanded pkg2 package expanded pkg2 package © 2009.. export pkg1::*. © 2009 33 of 59 Package Chaining . Inc. package pkg2.. import pkg3c::*. Add the src2_t Add the src2_t endpackage src2_t fld3. ... dst1_t fld2. Beaverton. endmodule 34 of 59 Multiple Package Export Mantis 1323 package pkg3a. export *::*. typedef logic [2:0] dst1_t... Mantis 1323 module register ( output pkt_t q. typedef logic [2:0] src2_t. typedef logic [7:0] byte_t.Export in a Package SystemVerilog-2009 allows SystemVerilog-2009 allows package nesting/import/export package nesting/import/export package pkg1. Inc. import/export the src1_t data_t fld5. Sunburst Design. Oregon. endpackage package pkg3c. import pkg2::*... extension . . import/export the src1_t and dst1_t types } pkt_t. endpackage package pkg3d. import pkg1::*. import pkg3d::*. endpackage export all packages export all packages (using wildcards) (using wildcards) Like doing package Like doing package extension . typedef logic [15:0] data_t..1 . endpackage package pkg3b... typedef logic [7:0] data_t.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. import pkg3b::*.. import pkg3a::byte_t. typedef struct packed { data_t fld3. with multiple . endpackage import each package import each package separately separately package pkg4... . src1_t fld1. input logic rst_n). . } pkt_t. dst1_t fld2. input pkt_t d.

im. input complex_s a. localparam DEPTH=1<<AWIDTH. Beaverton. function function complex_s add. return(sum).im = a.re. Sunburst Design. static function function package automatic complex.. .im + b. logic [DWIDTH-1:0] mem [DEPTH]. endfunction endpackage function complex_s add. typedef struct { logic [7:0] re. static ...re = a. input r_wn. always_latch if (!cs_n && !r_wn) mem[addr] <= data. input complex_s a.re. Sunburst Design. assign data = (!cs_n && r_wn) ? mem[addr] : 'z. typedef struct { logic [7:0] re.). } complex_s..1 . endfunction endpackage © 2009.. cs_n). package complex.. ram #(20. logic [7:0] im.. sum.re + b.. complex_s sum..16) ram1 (.. © 2009 35 of 59 Package Automatic Declarations Mantis 1524 SystemVerilog-2005 had: SystemVerilog-2005 had: • module automatic • module automatic • program automatic • program automatic • interface automatic • interface automatic SystemVerilog-2009 adds: SystemVerilog-2009 adds: • package automatic • package automatic Normal package . input [AWIDTH-1:0] addr.. Inc. logic [7:0] im.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. sum.im.. automatic function } complex_s. automatic package . b.re = a.re + b. 36 of 59 Localparams in ANSI-Style Headers Mantis 1134 localparam can be in localparam can be in the parameter port list the parameter port list `timescale 1ns / 1ns module ram #(parameter AWIDTH=10. automatic . . sum.im = a. Normal package .. return(sum). Inc. 18 of 30 Rev 1.. sum. parameter DWIDTH=8) (inout [DWIDTH-1:0] data.. endmodule Cannot override localparam Cannot override localparam Ordered parameter replacement Ordered parameter replacement omits the localparam value omits the localparam value DEPTH not DEPTH not listed listed ram instantiation: ram instantiation: AWIDTH=20 (1MB) AWIDTH=20 (1MB) DWIDTH=16 DWIDTH=16 © 2009.. Oregon.im + b. b... complex_s sum. automatic package .

.. More config parameter More config parameter capabilities have been added capabilities have been added (not shown) (not shown) File: lib. . register #(.map File: lib.map library tbLib tb/*. © 2009 37 of 59 Blank And Illegal Parameter Defaults Mantis 907 NOTE: SIZE parameter not NOTE: SIZE parameter not assigned aadefault value assigned default value module register #(SIZE) ( output logic [SIZE-1:0] q. else q <= d. negedge rst_n) if (!rst_n) q <= '0. input logic clk. parameter SZ = 12. .sv. instance tb use (. Oregon.. q. 19 of 30 Rev 1. p2..SIZE(WIDTH)) r[1:3] (. input logic clk). Beaverton.clk(clk)).p1}). library rtlLib rtl/*. endmodule module register #(SIZE=8) ( output logic [SIZE-1:0] q. clk. endconfig Parameter values Parameter values before config before config SZ SZ =12 =12 WIDTH=12 (default 4) WIDTH=12 (default 4) SIZE =12 (default 8) SIZE =12 (default 8) Parameter values Parameter values after rtl config after rtl config SZ SZ =16 =16 WIDTH=16 WIDTH=16 SIZE =16 SIZE =16 module pipeline #(WIDTH=4) ( output logic [WIDTH-1:0] q. always_ff @(posedge clk. logic [WIDTH-1:0] p1. rst_n. default liblist rtlLib. //.d}). endmodule © 2009. pipeline #(. Sunburst Design. endmodule © 2009. Inc.d({p2. design tbLib. . 38 of 59 Setting Parameters in Configurations Mantis 2037 module tb. register #(SIZE) r1 (.tb.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design.*). input logic [WIDTH-1:0] d. input logic [SIZE-1:0] d. . input logic clk).1 . d.*). input logic [SIZE-1:0] d..cfg config rtl. endmodule File: rtl. always_ff @(posedge clk) q <= d.SZ(16)). endmodule module tb.sv. Inc.p1.p2. Sunburst Design.cfg File: rtl.. rst_n). parameter SIZE = logic [SIZE-1:0] logic [SIZE-1:0] logic Parameter must be Parameter must be defined when the defined when the module is instantiated module is instantiated 64.q({q.WIDTH(SZ)) p1 (.

. © 2009 39 of 59 Verilog-95 Macro Capabilities `define CYCLE 100 .. initial begin clk <= '0.1 . Inc. clk2). 40 of 59 Macros with Default Arguments Mantis 1571 • SystemVerilog-2009 permits macros to have arguments with default values By default. ) (not all Verilog coders know this) (every Verilog coder knows this style) (every Verilog coder knows this style) Define and use aamacro Define and use macro Pass an argument to Pass an argument to the macro arg the macro arg Define aamulti-line macro Define multi-line macro with input arguments with input arguments (not all Verilog coders know this) (not all Verilog coders know this) `define assert_clk( arg ) \ assert property (@(posedge clk) disable iff (!rst_n) arg ) © 2009. macro uses clk for assertion sampling for assertion sampling `define assert_clk(arg. Oregon. Beaverton. Sunburst Design. ) \ assert property (@(posedge clk) disable iff (!rst_n) .. macro uses clk By default. ck=clk) \ assert property (@(posedge ck) disable iff (!rst_n) arg) ERROR_q_did_not_follow_d: `assert_clk(q==$past(d)).... end Line continuation Line continuation character \ character \ Define aamulti-line macro Define multi-line macro (not all Verilog coders know this) `define assert_clk( . Sunburst Design. Use default clk Use default clk Use clk2 Use clk2 20 of 30 Rev 1. © 2009. Inc. ERROR_q_did_not_follow_d: `assert_clk(q==$past(d).DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. forever #(`CYCLE/2) clk = ~clk.

Inc. end endmodule `undefineall `define data size. input [`ASIZE-1:0] addr. Beaverton.1 .DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. `undef address size `undef address size `undef memory depth `undef memory depth 42 of 59 `undefineall Mantis 1090 `define DSIZE 8 `define ASIZE 10 `define MDEPTH 1024 module ram1 ( inout [`DSIZE-1:0] data. `undef data size. end endmodule `undef DSIZE `undef ASIZE `undef MDEPTH © 2009. assign data = (rw_n && en) ? mem[addr] : {`DSIZE{1'bz}}. © 2009 41 of 59 Verilog `define & `undef `define DSIZE 8 `define ASIZE 10 `define MDEPTH 1024 module ram1 ( inout [`DSIZE-1:0] data. `define address size `define address size `define memory depth `define memory depth `undefineall un-defines `undefineall un-defines all `define macros all `define macros © 2009. logic [`DSIZE-1:0] mem [0:`MEM_DEPTH-1]. rw_n). assign data = (rw_n && en) ? mem[addr] : {`DSIZE{1'bz}}. rw_n). always @* begin if (!rw_n && en) mem[addr] <= data. always_latch begin if (!rw_n && en) mem[addr] <= data. Inc. 21 of 30 Rev 1. `define address size `define address size `define memory depth `define memory depth `undef data size. `define data size. `define data size. logic [`DSIZE-1:0] mem [0:`MEM_DEPTH-1]. Sunburst Design. input en. Oregon. input [`ASIZE-1:0] addr. input en. Sunburst Design. `define data size.

end endmodule Make the memory depth Make the memory depth aalocalparam localparam Calculate the memory depth Calculate the memory depth from the address size from the address size © 2009. local to the module local to the module module ram1 #(parameter ASIZE=10. input [ASIZE-1:0] addr. always_latch begin if (!rw_n && en) mem[addr] <= data. DSIZE=8) (inout [DSIZE-1:0] data.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design.1 . Oregon. input en. Beaverton. 22 of 30 Rev 1. assign data = (rw_n && en) ? mem[addr] : {DSIZE{1'bz}}. logic [DSIZE-1:0] mem [0:MEM_DEPTH-1]. © 2009 43 of 59 SystemVerilog Parameterized Model A Better Solution Consider this: Consider this: If you are using `undefineall If you are using `undefineall it looks like aalocal constant it looks like local constant Declare parameters. localparam MEM_DEPTH = 1<<ASIZE. Guideline: choose parameter first Guideline: choose parameter first Guideline: choose `define only if needed Guideline: choose `define only if needed 44 of 59 SystemVerilog-2009 Arrays & Queues Enhancements © 2009. Inc. Inc. Sunburst Design. Declare parameters. rw_n). Sunburst Design.

. Oregon. aa_display. endfunction foreach stores each aa[] index in the i variable foreach stores each aa[] index in the i variable 46 of 59 Associative Array Clarifications Mantis 1723 • SystemVerilog 2005 array types & methods – Dynamic arrays: . 1 ARRAY ELEMENTS aa[1234]=aa 9 ARRAY ELEMENTS aa[ 0]=cc aa[ 1]=cc aa[ 2]=cc aa[ 3]=cc aa[ 4]=cc aa[ 5]=cc aa[ 6]=cc aa[ 7]=cc aa[1234]=aa 12 ARRAY ELEMENTS aa[ 0]=cc aa[ 1]=cc aa[ 2]=cc aa[ 3]=cc aa[ 4]=cc aa[ 5]=dd aa[ 6]=cc aa[ 7]=cc aa[ 10]=dd aa[ 15]=dd aa[ 20]=dd aa[1234]=aa module aa2. aa. endfunction © 2009. $display("%0d ARRAY ELEMENTS %0d".. i. aa.size() method – Queues: . . initial begin aa[2143] = 8'hAA.size() method . Sunburst Design.num() method Returns the size of Returns the size of the dynamic array the dynamic array Returns the size of Returns the size of the queue the queue Returns the number of Returns the number of elements in the elements in the associative array associative array function void aa_display. end endmodule SV2009 clarifies SV2009 clarifies foreach fails with foreach fails with [*] assoc arrays [*] assoc arrays © 2009.. . function void aa_display.. Sunburst Design. © 2009 45 of 59 Associative Array Clarifications Mantis 1457 foreach command works with foreach command works with non-[*] associative arrays non-[*] associative arrays byte_t aa [*]. $display("%0d ARRAY ELEMENTS %0d".size()). i+=5) aa[i]=8'hDD. Inc. i<8. typedef bit [7:0] byte_t. endfunction function void aa_display.size() method – Asosciative arrays: . Beaverton. foreach (aa[i]) $display("aa[%4d]=%2". Inc. aa_display. aa[i]).size() method synonym for synonym for . i<21. i++) aa[i]=8'hCC.num()). aa_display.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design.num() method .num() method 23 of 30 Rev 1. byte_t aa [int]. for (int i=5.num()). for (int i=0. SV2009 defines SV2009 defines . $display("%0d ARRAY ELEMENTS %0d". aa..1 .

Sunburst Design. insert(@2) insert(@2) delete(@1) delete(@1) data=8'hA0 data=8'hA2 push_front push_front push_back push_back New to SV2009 New to SV2009 delete entire queue delete entire queue 48 of 59 SystemVerilog-2009 Classes & Verification Enhancements © 2009.push_back(8'hcc). q. q.pop_front().size=%0d".push_front(8'hbb).DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. $display $display Initial Initial values values data=8'h00 8'hA0 8'hA1 8'hA2 8'hA0 8'hA1 8'hFF 8'hA2 8'hA0 8'hFF 8'hA2 8'hFF 8'hA2 8'hFF 8'hBB 8'hFF 8'hBB 8'hFF 8'hCC <empty> q.size()). 8'hA2}.delete(1). q. Beaverton. Sunburst Design.1 . q.size=3 initial begin $display("q.8'hff).pop_back(). pop_front pop_front data=q. Inc. 24 of 30 Rev 1.insert(2. bit [7:0] data. Inc.delete() end endprogram No argument No argument means to delete means to delete entire queue entire queue © 2009. data=q. © 2009 47 of 59 Queue Delete Mantis 1560 SV2009 adds aabuilt-in method SV2009 adds built-in method to delete an entire queue to delete an entire queue program q_methods. Oregon. int q_size. bit [7:0] q[$] = '{8'hA0. pop_back pop_back q. q. 8'hA1.

j<3. $write("%3d". Oregon. Inc.static keyword is optional initialization happens before time 00 initialization happens before time automatic variable automatic variable assignment executes each assignment executes each time the outer loop is called time the outer loop is called Display values Display values 1 2 3 1 2 3 1 2 3 The static variable The static variable assignment executes assignment executes once before time 00 once before time Display values Display values 1 2 3 4 5 6 7 8 9 50 of 59 Pure Virtual Methods Mantis 1308 • pure virtual is an abstract method prototype defined in an abstract class (virtual class) virtual requires virtual requires • virtual requires: argument compatibility argument compatibility – – – – argument types must match argument directions must match number of arguments must match return types must match pure creates aaplace-holder pure creates place-holder pure requires that aa pure requires that method be overridden with method be overridden with an actual implementation an actual implementation • pure requires: – – – – method shall only be a prototype no code can be included for the prototype not even allowed to have endfunction/endtask keywords pure virtual methods MUST be overridden in non-abstract classes © 2009. Sunburst Design. 25 of 30 Rev 1. for (int j=0. j<3. i++) begin automatic int loop3 = 0. j++) begin loop3++. initial begin for (int i=0. loop2).DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. end end $display("\n"). Sunburst Design. © 2009 49 of 59 Static Variable In-Line Initialization Mantis 1556 module top. j++) begin loop2++. int svar1 = 1. end endmodule © 2009. end end $display("\n"). Inc. Beaverton. loop3).1 . for (int i=0. i++) begin static int loop2 = 0. $write("%3d". i<3. i<3. for (int j=0. static keyword is optional .

6). Sunburst Design. Sunburst Design. $time. time (3+3+4=10ns) time (3+3+4=10ns) join_none $display("%t: Initial Sequence started". fork b <= 8'hcc. – Every pure constraint MUST be overridden in non-abstract classes Again: pure creates aaplace-holder Again: pure creates place-holder pure requires that aa pure requires that constraint be overridden constraint be overridden with an actual constraint with an actual constraint © 2009. #4 $display("RUN(%t): a=%2h".DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design."ns". initial startup.b=cc 2ns: 3rd Sequence started RUN( 10ns): a=88 task run. #3 a=8'h88. 0ns: Initial Sequence started 1ns: 2nd Sequence started .1 . Oregon. © 2009 51 of 59 Pure Constraint Mantis 2514 • pure constraint is an constraint prototype defined in an abstract class (virtual class) • pure requires: – constraint shall only be a prototype pure constraint constraint-name. task call that consumes task call that consumes #2 $display("%t: 3rd Sequence started". #3 run. #1 $display("%t: 2nd Sequence started . int a. $time). endfunction Nonblocking assignment legal Nonblocking assignment legal in function when surrounded in function when surrounded by fork / /join_none by fork join_none endmodule Output display Output display © 2009. 52 of 59 Allow Functions to Spawn Processes Mantis 1336 fork / /join_none allows fork join_none allows module forkprocess. a). int b. b). Inc.b=%2h". initial $timeformat(-9. Beaverton. $time). Inc.0. $time. functions to spawn off functions to spawn off time-consuming code time-consuming code time-1 time-1 time-2 time-2 time-0 time-0 function void startup. endtask 26 of 30 Rev 1.

Sunburst Design. Inc. type T = int).sample(a. endfunction Fixed method Fixed method return type return type SystemVerilog-2005 does not SystemVerilog-2005 does not allow aaclass type to use both allow class type to use both parameters and external methods parameters and external methods Output display Output display 2 initial $display("%0d %0d". Beaverton.1 . @(posedge clk)(a. C#()::f(). ififc is high ##1 cycle later. C#()::f(). int x). extern static function T f()... Oregon.C#(5)::f())... endfunction SystemVerilog-2009 adds the SystemVerilog-2009 adds the ability to have parameterized ability to have parameterized classes with external methods classes with external methods Declaration of Declaration of extern static function (method) extern static function (method) with return type T (parameterized type) with return type T (parameterized type) initial $display(“%0d %0d”. c is high ##1 cycle later. cg1. return p + p. set covergroup cg1 (p_cg and pass the local variable x=b .. a. cross x.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. © 2009. 10 class C #(int p = 1. © 2009 53 of 59 External Methods w/ Parameterized Classes Mantis 1857 class C #(int p = 1). endproperty c1: cover property (p1). Sunburst Design. set covergroup cg1 (p_cg) )and pass the p_cg cg1 = new.. return p + C::p. endclass function C::T C::f(). int x.C#(5)::f()). When a is high. coverpoint x. endclass function int C::f(). 54 of 59 Covergroup Sample Method w/ Arguments Mantis 2149 covergroup with sample covergroup with sample arguments a and x arguments a and x covergroup p_cg with function sample(bit a. endgroup . x))... 27 of 30 Rev 1. © 2009. sampled a and x values to the covergroup property p1. Inc. x = b) ##1 (c. sample the . extern static function int f(). sampled a and x values to the covergroup local variable x=b . sample the When a is high.

. endmodule module blka (. endmodule module blka (.. always_ff @(posedge clk) q <= #1 d..). timeunit 100ps/100ps.. endmodule 1ns/1ns 1ns/1ns timescale timescale again active again active 28 of 30 Rev 1.). Inc. input logic [7:0] d. endmodule © 2009... endmodule module register ( output logic [7:0] q. input logic clk).. Sunburst Design. Oregon.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. .. Sunburst Design. 2-line syntax 2-line syntax SystemVerilog-2009 SystemVerilog-2009 1ns/1ns 1ns/1ns timescale timescale active active `timescale 1ns/1ns module tb.. Beaverton. . Inc...1 .. timeunit 100ps. 56 of 59 New Concise timeunit Syntax Mantis 1623 SystemVerilog-2005 SystemVerilog-2005 `timescale 1ns/1ns module tb. input logic clk). Combined 1-line syntax Combined 1-line syntax Must be placed Must be placed immediately after immediately after module header module header 100ps/100ps 100ps/100ps local timescale local timescale always_ff @(posedge clk) q <= #1 d.. endmodule module register ( output logic [7:0] q. . © 2009 55 of 59 SystemVerilog-2009 Miscellaneous Enhancements timeunit $system task `__FILE__ & `__LINE__ Macros SDF Annotation of $timeskew & $fullskew © 2009. timeprecision 100ps. input logic [7:0] d.

Inc.v"). 58 of 59 `__FILE__ & `__LINE__ Macros Mantis 1588 • SystemVerilog-2009 adds the C-like macros ‘__FILE__ ‘__LINE__ • These macros allow access to the current file and line number from within SystemVerilog code © 2009. Oregon. endmodule Most Verilog simulators already Most Verilog simulators already have this task. but ititwas never have this task. but was never part of the Verilog standard part of the Verilog standard © 2009. 29 of 30 Rev 1. Inc.1 . © 2009 57 of 59 $system Task to Invoke SystemCommands Mantis 1863 • The $system task allows SystemVerilog code to call operating system commands module top. Sunburst Design.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design.v adder. Beaverton. Sunburst Design. initial $system("mv design.

com www. Inc.com www. © 2009 59 of 59 SDF Annotation of $timeskew & $fullskew Mantis 1140 • Verilog-2001 added the timing skew checks $timeskew $fullskew • SystemVerilog-2009 defines how these checks are annotated from SDF files © 2009. Inc. Cummings Sunburst Design.sunburst-design.sutherland-hdl. Beaverton. Sunburst Design.1 . cliffc@sunburst-design.com Stuart Sutherland Sutherland HDL. stuart@sutherland-hdl.com sponsored by © 2009.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. Inc. Sunburst Design. Oregon. 30 of 30 Rev 1. Inc. 60 of 59 SystemVerilog Is Getting Even Better! An Update on the Proposed 2009 SystemVerilog Standard Part 1 Presented by Clifford E.

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