ECE/CS 5720/6720

ECE/CS 5720/6720 – Analog IC Design Tutorial for Cadence –Layout, DRC, LVS & Layout Simulation
In this tutorial you’ll build an inverter in two different ways: as a schematic and as layout. You know how to simulate the inverter using an analog simulator. After you design and simulate the schematic, you will design layout for an inverter and simulate a circuit extracted directly from the layout. You will be able to compare the two simulations and see how they differ. You will also check the layout for design rules, and check that the layout matches the schematic. Layout consists of the mask designs for each layer that gets sent to the chip fabrication service.

Draw the Schematic of an Inverter in Virtuoso Schematic Editor and make a symbol. Transistor Sizes: (W/L)p = 3.0/0.6 and (W/L)n = 1.5/0.6 (All in microns). Body of pMOS is connected to Vdd and that of the nMOS is connected to Vss.


ECE/CS 5720/6720

Schematic test bench for the inverter: Make a new schematic cell “inverter_test” to test the inverter you designed, as shown below:

Input: voltage pulse of 1MHz (V1 = 0V, V2 = 5V) Vdd: 5 V Vss: 0 V Run a transient analysis for 2µs and make sure your output looks okay.

Drawing the layout of a CMOS Inverter.
In this phase of the tutorial you’ll draw the layout for an inverter in the Virtuoso tool. You’ll check for design rule violations, and check that the extracted layout is the same circuit as the schematic. You’ll then simulate the circuit extracted from the layout and compare it with a simulation of the schematic you just drew. In library manager, click File → New → Cell View. Select the library and the cell in which you made the inverter schematic. Now, select Tool as Virtuoso. This would also set your View Name to layout. Click OK.


Note: Before we start with the layout. The Virtuoso Editing window where the layout will be drawn and the LSW (Layer Select Window). you will see this window: Set the Minor spacing. Major spacing. Click Apply and then OK. 3 . etc) to draw. X Snap Spacing and Y Snap Spacing as shown. Click on Options → Display. polysilicon.ECE/CS 5720/6720 This will open two windows. the display should be set as follows to facilitate layout for the current design rules. metal2. metal1. where you select the layers (diffusion.

Remember that our N-transistor in the inverter schematic had a W/L of 1.6µm 4 . Use the stretch command (by pressing s) and stretch the diffusion layer to be of the size 1. You can click on one of the corners of the green rectangle to place the ruler and measure the sides (Typing K will clear all rulers). (The width of the diffusion will be usually the same as the width of the transistors but the length of diffusion region has to account for the source/drain diffusions and the gate length.type Transistor 1) Click on the active (green) layer in the LSW window. press r to activate the Rectangle command.5µm/0.6µm. In the Virtuoso Layout Editor window.5µm x 3.ECE/CS 5720/6720 (a) To draw the layout of a N. Press k to activate the Ruler command. A general rule of the thumb is to have the length of the diffusion region to be 3µm + Gate length). Now you can draw a rectangle by selecting the start and end points of the rectangle.

6µm size to be overlapped by diffusion by (at least) 0.6µm x 0.ECE/CS 5720/6720 2) Draw contacts (black colored layer cc) of 0.3µm on the outside edges. 3) Now draw the gate of the transistor by selecting poly (red in color) in the LSW window.3µm on all sides. 5 .6µm. Also draw Metal 1 layer (blue colored layer metal1) to overlap the contacts by 0. as shown below. Note that the poly layer should have an overhang of 0.

ECE/CS 5720/6720 4) Now we have to surround the active region with nselect to make it n-type diffusion.6µm as shown below: 6 . Select nselect (green outline) in the LSW and wrap it around the active rectangle such that it extends beyond the active region by 0.

Note that we have not connected the body of this device to Vss (the substrate) (b) To draw the layout of a P-Type Transistor Draw the P. or rather addition.ECE/CS 5720/6720 Your NMOS transistor of W/L = 1.type transistor (W/L = 3µm/0.6µm) similarly. 7 . The only difference (apart from the sizes) would be to use pselect instead of nselect so that we get p type diffusion.5/0. The other change.6 microns is done. would be put this entire device in n-well.

8 . 9) Now. place n-well around this entire device so that it extends beyond the diffusion by 1. In step 4.8µm in all directions.ECE/CS 5720/6720 (5-8) Draw a transistor similar to the N transistor for the increased width of 3µm following steps 1 to 3. use pselect (orange outline) instead of nselect.

10) Select the entire N-transistor and place it exactly below the P transistor such that there is a gap of at least 1.8µm between the n-well and the diffusion of the N transistor. Again. your PMOS transistor is also ready. 9 . we have not yet connected the body of this device (the n-well) to Vdd.ECE/CS 5720/6720 Now. We are now set to put together these two devices to make an inverter.

ECE/CS 5720/6720 11) Join the gates of the P and the N transistor as well the drains of the two transistors by stretching the poly and metal1 respectively. 10 .

ECE/CS 5720/6720 12) Draw the supply lines for Vdd and Vss using Metal 1. such that the inverter is sandwiched between the two supply lines. They are made wide to avoid electro-migration issues 11 . The line below the NMOS will be our Vss and that above PMOS will be our Vdd.

Metal1 and poly should surround the contact by 0. which is out input by placing a layer of metal1. Make sure that the metal1 strips. are at least 0.9µm away.3µm. 12 .ECE/CS 5720/6720 and ohmic voltage drops. I made them 4. connect the sources of the two transistors to Vdd and Vss respectively. 13) Now. Also create a contact on the common gate.8µm wide. cc and poly as shown in the figure. one connecting the drains and other carrying the supply voltage.

To do this. 13 . click on Create → Pin.ECE/CS 5720/6720 14) Now label the different nodes on our layout that matches those on your schematic..

vdd (input pins) and out (output pin). vss. b) Use the same node names as used in your schematic for the inverter 14 . The nodes for the inverter would be in.ECE/CS 5720/6720 You get the following window: Enter the Terminal Name. all the pins are of metal1 type. Select Display Pin Name. Select I/O type and Pin type. Note: a) For this layout.

ECE/CS 5720/6720 Your layout now looks like this: We are to connect the bodies of the two transistors now (i. connect the n-well to Vdd) 15) Body contact for NMOS: 15 .e. for the NMOS. connect the substrate to Vss and for the PMOS.

P type diffusion (active surrounded by pselect) with a contact is shown below. 16) Next.2µm).2µm x 1.6µm x 0. It consists of an active (1. This metal1 has to be tied to the Vss line.ECE/CS 5720/6720 We need to put a P-type diffusion in the substrate and tie this to ground. The contact has to be surrounded by metal1. surrounded by pselect and a contact of 0. we need to tie the body of the PMOS transistor to Vdd.6µm in the middle. 16 .

17) You have made it! 17 . The n-well has to surround the active by 1. just that it is n-type diffusion(active surrounded by nselect) inside the n-well. This is shown in the figure below: The metal1 here is tied to Vdd.8µm.ECE/CS 5720/6720 A PMOS body contact looks similar.

Anyway.ECE/CS 5720/6720 The layout of the inverter is now complete. Your final layout may look like this: Before proceeding to the next step. All dimensions used in this example have been taken from the Design rules file posted on the class web site. save the layout. we will ask Cadence to do this check for us at a later stage. It might be a good exercise to trace the different nodes and make sure it is exactly identical to the inverter on your schematic. 18 .

You must do this repeatedly until you have no errors in your layout. Check the CIW window for any errors. choose Verify → DRC… A new window pops up as shown below. Now you can easily edit your layout and correct all your errors. you can go through all the error markers and their descriptions. In the new window. If you have followed the design rules correctly. the erroneous parts will blink. Once you find out the errors in your layout.ECE/CS 5720/6720 Design Rules Check Next check whether any of the design rules have been violated. It should say: UofU_TechLib_ami06.rul is entered and also that the Rules Library is checked. If some errors manage to creep into your layout. you should get ‘0 errors’ in the CIW window. In the Virtuoso Layout Editor Window. 19 . notice divaDRC. click the button corresponding to Zoom To Markers. Click OK to start the Design Rule Check. By pressing the Next button. In the Rules file field. You can find out the details of the errors you made by selecting Verify → Markers → Find. delete all markers by choosing Verify → Markers → Delete All….

Press Ok to extract your layout. A window should pop up and tell you that the netlists matched. You can verify this in the Library Manager. (This might take a minute… be patient. layout.rul and the rules library is checked. and symbol) of the cell inverter by the name extracted is created. Click the Run button to run LVS. To do this. choose Verify → LVS… in your Virtuoso Layout Editor Window.ECE/CS 5720/6720 Extracting the Layout Extract your layout by choosing Verify → Extract. It may also fail if some schematics or layouts haven’t been updated. Layout Versus Schematic Check Finally we compare our layout with the schematic that we made earlier to see if they are both the same. check the log 20 . In the new Extractor window notice that the rules file divaEXT. Check that the correct cells and views have been selected. Another view (like schematic. If you still have problems.) If the window says failed instead of succeeded. so make sure everything has been saved and checked. the LVS window may be incorrectly filled in.

but the names didn’t. Check the output of the LVS. It only means that the process completed! In order to see if the circuits match you need to check the output of LVS. 21 . by clicking the Output button in the LVS Window. Click OK in the next window. For performing Post layout simulation. that doesn’t mean the circuits match.log) Note that even if it says it succeeded. If you have done your layout right. It is called “si. This view can be created by pressing the Build Analog button in the LVS window. Check the class web page for a sample LVS output file. A new window containing some text should pop up. it will tell you that the circuits matched. If you didn’t use exactly the same names for the input and output in the schematic and in the layout. the text file should read "The netlists match". If they don’t match you can tell from the text what the problems were. an analog_extracted view for the inverter is required.ECE/CS 5720/6720 file for hints.log” and is found in the LVS directory (ex: IC_CAD\cadence\LVS\si. for example.

The reason for having two inverters in the schematic is to compare the output of the "schematic inverter" and that of a "layout inverter".ECE/CS 5720/6720 Post Layout Simulation of a CMOS inverter. To do this. Open the inverter_test schematic from the Library Manager. There are some parasitics extracted from the layout. The last few sentences preceding this explained how to get an analog_extracted view. we need to make a small modification in the schematic. it is possible to select simulation models for different instances in the top-level schematic. Check and save the schematic. a config view of inverter_test should be created. This testbench can also be used for the post-layout simulation. In the config view. which was not accounted for when we simulated the schematic. a testbench schematic for the inverter called inverter_test was created. Copy the inverter symbol and connect the copied instance to a new output called out_layout. In the previous schematic simulation. But before creating a config view. 22 . Make sure you have the analog_extracted view for your inverter.

In the one titled New Configuration. 23 . choose File → New → Cell View Choose the view name to be config. The tool Hierarchy-Editor should be automatically selected in the Tool pull-down menu.ECE/CS 5720/6720 In Library Manager. Two windows open up. click Use Template and choose spectreS in the new window and click OK. Replace myView with schematic and click OK in the New Configuration window.

information about the different instances in the inverter_test schematic view can now be seen. 24 .ECE/CS 5720/6720 In the Hierarchy Editor window. You can see that two inverters each having a unique instance number is found. In the design above the instance numbers for the inverters are I0 and I1. Select View → Tree in Hierarchy editor window.

To change the simulation model (in this case for inverter I1). right click on the instance in the config view and choose: Set Instance View → analog_extracted.ECE/CS 5720/6720 Now the simulation model for the inverter connected to the output out_layout should be changed to analog_extracted. The simulation model for the other inverter does not have to be changed since the default simulation view is schematic. 25 . Remember the analog_extracted view was created after performing the LVS of the layout. Save the configuration by clicking View → Update and then File → Save.

Note that Analog Environment does not automatically use the settings made in the config view. click NO.ECE/CS 5720/6720 From the schematic view. The simulation is now performed in the same way as the previous schematic simulation. 26 . Choose Setup → Design in the Analog Environment window and change the view from schematic to config for the inverter_test simulation and press OK If the question whether to save the current state pops up. open Analog Circuit Design Environment. Choose both the outputs out_schematic and out_layout to be plotted.

there are not much different.ECE/CS 5720/6720 From the simulation above. Now if you zoom in to one of the edges of the output waveform. That winds up this tutorial. DRC. 27 . but you will realize it will become easy after some practice. It may look confusing for students doing this stuff for the first time. Anyway. you can see that the layout produces a slightly slower inverter than that of the schematic simulation. To view the difference between the schematic simulation model and the analog_extracted simulation model. it can be seen that the inverter layout seems to be working properly. LVS and Analog extraction of the layout. first drag and drop one of the output waveforms over the other. You have gotten started with layout.

Sign up to vote on this title
UsefulNot useful