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PONDICHERRY ENGINEERING COLLEGE
B.Tech (EIE) –SEVENTH SEMESTER Seminar report on
Submitted to Pondicherry university Puducherry
Abstract Introduction Challenges faced Attaining these goals Developing techniques Improved characteristics Reconfiguring the architecture Reconfigurable computing Reconfigurable processor Reconfigurable chips Reconfigurable hardware Advantages of reconfigurability Currently available processors Multifunction implementation RCP architecture Development environment Present development environment Problems overcome by RCP platform Architecture components Reconfigurable processing fabric Programmable I/O Technologies used in chip Design process Comparison with other technologies Advantages Disadvantages Applications Conclusion Futuristic dream References
instead. Now using field programmed chips we have chips that can be rewired in an instant. It is a fusion between custom integrated circuits and programmable logic. An FPGA is covered with a grid of wires. such as crunching spreadsheets or editing digital photos Disadv: For any one application. At each crossover. could do almost anything. much of the chip's circuitry isn't needed. are developing techniques to rewire FPGA-like chips anytime--and even software that can map out circuitry that's optimized for specific problems. Japan.ABSTRACT Chameleon chips are chips whose circuitry can be tailored specifically for the problem at hand. The chips still won't change colors. Suppose. Thus the benefits of customization can be brought to the mass market. . even changing into a wireless phone. That's why you don't need separate computers for different jobs.In the case when we are doing highly performance oriented tasks custom chips that do one or two things spectacularly rather than lot of things averagely is used. little bigger than a credit card. Chameleon chips would be an extension of what can already be done with field-programmable gate arrays (FPGAS). labs in Europe. So computer scientists are hatching a novel concept that could increase numbercrunching power--and trim costs as well. there's a switch that can be semipermanently opened or closed by sending it a special signal. The market for such versatile marvels would be huge. and the U. and the presence of those "wasted" circuits slows things down. when you loaded a tax-preparation program. computer-aided design--and then rewired. One set of chips. that the chip's circuits could be tailored specifically for the problem at hand--say. Usually the chip must first be inserted in a little box that sends the programming signals. But they may well color the way we use computers in years to come.S. Adv: One chip can run a range of programs. on the fly. INTRODUCTION Today's microprocessors sport a general-purpose design which has its own advantages and disadvantages. and would translate into lower costs for users. But now. Call it the chameleon chip.
result . "That kind of chameleon device would be the killer app of reconfigurable computing" These experts predict that in the next couple of years reconfigurable systems will be used in cell phones to handle things like changes in telecommunications systems or standards as users travel between calling regions -. Fortunately. are developing techniques to rewire FPGA-like chips anytime--and even software that can map out circuitry that's optimized for specific problems. and the U. and ٭be brought to the market quicker than ever. Now using field programmed chips we have chips that can be rewired in an instant. the elaborate circuitry used in microprocessors. the chips will need to completely reconfigure themselves in a millisecond or less. the hat trick is generally unachievable with traditional design and implementation techniques. some new techniques are emerging from the study of reconfigurable computing that make it possible to design systems that satisfy all three requirements simultaneously. or etch.S. To be quick enough for personal information devices. IMPROVED CHARACTERISTICS In the case when we are doing highly performance oriented tasks custom chips that do one or two things spectacularly rather than lot of things averagely is used. labs in Europe. sometime in the next 10 to 15 years.CHALLENGES FACED Designers of multimedia systems face three significant challenges in today's ultracompetitive marketplace: ٭Our products must do more.or between countries. Thus the benefits of customization can be brought to the mass market. ٭cost less. As it is getting more expensive and difficult to pattern. many experts have predicted that maintaining the current rate of putting more circuits into ever smaller spaces will. ATTAINING THESE GOALS Though each of these goals is individually attainable. Japan. DEVELOPING TECHNIQUES But now.
which would demand a nearly impossible level of precision in fabricating circuitry But reconfigurable chips don't need that type of precision and we can make computers that function at the nanoscale level RECONFIGURING THE ARCHITECTURE Some of the new configurable DSP architectures are reconfigurable too—that is. Plus. (The densest of the current FPGAs have approximately 100. Proponents of such chips are proclaiming an era of "chip-on-demand.000 reprogrammable logic gates. developers can modify their landscape on the fly. Thus. A reconfigurable communications processor (RCP) can reconfigured for different processing algorithms in one clock cycle. This eliminates the cumbersome job of fitting the latest algorithms and protocols into existing rigid hardware. the company is dropping the term reconfigurability for the new architecture and going with a more traditional name.in features on microchips no bigger than a few atoms. the supplier is preparing a new. Additionally. it will be implemented in a 0. but these chips have only recently reached gate densities making them suitable for high-end applications. RECONFIGURABLE COMPUTING: History: Although originally proposed in the late 1960s by a researcher at UCLA. it will be substantially altered. depending on the incoming data stream. Reprogrammable logic chips like field programmable gate arrays (FPGAs) have been around for many years. This capability permits dynamic reconfigurability of the architecture as demanded by the application." wherein new algorithms can be accommodated on-chip in real time via software. Chameleon designers are revising the architecture to create a chip that can address a much broader range of applications. more user-friendly suite of tools for traditional DSP designers. the company says. reconfigurable computing is a relatively new field of study. Unlike the older RCP. Present developments: The decades-long delay had mostly to do with a lack of acceptable reconfigurable hardware. and it will support a much higher clock rate. the streaming data processor (SDP).13-µm CMOS process to meet the signal processing needs of a much broader market.) With an anticipated doubling of gate . Though the SDP will include a reconfigurable processing fabric. the new chip won't have the ARM RISC core.
System designers use FPGAs in many different ways. cost less. the design of the hardware may change in response to the demands placed upon the system while it is running. which works especially well when there are parts of the hardware that are occasionally idle. This use of FPGAs has nothing to do with reconfigurable computing. . Advantages: Reconfigurable computing has several advantages. In this scenario. reconfigurable computing goes one step further. the FPGA acts as an execution engine for a variety of different hardware functions — some executing in parallel. the FPGA is present only on the prototype hardware and is replaced by the corresponding ASIC in the final production system. It is not only possible but relatively commonplace to "rewrite" the silicon so that it can perform new functions in a split second. though just one a time. Unfortunately. Reconfigurable computing allows system designers to execute more hardware than they have gates to fit. Explanation: Reconfigurable computing goes a step beyond programmable chips in the matter of flexibility. the situation will only become more favorable from this point forward. you can redesign the internal logic of the FPGA and send the enhancement to the affected customers by email. hardware bug fixes and upgrades can be administered as easily as their software counterparts. The most common use of an FPGA is for prototyping the design of an ASIC. the hardware is automatically reconfigured. and have shorter design and implementation cycles. However. Reconfigurable computing involves manipulation of the logic within the FPGA at run-time. Once they’ve downloaded the new logic design to the system and restarted it. which has many advantages. One theoretical application is a smart cellular phone that supports multiple communication and data protocols. When the phone passes from a geographic region that is served by one protocol into a region that is served by another.densities every 18 months. The logic within the FPGA can be changed if or when it is necessary. and using this approach it is possible to design systems that do more. others in serial — much as a CPU acts as an execution engine for a variety of software threads. Here. that doesn’t qualify the term precisely enough. This is reconfigurable computing at its best. We might even go so far as to call the FPGA a reconfigurable processing unit (RPU). many system designers are choosing to leave the FPGAs as part of the production hardware. they’ll be able to use the new version of the protocol. For example. In order to support a new version of a network protocol. When we talk about reconfigurable computing we’re usually talking about FPGAbased system designs. In other words. This is configurable computing.
for higher-volume products. The fact that you’re no longer using an ASIC is a big help in this respect. for example. In addition. which does not manifest itself exactly as you might expect. Systems based on reconfigurable computing are upgradable in the field. RECONFIGURABLE PROCESSOR A reconfigurable processor is a microprocessor with erasable hardware that can rewire itself dynamically. This allows an incremental design flow. However. For example. all optimized to allow applications to run at the highest possible speed. First. a single device could serve as both a camera and a tape recorder (among numerous other possibilities): you would simply download the desired software and the processor would reconfigure itself to optimize performance for that function. it may even be possible to make such enhancements without customer involvement. a luxury not typically available to hardware designers. this ability can translate to immense flexibility in terms of device functions. . there will be some production cost savings. thus reducing lifetime costs. which eliminates a large amount of development effort. the production cost of fixed hardware may actually be lower. which result from the elimination of the expense of ASIC design and fabrication. Ideally." In practical terms. thus requiring no additional memory. the reconfigurable processor can transform itself from a video chip to a central processing unit (cpu) to a graphics chip. This allows the chip to adapt effectively to the programming tasks demanded by the particular software they are interfacing with at any given time. It is even conceivable that new protocols could be uploaded from a base station to the handheld phone on an as-needed basis. The new chips can be called a "chip on demand. It would be possible to support as many protocols as could be fit into the available on-board ROM. Because not all of the logic must be present in the FPGA at all times. The final advantage of reconfigurable computing is reduced time-to-market. The second advantage is lower system cost. Such changes extend the useful life of the system. There are no chip design and prototyping cycles. You can even ship a product that meets the minimum requirements and add features after deployment. the logic design remains flexible right up until (and even after) the product ships. We have to think in terms of lifetime system costs to see the savings. the cost of supporting additional features is reduced to the cost of the memory required to store the logic design. In the case of a networked product like a set-top box or cellular telephone. it is possible to achieve greater functionality with a simpler hardware design. Consider again the multiprotocol cellular phone. On a low-volume product.
the lower on-chip communication costs allow efficient cooperation between the processor and array at a finer grain than is sensible with discrete designs. Reconfigurable logic exploits more program parallelism. reconfigurable devices achieve a 10x improvement in functional density over microprocessors. we hope to demonstrate that this composite device is an ideal system element for embedded processing. The processor improves the efficiency of the reconfigurable array for irregular. While it is possible to combine a conventional processor with commercial reconfigurable devices at the circuit board level. As such. general-purpose computation. integration radically changes the i/o costs and design point for both devices. We anticipate that a processor combined with reconfigurable resources can achieve a significant performance improvement over either a separate processor or a separate reconfigurable device on an interesting range of problems drawn from embedded computing applications. allowing them to realize a higher yield of their raw capacity. The key to their cost/performance advantage is that conventional processors are often limited by instruction bandwidth and execution restrictions or by an insufficient number or type of functional units. Reconfigurable devices have proven extremely efficient for certain types of processing tasks. The reconfigurable array extends the usefulness and efficiency of the processor by providing the means to tailor its circuits for special tasks. Notably. resulting in a qualitatively different system. Microprocessors have evolved to a highly optimized configuration with clear cost/performance advantages over reconfigurable arrays for a large set of tasks with high functional diversity. At the same time this lower memory ratio allows reconfigurable devices to deploy active capacity at a finer grained level.We are developing an architecture and a prototype component that will combine a processor and a high performance reconfigurable array on a single chip. sometimes as much as 10x. than conventional processors. RECONFIGURABLE CHIPS Reconfigurable chips are simply the extreme end of programmability. By combining a reconfigurable array with a processing core we hope to achieve the best of both worlds. By dedicating significantly less instruction memory per active computing element. RECONFIGURABLE HARDWARE Description: . The high functional density characteristic of reconfigurable devices comes at the expense of the high functional diversity characteristic of microprocessors.
and contexts. Benefits: The principal benefits of reconfigurable computing are the ability to execute larger hardware designs with fewer gates and to realize the flexibility of a software-based solution while retaining the execution speed of a more traditional.For these reasons. In our own business we have seen tremendous cost savings. The reason we need a run-time environment at all is that there are decisions to be made while the system is running.) The embedded software that runs there is called the runtime environment and is analogous to the operating system that manages the execution of multiple software threads. we are not available to make these decisions. hardware-based approach. etc. It must then perform the necessary routing between the hardware object’s inputs and outputs and the blocks of memory reserved for each data stream. having software manage the reconfigurable hardware usually means having an embedded processor or microcontroller on-board. simply because our systems do not become obsolete as quickly as . Of course. In order to benefit from run-time reconfiguration. (We expect several vendors to introduce single-chip solutions that combine a CPU core and a block of reconfigurable logic by year’s end. The run-time environment is then free to reclaim the reconfigurable logic gates that were taken up by that hardware object and to wait for additional requests to arrive from the application software. This makes doing more with less a reality. it is necessary that the FPGAs involved have some or all of the following features. it must stop the appropriate clock. Next. Once the object starts to execute. Like threads. reprogram the internal logic. deadlines. the more flexible can be the system design. The more of these features they have. It is the job of the run-time environment to organize this information and make decisions based upon it. the caller can be notified and given the results. And as human designers. Process: To do this. and restart the RPU. So we impart these responsibilities to a piece of software. Deciding which hardware objects to execute and when Swapping hardware objects into and out of the reconfigurable logic Performing routing between hardware objects or between hardware objects and the hardware object framework. the run-time environment must continuously monitor the hardware object’s status flags to determine when it is done executing. Once it is done. the run-time environment must first locate space within the RPU that is large enough to execute the given hardware object. chip designers are turning increasingly to reconfigurable hardware— integrated circuits where the architecture of the internal logic elements can be arranged and rearranged on the fly to fit particular applications. hardware objects may have priorities. This allows us to write our application software at a very high level of abstraction.
allows rapid implementation of new standards and protocols on an as-needed basis. these benefits will only increase. and many can be broken down into components that are split between the two. and other hardware into a single chip. Consequently. it makes sense to always use the best technology for the job at hand. developers are typically forced to amortize the cost of SoCs and ASICs over a product lifetime that may be extremely short in today's volatile technology environment. And as reconfigurable computing becomes more popular. the user can choose only among functions that already reside inside the device. The limitation of most types of complex hardware devices—SoCs.our competitors because reconfigurable computing enables the addition of new features in the field. Careful analysis of computational requirements reveals that many algorithms are well suited to high-speed sequential processing. Billions of Operations (BOPS). that the benefits far exceed the initial learning curve. while SoCs offer choices. many can benefit from parallel processing capabilities. ADVANTAGES OF RECONFIGURABILITY Many system-on-a-chip (SoC) computer designs provide reconfigurability options that provide the high performance of hardware with the flexibility of software. You may find. . CURRENTLY AVAILABLE PROCESSORS Reconfigurable processors are currently available from Chameleon Systems. and protects their investment in computing hardware. and PACT (Parallel Array Computing Technology). To most designers. SoC means encapsulating one or more processing elements—that is. Whether you do it for your customers or for yourselves. These versatile chips can perform many different functions. general-purpose embedded processors and/or digital signal processor (DSP) cores—along with memory. you should at least consider using reconfigurable computing in your next design. as we have. Solutions involving combinations of cpus and FPGAs allow hardware functionality to be reprogrammed. and general-purpose cpus—is that the logical hardware functions cannot be modified once the silicon design is complete and fabricated. However. and enable medical instrument OEMs to develop new platforms for applications that require rapid adaptation to input. ASICs. The technologies combined provide the best of both worlds for system-level design. With this in mind. input/output devices. even in deployed systems. Developers also create ASICs—chips that handle a limited set of tasks but do them very quickly.
multiple algorithms are implemented as separate hardware modules. during this processing time. Four algorithms would divide the chip into four functional areas. the four algorithms are loaded into the entire reconfigurable Fabric one at a time. algorithm 2 is loaded into the background place. the entire Fabric is dedicated to algorithm 1. In a single clock cycle. lower cost and lower power consumption RCP ARCHITECTURE . The entire reconfigurable fabric is dedicated to just one algorithm at a time. First. MULTIFUNCTION IMPLEMENTATION In a conventional ASIC or FPGA. during this processing time. So finally the result is: much higher performance. which allows customers to convert their algorithms to hardware configuration by themselves. algorithm 3 is loaded into the background plane. With Reconfigurable Technology.Among those only Chameleon is providing a design environment. the entire Fabric is swapped to algorithm 2.
a new Reconfigurable machine is established. PRESENT DEVELOPMENT ENVIRONMENT In order to build sufficient performance. The most important parts are the logic circuits. FPGAs and ASICs. second by integrating a complete SoC subsystem. DEVELOPMENT ENVIRONMENT The development environment. Thus. enables customers to develop and debug communication and signal processing systems running on the RCP. according The various possible connections between functional blocks are encoded to bits known as Configuration bits. today's designers have been forced to employ an amalgamation of DSPs. each of which requires a unique design and debug environment. rules of their interconnections and ways of the input/output connections. PCI core. which configure function blocks to data in the configuration memory. ٭ ARCHITECTURE COMPONENTS 32-bit Risc ARC processor @125MHz 64 bit memory controller 32 bit PCI controller . and ٭ third by consolidating the design and debug environment into a single platformbased design system that affords the designer comprehensive visibility and control. PROBLEMS OVERCOME BY RCP PLATFORM The RCP platform was designed from the ground up to alleviate this problem: ٭ first by significantly exceeding the performance and channel capacity of the fastest DSPs. and flexibility into their systems. channel capacity. including an embedded microprocessor. A new chip must inside determine the set of the function blocks (FB). Resulting configuration stream is downloaded into configuration memory through configuration inputs. The RCP's development environment helps overcome a fundamental design and debug challenge facing communication system designers. which are used to construct the circuit. and high-speed bus. comprising Chameleon's C-SIDE software tool suite and CT2112SDM development kit. DMA function.Machine design supposes that some pins are considered as the configuration inputs and another as data or control inputs and outputs.
providing tremendous computational power. 32-bit interface. 2) A high-performance 32-bit Reconfigurable Processing Fabric (RPF) The RPF has 108 parallel computation units. and 64-bit high-performance memory controller. debug and verification. 3)Instantaneous reconfigurability These core technologies combine to eliminate the performance flexibility compromise. exploit platform-based design and enable you to implement your own algorithms to differentiate your product. These fully integrated and fully verified modules simplify design. This 128-bit. split-transaction bus provides 2GByte/sec on-chip bandwidth amongst the subsystems in the Embedded Processor System and the RPF. reconfigurable processing fabric (RPF) high speed system bus programmable I/O (160 pins) DMA Subsystem Configuration Subsystem The Chip incorporates three core architectural technologies: 1) A Complete 32 bit Embedded Processor system It provides all of the basic building blocks for a complete system: a 32-bit ARC processor. . This is where the “heavy lifting” (Rec Roadrunner Bus links these system modules.
The CS2112 has 4 Slices with 3 Tiles in each. and a control logic unit. The Fabric provides unmatched algorithmic computation power to Chameleon Chip. It consists of 84. the basic unit of reconfiguration.RECONFIGURABLE PROCESSING FABRIC The above mentioned fabric comprises an array of reconfigurable tiles used to implement the desired algorithms.32-bit Data path Units and 24. The fabric is divided into Slices.000 16-bit Million Operations Per Second. 16×24-bit Multipliers. four blocks of local store memory.Operating at 125Mhz. Each tile contains seven 32-bit reconfigurable datapath units. they provide up to 3.000 16-bit Million Multiply-Accumulates Per Second and 24. two 16x24-bit multipliers. Each tile can be reconfigured at runtime Tiles contain : 32-bit Datapath Units Local Store Memories 16x24 bit Single-Cycle multipliers Control Logic Unit .
The DPU is a data processing module that directly supports all C and Verilog operations.The high-performance 32bit Data path Unit (DPU): The Tile includes seven Data path Units. 32bit Data path Unit (DPU): The Tile includes seven Data path Units. The DPU is a data processing module that directly supports all C and Verilog (Verilog is a hardware description language used to design and . The Dynamic Interconnect connects the modules within the fabric’.
The routing multiplexers select operands. The DPU includes includes two 32-bi At the heart of the operators.document electronic systems) operations. There are 3 routing classes: a) Local routes-connects near by 7 DPUs with a delay of 1 clock cycle. The Op masking data oper . b) Intra-slice routes-connects DPUs within a slice with a delay of 1 clock cycle c) Inter-slice routes-connects DPUs in different slices with a delay of 2 clock cycles.
16×24 Single-Cyc The Tile includes four 32-bit wide by 128 word deep Local Store Memories. The CLU includes the Programmable Sum-of-Products(PSOP) and the Control State Memory (CSM). The LSM is accessed directly by the DMA Subsystem and the neighboring DPUs/Multipliers. The CSM stores eight user-specified Instructions for each of the seven DPUs in The Tile includes CS2112 delivers 3 . Control Logic Unit (CLU) The Control Logic Unit directly implements finite state machine sequencing and conditional operation.
In addition to code generation tools. eCONFIGURABLE™ TECHNOLOGY: This technology reconfigures fabric in one clock cycle and increases voice/data/video channels per chip. Chameleon Systems are providing the ability for the customers to do the programming themselves thus keeping the secrecy of their algorithms. each Slice can be configured independently. . As mentioned earlier.5 GBytes/sec I/O bandwidth. Loading the Background Plane from external memory requires just 3 µsec per Slice. Dynamic Interconnect PROGRAMMABLE I/O RCP includes banks of Programmable I/O (PIO) pins which provide tremendous bandwidth. the four algorithms are loaded into the entire reconfigurable processing Fabric one at a time.the Tile. with eConfigurable Technology. debugging and verifying RCP designs. The Fabric provid results in Dynamic and optimal datafl TECHNOLOGIES USED IN CHIP 1. the package contains source-level debugging tools that support simulation and real-time debugging. and Verilog simulation and synthesis tools used to create parallel datapath kernels which run on the CS2112's reconfigurable processing fabric. Swapping the Background Plane into the Active Plane requires just one clock cycle. where each Instruction represents a complete DPU configuration. The C-SIDE software suite includes tools used to compile C and assembly code for execution on the CS2112's embedded microprocessor.. Chameleon's design approach leverages the methods employed by most of today's communications system designers. 2. The PSOP implements conditional state sequences on a configurable context basis. Each PIO bank of 40 PIO pins delivers 0. C~Side uses a combined C language and Verilog flow to map algorithms into the chip’s reconfigurable processing fabric (RPF). C~SIDE Development Tools : With this software development tool . The Chameleon Systems Integrated Development Environment (C~SIDE) is a complete toolkit for designing. this operation does not interfere with active processing on the Fabric.
3. called kernels.The C-SIDE design system is a fully integrated tool suite. with C compiler. In the next phase. Verilog synthesizer. Using these tools.an element not readily found in ASIC and FPGA design flows.to 100-fold. configuration management and DMA services. The eBIOS calls are automatically generated at compile time. according to Chameleon. Design process: The designer starts with a C program that models signal processing functions of the baseband system. eBIOS provides resource allocation. in Chameleon's reconfigurable assembly language-like design entry language. the designer implements them in the RCP to accelerate them by 10. but can be edited for precise control of any function. the . eBIOS: It provides a interface between the Embedded Processor System and the Fabric. as well as a debug and verification environment -. full-chip simulator. The assembler then automatically generates standard Verilog for these kernels that the designer can verify with commercial Verilog simulators. the designer can compare testbench results for the original C functions with similar results for the Verilog kernels. The designer creates equivalent functions for those blocks. Having identified the dataflow intensive functional blocks.
Before actually productising the system. This helps prove the design concept. .designer synthesises the Verilog kernels using Chameleon's synthesis tools targeting Chameleon technology. At the end. the tools output a bit file that is used to configure the RCP.The designer then integrates the application level C code with Verilog kernels and the rest of the standard C function. including features like single-stepping and setting breakpoints. With telecommunications OEMs facing shrinking product life cycles and increasing market pressures. and enables the designer to profile the perormance of the whole basestation system in a real-world environment. This is where the chameleon chips are going to make its effect felt. not to mention the constant flux of protocols and standards. The CS2112 development environment makes all chip registers and memory locations accessible through a development console that enables full processor-like debugging. the designer must often perform a system-level simulation of the data flow within the context of the overall system. Chameleon's development board enables the designer to connect multiple RCPs to other devices in the system using the PCI bus and/or programmable I/O pins.Chameleon's C-SIDE compiler and linker technology makes this integration step transparent to the designer. it's more necessary than ever to have a platform that's reconfigurable.
Today’s system architects have at their disposal an arsenal of highly integrated. Enter the reconfigurable processor. ADVANTAGES Its advantages are can create customized communications signal processors increased performance and channel count can more quickly adapt to new requirements and standards lower development costs and reduce risk. and field-programmable gate arrays (FPGAs). highperformance semiconductor technologies. such as application-specific integrated circuits (ASICs). DISADVANTAGES Inertia – Engineers slow to change Inertia is the worst problem facing reconfigurable computing RCP designs requires comprehensive set of tools 'Learning curve' for designers unfamiliar with reconfigurable logic APPLICATIONS This application involves high-rate communications. digital signal processors (DSPs). an entirely new category of semiconductor solution that serves as a system-level platform for a broad range of applications. and a variety of network protocols and data formats. Reducing power Reducing manufacturing cost. Its applications are in. application-specific standard products (ASSPs). signal processing. However. data-intensive Internet DSP wireless basestations voice compression software-defined radio high-performance embedded telecom and datacom applications xDSL concentrators . system architects continue to struggle with the requirement that communication systems deliver both performance and flexibility.
multiprotocol packet and cell processing protocols. Its advantages are that it can create customized communications signal processors . data-intensive Internet. multichannel voice compression.Base-station infrastructure will have to be adaptive enough to accommodate those requirements. High-Performance DSL (Digital Subscriber Line Technology) DSL technology high Bandwidth to homely users. voice compression. high-performance embedded telecom and datacom applications. FUTURISTIC DREAM .this can also be called a “chip on demand” Its applications are in. With a fixed processor the channels must be able to support both simple voice calls and high-bandwidth data connections Wireless Local Loop (WLL) Reconfigurable technology is widely applied in Wireless Local Loops also because of their high processing power. Software-Defined Radio (SDR) SDR concept is applied in Cell phone Technology brings CONCLUSION These new chips called chameleon chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the utmost speed. fixed wireless local loop multichannel voice compression multiprotocol packet and cell processing protocols Wireless Base stations The reconfigurable technology mainly focuses on base stations and their unpredictable combination of voice and data traffic. and it can more quickly adapt to new requirements and standards and it has lower development costs and reduce risk.wireless basestations. bandwidth and reconfigurable nature.DSP.an example of such kind of a chip is a chameleon chip.fixed wireless local loop. xDSL concentrators. software-defined radio.it has increased performance and channel count.
Now a new kind of chip may reshape the semiconductor landscape. the phone will automatically adjust so that the quality improves. The chip will be smart enough to be the brains of a cell phone that can transmit or receive calls anywhere in the world. that chip doesn't exist today. videos. Just think of the possibilities for the fickle consumer. customers will chuck the static hard-wired solutions. Reconfigurable chips are simply the extreme end of programmability.” If these adaptable chips can reach a cost-performance parity with hard-wired chips. .an example of such kind of a chip is a chameleon chip. then so will the gadgets of the information age. It is not only possible but relatively commonplace to "rewrite" the silicon so that it can perform new functions in a split second. These new chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the utmost speed. And if silicon can indeed become dynamic. At the same time. could tilt the balance of power that has preserved a decade-long standoff between programmable chips and hard-wired custom chips. the device will also serve as a handheld organizer and a player for music. It would require • • • • flexibility high performance low power and low cost But we might be getting closer. These chips. No longer will you have to buy a camera and a tape recorder. someone will make a chip that does everything for the ultimate consumer device. You could just buy one gadget. If the reception is poor. or games.this can also be called a “chip on demand” “Reconfigurable computing goes a step beyond programmable chips in the matter of flexibility. and then download a new function for it when you want to take some pictures or make a recording. referred to as reconfigurable processors.One day. Unfortunately. The chip adapts to any programming task by effectively erasing its hardware design and regenerating new hardware that is perfectly suited to run the software at hand.
without the need to plug in adapter hardware REFERENCES • http://www. connect to the Internet.com • www.seminarprojects.xilinx.seminartopics. and serve as entertainment during travel delays -.chameleon systems.com/Thread-chameleon-chipsdownload-full-report-and-abstract#ixzz0vJuryb1J • www. maintain a calendar.iec.quicksilver technologies. this means that the day isn't far away when a cell phone can be used to talk. are more flexible than DSP chips but slower and more expensive For consumers.ieee.thinkdigit.com • www. transmit video images.com • www.info • www.Programmable logic chips. which are arrays of memory cells that can be programmed to perform hardware functions using software tools.org • www.org • www.com .
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