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# LAB MANUALS

FOR

## BASICS ELECTRONICS LAB

LIST OF EXPERIMENTS

## . 1. To plot V-I Characteristics of diode and calculate its forward

Dynamic and static resistance.

down voltage.

## 3 To plot the effect of temperature on reverse saturation current in

junction diode and determine forbidden energy gap.

4 To study half wave rectifier characteristics and study and calculate its
ripple factor.

## 5 To study full wave rectifier characteristics and calculate its ripple

factor with different filters.

## 6 To plot I/O Characteristics of transistor for CB Configuration and to

calculate current gain

## 7 To plot I/O Characteristics of transistor for CE Configuration and to

calculate current gain

## 8 To plot I/O Characteristics of transistor for CC Configuration and to

calculate current gain

## 9 To plot the drain characteristics &transfer characteristics of MOSFET

&determine offset voltage

## 12 To plot the drain characteristics of SCR.

EXPERIMENT NO 1

AIM:-
To plot the characteristics of Si diode and calculate its forward static and dynamic
resistance.

APPRATUS:-

Voltmeter ( 0-15 V), Milliameter ( 0-25 mA ), Microammeter ( 0-5 µA), Patch cords.
Supply voltage Vi = +12 V, R = 1K, D1 & D2 = Silicon type (1 N 4007 ).

THEORY:-
Forward condition of a P-N junction :

A P-N junction diode conducts in the forward direction that is when anode is connected
to the positive of supply voltage VAA and cathode to negative of supply voltage VAA

## Fig.1 Diode in forward bias condition

Above fig(1) shows the forward connection of diode. where VAA is forward voltage
applied. I = IF is the forward current flows through diode and V is the voltage drop
across the diode. With the forward bias, the barrier potential at the junction reduces &
majority carriers diffuse across the junction. This results in forward current through
diode. The amount of this forward bias VAA can be varied by changing a potentiometer
and series resistor ‘R’ decides the max. Forward current flow through diode.

## Reverse condition of a P-N junction :-

No flow electrons and hence no flow of electric current is possible in the reverse biased
condition fig.(2) shows the reverse bias connection of the diode.

## Fig.2 Diode in reverse bias condition

P-N junction diode conducts only in the forward biased condition that is it has the
property of a rectifier. This circuit is similar to that of forward biased condition except
two changes that is diode terminals are reversed and current flows in Microampere. In
reverse direction it draws negligibly small current Io,when reverse voltage is
continuously increased, at breakdown voltage Vz the diode draws heavy current at an
almost constant voltage. Fig (3) shows the forward V-I characteristics of diode.

The applied reverse voltage is gradually increased above zero in suitable steps and the
value of diode current are recorded at each step. If a graph is plotted with reverse voltage
along X-axis and the diode current along the Y-axix, we shall obtain a curve marked OC
as shown in fig. (3). The curve OC is called reverse characteristics of the diode.

## The dynamic static resistance of diode :

At the given operating point “P”

## (1) the dynamic (incremental) diode resistance or AC resistance is.

ΔVF BC
Rac = ----------- = ------------ ----------------------(1).
ΔIF AC
(2) The static diode Resistance,

V ON
RF = ---------- = ----------- -------------------------(2).
I OM

The voltage at which diode starts conducting is called a knee voltage, cut-in voltage or
threshold voltage. The knee voltage is designated either by Vk or Vv. It’s value is equal
to 0.6 V for Silicon & 0.2 V for germanium.

PROCEDURE :-

## 1. Study the circuit provided on the front panel on the kit.

2. Switch ‘ON’ the power supply the check variable power supply with digital
multimeter.
3. Select anyone diode (say silicon diode Si type) with the help of patch chord.
4. Make the connection of silicon diode for forward bias condition.
5. Connect the milli-ammeter and voltmeter in the circuit.
6. Increase the forward bias Vi from 012 V in steps and note down the
voltmeters(V) and milli-ammeter (IF) reading for each steps. Tabulate the
7. Now make the connections fo reverse bias condition.
8. Connect the Microammeter and voltmeter in the circuit.
9. Increase the reverse bias voltage in steps and note down the voltmeter (V) and
10. Plot the graph between (IF) on Y-axis and voltage (V) on X-axis.
11. Select the operating point calculate the dynamic and static resistance as per
equation (1) & (2). Given above.

OBSERVATIONS :-

## For forward bias :

D1 diode D2 diode
VAA
V IF V IF
For reverse bias :

D1 diode D2 diode
VAA
V Ir V Ir
RESULT :-

Static forward
Resistance, RF =
------------Ω.

Dynamic / resistance,
Rac =
-----------------Ω.

VIVA QUESTIONS :-

## 1. What do you mean by P-N junction?

2. Explain the characteristics of diode?
3. What is knee voltage?
4. What is the value of cut-in voltage for Si and Ge diode?
5. Explain working of diode in reverse bias condition?
6. What is the significance of η in diode current equation?
7. What is the effect of temperature on characteristic of diode?
8. What is the reverse saturation current?
EXPERMIENT 2

AIM

## To plot the forward and reverse characteristics of Zener diode.

APPRATUS:

Voltmeter (0-25 V), Ammeter (0-25 mA), patch chords. Supply voltage +12V, R=1
KΩ, Zener diode 5.6 V.

THEORY :

A properly doped crystal diode which has a sharp breakdown voltage is known as a Zener
diode. A breakdown or Zener voltage depends up on the amount of doping. If the diode is
heavily doped, depletion layer will be thin and consequently. the breakdown of the
junction will occur at a lower reverse voltage. On the other hand a lightly doped diode
has a higher breakdown voltage. When an ordinary crystal diode is properly doped so that
it has a sharp breakdown voltage it is called a Zener diode. Fig.1 shows the symbol of
zener diode.

## Fig. 1 ( Zener diode )

When the reverse bias on a crystal diode is increased, a critical voltage called breakdown
voltage is reached where the reverse current increases sharply to a high value. The
breakdown region is the knee of the reverse characteristic as shown in fig. 2.
The satisfactory explanation of this breakdown of the junction was first given by the
American scientist C. Zener. Therefore the breakdown voltage is sometimes called Zener
voltage and the sudden increase in current is known as Zener current.
Fig.2 ( characteristics of Zener diode )

When forward biased its characteristics are just those of ordinary diode as shown in fig.2.
A Zener diode is always reverse connected i.e. it always reverse biased. It has sharp
breakdown voltage called Zener voltage Vz. When the reverse voltage across the Zener
diode exceeds the the breakdown voltage Vz, the current increases very sharply. In this
region the curve is almost vertical. It means that voltage across Zener diode is constant at
Vz even though the current through it changes. Hence Zener diode can be used as a
voltage regulator regulator to provide a constant voltage from a source whose voltage
may vary over sufficient range. Therefore it is used as a voltage stabilizer.

PROCEDURE :-

(1) study the circuit provided on the front panel of the kit.shown in fig 3.
(2) Connect milli-ammeter &voltmeter in the circuit as shown.
(3) Make forward connection of Zener diode by connecting positive Vaa to anode of
selected Zener diode and negative Vaa to cathode of the same diode.
(4) Increase the forward bias V from 0 to 12 V in steps and note down the voltmeter
(V) and milli-ammeter (If) readings for each steps.
(5) Plot the graph between current (If) on Y-axis and voltage (V) on X-axis.
(6) Now remove the forward connection and make it for reverse connection and
repeat the step no. 4.
OBSERVATION :-

## Sr. No. V (volt) I(mA)

RESULT :-

Forward characteristics of Zener diode is studied and ploted. The breakdown voltage
(Vz) of the given Zener diode is found to be ---------- V.
Fig 3 . Circuit diagram of Zener Diode

VIVA QUESTIONS :-

(1) Explain the difference between ordinary diode and Zener diode?
(2) name the application of zener diode?
(3) what is zener breakdown?
(4) what is the difference between zener breakdown and avalanche breakdown?
(5) Explain V-I characteristics of Zener diode.
(6) what is the effect of Zener voltage when temperature is varying?
(7) what is voltage ratings in Zener diode?
(8) what is the working condition of Zener Diode?
EXPERIMENT NO 3

AIM :-

To plot the effect of temperature on reverse saturation current in junction diode and
determine forbidden energy gap.

APPARATUS :-

THEORY :-

## A P-type semiconductor in contact with N-type semiconductor constitute a P-N junction

diode . before the two semiconductor brought together each one is in equilibrium i.e.
holes and electrons concentration are constant and uniform together out each
semiconductor just after constant majority holes from the P-type diffuse in to N-type. The
holes and electrons recombine when they meet. However this flow of majority carrier
eventually stop because of formation of a thin layer in which holes and electrons
recombine leaving a row of negative ions on the P-type & a row of ions on N-type
materials.

The layer in which holes and electrons recombination occurs is called the depletion layer.
The formation of charges on either side of the layer constitute a potential barrier which
prevents together flow of charges. The potential barrier is 0.2 V for Ge and 0.6 V for Si.
It is the formation of potential barrier that makes the effect of P-N junction a useful
device. Since the effect can be controlled by an externally applied voltage. The barrier
voltage can be neutralized by applying a voltage of approximate polarity. The junction
conducts in forward bias condition while it offers a high value of resistance in reverse
bias. In this condition a reverse saturation current flows through it.

The relation between the diode current and voltage is given by,

I = Io ( e –v/ηVT - 1) ---------------(1)

Under reverse bias condition the reverse saturation current Io increases as the temperature
increases. The temperature dependence of Io is determined by ni which is given by

## where ξgo = energy gap at absolute zero.

However ξgo may be assumed to be practically constant. The reverse saturation current
may be represented by this relationship

Io = T3 e ( -ξg o / kT ) ---------------(3)

## Log Io = log T3 - ξgo / kT --------------(4)

In this operating range of diode the temperature dependency of is determined by second
term of equation (4). Hence a plot of log Io Vs Iis approximately linear.

Fig.1 Diode in forward bias condition Fig.1 Diode in reverse bias condition

PROCEDURE :-

## (1) switch ON the main supply.

(2) Keep the thermometer in the hole provided for it.
(3) Switch on the oven measure the temperature corresponding current in mA.
(4) Take the current in the rising and falling temperature.
(5) Represent result graphically.
(6) Plot the graph between 2.303 log Io as a f(1/T) .evaluate the slope.

CONCLUSION:-

## Graph of temperature v/s current is approximately linear.

VIVA QUESTION:-
(1) What is P-N junction ?
(2) What is forbidden energy gap?
(3) How depletion layer is formed in P-N junction ?
(4) Why is a semiconductor an insulator at ordinary temperature ?
(5) What is the effect of temperature in characteristic?
(6) What is effect of doping in characteristic of diode?
(7) What is effect of temperature on energy gap?
(8) What is the application of P-N junction?
EXPERIMENT NO 4

AIM :-

To study half wave rectifier characteristics and calculate it’s ripple factor and efficiency.

APPRATUS REQURIED :-

E & E make training module. Type : EE-41 with patch cords, CRO.

THEORY :-

For reasons associated with economics of generation and transmission , the electric
power available is usually an a.c. supply. The supply voltage varies sinusoidally and has
frequency of 50 Hz. It is used for lighting, heating and electric motors. But there are
many applications where d.c. supply is needed. When such a d.c. supply is required the
mains a.c supply is rectified by using crystal diodes.
(1) Half wave rectifier.
(2) Full wave rectifier.

## Half wave rectifier :-

Fig(2) shows a half wave rectifier circuit. It consists of a single diode in series with a load
resister. The input to the half wave rectifier is supplied from the 50 Hz a.c. supply, whose
waveform is shown in fig(1). Output will be as shown in fig(3).

## (1) (2) (3)

Fig. Half – wave rectifier
Fig(2) shows the circuit where a single crystal diode acts as a half-wave rectifier. The a.c.
supply to be rectified is applied in series with the diode and load resistance R L . the d.c.
output is obtained across the load RL. generally a.c. supply is given through a transformer.
The use of transformer permits two advantages, firstly it allows us to step-down the a.c.
input voltage as the situation demands. Secondly, the transformer isolates the rectifier
circuit from power line and thus reduces the risk of electric shock.

The a.c. voltage across the secondary winding AB changes polarities after every half
cycle. During the positive half cycle if input a.c voltage, end A becomes positive w.r.t
end B. this make the diode forward biased and hence it conducts current. During the
negative half cycle, end A is negative w.r.t. end B. under this condition the diode is
reverse biased and it conducts no current, therefore current flows through the diode
during positive half cycles of input a.c. voltage only; it is blocked during the negative
half cycles. In this way, current flows through load RL always in the same direction.
hence d.c. output is obtained across RL. Direction of load current IL during positive half
cycle is shown in fig(2). During negative half cycle no current will flow.

Ripple factor :-
The output voltage or load current of a rectifier consists of two components namely d.c.
component and a.c. component. The a.c. component present in the output is called a
ripple. As a matter of fact, the ripple is undesirable and accounts for pulsations in the
rectifier output. The effectiveness of a rectifier depends up on the magnitude of the
ripple in the output. Smaller the ripple, more effective will be the rectifier.
Mathematically the ripple factor,
The r.m.s. value of a.c. component of output voltage.
γ = -------------------------------------------------------------------
The d.c. component of output voltage

Vr (rms) Ir (rms)
= ---------- ---------
Vdc Idc
Where
Vrms = the r.m.s. value of the a.c. component of the output voltage

## We know that the r.m.s. value of the rectified load current,

Irms = √ I 2 dc + I 2 r (rms)
Dividing the above equation on both sides by Idc

## squaring and rearranging the above expression,

for half wave rectifier

Idc = Im / π

Where Im is the maximum value of loaf current. The r.m.s. value of the load
current for a half-wave rectifier may be found by using calculation and it’s value,
Irms = Im / 2

Substituting these values of Idc and Irms in the equation (1) for ripple factor

Efficiency :-

I 2 dc * RL
η = ------------------ ------------(2)
I 2 rms ( Rf + RL )

## Substituting the values of Idc and Irms in equation (2)

( Im / π) 2 * RL 4 RL
η = ------------------------------ = ------ * -------------
( Im / 2)2 * ( Rf + RL ) π2 ( Rf + RL )
0.406
η = ---------------
1 + Rf / R L
now efficiency will be maximum , if RL >> Rf
thus

PROCEDURE:-

## (1) connect the circuit as shown in fig(2).

(2) Apply the input a.c. voltage in to the circuit.
(3) Observe the input and output on the CRO.

CONCLUSION:-

VIVA- QUESTIONS

## (1) Explain the function of rectifier?

(2) What are the types of rectifier ?
(3) What do you mean by ripple factor ?
(4) How ripple factor can be minimized?
(5) What are the types of filter ?
(6) In which type of filter you will get less ripple, why ?
(7) What is the difference between half wave and full wave rectifier?
(8) In a half wave rectifier if a resistance equal t load resistance is connected in
parallel with diode then output voltage would be?

EXPERIMENT NO-5

Aim: - To study full wave rectifier characteristic &calculate its ripple factor with
&without filter.

APPRATUS :-
E & E make training module. Type: EE-41 with patch cords, CRO.

THEORY:-
In fullwave rectification current flows through the load in same direction for both
half cycle of i/p a.c. voltage .This can be achieved with two diodes working
alternatively. For the positive half cycles of input voltage, diodes supplies current
to the load and for next half cycle, the other diode does so, current flows in the

There fore a fullwave rectifier utilizes both half-cycles of i/p a.c voltage to
produces the d.c. o/p . The following two circuit are commonly used for fullwave
Rectification.

## The circuit employs two diodes D1 and D2 as shown in fig.

A center tapped secondary winding is used with two diodes connected so that
each one half –cycle of input a.c. voltage. In other words diodes D1 utilises the
a.c. voltage appearing across the upper half

SCHEMATIC DIAGRAM

## A Full Wave Rectifier is a circuit, which converts an ac voltage into a pulsating dc

voltage using both half cycles of the applied ac voltage. It uses two diodes of which one
conducts during one half cycle while the other conducts during the other half cycle of the
applied ac voltage.

During the positive half cycle of the input voltage, diode D1 becomes forward biased and
D2 becomes reverse biased. Hence D1 conducts and D2 remains OFF. The load current
flows through D1 and the voltage drop across RL will be equal to the input voltage.
During the negative half cycle of the input voltage, diode D1 becomes reverse biased and
D2 becomes forward biased. Hence D1 remains OFF and D2 conducts. The load current
flows through D2 and the voltage drop across RL will be equal to the input voltage.

Ripple Factor

## The ripple factor for a Full Wave Rectifier is given by

the average voltage or the dc voltage available across the load resistance is

Efficiency

## Transformer Utilization Factor

Transformer Utilization Factor, TUF can be used to determine the rating of a transformer
secondary. It is determined by considering the primary and the secondary winding
separately and it gives a value of 0.693.

Form Factor

Form factor is defined as the ratio of the rms value of the output voltage to the average
value of the output voltage.

Peak Factor

Peak factor is defined as the ratio of the peak value of the output voltage to the rms value
of the output voltage.
Peak inverse voltage for Full Wave Rectifier is 2Vm because the entire secondary voltage
appears across the non-conducting diode.

This concludes the explanation of the various factors associated with Full Wave Rectifier.

## Rectifier with Filter

The output of the Full Wave Rectifier contains both ac and dc components. A majority of
the applications, which cannot tolerate a high value ripple, necessitates further processing
of the rectified output. The undesirable ac components i.e. the ripple, can be minimized
using filters.

The output of the rectifier is fed as input to the filter. The output of the filter is not a
perfect dc, but it also contains small ac components. Some important filters are

1. Inductor Filter
2. Capacitor Filter
3. LC Filter
4. CLC or π Filter

Inductor Filter

The figure shows an inductor filter. When the output of the rectifier passes through an
inductor, it blocks the ac component and allows only the dc component to reach the load.
Ripple factor of the inductor filter is given by .

The above equation shows that ripple will decrease when L is increased and RL is
decreased. Thus the inductor filter is more effective only when the load current is high
(small RL). The larger value of the inductor can reduce the ripple and at the same time the
output dc voltage will be lowered as the inductor has a higher dc resistance.

The operation of the inductor filter depends on its property to oppose any change of
current passing through it. To analyze this filter for full wave, the Fourier series can be

written as

The dc component is .

Assuming the third and higher terms contribute little output, the output voltage is

The diode, choke and transformer resistances can be neglected since they are very small

## Therefore, the resulting current i is given by,

The ripple factor which can be defined as the ratio of the rms value of the ripple to the dc
value of the wave, is

## If , then a simplified expression for γ is

In case, the load resistance is infinity i.e., the output is an open circuit, then the ripple

factor is . This is slightly less than the value of 0.482. The difference
being attributable to the omission of higher harmonics as mentioned. It is clear that the
inductor filter should only be used where RL is consistently small.

Capacitor Filter

A capacitor filter connected directly across the load is shown above. The property of a
capacitor is that it allows ac component and blocks dc component. The operation of the
capacitor filter is to short the ripple to ground but leave the dc to appear at output when it
is connected across the pulsating dc voltage.

During the positive half cycle, the capacitor charges upto the peak vale of the transformer
secondary voltage, Vm and will try to maintain this value as the full wave input drops to
zero. Capacitor will discharge through RL slowly until the transformer secondary voltage
again increase to a value greater than the capacitor voltage. The diode conducts for a
period, which depends on the capacitor voltage. The diode will conduct when the
transformer secondary voltage becomes more than the diode voltage. This is called the
cut in voltage. The diode stops conducting when the transformer voltage becomes less
than the diode voltage. This is called cut out voltage.

Referring to the figure below, with slight approximation the ripple voltage can be
assumed as triangular. From the cut-in point to the cut-out point, whatever charge the
capacitor acquires is equal to the charge the capacitor has lost during the period of non-
conduction, i.e., from cut-out point to the next cut-in point.

## The charge it has lost

If the value of the capacitor is fairly large, or the value of the load resistance is very large,
then it can be assumed that the time T2 is equal to half the periodic time of the waveform.

From the above assumptions, the ripple waveform will be triangular and its rms value is
given by
The ripple may be decreased by increasing C or RL (both) with a resulting increase in the
dc. output voltage.

LC Filter: - The ripple factor is directly proportional to the load resistance RL in the
inductor filter and inversely proportional to RL in the capacitor filter. Therefore if these
two filters are combined as LC filter or L section filter as shown in figure the ripple
factor will be independent of RL.

If the value of inductance is increased it will increase the time of conduction. At some
critical value of inductance, one diode, either D1 or D2 will always conducting.

## The ripple factor

CLC or π Filter

The above figure shows CLC or π type filter, which basically consists of a capacitor
filter, followed by LC section. This filter offers a fairly smooth output and is
characterized by highly peaked diode currents and poor regulation. As in L section filter
the analysis is obtained as follows.

Procedure: -

EDWin 2000 -> Schematic Editor: The circuit diagram is drawn by loading components
from the library. Wiring and proper net assignment has been made. The values are
assigned for relevant components.
EDWin 2000 -> Mixed Mode Simulator: The circuit is preprocessed. The test points and
waveform markers are placed in input and output of the circuit. GND net is set as
reference net. The Transient Analysis parameters have been set. The Transient Analysis
is executed and output waveform is observed in Waveform Viewer.

Result: -

The output waveform for Full Wave Rectifier with filter and without filter may be
observed in the waveform viewer.

VIVA QUESTION

## 1. What is the function of fullwave rectifier?

2. What is the difference between fullwave rectifier and half wave rectifier?
3. What is filter?
4. What is voltage regulation?
5. What is the application of fullwave rectifier?
6. What is the efficiency of fullwave rectifier?
7. What is transformer utilization factor?
8. Why we are using with Rectifier?

--
EXPERIMENT NO-6

AIM :

## To plot Input/Output characteristic of transistor for CB configuration.

APPRATUS :

Ammeter 0-10 microamp(1 no.) 0-25 mA(1 no),Voltmeter 0-5V (1 no.) &0-15V(1 no.)
Transistor,NPN BC148,PNP BC157, V1=12V variable,Vcc=12V variable.

## THEORY:- Transistor has a three terminal(emitter, base &collector) two junction.

(emitter junction & collector junction).
When both the junctions are forward biased then it is called as saturation region When
both the junction are reversed biased than it is called as cut-off region of transistor. If
emitter junction is F.B. & collector junction is R.B. is called as Active region.

Transistor can be used as an amplifier in any one of the configurations.Any of its terminal
can be made common to input &output. This common terminal is usually grounded. The
connection is then described in terms of common terminal.
Basically there are three types of circuit connections alled configuration for operating a
transistor.
(1) Common base (CB)
(2) Common emitter(CE)
(3) Common collector(CC)
The term common is used to determine the terminal that is common to the input and
output circuits generally. This common terminal is grounded collector configuration.

CB CONFIGURATION
Fig.1shows the CB configuration circuits diagram. In this configuration emitter current Ie
is the input current & collector current IC is the output current. The I/P voltage is applied
between the emitter and base. Whereas O/P is taken out from the collector to base
junction is reverse biased.
Figure 1.CB configuration

In active region curves are horizontal. This shows that o/p dynamic resistance Ro is very
high .
ro= ∆ VCB /∆ Ic IE = const
At given operating point,Ac &Dc (ά) current gains is defined as Dc current gain & (ά)
Dc = Ic / IE
Ac current gain &(ά) ac ∆ Ic/∆ IE with VCB constant.
The input characteristic is plotted between emitter current Ie and emitter base voltage VEB
for constant values of VCB . I/P characteristics shows that if VEB is less cut in voltage or
knee/threshold voltage then Ie is negligible small. After this as Veb increases it’s value is
0.3 volt for Ge transistor &about 0.5 v for Si transistor .
For a given operating point point input or a dynamic resistance is given by
Ri = ∆ VEB /∆ IE VCB = const
It may be noted that char is linear in the upper region but Non linear(i.e. curved) in the
lower region .Thereforethe A.C. input resistance (Dynamic resistance) dpends upon
location of the operating point selected along the curve . Its value in the linear region of
the curve is about 50 ohms.
PROCEDURE:-
(1) Make the circuit for CB configuration .Connect all the Voltmeter &Ameter.
(2) Check the Vcc and VEE Voltages by using voltmeter.

## TO PLOT O/P CHARACTERISTICS

(1)It is char. Plotted between VCB (x-axis)and IC (y-axis) for constant values of IE.
(2) Keep IE =0 by adjusting plot P1 vary the VCB voltage in regular steps and note the
corres[ponding values of Ic. Plot the graph between VCB (x-axis) and Ic(y-axis).

(3)select a suitable operating point on the graph plotted. Ro ==∆ VCB /Ic IE =const

## Where Ic and IE arethe currents at the selected operating point.

OBSERVATION:-
For IE =0 ForIE =2 mA ForIE =5 mA
-VCB Ic -VCB Ic -VCB Ic

CALCULATION:-

Ro == ∆ VEB /∆ IE , IE = mA

## TO PLOT THE INPUT CHARACTERISTICS:-

PROCEDURE
(1) It is plotted VEB (x-axis) and IE (y-axis) for constant values of VCB.
(2) Keep VCB const. Say at 2V vary the VEB by plot P1 and note the corresponding IE
in steps.
(3) Rereat step (2) for different values say 5v ,10v,12v etc.
(4) Plot the graph between VEB (x-axis) and IE (y-axis) for for VCB =10 v draw a small
incremental triangle ABC on static the dynamic input resistance is given by

OBSERVATION

2V 5V 10 V

RESULT:-

## The values of different parameters for CB are found to be

Ro=……….Ω , α dc=……….

α dc=………. ,R!=………. Ω

VIVA QUESTION:
(1) Ilustarte CB input and output characteristic .
(2)Why CB is much less temperature dependent .
(3) What is the current gain in CB ?
(4) What is the application of CB ?
(5) What is the range of input and ouput impedance ?
(6) How it is different from other two configuration ?
(7)Relation between α withβ and α with γ.
(8) Draw graph between α and Ic(i.e. gain Vs output current).

EXPERIMENT NO-7

AIM :

## To plot input/output characteristic of transistor for CEconfiguration.

APPRATUS REQURIED:

Ammeter 0-10 microamp(1 no.) 0-25 mA(1 no),Voltmeter 0-5V (1 no.) &0-15V(1 no.)
Transistor,NPN BC148,PNP BC157, V1=12V variable,Vcc=12V variable.
THEORY:- Transistor has a three terminal(emitter, base &collector) two junction.
(emitter junction & collector junction).

When both the junctions are forward biased then it is called as saturation region When
both the junction are reversed biased than it is called as cut-off region of transistor. If
emitter junction is F.B. & collector junction is R.B. is called as Active region.

Transistor can be used as an amplifier in any one of the configurations.Any of its terminal
can be made common to input &output. This common terminal is usually grounded. The
connection is then described in terms of common terminal.

Basically there are three types of circuit connections alled configuration for operating a
transistor.
(4) Common base (CB)
(5) Common emitter(CE)
(6) Common collector(CC)
The term common is used to determine the terminal that is common to the input and
output circuits generally. This common terminal is grounded collector configuration.

In CE configuration, base acts as input terminal. So input and output &output quantities
are IB , VEB & IC, VCE respectively.
By observing the charcteristics of the transistor that relates transistor currents and voltages behaviors of the

transistor can be studied. This characteristics curve is known as static characteristic curves.
INPUT CHARACTERISTICS

It relates the input current IB with input voltage VBE for a given constant output voltage V
VCE.In CE configuration ,Ib & VBE are input variables. The output variables are Ic & VCE.
──Fig.2hows that typical input characteristics for CE configuration. It is plotted between
IB & VBE for different values VcE.
We can find the dynamic input resistance (ri) of the transistor at a given values of Vbe . It
is defined as the reciprocal of the slope of curve at operating point (p).

Ri =∆ VBE /∆ IB VCE.=const

OUTPUT CHARACTERISTIC:-

The curve plotted between Ic & VCE for given values of IB is called as output
characteristics.
We can find out the following
Dynamic output resistance,
ro= Ic /Ib VCE =const

DC current gain ,
βdc= Ic / IB VCE = const.
AC current gain

β = Δ Ic /Δ IB VCE =const
Note:- Input & output char. Can be plotted for NPN transistor . Only conections of all
voltage source, milliammeters and voltmeters will be reserved for the PNP transistor.

PROCEDURE:-
(1) Make the circuit for configuration . connect all the Voltmeter &Ammeter.

## (2) Input charateristics:-

Keep VCE constant,change P1 note IB & VBE .Repeat the same procedure for
different values .Plot the i/p curve between IB & VBE for different values of
VCE.Find out dynamic input resistance from curve plotted.

(3)Output characteristic :-

Keep IB constant (by setting P1) change P2 note Ic & V CE .Repeat the same
procedure for different values of IB. Plot the o/p curve between Ic & VCE for
different valuesof IB .Find out the dynamic o/p resistance dc current gain & ac
current gain as explained in theory section.

OBSERVATION:-

## (1)From input characteristics dynamic input resistance is given by

ri ==∆ VBE /∆ IB VCE =const
(2)From output characteristics =……………… Ω
(3)Dynamic o/p resistance
ro ==∆ VCE /∆Ic IB =const

## (4)DC current gain

βdc =Ic/ IB VCE =const
(5)AC current gain ,

CONCLUSION :

## By changing P1(Vbb), forward biasing of emitter junction can be change.Also by

changing P2 (Vcc) reverse biasing of collector junction can be changed. So by changing
Vbb& Vcc transistor can be operates in active , saturation or cut off region..

VIVA QUESTION:
1. What is the current gain inCE?
2. What is the application CE?
3. Draw graph between α and Ic.
4. What is advantage of CE .
5. Illustrate i/p and o/p characteristic of CE.
6. How it is different from other configuration?
7. What is the range of input and o/p impedance?
8. Why it is used for power amplification purpose?
EXPERIMENT NO-8

AIM :
To plot input/output characteristic of transistor for CCconfiguration.

APPRATUS REQURIED:

Ammeter 0-10 microamp(1 no.) 0-25 mA(1 no),Voltmeter 0-5V (1 no.) &0-15V(1 no.)
Transistor,NPN BC148,PNP BC157, V1=12V variable,Vcc=12V variable.

## THEORY:- Transistor has a three terminal(emitter, base &collector) two junction.

(emitter junction & collector junction).

When both the junctions are forward biased then it is called as saturation region When
both the junction are reversed biased than it is called as cut-off region of transistor. If
emitter junction is F.B. & collector junction is R.B. is called as Active region.

Transistor can be used as an amplifier in any one of the configurations.Any of its terminal
can be made common to input &output. This common terminal is usually grounded. The
connection is then described in terms of common terminal.

Basically there are three types of circuit connections allied configuration for operating a
transistor.
(7) Common base (CB)
(8) Common emitter(CE)
(9) Common collector(CC)
The term common is used to determine the terminal that is common to the input and
output circuits generally. This common terminal is grounded collector configuration.
Above fig 1.shows that in common collector configuration a collector is common to both
I/P O/P.
Base termional acts as a I/P having I/P quantities as IB and VCB.
Emitter terminal acts as a O/P having O/P quantities as Ie and VCE
The O/P characteristics is plotted between Ie and VCE for several values of IB . Since
Ic~Ie,this characteristics is partially identical to that of Ce cicuit and is shown in fig (a)
below.
Similarly its I/P characteristic is plotted between VCB and IB for different value of VCE as
shown in fig(b) below . In I/P characteristic as a VBE is increased VCB is redused there by
reducing IB
PROCEDURE:-
(1) Make the circuit for CCconfiguration
(2) Connect the voltmeter,ammeter as shown in the cicuit.

## (3) FOR O/P CHARACTERISTICS

(1) Keep IB=0 microampere,& repeat the above step and the values of VCE & IE plot the
graph between VCE & IE.
(2) Keep IB=10icroampere,& repeat the above step and the values of VCE & IE plot the
graph between VCE & IE

OBSERVATION TABLE

## IB=0 IB=10icro IB=20micro IB=0

micro Am Am micro
Am Am
VCE IE VCE IE VCE IE

## (4) For i/p characteristic:-

(1) Keep VCE = constant, vary VCBin steps and note IB for each step. Plot the graph
between VCB(x-axis) and IB (y-axis)
(2) Repeat above step for several values of says VCE says at 4v, 8v, 12v etc.

OBSERVATION TABLE:-

## VCE =2V VCE =4V VCE =6V VCE

=12V
VCB IB VCB IB VCB IB VCB IB
RESULT:-

## The values of different parameters for CC found to be

Ro=……………………………………Ω.,αdc=……………………..
αAc=……………..,Ri=………………………Ω

VIVA QUESTION:

## 1. What is the current gain inCC?

2. What is the application CC?
3. Draw graph between and Ic and γ.
4. What is advantage of CC.
5. Illustrate i/p and o/p characteristic of C
6. How it is different from other configuration?
7. What is the range of input and o/p impedance?
8. How we can enhance the input impedance of CC?
EXPERIMENT 9

AIM:
To study and plot the drain characteristics of metal oxide semiconductor field effect
transistor (MOSFET).

APPARATUS REQURIED:

E&E make training module type:EE-05 with patch chords and instruction manual.

THEORY:

It is a unipolar device .fig show a p type MOSFET.It consist of a lightly doped n-type
substrate into which two highly doped p+ regions are diffused.These two regions acts as
sourse and drain.A thin layer of SiO2 layer,a metal layer is over laid,covering the entire
channel region from sourse to drain this alluminium layer constitute the gate.
A parallel plate capacitor is formed with the metal area of
gate and the semiconductor channel acting as the electrodes with the oxide layer as the
dielectric in between.Thus the gate is insulated by means of SiO2,This SiO2 layer results
in extremely high i/p resistance of the MOSFET .
Two types of MOSFET are there:

1.Enhancement MOSFET
2.Depletion MOSFET

## Enhancement type MOSFET:

Fig 1 shows the p –channel enhancement MOSFET and fig 2 shows its symbol. When the
substrate is grounded and a –ve voltage is applied at the gate, these results an electric
field normal to the SiO2 layer.This field originates from induced +ve charges on the
semiconductor site and terminates on the –ve charges on the lower surface of SiO2
layer.These induced +ve charges form minority carriers in the n-type substrate and form
an inversion layer.the magnitude of these induced +ve charges in the semiconductor
increases with the increase of the magnitude of the –ve voltage on the gate.The region
immedietly below the oxide layer has p type carriers.Accordingly the conductivity of this
region increases and current flow through this induced channel from source to drain also
increases.Thus the drain current has been enhanced on application of –ve voltage .For
this reason,this MOSFET is called enhancement MOSFET.
Fig shows the typical characteristics of p-channel enhancement type MOSFET.

## Fig1.N channel Enhancement mode MOSFET fig2 .N channel Enhancement mode

MOSFET
Depletion type MOSFET:

Fig 3 shows the basic structure of a n-channel depletion type MOSFET and fig4 shows its
symbol. It is fabricated by diffusing n-type channel between between n+ type sourse and
drain. The type of impurity is kept the same as for the sourse and drain diffusions.By
this ,unlike enhancement MOSFET ,an appreciable drain current IDSS flows for
VGS=0.On making the gate voltage –ve ,+ve charge gets induced in the n-type channel
through the SiO2 layer of the gate capacitor.But n-channel FET ,current is due to
majority carriers ,electrons.Hence these induced +ve charges make the n-channel less
conductive.The drain current ,therefore ,reduces as VGS is made more and more –ve.This
new distribution of the charges results in depletion of majority carriers.this lead to the
name MOSFET.

MOSFET

PROCEDURE:

## 1. Make the connections as shown in below fig.

2. Apply a constant dc voltage between gate and sourse VGS (say -0.2v)
3. Keep the voltmeter range switch to 10V.
4. Vary the output voltage VDS in steps of 1V and note down corresponding VDS &ID
5. Repeat the above steps by keeping different constant voltage VGS (say -0.5v,-0.8v etc)
6. Plot the graph of ID V/S VDS for constant VGS.

OBSERVATION TABLE:

## S.NO VGS =OV VGS =-0.5V VGS =-0.8 V

VDS (V) ID (mA) VDS (V) ID (mA) VDS (V) ID (mA)

CONCLUSION:

## VIVA –VOICE QUESTIONS:

1. What is MOSFET?
2. How many types of MOSFET are there?
3. How do the constructional features of a MOSFET differ from that of a JFET?
4. Compare N-channel MOSFET with P-channel MOSFET?
5. Why are N-channel MOSFET with preferred over P channel MOSFET?
6. Use of MOSFET?
7. Why are N channel MOSFET preferred over P channel MOSFET?
8. Define pinch off voltage.
EXPERIMENT 10

AIM—
1.To study the JFET Characteristeristics.
2.To plot the drain characteristics of JFET.
3.To plot the transfer characteristics of JFET.

APPARATUS—
Digital multimeter or voltmeter(0-25v),ammeter(0-10mA)

Theory—
FET is a three terminal unipolar solid state device in which the current is controlled by an
electric field.It is classified as—
1 JFET (Junction field effect transistor)
2.MOSFET( meatal oxide semiconductor field effect transistor).
The JFET can be divided depending upon their structure as follows:
a.N-channel JFET
b.P-channel JFET

Symbols

## Fig 1 Junction FET N-Channel fig2 Junction FET P-channel

The N-channel JFET consist of an N-type semiconductor bar with two P type heavily
doped regions diffused on opposite sides of its middle part.the P type region form two PN
junctions.The space between the junctions (ie N-type region) is called the channel.Both
P-type regions are connected internally and a single wire is taken out in the form of a
terminal called the gate(G).Other two terminals are called drain(D) and sourse(S).The
drain (D) is the terminalthrough which electrons leave the semiconductor bar and sourse
S is a terminal through which the electrons enter the semiconductor.
Whenever a voltage is
applied across the drain and sourse terminals,a current flows through the N-channel.The
current consists of only one of carrier (ie electrons).Therefore the FET is called a
unipolar device.
OPERATION OF JFET—

When the gate to sourse voltage(VGS) is applied by the battey (VGG),yhe reverse bias
voltage across the gate –sourse junction is increased .As a result of this,the depletion
regions are widened.This reduces the effective width of the channel and therefore
controls the flow of drain current through the channel.When this VGS is further
increased ,a stage is reached at which two depletion region touch each other.At this
voltage ,the channel is completely blocked and the drain current is reduced to 0.the gate
to sourse voltage at which the drain current is 0 is called pinch off voltage.as shown in
the diagram—

CHARACTERISTICS OF JFET:

## 1) V.I or Drain Characteristics:

These curve give relationship between the drain current (ID)and drain to sourse
voltage(VDS) for different values of gate to source voltage(VGS) to 0 volt.Then increase
the dtrain to sourse voltage voltage(VDS) in small suitable steps and record the
corresponding values of drain current (ID) at each step.Now,if a graph is plotted with VDS
along x axis and drain current along the y axis,a curve marked VGS =0 is obtained as
shown in fig 3.
:.

PROCEDURE:

## A. For drain characteristics

1. Study the ckt provided on the front panel of the kit shown in fig4.
2. Connect the milliammeter and voltmeters at the respective places.
3. keep the VGS and VDD a t minimum positions.
4. switch ON the power supply.
5.Keep the VGS at fix value say VGS =0V.
6.Now increase the VDD in steps and note down the readings of ID & VDS with the 0.5v
interval of VDS.
7.Plot the graph with VDS along x axis and ID along Yaxis.
8. Repeat steps 6 to8 for different values of VGS.

## 1.Keep the VDS at constant voltage say VDS =1V.

2.Now increase the value VGG and note the readings of ID and VGS with the 1V with 1V
internal of VGS
3. Plot the graph with graph with VGS along x axis and ID along y axis.
4. Repeat the above steps for different values of VDS

OBSERVATION:

## 1. For drain characteristics:

VGS =0V, VGS =-1V, VGS =-2, VGS =-3V, VGS =-4V

## S.NO VDS (V) ID (mA)

CONCLUSION:

The drain & transfer characteristics of JFET has been studied.From the exp.It can be
conclude that the depletion layer increases and decreases as the gate to sourse voltage is
reduced & increased respectively.
Fig 4. Circuit diagram of N-Channel JFET.

VIVA QUESTION

## 1.What is the difference between JFET and a bipolar transistor?

2. What are the applications of JFET?
3.What is the difference between MOSFET and JFET?
5.What do you mean by pinch off voltage?
6.What are the advantages of FET over BJT?
7.In which mode JFET is work?
8.What is the controlled parameter in JFET?
EXPERIMENT No. 11

AIM:-
a) To study and plot V-I characteristics of UJT
b) To study UJT relaxation oscillator.

APPARATUS:-
E&E Make training module type: EE-06 with patch chords and instruction manual.

THEORY:-

## The UJT is a 3 terminal semiconductor device with negative resistance characteristics. It

consists of a bar of n-type silicon with a small p-type insert(emmiter) nearer to one of the
ends as shown in the diagram—

FIG 1 FIG 2

The two ohmic contacts at the ends of the bar constitute two base terminals B1 and
B2.The rectifying contact is called the emitter.as the name suggests,UJT has only one
junction.
The n-type bar is lightly doped and acts as a resistor.The effective resistance
between the two bases is called the “interbase resistance RBB.”It may be thought of as
consisting of two resistors RB1&RB2 connected in series.The p-n junction is represented
by the diode in the equivalent ckt of UJT as shown in fig.
Under normal operating conditions,the emmiter is
forward biased and a supply voltage VBB is used such that B2 is +ve with respect to
B1.Fraction of VBB appears across RB1 and is given by VRB1=ηVBB
Where η=RB1/(RB1+RB2)
η is called the intrinsic stand off ratio.This ratio has a value between 0.5 to0.8.For small
values of VE(ie VE‹η VBB),the p-n junction is reverse biased and negligibly small
leakage current flows.when VE>ηVBB,
the diode conducts and holes are injected into RB1.They are attracted towards the
negative terminal of VBB.This causes an equal no.of electrons to flow from RB1to the
emitter,leading to decrease of RB1.Thus as the emitter current increase ,VE drops .This
phenomenon is known as conductivity modulation and results in –ve resistence.
-ve resistance region extends from peak point Vp to valley point
Vv.For voltages higher than Vv the density of charge carriers is so high that the life time
of the carriers is decreased considerably which counteracts the effect of new carriers
being generated.as a result ,the emitter voltage increases gradually for currents above Iv
and the UJT behaves like conventional forward biased diode.

PROCEDURE—

## 1 Make connections as shown in fig 4

2.Keep VBB constant at some value(say 5v).
3.Vary emitter to base -1 voltage VEB in steps of 0.2 and note down corresponding VE
4. Repeat above step by keeping different constant voltage VBB(say 10v)
5.Plot the graph of VE v/s IE for constant VBB.

## 1.Make connection as shown in fig.5.

2.Fix VBB to any constant voltage (say 10v).
3.Connect o/p across the capacitor and R2 on different channels of CRO and observe the
waveforms.
4.For charging time period T1,vary pot R1 and for discharging time period T2,vary pot
R2.In both the cases total time period T changes,thus changing the frequency.
5.Calculate the frequency of the waveform across the capacitor.
6. Voltage across capacitor gives sawtooth waveform and across R2 is the time delayed
trigger pulses,as shown in fig6 .
NO DATA
DC A 1k

NO DATA
+

DC V
UJT 10V
+
10V

## Fig 4 Circuit diagram of UJT

OBSERVATION TABLE—

S.NO VB
VBB=5V B=10V
VE (V) IE (mA) VE (V) IE (mA)
CONCLUSION:

## UJT Characteristics graph is similar as shown in fig.3 .sawtooth waveform is generated

when UJT is configured as relaxation oscillator.The frequency of the saw tooth waveform
can be varied by R1 or R2 resistances.

VIVA QUESTION :-

## (1) Is the name UJT appropriate ?

(2) what are the applications of UJT ?
(3) draw an equivalent circuit of UJT .
(4) What do you understand by intrinsic stand-off ratio ?
(5) What are negative resistance devices ?
(6) What is the range of intrinsic stand-off ratio ?
(7) How UJT works in Relaxtion oscillator?
EXPERIMENT No.12

AIM—
To study and plot
a. The D.C. gate controlled characteristics of SCR
b. The anode current characteristics.
c. The phase shift control of SCR.

## APPARATUS—E&E make training module type EE-07 with patch chords

,ammeter,voltmeter etc.

THEORY—

SCR is a four layer three terminal device called silicon controlled rectifier ,known as
thyristor shown in fig 1 and 2.The three terminals are anode,cathode, gate.SCR acts as a
switch.A SCR will conduct only when a triggering signal is applied at least for a moment
to its gate while its anode is +ve w.r.t cathode.The SCR will not conduct if the triggering
of the gate is done while its anode is –ve.once the SCR conducts,ie current starts flowing
from its anode to cathode,it behaves as an ordinary rectifier till its anode is at +ve
voltage.The gate has no longer any control over this anode current.thus the gate can only
make the conductive SCR to non conductive .To make it non conductive ,the anode
current has to be interrupted atleast for a moment by external means .After this if once
again the anode is made +ve w.r.t its cathode,the SCR will not conduct unless its gate is
triggered again.
The SCR is very fast in its switching .The duration required to
turn ON is called turn ON time.fig shows structure &ckt symbol of SCR.The fig shows
the typical characteristics of a SCR

Fig 1 Fig 2
The firing voltage (at which SCR starts conducting is a function of gate current )
decreasing with increasing gate current .When gate current is very large,breakdown will
take place over voltage VBO .Thus in a SCR the o/p can be control with gate
trigerring .Hence SCR finds wide application in power controllers.

PROCEDURE A

## 1. Make the connections shown in fig 4.

2. Select the DC supply on both toggle switches and by turning the supply knob to
counter clockkwise direction ,adjust 0 voltage.
3. Insert full value of 100 k ohm by turning 100kohm pot to its full clkwise direction.
4.put the mains ON. the indicator glows.
5. Now turn both the DC supply controls to fully clockwise direction, this gives
maximum DC voltage available. Record the anode voltage.
6. Vary the 100kohm resistance supply knob slowly in anticlkwise direction till the SCR
fires.firing of the SCR will be indicated by the meter.Note down the value of gate
current .
7. Turn OFF the power,insert the 100kohm pot to its full value, Turn ON the power
again.
8. Reduce the anode voltage by step of 2 v.Repeat the above procedure and take a set of
readings of anode voltage and gate current required for firing.
9. Plot the firing characteristics of SCR on a graph paper by taking anode voltage on the x
axis and gate current on y axis.
10. Determine the value of forward break over voltage VB0.
OBSERVATION TABLE—

PROCEDURE B

## 1. Make the connections.

2. Select A.C Supply by both the toggle switches.
3. put 100K Resistance to its full value.
4. Put the mains ON.
5. Rotate the 100k pot anticlkwise till the SCR fires.
6Measure the gate current & anode current observe the o/p waveform on the CRO& trace
the waveform.
7. Vary the gate resistance, record the anode current for different values of gate current
.Plot the characteristics on the graph paper.

OBSERVATION TABLE

PROCEDURE C

## 1.Make the connections.

2.with the toggle switches select 15v AC & 2V AC.
3 Turn the step decade resistance of 0.1 k to minimum ie.0 value .
4.Put the mains switch ON.
5.Record the anode current by millimeter & trace the waveform at the cathode on the
CRO.
6.Repeate the above procedure by varying the decade resistance in the steps.
7.By tracing the waveform on CRO find out angle of conduction on CRO on each setting.
8.Plot the phase firing characteristics of the SCR by plotting the phase shift on x axis and
anode current on y axis.The phase shift can also be calculated by the formula:

θ=2tan-1wRC

OBSERVATION TABLE

## S.NO DECADE Anode current I Phase angle θ

RESISTANCE R mA

CONCLUSION:-

The SCR can be fired by increasing the anode voltage again the breakover voltage should
be reduced by application of gate current.thus SCR is employed for controlled rectifier.

.
VIVA QUESTIONS:-

## 1. Why not GCR ?

2. What are the advantages of SCR .?
3. What are the applications of SCR ?
4. What is breakover voltage ?
5. Why is power electronics so important ?
6. When SCR is conducting,it have resistance?
7. How SCR turned off?
8. SCR consist how many PN junction?