Fundamentals

Chapter 1,2,4
From
Howard Johnson & Martin Graham; High speed Digital Design A hand book of Black Magic, Prentice Hall PTR, 1993.

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 Frequency and Time

 For every electrical parameter, we must consider the frequency range over which
that parameter is valid.

 The bandwidth of an electronic filter is the part of the filter's frequency response
that lies within 3 dB of the response at the center frequency of its peak.

 Fknee = 0.5/Tr Fknee = frequency below which most energy in digital pulses concentrated
Tr = pulse rise time

Fknee is used as the practical upper bound on the spectral content of digital signal

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Decomposing a Digital Signal into Frequency Components

• Digital signals are composed of an infinite number of sinusoidal functions – the

Fourier series
The Fourier series is shown in its progression to approximate a square wave:
1+2 1+2+3

0
-  2 3

1+2+3+4+5
1+2+3+4

Square wave: Y = 0 for - < x < 0 and Y=1 for 0 < x < 

Y = 1/2 + 2/pi( sinx + sin3x/3 + sin5x/5 + sin7x/7 … + sin(2m+1)x/(2m+1) + …)

1 2 3 4 5
May do with sum of cosines too.
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 Frequency Content of Digital Signals
• The amplitude of the sinusoid components are used to construct the
“frequency envelope” – Output of FT

Tr
0.35
20dB/decade
Tr

Pw
T

40dB/decade

1
T
Harmonic Number
1 3 5 7 9 …...
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 Estimating the Frequency Content
0.35
• Where does that famous equation F come from?
Tr
• It can be derived from the response of a step function into a filter
with time constant tau

V  Vinput (1  et / )
• Setting V=0.1Vinput and V=0.9Vinput allows the calculation of the
10-90% rise time in terms of the time constant

t1090%  t90%  t10%  2.3  0.105  2.195

• The frequency response of a 1 pole network is
1 1
F3dB   
2 2F3dB
• Substituting into the step response yields
1.09 0.35
t1090%  
F3dB F3 dB
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 Estimating the Frequency Content

0.35 Edge time

t10 90%  factor
F3 dB
This equation says:
 The frequency response of the network with time constant tau will
degrade a step function to a risetime of t10-90%
 The frequency response of the network determines the resulting rise
time ( or transition time)
 The majority of the spectral energy will be contained below F3dB
• This is a good “back of the envelope” way to estimate the frequency
response of a digital signal.
• Simple time constant estimate can take the form L/R, L/Z0, R*C or Z0*C.

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Examining Frequency Content of Digital Signals
• The frequency dependent effects described earlier in this class can be
applied to each sinusoidal function in the series
 Digital signal decomposed into its sinusoidal components
 Frequency domain transfer functions applied to each sinusoidal
component
 Modified sinusoidal functions are then re-combined to construct the
altered time digital signal
• There are several ways to determine this response
 Fourier series (just described)
 Fast Fourier transform (FFT)
 Widely available in tools such as Mathematica, MathCad…

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 Response on d-flip flop

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RNS, MS, MIT
 TIME AND DISTANCE
 Electrical signals in conducting wires, or conducting circuit traces, propagate at a speed dependent on the
surrounding medium.

 Propagation delay is measured in units of picoseconds per inch.

 Propagation speed is measure in inches per picoseconds.

 Propagation delay of conducting wire increases in proportion to the square root of the dielectric
constant of surrounding medium

 Delay per inch for PCB traces depends on both the dielectric constant of the PCB material and the trace
geometry.)

 Trace geometry determines whether the electric field stays in the board(signal propagates slow) or goes into the
air (effective dielectric is half).

 Outer layer PCB traces are always faster than inner traces

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 LUMPED VERSUS DISTRIBUTED SYSTEMS
Distributed System : The reaction of system to the incoming pulse is distributed
along the trace,

Lumped System : The system small enough for all points to react together with
uniform potential .

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 3-db and rms frequencies

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 reactance
 Four concepts provide rich language for describing and understanding the behavior
of digital circuit elements at high speeds.
 Capacitance
 Inductance
 Mutual capacitance
 Mutual Inductance

 Many ways to study capacitance and inductance

 Microwave engineer studies them using Maxwell's equations
 Designer of control systems uses Laplace transforms
 An advocate of spice simulations uses linear difference equations
 Digital engineer use the step response.

 Step response measurement shows us just what we need to see: what happens when a
pulse hits a circuit element.

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 Step response

W e can characterize DUT by observing the step response and using these thumb rules.
Resistor display a flat step response. At time zero, the output rises to a fixed value and holds steady.

Capacitor display a rising step response. At time zero, the step respose starts at zero but then later rises to a
full valued output.
Inductor display
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sinking
MIT step response. At time zero, the output rises instantly to full size and then later
decays back towards zero.
 Ordinary capacitance

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 Ordinary inductance

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 Mutual capacitance

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 Mutual Inductance
The coefficient of interaction between two loops is called
mutual inductance, which decay rapidly with increasing
distance. Unit : volt-sec/amp

Faraday's law tells us that there will be no induced voltage in the

secondary coil.

The fact that the induced field always opposes the change is
an example of Lenz' law.
electromotive force (emf) energy per unit charge

The induced emf in coil 1 is due to self inductance L. The

induced emf in coil #2 caused by the change in current I1 can
be expressed as

The mutual inductance M can be defined as the proportionality

between the emf generated in coil 2 to the change in current in
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 MUTUAL Inductance transformer

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 Mutual inductance and crosstalk

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RNS, MS, MIT
 Signaling Convention and Circuits

William S. Dally & John W. Poulton; Digital Systems Engineering, Cambridge

University Press, 1998.

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 Signaling Modes for Transmission lines
 The method used to encode a signal (binary symbols into currents) on a transmission line.
 Good signaling mode is one that provides good noise immunity while minimizing power
dissipation and delay.
 Figure below is a typical transmission line signaling system.

 We will analyze transmitter and receiver separately (by RT = ZO)

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 Transmitter Signaling Mode
 Four major variables for designing transmitter
 The output impedance Ro
 Coupling between the signal level and local power supply (or ground) Zgt
 Whether signal is bipolar or unipolar
 Signal amplitude.

 Current and voltage mode transmission

 Analyze how to isolate the signal from noise sources :
 signal return cross talk,
 single supply power supply noise.

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 Transmitter Signal return cross talk
 Analyze this circuit using superposition theorem.

 For R0 = 0, KXRT = MAX FOR VOLTAGE MODE

R0 = ∞, KXRT = CROSS TALK IS COMPLETELY ELEMENATED

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 Bipolar vs. unipolar encoding
 Illustrates two methods for encoding binary symbols into currents.

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 Transmitter generated references

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 Receiver signal detection
 Figure illustrates receiving end of a transmission line signaling system.

 Methods for generating receiver reference

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 Receiver return cross talk
 Receiver return cross talk coefficient is given by

 Power supply noise.

 To reject noise impedance
should be as large as possible

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 Source termination

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 Differential Signaling
 Binary signal can be sent differentially over a pair of conductors by driving one
conductor with signal and a second conductor with complement of the signal.

 Voltage mode differential signaling

 Bipolar signaling
 Unipolar signaling

 Disadvantages
 It requires more pins and wires.

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 Advantages
 References
 Differential signal serves as its own receiver reference even with unipolar signaling.
 Transmitter generated reference , the delays of the two lines must carefully be matched for
the noise to cancel.

 Signal swing:
 Twice the noise margin

 Return current
 Is a constant DC value.
 For bipolar V1 = -V0 , IR = 0.

 Self induced power supply noise (Kin)

 A change is true signal’s driver is compensated equally and opposite change in current is
complement signal’s driver.
 Other signaling modes
 Bipolar current mode signaling

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 When differential signaling

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 Symmetric transmission lines
 Return inductance equals to signal inductance

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RNS, MS, MIT
 Advanced Signaling Techniques

William S. Dally & John W. Poulton; Digital

Systems Engineering, Cambridge University Press,
1998.

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
Signaling
Signaling over RC or LRC
over RC interconnect
 RC line have delay increases quadratic ally with length and long tail to step response that lead to ISI (solved using
repeaters or by over driving lines).
 LRC line have frequency dependent attenuation that leads to ISI at high signaling rates (solved using equalization).

 Circuit model (Distributed RC Transmission Line)

 Behaviour of line described by diffusion or heat equation

 Delay of an unloaded line of length d is apprx.

 Delay in line can be made linear rather than quadratic

With distance by breaking line into multiple segments
And inserting repeaters b/w each segment

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Repeaters
 Uses combined resistor-capacitor symbol to denote a resistive line segment with distributed
capacitance.

 Delay of line with repeaters.

 Calculating optimal section length which minimizes delay by differentiation w.r.t ls (wire delay matches
repeater delay , 2tb)

 Velocity at optimal section length

 Increasing wire width and spacing

 Reduces delay (resistance decreases, capacitance increases -- power dissipation increases)
 Ch1 capacitance to adjacent wires
 Ch2 fringing capacitance

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
Over drive
Delay can be reduced
of low swing RC line
 Increasing width and spacing
 Repeaters
 Overdrive

 This technique equalizes low pass nature of RC line by preemphasizing the high frequency
components of the signal.

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
Driving lossey LC lines
Frequency dependency attenuation, skin effect results in ISI.
 Effects can be countered by equalizing and preemphasis
 Figure below shows attenuation of high frequency by 50%
 Shifts base line presented to high frequency component and they hardly reach output.

 High frequency attenuation affects lone pulse

eye opening data dependent jitter

Frequency dependent attenuation can be canceled by equalization.

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RNS, MS, MIT
Equalization of LRC lines

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RNS, MS, MIT
Bidirectional signaling waveforms

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Voltage mode simultaneous
bidirectional signaling.

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
Reverse channel cross talk
Simultaneous bidirectional signaling introduces reverse channel cross talk.
 A proportional noise source that reflects coupling between the two channel that share
conductor
 Coupling occurs due to

 Solution
 1. care full matching of components.
 2. digitally trimming the termination resistance.
 3. by splitting signal return into clean and dirty paths.

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 Signal splitting into clean and dirty
path
 Clean path offers zero AC current across zrc.

 Dirty channel halves the cross talk

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Signaling Standards, Chip-to-Chip Communication
Networks, ESD Protection

Kerry Bernstein & et. al., High Speed CMOS Design Styles,
Kluwer, 1999.

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Introduction
 System level considerations
 Interface timings, valid signal levels, and signaling protocols
 Chip-to-chip communications networks
 Packaging constraints and parasitics.
 Electrostatic discharge (ESD) protection
 Voltage translation and over-voltage protection
 Receiver and off chip driver circuit topologies
 External and self induced sources of noise.

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Signaling standards
• JEDEC(Joint Electron Device Engineering Council) established standards to provide
compatible I/O levels among Integrated Circuits.

• JEDEC standard interface level definitions include

▫ Small signal
▫ Full signal swing conventions.

• Small amplitude voltage swings about a reference voltage.

▫ Stub series terminated logic (SSTL)
▫ High speed transceiver logic (HSTL)
▫ Gunning transceiver logic (GTL)

• Full signal swing (Rail-to-rail, Bipolar)

▫ Low voltage CMOS (LVCMOS)
▫ Low voltage transistor-transistor logic (LVTTL)
▫ Emitter coupled logic (ECL)

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Signaling standards
 Parameters commonly used to specify I/O signal levels (valid for AC & DC)
 VDD: Chip supply voltage(driver supply for LVCMOS, LVTTL)
 VDDQ: driver supply voltage
 VREF: input reference voltage
 VTT: termination voltage
 VIH, VIL: Valid high and low input levels
 VOH, VOL: Valid high and low output levels

 Data integrity requires zero slope reversal through the valid signal levels.

 Figure next slide shows valid and corrupted transmitted signal

 Over shoot and undershoot can cause data corruption and over time, I/O device performance
degradation.

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Signaling standards

• In many applications , both valid signal levels and the entire interface protocol are standardized.
• DRAM (both Synchronous Link DRAM & Direct Rambus DRAM)
▫ Use terminated , Rambus signaling logic (RSL), small signal swing interface levels.
▫ Define clocking and control signal strategies with objective of maximizing memory bandwidth.

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Chip-to-chip communication networks
 This section examines practical transmission line signal networks and discussions on
transmission line effects .

 Transmission lines effects

 Propagation delay greater than rise time of transmitted signal
 Reflections (cause overshoot, undershoot and system-wide noise)
 Result is reduction in the valid-data window of transmitted pulses with respect to the system
clock.

 The characteristics impedance for a transmission line having and inductance L per unit
length, a capacitance C per unit length, and a low resistance may be approximated as:

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Chip-to-chip communication networks
 Any impedance discontinuity in a transmission line, from and impedance Z1 to an
impedance Z2, results in a partial reflection of the propagated signal at the discontinuity.

 The fraction of reflected signal, or reflection coefficient, is given as:

 Velocity of signal propagation along a low resistance transmission line is:

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Point-to-point Networks
 Point-to-point network consists of a single driver and receiver pair.

 In systems where the distance between the driver and receiver may be kept short and
source and load impedances may be carefully controlled, these networks may be series-
terminated. Series termination is preferable because there is no DC power consumption
in the signal network.

 Rule of thumb: if the distance from driver to receiver is short enough that the round trip
transmission line delay is less than the pulse width of the transmitted data, point-to-point
termination may be used.

 The load capacitance (receiver, ESD, Packaging) introduces some inherent impedance
mismatch is the system.

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Ideal and cmos p-p series terminated network

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Near end and far end voltages resulting from single data pulse
on the ideal series terminated configuration

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Effects of mismatched source and transmission line
impedance

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Multiple load networks
 Common in microprocessor applications where, a single driver must supply an address signal
to multiple external devices.

 Signal reflections in series terminated network result in un acceptable switching delays under
these conditions: load termination is used instead

 Two ideal load terminated configurations common to HSTL, SSTL and other small swing
interface protocols.

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Impedance matched networks

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ESD protection
• ESD protection circuits provide low resistance paths under high voltage conditions to
dissipate the energy in ESD pulses.

• Three standard models for ESD pulses

▫ Human body model (HBM)
▫ The machine model (MM)
▫ The charged-device model (CDM)

• HBM pulses represent a discharge of a 1kv pulse over nearly 200ns, an approximation of a
human body contacting a grounded device.

• MM pulse described as damped, oscillatory current sources with peak current of 7 to 16A at
frequencies of 7 to 16 Mhz. these events which can occur during machine handling.

• CDM pulses are lower in voltage, but longer in duration than HBM and MM pulses,
representing the flow of charge accumulated on-chip to an external ground.
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ESD protection
 ESD pulses can cause irreversible damage such as
 Fused metal wires
 Thermal breakdown of PFET and NFET devices (occurs when the high drain current localized silicon
heating and irreversible damage).

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ESD protection topology to prevent irreversible damage to CMOS devices
 This method uses either SCR’s or diodes (or both) for primary ESD protection and NFET
device N1, a gate coupled NMOS device for secondary protection.

 The protection circuit requires significant area to dissipate large currents, adding 1 to 3 pf of
capacitance to the chip pad.

 This circuit merits careful optimization to minimize capacitive loading of high frequency I/O
signals.

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RNS, MS, MIT
Power Distribution and noise

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Power Supply Networks

 In integrated circuits, electrical power is distributed to the components of the chip over a
network of conductors on the chip. Power network design (IC) includes the analysis and
design of such networks.

 Networks tradeoffs
 Performance
 Reliable
 Effective

 The power distribution network distributes power and ground voltages from pad locations to
all devices in a design.

 A robust power distribution network is essential to ensure reliable operation of circuits on a

chip.

 Power supply integrity verification is a critical concern in high-performance designs.

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IR Drop
 Due to the resistance of the interconnects constituting the network, there is a voltage drop
across the network, commonly referred to as the IR-drop.

 The package supplies currents to the pads of the power grid either by means of package leads
in wire-bond chips or through C4 bump arrays in flip chip technology.

 Although the resistance of package is quite small, the inductance of package leads is significant
which causes a voltage drop at the pad locations due to the time varying current drawn by the
devices on die.This voltage drop is referred to as the di/dt-drop.

 Therefore the voltage seen at the devices is the supply voltage minus the IR-drop and di/dt-
drop.

 Excessive voltage drops in the power grid reduce switching speeds and noise margins of
circuits, and inject noise which might lead to functional failures. High average current
densities lead to undesirable wearing out of metal wires due to electromigration {EM).
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Challenges in design
 the challenge in the design of a power distribution network is in achieving excellent voltage
regulation at the consumption points notwithstanding the wide fluctuations in power demand across
the chip, and to build such a network using minimum area of the metal layers.

 These issues are prominent in high performance chips such as microprocessors, since large amounts
of power have to be distributed through a hierarchy of many metal layers. A robust power
distribution network is vital in meeting performance guarantees and ensuring reliable operation.

 Parasitic interconnect resistance, decoupling capacitance and package/interconnect inductance

form a complex RLC circuit which has its own resonance frequency. If the resonance frequency lies
close to the operating frequency of the design, large voltage drops can develop in the grid.

 explicitly added decoupling capacitances are not free and increase the area and leakage power
consumption of the chip.

 most commercial tools focus on post-layout verification of the power grid when the entire chip design is
complete and detailed information about the parasitic of the power and ground lines and the currents drawn by
the transistors are known. Power grid problems revealed at this stage are usually very difficult or expensive to fix

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implicit solution

 Capacitance between power and ground distribution networks, referred to as decoupling

capacitors or decaps, acts as local charge storage and is helpful in mitigating the voltage drop at
supply points. Parasitic capacitance between metal wires of supply lines, device capacitance of
the non-switching devices, and capacitance between N-well and substrate, occur as implicit
decoupling capacitance in a power distribution network. Unfortunately, this implicit
decoupling capacitance is sometimes not enough to constrain the voltage drop within safe
bounds and designers often have to add intentional explicit decoupling capacitance structures
on the die at strategic locations.

 decisions about the structure, size and layout of the power grid have to be made at very early
stages when a large part of the chip design has not even begun.

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Implicit solution

 Due to the growth in power consumption and switching speeds of modern high performance
microprocessors, the di/dt effects are becoming a growing concern in high speed designs.
Clock gating, which is a preferred scheme for power management of high performance
designs, can cause rapid surges in current demands of macro-blocks and increase di/dt effects.
Designers rely on the on-chip parasitic capacitances and intentionally added decoupling
capacitors to counteract the di/dt variations in the voltage. But it is necessary to model
accurately the inductance and capacitance of the package and chip and analyze the grid with
such models, as otherwise the amount of decoupling to be added might be underestimated or
overestimated. Also it is necessary to maintain the efficiency of the analysis even when
including these detailed models.

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Contd………..
 A critical issue in the analysis of power grids is the large size of the network (typically millions
of nodes in a state-of-the-art microprocessor). Simulating all the non-linear devices in the chip
together with the power grid is computationally infeasible. To make the size manageable, the
simulation is done in two steps. First, the non-linear devices are simulated assuming perfect
supply voltages and the currents drawn by the devices are measured. Next, these devices are
modeled as independent time-varying current sources for simulating the power grid and the
voltage drops at the transistors are measured. Since voltage drops are typically less than 10%
of the power supply voltage, the error incurred by ignoring the interaction between the device
currents and the supply voltage is small. By doing these two steps, the power grid analysis
problem reduces to solving a linear network which is still quite large. To further reduce the
network size, we can exploit the hierarchy in the power distribution models.
 Note that the circuit currents are not independent due to signal correlations between blocks.
This is addressed by deriving the inputs for individual blocks of the chip from the results of
logic simulation using a common set of chip-wide input patterns. An important issue in power
grid analysis is to determine what these input patterns should be. For IR-drop analysis,
patterns that produce maximum instantaneous currents are required, whereas for
electromigration purposes, patterns producing large sustained (average) currents are of
interest.

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Contd…..

 Power grid analysis can be classified into input vector dependent methods and vectorless methods.
The input vector pattern dependent methods employ search techniques to find a set of input
patterns which cause the worst drop in the grid. A number of methods have been proposed in
literature which use genetic algorithms or other search techniques to find vectors or a pattern
of vectors that maximize the total current drawn from the supply network. Input vector-
pattern dependent approaches are computationally intensive and are limited to circuit blocks
rather than full-chip analysis. Furthermore, these approaches are inherently optimistic,
underestimating the voltage drop and thus letting some of the supply noise problems go
unnoticed. The vectorless approaches, on the other hand, aim to compute an upper bound on
the worst-case drop in an efficient manner. These approaches have the advantage of being fast
and conservative, but are sometimes too conservative, leading to overdesign.

 Most of the literature on power network analysis deals with the issue of computing the worst
voltage drops in the power network. Electromigration is an equally serious concern, but is
attacked with almost identical methods. Instead of the voltage at each node, EM analysis solves
for current in each branch, and instead of a voltage limit, there is a current limit per wire,
depending on its layer and width.

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Contd……..

 Other IC applications may use only a portions of the flows mentioned here. A gate array or
field programmable gate array (FPGA) designer, for example, will only do only the design
stages, since the detailed usage of these parts is not known when the power supply must be
designed. Likewise, a user of FPGAs or gate arrays will only use the analysis portion, as the
design is already fixed.

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 noise

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Noise
 Noise with in CMOS digital circuits is more prevalent today than ever due to
 Shrinking of the physical chip dimension
 Shrinking of the interconnects with in chip.

 As separation b/w interconnect decreases, increases capacitive coupling or

crosstalk.

 Noise source
 Crosstalk
 Sagging and recovery of the power supplies
 Ringing on both Vdd and GND power supplies (power supply network).

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Capacitive coupling (crosstalk)
 I = c dv/dt , exchanged current

 dv/dt is rate of change of voltage b/w a wire and neighbor.

 C is capacitance
 Width and thickness of wire
 Linear spacing between the lines
 Separation distance to any other conductor such as wiring levels above and below
 Type of dielectric
 Distance of common run length shared by the two wires.

 As technology scale to smaller dimensions

 Circuits get faster
 RNS, MS,
Crosstalk MIT
is higher
Crosstalk
 Different wiring configurations will result in different noise amplitudes and widths

 Wires are longer and overlap more, noise pulse are taller or wider due to pulse travelling down a
resistive line (short pulse wider).

 One can make this noise pulse larger by putting the driver of the victim wire farther away(shield
driver)

 Rule of thumb: one only needs to account 3-4 longest aggressor wires for any particular victim wire.

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Reduce crosstalk
 Methods for reducing crosstalk from process point of view include
 Making wires thinner
 Not allowing tight minimum spaces
 Low epsilon dielectrics.

 Design perspective
 One can space the wires farther apart,
 Keep the wires as short as possible
 Increase the driving strength of the victim lines
 Make sure direction of transitions of the neighboring wires are in a direction that do not cause logic
noise.

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Delay noise
 When induced noise from the aggressor wire either speeds up a victim wire or slows
it down, this is called delay noise.

 It is synchronous in nature since both the victim and aggressor net are switching at
the same time (race condition at victim).

 Signal switching in opposite directions results in large effective capacitance for

driving circuit to overcome, voltage across the coupling capacitance 2 dv/dt . The
added delay could result in a signal being propagated too slow to arrive at input of
device.

 Performance limited paths that consist of a large amount of RC delay must be

accommodate the added delay due to switching neighbors to accurately predict a chip
final cycle time.

 Delay can be function of the inductance of a line.

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Logic noise
 Logic noise is defined as an asynchronous noise pulse from a neighboring net on to
victim net which is quiet which causes a circuit fail.

 CMOS circuit family

 Static
 Dynamic domino
 Pass gate
 DCVS

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 Timing convention and
synchronization
Timing fundamentals, Clocking Styles, Clock Jitter,
Clock Skew, Clock Generation, Clock Distribution,

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 Timing fundamentals
 Timing is the spacing of events in time.

 Timing convention governs when a transmitter drivers symbols onto the signal line and when
they are sampled by the receiver (periodic, aperiodic).

 A good timing convention is one that manages timing noise, skew and jitter in an efficient
manner and allows the system to operate over a wide range of data rates.

 Timing nomenclature
 Delay and transition times
 Relative timing b/w two
transitions is measured from
50% point of one transition to
50% transition of the other.

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 Latching Strategies

Kerry Bernstein & et. al., High Speed CMOS

Design Styles, Kluwer, 1999.

RNS, MS, MIT

Introduction
 Latching refers to the system and usage guide lines that govern a given chip design w.r.t
storage elements, which are circuits that store digital signal states.

System and Storage

guidelines Chip design Elements
govern
latching

 Importance of Latching Storage Element

Logics Storage Element
1. 2.
pipelined Partition

Computer Systems

Starting and ending

3. point for timing and
Testing and Bringing up System 4. test analysis: chip
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design
Introduction
 Chapter
 Types of storage elements and their design
 How they fit into over all chip system
 Types of errors.

 Performance of latch circuits

 Propagation delay from the data input to the data output with the clock set to a mode that makes latch
transparent(logic circuit, performance optimized).
 Time the data must arrive before the clock closes the latch (data storage).
 Delay introduced in path by the arrival times of the clock edges.

 Power consumption of a latch

 Power required to switch the chip-wide clocking network (microprocessor, 25% of total chip power).
 Power consumed by the switching activity initiated by invalid signal edges passing through latch (waste
power in down stream logic causing invalid switching activity).

 Testability
 Maintaining current state of its storage node to controlling the behavior of the logic being tested
 Design of remainder of the latch can be greatly affected.

RNS, MS, MIT

Introduction
 High speed CMOS designs require that latches and their clocking be integrated in to the
logic circuit design to a much higher degree resulting in latches serving many more
functions than simply storing a logic state.

 Cycle boundaries: in almost every design, latches are used at the cycle boundaries to pass valid
logic states from one pipeline stage to the next.
 Mid-cycle boundaries: the insertion, or movement, of latches to some intermediate point
between cycle boundaries is a key element of cycle stealing.
 Execute logic function: one method of reducing latch delay is to merge it with logic function
from either its input or output side.
 Transition from one circuit style to another.
 Dynamic to static
 Single rail to differential
 Pulse to static and static to pulse.
 Initiate test of a portion of the logic.

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Basic latch design
 Transmission gate latch
 Tristate inverter latch
 Storage Elements.
 Is a circuit that holds the state of a signal after the logic that set the signal has changed its state.
 Composed of
 A clock gate that controls when the next valid state is stored.
 A storage node, a capacitor usually with cross-coupled transistors to maintain the charge, that holds the current valid state
a t the output while it is processed by the next stage of the logic pipeline.

 Latch
 Is defined as a single bit storage element that can store only a single value in response to a
control signal (D-Latch).
 Level-sensitive storage element is one that passes data from the input to the output
when the control signal is active.
 A single level-sensitive latch is the basic building block for all latches and flip-flops.

RNS, MS, MIT

Basic latch design
 Flip-flop
 Is defined as a single bit storage element that can store two values in a master slave type of
arrangement in response to a control signal .

 Edge-triggered latch
 Is one that samples the input data on either a rising or falling edge, of a control signal.

Sampling: data does not enter the latch until the activating edge of the control signal
Capture: data that propagates into the storage element before the activating clock edge the latch is
said to be captured.

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Basic latch design
 Static and dynamic latches
 The storage node in a latch is simply the capacitor that holds the value sampled from the data
input.
 Two types of storage nodes
 Static latch uses a storage node that always has a conducting path to either a power or ground connection.
 Dynamic latch has a conducting path to power or ground only while the data is being sampled.

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Basic latch design
 Latch clocking
 Formulation of latching strategy : Trade off between the design of the latch circuits and the
clocking used to control the latches.
 Clock phases and edges.
 The state of latch is determined by the phase of its clock input. (active high, active low, capture
edge, launch edge)
 Timing: setup and hold
 Setup time & Hold time : a signal level must be valid, or setup, at a specified time with respect
to the capture edge of the clock and that level must be held for another specified amount of
time with respect to the same capture edge of the clock.
 Effects of clock skew
 Arrival times of clocks to consecutive latches dictates the behavior of the logic in between and
around the catches.
 Clock overlap is defined as two different clocks causing all of the latches they control to be
transparent at the same time.
 Clock underlap is defined as two different clocks causing the latches they control to all be
opaque at the same time.

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Basic latch design
 Noise/robust design
 Latch circuits are subject to the same noise concerns as any other circuits with weakly held
internal nodes.

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Race Free Latches for precharged logic

 Cross-coupled Differential Output

 Negative Setup Pipeline Latch

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Asynchronous Latch Techniques
 Self-Resetting CMOS (SRCMOS) Latch
 Muller C-element
 Asynchronous TSPC Latch
 Cycle stealing is used to describe the "stealing" of a single CPU cycle to allow a DMA
engine to perform a DMA operation. This is opposed to block operation where a DMA
engine would request a bus, hold it for a complete transaction (typically 16-32 bytes but
could last much longer) before releasing to a CPU.

RNS, MS, MIT