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VERILOG Presentation

VERILOG Presentation

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Published by: Ravikiran Kadannavar on Sep 01, 2010
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Introduction to Verilog HDL

How it started!

‡ Developed by Gateway Design Automation Limited in 1983. ‡ ‡ Cadence purchased Gateway in 1989. ‡ Verilog was placed in the public domain. ‡Open Verilog International (OVI) was created to develop the Verilog Language as IEEE standard.

The Verilog Language

‡ Preferred in the commercial electronics industry ‡ Now, one of the two most commonly-used languages in digital hardware design (VHDL is the other) ‡ Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these two languages ‡ Best for configuring large designs produced by large design teams Best for describing low-level logic (more concise )

‡ HW description language competing with VHDL Standardized: IEEE 1364-1995 (Verilog version 1.0) IEEE 1364-2001 (Verilog version 2.0) ‡ Features similar to VHDL: but Case-Sensitive ( only lower-case letters) ‡ Designs described as connected entities ‡ Bit-vectors and time units are supported ‡ Features that are different: ‡ Built-in support for 4-value logic and for logic with 8 strength levels encoded in two bytes per signal. ‡ More features for transistor-level descriptions ‡ Less flexible than VHDL. ‡ More popular in the US (VHDL common in Europe)

SIMPLE VERILOG PROGRAM .

function. // in. inout port declarations // signal/wire/reg declarations // data variable declarations // sub-module instantiation and connection // functional blocks: initial. ‡ Module describes the functionality or structure of the design Module declaration module module_name (list of ports). out. task Endmodule .QUICK TUTORIAL OF VERILOG LANGUAGE ‡ Module is the basic design unit. always.

For Ex : .

a design can be described in the following styles Data-flow style Behavioral style Structural style Any mix of above .Within a module.

An example Half adder structural model (gate-level) Half adder data-flow model Half adder behavioral model structural model (gate-level) instantiation of primitives and modules. .

Half adder data-flow model Continuous assignments. .

Half adder behavioral model procedural assignments. .

A block comment begins with µ/*¶ and ends with µ*/¶. .Language elements A single line comment begins with µ//¶ and ends with a newline. Identifiers Equivalent to variable names Identifiers can be up to 1024 characters.

high. true high impedance. false one. low.Logic Values and Signal Strengths The Verilog HDL has 4 logic values: 0 1 z or Z x or X zero. floating unknown or uninitialized .

Nets Represents a hardware wire Driven by logic Value `z¶ (high-impedance) when unconnected Initial value is x (unknown) Types of nets µwire¶ .

Register Variable that stores value Can be a register (value holding unit) in real hardware NOTE: It can be also combinational logic according to the description Only one type: µreg¶ .

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Vector and array data type Vector represents bus Left number is MS bit Vector assignment by position .

Array is a collection of the same data type Multi-dimensional array is not supported Cannot access array subfield or entire array at once Array for real data type is not supported .

a <= 2¶x7A. // binary . // bit string hex ³01111010´ a <= 3¶o172. // octal (base 8) a <= 8¶b01111010.

OPERATORS Logical operators Result in one bit value .

Bitwise operators (infix): Operation on bit by bit basis .

Reduction operators (prefix): Result in one bit value .

always fills zero .Shift operators Result in the same size.

*. >=. /. } Replication: {n{X}} Relational operators: >. - . ! =. -. Arithmetic operators: +. % Unary : +. <.Concatenation operators: {. <= Equality operators: = =.

#2 refers to 2 time units SUM must be ³net´ type . but outside procedures.Behavioral constructs Continuous assignment with µassign¶ keyword. Inside a module. LHS of continuous assignment must be a `net¶ type. µ timescale 1ns / 1ns For ex : assign #2 SUM = A ^ B.

Time Units for #delay Specify by: `timescale <time_unit> / <time_precision> Unit of Measurement seconds milliseconds microseconds nanoseconds picoseconds femtoseconds Abbreviation s ms us ns ps fs .

Example: `timescale 10 ns / 1 ns // Each time unit is 10 ns. maintained to a precision of 1 ns .

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`real¶. Initial blocks start execution at simulation time zero and finish when their last statement executes. LHS of procedural assignment must be a reg¶.`integer¶.`time¶ type.µinitial¶ block One-time sequential activity flow from simulation start. .

`integer¶. LHS of procedural assignment must be a reg¶. .`real¶.`time¶ type.µalways¶ block Cyclic (repetitive) sequential activity flow Always blocks start execution at simulation time zero and continue until simulation finishes.

Events @ When the control meet `Event¶. . it waits until required event occurs.

2 : 1 mux Example Write a verilog code for 8 : 1 mux ( in syllabus) .

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Control Statements If-else-if .

Case .

¶ .µ(expression) ? statement : statement.

i = i + 1 ) begin output = i. i <= 15 . #10. end . output. for ( i = 0 .For Loops A increasing sequence of values on an output reg [3:0] i.

end . i = 0. output.While Loops A increasing sequence of values on an output reg [3:0] i. #10 i = i + 1. while (I <= 15) begin output = i.

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T Flip-Flop module tff_logic (input t. end endmodule . input clk. output q). always @(posedge clk) begin if (t == 1¶b1) q <= not (q). else q <= q.

else begin if (init == 1¶b1) q <= 8¶b11111111. input clk. Synchronous Preset module reg_logic (input d [0:7]. input reset. Asynchronous Reset. output q [0:7]).8-bit Register. // decimal -1 else q <= d. end end endmodule . always @(posedge clk. input init. posedge reset) begin if (reset == 1¶b1) q <= 8¶b0.

cout.x.x. assign cout = x & y | x & cin | y & cin.sum.y.cin.y. output sum. //logical assignment assign sum = x ^ y ^ cin.y.cout. input x. //declaration for continuous assignment wire cin.cout.Full Adder from Logical Operations module ADD_FULL_RTL (sum. endmodule .cin).

carryIn). ac). bc ac ab ca r r yO u t endmodule lis t toof fggaa te in sst t ance ss te in an ce lis oof fssam eef f u ncc t ionn am u n t io 8/20/2 007 aIn p u t ca r r yIn im pp lic itw ire im lic it w ire dd e cla r at io n s e cla r at io n s Thom as: Digi tal Sy stem s Design Lecture 8 b In p u t 19 . bInput. aInput. aInput. carryIn). bc. aInput. sum . (ab. su m in ss t a nce nnam ee s in t a n ce am s aa n d dd e la ys n d e la ys oo p io nn a l p t t io a l (sum . bInput). (ac. carryIn). (bc. ab. carryIn). aInput.VERILOG CODE FOR 1 BIT FULL ADDER Some More Gate Level Examples Q An adder module adder (output input xor or and carryOut. bInput. (carryOut. bInput.

output [7:0] Q. else tmp = tmp + 1'b1. endmodule . reg [7:0] tmp. CLR. module counter (C.Verilog code for a 8-bit Up counter with asynchronous clear. CLR. Q). end assign Q = tmp. always @(posedge C or posedge CLR) begin if (CLR) tmp = 8'b00000000. input C.

In Conclusion ‡ Verilog is widely used because it solves a problem ‡ Good simulation speed that continues to improve ‡ Designers use a well-behaved subset of the language ‡ Makes a reasonable specification language for logic synthesis ‡ Logic synthesis one of the great design automation success stories .

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