VLSI Technology

Scaling s Moore’s Law s 3D VLSI

The beginning
Microprocessors are essential to many of the products we use every day such as TVs, cars, radios, home appliances and of course, computers. Transistors are the main components of microprocessors. At their most basic level, transistors may seem simple. But their development actually required many years of painstaking research. Before transistors, computers relied on slow, inefficient vacuum tubes and mechanical switches to process information. In 1958, engineers managed to put two transistors onto a Silicon crystal and create the first integrated circuit, which subsequently led to the first


Transistor Size Scaling

performance improves as size is decreased: shorter switching time, lower power consumption.

2 orders of magnitude reduction in transistor size in

which are round polished disks made of silicon. Wafer size: Wafers. . Manufacturing process: A new manufacturing process called 130 nanometer process technology (a nanometer is a billionth of a meter) allows Intel today to manufacture chips with circuitry so small it would take almost 1. This new 130-nanometer process has 60nm gate-length transistors and six layers of copper interconnect. We continue to build smaller and smaller transistors that are faster and faster. with a gate length of 15nm. and now to 15 nanometer gates. This process is producing microprocessors today with millions of transistors and running at multi-gigahertz clock speeds.Significant Breakthroughs Transistor size: Intel’s research labs have recently shown the world’s smallest transistor.000 of these "wires" placed side-by-side to equal the width of a human hair. Intel has begun using a 300 millimeter (about 12 inches) diameter silicon wafer size. provide the base on which chips are manufactured. up from the previous wafer size of 200mm (about 8 inches). We've reduced the size from 70 nanometer to 30 nanometer to 20 nanometer. Use a bigger wafer and you can reduce manufacturing costs.

130 M Tr. manufacturability – clock distribution Year 1997 1998 1999 2002 Tech.35 0. 0.Major Design Challenges s Microscopic issues – ultra-high speeds – power dissipation and supply rail drop – growing importance of interconnect – noise. crosstalk – reliability.18 0. 32 M Tr.25 0. portability – systems on a chip (SoC) – tool interoperability Staff Size 210 270 360 800 Staff Costs $90 M $120 M $160 M $360 M .13 Complexity 13 M Tr. Frequency 400 MHz 500 MHz 600 MHz 800 MHz s Macroscopic issues – time-to-market – design complexity (millions of gates) – high levels of abstractions – design for test – reuse and IP. 20 M Tr.

gallium arsenide s Variety of logic families .Integrated Circuits s Digital logic is implemented using transistors in integrated circuits containing many gates. – – – – small-scale integrated circuits (SSI) contain 10 gates or less medium-scale integrated circuits (MSI) contain 10-100 gates large-scale integrated circuits (LSI) contain up to 104 gates very large-scale integrated circuits (VLSI) contain >104 gates s Improvements in manufacturing lead to ever smaller transistors allowing more per chip.transistor-transistor logic CMOS .complementary metal-oxide semiconductor ECL . doubles every 18 months or so – – – – TTL . – >107 gates/chip now possible.emitter-coupled logic GaAs .

Sodini: Microelectronics:An Integrated Approach. Prentice Hall . The wafer then has to be tested and the chips diced up and the good chips mounted and wire‑bonded in different types of IC package and tested again before being shipped out. From Howe. The end result are wafers each containing a regular array of the same IC chip or die.What are shown on previous diagrams cover only the so called front‑end processing ‑ fabrication steps that go towards forming the devices and inter‑connections between these devices to produce the functioning IC's.

release dates: – Noticed number of transistors doubling with release of each new IC generation – release dates (separate generations) were all 18-24 months apart s Moore’s Law: – The number of transistors on an integrated circuit will double every 18 months s s s s The level of integration of silicon technology as measured in terms of number of devices per IC This comes about in two ways – size reduction of the individual devices and increase in the chip or dice size As an indication of size reduction. 1 mil = 25 mm) up to early 1970’s. it is interesting to note that feature size was measured in mils (1/1000 inch. whereas now all features are measured in mm’s (1 mm = 10-6 m or 10-4 cm) Semiconductor industry has followed this prediction with surprising accuracy .# of transistors on ICs vs.Chairman Emeritus of Intel Corporation 1965 . Moore .Moore’s Law s s Gordon E.observed trends in industry .

com) .. Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months • i.2001 – 140 Million transistor (HP PA-8500) Source: Intel web page (www.Moore’s Law • • In 1965.1971 – 42 Million.intel. 2 GHz clock (Intel P4) .e. 1 MHz clock (Intel 4004) . grow exponentially with time Amazing visionary – million transistor/chip barrier was crossed in the 1980’s. – 2300 transistors.

500.Moore’s Law s From Intel’s 4040 (2300 transistors) to Pentium II (7.000 transistors) and beyond Relative sizes of ICs in graph .

13 micron. the smallest feature size has been reducing every year. the pace slowed down a bit. Classic example is the case of memory chips: Gordon Moore of Intel in early 1970s found that: “density” (bits per chip) growing at the rate of four times in 3 to 4 years . Currently (2002) the smallest feature size is about 0. At the same time the number transistors per chip is increasing due to feature size reduction and increase in chip area. In subsequent years.Ever since the invention of integrated circuit. data density has doubled approximately every 18 months – current definition of Moore’s Law. .often referred to as Moore’s Law.

reached in 2001 + 1. .Limits of Moore’s Law? s Growth expected until 30 nm gate length (currently: 180 nm) – size halved every 18 mos.5 log2((180/30)2) = 2009 s – what then? Paradigm shift needed in fabrication process .

Technological Background of the Moore’s Law s s s To accommodate this change. line width etc) measured in nanometres or 10-9 metres . the size of the silicon wafers on which the integrated circuits are fabricated have also increased by a very significant factor – from the 2 and 3 in diameter wafers to the 8 in (200 mm) and 12 in (300 mm) diameter wafers The latest catch phrase in semiconductor technology (as well as in other material science) is nanotechnology – usually referring to GaAs devices based on quantum mechanical phenomena These devices have feature size (such as film thickness.

− --------------------------die area √ 2 × die area die yield = (1 + (defects per unit area × die area)/α )-α .Recurring Costs cost of die + cost of die test + cost of packaging variable cost = ---------------------------------------------------------------final test yield cost of wafer cost of die = ----------------------------------dies per wafer × die yield π × (wafer diameter/2)2 π × wafer diameter dies per wafer = ---------------------------------.

5 cm2.Yield Example  Example q q q q wafer size of 12 inches. die size of 2. α = 3 (measure of manufacturing process complexity) 252 dies/wafer (remember. 1 defects/cm2. wafers round & dies square) die yield of 16% 252 x 16% = only 40 dies/wafer die yield !  Die cost is strong function of die area  proportional to the third or fourth power of the die area .

Intel 4004 Microprocessor .

Intel Pentium (IV) Microprocessor .

Intel 1990 Year 2000 2010 .Die Size Growth Die size grows by 14% to satisfy Moore’s Law 100 Die size (mm) 10 8080 8008 4004 1 1970 1980 8086 8085 286 386 P6 486 Pentium ® proc ~7% growth per year ~2X growth in 10 years Courtesy.

1 1970 386 8085 8086 286 8080 8008 4004 1980 1990 Year 2000 2010 Courtesy.Clock Frequency Lead microprocessors frequency doubles every 2 years 10000 1000 2X every 2 years P6 486 Pentium ® proc Frequency (Mhz) 100 10 1 0. Intel .

70 0.5 43 81 121 196 234 256 296 360 181 115 66 53 48 40 71% 54% 28% 27% Die cost $4 $12 $53 $73 19% $149 13% $272 9% $417 .0 1.2 1.0 1.80 0.90 0.0 1.3 1.70 0.80 0.80 Wafer Defects/c Area Dies/wa Yield cost m2 (mm2) fer $900 $1200 $1700 $1300 $1500 $1700 $1500 1.6 1.80 0.Examples of Cost Metrics (1994) Chip 386DX 486DX2 PowerPC 601 HP PA 7100 DEC Alpha Super SPARC Pentium Metal layers 2 3 4 3 3 3 3 Line width 0.

each a few µ m in size – applications wide ranging: most electronic logic devices . complex circuitry using modified semiconductor material – integrated circuit (IC) may contain millions of transistors.VLSI s Very Large Scale Integration – design/manufacturing of extremely small.

Bardeen.CDC 1604 . Brattain (Bell Laboratories) first transistor – 1956 Nobel Physics Prize Late 1950s .Shockley. especially for radar 1940 .purification of Si advances to acceptable levels for use in electronics 1958 .first transistorized computer .Seymour Cray (Control Data Corporation) .Russell Ohl (Bell Laboratories) .first pn junction 1948 .Origins of VLSI s s s s s Much development motivated by WWII need for improved electronics.

Robert Norton Noyce (founder.Noyce.) s s s s s 1959 .2300 transistors on 9 mm2 Since then . Gordon E.Ted Hoff (Intel) .continued improvement in technology has allowed for increased performance as predicted by Moore’s Law .improved integrated circuit 1968 .Jack St.10 components on 9 mm2 1959 .Origins of VLSI (Cont.first integrated circuit . Moore found Intel 1971 . Claire Kilby (Texas Instruments) . Fairchild Semiconductor) .first microprocessor (4004) .

Three Dimensional VLSI s s The fabrication of a single integrated circuit whose functional parts (transistors. etc) extend in three dimensions The vertical orientation of several bare integrated circuits in a single package .

Advantages of 3D VLSI s Speed . – Delay depends on resistance/capacitance of interconnections – resistance proportional to interconnection length .the time required for a signal to travel between the functional circuit blocks in a system (delay) reduced.

Advantages of 3D VLSI s s Noise .unwanted disturbances on a useful signal – reflection noise (varying impedance along interconnect) – crosstalk noise (interference between interconnects) – electromagnetic interference (EMI) (caused by current in pins) 3D chips – fewer. shorter interconnects – fewer pins .

Advantages of 3D VLSI s Power consumption – power used charging an interconnect capacitance » P = fCV2 – power dissipated through resistive material » P = V2/R – capacitance/resistance proportional to length – reduced interconnect lengths will reduce power .

Advantages of 3D VLSI s Interconnect capacity (connectivity) – more connections between chips – increased functionality. ease of design .

Advantages of 3D VLSI s Printed circuit board size/weight – planar size of PCB reduced with negligible IC height increase – weight reduction due to more circuitry per package/smaller PCBs – estimated 40-50 times reduction in size/weight .

3D VLSI .Challenges and Solutions s s Challenge: Thermal management – smaller packages – increased circuit density – increased power density Solutions: – circuit layout (design stage) » high power sections uniformly distributed – advancement in cooling techniques (heat pipes) .

. TI.Industry s s s Mitsubishi. CTS Microelectronics. Irvine Sensors.Influential Participants . others. Hitachi.. Intel. – high density memories AT&T – high density “multiprocessor” Many other applications/participants .

3D VLSI many advantages over 2D VLSI – economic limitations of fabrication overhaul will be overcome by market demand – s Three Dimensional VLSI may be the savior of Moore’s Law .Three Dimensional VLSI s s s Moore’s Law approaching physical limit Increased performance expected by market Paradigm shift needed .

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