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4 Manual Copyright © 2009 UC Berkeley
BSIM4.6.4 MOSFET Model
User’s Manual
Tanvir Hasan Morshed, Wenwei (Morgan) Yang, Mohan V. Dunga, Xuemei
(Jane) Xi, Jin He,
Weidong Liu, Kanyu, M. Cao, Xiaodong Jin, Jeff J. Ou, Mansun Chan,
Ali M. Niknejad, Chenming Hu
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley, CA 94720
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
Developers:
BSIM4.6.4 Developers:
Professor Chenming Hu (project director), UC Berkeley
Professor Ali M. Niknejad(project director), UC Berkeley
Wenwei Yang, UC Berkeley
Darsen Lu, UC Berkeley
Developers of BSIM4 Previous Versions:
Dr. Weidong Liu, Synopsys
Dr. Xiaodong Jin, Marvell
Dr. Kanyu (Mark) Cao, UC Berkeley
Dr. Jeff J. Ou, Intel
Dr. Jin He, UC Berkeley
Dr. Xuemei (Jane) Xi, UC Berkeley
Mohan V. Dunga, UC Berkeley
Professor Ali M. Niknejad, UC Berkeley
Professor Chenming Hu, UC Berkeley
Web Sites:
BSIM4 web site with BSIM source code and documents:
http://wwwdevice.eecs.berkeley.edu/~bsim3/bsim4.html
Compact Model Council: http://www.eigroup.org/CMC/default.htm
Technical Support:
Tanvir Hasan Morshed: morshedt@eecs.berkeley.edu
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
Acknowledgement:
The development of BSIM4.6.4 benefited from the input of many BSIM
users, especially the Compact Model Council (CMC) member companies.
The developers would like to thank Xingming Liu and Jushan Xie at
Cadence, Joddy Wang, Robin Tan, Jane Xi and Weidong Liu at Synopsys,
Ben Gu at Freescale, James Ma at ProPlus Design, Joe Watts at IBM,
Geoffrey Coram at Analog Device, Weihung Chen at UC Berkeley, for
their valuable assistance in identifying the desirable modifications and
testing of the new model.
The BSIM project is partially supported by SRC and CMC.
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
Contents
Chapter 1: Effective Oxide Thickness, Channel Length and Channel Width .................... 1
1.1 Gate Dielectric Model ............................................................................................... 3
1.2 PolySilicon Gate Depletion...................................................................................... 4
1.3 Effective Channel Length and Width........................................................................ 7
Chapter 2: Threshold Voltage Model ............................................................................... 10
2.1 LongChannel Model With Uniform Doping.......................................................... 10
2.2 NonUniform Vertical Doping................................................................................ 11
2.3 NonUniform Lateral Doping: Pocket (Halo) Implant............................................ 13
2.4 ShortChannel and DIBL Effects ............................................................................ 14
2.5 NarrowWidth Effect............................................................................................... 16
Chapter 3: Channel Charge and Subthreshold Swing Models.......................................... 19
3.1 Channel Charge Model............................................................................................ 19
3.2 Subthreshold Swing n.............................................................................................. 22
Chapter 4: Gate Direct Tunneling Current Model ............................................................ 24
4.1 Model Selectors....................................................................................................... 25
4.2 Voltage Across Oxide V
ox
....................................................................................... 25
4.3 Equations for Tunneling Currents........................................................................... 26
4.3.1 GatetoSubstrate Current (I
gb
= I
gbacc
+ I
gbinv
)................................................. 26
4.3.2 GatetoChannel Current (I
gc0
) and GatetoS/D (I
gs
and I
gd
) ........................... 27
4.3.3. Partition of I
gc
.................................................................................................. 28
Chapter 5: Drain Current Model ....................................................................................... 30
5.1 Bulk Charge Effect.................................................................................................. 30
5.2 Unified Mobility Model .......................................................................................... 30
5.3 Asymmetric and BiasDependent Source/ Drain Resistance Model....................... 33
5.4 Drain Current for Triode Region............................................................................. 35
5.5 Velocity Saturation.................................................................................................. 36
5.6 Saturation Voltage V
dsat
........................................................................................... 37
5.6.1 Intrinsic case..................................................................................................... 37
5.6.2 Extrinsic Case................................................................................................... 37
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
5.6.3V
dseff
Formulation............................................................................................... 38
5.7 SaturationRegion Output Conductance Model ...................................................... 38
5.7.1 Channel Length Modulation (CLM)................................................................. 40
5.7.2 DrainInduced Barrier Lowering (DIBL) ......................................................... 40
5.7.3 Substrate Current Induced Body Effect (SCBE) .............................................. 41
5.7.4 DrainInduced Threshold Shift (DITS) by Pocket Implant ............................. 43
5.8 SingleEquation Channel Current Model ................................................................ 43
5.9 New Current Saturation Mechanisms: Velocity Overshoot and Source End Velocity
Limit Model................................................................................................................... 44
5.9.1 Velocity Overshoot .....................................................................................44
5.9.2 Source End Velocity Limit Model.................................................................... 44
Chapter 6: Body Current Models...................................................................................... 46
6.1 I
ii
Model................................................................................................................... 46
6.2 I
GIDL
and I
GISL
Model ............................................................................................... 46
Chapter 7: Capacitance Model.......................................................................................... 49
7.1 General Description................................................................................................. 49
7.2 Methodology for Intrinsic Capacitance Modeling .................................................. 50
7.2.1 Basic Formulation............................................................................................. 50
7.2.2 Short Channel Model........................................................................................ 52
7.2.3 Single Equation Formulation............................................................................ 54
7.2.4.Charge partitioning........................................................................................... 55
7.3 ChargeThickness Capacitance Model (CTM) ....................................................... 56
7.4 Intrinsic Capacitance Model Equations................................................................... 60
7.4.1 capMod = 0....................................................................................................... 60
7.4.2 capMod = 1....................................................................................................... 62
7.4.3 capMod = 2....................................................................................................... 64
7.5 Fringing/Overlap Capacitance Models.................................................................... 66
7.5.1 Fringing capacitance model.............................................................................. 66
7.5.2 Overlap capacitance model............................................................................... 67
Chapter 8: New Material Models...................................................................................... 70
8.1 Model Selector ........................................................................................................ 70
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
8.2 NonSilicon Channel ............................................................................................... 70
8.3 NonSiO
2
Gate insulator.......................................................................................... 71
8.4 NonPoly Silicon Gate Dielectric............................................................................ 72
Chapter 9: HighSpeed/RF Models................................................................................... 74
9.1 ChargeDeficit NonQuasiStatic (NQS) Model..................................................... 74
9.1.1 Transient Model................................................................................................ 75
9.1.2 AC Model ........................................................................................................ 77
9.2 Gate Electrode Electrode and IntrinsicInput Resistance (IIR) Model ................... 78
9.2.1 General Description.......................................................................................... 78
9.2.2 Model Option and Schematic ........................................................................... 78
9.3 Substrate Resistance Network................................................................................. 80
9.3.1 General Description.......................................................................................... 80
9.3.2 Model Selector and Topology .......................................................................... 80
Chapter 10: Noise Modeling............................................................................................. 84
10.1 Flicker Noise Models ............................................................................................ 84
10.1.1 General Description........................................................................................ 84
10.1.2 Equations ........................................................................................................ 84
10.2 Channel Thermal Noise......................................................................................... 86
10.3 Other Noise Sources Modeled............................................................................... 88
Chapter 11: Asymmetric MOS Junction Diode Models................................................... 89
11.1 Junction Diode IV Model...................................................................................... 89
11.1.1 Source/Body Junction Diode.......................................................................... 89
11.1.2 Drain/Body Junction Diode............................................................................ 91
11.1.3 Total Junction Source/Drain Diode Including Tunneling .............................. 92
11.2 Junction Diode CV Model..................................................................................... 93
11.2.1 Source/Body Junction Diode.......................................................................... 93
11.2.2 Drain/Body Junction Diode............................................................................ 94
Chapter 12: LayoutDependent Parasitics Models ........................................................... 96
12.1 Geometry Definition ............................................................................................. 96
12.2 Model Formulation and Options ........................................................................... 97
12.2.1 Effective Junction Perimeter and Area........................................................... 97
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
12.2.2 Source/Drain Diffusion Resistance ................................................................ 98
12.2.3 Gate Electrode Resistance .............................................................................. 99
12.2.4 Option for Source/Drain Connections ............................................................ 99
12.2.5 Option for Source/Drain Contacts ................................................................ 100
Chapter 13: Temperature Dependence Model ................................................................ 101
13.1 Temperature Dependence of Threshold.............................................................. 101
13.2 Temperature Dependence of Mobility ................................................................ 101
13.3 Temperature Dependence of Saturation Velocity............................................... 102
13.4 Temperature Dependence of LDD...................................................................... 103
13.5 Temperature Dependence of Junction................................................................. 104
13.6 Temperature Dependence of Junction Diode CV ............................................... 107
13.7 Temperature Dependences of E
g
and n
i
.............................................................. 108
Chapter 14: Stress Effect Model ..................................................................................... 110
14.1 Stress Effect Model Development....................................................................... 110
14.1.1 Mobilityrelated Equations........................................................................... 111
14.1.2 Vthrelated Equations................................................................................... 113
14.1.3 Multiple Finger Device................................................................................. 114
14.2 Effective SA and SB for Irregular LOD.............................................................. 114
Chapter 15: Well Proximity Effect Model...................................................................... 116
15.1 Well Proximity Effect Model .............................................................................. 117
Chapter 16: Parameter Extraction Methodology ............................................................ 118
16.1 Optimization strategy.......................................................................................... 118
16.2 Extraction Strategy.............................................................................................. 119
16.3 Extraction Procedure........................................................................................... 119
16.3.1 Extraction Requirements .............................................................................. 119
16.3.2 Optimization................................................................................................ 121
16.3.3 Extraction Routine........................................................................................ 123
Appendix A: Complete Parameter List........................................................................... 131
A.1 BSIM4.6.1 Model Selectors/Controller................................................................ 131
A.2 Process Parameters............................................................................................... 134
A.3 Basic Model Parameters....................................................................................... 136
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
A.4 Parameters for Asymmetric and BiasDependent R
ds
Model ............................... 142
A.5 Impact Ionization Current Model Parameters ...................................................... 143
A.6 GateInduced Drain Leakage Model Parameters ................................................. 144
A.7 Gate Dielectric Tunneling Current Model Parameters......................................... 145
A.8 Charge and Capacitance Model Parameters......................................................... 148
A.9 HighSpeed/RF Model Parameters....................................................................... 150
A.10 Flicker and Thermal Noise Model Parameters................................................... 153
A.11 LayoutDependent Parasitic Model Parameters................................................. 154
A.12 Asymmetric Source/Drain Junction Diode Model Parameters .......................... 155
A.13 Temperature Dependence Parameters ................................................................ 159
A.14 Stress Effect Model Parameters ......................................................................... 161
A.15 WellProximity Effect Model Parameters.......................................................... 163
A.16 dW and dL Parameters........................................................................................ 164
A.17 Range Parameters for Model Application.......................................................... 166
A.18 Notes 18 ............................................................................................................ 167
Appendix B: Core Parameters ........................................................................................ 169
Appendix C: References ................................................................................................. 170
Effective Oxide Thickness, Channel Length and Channel Width
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 1
Chapter 1: Effective Oxide Thickness,
Channel Length and Channel Width
BSIM4, as the extension of BSIM3 model, addresses the MOSFET physical
effects into sub100nm regime. The continuous scaling of minimum feature
size brought challenges to compact modeling in two ways: One is that to
push the barriers in making transistors with shorter gate length, advanced
process technologies are used such as nonuniform substrate doping. The
second is its opportunities to RF applications.
To meet these challenges, BSIM4 has the following major improvements
and additions over BSIM3v3: (1) an accurate new model of the intrinsic
input resistance for both RF, highfrequency analog and highspeed digital
applications; (2) flexible substrate resistance network for RF modeling; (3) a
new accurate channel thermal noise model and a noise partition model for
the induced gate noise; (4) a nonquasistatic (NQS) model that is consistent
with the Rgbased RF model and a consistent AC model that accounts for
the NQS effect in both transconductances and capacitances. (5) an accurate
gate direct tunneling model for multiple layer gate dielectrics; (6) a
comprehensive and versatile geometrydependent parasitics model for
various source/drain connections and multifinger devices; (7) improved
model for steep vertical retrograde doping profiles; (8) better model for
pocketimplanted devices in V
th
, bulk charge effect model, and Rout; (9)
asymmetrical and biasdependent source/drain resistance, either internal or
external to the intrinsic MOSFET at the user's discretion; (10) acceptance of
Effective Oxide Thickness, Channel Length and Channel Width
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 2
anyone of the electrical, physical gate oxide thickness or equivalent oxide
thickness as the model input at the user's choice in a physically accurate
manner; (11) the quantum mechanical chargelayerthickness model for both
IV and CV; (12) a more accurate mobility model for predictive modeling;
(13) a improved gateinduced drain/source leakage (GIDL/GISL) current
model considering the work function difference between drain/source and
gate; (14) an improved unified flicker (1/f) noise model, which is smooth
over all bias regions and considers the bulk charge effect; (15) different
diode IV and CV chrematistics for source and drain junctions; (16) junction
diode breakdown with or without current limiting; (17) dielectric constant of
the gate dielectric as a model parameter; (18) A new scalable stress effect
model for process induced stress effect; device performance becoming thus
a function of the active area geometry and the location of the device in the
active area; (19) A unified currentsaturation model that includes all
mechanisms of current saturation velocity saturation, velocity overshoot
and source end velocity limit; (20) A new temperature model format that
allows convenient prediction of temperature effects on saturation velocity,
mobility, and S/D resistances; (21) A improved material model that is
suitable to describe nonSiO
2
gate insulator, nonpolySi gate and nonSi
channel; (22) A new threshold voltage definition is introduced into CV
model to improve subthreshold fitting; (23) an improved model predicts
well the mobility behavior in high k/metal gate structure; (24) a width
dependent trapassistant tunneling model is introduced to describe the
current density enhancement in narrow device.
Effective Oxide Thickness, Channel Length and Channel Width
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 3
1.1 Gate Dielectric Model
As the gate oxide thickness is vigorously scaled down, the finite charge
layer thickness can’t be ignored [1]. BSIM4 models this effect in both IV
and CV. For this purpose, BSM4 accepts two of the following methods as
the model inputs:
• mrtlMod=0, the electrical gate oxide thickness TOXE
1
, the
physical gate oxide thickness TOXP, and their difference DTOX
= TOXE – TOXP are the input parameters. Based on these
parameters, the effect of effective gate oxide capacitance C
oxeff
on IV and CV is modeled [2].
• mrtlMod=1, for the highk gate dielectric, the equivalent SiO
2
thickness (EOT) is the input parameter. Based on EOT, TOXP
could be calculated as following:
, 0
3.9
gs ds bs
DC
V VDDEOT V V
TOXP EOT X
EPSRSUB
= = =
= − ×
(1.1)
In this case, TOXE is equal to EOT. It is worth pointing out that
the new model parameters: the effective width (Weffeot), length
(Leffeot), temperature (Tempeot) and bias condition (Vddeot)
for EOT extraction are also needed in this calculation.
Here, mrtlMod is a global selector which is used to turn on or off the new
material models. This selector will be discussed in detail in Chapter 8.
Figure 1.1 illustrates the algorithm and options for specifying the gate
dielectric thickness and calculation of the gate dielectric capacitance for
BSIM4 model evaluation.
1
Capital and italic alphanumericals in this manual are model parameters.
Effective Oxide Thickness, Channel Length and Channel Width
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 4
Figure 1.1 Algorithm for BSIM4 gate dielectric model.
1.2 PolySilicon Gate Depletion
When a gate voltage is applied to the polysilicon gate, e.g. NMOS with n
+
polysilicon gate, a thin depletion layer will be formed at the interface
between the polysilicon and the gate oxide. Although this depletion layer is
very thin due to the high doping concentration of the polysilicon gate, its
effect cannot be ignored since the gate oxide thickness is small.
Effective Oxide Thickness, Channel Length and Channel Width
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 5
Figure 1.2 shows an NMOSFET with a depletion region in the n
+
poly
silicon gate. The doping concentration in the n
+
polysilicon gate is NGATE
and the doping concentration in the substrate is NSUB. The depletion width
in the poly gate is X
p
. The depletion width in the substrate is X
d
. The positive
charge near the interface of the polysilicon gate and the gate oxide is
distributed over a finite depletion region with thickness X
p
. In the presence
of the depletion region, the voltage drop across the gate oxide and the
substrate will be reduced, because part of the gate voltage will be dropped
across the depletion region in the gate. That means the effective gate voltage
will be reduced.
NGATE
Figure 1.2. Charge distribution in a MOSFET with the poly gate depletion effect. The
device is in the strong inversion region.
The effective gate voltage can be calculated in the following manner.
Assume the doping concentration in the poly gate is uniform. The voltage
drop in the poly gate V
poly
can be calculated as
2
0.5
2
poly
poly poly poly
si
qNGATE X
V X E
ε
⋅
= =
(1.2)
Effective Oxide Thickness, Channel Length and Channel Width
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 6
where E
poly
is the maximum electrical field in the poly gate. The boundary
condition at the interface of poly gate and the gate oxide is
2
ox si poly si poly
EPSROX E E q NGATE V ε ε ⋅ = = ⋅ (1.3)
where E
ox
is the electric field in the gate oxide. The gate voltage satisfies
gs FB s poly ox
V V V V − −Φ = +
(1.4)
where V
ox
is the voltage drop across the gate oxide and satisfies V
ox
=
E
ox
TOXE.
From (1.2) and (1.3), we can obtain
( )
2
0
gs FB s poly poly
a V V V V − −Φ − − =
(1.5)
where
2
2
2
si
EPSROX
a
q NGATE TOXE ε
=
⋅
(1.6)
By solving (1.5), we get the effective gate voltage V
gse
which is equal to
( )
2
2
2 2
2
1 1
gs s
si
gse s
si
EPSROX V VFB
q NGATE TOXE
V VFB
EPSROX q NGATE TOXE
ε
ε
 
− −Φ
⋅

= + Φ + + −
 ⋅
\ .
(1.7)
The above discussion is only suitable when mrtlMod=0. Considering the
nonsilicon channel or highk gate insulator, V
gse
is modified as follows:
( )
2
2
2
1 1
gs s
gate
gse s
gate
coxe V VFB
q NGATE
V VFB
coxe q NGATE
ε
ε
 
− −Φ

= + Φ + + −

\ .
(1.8)
Note: Here 0
si
EPSRGATE EPS ε = ⋅ . EPSRGATE =0 means the metal gate,
and there is no depletion effect.
Effective Oxide Thickness, Channel Length and Channel Width
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 7
1.3 Effective Channel Length and Width
The effective channel length and width used in the drain current model are
given below where XL and XW are parameters to account the channel
length/width offset due to mask/etch effect
2
eff drawn
L L XL dL = + −
(1.9)
2
drawn
eff
W
W XW dW
NF
= + −
(1.10)
' 2 '
drawn
eff
W
W XW dW
NF
= + −
(1.11)
The difference between (1.10) and (1.11) is that the former includes bias
dependencies. NF is the number of device fingers. dW and dL are modeled
by
( )
'
'
gsteff s bseff s
WLN WWN WLN WWN
dW dW DWG V DWB V
WL WW WWL
dW WINT
L W L W
= + ⋅ + Φ − − Φ
= + + +
(1.12)
LLN LWN LLN LWN
LL LW LWL
dL LINT
L W L W
= + + +
WINT represents the traditional manner from which "delta W" is extracted
(from the intercept of straight lines on a 1/R
ds
~W
drawn
plot). The parameters
DWG and DWB are used to account for the contribution of both gate and
substrate bias effects. For dL, LINT represents the traditional manner from
which "delta L" is extracted from the intercept of lines on a R
ds
~L
drawn
plot).
The remaining terms in dW and dL are provided for the convenience of the
user. They are meant to allow the user to model each parameter as a function
of W
drawn
, L
drawn
and their product term. By default, the above geometrical
dependencies for dW and dL are turned off.
Effective Oxide Thickness, Channel Length and Channel Width
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 8
MOSFET capacitances can be divided into intrinsic and extrinsic
components. The intrinsic capacitance is associated with the region between
the metallurgical source and drain junction, which is defined by the effective
length (L
active
) and width (W
active
) when the gate to source/drain regions are
under flatband condition. L
active
and W
active
are defined as
2
active drawn
L L XL dL = + − (1.13)
2
drawn
active
W
W XW dW
NF
= + −
(1.14)
LLN LWN LLN LWN
LLC LWC LWLC
dL DLC
L W L W
= + + +
(1.15)
WLN WWN WLN WWN
WLC WWC WWLC
dW DWC
L W L W
= + + +
(1.16)
The meanings of DWC and DLC are different from those of WINT and LINT
in the IV model. Unlike the case of IV, we assume that these dimensions
are bias dependent. The parameter δL
eff
is equal to the source/drain to gate
overlap length plus the difference between drawn and actual POLY CD due
to processing (gate patterning, etching and oxidation) on one side.
The effective channel length L
eff
for the IV model does not necessarily carry
a physical meaning. It is just a parameter used in the IV formulation. This
L
eff
is therefore very sensitive to the IV equations and also to the conduction
characteristics of the LDD region relative to the channel region. A device
with a large L
eff
and a small parasitic resistance can have a similar current
drive as another with a smaller L
eff
but larger R
ds
.
The L
active
parameter extracted from capacitance is a closer representation of
the metallurgical junction length (physical length). Due to the graded
source/drain junction profile, the source to drain length can have a very
Effective Oxide Thickness, Channel Length and Channel Width
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 9
strong bias dependence. We therefore define L
active
to be that measured at
flatband voltage between gate to source/drain. If DWC, DLC and the
length/width dependence parameters (LLC, LWC, LWLC, WLC, WWC and
WWLC) are not specified in technology files, BSIM4 assumes that the DC
biasindependent L
eff
and W
eff
will be used for the capacitance models, and
DWC, DLC, LLC, LWC, LWLC, WLC, WWC and WWLC will be set to the
values of their DC counterparts.
BSIM4 uses the effective source/drain diffusion width W
effcj
for modeling
parasitics, such as source/drain resistance, gate electrode resistance, and
gateinduced drain leakage (GIDL) current. W
effcj
is defined as
2
drawn
effcj WLN WWN WLN WWN
W WLC WWC WWLC
W XW DWJ
NF L W L W
 
= + − ⋅ + + +

\ .
(1.17)
Note: Any compact model has its validation limitation, so does BSIM4.
BSIM4 is its own valid designation limit which is larger than the warning
limit, shown in following table. For users’ reference, the fatal limitation in
BSIM4 is also shown.
Parameter name
Designed
Limitation(m)
Warning
Limitation(m)
Fatal
Limitation(m)
Leff 1e8 1e9 0
LeffCV 1e8 1e9 0
Weff 1e7 1e9 0
WeffCV 1e7 1e9 0
Toxe 5e10 1e10 0
Toxp 5e10 1e10 0
Toxm 5e10 1e10 0
Threshold Voltage Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 10
Chapter 2: Threshold Voltage Model
2.1 LongChannel Model With Uniform Doping
Accurate modeling of threshold voltage V
th
is important for precise
description of device electrical characteristics. V
th
for long and wide
MOSFETs with uniform substrate doping is given by
( )
0
th s s bs s bs s
V VFB V VTH V γ γ = + Φ + Φ − = + Φ − − Φ
(2.1)
where VFB is the flat band voltage, VTH0 is the threshold voltage of the
long channel device at zero substrate bias, and γ is the body bias coefficient
given by
2
si substrate
oxe
q N
C
ε
γ =
(2.2)
where N
substrate
is the uniform substrate doping concentration.
Equation (2.1) assumes that the channel doping is constant and the channel
length and width are large enough. Modifications have to be made when the
substrate doping concentration is not constant and/or when the channel is
short, or narrow.
Consider process variation, a new instance parameter DELVTO is added to
VTH0 as:
If VTH0 is given,
0 0 VTH VTH DELVTO = +
(2.3)
If VTH0 isn’t given,
Threshold Voltage Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 11
0
s s
VFB VFB DELVTO
VTH VFB γ
= +
= + Φ + Φ
(2.4)
2.2 NonUniform Vertical Doping
The substrate doping profile is not uniform in the vertical direction and
therefore γ in (2.2) is a function of both the depth from the interface and the
substrate bias. If N
substrate
is defined to be the doping concentration (NDEP)
at X
dep0
(the depletion edge at V
bs
= 0), V
th
for nonuniform vertical doping is
0 1
,
1
th th NDEP NDEP s bs s bs
oxe si
qD qD
V V K V V
C
ϕ ϕ
ε
 
= + + − − − −


\ .
(2.5)
where K1
NDEP
is the bodybias coefficient for N
substrate
= NDEP,
( ) ,
0 1
th NDEP NDEP s bs s
V VTH K V ϕ ϕ = + − −
(2.6)
with a definition of
0.4 ln
B
s
i
k T NDEP
q n
ϕ
 
= +

\ .
(2.7)
where n
i
is the intrinsic carrier concentration in the channel region. The
zeroth and 1st moments of the vertical doping profile in (2.5) are given by
(2.8) and (2.9), respectively, as
( ) ( ) ( ) ( )
0
0
0 00 01
0
dep dep
dep
X X
X
D D D N x NDEP dx N x NDEP dx = + = − + −
∫ ∫
(2.8)
( ) ( ) ( ) ( )
0
0
1 10 11
0
dep dep
dep
X X
X
D D D N x NDEP xdx N x NDEP xdx = + = − + −
∫ ∫
(2.9)
By assuming the doping profile is a steep retrograde, it can be shown that
D01 is approximately equal to C
01
V
bs
and that D
10
dominates D
11
; C
01
Threshold Voltage Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 12
represents the profile of the retrograde. Combining (2.5) through (2.9), we
obtain
( )
0 1 2
th s bs s bs
V VTH K V K V = + Φ − − Φ − ⋅
(2.10)
where K2 = qC
01
/ C
oxe
, and the surface potential is defined as
0.4 ln
B
s
i
k T NDEP
PHIN
q n
 
Φ = + +

\ .
(2.11)
where
10 si
PHIN qD ε = −
(2.12)
VTH0, K1, K2, and PHIN are implemented as model parameters for model
flexibility. Appendix A lists the model selectors and parameters. Detail
information on the doping profile is often available for predictive modeling.
Like BSIM3v3, BSIM4 allows K1 and K2 to be calculated based on such
details as NSUB, XT, VBX, VBM, etc. (with the same meanings as in
BSIM3v3):
2
1 2 2
s
K K VBM γ = − Φ −
(2.13)
( )
( )
( )
1 2
2
2
s s
s s s
VBX
K
VBM VBM
γ γ − Φ − − Φ
=
Φ Φ − − Φ +
(2.14)
where γ
1
and γ
2
are the body bias coefficients when the substrate doping
concentration are equal to NDEP and NSUB, respectively:
1
2
si
oxe
q NDEP
C
ε
γ =
(2.15)
2
2
si
oxe
q NSUB
C
ε
γ =
(2.16)
Threshold Voltage Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 13
VBX is the body bias when the depletion width is equal to XT, and is
determined by
2
2
s
si
qNDEP XT
VBX
ε
⋅
= Φ −
(2.17)
2.3 NonUniform Lateral Doping: Pocket (Halo)
Implant
In this case, the doping concentration near the source/drain junctions is
higher than that in the middle of the channel. Therefore, as channel length
becomes shorter, a V
th
rollup will usually result since the effective channel
doping concentration gets higher, which changes the body bias effect as well.
To consider these effects, V
th
is written as
( )
0 1 1 2
0
1 1 1
th s bs s bs
eff
s
eff
LPEB
V VTH K V K V
L
LPE
K
L
= + Φ − − Φ ⋅ + − ⋅
 
+ + − Φ 

\ .
(2.18)
In addition, pocket implant can cause significant draininduced threshold
shift (DITS) in longchannel devices [3]:
( )
( )
( )
/
1
1
ln
0 1
ds t
ds
V v
eff
th t
DVTP V
eff
e L
V DITS nv
L DVTP e
−
− ⋅
 
− ⋅

∆ = − ⋅

+ ⋅ +
\ .
(2.19)
For V
ds
of interest, the above equation is simplified and implemented as for
tempMod = 1:
( )
( )
1
ln
0 1
ds
eff
th t
DVTP V
eff
L
V DITS nv
L DVTP e
− ⋅
 

∆ = − ⋅

+ ⋅ +
\ .
(2.20)
for tempMod = 2:
Threshold Voltage Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 14
( )
( )
1
ln
0 1
ds
eff
th t
DVTP V
eff
L
V DITS nv
L DVTP e
− ⋅
 

∆ = − ⋅

+ ⋅ +
\ .
(2.21)
Note: when tempMod =2, draininduced threshold voltage shift (DITS) due
to pocket implant has no temperature dependence, so nominal temperature
(TNOM) is used as Eq.(3.22). when tempMod=0 or 1, Eq.(3.21) is used.
( )
( )
1
ln
0 1
ds
eff
th tnom
DVTP V
eff
L
V DITS nv
L DVTP e
− ⋅
 

∆ = − ⋅

+ ⋅ +
\ .
(2.22)
2.4 ShortChannel and DIBL Effects
As channel length becomes shorter, V
th
shows a greater dependence on
channel length (SCE: shortchannel effect) and drain bias (DIBL: drain
induced barrier lowering). V
th
dependence on the body bias becomes weaker
as channel length becomes shorter, because the body bias has weaker control
of the depletion region. Based on the quasi 2D solution of the Poisson
equation, V
th
change due to SCE and DIBL is modeled [4]
( ) ( ) ( ) , 2
th th eff bi s ds
V SCE DIBL L V V θ ∆ = − ⋅ −Φ +
(2.23)
where V
bi
, known as the builtin voltage of the source/drain junctions, is
given by
2
ln
B
bi
i
k T NDEP NSD
V
q n
  ⋅
=

\ .
(2.24)
where NSD is the doping concentration of source/drain diffusions. The short
channel effect coefficient θ
th
(L
eff
) in (2.23) has a strong dependence on the
channel length given by
Threshold Voltage Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 15
( )
( )
0.5
cosh 1
eff
t
th eff
L
l
L θ =
−
(2.25)
l
t
is referred to as the characteristic length and is given by
si dep
t
TOXE X
l
EPSROX
ε
η
⋅ ⋅
=
⋅
(2.26)
with the depletion width X
dep
equal to
( ) 2
si s bs
dep
V
X
qNDEP
ε Φ −
=
(2.27)
X
dep
is larger near the drain due to the drain voltage. X
dep
/η represents the
average depletion width along the channel.
Note that in BSIM3v3 and [4], θ
th
(L
eff
) is approximated with the form of
( )
exp 2exp
2
eff eff
th eff
t t
L L
L
l l
θ
   
= − + −
 
\ . \ .
(2.28)
which results in a phantom second V
th
rollup when L
eff
becomes very small
(e.g. L
eff
< LMIN). In BSIM4, the function form of (2.25) is implemented
with no approximation.
To increase the model flexibility for different technologies, several
parameters such as DVT0, DVT1, DVT2, DSUB, ETA0, and ETAB are
introduced, and SCE and DIBL are modeled separately.
To model SCE, we use
( )
( )
0.5 0
SCE
cosh 1 1
eff
t
th
L
l
DVT
DVT
θ
⋅
=
⋅ −
(2.29)
( ) ( ) ( ) SCE SCE
th th bi s
V V θ ∆ = − ⋅ −Φ
(2.30)
with l
t
changed to
Threshold Voltage Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 16
( ) 1 2
si dep
t bs
TOXE X
l DVT V
EPSROX
ε ⋅ ⋅
= ⋅ + ⋅
(2.31)
To model DIBL, we use
( )
( )
0
0.5
DIBL
cosh 1
eff
t
th
L
l
DSUB
θ =
⋅ −
(2.32)
( ) ( ) ( ) DIBL DIBL 0
th th bs ds
V ETA ETAB V V θ ∆ = − ⋅ + ⋅ ⋅
(2.33)
and l
t0
is calculated by
0
0
si dep
t
TOXE X
l
EPSROX
ε ⋅ ⋅
=
(2.34)
with
0
2
si s
dep
X
qNDEP
ε Φ
=
(2.35)
DVT1 is basically equal to 1/η. DVT2 and ETAB account for substrate bias
effects on SCE and DIBL, respectively.
2.5 NarrowWidth Effect
The actual depletion region in the channel is always larger than what is
usually assumed under the onedimensional analysis due to the existence of
fringing fields. This effect becomes very substantial as the channel width
decreases and the depletion region underneath the fringing field becomes
comparable to the "classical" depletion layer formed from the vertical field.
The net result is an increase in V
th
. This increase can be modeled as
2
,max
3
2
dep
s
oxe eff eff
qNDEP X
TOXE
C W W
π
π
⋅
= Φ
(2.36)
Threshold Voltage Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 17
This formulation includes but is not limited to the inverse of channel width
due to the fact that the overall narrow width effect is dependent on process
(i.e. isolation technology). V
th
change is given by
( ) ( ) 1 3 3
' 0
th bs s
eff
TOXE
V Narrow width K K B V
W W
−
∆ = + ⋅ Φ
+
(2.37)
In addition, we must consider the narrow width effect for small channel
lengths. To do this we introduce the following
( )
( )
( )
'
0.5 0
2
cosh 1 1
eff eff
tw
th  bi s
L W
l
DVT W
V Narrow width V
DVT W
⋅
∆ = − ⋅ −Φ
⋅ −
(2.38)
with l
tw
given by
( ) 1 2
si dep
tw bs
TOXE X
l DVT W V
EPSROX
ε ⋅ ⋅
= ⋅ + ⋅
(2.39)
The complete V
th
model implemented in SPICE is
(2.40)
( )
( )
( ) ( )
( )
( )
0
1 2
1
'
0 1 1
0
1 1 3 3
' 0
0 0
0.5
cosh 1 1 cosh 1 1
0.5
0
cosh 1
eff eff eff
tw t
eff
t
th ox s bseff s ox bseff
eff
ox s bseff s
eff eff
bi s
L W L
l l
L
l
LPEB
V VTH K V K K V
L
LPE TOXE
K K K B V
L W W
DVT W DVT
V
DVT W DVT
ETA E
DSUB
= + ⋅ Φ − − ⋅ Φ + −
 
+ + − Φ + + ⋅ Φ 

+
\ .
− ⋅ + −Φ
− −
− +
−
( )
( )
1
.ln
0. 1
DS
eff
bseff ds t
DVTP V
eff
L
TAB V V nv
L DVTP e
− ⋅
 

⋅ ⋅ −

+ +
\ .
where TOXE dependence is introduced in model parameters K1 and K2 to
improve the scalability of V
th
model over TOXE as
Threshold Voltage Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 18
1
1
ox
TOXE
K K
TOXM
= ⋅
(2.41)
and
2
2
ox
TOXE
K K
TOXM
= ⋅
(2.42)
Note that all V
bs
terms are substituted with a V
bseff
expression as shown in
(2.43). This is needed in order to set a low bound for the body bias during
simulations since unreasonable values can occur during SPICE iterations if
this expression is not introduced.
( ) ( )
2
1 1 1
0.5 4
bseff bc bs bc bs bc bc
V V V V V V V δ δ δ
= + ⋅ − − + − − − ⋅
(2.43)
where δ
1
= 0.001V, and V
bc
is the maximum allowable V
bs
and found from
dV
th
/dV
bs
= 0 to be
2
2
1
0.9
4 2
bc s
K
V
K
 
= Φ −

\ .
(2.44)
For positive V
bs
, there is need to set an upper bound for the body bias as:
(2.45)
( )
2
' '
1 1 1
0.95 0.5 0.95 0.95 4 .0.95
bseff s s bseff s bseff s
V V V δ δ δ
 
= Φ − Φ − − + Φ − − + Φ

\ .
Channel Charge and Substhreshold Swing Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 19
Chapter 3: Channel Charge and
Subthreshold Swing Models
3.1 Channel Charge Model
The channel charge density in subthreshold for zero V
ds
is written as
'
eff
VOFFL
Voff VOFF
L
= +
(3.1)
where
'
eff
VOFFL
Voff VOFF
L
= +
(3.2)
VOFFL is used to model the length dependence of V
off
’ on nonuniform
channel doping profiles.
In strong inversion region, the density is expressed by
( )
0 chs oxe gse th
Q C V V = ⋅ −
(3.3)
A unified charge density model considering the charge layer thickness effect
is derived for both subthreshold and inversion regions as
0 ch oxeff gsteff
Q C V = ⋅
(3.4)
where C
oxeff
is modeled by
oxe cen si
oxeff cen
oxe cen DC
C C
C with C
C C X
ε ⋅
= =
+
(3.5)
Channel Charge and Substhreshold Swing Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 20
and X
DC
is given as
( )
9
0.7
1.9 10 m
4 0
1
2
DC BDOS
gsteff s
ADOS
X
V VTH VFB
TOXP
−
×
× ×
=
+ − −Φ  
+

\ .
(3.6)
Here, ADOS and BDOS are the parameters to describe the density of states
in new materials and used to control the charge centroid. In the above
equations, V
gsteff
the effective (V
gse
V
th
) used to describe the channel charge
densities from subthreshold to strong inversion, is modeled by
( )
( )( )
ln 1 exp
1 '
2
exp
gse th
t
t
gsteff
gse th
s
oxe
si t
m V V
nv
nv
V
m V V Voff
m nC
qNDEP nv ε
∗
∗
∗
¦ ¹
−
¦ ¦
+
´ `
¦ ¦
¹ )
=
− − −
Φ
+ ⋅ −
(3.7)
where
( ) arctan
0.5
MINV
m
π
∗ = +
(3.8)
MINV is introduced to improve the accuracy of G
m
, G
m
/I
d
and G
m2
/I
d
in the
moderate inversion region. To account for the drain bias effect, The y
dependence has to be included in (3.4). Consider first the case of strong
inversion
( ) ( ) ( )
chs oxeff gse th bulk F
Q y C V V A V y = ⋅ − −
(3.9)
VF(y) stands for the quasiFermi potential at any given point y along the
channel with respect to the source. (3.9) can also be written as
( ) ( )
0 chs chs chs
Q y Q Q y = + ∆
(3.10)
Channel Charge and Substhreshold Swing Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 21
The term Q
chs
(y) = C
oxeff
A
bulk
VF(y) is the incremental charge density
introduced by the drain voltage at y. In subthreshold region, the channel
charge density along the channel from source to drain can be written as
( )
( )
0
exp
bulk F
chsubs chsubs
t
A V y
Q y Q
nv
 
= ⋅ −

\ .
(3.11)
Taylor expansion of (3.11) yields the following (keeping the first two terms)
( )
( )
0
1
bulk F
chsubs chsubs
t
A V y
Q y Q
nv
 
= −

\ .
(3.12)
Similarly, (3.12) is transformed into
( ) ( )
0 chsubs chsubs chsubs
Q y Q Q y = + ∆
(3.13)
where Q
chsubs
(y) is the incremental channel charge density induced by the
drain voltage in the subthreshold region. It is written as
( )
( )
0
bulk F
chsubs chsubs
t
A V y
Q y Q
nv
∆ = − ⋅
(3.14)
To obtain a unified expression for the incremental channel charge density
Q
ch
(y) induced by V
ds
, we assume Q
ch
(y) to be
( )
( ) ( )
( ) ( )
chs chsubs
ch
chs chsubs
Q y Q y
Q y
Q y Q y
∆ ⋅ ∆
∆ =
∆ + ∆
(3.15)
Substituting Q
ch
(y) of (3.13) and (3.14) into (3.15), we obtain
( )
( )
0
F
ch ch
b
V y
Q y Q
V
∆ = −
(3.16)
where V
b
= (V
gsteff
+ nv
t
) / A
bulk
. In the model implementation, n of V
b
is
replaced by a typical constant value of 2. The expression for V
b
now
becomes
Channel Charge and Substhreshold Swing Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 22
2
gsteff t
b
bulk
V v
V
A
+
=
(3.17)
A unified expression for Q
ch
(y) from subthreshold to strong inversion
regions is
( )
( )
1
F
ch oxeff gsteff
b
V y
Q y C V
V
 
= ⋅ ⋅ −

\ .
(3.18)
3.2 Subthreshold Swing n
The drain current equation in the subthreshold region can be expressed as
0
'
1 exp exp
gs th off
ds
ds
t t
V V V
V
I I
v nv
− −    
= − − ⋅
 
\ . \ .
(3.19)
where
2
0
2
si
t
s
q NDEP W
I v
L
ε
u =
Φ
(3.20)
v
t
is the thermal voltage and equal to k
B
T/q. V
off
’ = VOFF + VOFFL / L
eff
is
the offset voltage, which determines the channel current at V
gs
= 0. In (3.19),
n is the subthreshold swing parameter. Experimental data shows that the
subthreshold swing is a function of channel length and the interface state
density. These two mechanisms are modeled by the following
1
dep
oxe oxe
C
Cdsc Term CIT
n NFACTOR
C C
−
+
= + ⋅ +
(3.21)
where CdscTerm, written as
( )
( )
0.5
cosh 1 1
eff
t
ds bseff
L
l
Cdsc Term CDSC CDSCD V CDSCB V
DVT
−
= + ⋅ + ⋅ ⋅
−
(3.22)
Channel Charge and Substhreshold Swing Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 23
represents the coupling capacitance between drain/source to channel.
Parameters CDSC, CDSCD and CDSCB are extracted. Parameter CIT is the
capacitance due to interface states. From (3.21), it can be seen that
subthreshold swing shares the same exponential dependence on channel
length as the DIBL effect. Parameter NFACTOR is close to 1 and introduced
to compensate for errors in the depletion width capacitance calculation.
Gate Direct Tunneling Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 24
Chapter 4: Gate Direct Tunneling
Current Model
As the gate oxide thickness is scaled down to 3nm and below, gate leakage
current due to carrier direct tunneling becomes important. This tunneling
happens between the gate and silicon beneath the gate oxide. To reduce the
tunneling current, highk dielectrics are being studied to replace gate oxide.
In order to maintain a good interface with substrate, multilayer dielectric
stacks are being proposed. The BSIM4 gate tunneling model has been shown
to work for multilayer gate stacks as well. The tunneling carriers can be
either electrons or holes, or both, either from the conduction band or valence
band, depending on (the type of the gate and) the bias regime.
In BSIM4, the gate tunneling current components include the tunneling
current between gate and substrate (I
gb
), and the current between gate and
channel (I
gc
), which is partitioned between the source and drain terminals by
I
gc
= I
gcs
+ I
gcd
. The third component happens between gate and source/drain
diffusion regions (I
gs
and I
gd
). Figure 4.1 shows the schematic gate tunneling
current flows.
Gate Direct Tunneling Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 25
Figure 4.1. Shematic gate current components flowing between nMOSFET
terminals in version.
4.1 Model Selectors
Two global selectors are provided to turn on or off the tunneling components.
igcMod = 1, 2 turns on I
gc
, I
gs
, and I
gd
; igbMod = 1 turns on I
gb
. When the
selectors are set to zero, no gate tunneling currents are modeled. When
tempMod = 2, following V
t
(= kT/q) will be replaced by V
tnom
(=kTnom/q)
4.2 Voltage Across Oxide V
ox
The oxide voltage V
ox
is written as V
ox
= V
oxacc
+ V
oxdepinv
with
oxacc fbzb FBeff
V V V = −
(4.1)
1 oxdepinv ox s gsteff
V K V = Φ +
(4.2)
(4.1) and (4.2) are valid and continuous from accumulation through
depletion to inversion. V
fbzb
is the flatband voltage calculated from zerobias
V
th
by
1
bs ds
fbzb th zeroV andV s s
V V K = −Φ − Φ
(4.3)
and
( ) ( )
2
0.5 0.02 0.02 0.08
FBeff fbzb fbzb gb fbzb gb fbzb
V V V V V V V
= − − − + − − +
(4.4)
Gate Direct Tunneling Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 26
4.3 Equations for Tunneling Currents
Note: when tempMod = 2, nominal temperature (TNOM) is used to replace
the operating temperature in following gate tunneling current equations.
When tempMod=0, or 1, operating temperature is still used.
4.3.1 GatetoSubstrate Current (I
gb
= I
gbacc
+ I
gbinv
)
I
gbacc
, determined by ECB (Electron tunneling from Conduction Band), is
significant in accumulation and given by
( ) ( ) exp 1
gbacc eff eff oxRatio gb aux
oxacc oxacc
I W L A T V V
B TOXE AIGBACC BIGBACC V CIGBACC V
= ⋅ ⋅ ⋅ ⋅
⋅ − ⋅ − ⋅ ⋅ + ⋅
(4.5)
where the physical constants A = 4.97232e7 A/V
2
, B = 7.45669e11 (g/F
s
2
)
0.5
, and
2
1
NTOX
oxRatio
TOXREF
T
TOXE TOXE
 
= ⋅

\ .
(4.6)
log 1 exp
gb fbzb
aux t
t
V V
V NIGBACC v
NIGBACC v
  −  
= ⋅ ⋅ + −
 

⋅
\ . \ .
(4.7)
I
gbinv
, determined by EVB (Electron tunneling from Valence Band), is
significant in inversion and given by
( ) ( )
exp 1
gbinv eff eff oxRatio gb aux
oxdepinv oxdepinv
I W L A T V V
B TOXE AIGBINV BIGBINV V CIGBINV V
= ⋅ ⋅ ⋅ ⋅
⋅ − ⋅ − ⋅ ⋅ + ⋅
(4.8)
where A = 3.75956e7 A/V
2
, B = 9.82222e11 (g/Fs
2
)
0.5
, and
Gate Direct Tunneling Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 27
log 1 exp
oxdepinv
aux t
t
V EIGBINV
V NIGBINV v
NIGBINV v
  −  
= ⋅ ⋅ +
 

⋅
\ . \ .
(4.9)
4.3.2 GatetoChannel Current (I
gc0
) and GatetoS/D
(I
gs
and I
gd
)
I
gc0
, determined by ECB for NMOS and HVB (Hole tunneling from Valence
Band) for PMOS at V
ds
=0, is formulated as
( ) ( )
0
exp 1
eff eff oxRatio gse aux
oxdepinv oxdepinv
Igc W L A T V V
B TOXE AIGC BIGC V CIGC V
= ⋅ ⋅ ⋅ ⋅
⋅ − ⋅ − ⋅ ⋅ + ⋅
(4.10)
where A = 4.97232 A/V
2
for NMOS and 3.42537 A/V
2
for PMOS, B =
7.45669e11 (g/Fs
2
)
0.5
for NMOS and 1.16645e12 (g/Fs
2
)
0.5
for PMOS, and
for igcMod = 1:
0
log 1 exp
gse
aux t
t
V VTH
V NIGC v
NIGC v
  −  
= ⋅ ⋅ +
 

⋅
\ . \ .
(4.11)
for igcMod = 2:
log 1 exp
gse
aux t
t
V VTH
V NIGC v
NIGC v
  −  
= ⋅ ⋅ +
 

⋅
\ . \ .
(4.12)
I
gs
and I
gd
 I
gs
represents the gate tunneling current between the gate and
the source diffusion region, while I
gd
represents the gate tunneling current
between the gate and the drain diffusion region. I
gs
and I
gd
are determined by
ECB for NMOS and HVB for PMOS, respectively.
( ) ( )
'
' '
exp 1
gs eff oxRatioEdge gs gs
gs gs
I W DLCIG A T V V
B TOXE POXEDGE AIGS BIGS V CIGS V
= ⋅ ⋅ ⋅ ⋅
⋅ − ⋅ ⋅ ⋅ − ⋅ ⋅ + ⋅
(4.13)
and
Gate Direct Tunneling Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 28
( ) ( )
'
' '
exp 1
gd eff oxRatioEdge gd gd
gd gd
I W DLCIGD A T V V
B TOXE POXEDGE AIGD BIGD V CIGD V
= ⋅ ⋅ ⋅ ⋅
⋅ − ⋅ ⋅ ⋅ − ⋅ ⋅ + ⋅
(4.14)
where A = 4.97232 A/V
2
for NMOS and 3.42537 A/V
2
for PMOS, B =
7.45669e11 (g/Fs
2
)
0.5
for NMOS and 1.16645e12 (g/Fs
2
)
0.5
for PMOS, and
( )
2
1
NTOX
oxRatioEdge
TOXREF
T
TOXE POXEDGE
TOXE POXEDGE
 
= ⋅

⋅
\ . ⋅
(4.15)
( )
2
'
1.0 4
gs gs fbsd
V V V e = − + −
(4.16)
( )
2
'
1.0 4
gd gd fbsd
V V V e = − + −
(4.17)
V
fbsd
is the flatband voltage between gate and S/D diffusions calculated as
If NGATE > 0.0
log
B
fbsd
k T NGATE
V VFBSDOFF
q NSD
 
= +

\ .
(4.18)
Else V
fbsd
= 0.0.
4.3.3. Partition of I
gc
To consider the drain bias effect, I
gc
is split into two components, I
gcs
and I
gcd
,
that is I
gc
= I
gcs
+ I
gcd
, and
( )
2 2
exp 1 1.0e 4
0
2.0e 4
dseff dseff
dseff
PIGCD V PIGCD V
Igcs Igc
PIGCD V
⋅ + − ⋅ − + −
= ⋅
⋅ + −
(4.19)
and
Gate Direct Tunneling Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 29
( ) ( )
2 2
1 1 exp 1.0e 4
0
2.0e 4
dseff dseff
dseff
PIGCD V PIGCD V
Igcd Igc
PIGCD V
− ⋅ + ⋅ − ⋅ + −
= ⋅
⋅ + −
(4.20)
where I
gc0
is I
gc
at V
ds
=0.
If the model parameter PIGCD is not specified, it is given by
2
1
2
dseff
gsteff gsteff
V
B TOXE
PIGCD
V V
 
⋅
= −


⋅
\ .
(4.21)
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 30
Chapter 5: Drain Current Model
5.1 Bulk Charge Effect
The depletion width will not be uniform along channel when a nonzero V
ds
is applied. This will cause V
th
to vary along the channel. This effect is called
bulk charge effect.
BSIM4 uses A
bulk
to model the bulk charge effect. Several model parameters
are introduced to account for the channel length and width dependences and
bias effects. A
bulk
is formulated by
(5.1)
2
0
2
1
1
1
0
1
' 1 2
eff
eff dep
bulk
bseff
eff
gsteff
eff eff dep
A L
L XJ X
A F doping
KETA V
L
B
AGS V
W B L XJ X
−
¦ ⋅ ¹
⋅
¦ ¦
+ ⋅
¦ ¦
¦ ¦
= + ⋅ ⋅
´ `
 
  + ⋅
¦ ¦

 − ⋅ +
¦ ¦
 
+ + ⋅

\ . ¦ ¦
\ . ¹ )
where the second term on the RHS is used to model the effect of non
uniform doping profiles
1
2
1
3
' 0 2
eff ox
ox s
eff s bseff
LPEB L K
TOXE
F doping K K B
W W V
−
+
= + − Φ
+ Φ −
(5.2)
Note that A
bulk
is close to unity if the channel length is small and increases as
the channel length increases.
5.2 Unified Mobility Model
mrtlMod=0
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 31
A good mobility model is critical to the accuracy of a MOSFET model. The
scattering mechanisms responsible for surface mobility basically include
phonons, coulombic scattering, and surface roughness. For good quality
interfaces, phonon scattering is generally the dominant scattering mechanism
at room temperature. In general, mobility depends on many process
parameters and bias conditions. For example, mobility depends on the gate
oxide thickness, substrate doping concentration, threshold voltage, gate and
substrate voltages, etc. [5] proposed an empirical unified formulation based
on the concept of an effective field E
eff
which lumps many process
parameters and bias conditions together. E
eff
is defined by
/ 2
B n
eff
si
Q Q
E
ε
+
=
(5.3)
The physical meaning of E
eff
can be interpreted as the average electric field
experienced by the carriers in the inversion layer. The unified formulation of
mobility is then given by
0
0
1 ( / )
eff v
eff
E E
u
u =
+
(5.4)
For an NMOS transistor with ntype polysilicon gate, (6.3) can be rewritten
in a more useful form that explicitly relates E
eff
to the device parameters
6
gs th
eff
V V
E
TOXE
+
≈
(5.5)
BSIM4 provides three different models of the effective mobility. The
mobMod = 0 and 1 models are from BSIM3v3.2.2; the new mobMod = 2, a
universal mobility model, is more accurate and suitable for predictive
modeling.
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 32
mobMod = 0
(5.6)
( )
2
2
2
0 ( )
2 2
1
2 0.0001
eff
eff
gsteff th gsteff th
th
bseff
gsteff th
U f L
V V V V
V TOXE
UA UCV UB UD
TOXE TOXE
V V
u
⋅
=
 
+ +     ⋅

+ + + +
 

+ + \ . \ .
\ .
mobMod = 1
(5.7)
( )
2
2
2
0 ( )
2 2
1 1
2 0.0001
eff
eff
gsteff th gsteff th
th
bseff
gsteff th
U f L
V V V V
V TOXE
UA UB UC V UD
TOXE TOXE
V V
u
⋅
=
 
+ +     ⋅
 + + + ⋅ +
 

+ + \ . \ .
\ .
mobMod = 2
(5.8)
( )
( )
( )
0
2
0
1
2 0.0001
eff
eff
EU
gsteff s
th
bseff
gsteff th
U f L
V C VTHO VFB
V TOXE
UA UC V UD
TOXE
V V
u
⋅
=
 
+ ⋅ − −Φ
⋅
 + + ⋅ +

+ +
\ .
where the constant C0 = 2 for NMOS and 2.5 for PMOS.
( ) 1 exp
eff
eff
L
f L UP
LP
 
= − ⋅ −

\ .
(5.9)
mrtlMod=1
A new expression of the vertical field in channel is adopted:
(5.10)
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 33
2 2 4 ( / 2 0.45)
3.9
gsteff th
eff
V V BSIM type PHIG EASUB Eg
E
EOT EPSRSUB
+ − ⋅ ⋅ − − +
= ⋅
Thus the mobility model is modified as following:
mobMod=0
2
2
2
0 ( )
1 ( )
2 0.00001
eff
eff
th
bseff eff eff
gsteff th
U f L
V EOT
UA UC V E UB E UD
V V
u
⋅
=
 
⋅

+ + ⋅ + ⋅ +

+ +
\ .
(5.11)
mobMod=1
2
2
2
0 ( )
1 ( )(1 )
2 0.00001
eff
eff
th
eff eff bseff
gsteff th
U f L
V EOT
UA E UB E UC V UD
V V
u
⋅
=
 
⋅

+ ⋅ + ⋅ + ⋅

+ +
\ .
(5.12)
Note: There is no changes in mobMod=2 when mtrlMod=1.
BSIM4.6.2 introduces a new model to predict the mobility in high k/metal
gate structure, in which Coulombic scattering is important. mobMod=3
( )
( )
( )
 
UCS
Vth gsteff gsteff
EU
S fb gsteff
bseff
eff
eff
V V
UD
TOXE
V VTH C V
V UC UA
L f U
,
0
/ 1 5 . 0
. 6
0 .
. 1
. 0
+
+
Φ − − +
+ +
= u
(5.13)
Here, Vgsteff,Vth=Vgsteff(Vgse=Vth,Vds=Vbs=0).
5.3 Asymmetric and BiasDependent Source/ Drain
Resistance Model
BSIM4 models source/drain resistances in two components: bias
independent diffusion resistance (sheet resistance) and biasdependent LDD
resistance. Accurate modeling of the biasdependent LDD resistances is
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 34
important for deepsubmicron CMOS technologies. In BSIM3 models, the
LDD source/drain resistance R
ds
(V) is modeled internally through the IV
equation and symmetry is assumed for the source and drain sides. BSIM4
keeps this option for the sake of simulation efficiency. In addition, BSIM4
allows the source LDD resistance R
s
(V) and the drain LDD resistance R
d
(V)
to be external and asymmetric (i.e. R
s
(V) and R
d
(V) can be connected
between the external and internal source and drain nodes, respectively;
furthermore, R
s
(V) does not have to be equal to R
d
(V)). This feature makes
accurate RF CMOS simulation possible. The internal R
ds
(V) option can be
invoked by setting the model selector rdsMod = 0 (internal) and the external
one for R
s
(V) and R
d
(V) by setting rdsMod = 1 (external).
rdsMod = 0 (Internal R
ds
(V))
( )
( )
( )
1e6
1
1
WR
ds effcj
s bseff s
gsteff
RDSWMIN RDSW
R V W
PRWB V
PRWG V
+ ⋅ ¦ ¹
¦ ¦
= ⋅
´ `
⋅ Φ − − Φ +
¦ ¦
+ ⋅
¹ )
(5.14)
rdsMod = 1 (External R
d
(V) and R
s
(V))
( )
( )
( )
1e6
1
1
WR
d effcj
bd
gd fbsd
RDWMIN RDW
R V W NF
PRWB V
PRWG V V
+ ⋅ ¦ ¹
¦ ¦
¦ ¦
= ⋅ ⋅
´ `
− ⋅ +
¦ ¦
+ ⋅ −
¦ ¦ ¹ )
(5.15)
( )
( )
( )
1e6
1
1
WR
s effcj
bs
gs fbsd
RSWMIN RSW
R V W NF
PRWB V
PRWG V V
+ ⋅ ¦ ¹
¦ ¦
¦ ¦
= ⋅ ⋅
´ `
− ⋅ +
¦ ¦
+ ⋅ −
¦ ¦ ¹ )
(5.16)
V
fbsd
is the calculated flatband voltage between gate and source/drain as
given in Section 4.3.2.
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 35
The following figure shows the schematic of source/drain resistance
connection for rdsMod = 1.
The diffusion source/drain resistance R
sdiff
and R
ddiff
models are given in the
chapter of layoutdependence models.
5.4 Drain Current for Triode Region
R
ds
(V)=0 or rdsMod=1 (“intrinsic case”)
Both drift and diffusion currents can be modeled by
( ) ( ) ( )
( )
F
ds ch ne
dV y
I y WQ y y
dy
u =
(5.17)
where µ
ne
(y) can be written as
( )
1
eff
ne
y
sat
y
E
E
u
u =
+
(5.18)
Substituting (6.17) in (6.16), we get
( )
( ) ( )
0
1
1
eff F F
ds ch
y
b
sat
V y dV y
I y WQ
E
V dy
E
u  
= −

\ .
+
(5.19)
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 36
(6.18) is integrated from source to drain to get the expression for linear drain
current. This expression is valid from the subthreshold regime to the strong
inversion regime
0
0
1
2
1
ds
eff ch ds
b
ds
ds
sat
V
W Q V
V
I
V
L
E L
u
 
−

\ .
=
 
+

\ .
(5.20)
R
ds
(V) > 0 and rdsMod=0 (“Extrinsic case”)
The drain current in this case is expressed by
0
0
1
ds
ds
ds ds
ds
I
I
R I
V
=
+
(5.21)
5.5 Velocity Saturation
Velocity saturation is modeled by [5]
1
eff
sat
sat
sat
E
v E E
E E
VSAT E E
u
= <
+
= ≥
(5.22)
where E
sat
corresponds to the critical electrical field at which the carrier
velocity becomes saturated. In order to have a continuous velocity model at
E = E
sat
, E
sat
must satisfy
2
sat
eff
VSAT
E
u
=
(5.23)
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 37
5.6 Saturation Voltage V
dsat
5.6.1 Intrinsic case
In this case, the LDD source/drain resistances are either zero or non zero but
not modeled inside the intrinsic channel region. It is easy to obtain V
dsat
as [7]
( 2 )
2
sat gsteff t
dsat
bulk sat gsteff t
E L V v
V
A E L V v
+
=
+ +
(5.24)
5.6.2 Extrinsic Case
In this case, nonzero LDD source/drain resistance R
ds
(V) is modeled
internally through the IV equation and symetry is assumed for the source
and drain sides. V
dsat
is obtained as [7]
2
4
2
dsat
b b ac
V
a
− − −
=
(5.25)
where
2
1
1
bulk eff oxe ds bulk
a A W VSATC R A
λ
 
= + −

\ .
(5.26)
( )
( )
2
2 1
3 2
gsteff t bulk sat eff
bulk gsteff t eff oxe ds
V v A E L
b
A V v W VSATC R
λ
 
+ − +

\ . = −
+ +
(5.27)
( ) ( )
2
2 2 2
gsteff t sat eff gsteff t eff oxe ds
c V v E L V v W VSATC R = + + +
(5.28)
1 2
gsteff
A V A λ = +
(5.29)
λ is introduced to model the nonsaturation effects which are found for
PMOSFETs.
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 38
5.6.3V
dseff
Formulation
An effective V
ds
, V
dseff
, is used to ensure a smooth transition near V
dsat
from
trode to saturation regions. V
dseff
is formulated as
( ) ( )
2 1
4
2
dseff dsat dsat ds dsat ds dsat
V V V V V V V δ δ δ
= − − − + − − + ⋅
(5.30)
where δ (DELTA) is a model parameter.
5.7 SaturationRegion Output Conductance Model
A typical IV curve and its output resistance are shown in Figure 6.1.
Considering only the channel current, the IV curve can be divided into two
parts: the linear region in which the current increases quickly with the drain
voltage and the saturation region in which the drain current has a weaker
dependence on the drain voltage. The first order derivative reveals more
detailed information about the physical mechanisms which are involved in
the device operation. The output resistance curve can be divided into four
regions with distinct R
out
~V
ds
dependences.
The first region is the triode (or linear) region in which carrier velocity is not
saturated. The output resistance is very small because the drain current has a
strong dependence on the drain voltage. The other three regions belong to
the saturation region. As will be discussed later, there are several physical
mechanisms which affect the output resistance in the saturation region:
channel length modulation (CLM), draininduced barrier lowering (DIBL),
and the substrate current induced body effect (SCBE). These mechanisms all
affect the output resistance in the saturation range, but each of them
dominates in a specific region. It will be shown next that CLM dominates in
the second region, DIBL in the third region, and SCBE in the fourth region.
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 39
Figure 5.1 General behavior of MOSFET output resistance.
The channel current is a function of the gate and drain voltage. But the
current depends on the drain voltage weakly in the saturation region. In the
following, the Early voltage is introduced for the analysis of the output
resistance in the saturation region:
( ) ( )
( )
( )
,
, ,
1
, 1
ds
dsat
ds
dsat
V
ds gs ds
ds gs ds dsat gs dsat d
V
d
V
dsat gs dsat d
V
A
I V V
I V V I V V dV
V
I V V dV
V
∂
= + ⋅
∂
= ⋅ + ⋅
∫
∫
(5.31)
where the Early voltage V
A
is defined as
( )
1
,
ds gs ds
A dsat
d
I V V
V I
V
−
∂
= ⋅
∂
(5.32)
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 40
We assume in the following analysis that the contributions to the Early
voltage from all mechanisms are independent and can be calculated
separately.
5.7.1 Channel Length Modulation (CLM)
If channel length modulation is the only physical mechanism to be taken into
account, the Early voltage can be calculated by
( )
1
,
ds gs ds
ACLM dsat
d
I V V
L
V I
L V
−
∂
∂
= ⋅ ⋅
∂ ∂
(5.33)
Based on quasi twodimensional analysis and through integration, we
propose V
ACLM
to be
( )
ACLM clm ds dsat
V C V V = ⋅ − (5.34)
where
1 1
1 1
gsteff
ds dso dsat
clm eff
sat eff dseff sat
V
R I V
C F PVAG L
PCLM E L V E litl
  
  ⋅
= ⋅ ⋅ + + + ⋅
 

 
\ .
\ .\ .
(5.35)
and the F factor to account for the impact of pocket implant technology is
1
1
2
eff
gsteff t
F
L
FPROUT
V v
=
+ ⋅
+
(5.36)
and litl in (6.34) is given by
si
TOXE XJ
litl
EPSROX
ε ⋅
=
(5.37)
PCLM is introduced into V
ACLM
to compensate for the error caused by XJ
since the junction depth XJ cannot be determined very accurately.
5.7.2 DrainInduced Barrier Lowering (DIBL)
The Early voltage V
ADIBLC
due to DIBL is defined as
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 41
( )
1
,
ds gs ds
th
ADIBL dsat
th d
I V V
V
V I
V V
−
∂
∂
= ⋅ ⋅
∂ ∂
(5.38)
V
th
has a linear dependence on V
ds
. As channel length decreases, V
ADIBLC
decreases very quickly
(5.39)
( )
2
1 1
2 1
gsteff t gsteff
bulk dsat
ADIBL
bulk dsat gsteff t sat eff rout bseff
V v V
A V
V PVAG
A V V v E L PDIBLCB V θ
    +
= − ⋅ +
 
 
+ + + ⋅
\ . \ .
where θ
rout
has a similar dependence on the channel length as the DIBL
effect in V
th
, but a separate set of parameters are used:
( ) 0
1
2
2cosh 2
eff
rout
DROUT L
lt
PDIBLC
PDIBLC θ
⋅
= +
−
(5.40)
Parameters PDIBLC1, PDIBLC2, PDIBLCB and DROUT are introduced to
correct the DIBL effect in the strong inversion region. The reason why
DVT0 is not equal to PDIBLC1 and DVT1 is not equal to DROUT is because
the gate voltage modulates the DIBL effect. When the threshold voltage is
determined, the gate voltage is equal to the threshold voltage. But in the
saturation region where the output resistance is modeled, the gate voltage is
much larger than the threshold voltage. Drain induced barrier lowering may
not be the same at different gate bias. PDIBLC2 is usually very small. If
PDIBLC2 is put into the threshold voltage model, it will not cause any
significant change. However it is an important parameter in V
ADIBLC
for long
channel devices, because PDIBLC2 will be dominant if the channel is long.
5.7.3 Substrate Current Induced Body Effect (SCBE)
When the electrical field near the drain is very large (> 0.1MV/cm), some
electrons coming from the source (in the case of NMOSFETs) will be
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 42
energetic (hot) enough to cause impact ionization. This will generate
electronhole pairs when these energetic electrons collide with silicon atoms.
The substrate current I
sub
thus created during impact ionization will increase
exponentially with the drain voltage. A well known I
sub
model [8] is
( ) exp
i i
sub ds ds dsat
i ds dsat
A B litl
I I V V
B V V
  ⋅
= − −

−
\ .
(5.41)
Parameters A
i
and B
i
are determined from measurement. I
sub
affects the drain
current in two ways. The total drain current will change because it is the sum
of the channel current as well as the substrate current. The total drain current
can now be expressed as follows
( )
/ /
1
exp
i i
i ds dsat
ds dsat
ds ds w o Isub sub ds w o Isub
B B litl
A V V
V V
I I I I
− − − −
⋅
−
−
= + = ⋅ +
(5.42)
The Early voltage due to the substrate current V
ASCBE
can therefore be
calculated by
exp
i i
ASCBE
i ds dsat
B B litl
V
A V V
  ⋅
=

−
\ .
(5.43)
We can see that V
ASCBE
is a strong function of V
ds
. In addition, we also
observe that V
ASCBE
is small only when V
ds
is large. This is why SCBE is
important for devices with high drain voltage bias. The channel length and
gate oxide dependence of V
ASCBE
comes from V
dsat
and litl. We replace B
i
with PSCBE2 and A
i
/B
i
with PSCBE1/L
eff
to get the following expression for
V
ASCBE
1 2 1
exp
ASCBE eff ds dsat
PSCBE PSCBE litl
V L V V
  ⋅
= −

−
\ .
(5.44)
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 43
5.7.4 DrainInduced Threshold Shift (DITS) by Pocket Implant
It has been shown that a longchannel device with pocket implant has a
smaller R
out
than that of uniformlydoped device [3]. The R
out
degradation
factor F is given in (6.35). In addition, the pocket implant introduces a
potential barrier at the drain end of the channel. This barrier can be lowered
by the drain bias even in longchannel devices. The Early voltage due to
DITS is modeled by
( ) ( )
1
1 1 exp
ADITS eff ds
V F PDITSL L PDITSD V
PDITS
= ⋅ ⋅ + + ⋅ ⋅
(5.45)
5.8 SingleEquation Channel Current Model
The final channel current equation for both linear and saturation regions now
becomes
0
0
1
1 ln
1
1 1 1
ds ds
dseff
ds A
ds R I
clm Asat V
ds dseff ds dseff ds dseff
ADIBL ADITS ASCBE
I NF V
I
C V
V V V V V V
V V V
  ⋅
= +

+
\ .
− − −      
⋅ + ⋅ + ⋅ +
  
\ . \ . \ .
(5.46)
where NF is the number of device fingers, and
V
A
is written as
A Asat ACLM
V V V = + (5.47)
where V
Asat
is
( )
2 2
2
2 1
1
bulk dsat
gsteff t
A V
sat eff dsat ds oxe eff gsteff
V v
Asat
ds oxe eff bulk
E L V R vsatC W V
V
R vsatC W A
λ
+
+ + ⋅ −
=
− +
(5.48)
V
Asat
is the Early voltage at V
ds
= V
dsat
. V
Asat
is needed to have continuous
drain current and output resistance expressions at the transition point
between linear and saturation regions.
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 44
5.9 New Current Saturation Mechanisms: Velocity
Overshoot and Source End Velocity Limit Model
5.9.1 Velocity Overshoot
In the deepsubmicron region, the velocity overshoot has been observed to
be a significant effect even though the supply voltage is scaled down
according to the channel length. An approximate nonlocal velocity field
expression has proven to provide a good description of this effect
(1 ) (1 )
1 /
d
c
E E E
v v
E x E E E x
λ u λ ∂ ∂
= + = +
∂ + ∂
(5.49)
This relationship is then substituted into (6.45) and the new current
expression including the velocity overshoot effect is obtained:
,
1
1
dseff
DS
eff sat
DS HD
dseff
OV
eff sat
V
I
L E
I
V
L E
 
⋅ +


\ .
=
+
(5.50)
where
2
2
1 1
1
1 1
sat
ds dseff
OV
sat
eff eff
ds dseff
V V
Esat litl LAMBDA
E E
L
V V
Esat litl
u
−  
+ −

⋅
\ .
= + ⋅
⋅
−  
+ +

⋅
\ .
(5.51)
LAMBDA is the velocity overshoot coefficient.
5.9.2 Source End Velocity Limit Model
When MOSFETs come to nanoscale, because of the high electric field and
strong velocity overshoot, carrier transport through the drain end of the
channel is rapid. As a result, the dc current is controlled by how rapidly
carriers are transported across a short lowfield region near the beginning of
Drain Current Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 45
the channel. This is known as injection velocity limits at the source end of
the channel. A compact model is firstly developed to account for this current
saturation mechanism.
Hydrodynamic transportation gives the source end velocity as :
, DS HD
sHD
s
I
v
Wq
=
(5.52)
where q
s
is the source end inversion charge density. Source end velocity
limit gives the highest possible velocity which can be given through ballistic
transport as:
1
1
sBT
r
v VTL
r
−
=
+
(5.53)
where VTL: thermal velocity, r is the back scattering coefficient which is
given:
XN 3.0
eff
eff
L
r
XN L LC
= ≥
⋅ +
(5.54)
The real source end velocity should be the lower of the two, so a final
Unified current expression with velocity saturation, velocity overshoot and
source velocity limit can be expressed as :
( )
,
1/ 2
2
1 /
DS HD
DS MM
MM
sHD sBT
I
I
v v
=
+
(5.55)
where MM=2.0.
Body Current Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 46
Chapter 6: Body Current Models
In addition to the junction diode current and gatetobody tunneling current,
the substrate terminal current consists of the substrate current due to impact
ionization (I
ii
), and gateinduced drain leakage and source leakage currents
(I
GIDL
and I
GISL
).
6.1 I
ii
Model
The impact ionization current model in BSIM4 is the same as that in
BSIM3v3.2, and is modeled by
( )
0 1
0
exp
eff
ii ds dseff dsNoSCBE
eff ds dseff
ALPHA ALPHA L
BETA
I V V I
L V V
  + ⋅
= − ⋅


−
\ .
(6.1)
where parameters ALPHA0 and BETA0 are impact ionization coefficients;
parameter ALPHA1 is introduced to improves the I
ii
scalability, and
0
0
1
1 ln 1 1
1
ds ds
dseff
ds dseff ds dseff
ds A
dsNoSCBE R I
clm Asat ADIBL ADITS V
V V V V
I NF V
I
C V V V
− −       ⋅
= + ⋅ + ⋅ +
  
+
\ . \ . \ .
(6.2)
6.2 I
GIDL
and I
GISL
Model
mtrlMod=0
The GIDL/GISL current and its body bias effect are modeled by [9][10]
3
3
3
3
exp
ds gse
GIDL effCJ
oxe
oxe db
ds gse db
V V EGIDL
I AGIDL W Nf
T
T BGIDL V
V V EGIDL CGIDL V
− −
= ⋅ ⋅ ⋅
⋅
 
⋅ ⋅
⋅ − ⋅


− − +
\ .
(6.3)
Body Current Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 47
3
3
3
3
exp
ds gde
GISL effCJ
oxe
oxe sb
ds gde sb
V V EGISL
I AGISL W Nf
T
T BGISL V
V V EGISL CGISL V
− − −
= ⋅ ⋅ ⋅
⋅
 
⋅ ⋅
⋅ − ⋅


− − − +
\ .
(6.4)
where AGIDL, BGIDL, CGIDL and EGIDL are model parameters for the
drain side and AGISL, BGISL, CGISL and EGISL are the model parameters
for the source side. They are explained in Appendix A. CGIDL and CGISL
account for the bodybias dependence of I
GIDL
and
I
GISL
respectively. W
effCJ
and Nf are the effective width of the source/drain diffusions and the number
of fingers. Further explanation of W
effCJ
and Nf can be found in the chapter of
the layoutdependence model.
mtrlMod=1
In this case, the work function difference (V
fbsd
) between source/drain and
channel could be modeled as follows:
0 0
( 4 , ln
2 2
fbsd t
i
Eg Eg NSD
V PHIG EASUB BSIM typy MIN v
n
   
= − + − ×
 

\ . \ .
(6.5)
Moreover, the GIDL/GISL current should be modified as following:
3
3
3.9
3.9
exp
ds gse fbsd
GIDL effCJ
db
ds gse fbsd db
V V EGIDL V
I AGIDL W Nf
EPSRSUB
EOT
EPSRSUB
EOT BGIDL
V
V V EGIDL V CGIDL V
− − +
= ⋅ ⋅ ⋅
⋅
 
⋅ ⋅

− ⋅

− − + +

\ .
(6.6)
Body Current Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 48
3
3
3.9
3.9
exp
ds gse fbsd
GIDS effCJ
db
ds gse fbsd db
V V EGISL V
I AGISL W Nf
EPSRSUB
EOT
EPSRSUB
EOT BGISL
V
V V EGISL V CGISL V
− − +
= ⋅ ⋅ ⋅
⋅
 
⋅ ⋅

− ⋅

− − + +

\ .
(6.7)
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 49
Chapter 7: Capacitance Model
Accurate modeling of MOSFET capacitance plays equally important role as
that of the DC model. This chapter describes the methodology and device
physics considered in both intrinsic and extrinsic capacitance modeling in
BSIM4.0.0. Complete model parameters can be found in Appendix A.
7.1 General Description
BSIM4.0.0 provides three options for selecting intrinsic and overlap/fringing
capacitance models. These capacitance models come from BSIM3v3.2, and
the BSIM3v3.2 capacitance model parameters are used without change in
BSIM4 except that separate CKAPPA parameters are introduced for the
sourceside and drainside overlap capacitances. The BSIM3v3.2 capMod =
1 is no longer supported in BSIM4. The following table maps the BSIM4
capacitance models to those of BSIM3v3.2.
BSIM4 capacitance models
Matched capMod in BSIM3v3.2.2
capMod = 0 (simple and piece wise model)
Intrinsic capMod = 0 + overlap/fringing capMod = 0
capMod = 1 (singleequation model)
Intrinsic capMod = 2 + overlap/fringing capMod = 2
capMod = 2 (default model;
singelequation and chargethickness model
Intrinsic capMod = 3 + overlap/fringing capMod = 2
BSIM4 capacitance models have the following features:
• Separate effective channel length and width are used for
capacitance models.
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 50
• capMod = 0 uses piecewise equations. capMod = 1 and 2 are
smooth and single equation models; therefore both charge and
capacitance are continous and smooth over all regions.
• Threshold voltage is consistent with DC part except for capMod =
0, where a longchannel V
th
is used. Therefore, those effects such as
body bias, short/narrow channel and DIBL effects are explicitly
considered in capMod = 1 and 2.
• A new threshold voltage definition is introduced to improve the
fitting in subthreshold region. Setting cvchargeMod = 1 activates the
new V
gsteff,CV
calculation which is similar to the V
gsteff
formulation in
the IV model.
• Overlap capacitance comprises two parts: (1) a biasindependent
component which models the effective overlap capacitance between
the gate and the heavily doped source/drain; (2) a gatebias dependent
component between the gate and the lightly doped source/drain region.
• Biasindependent fringing capacitances are added between the gate
and source as well as the gate and drain.
7.2 Methodology for Intrinsic Capacitance Modeling
7.2.1 Basic Formulation
To ensure charge conservation, terminal charges instead of terminal voltages
are used as state variables. The terminal charges Q
g
, Q
b
, Q
s
, and Q
d
are the
charges associated with the gate, bulk, source, and drain termianls,
respectively. The gate charge is comprised of mirror charges from these
components: the channel charge (Q
inv
), accumulation charge (Q
acc
) and
substrate depletion charge (Q
sub
).
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 51
The accumulation charge and the substrate charge are associated with the
substrate while the channel charge comes from the source and drain
terminals
( )
g sub inv acc
b acc sub
inv s d
Q Q Q Q
Q Q Q
Q Q Q
= − + + ¦
¦
= +
´
¦
= +
¹
(7.1)
The substrate charge can be divided into two components: the substrate
charge at zero sourcedrain bias (Q
sub0
), which is a function of gate to
substrate bias, and the additional nonuniform substrate charge in the
presence of a drain bias (δQ
sub
). Q
g
now becomes
0
( )
g inv acc sub sub
Q Q Q Q Q δ = − + + +
(7.2)
The total charge is computed by integrating the charge along the channel.
The threshold voltage along the channel is modified due to the nonuniform
substrate charge by
( ) (0) ( 1)
th th bulk y
V y V A V = + −
(7.3)
( )
( )
( ) ( )
0 0
0 0
0 0
1
active active
active active
active active
L L
c active c active oxe gt bulk y
L L
g active g active oxe gt th FB s y
L L
b active b active oxe th FB s bulk y
Q W q dy W C V A V dy
Q W q dy W C V V V V dy
Q W q dy W C V V A V dy
¦
= = − −
¦
¦
¦
¦
= = + − −Φ −
´
¦
¦
¦
= = − − −Φ + −
¦
¹
∫ ∫
∫ ∫
∫ ∫
(7.4)
where V
gt
= V
gse
 V
th
and
y
y
dV
dy
E
=
(7.5)
where E
y
is expressed in
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 52
( )
2
active eff oxe
bulk
ds gt ds ds active eff oxe gt bulk y y
active
W C
A
I V V V W C V A V E
L
u
u
 
= − = −

\ .
(7.6)
All capacitances are derived from the charges to ensure charge conservation.
Since there are four terminals, there are altogether 16 components. For each
component
i
ij
j
Q
C
V
∂
=
∂
(7.7)
where i and j denote the transistor terminals. C
ij
satisfies
0
ij ij
i j
C C = =
∑ ∑
(7.8)
7.2.2 Short Channel Model
cvchargeMod=0
The longchannel charge model assumes a constant mobility with no
velocity saturation. Since no channel length modulation is considered, the
channel charge remains constant in saturation region. Conventional long
channel charge models assume V
dsat,CV
= V
gt
/ A
bulk
and therefore is
independent of channel length. If we define a drain bias, V
dsat,CV
, for
capacitance modeling, at which the channel charge becomes constant, we
will find that V
dsat,CV
in general is larger than V
dsat
for IV but smaller than
the longchannel V
dsat
= V
gt
/ A
bulk
. In other words,
,
, , ,
gsteff CV
dsat IV dsat CV dsat IV Lactive
bulk
V
V V V
A
→∞
< < =
(7.9)
and V
dsat,CV
is modeled by
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 53
,
,
1
gsteff CV
dsat CV
CLE
bulk
active
V
V
CLC
A
L
=
 
⋅ +

\ .
(7.10)
,
ln 1 exp
gse th
gsteff CV t
t
V V VOFFCV
V NOFF nv
NOFF nv
− −  
= ⋅ ⋅ +

⋅
\ .
(7.11)
Model parameters CLC and CLE are introduced to consider the effect of
channellength modulation. A
bulk
for the capacitance model is modeled by
0
0 1
1
' 1 1 2
eff
bulk
eff bseff eff dep
A L
B
A F doping
W B KETA V L XJ X
−
¦ ¹
⋅
¦ ¦
= + ⋅ ⋅ + ⋅
´ `
+ + ⋅ + ⋅
¦ ¦
¹ )
(7.12)
where
1
2
1
3
' 0 2
eff ox
ox s
eff s bseff
LPEB L K
TOXE
F doping K K B
W W V
−
+
= + − Φ
+ Φ −
(7.13)
cvchargeMod=1
In order to improve the predictive modeling in the subthreshold region, a
new threshold voltage for CV is introduced as following:
( )
( )( )
*
* '
*
ln 1 exp
1
2
exp
gse th
t
t
gsteffCV
gse th
s
oxe
Si t
m V V
nv
nv
V
m V V Voff
m nC
qNDEP nv
φ
ε
 
 
−

 +


\ . \ .
=
 
− − −
 + −

\ .
(7.14)
( )
*
arctan
0.5
MINVCV
m
π
= +
(7.15)
'
eff
VOFFCVL
Voff VOFFCV
L
= +
(7.16)
It is clear that this new definition is similar to V
gsteff
in IV model.
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 54
Note: The default value of cvchargeMod is zero to keep the backward
compatibility.
7.2.3 Single Equation Formulation
Traditional MOSFET SPICE capacitance models use piecewise equations.
This can result in discontinuities and nonsmoothness at transition regions.
The following describes singleequation formulation for charge, capacitance
and voltage modeling in capMod = 1 and 2.
(a) Transition from depletion to inversion region
The biggest discontinuity is at threshold voltage where the inversion
capacitance changes abruptly from zero to C
oxe
. Concurrently, since the
substrate charge is a constant, the substrate capacitance drops abruptly to
zero at threshold voltage. The BSIM4 charge and capacitance models are
formulated by substituting V
gst
with V
gsteff,CV
as
( ) ( )
, gst gsteff CV
Q V Q V = (7.17)
For capacitance modeling
( ) ( )
,
,
, , ,
gsteff CV
gst gsteff CV
g d s b
V
C V C V
V
∂
=
(7.18)
(b) Transition from accumulation to depletion region
An effective smooth flatband voltage V
FBeff
is used for the accumulation and
depletion regions.
( ) ( )
2
0.5 0.02 0.02 0.08
FBeff fbzb fbzb gb fbzb gb fbzb
V V V V V V V
= − − − + − − +
(7.19)
where
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 55
1
bs ds
fbzb th zeroV andV s s
V V K = −Φ − Φ (7.20)
A biasindependent V
th
is used to calculate V
fbzb
for capMod = 1 and 2. For
capMod = 0, VFBCV is used instead (refer to Appendix A).
(c) Transition from linear to saturation region
An effective V
ds
, V
cveff
, is used to smooth out the transition between linear
and saturation regions.
{ }
2
, 4 4 4 ,
4 , 4 4
0.5 4
where ; 0.02
cveff dsat CV dsat CV
dsat CV ds
V V V V V
V V V V
δ
δ δ
= − + +
= − − =
(7.21)
7.2.4.Charge partitioning
The inversion charges are partitioned into Q
inv
= Q
s
+ Q
d
. The ratio of Q
d
to
Q
s
is the charge partitioning ratio. Existing charge partitioning schemes are
0/100, 50/50 and 40/60 (XPART = 1, 0.5 and 0).
50/50 charge partition
This is the simplest of all partitioning schemes in which the inversion
charges are assumed to be contributed equally from the source and drain
terminals.
40/60 charge partition
This is the most physical model of the three partitioning schemes in which
the channel charges are allocated to the source and drain terminals by
assuming a linear dependence on channel position y.
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 56
0
0
1
active
active
L
s active c
active
L
d active c
active
y
Q W q
L
dy
y
Q W q dy
L
¦
 
= −
¦ 
¦ \ .
´
¦
=
¦
¹
∫
∫
(7.22)
0/100 charge partition
In fast transient simulations, the use of a quasistatic model may result in a
large unrealistic drain current spike. This partitioning scheme is developed
to artificially suppress the drain current spike by assigning all inversion
charges in the saturation region to the source electrode. Notice that this
charge partitioning scheme will still give drain current spikes in the linear
region and aggravate the source current spike problem.
7.3 ChargeThickness Capacitance Model (CTM)
mtrlMod=0
Current MOSFET models in SPICE generally overestimate the intrinsic
capacitance and usually are not smooth at V
fb
and V
th
. The discrepancy is
more pronounced in thinner T
ox
devices due to the assumption of inversion
and accumulation charge being located at the interface. Numerical quantum
simulation results in Figure 8.1 indicate the significant charge thickness in
all regions of operation.
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 57
Figure 7.1 Charge distribution from numerical quantum simulations show
significant charge thickness at various bias conditions shown in the inset.
CTM is a chargebased model and therefore starts with the DC charge
thickness, X
DC
. The charge thickness introduces a capacitance in series with
C
ox
as illustrated in Figure 7.2 , resulting in an effective C
oxeff
. Based on
numerical selfconsistent solution of Shrődinger, Poisson and FermiDirac
equations, universal and analytical X
DC
models have been developed. C
oxeff
can be expressed as
oxp cen
oxeff
oxp cen
C C
C
C C
⋅
=
+
(7.23)
where
/
cen si DC
C X ε = (7.24)
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 58
Figure 7.2 Chargethickness capacitance concept in CTM. V
gse
accounts for the poly
depletion effect.
(i) X
DC
for accumulation and depletion
The DC charge thickness in the accumulation and depletion regions can be
expressed by
0.25
16
1
exp
3 2 10
gse bseff FBeff
DC debye
V V V
NDEP
X L ACDE
TOXP
−
− −
 
= ⋅ ⋅

×
\ .
(7.25)
where L
debye
is Debye length, and X
DC
is in the unit of cm and (V
gse
 V
bseff

V
FBeff
) / TOXP is in units of MV/cm. For numerical stability, (8.25) is
replaced by (8.26)
( )
2
max 0 0 max
1
4
2
DC x
X X X X X δ = − + +
(7.26)
where
0 max DC x
X X X δ = − − (7.27)
and X
max
= L
debye
/ 3; = 10
3
TOXE.
(ii) X
DC
of inversion charge
The inversion charge layer thickness can be formulated as
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 59
( )
9
0.7
1.9 10 m
4 0
1
2
DC BDOS
gsteff s
ADOS
X
V VTH VFB
TOXP
−
×
× ×
=
+ − −Φ  
+

\ .
(7.28)
Here, the density of states parameters ADOS and BDOS are introduced to
control the charge centroid. Their default values are one.
Through the VFB term, equation (7.28) is found to be applicable to N
+
or P
+
polySi gates and even other future gate materials.
(iii) Body charge thickness in inversion
In inversion region, the body charge thickness effect is modeled by
including the deviation of the surface potential Ф
S
(biasdependence) from 2
Ф
B
[2]
1
2
1
( 2 2
2 ln 1
gsteffCV gsteffCV ox B
s B t
ox t
V V K
MOIN K
δ
ϕ ν
ν
 
⋅ + Φ
= Φ − Φ = + 

⋅
\ .
(7.29)
The channel charge density is therefore derived as
( )
, inv oxeff gsteff CV
eff
q C V
δ
ϕ = − ⋅ −
(7.30)
where
(7.31)
mtrlMod=1
First, TOXP should be iteratively calculated by EOT as follows:
, 0
3.9
gs ds bs
DC
V VDDEOT V V
TOXP EOT X
EPSRSUB
= = =
= − ×
(7.32)
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 60
9
0.7
1.9 10
( 0 )
1
2
DC BDOS
gsteff s
ADOS
X
V VTH VFB
TOXP
φ
−
×
× ×
=
+ − −  
+

\ .
(7.33)
With the calculated TOXP, X
DC
could be obtained at different gate voltage.
Now C
cen
is equal to EPSRSUB/X
DC
. The other calculations are as same as
mtrlMod=0.
7.4 Intrinsic Capacitance Model Equations
7.4.1 capMod = 0
Accumulation region
( )
g active active oxe gs bs
Q W L C V V VFBCV = − − (7.34)
sub g
Q Q = −
(7.35)
0
inv
Q = (7.36)
Subthreshold region
( )
2
1
0 2
1
4
1 1
2
gs bs
ox
sub active active oxe
ox
V VFBCV V
K
Q W L C
K
 
− −

= − ⋅ − + +

\ .
(7.37)
0 g sub
Q Q = −
(7.38)
0
inv
Q = (7.39)
Strong inversion region
,
'
gs th
dsat cv
bulk
V V
V
A
−
=
(7.40)
' 1
CLE
bulk bulk
eff
CLC
A A
L
 
 

= +



\ .
\ .
(7.41)
1 th s ox s bseff
V VFBCV K V = + Φ + Φ − (7.42)
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 61
Linear region
2
'
' 2
12
2
ds bulk ds
g oxe active active gs s
bulk ds
gs th
V A V
Q C W L V VFBCV
A V
V V
 


= − −Φ − +
  
− −
 
\ . \ .
(7.43)
(7.44)
( ) ( )
2
1 ' 1 ' '
' 2
12
2
bulk ds bulk bulk ds
b oxe active active th s
bulk ds
gs th
A V A A V
Q C W L VFBCV V
A V
V V
 

− −

= − −Φ + −
  
− −
 
\ . \ .
50/50 partitioning:
2 2
' '
' 2
12
2
bulk ds bulk ds
inv oxe active active gs th s
bulk ds
gs th
A V A V
Q C W L V V
A V
V V
 


= − − −Φ − +
  
− −
 
\ . \ .
(7.45)
0.5
s d inv
Q Q Q = = (7.46)
40/60 partitioning:
(7.47)
( ) ( ) ( )
( )
2
2
'
'
6 8 40
2
'
2
'
'
2 2
12
gs th bulk ds gs th
bulk ds
bulk ds
V V A V V V
A V
bulk ds
gs th
bulk ds
d oxe active active
A V
gs th
A V
V V
A V
Q C W L
V V
− −  
− +

−
 = − − +

− −

\ .
( )
s g b d
Q Q Q Q = − + + (7.48)
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 62
0/100 partitioning:
( )
2
' '
2 4 24
gs th bulk ds bulk ds
d oxe active active
V V A V A V
Q C W L
 
−
= − + − 

\ .
(7.49)
( )
s g b d
Q Q Q Q = − + + (7.50)
Saturation region:
3
dsat
g oxe active active gs s
V
Q C W L V VFBCV
 
= − −Φ −

\ .
(7.51)
( ) 1 '
3
bulk dsat
b oxe active active s th
A V
Q C W L VFBCV V
−  
= − +Φ − +

\ .
(7.52)
50/50 partitioning:
( )
1
3
s d oxe active active gs th
Q Q C W L V V = = − −
(7.53)
40/60 partitioning:
( )
4
15
d oxe active active gs th
Q C W L V V = − −
(7.54)
( )
s g b d
Q Q Q Q = − + + (7.55)
0/100 partitioning:
0
d
Q = (7.56)
( )
s g b
Q Q Q = − + (7.57)
7.4.2 capMod = 1
( )
0 g inv acc sub sub
Q Q Q Q Q δ = − + + + (7.58)
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 63
( )
s g b d
Q Q Q Q = − + + (7.59)
inv s d
Q Q Q = + (7.60)
( )
acc active active oxe FBeff fbzb
Q W L C V V = − ⋅ − (7.61)
( )
2
1
0 2
1
4 V
1 1
2
gse FBeff gsteff bseff
ox
sub active active oxe
ox
V V V
K
Q W L C
K
− − −
= − ⋅ ⋅ + +
(7.62)
,
'
gsteffcv
dsat cv
bulk
V
V
A
=
(7.63)
2 2
,
,
'
1
'
' 2
12
2
bulk cveff
inv active active oxe gsteff cv bulk cveff
bulk cveff
gsteff cv
A V
Q W L C V A V
A V
V
= − ⋅ − +
 
⋅ −

\ .
(7.64)
( )
2
,
1 ' '
1 '
' 2
12
2
bulk bulk cveff
bulk
sub active active oxe cveff
bulk cveff
gsteff cv
A A V
A
Q W L C V
A V
V
δ
− ⋅
−
= ⋅ −
 
⋅ −

\ .
(7.65)
50/50 charge partitioning:
2 2
,
,
'
1
'
' 2 2
12
2
bulk cveff
active active oxe
S D gsteff cv bulk cveff
bulk cveff
gsteff cv
A V
W L C
Q Q V A V
A V
V
= = − − +
 
⋅ −

\ .
(7.66)
40/60 charge partitioning:
( ) ( )
3 2
, ,
2
2 3
,
,
4
'
3
2 2
'
' '
2
2
3 15
gsteff cv gsteff cv bulk cveff
active active oxe
S
bulk cveff
gsteff cv bulk cveff bulk cveff
gsteff cv
V V A V
W L C
Q
A V
V A V A V
V
−
= −
 
+ −
−

\ .
(7.67)
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 64
( ) ( )
3 2
, ,
2
2 3
,
,
5
'
3
1
'
' '
2
2
5
gsteff cv gsteff cv bulk cveff
active active oxe
D
bulk cveff
gsteff cv bulk cveff bulk cveff
gsteff cv
V V A V
W L C
Q
A V
V A V A V
V
−
= −
 
+ −
−

\ .
(7.68)
0/100 charge partitioning:
2 2
,
,
'
1
'
' 2 2
12
2
bulk cveff
active active oxe
S gsteff cv bulk cveff
bulk cveff
gsteff cv
A V
W L C
Q V A V
A V
V
= − ⋅ + −
 
⋅ −

\ .
(7.69)
2 2
,
,
'
3
'
' 2 2
4
2
bulk cveff
active active oxe
D gsteff cv bulk cveff
bulk dveff
gsteff cv
A V
W L C
Q V A V
A V
V
= − ⋅ − +
 
⋅ −

\ .
(7.70)
7.4.3 capMod = 2
acc active active oxeff gbacc
Q W L C V = ⋅
(7.71)
2
0 0
1
0.08
2
gbacc fbzb
V V V V
= ⋅ + +
(7.72)
0
0.02
fbzb bseff gs
V V V V = + − −
(7.73)
( )
2
1 1
1
0.08
2
cveff dsat dsat
V V V V V = − ⋅ + +
(7.74)
1
0.02
dsat ds
V V V = − − (7.75)
,
'
gsteff cv
dsat
bulk
V
V
A
δ
ϕ −
=
(7.76)
( ) ( ) ( )
2
, , ,
0.5 0.001 0.001
gsteff CV gsteff CV gsteff CV g
eff
V V V V
δ δ δ
ϕ ϕ ϕ
− = ⋅ − − + − − +
(7.77)
( )
2
,
1
0 2
1
4 V
1 1
2
gse FBeff bseffs gsteff cv
ox
sub active active oxeff
ox
V V V
K
Q W L C
K
− − −
= − ⋅ ⋅ + +
(7.78)
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 65
( )
2
,
1 ' '
1 '
' 2
12
2
bulk bulk cveff
bulk
sub active active oxeff cveff
bulk cveff
gsteff cv
A A V
A
Q W L C V
A V
V
δ
δ
ϕ
− ⋅
−
= ⋅ −
 
⋅ − −

\ .
(7.79)
(7.80)
( ) ( )
2
1 ' 1 ' '
' 2
12
2
bulk ds bulk bulk ds
b oxe active active th s
bulk ds
gs th
A V A A V
Q C W L VFBCV V
A V
V V
 

− −

= − −Φ + −
  
− −
 
\ . \ .
50/50 partitioning:
(7.81)
( )
2 2
,
,
'
1
'
' 2 2
12
2
active active oxeff bulk cveff
S D gsteff cv bulk cveff
bulk cveff
gsteff cv
eff
W L C A V
Q Q V A V
A V
V
δ
δ
ϕ
ϕ
= = − − − +
 
⋅ − −

\ .
40/60 partitioning:
(7.82)
( ) ( )
( )( ) ( )
3 2
, ,
2
2 3
,
,
4
'
3
2 2
'
' '
2
2
3 15
gsteff cv gsteff cv bulk cveff
active active oxeff
S
bulk cveff
gsteff cv bulk cveff bulk cveff
gsteff cv
V V A V
W L C
Q
A V
V A V A V
V
δ δ
δ
δ
ϕ ϕ
ϕ
ϕ
− − −
= −
 
+ − −
− −

\ .
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 66
(7.83)
( ) ( )
( )( ) ( )
3 2
, ,
2
2 3
,
,
5
'
3
1
'
' '
2
2
5
gsteff cv gsteff cv bulk cveff
active active oxeff
D
bulk cveff
gsteff cv bulk cveff bulk cveff
gsteff cv
V V A V
W L C
Q
A V
V A V A V
V
δ δ
δ
δ
ϕ ϕ
ϕ
ϕ
− − −
= −
 
+ − −
− −

\ .
0/100 partitioning:
(7.84)
2 2
,
,
'
1
'
' 2 2
12
2
active active oxeff bulk cveff
S gsteff cv bulk cveff
bulk cveff
gsteff cv
W L C A V
Q V A V
A V
V
δ
δ
ϕ
ϕ
= − ⋅ − + −
 
⋅ − −

\ .
(7.85)
( )
( )
2 2
,
,
'
3
'
' 2 2
4
2
active active oxeff bulk cveff
D gsteff cv bulk cveff
eff
bulk dveff
gsteff cv
eff
W L C A V
Q V A V
A V
V
δ
δ
ϕ
ϕ
= − ⋅ − − +
 
⋅ − −

\ .
7.5 Fringing/Overlap Capacitance Models
7.5.1 Fringing capacitance model
The fringing capacitance consists of a biasindependent outer fringing
capacitance and a biasdependent inner fringing capacitance. Only the bias
independent outer fringing capacitance (CF) is modeled. If CF is not given,
it is calculated by
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 67
0
2 4.0 7
log 1
EPSROX e
CF
TOXE
ε
π
⋅ ⋅ −  
= ⋅ +

\ .
(7.86)
7.5.2 Overlap capacitance model
An accurate overlap capacitance model is essential. This is especially true
for the drain side where the effect of the capacitance is amplified by the
transistor gain. In old capacitance models this capacitance is assumed to be
bias independent. However, experimental data show that the overlap
capacitance changes with gate to source and gate to drain biases. In a single
drain structure or the heavily doped S/D to gate overlap region in a LDD
structure the bias dependence is the result of depleting the surface of the
source and drain regions. Since the modulation is expected to be very small,
we can model this region with a constant capacitance. However in LDD
MOSFETs a substantial portion of the LDD region can be depleted, both in
the vertical and lateral directions. This can lead to a large reduction of the
overlap capacitance. This LDD region can be in accumulation or depletion.
We use a single equation for both regions by using such smoothing
parameters as V
gs,overlap
and V
gd,overlap
for the source and drain side,
respectively. Unlike the case with the intrinsic capacitance, the overlap
capacitances are reciprocal. In other words, C
gs,overlap
= C
sg,overlap
and C
gd,overlap
= C
dg,overlap
.
If capMod is nonzero, BSIM4 uses the biasdependent overlap capacitance
model; otherwise, a simple biasindependent model will be used.
Biasdependent overlap capacitance model
(i) Source side
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 68
,
,
,
4
1 1
2
overlap s
active
gs overlap
gs gs gs overlap
Q
W
V
CKAPPAS
CGSO V CGSL V V
CKAPPAS
=
   
 ⋅ + − − − + − 
 
\ . \ .
(7.87)
( )
2
, 1 1 1 1
1
( ) 4 0.02
2
gs overlap gs gs
V V V V δ δ δ δ = + − + + =
(7.88)
(ii) Drain side
,
,
,
4
1 1
2
overlap d
gd
active
gd overlap
gd gd overlap
Q
CGDO V
W
V
CKAPPAD
CGDL V V
CKAPPAD
= ⋅
   
 + − − − + − 
 
\ . \ .
(7.89)
( )
2
, 1 1 1 1
1
( ) 4 0.02
2
gd overlap gd gd
V V V V δ δ δ δ = + − + + =
(7.90)
(iii) Gate Overlap Charge
( ) ( )
, , , overlap g overlap d overlap s active gb
Q Q Q CGBO L V = − + + ⋅ ⋅ (7.91)
where CGBO is a model parameter, which represents the gatetobody
overlap capacitance per unit channel length.
Biasindependent overlap capacitance model
If capMod = 0, a biasindependent overlap capacitance model will be used.
In this case, model parameters CGSL, CGDL, CKAPPAS and CKAPPD all
have no effect.
The gatetosource overlap charge is expressed by
Capacitance Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 69
, overlap s active gs
Q W CGSO V = ⋅ ⋅
(7.92)
The gatetodrain overlap charge is calculated by
, overlap d active gd
Q W CGDO V = ⋅ ⋅
(7.93)
The gatetosubstrate overlap charge is computed by
, overlap b active gb
Q L CGBO V = ⋅ ⋅
(7.94)
Default CGSO and CGDO
If CGSO and CGDO (the overlap capacitances between the gate and the
heavily doped source / drain regions, respectively) are not given, they will
be calculated. Appendix A gives the information on how CGSO, CGDO and
CGBO are calculated.
New Material Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 70
Chapter 8: New Material Models
The enormous success of CMOS technology in the past is mainly resulted
from the continuous scaling of MOSFET device. Until very recently, the
evolutionary scaling (such as gate dielectric) is based on the shrinking of
physical dimensions. Many fundamental problems, such as increased gate
leakage and oxide breakdown, have arisen from this conventional method.
One of the effective solutions is to introduce new materials to replace the
conventional material (For example, the silicon oxide gate is substituted by
the highk gate insulator). Significant progress has been achieved in terms of
the understanding of new material properties and their integration into
CMOS technology.
Considering the impacts of new materials on the electrical characteristics,
BSIM introduces the new material model, which could predict well the non
SiO
2
gate insulator, nonpolySi gate and nonSi channel.
8.1 Model Selector
One global selector is provided to turn on or off the new material models.
When the selector (mtrlMod) is set to one, the new materials are modeled;
while the default value (mtrlMod=0) maintains the backward compatibility.
8.2 NonSilicon Channel
With the three new parameters, the temperaturedependent band gap and
intrinsic carriers in nonsilicon channel are described as follow:
2
0 0
TBGASUB Tnom
Eg BG SUB
Tnom TBGBSUB
×
= −
+
(8.1)
New Material Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 71
2
300.15
(300.15) 0
300.15
TBGASUB
Eg BG SUB
TBGBSUB
×
= −
+
(8.2)
3/ 2
(300.15) 0
0 exp
300.15 2
i
t
Tnom Eg Eg
n NI SUB
v
  −  
= × ×
 
\ .
\ .
(8.3)
2
0
TBGASUB Temp
Eg BG SUB
Temp TBGBSUB
×
= −
+
(8.4)
Here, BG0SUB is the bandgap of substrate at T=0K; TBGASUB and
TBGBSUB are the first and second parameters of bandgap change due to
temperature, respectively.
The inversion charge layer thickness (X
DC
) is also modified as follows:
9
0.7
1.9 10
( 0 )
1
2
DC BDOS
gsteff s
ADOS
X
V VTH VFB
TOXP
φ
−
×
× ×
=
+ − −  
+

\ .
(8.5)
Here, the density of states parameters ADOS and BDOS are introduced to
control the charge centroid.
8.3 NonSiO
2
Gate insulator
For NonSiO
2
gate insulator, the equivalent SiO
2
thickness (EOT) is a new
input parameter, which is measured at VDDEOT. Given this new parameter,
the physical gate oxide thickness TOXP could be calculated as follows:
, 0
3.9
gs ds bs
DC
V VDDEOT V V
TOXP EOT X
EPSRSUB
= = =
= − ×
(8.6)
Here, EPSRSUB is the dielectric constant of substrate relative to vacuum.
New Material Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 72
8.4 NonPoly Silicon Gate Dielectric
Two new parameters are introduced to describe the nonpoly silicon gate
dielectric. One is PHIG, which is the gate work function. Another is
EPSRGATE, the dielectric constant of gate relative to vacuum. It is worth
pointing out that EPSRGATE=0 represents the metal gate and deactivates
the ploy depletion effect.
When the gate dielectric and channel are different materials, the flat band
voltage at Source/Drain is calculated using the following:
0 0
( 4 , ln
2 2
fbsd t
i
Eg Eg NSD
V PHIG EASUB BSIM typy MIN v
n
   
= − + − ×
 

\ . \ .
(8.7)
This new flat band equation improves the GIDL/GISL models as following:
3
3
3.9
3.9
exp
ds gse fbsd
GIDL effCJ
db
ds gse fbsd db
V V EGIDL V
I AGIDL W Nf
EPSRSUB
EOT
EPSRSUB
EOT BGIDL
V
V V EGIDL V CGIDL V
− − +
= ⋅ ⋅ ⋅
⋅
 
⋅ ⋅

− ⋅

− − + +

\ .
(8.8)
3
3
3.9
3.9
exp
ds gse fbsd
GIDS effCJ
db
ds gse fbsd db
V V EGISL V
I AGISL W Nf
EPSRSUB
EOT
EPSRSUB
EOT BGISL
V
V V EGISL V CGISL V
− − +
= ⋅ ⋅ ⋅
⋅
 
⋅ ⋅

− ⋅

− − + +

\ .
(8.9)
Furthermore, for mtrlMod=1 the mobility degradation uses the new
expression of the vertical field in channel as following:
New Material Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 73
(8.10)
2 2 4 ( / 2 0.45)
3.9
gsteff th
eff
V V BSIM type PHIG EASUB Eg
E
EOT EPSRSUB
+ − ⋅ ⋅ − − +
= ×
Consequently, when mtrlMod=1, mobMod=0 and mobMod=1 are changed,
respectively:
mobMod=0
2
2
2
0 ( )
1 ( )
2 0.00001
eff
eff
th
bseff eff eff
gsteff th
U f L
V EOT
UA UC V E UB E UD
V V
u
⋅
=
 
⋅

+ + ⋅ + ⋅ +

+ +
\ .
(8.11)
mobMod=1
2
2
2
0 ( )
1 ( )(1 )
2 0.00001
eff
eff
th
eff eff bseff
gsteff th
U f L
V EOT
UA E UB E UC V UD
V V
u
⋅
=
 
⋅

+ ⋅ + ⋅ + ⋅

+ +
\ .
(8.12)
.
HighSpeed/RF Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 74
Chapter 9: HighSpeed/RF Models
As circuit speed and operating frequency rise, the need for accurate
prediction of circuit performance near cutoff frequency or under very rapid
transient operation becomes critical. BSIM4.0.0 provides a set of accurate
and efficient highspeed/RF (radio frequency) models which consist of three
modules: chargedeficit nonquasistatic (NQS) model, intrinsicinput
resistance (IIR) model (biasdependent gate resistance model), and substrate
resistance network model. The chargedeficit NQS model comes from
BSIM3v3.2 NQS model [11] but many improvements are added in BSIM4.
The IIR model considers the effect of channelreflected gate resistance and
therefore accounts for the firstorder NQS effect [12]. Thus, the charge
deficit NQS model and the IIR model should not be turned on
simultaneously. These two models both work with multifinger
configuration. The substrate resistance model does not include any geometry
dependence.
9.1 ChargeDeficit NonQuasiStatic (NQS) Model
BSIM4 uses two separate model selectors to turn on or off the chargedeficit
NQS model in transient simulation (using trnqsMod) and AC simulation
(using acnqsMod). The AC NQS model does not require the internal NQS
charge node that is needed for the transient NQS model. The transient and
AC NQS models are developed from the same fundamental physics: the
channel/gate charge response to the external signal are relaxationtime (τ)
dependent and the transcapacitances and transconductances (such as G
m
) for
AC analysis can therefore be expressed as functions of jωτ.
HighSpeed/RF Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 75
MOSFET channel region is analogous to a biasdependent RC distributed
transmission line (Figure 10. 1a). In the QuasiStatic (QS) approach, the gate
capacitor node is lumped with the external source and drain nodes (Figure
10. 1b). This ignores the finite time for the channel charge to buildup. One
way to capture the NQS effect is to represent the channel with n transistors
in series (Figure 10.1c), but it comes at the expense of simulation time. The
BSIM4 chargedeficit NQS model uses Elmore equivalent circuit to model
channel charge buildup, as illustrated in Figure 9.1d.
Figure 9.1 QuasiStatic and NonQuasiStatic models for SPICE
analysis.
9.1.1 Transient Model
The transient chargedeficit NQS model can be turned on by setting
trnqsMod = 1 and off by setting trnqsMod = 0.
Figure 10.2 shows the RC subcircuit of charge deficit NQS model for
transient simulation [13]. An internal node, Q
def
(t), is created to keep track of
the amount of deficit/surplus channel charge necessary to reach equilibrium.
The resistance R is determined from the RC time constant (τ). The current
HighSpeed/RF Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 76
source i
cheq
(t) represents the equilibrium channel charging effect. The
capacitor C is to be the value of C
fact
(with a typical value of Farad [11]) to
improve simulation accuracy. Q
def
now becomes
( )
def def fact
Q t V C = × (9.1)
Figure 9.2 Charge deficit NQS subcircuit for transient analysis.
Considering both the transport and charging component, the total current
related to the terminals D, G and S can be written as
, ,
, , , ,
( )
( ) ( )
d g s
D G S D G S
Q t
i t I DC
t
∂
= +
∂
(9.2)
Based on the relaxation time approach, the terminal charge and
corresponding charging current are modeled by
( ) ( ) ( )
def cheq ch
Q t Q t Q t = − (9.3)
and
, ,
( ) ( ) ( )
d g s cheq def
Q t Q t Q t
t t τ
∂ ∂
=
∂ ∂
(9.4)
HighSpeed/RF Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 77
, ,
( ) ( )
, ,
d g s def
xpart
Q t Q t
D G S
t τ
∂
=
∂
(9.5)
where D,G,S
xpart
are charge deficit NQS channel charge partitioning number
for terminals D, G and S, respectively; D
xpart
+ S
xpart
= 1 and G
xpart
= 1.
The transit time τ is equal to the product of R
ii
and W
eff
L
eff
C
oxe
, where R
ii
is
the intrinsicinput resistance [12] given by
1
1 2
eff eff oxeff B
ds
ii dseff eff
W C k T
I
XRCRG XRCRG
R V qL
u  
= ⋅ + ⋅


\ .
(9.6)
where C
oxeff
is the effective gate dielectric capacitance calculated from the
DC model. Note that R
ii
in (9.6) considers both the drift and diffusion
componets of the channel conduction, each of which dominates in inversion
and subthreshold regions, respectively.
9.1.2 AC Model
Similarly, the smallsignal AC chargedeficit NQS model can be turned on
by setting acnqsMod = 1 and off by setting acnqsMod = 0.
For small signals, by substituting (9.3) into (9.5), it is easy to show that in
the frequency domain, Q
ch
(t) can be transformed into
( )
( )
1
cheq
ch
Q t
Q t
jωτ
∆
∆ =
+
(9.7)
where ω is the angular frequency. Based on (9.7), it can be shown that the
transcapacitances C
gi
, C
si
, and C
di
(i stands for any of the G, D, S and B
terminals of the device) and the channel transconductances G
m
, G
ds
, and G
mbs
all become complex quantities. For example, now G
m
have the form of
HighSpeed/RF Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 78
0 0
2 2 2 2
1 1
m m
m
G G
G j
ωτ
ω τ ω τ
⋅  
= + −

+ +
\ .
(9.8)
and
0 0
2 2 2 2
1 1
dg dg
dg
C C
C j
ωτ
ω τ ω τ
⋅  
= + −

+ +
\ .
(9.9)
Those quantities with sub “0” in the above two equations are known from
OP (operating point) analysis.
9.2 Gate Electrode Electrode and IntrinsicInput
Resistance (IIR) Model
9.2.1 General Description
BSIM4 provides four options for modeling gate electrode resistance (bias
independent) and intrinsicinput resistance (IIR, biasdependent). The IIR
model considers the relaxationtime effect due to the distributive RC nature
of the channel region, and therefore describes the firstorder nonquasistatic
effect. Thus, the IIR model should not be used together with the charge
deficit NQS model at the same time. The model selector rgateMod is used to
choose different options.
9.2.2 Model Option and Schematic
rgateMod = 0 (zeroresistance):
In this case, no gate resistance is generated.
HighSpeed/RF Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 79
rgateMod = 1 (constantresistance):
In this case, only the electode gate resistance (biasindependent) is generated
by adding an internal gate node. Rgeltd is give by
( )
( )
3
effcj
W
NGCON
drawn
RSHG XGW
Rgeltd
NGCON L XGL NF
⋅
⋅ +
=
⋅ − ⋅
(9.10)
Refer to Chapter 8 for the layout parameters in the above equation.
rgateMod = 2 (IIR model with variable resistance):
In this case, the gate resistance is the sum of the electrode gate resistance
(9.10) and the intrinsicinput resistance R
ii
as given by (9.6). An internal gate
node will be generated. trnqsMod = 0 (default) and acnqsMod = 0 (default)
should be selected for this case.
HighSpeed/RF Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 80
rgateMod = 3 (IIR model with two nodes):
In this case, the gate electrode resistance given by (9.10) is in series with the
intrinsicinput resistance R
ii
as given by (9.6) through two internal gate
nodes, so that the overlap capacitance current will not pass through the
intrinsicinput resistance. trnqsMod = 0 (default) and acnqsMod = 0 (default)
should be selected for this case.
9.3 Substrate Resistance Network
9.3.1 General Description
For CMOS RF circuit simulation, it is essential to consider the high
frequency coupling through the substrate. BSIM4 offers a flexible builtin
substrate resistance network. This network is constructed such that little
simulation efficiency penalty will result. Note that the substrate resistance
parameters as listed in Appendix A should be extracted for the total device,
not on a perfinger basis.
9.3.2 Model Selector and Topology
The model selector rbodyMod can be used to turn on or turn off the
resistance network.
rbodyMod = 0 (Off):
HighSpeed/RF Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 81
No substrate resistance network is generated at all.
rbodyMod = 1 (On):
All five resistances in the substrate network as shown schematically below
are present simultaneously.
A minimum conductance, GBMIN, is introduced in parallel with each
resistance and therefore to prevent infinite resistance values, which would
otherwise cause poor convergence. In Figure 8.3, GBMIN is merged into
each resistance to simplify the representation of the model topology. Note
that the intrinsic model substrate reference point in this case is the internal
body node bNodePrime, into which the impact ionization current I
ii
and the
GIDL current I
GIDL
flow.
rbodyMod = 2 (On : Scalable Substrate Network):
The schematic is similar to rbodyMod = 1 but all the five resistors in the
substrate network are now scalable with a possibility of choosing either five
resistors, three resistors or one resistor as the substrate network.
The resistors of the substrate network are scalable with respect to channel
length (L), channel width (W) and number of fingers (NF). The scalable
model allows to account for both horizontal and vertical contacts.
The scalable resistors RBPS and RBPD are evaluated through
HighSpeed/RF Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 82
6 6
0
10 10
RBPSL RBPSW
RBPSNF
L W
RBPS RBPS NF
− −
   
= • • •
 
\ . \ .
(9.11)
6 6
0
10 10
RBPDL RBPDW
RBPDNF
L W
RBPD RBPD NF
− −
   
= • • •
 
\ . \ .
(9.12)
The resistor RBPB consists of two parallel resistor paths, one to the
horizontal contacts and other to the vertical contacts. These two resistances
are scalable and RBPB is given by a parallel combination of these two
resistances.
6 6
0
10 10
RBPBXL RBPBXW
RBPBNF
L W
RBPBX RBPBX NF
− −
   
= • • •
 
\ . \ .
(9.13)
6 6
0
10 10
RBPBYL RBPBYW
RBPBYNF
L W
RBPBY RBPBY NF
− −
   
= • • •
 
\ . \ .
(9.14)
RBPBX RBPBY
RBPB
RBPBX RBPBY
•
=
+
(9.15)
The resistors RBSB and RBDB share the same scaling parameters but have
different scaling prefactors. These resistors are modeled in the same way as
RBPB. The equations for RBSB are shown below. The calculation for RBDB
follows RBSB.
6 6
0
10 10
RBSDBXL RBSDBXW
RBSDBXNF
L W
RBSBX RBSBX NF
− −
   
= • • •
 
\ . \ .
(9.16)
6 6
0
10 10
RBSDBYL RBSDBYW
RBSDBYNF
L W
RBSBY RBSBY NF
− −
   
= • • •
 
\ . \ .
(9.17)
RBSBX RBSBY
RBSB
RBSBX RBSBY
•
=
+
(9.18)
HighSpeed/RF Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 83
The implementation of rbodyMod = 2 allows the user to chose between the
5R network (with all five resistors), 3R network (with RBPS, RBPD and
RBPB) and 1R network (with only RBPB).
If the user doesn’t provide both the scaling parameters RBSBX0 and RBSBY0
for RBSB OR both the scaling parameters RBDBX0 and RBDBY0 for RBDB,
then the conductances for both RBSB and RBDB are set to GBMIN. This
converts the 5R schematic to 3R schematic where the substrate network
consists of the resistors RBPS, RBPD and RBPB. RBPS, RBPD and RBPB
are then calculated using (9.10), (9.11) and (9.12).
If the user chooses not to provide either of RBPS0 or RBPD0, then the 5R
schematic is converted to 1R network with only one resistor RBPB. The
conductances for RBSB and RBDB are set to GBMIN. The resistances RBPS
and RBPD are set to 1e3 Ohm. The resistor RBPB is then calculated using
(9.12).
In all other situations, 5R network is used with the resistor values calculated
from the equations aforementioned.
Figure 9.3 Topology with the substrate resistance network
turned on.
Noise Modeling
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 84
Chapter 10: Noise Modeling
The following noise sources in MOSFETs are modeled in BSIM4 for SPICE
noise ananlysis: flicker noise (also known as 1/f noise), channel thermal
noise and induced gate noise and their correlation, thermal noise due to
physical resistances such as the source/ drain, gate electrode, and substrate
resistances, and shot noise due to the gate dielectric tunneling current. A
complete list of the noise model parameters and explanations are given in
Appendix A.
10.1 Flicker Noise Models
10.1.1 General Description
BSIM4 provides two flicker noise models. When the model selector
fnoiMod is set to 0, a simple flicker noise model which is convenient for
hand calculations is invoked. A unified physical flicker noise model, which
is the default model, will be used if fnoiMod = 1. These two modes come
from BSIM3v3, but the unified model has many improvements. For instance,
it is now smooth over all bias regions and considers the bulk charge effect.
10.1.2 Equations
fnoiMod = 0 (simple model)
The noise density is
( )
2
AF
ds
id EF
oxe eff
KF I
S f
C L f
⋅
=
(10.1)
Noise Modeling
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 85
where f is device operating frequency.
fnoiMod = 1 (unified model)
The physical mechanism for the flicker noise is trapping/detrappingrelated
charge fluctuation in oxide traps, which results in fluctuations of both
mobile carrier numbers and mobilities in the channel. The unified flicker
noise model captures this physical process.
In the inversion region, the noise density is expressed as [14]
(10.2)
( ) ( )
( )
2
2
10 2
2
2 2
0 0
0
10 2
2
10 2
2 10 2
*
l
l l
ef
eff eff
clm ds B
l l *
l
*
ef
bulk eff oxe
ds eff B
inv , id
N N
N NOIC N NOIB NOIA
f ) LINTNOI L ( W
L TI k
N N
NOIC
N N NOIB
N N
N N
log NOIA
f A ) LINTNOI L ( C
I Tq k
) f ( S
+
⋅ + ⋅ +
⋅
⋅ ⋅ − ⋅
∆
+


.

\

− + − ⋅ +


.

\

+
+
⋅
⋅ ⋅ −
=
u
where u
eff
is the effective mobility at the given bias condition, and L
eff
and
W
eff
are the effective channel length and width, respectively. The parameter
N
0
is the charge density at the source side given by
0 oxe gsteff
N C V q = ⋅
(10.3)
The parameter N
l
is the charge density at the drain end given by
1
2
bulk dseff
l oxe gsteff
gsteff t
A V
N C V q
V ν
 
= ⋅ ⋅ −


+
\ .
(10.4)
N
*
is given by
( ) *
2
B oxe d
k T C C CIT
N
q
⋅ + +
=
(10.5)
Noise Modeling
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 86
where CIT is a model parameter from DC IV and C
d
is the depletion
capacitance.
∆L
clm
is the channel length reduction due to channel length modulation and
given by
log
2
ds dseff
clm
sat
sat
eff
V V
EM
Litl
L Litl
E
VSAT
E
u
−  
+

∆ = ⋅ 


\ .
=
(10.6)
In the subthreshold region, the noise density is written as
( )
2
, *2 10
10
B ds
id subVt EF
eff eff
NOIA k T I
S f
W L f N
⋅ ⋅
=
⋅
(10.7)
The total flicker noise density is
( )
( ) ( )
( ) ( )
i , ,
, i ,
d inv id subvt
id
id subvt d inv
S f S f
S f
S f S f
×
=
+
(10.8)
10.2 Channel Thermal Noise
There are two channel thermal noise models in BSIM4. One is a charge
based model (default model) similar to that used in BSIM3v3.2. The other is
the holistic model. These two models can be selected through the model
selector tnoiMod.
tnoiMod = 0 (charge based)
The noise current is given by
( )
2
2
4
eff
eff inv
B
d
L
ds Q
k T f
i NTNOI
R V
u
∆
= ⋅
+
(10.9)
Noise Modeling
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 87
where R
ds
(V) is the biasdependent LDD source/drain resistance, and the
parameter NTNOI is introduced for more accurate fitting of shortchannel
devices. Q
inv
is modeled by
( )
2 2
2
2
12
bulk dseff
bulk dseff bulk dseff
inv active active oxeff gsteff
A V
gsteff
A V A V
Q W L C NF V
V
= ⋅ ⋅ − +
⋅ −
(10.10)
Figure 10.1a shows the noise source connection for tnoiMod =
0.
Figure 10.1 Schematic for BSIM4 channel thermal
noise modeling.
tnoiMod = 1 (holistic)
In this thermal noise model, all the shortchannel effects and velocity
saturation effect incorporated in the IV model are automatically included,
hency the name “holistic thermal noise model”. In addition, the
amplification of the channel thermal noise through G
m
and G
mbs
as well as
the inducedgate noise with partial correlation to the channel thermal noise
are all captured in the new “noise partition” model. Figure 10.1b shows
schematically that part of the channel thermal noise source is partitioned to
the source side.
The noise voltage source partitioned to the source side is given by
Noise Modeling
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 88
2 2
4
dseff
d B tnoi
ds
V f
v k T
I
θ
∆
= ⋅ ⋅
(10.11)
and the noise current source put in the channel region with gate and body
amplication is given by
( )
( )
2
2
2
2
4
dseff
d B ds tnoi m mbs
ds
d m ds mbs
V f
i k T G G G
I
v G G G
β
∆
= + ⋅ +
− ⋅ + +
(10.12)
where
2
1
gsteff
tnoi eff
sat eff
V
RNOIB TNOIB L
E L
θ
 
= ⋅ + ⋅ ⋅


\ .
(10.13)
and
2
1
gsteff
tnoi eff
sat eff
V
RNOIA TNOIA L
E L
β
 
= ⋅ + ⋅ ⋅


\ .
(10.14)
where RNOIB and RNOIA are model parameters with default values 0.37
and 0.577 respectively.
10.3 Other Noise Sources Modeled
BSIM4 also models the thermal noise due to the substrate, electrode gate,
and source/drain resistances. Shot noise due to various gate tunneling
components is modeled as well.
Asymmetric MOS Junction Diode Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 89
Chapter 11: Asymmetric MOS Junction
Diode Models
11.1 Junction Diode IV Model
In BSIM4, there are three junction diode IV models. When the IV model
selector dioMod is set to 0 ("resistancefree"), the diode IV is modeled as
resistancefree with or without breakdown depending on the parameter
values of XJBVS or XJBVD. When dioMod is set to 1 ("breakdownfree"),
the diode is modeled exactly the same way as in BSIM3v3.2 with current
limiting feature in the forwardbias region through the limiting current
parameters IJTHSFWD or IJTHDFWD; diode breakdown is not modeled for
dioMod = 1 and XJBVS, XJBVD, BVS, and BVD parameters all have no
effect. When dioMod is set to 2 ("resistanceandbreakdown"), BSIM4
models the diode breakdown with current limiting in both forward and
reverse operations. In general, setting dioMod to 1 produces fast
convergence.
11.1.1 Source/Body Junction Diode
In the following, the equations for the sourceside diode are given. The
model parameters are shown in Appendix A.
• dioMod = 0 (resistancefree)
min
exp 1
bs
bs sbs breakdown bs
B
qV
I I f V G
NJS k TNOM
 
= − ⋅ + ⋅

⋅
\ .
(11.1)
Asymmetric MOS Junction Diode Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 90
where I
sbs
is the total saturation current consisting of the components through
the gateedge (J
sswgs
) and isolationedge sidewalls (J
ssws
) and the bottom
junction (J
ss
),
( ) ( ) ( )
sbs seff ss seff ssws effcj sswgs
I A J T P J T W NF J T = + + ⋅ ⋅ (11.2)
where the calculation of the junction area and perimeter is discussed in
Chapter 12, and the temperaturedependent current density model is given in
Chapter 13. In (11.1), f
breakdown
is given by
( )
1 exp
bs
breakdown
B
q BVS V
f XJBVS
NJS k TNOM
⋅ +  
= + ⋅ −

⋅
\ .
(11.3)
In the above equation, when XJBVS = 0, no breakdown will be modeled. If
XJBVS < 0.0, it is reset to 1.0.
• dioMod = 1 (breakdownfree)
No breakdown is modeled. The exponential IV term in (11.5) is linearized at
the limiting current IJTHSFWD in the forwardbias model only.
min
exp 1
bs
bs sbs bs
B
qV
I I V G
NJS k TNOM
 
= − + ⋅

⋅
\ .
(11.4)
• dioMod = 2 (resistanceandbreakdown):
Diode breakdown is always modeled. The exponential term (11.5) is
linearized at both the limiting current IJTHSFWD in the forwardbias mode
and the limiting current IJTHSREV in the reversebias mode.
min
exp 1
bs
bs sbs breakdown bs
B
qV
I I f V G
NJS k TNOM
 
= − ⋅ + ⋅

⋅
\ .
(11.5)
For dioMod = 2, if XJBVS <= 0.0, it is reset to 1.0.
Asymmetric MOS Junction Diode Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 91
11.1.2 Drain/Body Junction Diode
The drainside diode has the same system of equations as those for the
sourceside diode, but with a separate set of model parameters as explained
in detail in Appendix A.
• dioMod = 0 (resistancefree)
min
exp 1
bd
bd sbd breakdown bd
B
qV
I I f V G
NJD k TNOM
 
= − ⋅ + ⋅

⋅
\ .
(11.6)
where I
sbd
is the total saturation current consisting of the components
through the gateedge (J
sswgd
) and isolationedge sidewalls (J
sswd
) and the
bottom junction (J
sd
),
( ) ( ) ( )
sbd deff sd deff sswd effcj sswgd
I A J T P J T W NF J T = + + ⋅ ⋅ (11.7)
where the calculation of the junction area and perimeter is discussed in
Chapter 11, and the temperaturedependent current density model is given in
Chapter 12. In (11.6), f
breakdown
is given by
( )
1 exp
bd
breakdown
B
q BVD V
f XJBVD
NJD k TNOM
⋅ +  
= + ⋅ −

⋅
\ .
(11.8)
In the above equation, when XJBVD = 0, no breakdown will be modeled. If
XJBVD < 0.0, it is reset to 1.0.
• dioMod = 1 (breakdownfree)
No breakdown is modeled. The exponential IV term in (11.9) is linearized at
the limiting current IJTHSFWD in the forwardbias model only.
min
exp 1
bd
bd sbd bd
B
qV
I I V G
NJD k TNOM
 
= − + ⋅

⋅
\ .
(11.9)
• dioMod = 2 (resistanceandbreakdown):
Asymmetric MOS Junction Diode Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 92
Diode breakdown is always modeled. The exponential term (11.10) is
linearized at both the limiting current IJTHSFWD in the forwardbias mode
and the limiting current IJTHSREV in the reversebias mode.
min
exp 1
bd
bd sbd breakdown bd
B
qV
I I f V G
NJD k TNOM
 
= − ⋅ + ⋅

⋅
\ .
(11.10)
For dioMod = 2, if XJBVD <= 0.0, it is reset to 1.0.
11.1.3 Total Junction Source/Drain Diode Including Tunneling
Total diode current including the carrier recombination and trapassisted
tunneling current in the spacecharge region is modeled by:
_
,
,
( ) exp 1
( ) 0
( ) exp 1
( ) 0
bs total bs
bs
effcj tsswgs
bs
bs
s deff tssws
bs
s deff tss
I I
V VTSSWGS
W NF J T
NJTSSWG T Vtm VTSSWGS V
V VTSSWS
P J T
NJTSSW T Vtm VTSSWS V
A J
=
  −
− ⋅ ⋅ ⋅ ⋅ −

⋅ −
\ .
  −
− ⋅ −

⋅ −
\ .
−
`min
( ) exp 1
( ) 0
bs
bs
bs
V VTSS
T g V
NJTS T Vtm VTSS V
  −
⋅ − + ⋅

⋅ −
\ .
(11.11)
_
,
,
( ) exp 1
( ) 0
( ) exp 1
( ) 0
bd total bd
bd
effcj tsswgd
bd
bd
d deff tsswd
bd
d deff t
I I
V VTSSWGD
W NF J T
NJTSSWGD T Vtm VTSSWGD V
V VTSSWD
P J T
NJTSSWD T Vtm VTSSWD V
A J
=
  −
− ⋅ ⋅ ⋅ ⋅ −

⋅ −
\ .
  −
− ⋅ −

⋅ −
\ .
−
`min
( ) exp 1
( ) 0
bd
sd bd
bd
V VTSD
T g V
NJTSD T Vtm VTSD V
  −
⋅ − + ⋅

⋅ −
\ .
(11.12)
Asymmetric MOS Junction Diode Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 93
11.2 Junction Diode CV Model
Source and drain junction capacitances consist of three components: the
bottom junction capacitance, sidewall junction capacitance along the
isolation edge, and sidewall junction capacitance along the gate edge. An
analogous set of equations are used for both sides but each side has a
separate set of model parameters.
11.2.1 Source/Body Junction Diode
The sourceside junction capacitance can be calculated by
bs seff jbs seff jbssw effcj jbsswg
C A C P C W NF C = + + ⋅ ⋅
(11.13)
where C
jbs
is the unitarea bottom S/B junciton capacitance, C
jbssw
is the
unitlength S/B junction sidewall capacitance along the isolation edge, and
C
jbsswg
is the unitlength S/B junction sidewall capacitance along the gate
edge. The effective area and perimeters in (11.13) are given in Chapter 11.
C
jbs
is calculated by
if V
bs
< 0
( )
( )
1
MJS
bs
jbs
V
C CJS T
PBS T
−
 
= ⋅ −


\ .
(11.14)
otherwise
( )
( )
1
bs
jbs
V
C CJS T MJS
PBS T
 
= ⋅ + ⋅


\ .
(11.15)
C
jbssw
is calculated by
if V
bs
< 0
Asymmetric MOS Junction Diode Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 94
( )
( )
1
MJSWS
bs
jbssw
V
C CJSWS T
PBSWS T
−
 
= ⋅ −


\ .
(11.16)
otherwise
( )
( )
1
bs
jbssw
V
C CJSWS T MJSWS
PBSWS T
 
= ⋅ + ⋅


\ .
(11.17)
C
jbsswg
is calculated by
if V
bs
< 0
( )
( )
1
MJSWGS
bs
jbsswg
V
C CJSWGS T
PBSWGS T
−
 
= ⋅ −


\ .
(11.18)
otherwise
( )
( )
1
MJSWGS
bs
jbsswg
V
C CJSWGS T
PBSWGS T
−
 
= ⋅ −


\ .
(11.19)
11.2.2 Drain/Body Junction Diode
The drainside junction capacitance can be calculated by
bd deff jbd deff jbdsw effcj jbdswg
C A C P C W NF C = + + ⋅ ⋅
(11.20)
where C
jbd
is the unitarea bottom D/B junciton capacitance, C
jbdsw
is the
unitlength D/B junction sidewall capacitance along the isolation edge, and
C
jbdswg
is the unitlength D/B junction sidewall capacitance along the gate
edge. The effective area and perimeters in (11.20) are given in Chapter 12.
C
jbd
is calculated by
if V
bd
< 0
( )
( )
1
MJD
bd
jbd
V
C CJD T
PBD T
−
 
= ⋅ −


\ .
(11.21)
otherwise
Asymmetric MOS Junction Diode Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 95
( )
( )
1
bd
jbd
V
C CJD T MJD
PBD T
 
= ⋅ + ⋅


\ .
(11.22)
C
jbdsw
is calculated by
if V
bd
< 0
( )
( )
1
MJSWD
bd
jbdsw
V
C CJSWD T
PBSWD T
−
 
= ⋅ −


\ .
(11.23)
otherwise
( )
( )
1
bd
jbdsw
V
C CJSWD T MJSWD
PBSWD T
 
= ⋅ + ⋅


\ .
(11.24)
C
jbdswg
is calculated by
if V
bd
< 0
( )
( )
1
MJSWGD
bd
jbdswg
V
C CJSWGD T
PBSWGD T
−
 
= ⋅ −


\ .
(11.25)
otherwise
( )
( )
1
bd
jbdswg
V
C CJSWGD T MJSWGD
PBSWGD T
 
= ⋅ + ⋅


\ .
(11.26)
LayoutDependent Parasitics Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 96
Chapter 12: LayoutDependent Parasitics
Models
BSIM4 provides a comprehensive and versatile geometry/layoutdependent
parasitcs model [15]. It supports modeling of series (such as isolated, shared,
or merged source/ drain) and multifinger device layout, or a combination of
these two configurations. This model have impact on every BSIM4 sub
models except the substrate resistance network model. Note that the narrow
width effect in the perfinger device with multifinger configuration is
accounted for by this model. A complete list of model parameters and
selectors can be found in Appendix A.
12.1 Geometry Definition
Figure 12.1 schematically shows the geometry definition for various
source/drain connections and source/drain/gate contacts. The layout
parameters shown in this figure will be used to calculate resistances and
source/drain perimeters and areas.
LayoutDependent Parasitics Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 97
Figure 12.1 Definition for layout parameters.
12.2 Model Formulation and Options
12.2.1 Effective Junction Perimeter and Area
In the following, only the sourceside case is illustrated. The same approach
is used for the drain side. The effective junction perimeter on the source side
is calculated by
LayoutDependent Parasitics Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 98
If (PS is given)
if (perMod == 0)
P
seff
= PS
else
NF W PS P
effcj seff
⋅ − =
Else
P
seff
computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG,
DMCGT, and MIN.
The effective junction area on the source side is calculated by
If (AS is given)
A
seff
= AS
Else
A
seff
computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG,
DMCGT, and MIN.
In the above, P
seff
and A
seff
will be used to calculate junction diode IV and
CV. P
seff
does not include the gateedge perimeter.
12.2.2 Source/Drain Diffusion Resistance
The source diffusion resistance is calculated by
If (number of source squares NRS is given)
RSH NRS R
sdiff
⋅ =
Else if (rgeoMod == 0)
Source diffusion resistance R
sdiff
is not generated.
Else
R
sdiff
computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG,
DMCGT, RSH, and MIN.
where the number of source squares NRS is an instance parameter. Similarly,
the drain diffusion resistance is calculated by
LayoutDependent Parasitics Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 99
If (number of source squares NRD is given)
RSH NRD R
ddiff
⋅ =
Else if (rgeoMod == 0)
Drain diffusion resistance R
ddiff
is not generated.
Else
R
ddiff
computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG,
DMCGT, RSH, and MIN.
12.2.3 Gate Electrode Resistance
The gate electrode resistance with multifinger configuration is modeled by
( )
( )
3
effcj
W
NGCON
drawn
RSHG XGW
Rgeltd
NGCON L XGL NF
⋅
⋅ +
=
⋅ − ⋅
(12.1)
12.2.4 Option for Source/Drain Connections
Table 12.1 lists the options for source/drain connections through the model
selector geoMod.
geoMod End source End drain Note
0 isolated isolated NF=Odd
1 isolated shared NF=Odd, Even
2 shared isolated NF=Odd, Even
3 shared shared NF=Odd, Even
4 isolated merged NF=Odd
5 shared merged NF=Odd, Even
6 merged isolated NF=Odd
7 merged shared NF=Odd, Even
8 merged merged NF=Odd
9 sha/iso shared NF=Even
10 shared sha/iso NF=Even
Table 12.1 geoMod options.
For multifinger devices, all inside S/D diffusions are assumed shared.
LayoutDependent Parasitics Models
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 100
12.2.5 Option for Source/Drain Contacts
Table 12.2 lists the options for source/drain contacts through the model
selector rgeoMod.
rgeoMod Endsource contact Enddrain contact
0 No R
sdiff
No R
ddiff
1 wide wide
2 wide point
3 point wide
4 point point
5 wide merged
6 point merged
7 merged wide
8 merged point
Table 12.2 rgeoMod options.
Temperature Dependence Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 101
Chapter 13: Temperature Dependence
Model
Accurate modeling of the temperature effects on MOSFET characteristics is
important to predict circuit behavior over a range of operating temperatures
(T). The operating temperature might be different from the nominal
temperature (TNOM) at which the BSIM4 model parameters are extracted.
This chapter presents the BSIM4 temperature dependence models for
threshold voltage, mobility, saturation velocity, source/drain resistance, and
junction diode IV and CV.
13.1 Temperature Dependence of Threshold
Voltage
The temperature dependence of V
th
is modeled by
( ) ( )
1
1 2 1
th th bseff
eff
KT L T
V T V TNOM KT KT V
L TNOM
 
 
= + + + ⋅ ⋅ −



\ .
\ .
(13.1)
( ) ( ) 1 1
fb fb
T
V T V TNOM KT
TNOM
 
= − ⋅ −

\ .
(13.2)
( ) ( ) ( ) [1 ] VOFF T VOFF TNOM TVOFF T TNOM = ⋅ + ⋅ − (13.3)
( ) ( )
( ) [1 ]
VFBSDOFF T VFBSDOFF TNOM
TVFBSDOFF T TNOM
=
⋅ + ⋅ −
(13.4)
13.2 Temperature Dependence of Mobility
The BSIM4 mobility model parameters have the following temperature
dependences depending on the model selected through TEMPMOD.
If TEMPMOD = 0,
Temperature Dependence Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 102
( ) ( ) ( ) 0 0
UTE
U T U TNOM T TNOM = ⋅
(13.5)
( ) ( ) ( ) 1 1 UA T UA TNOM UA T TNOM = + ⋅ − (13.6)
( ) ( ) ( ) 1 1 UB T UB TNOM UB T TNOM = + ⋅ − (13.7)
( ) ( ) ( ) 1 1 UC T UC TNOM UC T TNOM = + ⋅ − (13.8)
and
( ) ( ) ( ) 1 1 UD T UD TNOM UD T TNOM = + ⋅ − (13.9)
If TEMPMOD = 1 or 2,
( ) ( ) ( ) 0 0
UTE
U T U TNOM T TNOM = ⋅
(13.10)
( ) ( ) ( ) [1 1 ] UA T UA TNOM UA T TNOM = + ⋅ − (13.11)
( ) ( ) ( ) 1 1 UB T UB TNOM UB T TNOM = + ⋅ − (13.12)
( ) ( ) ( ) [1 1 ] UC T UC TNOM UC T TNOM = + ⋅ − (13.13)
and
( ) ( ) ( ) [1 1 ] UD T UD TNOM UD T TNOM = + ⋅ − (13.14)
If TEMPMOD = 3,
( ) ( ) ( ) 0 0
UTE
U T U TNOM T TNOM = ⋅
(13.15)
( ) ( ) ( )
UCSTE
UCS T UCS TNOM T TNOM = ⋅
(13.16)
( ) ( ) ( )
1
/
UA
UA T UA TNOM T TNOM = ⋅
(13.17)
( ) ( ) ( )
1
/
UB
UB T UB TNOM T TNOM = ⋅
(13.18)
( ) ( ) ( )
1
/
UC
UC T UC TNOM T TNOM = ⋅
(13.19)
and
Temperature Dependence Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 103
( ) ( ) ( )
1
/
UD
UD T UD TNOM T TNOM = ⋅
(13.20)
It is worth pointing out that tempMod=3 only affects the mobility. Other
parameters such as Rs and Rd are same as those in tempMod=2.
13.3 Temperature Dependence of Saturation Velocity
If TEMPMOD = 0, the temperature dependence of VSAT is modeled by
( ) ( ) ( ) 1 VSAT T VSAT TNOM AT T TNOM = − ⋅ − (13.21)
If TEMPMOD = 1, the temperature dependence of VSAT is modeled by
( ) ( ) ( ) [1 ] VSAT T VSAT TNOM AT T TNOM = − ⋅ − (13.22)
13.4 Temperature Dependence of LDD
Resistance
If TEMPMOD = 0,
rdsMod = 0 (internal source/drain LDD resistance)
( ) ( ) ( ) 1 RDSW T RDSW TNOM PRT T TNOM = + ⋅ − (13.23)
( ) ( ) ( ) 1 RDSWMIN T RDSWMIN TNOM PRT T TNOM = + ⋅ − (13.24)
rdsMod = 1 (external source/drain LDD resistance)
( ) ( ) ( ) 1 RDW T RDW TNOM PRT T TNOM = + ⋅ − (13.25)
( ) ( ) ( ) 1 RDWMIN T RDWMIN TNOM PRT T TNOM = + ⋅ − (13.26)
( ) ( ) ( ) 1 RSW T RSW TNOM PRT T TNOM = + ⋅ − (13.27)
and
Temperature Dependence Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 104
( ) ( ) ( ) 1 RSWMIN T RSWMIN TNOM PRT T TNOM = + ⋅ − (13.28)
If TEMPMOD = 1,
rdsMod = 0 (internal source/drain LDD resistance)
( ) ( ) ( ) [1 ] RDSW T RDSW TNOM PRT T TNOM = + ⋅ − (13.29)
( ) ( ) ( ) [1 ] RDSWMIN T RDSWMIN TNOM PRT T TNOM = + ⋅ − (13.30)
rdsMod = 1 (external source/drain LDD resistance)
( ) ( ) ( ) [1 ] RDW T RDW TNOM PRT T TNOM = + ⋅ − (13.31)
( ) ( ) ( ) [1 ] RDWMIN T RDWMIN TNOM PRT T TNOM = + ⋅ − (13.32)
( ) ( ) ( ) [1 ] RSW T RSW TNOM PRT T TNOM = + ⋅ − (13.33)
( ) ( ) ( ) [1 ] RSWMIN T RSWMIN TNOM PRT T TNOM = + ⋅ − (13.34)
13.5 Temperature Dependence of Junction
Diode IV
• Sourceside diode
The sourceside saturation current is given by
( ) ( ) ( )
sbs seff ss seff ssws effcj sswgs
I A J T P J T W NF J T = + + ⋅ ⋅ (13.35)
where
( ) ( )
( )
( )
( )
( )
ln
exp
g g
t t
ss
E TNOM E T
T
XTIS
v TNOM v T TNOM
J T JSS TNOM
NJS
 
 
− + ⋅
 
\ .

= ⋅



\ .
(13.36)
(13.37)
Temperature Dependence Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 105
( ) ( )
( )
( )
( )
( )
ln
exp
g g
t t
ssws
E TNOM E T
T
XTIS
v TNOM v T TNOM
J T JSSWS TNOM
NJS
 
 
− + ⋅
 
\ .

= ⋅



\ .
and
( ) ( )
( ) ( )
ln
exp
g g
b b
sswgs
E TNOM E T
T
XTIS
k TNOM k T TNOM
J T JSSWGS TNOM
NJS
 
 
− + ⋅
 
⋅ ⋅
\ .

= ⋅


\ .
(13.38)
where E
g
is given in Section 12.7.
• Drainside diode
The drainside saturation current is given by
( ) ( ) ( )
sbd deff sd deff sswd effcj sswgd
I A J T P J T W NF J T = + + ⋅ ⋅ (13.39)
where
( ) ( )
( ) ( )
ln
exp
g g
b b
sd
E TNOM E T
T
XTID
k TNOM k T TNOM
J T JSD TNOM
NJD
 
 
− + ⋅
 
⋅ ⋅
\ .

= ⋅


\ .
(13.40)
( ) ( )
( ) ( )
ln
exp
g g
b b
sswd
E TNOM E T
T
XTID
k TNOM k T TNOM
J T JSSWD TNOM
NJD
 
 
− + ⋅
 
⋅ ⋅
\ .

= ⋅


\ .
(13.41)
and
( ) ( )
( ) ( )
ln
exp
g g
b b
sswgd
E TNOM E T
T
XTID
k TNOM k T TNOM
J T JSSWGD TNOM
NJD
 
 
− + ⋅
 
⋅ ⋅
\ .

= ⋅


\ .
(13.42)
Temperature Dependence Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 106
• trapassisted tunneling and recombination current
( ) ( ) 1
( )
.exp 1
tsswgs tsswgs
effcj
tsswgs
B
JTWEFF
J T J TNOM
W
Eg TNOM T
X
k T TNOM
 
= ⋅ + 

\ .
−  
⋅ ⋅ −

\ .
(13.43)
( )
( ) ( ) exp 1
tssws tssws tssws
B
Eg TNOM T
J T J TNOM X
k T TNOM
−  
= ⋅ ⋅ ⋅ −

\ .
(13.44)
( )
( ) ( ) exp 1
tss tss tss
B
Eg TNOM T
J T J TNOM X
k T TNOM
−  
= ⋅ ⋅ ⋅ −

\ .
(13.45)
( ) ( ) 1
( )
.exp 1
tsswgd tsswgd
effcj
tsswgd
B
JTWEFF
J T J TNOM
W
Eg TNOM T
X
k T TNOM
 
= ⋅ + 

\ .
−  
⋅ ⋅ −

\ .
(13.46)
( )
( ) ( ) exp 1
tsd tsd tsd
B
Eg TNOM T
J T J TNOM X
k T TNOM
−  
= ⋅ ⋅ ⋅ −

\ .
(13.47)
( ) ( ) 1 1
T
NJTSSWG T NJTSSWG TNOM TNJTSSWG
TNOM
 
= ⋅ + −

\ .
(13.48)
( ) ( ) 1 1
T
NJTSSW T NJTSSW TNOM TNJTSSW
TNOM
 
= ⋅ + −

\ .
(13.49)
( ) ( ) 1 1
T
NJTS T NJTS TNOM TNTJS
TNOM
 
= ⋅ + −

\ .
(13.50)
( ) ( ) 1 1
T
NJTSSWGD T NJTSSWGD TNOM TNJTSSWGD
TNOM
 
= ⋅ + −

\ .
(13.51)
( ) ( ) 1 1
T
NJTSSWD T NJTSSWD TNOM TNJTSSWD
TNOM
 
= ⋅ + −

\ .
(13.52)
( ) ( ) 1 1
T
NJTSSWD T NJTSSWD TNOM TNJTSSWD
TNOM
 
= ⋅ + −

\ .
(13.53)
Temperature Dependence Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 107
( ) ( ) 1 1
T
NJTSD T NJTSD TNOM TNTJSD
TNOM
 
= ⋅ + −

\ .
(13.54)
The original TAT current densities J
tsswgs
and J
tsswgd
(i.e., Equ. 13.43 and 13.46) are width
independent, while in experiments narrower device shows higher TAT current per width.
Here, BSIM 4.6.2 introduced a new parameter JTWEFF to describe this phenomenon.
The backward compatibility is kept when JTWEFF is zero.
13.6 Temperature Dependence of Junction Diode CV
• Sourceside diode
The temperature dependences of zerobias unitlength/area junction
capacitances on the source side are modeled by
( ) ( ) ( ) CJS T CJS TNOM TCJ T TNOM = + ⋅ − (13.55)
( ) ( ) ( ) CJSWS T CJSWS TNOM TCJSW T TNOM = + ⋅ − (13.56)
and
( ) ( ) ( ) 1 CJSWGS T CJSWGS TNOM TCJSWG T TNOM = ⋅ + ⋅ −
(13.57)
The temperature dependences of the builtin potentials on the source side are
modeled by
( ) ( ) ( ) PBS T PBS TNOM TPB T TNOM = − ⋅ − (13.58)
( ) ( ) ( ) PBSWS T PBSWS TNOM TPBSW T TNOM = − ⋅ − (13.59)
and
( ) ( ) ( ) PBSWGS T PBSWGS TNOM TPBSWG T TNOM = − ⋅ − (13.60)
• Drainside diode
The temperature dependences of zerobias unitlength/area junction
capacitances on the drain side are modeled by
( ) ( ) ( ) 1 CJD T CJD TNOM TCJ T TNOM = ⋅ + ⋅ −
(13.61)
Temperature Dependence Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 108
( ) ( ) ( ) CJSWD T CJSWD TNOM TCJSW T TNOM = + ⋅ − (13.62)
and
( ) ( ) ( ) 1 CJSWGD T CJSWGD TNOM TCJSWG T TNOM = ⋅ + ⋅ −
(13.63)
The temperature dependences of the builtin potentials on the drain side are
modeled by
( ) ( ) ( ) PBD T PBD TNOM TPB T TNOM = − ⋅ − (13.64)
( ) ( ) ( ) PBSWD T PBSWD TNOM TPBSW T TNOM = − ⋅ − (13.65)
and
( ) ( ) ( ) PBSWGD T PBSWGD TNOM TPBSWG T TNOM = − ⋅ − (13.66)
13.7 Temperature Dependences of E
g
and n
i
mrtlMod=0
• Energyband gap of Si (E
g
)
The temperature dependence of E
g
is modeled by
( )
4 2
7.02 10
1.16
1108
g
TNOM
E TNOM
TNOM
−
×
= −
+
(13.67)
and
( )
4 2
7.02 10
1.16
1108
g
T
E T
T
−
×
= −
+
(13.68)
• Intrinsic carrier concentration of Si (n
i
)
The temperature dependence of n
i
is modeled by
( )
1.45 10 exp 21.5565981
300.15 300.15 2
g
i
B
qE TNOM
TNOM TNOM
n e
k T
= ⋅ ⋅ ⋅ −
⋅
(13.69)
mrtlMod=1
Temperature Dependence Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 109
• Energyband gap of nonsilicon channel (E
g
)
The temperature dependence of E
g
is modeled by
2
0 0
TBGASUB Tnom
Eg BG SUB
Tnom TBGBSUB
×
= −
+
(13.70)
2
300.15
(300.15) 0
300.15
TBGASUB
Eg BG SUB
TBGBSUB
×
= −
+
(13.71)
2
0
TBGASUB Temp
Eg BG SUB
Temp TBGBSUB
×
= −
+
(13.72)
• Intrinsic carrier concentration of nonsilicon channel (n
i
)
3/ 2
(300.15) 0
0 exp
300.15 2
i
t
Tnom Eg Eg
n NI SUB
v
  −  
= × ×
 
\ .
\ .
(13.73)
Stress Effect Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 110
Chapter 14: Stress Effect Model
CMOS feature size aggressively scaling makes shallow trench isolation(STI)
very popular active area isolatiohn process in advanced technologies. Recent
years, strain channel materials have been employed to achieve high device
performance. The mechanical stress effect induced by these process causes
MOSFET performance function of the active area size(OD: oxide definition)
and the location of the device in the active area. And the necessity of new
models to describe the layout dependence of MOS parameters due to stress
effect becomes very urgent in advance CMOS technologies.
Influence of stress on mobility has been well known since the 0.13um
technology. The stress influence on saturation velocity is also
experimentally demonstrated. Stressinduced enhancement or suppression of
dopant diffusion during the processing is reported. Since the doping profile
may be changed due to different STI sizes and stress, the threshold voltage
shift and changes of other secondorder effects, such as DIBL and body
effect, were shown in process integration.
BSIM4 considers the influence of stress on mobility, velocity saturation,
threshold voltage, body effect, and DIBL effect.
14.1 Stress Effect Model Development
Experimental analysis show that there exist at least two different
mechanisms within the influence of stress effect on device characteristics.
The first one is mobilityrelated and is induced by the band structure
modification. The second one is Vthrelated as a result of doping profile
Stress Effect Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 111
variation. Both of them follow the same 1/LOD trend but reveal different L
and W scaling. We have derived a phenomenological model based on these
findings by modifying some parameters in the BSIM model. Note that the
following equations have no impact on the iteration time because there are
no voltagecontrolled components in them.
14.1.1 Mobilityrelated Equations
This model introduces the first mechanism by adjusting the U0 and Vsat
according to different W, L and OD shapes. Define mobility relative change
due to stress effect as :
/ ( ) / 1
eff
eff
eff effo eff effo effo
effo
u
u
ρ u u u u u
u
= ∆ = − = −
(14.1)
So,
1
eff
eff
effo
u
u
ρ
u
= +
(14.2)
Figure14.1 shows the typical layout of a MOSFET on active layout
surrounded by STI isolation. SA, SB are the distances between isolation
edge to Poly from one and the other side, respectively. 2D simulation shows
that stress distribution can be expressed by a simple function of SA and SB.
Figure 14.1 shows the typical layout of a MOSFET
Stress Effect Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 112
Figure 14.2 Stress distribution within MOSFET channel
using 2D simulation
Assuming that mobility relative change is propotional to stress distribution.
It can be described as function of SA, SB(LOD effect), L, W, and T
dependence:
( )
KU0
_ _
_ 0
eff
Inv sa Inv sb
Kstress u
u
ρ = ⋅ +
(14.3)
where:
Stress Effect Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 113
0 0
0 0
1 1
_ _
0.5 0.5
0 0
_ 0 1
( ) ( )
0
+ 1 0
( ) ( )
drawn drawn
LLODKU WLODKU
drawn drawn
LLODKU WLODKU
drawn drawn
Inv sa Inv sb
SA L SB L
LKU WKU
Kstress u
L XL W XW WLOD
PKU Tempera
TKU
L XL W XW WLOD TNO
= =
+ ⋅ + ⋅

= + +
+ + +
\

× + ⋅

+ ⋅ + +
.
M
 
\ \
So that:
1 ( , )
1 ( , )
eff
eff effo
eff ref ref
SA SB
SA SB
u
u
ρ
u u
ρ
+
=
+
(14.5)
1 K ( , )
1 K ( , )
eff
sattemp sattempo
eff ref ref
VSAT SA SB
VSAT SA SB
u
u
ρ
υ υ
ρ
+ ⋅
=
+ ⋅
(14.6)
and SA
ref
, SB
ref
are reference distances between OD edge to poly from one
and the other side.
14.1.2 Vthrelated Equations
Vth0, K2 and ETA0 are modified to cover the doping profile change in the
devices with different LOD. They use the same 1/LOD formulas as shown in
section(14.1), but different equations for W and L scaling:
( )
( )
LODK2
LOD
KVTH0
0 0 _ _ _ _
0
STK2
2 2 _ _ _ _
0
STETA0
0 0
0
original ref ref
original ref ref
original
VTH VTH Inv sa Inv sb Inv sa Inv sb
Kstress_vth
K K Inv sa Inv sb Inv sa Inv sb
Kstress_vth
ETA ETA
Kstress_vth
= + ⋅ + − −
= + ⋅ + − −
= +
( )
ETA0
_ _ _ _
ref ref
Inv sa Inv sb Inv sa Inv sb ⋅ + − −
(14.7)
Where:
Stress Effect Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 114
(14.8)
LLODKVTH WLODKVTH
LLODKVTH WLODKVTH
LKVTH0 WKVTH0
_ 0 1
( ) ( )
PKVTH0
( ) ( )
drawn drawn
drawn drawn
Kstress vth
L XL W XW WLOD
L XL W XW WLOD
= + +
+ + +
+
+ ⋅ + +
(14.9)
14.1.3 Multiple Finger Device
For multiple finger device, the total LOD effect is the average of LOD effect
to every finger. That is(see Figure14.3) for the layout for multiple finger
device):
1
0
1
0
1 1
_
S 0.5 ( )
1 1
_
S 0.5 ( )
NF
i
drawn drawn
NF
i
drawn drawn
Inv sa
NF A L i SD L
Inv sb
NF B L i SD L
−
=
−
=
=
+ ⋅ + ⋅ +
=
+ ⋅ + ⋅ +
∑
∑
Figure 14.3 Layout of multiple finger MOSFET
14.2 Effective SA and SB for Irregular LOD
General MOSFET has an irregular shape of active area shown in Figure 14.3
To fully describe the shape of OD region will require additional instance
Stress Effect Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 115
parameters. However, this will result in too many parameters in the net lists
and would massively increase the readin time and degrade the readability of
parameters. One way to overcome this difficulty is the concept of effective
SA and SB similar to ref. [16].
Stress effect model described in Section(14.1) allows an accurate and
efficient layout extraction of effective SA and SB while keeping fully
compatibility of the LOD model. They are expressed as:
i
1
eff i
i
1
eff i
sw 1 1
S 0.5 sa 0.5
sw 1 1
S 0.5 sb 0.5
n
i
drawn drawn drawn
n
i
drawn drawn drawn
A L W L
B L W L
=
=
= ⋅
+ ⋅ + ⋅
= ⋅
+ ⋅ + ⋅
∑
∑
(14.10)
Figure 14.4 A typical layout of MOS devices with more instance
parameters (swi, sai and sbi) in addition to the traditional L and W
Well Proximity Effect Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 116
Chapter 15: Well Proximity Effect Model
Retrograde well profiles have several key advantages for highly scaled bulk
complementary metal oxide semiconductor(CMOS) technology. With the
advent of highenergy implanters and reduced thermal cycle processing, it
has become possible to provide a relatively heavily doped deep nwell and
pwell without affecting the critical devicerelated doping at the surface. The
deep well implants provide a low resistance path and suppress parasitic
bipolar gain for latchup protection, and can also improve soft error rate and
noise isolation. A deep buried layer is also key to forming triplewell
structures for isolatedwell NMOSFETs. However, deep buried layers can
affect devices located near the mask edge. Some of the ions scattered out of
the edge of the photoresist are implanted in the silicon surface near the mask
edge, altering the threshold voltage of those devices[17]. It is observed a
threshold voltage shifts of up to 100 mV in a deep boron retrograde pwell, a
deep phosphorus retrograde nwell, and also a triplewell implementation
with a deep phosphorus isolation layer below the pwell over a lateral
distance on the order of a micrometer[17]. This effect is called well
proximity effect.
BSIM4 considers the influence of well proximity effect on threshold voltage,
mobility, and body effect. This well proximity effect model is developed by
the Compact Model Council[19].
Well Proximity Effect Model
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 117
15.1 Well Proximity Effect Model
Experimental analysis[17] shows that well proximity effect is strong
function of distance of FET from mask edge, and electrical quantities
influenced by it follow the same geometrical trend. A phenomenological
model based on these findings has been developed by modifying some
parameters in the BSIM model. Note that the following equations have no
impact on the iteration time because there are no voltagecontrolled
components in them.
Well proximity affects threshold voltage, mobility and the body effect of the
device. The effect of the well proximity can be described through the
following equations :
( )
( )
( ) ( )
,
0 0 KVTH0WE SCA WEB SCB WEC SCC
2 2 K2WE SCA WEB SCB WEC SCC
1 KU0WE SCA WEB SCB WEC SCC
org
org
eff eff org
Vth Vth
K K
u u
= + ⋅ + ⋅ + ⋅
= + ⋅ + ⋅ + ⋅
= ⋅ + ⋅ + ⋅ + ⋅
(15.1)
where SCA, SCB, SCC are instance parameters that represent the integral of
the first/second/third distribution function for scattered well dopant.
The guidelines for calculating the instance parameters SCA, SCB, SCC have
been developed by the Compact Model Council which can be found at the
CMC website [19].
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 118
Chapter 16: Parameter Extraction
Methodology
Parameter extraction is an important part of model development. The
extraction methodology depends on the model and on the way the model is
used. A combination of a local optimization and the group device extraction
strategy is adopted for parameter extraction.
16.1 Optimization strategy
There are two main, different optimization strategies: global optimization
and local optimization. Global optimization relies on the explicit use of a
computer to find one set of model parameters which will best fit the
available experimental (measured) data. This methodology may give the
minimum average error between measured and simulated (calculated) data
points, but it also treats each parameter as a "fitting" parameter. Physical
parameters extracted in such a manner might yield values that are not
consistent with their physical intent.
In local optimization, many parameters are extracted independently of one
another. Parameters are extracted from device bias conditions which
correspond to dominant physical mechanisms. Parameters which are
extracted in this manner might not fit experimental data in all the bias
conditions. Nonetheless, these extraction methodologies are developed
specifically with respect to a given parameter’s physical meaning. If
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 119
properly executed, it should, overall, predict device performance quite well.
Values extracted in this manner will now have some physical relevance.
16.2 Extraction Strategy
Two different strategies are available for extracting parameters: single
device extraction strategy and group device extraction strategy. In single
device extraction strategy, experimental data from a single device is used to
extract a complete set of model parameters. This strategy will fit one device
very well but will not fit other devices with different geometries.
Furthermore, single device extraction strategy cannot guarantee that the
extracted parameters are physical. If only one set of channel length and
width is used, parameters related to channel length and channel width
dependencies can not be determined.
It is suggested that BSIM4 use group device extraction strategy. This
requires measured data from devices with different geometries. All devices
are measured under the same bias conditions. The resulting fit might not be
absolutely perfect for any single device but will be better for the group of
devices under consideration. In the following, a general extraction
methodology is proposed for basic BSIM4 model parameters. Thus, it will
not cover other model parameters, such as those of the gate tunneling current
model and RF models, etc.
16.3 Extraction Procedure
16.3.1 Extraction Requirements
One large size device and two sets of smallersized devices are needed to
extract parameters, as shown in Figure 16.1.
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 120
Figure 16.1 Device geometries used for parameter extraction
The largesized device (W ≥ 10um, L ≥ 10um) is used to extract parameters
which are independent of short/narrow channel effects and parasitic
resistance. Specifically, these are: mobility, the largesized device threshold
voltage VTH0, and the body effect coefficients K1 and K2 which depend on
the vertical doping concentration distribution. The set of devices with a fixed
large channel width but different channel lengths are used to extract
parameters which are related to the short channel effects. Similarly, the set
of devices with a fixed, long channel length but different channel widths are
used to extract parameters which are related to narrow width effects.
Regardless of device geometry, each device will have to be measured under
four, distinct bias conditions.
(1) I
ds
vs. V
gs
@ V
ds
= 0.05V with different V
bs
.
(2) I
ds
vs. V
ds
@ V
bs
= 0V with different V
gs
.
(3) I
ds
vs. V
gs
@ V
ds
= V
dd
with different V
bs
.
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 121
(4) I
ds
vs. V
ds
@ V
bs
= V
bb
with different V
gs
. (V
bb
 is the maximum body bias).
16.3.2 Optimization
The optimization process recommended is a combination of Newton
Raphson's iteration and linearsquares fit of either one, two, or three
variables. A flow chart of this optimization process is shown in Figure 16.2.
The model equation is first arranged in a form suitable for Newton
Raphson's iteration as shown in (16.1):
( ) ( ) ( )
exp 10 20 30 1 2 3 1 2 3
1 2 3
( , , ) ( , , )
m m m m m m sim sim sim
sim
f f f
f P P P f P P P P P P
P P P
∂ ∂ ∂
− = ∆ + ∆ + ∆
∂ ∂ ∂
(16.1)
The variable f
sim
() is the objective function to be optimized. The variable f
exp
()
stands for the experimental data. P
10
, P
20
, and P
30
represent the desired
extracted parameter values. P
1
(m)
, P
2
(m)
and P
3
(m)
represent parameter values
after the mth iteration.
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 122
Figure 16.2 Optimization flow
To change (16.1) into a form that a linear leastsquares fit routine can be
used (i.e. in a form of y = a + bx1 + cx2), both sides of (16.1) are divided by
∂f
sim
/ ∂P
1
. This gives the change in P
1
, ∆P
1
(m)
, for the next iteration such
that:
( 1) ( ) m m m
i i i
P P P
+
= + ∆ (16.2)
where i=1, 2, 3 for this example. The (m+1) parameter values for P
2
and P
3
are obtained in an identical fashion. This process is repeated until the
incremental parameter change in parameter values ∆P
i
(m) are smaller than a
predetermined value. At this point, the parameters P
1
, P
2
, and P
3
have been
extracted.
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 123
16.3.3 Extraction Routine
Before any model parameters can be extracted, some process parameters
have to be provided. They are listed below in Table 16.1.
Input Parameters Names Physical Meaning
TOXE, TOXP, DTOX, or
EPSROX
Gate oxide thickness and dielectric
constant
NDEP Doping concentration in the channel
TNOM Temperature at which the data is taken
L
drawn
Mask level channel length
W
drawn
Mask level channel width
XJ Junction depth
Table 16.1 Prerequisite input parameters prior to extraction process
The parameters are extracted in the following procedure. These procedures
are based on a physical understanding of the model and based on local
optimization. (Note: Fitting Target Data refers to measurement data used for
model extraction.)
Step 1
Extracted Parameters & Fitting Target Data
Device & Experimental Data
VTH0, K1, K2
Fitting Target Exp. Data: V
th
(V
bs
)
Large Size Device (Large W & L).
I
ds
vs. V
gs
@ V
ds
= 0.05V at Different V
bs
Extracted Experimental Data
V
th
(V
bs
)
Step 2
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
UA, UB, UC, EU Large Size Device (Large W & L).
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 124
Fitting Target Exp. Data: Strong Inversion
region I
ds
(V
gs
, V
bs
)
I
ds
vs. V
gs
@ V
ds
= 0.05V at Different V
bs
Step 3
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
LINT, R
ds
(RDSW, W, V
bs
)
Fitting Target Exp. Data: Strong Inversion
region I
ds
(V
gs
, V
bs
)
One Set of Devices (Large and Fixed W &
Different L).
I
ds
vs. V
gs
@ V
ds
= 0.05V at Different V
bs
Step 4
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
WINT, R
ds
(RDSW, W, V
bs
)
Fitting Target Exp. Data: Strong Inversion
region I
ds
(V
gs
, V
bs
)
One Set of Devices (Large and Fixed L &
Different W).
I
ds
vs. V
gs
@ V
ds
= 0.05V at Different V
bs
Step 5
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
RDSW, PRWG, PRWB, WR
Fitting Target Exp. Data: R
ds
(RDSW, W,
V
gs
, V
bs
)
R
ds
(RDSW, W, V
gs
, V
bs
)
Step 6
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
DVT0, DVT1, DVT2, LPE0, LPEB One Set of Devices (Large and Fixed W &
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 125
Fitting Target Exp. Data: V
th
(V
bs
,
L, W)
Different L).
V
th
(V
bs
,
L, W)
Step 7
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
DVT0W, DVT1W, DVT2W
Fitting Target Exp. Data: V
th
(V
bs
,
L, W)
One Set of Devices (Large and Fixed W &
Different L).
V
th
(V
bs
,
L, W)
Step 8
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
K3, K3B, W0
Fitting Target Exp. Data: V
th
(V
bs
,
L, W)
One Set of Devices (Large and Fixed W &
Different L).
V
th
(V
bs
,
L, W)
Step 9
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
MINV, VOFF, VOFFL, NFACTOR,
CDSC, CDSCB
Fitting Target Exp. Data: Subthreshold
region I
ds
(V
gs
, V
bs
)
One Set of Devices (Large and Fixed W &
Different L).
I
ds
vs. V
gs
@ V
ds
= 0.05V at Different V
bs
Step 10
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
CDSCD
Fitting Target Exp. Data: Subthreshold
region I
ds
(V
gs
, V
bs
)
One Set of Devices (Large and Fixed W &
Different L).
I
ds
vs. V
gs
@ V
bs
= V
bb
at Different V
ds
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 126
Step 11
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
DWB
Fitting Target Exp. Data: Strong Inversion
region I
ds
(V
gs
, V
bs
)
One Set of Devices (Large and Fixed W &
Different L).
I
ds
vs. V
gs
@ V
ds
= 0.05V at Different V
bs
Step 12
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
VSAT, A0, AGS, LAMBDA, XN, VTL,
LC
Fitting Target Exp. Data: I
sat
(V
gs
, V
bs
)/W
A1, A2 (PMOS Only)
Fitting Target Exp. Data V
dsat
(V
gs
)
One Set of Devices (Large and Fixed W &
Different L).
I
ds
vs. V
ds
@ V
bs
= 0V at Different V
gs
Step 13
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
B0, B1
Fitting Target Exp. Data: I
sat
(V
gs
, V
bs
)/W
One Set of Devices (Large and Fixed L &
Different W).
I
ds
vs. V
ds
@ V
bs
= 0V at Different V
gs
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 127
Step 14
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
DWG
Fitting Target Exp. Data: I
sat
(V
gs
, V
bs
)/W
One Set of Devices (Large and Fixed L &
Different W).
I
ds
vs. V
ds
@ V
bs
= 0V at Different V
gs
Step 15
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
PSCBE1, PSCBE2
Fitting Target Exp. Data: R
out
(V
gs
, V
ds
)
One Set of Devices (Large and Fixed W &
Different L).
I
ds
vs. V
ds
@ V
bs
= 0V at Different V
gs
Step 16
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
PCLM, θ(DROUT, PDIBLC1, PDIBLC2,
L), PVAG, FPROUT, DITS, DITSL,
DITSD
Fitting Target Exp. Data: R
out
(V
gs
, V
ds
)
One Set of Devices (Large and Fixed W &
Different L).
I
ds
vs. V
ds
@ V
bs
= 0V at Different V
gs
Step 17
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 128
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
DROUT, PDIBLC1, PDIBLC2
Fitting Target Exp. Data: θ(DROUT,
PDIBLC1, PDIBLC2, L)
One Set of Devices (Large and Fixed W &
Different L).
θ(DROUT, PDIBLC1, PDIBLC2, L)
Step 18
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
PDIBLCB
Fitting Target Exp. Data: θ(DROUT,
PDIBLC1, PDIBLC2, L, V
bs
)
One Set of Devices (Large and Fixed W &
Different L).
I
ds
vs. V
gs
@ fixed V
gs
at Different V
bs
Step 19
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
θ
DIBL
(ETA0, ETAB, DSUB, DVTP0,
DVTP1, L)
Fitting Target Exp. Data: Subthreshold
region I
ds
(V
gs
, V
bs
)
One Set of Devices (Large and Fixed W &
Different L).
I
ds
vs. V
gs
@ V
ds
= V
dd
at Different V
bs
Step 20
Extracted Parameters & Fitting Target Data Devices & Experimental Data
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 129
ETA0, ETAB, DSUB
Fitting Target Exp. Data: θ
DIBL
(ETA0,
ETAB, L)
One Set of Devices (Large and Fixed W &
Different L).
I
ds
vs. V
gs
@ V
ds
= V
dd
at Different V
bs
Step 21
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
KETA
Fitting Target Exp. Data: I
sat
(V
gs
, V
bs
)/W
One Set of Devices (Large and Fixed W &
Different L).
I
ds
vs. V
ds
@ V
bs
= V
bb
at Different V
gs
Step 22
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
ALPHA0, ALPHA1, BETA0
Fitting Target Exp. Data: I
ii
(V
gs
, V
bs
)/W
One Set of Devices (Large and Fixed W &
Different L).
I
ds
vs. V
ds
@ V
bs
= V
bb
at Different V
ds
Step 23
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
Parameter Extraction Methodology
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 130
ku0, kvsat, tku0, lku0, wku0, pku0,
llodku0, wlodku0
Fitting Target Exp. Data: Mobility (SA, SB,
L, W)
Set of Devices ( Different L, W, SA, SB).
I
dslinear
@ V
gs
= V
dd,
V
ds
= 0.05
Step 24
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
kvth0, lkvth0, wkvth0, pvth0, llodvth,
wlodvth
Fitting Target Exp. Data: V
th
(SA, SB, L, W)
Set of Devices ( Different L, W, SA, SB).
V
th
(SA, SB, L, W)
Step 25
Extracted Parameters & Fitting Target Data
Devices & Experimental Data
stk2, lodk2, steta0, lodeta0
Fitting Target Exp. Data: k2(SA, SB, L, W),
eta0(SA, SB, L, W)
Set of Devices ( Different L, W, SA, SB).
k2(SA, SB, L, W), eta0(SA, SB, L, W)
BSIM4.6.1 Model Selectors/Controller
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 131
Appendix A: Complete Parameter List
A.1 BSIM4.6.1 Model Selectors/Controller
Parameter name
Description
Default
value
Binnable? Note
LEVEL (SPICE3
parameter)
SPICE3 model selector 14 NA BSIM4 also
set as the
default
model in
SPICE3
VERSION Model version number 4.6.4 NA Berkeley
Latest
official
release
BINUNIT Binning unit selector 1 NA 
PARAMCHK Switch for parameter
value check
1 NA Parameters
checked
MOBMOD
Mobility model
selector
0 NA 
MTRLMOD
New material model
selector
0 NA
If 0,original
model is
used If 1,
new format
used
RDSMOD Biasdependent
source/drain resistance
model selector 0 NA
R
ds
(V)
modeled
internally
through IV
equation
IGCMOD Gatetochannel
tunneling current
model selector
0 NA OFF
IGBMOD Gatetosubstrate
tunneling current
model selector
0 NA OFF
CVCHARGEMOD Threshold voltage for
CVmodel selector
0 NA 
CAPMOD
Capacitance model
selector
2 NA 
BSIM4.6.1 Model Selectors/Controller
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 132
RGATEMOD
(Also an instance
parameter)
Gate resistance model
selector
0 (no gate
resistance)

RBODYMOD
(Also an instance
parameter)
Substrate resistance
network model selector
0 ( network
off)
NA 
TRNQSMOD
(Also an instance
parameter)
Transient NQS model
selector
0 NA OFF
ACNQSMOD
(Also an instance
parameter)
AC smallsignal NQS
model selector
0 NA OFF
FNOIMOD
Flicker noise model
selector
1 NA 
TNOIMOD Thermal noise model
selector
0 NA

DIOMOD Source/drain junction
diode IV model
selector
1 NA 
TEMPMOD Temperature mode
selector
0 No If 0,original
model is
used If 1,
new format
used
PERMOD Whether PS/PD (when
given) includes the
gateedge perimeter
1 (including
the gate
edge
perimeter)
NA 
GEOMOD (Also
an instance
parameter)
Geometrydependent
parasitics model
selector  specifying
how the end S/D
diffusions are
connected
0 (isolated) NA 
RGEOMOD
(Instance
parameter only)
Source/drain diffusion
resistance and contact
model selector 
specifying the end S/D
contact type: point,
wide or merged, and
how S/D parasitics
resistance is computed
0 (no S/D
diffusion
resistance)
NA 
BSIM4.6.1 Model Selectors/Controller
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 133
WPEMOD Flag for WPE model
(WPEMOD=1 to
activate this model
0 NA 
Process Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 134
A.2 Process Parameters
Parameter
name Description
Default
value Binnable?
Note
EPSROX Gate dielectric constant
relative to vacuum
3.9 (SiO
2
) No Typically
greater than
or equal to
3.9
TOXE Electrical gate equivalent
oxide thickness
3.0e9m No
Fatal error if
not positive
EOT Equivalent SiO
2
thickness 1.5e9m No
Fatal error if
not positive
TOXP Physical gate equivalent
oxide thickness
TOXE No
Fatal error if
not positive
TOXM Tox at which parameters are
extracted
TOXE No
Fatal error if
not positive
DTOX Defined as (TOXETOXP) 0.0m No 
XJ S/D junction depth 1.5e7m Yes 
GAMMA1
(γ1 in
equation)
Bodyeffect coefficient near
the surface
calculated
V
1/2
Note1
GAMMA2
(γ2 in
equation)
Bodyeffect coefficient in
the bulk
calculated
V
1/2
Note1
NDEP Channel doping
concentration at depletion
edge for zero body bias
1.7e17cm
3
Yes Note2
NSUB
Substrate doping
concentration
6.0e16cm
3
Yes 
NGATE
Poly Si gate doping
concentration
0.0cm
3
Yes 
NSD Source/drain doping
concentration Fatal error if
not positive
1.0e20cm
3
Yes 
Process Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 135
VBX
V
bs
at which the depletion
region width equalsXT
calculated
(V)
No Note3
XT Doping depth 1.55e7m Yes 
RSH Source/drain sheet
resistance
0.0ohm/
square
No Should not
be negative
RSHG Gate electrode sheet
resistance
0.1ohm/
square
No
Should not
be negative
Basic Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 136
A.3 Basic Model Parameters
Parameter
name
Description
Default value
Binnable? Note
VTH0 or
VTHO
Longchannel threshold
voltage at V
bs
=0
0.7V (NMOS)
0.7V(PMOS)
Yes Note4
DELVTO
(Instance
parameter
only)
Zero bias threshold voltage
variation
0.0V No
VFB Flatband voltage 1.0V Yes Note4
VDDEOT
Gate voltage at which EOT
is measured
1.5V (NMOS)
1.5V(PMOS)
No 
LEFFEOT
Effective gate length at
which EOT is measured
1u No
WEFFEOT
Effective width at which
EOT is measured
10u No
TEMPEOT
Temperature at which EOT
is measured
27
o
C
No
PHIN Nonuniform vertical
doping effect on surface
potential
0.0V Yes 
EASUB
Electron affinity of
substrate
4.05eV No 
EPSRSUB
Dielectric constant of
substrate relative to vacuum
11.7 No 
EPSRSUB
Dielectric constant of gate
relative to vacuum
11.7 No 
NI0SUB Intrinsic carrier
concentration at
T=300.15K
1.45e16m
3
No 
BG0SUB
Bandgap of substrate at
T=0K
1.16eV No 
TBGASUB
First parameter of bandgap
change due to temperature
7.02e4eV/K No 
TBGBSUB Second parameter of band
gap change due to
temperature
1108.0K No 
ADOS
Density of states parameter
to control charge centroid
1 No 
Basic Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 137
BDOS
Density of states parameter
to control charge centroid
1 No 
K1
Firstorder body bias
coefficient
0.5V
1/2
Yes Note5
K2
Secondorder body bias
coefficient
0.0 Yes Note5
K3 Narrow width coefficient 80.0 Yes 
K3B
Body effect coefficient of
K3
0.0 V
1
Yes 
W0 Narrow width parameter 2.5e6m Yes 
LPE0 Lateral nonuniform doping
parameter at V
bs
=0
1.74e7m Yes 
LPEB
Lateral nonuniform doping
effect on K1
0.0m Yes 
VBM
Maximum applied body
bias in VTH0 calculation
3.0V Yes 
DVT0 First coefficient of short
channel effect on V
th
2.2 Yes 
DVT1
Second coefficient of short
channel effect on V
th
0.53 Yes 
DVT2
Bodybias coefficient of
shortchannel effect on V
th
0.032V
1
Yes 
DVTP0 First coefficient of drain
induced V
th
shift due to for
longchannel pocket
devices
0.0m Yes Not
modeled if
binned
DVTP0
<=0.0
DVTP1 First coefficient of drain
induced V
th
shift due to for
longchannel pocket devices
0.0V
1
Yes 
DVT0W First coefficient of narrow
width effect on V
th
for small
channel length
0.0 Yes 
DVT1W Second coefficient of
narrow width effect on V
th
for small channel length
5.3e6m
1
Yes 
DVT2W Bodybias coefficient of
narrow width effect for
small channel length
0.032V
1
Yes 
U0 Lowfield mobility 0.067 m
2
/(Vs)
(NMOS);
0.025 m
2
/(Vs)
PMOS
Yes 
Basic Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 138
UA Coefficient of firstorder
mobility degradation due to
vertical field
1.0e9m/V for
MOBMOD =0
and 1; 1.0e
15m/V for
MOBMOD =2
Yes 
UB Coefficient of seconorder
mobility degradation due to
vertical field
1.0e19m
2
/ V
2
Yes 
UC Coefficient of mobility
degradation due to body
bias effect
0.0465V
1
for
MOBMOD=1;
0.0465e9
m/V
2
for
MOBMOD =0
and 2
Yes 
UD
Mobility Coulumb
scattering coefficient
0.0m
2
Yes 
UCS Coulombic scattering
exponent
1.67 (NMOS)
1.0 (PMOS)
Yes 
UP
Mobility channel length
coefficient
0(1/m
2
) Yes 
LP
Mobility channel length
exponential coefficient
1e8(m) Yes 
EU Exponent for mobility
degradation of
MOBMOD=2
1.67 NMOS);
1.0 (PMOS)

VSAT Saturation velocity 8.0e4m/s Yes 
A0 Coefficient of channel
length dependence of bulk
charge effect
1.0 Yes 
AGS Coefficient of Vgs
dependence of bulk charge
effect
0.0V
1
Yes 
B0 Bulk charge effect
coefficient for channel
width
0.0m Yes 
B1
Bulk charge effect width
offset
0.0m Yes 
KETA
Bodybias coefficient of
bulk charge effect
0.047V
1
Yes 
A1
First nonsaturation effect
parameter
0.0V
1
Yes 
A2
Second nonsaturation
factor
1.0 Yes 
Basic Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 139
WINT
Channelwidth offset
parameter
0.0m
No

LINT
Channellength offset
parameter
0.0m No 
DWG
Coefficient of gate bias
dependence of W
eff
0.0m/V Yes 
DWB Coefficient of body bias
dependence of W
eff
bias
dependence
0.0m/V
1/2
Yes 
VOFF Offset voltage in
subthreshold region for
large W and L
0.08V Yes

VOFFL
Channellength dependence
of VOFF
0.0mV No

MINV V
gsteff
fitting parameter for
moderate inversion
condition
0.0 Yes 
NFACTOR Subthreshold swing factor 1.0 Yes 
ETA0
DIBL coefficient in
subthreshold region
0.08 Yes 
ETAB Bodybias coefficient for
the subthreshold DIBL
effect
0.07V
1
Yes 
DSUB
DIBL coefficient exponent
in subthreshold region
DROUT Yes 
CIT Interface trap capacitance
0.0F/m
2
Yes 
CDSC coupling capacitance
between source/ drain and
channel
2.4e4F/m
2
Yes 
CDSCB
Bodybias sensitivity of
Cdsc
0.0F/(Vm
2
) Yes 
CDSCD
Drainbias sensitivity of
CDSC
0.0(F/Vm
2
) Yes 
PCLM
Channel length modulation
parameter
1.3 Yes 
PDIBLC1
Parameter for DIBL effect
on Rout
0.39 Yes 
PDIBLC2
Parameter for DIBL effect
on Rout
0.0086 Yes 
PDIBLCB
Body bias coefficient of
DIBL effect on Rout
0.0V
1
Yes

Basic Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 140
DROUT
Channellength dependence
of DIBL effect on Rout
0.56 Yes 
PSCBE1 First substrate current
induced bodyeffect
parameter
4.24e8V/m Yes 
PSCBE2 Second substrate current
induced bodyeffect
parameter
1.0e5m/V Yes 
PVAG
Gatebias dependence of
Early voltage
0.0 Yes 
DELTA (δ in
equation)
Parameter for DC V
dseff
0.01V Yes 
FPROUT Effect of pocket implant on
Rout degradation
0.0V/m
0.5
Yes Not
modeled if
binned
FPROUT
not
positive
PDITS Impact of draininduced Vth
shift on Rout
0.0V
1
Yes Not
modeled if
binned
PDITS=0;
Fatal error
if binned
PDITS
negative
PDITSL Channellength dependence
of draininduced V
th
shift for
Rout
0.0m
1
No Fatal error
if PDITSL
negative
PDITSD
V
ds
dependence of drain
induced V
th
shift for Rout
0.0V
1
Yes 
LAMBDA Velocity overshoot
coefficient
0.0 Yes If not
given or
(<=0.0),
velocity
overshoot
will be
turned off
Basic Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 141
VTL Thermal velocity 2.05e5[m/s] Yes If not
given or
(<=0.0),
source end
thermal
velocity
will be
turned off
LC Velocity back scattering
coefficient
0.0[m] No 5e9[m] at
room
temperatur
e
XN
Velocity back scattering
coefficient
3.0 Yes 
Parameters for Asymmetric and BiasDependent RModel
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 142
A.4 Parameters for Asymmetric and BiasDependent R
ds
Model
Parameter
name
Description
Default value
Binnable? Note
RDSW Zero bias LDD resistance
per unit width for
RDSMOD=0
200.0
ohm(µm)WR
Yes If negative,
reset to 0.0
RDSWMIN LDD resistance per unit
width at high V
gs
and
zero V
bs
for RDSMOD=0
0.0
ohm(µm)WR
No 
RDW Zero bias lightlydoped
drain resistance Rd(V)
per unit width for
RDSMOD=1
100.0
ohm(µm)WR
Yes 
RDWMIN Lightlydoped drain
resistance per unit width
at high V
gs
and zero V
bs
for RDSMOD=1
0.0
ohm(µm)WR
No 
RSW Zero bias lightlydoped
source resistance Rs(V)
per unit width for
RDSMOD=1
100.0
ohm(µm)WR
Yes 
RSWMIN Lightlydoped source
resistance per unit width
at high V
gs
and zero V
bs
for RDSMOD=1
0.0
ohm(µm)WR
No 
PRWG
Gatebias dependence of
LDD resistance
1.0V
1
Yes 
PRWB
Bodybias dependence of
LDD resistance
0.0V
0.5
Yes 
WR Channelwidth
dependence parameter of
LDD resistance
1.0 Yes 
NRS
(instance
parameter
only)
Number of source
diffusion squares
1.0 No 
NRD
(instance
parameter
only)
Number of drain
diffusion squares
1.0 No 
Impact Ionization Current Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 143
A.5 Impact Ionization Current Model Parameters
Parameter
name Description
Default
value Binnable? Note
ALPHA0
First parameter of impact
ionization current
0.0m/V Yes 
ALPHA1 Channel length scaling
parameter of impact ionization
current
0.0/V Yes 
BETA0
First V
ds
dependent parameter
of impact ionization current
0.0/V Yes 
GateInduced Drain Leakage Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 144
A.6 GateInduced Drain Leakage Model Parameters
Parameter
name Description
Default
value Binnable? Note
AGIDL Preexponential coefficient
for GIDL
0.0mho Yes I
gidl
=0.0 if
binned
AGIDL
=0.0
BGIDL Exponential coefficient for
GIDL
2.3e9V/m Yes I
gidl
=0.0 if
binned
BGIDL
=0.0
CGIDL
Paramter for bodybias effect
on GIDL
0.5V
3
Yes 
EGIDL
Fitting parameter for band
bending for GIDL
0.8V Yes 
AGISL Preexponential coefficient
for GISL
AGIDL Yes I
gisl
=0.0 if
binned
AGISL
=0.0
BGISL Exponential coefficient for
GISL
BGIDL Yes I
gisl
=0.0 if
binned
BGISL
=0.0
CGISL
Parameter for bodybias
effect on GISL CGIDL
Yes 
EGISL
Fitting parameter for band
bending for GISL
EGIDL Yes 
Gate Dielectric Tunneling Current Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 145
A.7 Gate Dielectric Tunneling Current Model
Parameters
Parameter
name Description
Default value
Binnable? Note
AIGBACC Parameter for I
gb
in
accumulation
9.49e4 (Fs
2
/g)
0.5
m
1
Yes 
BIGBACC Parameter for I
gb
in
accumulation
1.71e3 (Fs
2
/g)
0.5
m
1
V
1
Yes 
CIGBACC
Parameter for I
gb
in
accumulation
0.075V
1
Yes 
NIGBACC Parameter for I
gb
in
accumulation
1.0 Yes Fatal error
if binned
value not
positive
AIGBINV Parameter for I
gb
in
inversion
1.11e2 (Fs
2
/g)
0.5
m
1
Yes 
BIGBINV Parameter for I
gb
in
inversion
9.49e4 (Fs
2
/g)
0.5
m
1
V
1
Yes 
CIGBINV
Parameter for I
gb
in
inversion
0.006V
1
Yes 
EIGBINV
Parameter for I
gb
in
inversion
1.1V Yes 
NIGBINV Parameter for I
gb
in
inversion
3.0 Yes Fatal error
if binned
value not
positive
AIGC Parameter for I
gcs
and I
gcd
1.36e2 (NMOS)
and 9.8e3
(PMOS)
(Fs
2
/g)
0.5
m
1
Yes 
BIGC Parameter for I
gcs
and I
gcd
1.71e3 (NMOS)
and 7.59e4
(PMOS)
(Fs
2
/g)
0.5
m
1
V
1
Yes 
Gate Dielectric Tunneling Current Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 146
CIGC Parameter for I
gcs
and I
gcd
0.075 (NMOS)
and 0.03
(PMOS) V
1
Yes 
AIGS Parameter for I
gs
1.36e2 (NMOS)
and 9.8e3
(PMOS)
(Fs
2
/g)
0.5
m
1
Yes 
BIGS Parameter for I
gs
1.71e3 (NMOS)
and 7.59e4
(PMOS)
(Fs
2
/g)
0.5
m
1
V
1
Yes 
CIGS Parameter for I
gs
0.075 (NMOS)
and 0.03
(PMOS) V
1
Yes 
DLCIG
Source/drain overlap
length for I
gs
LINT Yes 
AIGD Parameter for I
gd
1.36e2 (NMOS)
and 9.8e3
(PMOS)
(Fs2/g)
0.5
m
1
Yes 
BIGD Parameter for I
gd
1.71e3 (NMOS)
and 7.59e4
(PMOS)
(Fs2/g)
0.5
m
1
V
1
Yes 
CIGD Parameter for I
gd
0.075 (NMOS)
and 0.03
(PMOS) V
1
Yes 
DLCIGD
Source/drain overlap
length for I
gd
LINT Yes 
NIGC Parameter for I
gcs
, I
gcd
,I
gs
and I
gd
1.0 Yes Fatal error
if binned
value not
positive
POXEDGE Factor for the gate oxide
thickness in source/drain
overlap regions
1.0 Yes Fatal error
if binned
value not
positive
Gate Dielectric Tunneling Current Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 147
PIGCD V
ds
dependence of I
gcs
and
I
gcd
1.0 Yes Fatal error
if binned
value not
positive
NTOX
Exponent for the gate
oxide ratio
1.0 Yes 
TOXREF Nominal gate oxide
thickness for gate
dielectric tunneling
current model only
3.0e9m No
Fatal error
if not
positive
VFBSDOFF
Flatband Voltage Offset
Parameter
0.0V Yes 
Charge and Capacitance Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 148
A.8 Charge and Capacitance Model Parameters
Parameter
name
Description
Default
value
Binnable? Note
XPART Charge partition parameter 0.0 No 
CGSO Non LDD region sourcegate
overlap capacitance per unit
channel width
calculated
(F/m)
No Note6
CGDO Non LDD region draingate
overlap capacitance per unit
channel width
calculated
(F/m)
No Note6
CGBO
Gatebulk overlap capacitance
per unit channel length
0.0 F/m Note6
CGSL Overlap capacitance between
gate and lightlydoped source
region
0.0F/m Yes 
CGDL Overlap capacitance between
gate and lightlydoped source
region
0.0F/m Yes 
CKAPPAS Coefficient of biasdependent
overlap capacitance for the
source side
0.6V Yes 
CKAPPAD Coefficient of biasdependent
overlap capacitance for the
drain side
CKAPPAS Yes 
CF Fringing field capacitance
calculated
(F/m)
Yes Note7
CLC
Constant term for the short
channel model
1.0e7m Yes 
CLE
Exponential term for the short
channel model
0.6 Yes 
DLC
Channellength offset
parameter for CV model
LINT (m) No 
DWC
Channelwidth offset parameter
for CV model
WINT (m) No 
VFBCV
Flatband voltage parameter
(for CAPMOD=0 only)
1.0V Yes 
NOFF
CV parameter in V
gsteff,CV
for
weak to strong inversion
1.0 Yes 
VOFFCV
CV parameter in V
gsteff,CV
for
week to strong inversion
0.0V Yes 
Charge and Capacitance Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 149
VOFFCVL
Channellength dependence of
VOFFCVL
0.0 Yes 
MINVCV
V
gsteff,CV
fitting parameter for
moderate inversion condition
0.0 Yes 
ACDE Exponential coefficient for
charge thickness in
CAPMOD=2 for accumulation
and depletion regions
1.0m/V Yes 
MOIN
Coefficient for the gatebias
dependent surface potential
15.0 Yes 
HighSpeed/RF Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 150
A.9 HighSpeed/RF Model Parameters
Parameter
name
Description
Default
value
Binnable?
Note
XRCRG1 Parameter for distributed
channelresistance effect for
both intrinsicinput resistance
and chargedeficit NQS models
12.0 Yes Warning
message
issued if
binned
XRCRG1
<=0.0
XRCRG2 Parameter to account for the
excess channel diffusion
resistance for both intrinsic
input resistance and charge
deficit NQS models
1.0 Yes 
RBPB (Also
an instance
parameter)
Resistance connected between
bNodePrime and bNode
50.0ohm No If less
than
1.0e
3ohm,
reset to
1.0e
3ohm
RBPD (Also
an instance
parameter)
Resistance connected between
bNodePrime and dbNode
50.0ohm No If less
than
1.0e
3ohm,
reset to
1.0e
3ohm
RBPS (Also
an instance
parameter)
Resistance connected between
bNodePrime and sbNode
50.0ohm No If less
than
1.0e
3ohm,
reset to
1.0e
3ohm
RBDB (Also
an instance
parameter)
Resistance connected between
dbNode and bNode
50.0ohm No If less
than
1.0e
3ohm,
reset to
1.0e
3ohm
HighSpeed/RF Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 151
RBSB (Also
an instance
parameter)
Resistance connected between
sbNode and bNode
50.0ohm No If less
than
1.0e
3ohm,
reset to
1.0e
3ohm
GBMIN Conductance in parallel with
each of the five substrate
resistances to avoid potential
numerical instability due to
unreasonably too large a
substrate resistance
1.0e
12mho
No Warning
message
issued if
less than
1.0e20
mho
RBPS0 Scaling prefactor for RBPS 50 Ohms No
RBPSL Length Scaling parameter for
RBPS
0.0 No
RBPSW
Width Scaling parameter for
RBPS
0.0 No
RBPSNF Number of fingers Scaling
parameter for RBPS
0.0 No
RBPD0 Scaling prefactor for RBPD 50 Ohms No
RBPDL
Length Scaling parameter for
RBPD
0.0 No
RBPDW Width Scaling parameter for
RBPD
0.0 No
RBPDNF Number of fingers Scaling
parameter for RBPD
0.0 No
RBPBX0 Scaling prefactor for RBPBX 100 Ohms No
RBPBXL Length Scaling parameter
forRBPBX
0.0 No
RBPBXW
Width Scaling parameter for
RBPBX
0.0 No
RBPBXNF Number of fingers Scaling
parameter for RBPBX
0.0 No
RBPBY0 Scaling prefactor for RBPBY 100 Ohms No
RBPBYL
Length Scaling parameter
forRBPBY
0.0 No
RBPBYW
Width Scaling parameter for
RBPBY
0.0 No
RBPBYNF Number of fingers Scaling
parameter for RBPBY
0.0 No
RBSBX0 Scaling prefactor for RBSBX 100 Ohms No
RBSBY0 Scaling prefactor for RBSBY 100 Ohms No
RBDBX0 Scaling prefactor for RBDBX 100 Ohms No
HighSpeed/RF Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 152
RBDBY0 Scaling prefactor for RBDBY 100 Ohms No
RBSDBXL Length Scaling parameter for
RBSBX and RBDBX
0.0 No
RBSDBXW Width Scaling parameter for
RBSBX and RBDBX
0.0 No
RBSDBXNF Number of fingers Scaling
parameter for RBSBX and
RBDBX
0.0 No
RBSDBYL Length Scaling parameter for
RBSBY and RBDBY
0.0 No
RBSDBYW Width Scaling parameter for
RBSBY and RBDBY
0.0 No
RBSDBYNF Number of fingers Scaling
parameter for RBSBY and
RBDBY
0.0 No
Flicker and Thermal Noise Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 153
A.10 Flicker and Thermal Noise Model Parameters
Parameter
name
Description
Default
value
Binnable? Note
NOIA Flicker noise parameter A 6.25e41
(eV)
1
s
1
EF
m
3
for
NMOS;
6.188e40
(eV)
1
s
1
EF
m
3
for
PMOS
No 
NOIB Flicker noise parameter B 3.125e26
(eV)
1
s
1
EF
m
1
for
NMOS;
1.5e25
(eV)
1
s
1
EF
m
1
for
PMOS
No 
NOIC Flicker noise parameter C
8.75 (eV)

1
s
1EF
m
No 
EM Saturation field 4.1e7V/m No 
AF Flicker noise exponent 1.0 No 
EF
Flicker noise frequency
exponent
1.0 No 
KF Flicker noise coefficient
0.0
A2EF
s
1
EFF
No 
LINTNOI Length Reduction Parameter
Offset
0.0 m
No 
NTNOI
Noise factor for shortchannel
devices for TNOIMOD=0 only
1.0 No 
TNOIA Coefficient of channellength
dependence of total channel
thermal noise
1.5 No 
TNOIB Channellength dependence
parameter for channel thermal
noise partitioning
3.5 No 
RNOIA Thermal Noise Coefficient 0.577 No 
RNOIB Thermal Noise Coefficient 0.5164 No 
LayoutDependent Parasitic Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 154
A.11 LayoutDependent Parasitic Model Parameters
Parameter
name
Description
Default
value
Binnable?
Note
DMCG Distance from S/D contact
center to the gate edge
0.0m No 
DMCI Distance from S/D contact
center to the isolation edge in
the channellength direction
DMCG No 
DMDG Same as DMCG but for merged
device only
0.0m No 
DMCGT DMCG of test structures 0.0m No 
NF (instance
parameter
only)
Number of device fingers 1 No Fatal
error if
less than
one
DWJ Offset of the S/D junction
width
DWC (in
CVmodel)
No 
MIN
(instance
parameter
only)
Whether to minimize the
number of drain or source
diffusions for evennumber
fingered device
0
(minimize
the drain
diffusion
number)
No 
XGW(Also
an instance
parameter)
Distance from the gate contact
to the channel edge
0.0m No 
XGL Offset of the gate length due to
variations in patterning
0.0m No 
XL Channel length offset due to
mask/ etch effect
0.0m No 
XW Channel width offset due to
mask/etch effect
0.0m No 
NGCON(Also
an instance
parameter)
Number of gate contacts 1 No Fatal
error if
less than
one; if
not equal
to 1 or 2,
warning
message
issued
and reset
to 1
Asymmetric Source/Drain Junction Diode Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 155
A.12 Asymmetric Source/Drain Junction Diode Model
Parameters
Parameter
name
(separate for
source and
drain side as
indicated in
the names) Description
Default
value Binnable? Note
IJTHSREV
IJTHDREV
Limiting current in reverse
bias region
IJTHSREV
=0.1A
IJTHDREV
=IJTHSREV
No If not
positive,
reset to
0.1A
IJTHSFWD
IJTHDFWD
Limiting current in forward
bias region
IJTHSFWD
=0.1A
IJTHDFWD
=IJTHSFWD
No If not
positive,
reset to
0.1A
XJBVS
XJBVD
Fitting parameter for diode
breakdown
XJBVS=1.0
XJBVD
=XJBVS
No Note8
BVS BVD Breakdown voltage BVS=10.0V
BVD=BVS
No If not
positive,
reset to
10.0V
JSS JSD Bottom junction reverse
saturation current density
JSS= 1.0e
4A/m2
JSD=JSS
No 
JSWS JSWD Isolationedge sidewall
reverse saturation current
density
JSWS
=0.0A/m
JSWD
=JSWS
No 
Asymmetric Source/Drain Junction Diode Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 156
JSWGS
JSWGD
Gateedge sidewall reverse
saturation current density
JSWGS
=0.0A/m
JSWGD
=JSWGS
No 
JTSS JTSD Bottom trapassisted
saturation current density
JTSS
=0.0A/m
JTSD=JTSS
No 
JTSSWS
JTSSWD
STI sidewall trapassisted
saturation current density
JTSSWS
=0.0A/m2
JTSSWD
=JTSSWS
No 
JTSSWGS
JTSSWGD
Gateedge sidewall trap
assisted saturation current
density
JTSSWGS
=0.0A/m
JTSSWGD
=JTSSWGS
No 
JTWEFF Trapassistant tunneling
current density width
dependence
0.0 No 
NJTS NJTSD Nonideality factor for JTSS
and JTSD
NJTS=20.0
NJTSD
=NJTS
No 
NJTSSW
NJTSSWD
Nonideality factor for
JTSSWS and JTSSWD
NJTSSW
=20.0
NJTSSWD
=NJTSSW
No 
NJTSSWG
NJTSSWGD
Nonideality factor
forJTSSWGS and JTSSWGD
NJTSSWG
=20.0
NJTSSWGD
=NJTSSWG
No 
Asymmetric Source/Drain Junction Diode Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 157
XTSS, XTSD Power dependence of JTSS,
JTSD on temperature
XTSS=0.02
XTSD=0.02
No 
XTSSWS,
XTSSWD
Power dependence of
JTSSWS, JTSSWD on
temperature
XTSSWS
=0.02
XTSSWD
=0.02
No 
XTSSWGS,
XTSSWGD
Power dependence of
JTSSWGS, JTSSWGD on
temperature
XTSSWGS
=0.02
XTSSWGD
=0.02
No 
VTSS VTSD Bottom trapassisted voltage
dependent parameter
VTSS=10V
VTSD
=VTSS
No 
VTSSWS
VTSSWD
STI sidewall trapassisted
voltage dependent parameter
VTSSWS
=10V
VTSSWD
=VTSSWS
No 
VTSSWGS
VTSSWGD
Gateedge sidewall trap
assisted voltage dependent
parameter
VTSSWGS
=10V
VTSSWGD
=VTSSWGS
No 
TNJTS
TNJTSD
Temperature coefficient for
NJTS and NJTSD
TNJTS=0.0
TNJTSD
=TNJTS
No 
TNJTSSW
TNJTSSWD
Temperature coefficient for
NJTSSW and NJTSSWD
TNJTSSW=
0.0
TNJTSSWD
=TNJTSSW
No 
TNJTSSWG
TNJTSSWGD
Temperature coefficient for
NJTSSWG and NJTSSWG
TNJTSSWG
=0.0
TNJTSSWGD
= TNJTSSWG
No 
Asymmetric Source/Drain Junction Diode Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 158
CJS CJD Bottom junction capacitance
per unit area at zero bias
CJS=5.0e4
F/m
2
CJD=CJS
No 
MJS MJD
Bottom junction capacitance
grating coefficient
MJS=0.5
MJD=MJS
No 
MJSWS
MJSWD
Isolationedge sidewall
junction capacitance grading
coefficient
MJSWS =0.33
MJSWD
=MJSWS
No 
CJSWS
CJSWD
Isolationedge sidewall
junction capacitance per unit
area CJSWS=
5.0e10 F/m
CJSWD
=CJSWS
No 
CJSWGS
CJSWGD
Gateedge sidewall junction
capacitance per unit length
CJSWGS
=CJSWS
CJSWGD
=CJSWS
No 
MJSWGS
MJSWGD
Gateedge sidewall junction
capacitance grading
coefficient
MJSWGS
=MJSWS
MJSWGD
=MJSWS
No 
PB Bottom junction builtin
potential
PBS=1.0V
PBD=PBS
No 
PBSWS
PBSWD
Isolationedge sidewall
junction builtin potential
PBSWS
=1.0V
PBSWD
=PBSWS
No 
PBSWGS
PBSWGD
Gateedge sidewall junction
builtin potential
PBSWGS
=PBSWS
PBSWGD
=PBSWS
No 
Stress Effect Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 159
A.13 Temperature Dependence Parameters
Parameter
name
Description Default value Binnable? Note
TNOM
Temperature at which
parameters are extracted
27
o
C No 
UTE
Mobility temperature
exponent 1.5 Yes

UCSTE
Temperature coefficient of
coulombic mobility 4.775e3 Yes

KT1
Temperature coefficient for
threshold voltage
0.11V Yes

KT1L
Channel length dependence
of the temperature coefficient
for threshold voltage
0.0Vm Yes 
KT2
Bodybias coefficient of V
th
temperature effect
0.022 Yes

UA1
Temperature coefficient for
UA 1.0e9m/V Yes

UB1 Temperature coefficient for
UB
1.0e18
(m/V)
2
Yes 
UC1 Temperature coefficient for
UC
0.056V1 for
MOBMOD=1;
0.056e9m/ V
2
for
MOBMOD=0
and 2
Yes 
UD1
Temperature coefficient for
UD 0.0(1/m)
2
Yes 
AT
Temperature coefficient for
saturation velocity
3.3e4m/s Yes

PRT
Temperature coefficient for
Rdsw
0.0ohmm Yes 
NJS, NJD
Emission coefficients of
junction for source and drain
junctions, respectively
NJS=1.0;
NJD=NJS
No 
Stress Effect Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 160
XTIS, XTID Junction current temperature
exponents for source and drain
junctions, respectively
XTIS=3.0;
XTID=XTIS
No 
TPB Temperature coefficient of PB 0.0V/K No 
TPBSW
Temperature coefficient of
PBSW
0.0V/K No 
TPBSWG
Temperature coefficient of
PBSWG
0.0V/K No 
TCJ Temperature coefficient of CJ 0.0K1 No 
TCJSW
Temperature coefficient of
CJSW
0.0K1 No 
TCJSWG
Temperature coefficient of
CJSWG
0.0K1 No 
TVOFF
Temperature coefficient of
VOFF
0.0K1 No 
TVFBSDOFF
Temperature coefficient of
VFBSDOFF
0.0K1 No

Stress Effect Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 161
A.14 Stress Effect Model Parameters
Parameter
name
Description
Default
value
Binnable? Note
SA (Instance
Parameter)
Distance between OD edge to
Poly from one side
0.0 If not
given
or(<=0),
stress
effect
will be
turned
off
SB (Instance
Parameter)
Distance between OD edge to
Poly from other side
0.0 If not
given
or(<=0),
stress
effect
will be
turned
off
SD (Instance
Parameter)
Distance between neighbouring
fingers
0.0 For
NF>1 :If
not given
or(<=0),
stress
effect
will be
turned
off
SAref
Reference distance between OD
and edge to poly of one side
1E06[m] No
>0.0
SBref
Reference distance between OD
and edge to poly of the other
side
1E06[m] No >0.0
WLOD
Width parameter for stress
effect 0.0[m] No

KU0
Mobility
degradation/enhancement
coefficient for stress effect
0.0[m] No

Stress Effect Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 162
KVSAT
Saturation velocity degradation/
enhancement parameter for
stress effect
0.0[m] No

1<=kvsat
<=1
TKU0
Temperature coefficient of
KU0
0.0 No 
LKU0 Length dependence of ku0 0.0 No 
WKU0 Width dependence of ku0 0.0 No 
PKU0 Crossterm dependence of ku0 0.0 No 
LLODKU0
Length parameter for u0 stress
effect
0.0 No >0
WLODKU0
Width parameter for u0 stress
effect
0.0 No >0
KVTH0
Threshold shift parameter for
stress effect
0.0[Vm] No

LKVTH0 Length dependence of kvth0 0.0 No 
WKVTH0 Width dependence of kvth0 0.0 No 
PKVTH0
Crossterm dependence of
kvth0
0.0 No 
LLODVTH
Length parameter for V
th
stress
effect
0.0 No >0
WLODVTH
Width parameter for V
th
stress
effect
0.0 No >0
STK2
K2 shift factor related to Vth0
change
0.0[m] No
LODK2
K2 shift modification factor for
stress effect
1.0 No >0
STETA0
eta0 shift factor related to Vth0
change
0.0[m] No
LODETA0
eta0 shift modification factor
for stress effect
1.0 No >0
WellProximity Effect Model Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 163
A.15 WellProximity Effect Model Parameters
Parameter
name
Description
Default
value
Binnable? Note
SCA
(Instance
Parameter)
Integral of the first distribution
function for scattered well
dopant
0.0 no If not
given ,
calculated
SCB
(Instance
Parameter)
Integral of the second
distribution function for
scattered well dopant
0.0 no
If not
given ,
calculated
SCC
(Instance
Parameter)
Integral of the third distribution
function for scattered well
dopant
0.0 no
If not
given ,
calculated
SC (Instance
Parameter)
Distance to a single well edge 0.0[m] no If not
given or
<=0.0,
turn off
WPE
WEB Coefficient for SCB 0.0 No
>0.0
WEC Coefficient for SCC
0.0
No
>0.0
KVTH0WE
Threshold shift factor for well
proximity effect
0.0 Yes

K2WE
K2 shift factor for well
proximity effect
0.0 Yes

KU0WE
Mobility degradation factor for
well proximity effect
0.0 Yes

SCREF
Reference distance to calculate
SCA, SCB and SCC
1e6[m] No >0
dW and dL Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 164
A.16 dW and dL Parameters
Parameter
name Description Default name Binnable? Note
WL
Coefficient of length
dependence for width offset
0.0mWLN No 
WLN
Power of length dependence
of width offset
1.0 No

WW
Coefficient of width
dependence for width offset
0.0mWWN No

WWN
Power of width dependence
of width offset
1.0 No

WWL Coefficient of length and
width cross term dependence
for width offset
0.0
mWWN+WLN
No 
LL
Coefficient of length
dependence for length offset
0.0mLLN No

LLN
Power of length dependence
for length offset
1.0 No

LW
Coefficient of width
dependence for length offset
0.0mLWN No

LWN
Power of width dependence
for length offset
1.0 No

LWL Coefficient of length and
width cross term dependence
for length offset
0.0
mLWN+LLN
No 
LLC
Coefficient of length
dependence for CV channel
length offset
LL No

LWC
Coefficient of width
dependence for CV channel
length offset
LW No

LWLC Coefficient of length and
width crossterm
dependence for CV channel
length offset
LWL No 
WLC
Coefficient of length
dependence for CV channel
width offset
WL No

dW and dL Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 165
WWC
Coefficient of width
dependence for CV channel
width offset
WW No

WWLC
Coefficient of length and width
crossterm dependence for CV
channel width offset
WWL No 
Range Parameters for Model Application
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 166
A.17 Range Parameters for Model Application
Parameter
name Description
Default
value Binnable? Note
LMIN Minimum channel length 0.0m No 
LMAX Maximum channel length 1.0m No

WMIN Minimum channel width 0.0m No

WMAX Maximum channel width 1.0m No

Notes 18
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 167
A.18 Notes 18
Note1: If γ
1
is not given, it is calculated by
1
2
si
oxe
q NDEP
C
ε
γ =
If γ
2
is not given, it is calculated by
2
2
si
oxe
q NSUB
C
ε
γ =
Note2: If NDEP is not given and γ
1
is given, NDEP is calculated from
2 2
1
2
oxe
si
C
NDEP
q
γ
ε
=
If both γ
1
and NDEP are not given, NDEP defaults to 1.7e17cm
3
and γ
1
is calculated
from NDEP.
Note3: If VBX is not given, it is calculated by
2
2
s
si
qNDEP XT
VBX
ε
⋅
= Φ −
Note4: If VTH0 is not given, it is calculated by
0 1
s s bs
VTH VFB K V = + Φ + Φ −
where VFB
= 1.0. If VTH0
is given, VFB defaults to
0 1
s s bs
VFB VTH K V = −Φ − Φ −
Note5: If K
1
and K
2
are not given, they are calculated by
2
1 2 2
s
K K VBM γ = − Φ −
( )
( )
( )
1 2
2
2
s s
s s s
VBX
K
VBM VBM
γ γ − Φ − − Φ
=
Φ Φ − − Φ +
Notes 18
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 168
Note6: If CGSO is not given, it is calculated by
If (DLC is given and > 0.0)
oxe
CGSO DLC C CGSL = ⋅ −
if (CGSO < 0.0), CGSO = 0.0
Else
0.6
oxe
CGSO XJ C = ⋅ ⋅
If CGBO is not given, it is calculated by
2
oxe
CGBO DWC C = ⋅ ⋅
Note8:
For dioMod = 0, if XJBVS < 0.0, it is reset to 1.0.
For dioMod = 2, if XJBVS <=0.0, it is reset to 1.0.
For dioMod = 0, if XJBVD < 0.0, it is reset to 1.0.
For dioMod = 2, if XJBVD <=0.0, it is reset to 1.0.
Core Parameters
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 169
Appendix B: Core Parameters
Parameter
name
Description
Default
value
Binnable? Note
TOXE Electrical gate equivalent oxide
thickness
3.0e9m No Fatal
error if
not
positive
TOXP Physical gate equivalent oxide
thickness
TOXE No Fatal
error if
not
positive
DTOX Defined as (TOXETOXP) 0.0m No 
XJ S/D junction depth 1.5e7m Yes

NDEP Channel doping concentration
at depletion edge for zero body
bias
1.7e17cm
3
Yes Note2
VTH0 or
VTHO
Longchannel threshold voltage
at V
bs
=0
0.7V
(NMOS)
0.7V
(PMOS)
Yes Note4
K1
Firstorder body bias
coefficient
0.5V
1/2
Yes Note5
K2
Secondorder body bias
coefficient
0.0 Yes Note5
LPE0 Lateral nonuniform doping
parameter at V
bs
=0
1.74e7m Yes 
DVT0 First coefficient of short
channel effect on V
th
2.2 Yes 
DVT1
Second coefficient of short
channel effect on V
th
0.53 Yes 
U0 Lowfield mobility
0.067
m
2
/(Vs)
(NMOS);
0.025
m
2
/(Vs)
PMOS
Yes 
VSAT Saturation velocity 8.0e4m/s Yes 
References
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 170
Appendix C: References
[1] Y. C. King, H. Fujioka, S. Kamohara, K. Chen, and Chenming Hu, “DC electrical
oxide thickness model for quantization of the inversion layer in MOSFETs”, Semicond.
Sci. Technol., vol. 13, pp. 963966, 1998.
[2] Weidong Liu, Xiaodong Jin, Yachin King, and Chenming Hu, “An efficient and
accurate compact model for thinoxideMOSFET intrinsic capacitance considering the
finite charge layer thickness”, IEEE Trans. Electron Devices, vol. ED46, May, 1999.
[3] Kanyu M. Cao, Weidong Liu, Xiaodong Jin, Karthik Vasanth, Keith Green, John
Krick, Tom Vrotsos, and Chenming Hu, “Modeling of pocket implanted MOSFETs for
anomalous analog behavior,” Tech. Dig. of IEDM, pp. 171174, 1999.
[4] Z.H. Liu, C. Hu, J.H. Huang, T.Y. Chan, M.C. Jeng, P.K. Ko, and Y.C.
Cheng,“Threshold Voltage Model For DeepSubmicrometer MOSFETs,” IEEE Tran.
Electron Devices, vol. 40, pp. 8695, 1993.
[5] J.A. Greenfield and R.W. Dutton, “Nonplanar VLSI Device Analysis Using the
Solution of Poisson's Equation,” IEEE Trans. Electron Devices, vol. ED27, p.1520,
1980.
[6] H. S. Lee, “An Analysis of the Threshold Voltage for ShortChannel IGFET's,” Solid
State Electronics, vol.16, p.1407, 1973.
[7] Yuhua Cheng and Chenming Hu, “MOSFET Modeling & BSIM3 User’s Guide,”
Kluwer Academic Publishers, 1999.
[8] C. Hu, S. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan and K.W. Kyle, "HotElectron Induced
MOSFET Degradation  Model, Monitor, Improvement," IEEE Trans. Electron Devices,
vol. 32, pp. 375385, 1985.
[9] T. Y. Chen, J. Chen, P. K. Ko, C. Hu, “The impact of gateinduced drain leakage
current on MOSFET scaling,” Tech. Digest of IEDM, pp. 718721, 1987.
[10] S. A. Parke, E. Moon, HJ. Wenn, P. K. Ko, and C. Hu, “Design for suppression of
gateinduced drain leakage in LDD MOSFETs using a quasi 2D analytical model,”
IEEE Trans. Electron Devices, vol. 39, no. 7, pp 16941703, 1992.
[11] Weidong Liu, Xiaodong Jin, J. Chen, M. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan,
K. Hui, J. Huang, R. Tu, P. Ko, and Chenming Hu, “BSIM3v3.2 MOSFET Model and
Users’ Manual,” http://wwwdevice.eecs.berkeley.edu/~bsim3.
[12] Xiaodong Jin, JJ Ou, CH Chen, Weidong Liu, Paul Gray, and Chenming Hu, “An
effective gate resistance model for CMOS RF and noise modeling,” Tech. Dig. of
IEDM, pp. 961964, 1998.
[13] Mansun Chan, K. Hui, R. Neff, C. Hu, P. Ko, “A Relaxation time Approach to
Model the NonQuasiStatic Transient Effects in MOSFETs,” Tech. Dig. of IEDM, pp.
169172, 1994.
References
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley 171
[14] K.K. Hung, P. Ko, C. Hu, and Y. C. Cheng, “A PhysicsBased MOSFET Noise
Model for Circuit Simulators,” IEEE Trans. Electron Devices, vol. 37, no. 5, pp. 1323
1333, 1990.
[15] Weidong Liu, Kanyu M. Cao, Xiaodong Jin, and Chenming Hu, “BSIM4.0.0
Technical Notes,” http:// wwwdevice.eecs.berkeley.edu/~bsim3/bsim4.html.
[16] R.A.Bianchi, G.Bouche and O.RouxditBuisson, "Accurate Modeling of Trench
Isolation Induced Mechanical Stress Effect on MOSFET Electrical Performance,"
IEDM 2002, pp. 117120.
[17] Hook, T.B.; Brown, J.; Cottrell, P.; Adler, E.; Hoyniak, D.; Johnson, J.; Mann, R.,
“Lateral ion implant straggle and mask proximity effect”, IEEE Trans. Electron
Devices, Volume 50, no 9, pp 1946 1951, Sept. 2003
[18] YiMing Sheu, KeWei Su, ShengJier Yang, HsienTe Chen, ChihChiang Wang,
MingJer Chen, and Sally Liu, “Modeling Well Edge Proximity Effect on Highly
Scaled MOSFETs”, CICC 2005
[19] CMC Website : http://www.eigroup.org/cmc
Developers:
BSIM4.6.4 Developers: Professor Chenming Hu (project director), UC Berkeley Professor Ali M. Niknejad(project director), UC Berkeley Wenwei Yang, UC Berkeley Darsen Lu, UC Berkeley
Developers of BSIM4 Previous Versions:
Dr. Weidong Liu, Synopsys Dr. Xiaodong Jin, Marvell Dr. Kanyu (Mark) Cao, UC Berkeley Dr. Jeff J. Ou, Intel Dr. Jin He, UC Berkeley Dr. Xuemei (Jane) Xi, UC Berkeley Mohan V. Dunga, UC Berkeley Professor Ali M. Niknejad, UC Berkeley Professor Chenming Hu, UC Berkeley Web Sites: BSIM4 web site with BSIM source code and documents:
http://wwwdevice.eecs.berkeley.edu/~bsim3/bsim4.html Compact Model Council: http://www.eigroup.org/CMC/default.htm
Technical Support: Tanvir Hasan Morshed: morshedt@eecs.berkeley.edu BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
Acknowledgement:
The development of BSIM4.6.4 benefited from the input of many BSIM users, especially the Compact Model Council (CMC) member companies. The developers would like to thank Xingming Liu and Jushan Xie at Cadence, Joddy Wang, Robin Tan, Jane Xi and Weidong Liu at Synopsys, Ben Gu at Freescale, James Ma at ProPlus Design, Joe Watts at IBM, Geoffrey Coram at Analog Device, Weihung Chen at UC Berkeley, for their valuable assistance in identifying the desirable modifications and testing of the new model. The BSIM project is partially supported by SRC and CMC.
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
................................................. 1 1........................................................Contents Chapter 1: Effective Oxide Thickness.......................... 22 Chapter 4: Gate Direct Tunneling Current Model ..... 25 4...........5 Velocity Saturation........................................4 Drain Current for Triode Region................................................ 19 3....................... 35 5............................................................................................................................................................... 11 2.3..................................................................3 Effective Channel Length and Width............................................................................................................. 33 5. 10 2......................................................................................................5 NarrowWidth Effect....................................... 36 5.................. 30 5................ 13 2.. Partition of Igc ................................................... 28 Chapter 5: Drain Current Model ..............................................1 Intrinsic case .....................................................3....4 Manual Copyright © 2009 UC Berkeley .............. 24 4..................... 10 2......................................................... 14 2................................................3..................... 37 5.................................2 NonUniform Vertical Doping ........ 16 Chapter 3: Channel Charge and Subthreshold Swing Models............................................................... 26 4.2 Voltage Across Oxide Vox ................... 37 BSIM4.............................2 Extrinsic Case ........................................ 7 Chapter 2: Threshold Voltage Model ..................2 Unified Mobility Model ....1 Model Selectors.....................3.............. 37 5...6.............2 PolySilicon Gate Depletion..................6 Saturation Voltage Vdsat ................ 27 4........................4 ShortChannel and DIBL Effects .. 4 1...................... 25 4. 30 5...........................................1 Bulk Charge Effect.............................3 NonUniform Lateral Doping: Pocket (Halo) Implant........1 LongChannel Model With Uniform Doping.................................1 Gate Dielectric Model ...................................................................................3 Asymmetric and BiasDependent Source/ Drain Resistance Model............6...................................................................................................... 26 4.........2 GatetoChannel Current (Igc0) and GatetoS/D (Igs and Igd) ................................................................................3 Equations for Tunneling Currents ............................................................................................................................... 30 5......................................2 Subthreshold Swing n........................................ 19 3........6..............................................................................................................1 GatetoSubstrate Current (Igb = Igbacc + Igbinv)....1 Channel Charge Model........... 3 1..... Channel Length and Channel Width .....................................................
...6.........................4............................................................................. 55 7...........1 General Description...2 capMod = 1................. 40 5.....4 Manual Copyright © 2009 UC Berkeley ...... 60 7...................................... 44 Chapter 6: Body Current Models...... 70 8................................ 44 5......................................................... 46 Chapter 7: Capacitance Model....................2..........................................................................................2......... 49 7..............................................................7......1 Velocity Overshoot ........................ 41 5.......................7........................5..................................5......................................................................................... 46 6.....................................................................1 Iii Model...........3Vdseff Formulation......................7....4............................................44 5. 40 5..........................4 DrainInduced Threshold Shift (DITS) by Pocket Implant ...... 49 7....................................................................2 IGIDL and IGISL Model ....................................................................... 52 7.......................7 SaturationRegion Output Conductance Model ..............1 Model Selector .................2 Short Channel Model..9.............................................1 Basic Formulation.......3 Substrate Current Induced Body Effect (SCBE) ........................1 Channel Length Modulation (CLM)............... 66 7............................................................4.................................................6..........................................3 ChargeThickness Capacitance Model (CTM) ........ 50 7........Charge partitioning ...............................8 SingleEquation Channel Current Model.............................................3 capMod = 2............................................ 64 7.2 DrainInduced Barrier Lowering (DIBL) ..... 38 5......2.......................................1 capMod = 0.............. 62 7...............................................................................................................................................................................9. 67 Chapter 8: New Material Models...................................................................................................................3 Single Equation Formulation.................................................................................... 56 7.................................1 Fringing capacitance model........................................... 66 7.....................................2 Source End Velocity Limit Model........................5...................................................................2 Methodology for Intrinsic Capacitance Modeling ........................................................................................................................................................ 38 5........... 54 7................................7............................................5 Fringing/Overlap Capacitance Models....2....2 Overlap capacitance model........ 70 BSIM4...4 Intrinsic Capacitance Model Equations....... 46 6................9 New Current Saturation Mechanisms: Velocity Overshoot and Source End Velocity Limit Model.................... 50 7. 43 5...........................4.......................... 60 7..... 43 5...............................
.....................2 Drain/Body Junction Diode ..1.....................................3 Substrate Resistance Network.....1 Source/Body Junction Diode ................................ 91 11...........................1..........3 Total Junction Source/Drain Diode Including Tunneling ................1........... 88 Chapter 11: Asymmetric MOS Junction Diode Models ................ 89 11...........................3 NonSiO2 Gate insulator......................................................6..................................................................... 71 8............................................. 84 10....... 75 9.............2....................................................................2 NonSilicon Channel ......................1 Flicker Noise Models ..............2 Model Selector and Topology ........................3 Other Noise Sources Modeled..............1 Effective Junction Perimeter and Area.................... 80 9............................................................................................4 Manual Copyright © 2009 UC Berkeley ..... 74 9............................................................................................1..1 Transient Model........................................................................................................................................ 96 12.................................2 AC Model .....................................2 Junction Diode CV Model....................................................................................................................................................................................2 Channel Thermal Noise. 89 11...................2.................................................2 Gate Electrode Electrode and IntrinsicInput Resistance (IIR) Model ................ 92 11..........................2..... 80 Chapter 10: Noise Modeling...... 77 9......... 93 11..............................1........2......................................................... 74 9............................................................2 Drain/Body Junction Diode ........1 General Description... 80 9........ 96 12................................ 97 12.. 84 10......................................................................................................................................................................... 84 10...........................1 Geometry Definition ............. 78 9. 72 Chapter 9: HighSpeed/RF Models..................................... 89 11...................... 70 8........ 84 10............................1 ChargeDeficit NonQuasiStatic (NQS) Model.......... 86 10............ 94 Chapter 12: LayoutDependent Parasitics Models ........................1 General Description........................ 78 9.........................................2 Equations ..........4 NonPoly Silicon Gate Dielectric..................................2 Model Formulation and Options ............................. 97 BSIM4......................................................................1 General Description....................................... 93 11...........3...........................................3.............................................................. 78 9.............................1...................................1...2 Model Option and Schematic ....1 Junction Diode IV Model..8..................1 Source/Body Junction Diode .........................2.........................................................................................................................................................
................................................................................................ 119 16.................1 BSIM4.....3 Basic Model Parameters....4 Option for Source/Drain Connections ............... 108 Chapter 14: Stress Effect Model ...................................................1 Well Proximity Effect Model.................................................................1......................................4 Temperature Dependence of LDD ....................1 Mobilityrelated Equations ..................................................3 Temperature Dependence of Saturation Velocity ....................................................................................5 Temperature Dependence of Junction. 131 A...... 136 BSIM4............................1 Stress Effect Model Development................... 118 16.......... 123 Appendix A: Complete Parameter List..............................................6 Temperature Dependence of Junction Diode CV ............................. 98 12..........................2 Optimization .......... 114 14.....................2 Process Parameters ....................................... 103 13............................2 Extraction Strategy.........................6......6........3......3 Extraction Routine.....................................3 Multiple Finger Device......... 119 16..................................................................................... 102 13........... 113 14..........................................................................................................2 Source/Drain Diffusion Resistance ........................ 131 A.......................... 99 12....... 101 13..................................................................................................................................................................................................1....................3........................................................................................ 114 Chapter 15: Well Proximity Effect Model.......... 99 12...7 Temperature Dependences of Eg and ni ........2 Vthrelated Equations .......1 Model Selectors/Controller.................................................................2 Temperature Dependence of Mobility .....................................................1 Optimization strategy ..............................................1 Extraction Requirements ...2 Effective SA and SB for Irregular LOD....................5 Option for Source/Drain Contacts .................................... 100 Chapter 13: Temperature Dependence Model .....2..........3.............................................................................................2...............2............................... 119 16............ 117 Chapter 16: Parameter Extraction Methodology .....................1.........................................12..................................................................3 Extraction Procedure ..............1 Temperature Dependence of Threshold .. 107 13............ 101 13................................................................................................................2.............................. 134 A.................. 118 16.................... 104 13........ 111 14........... 101 13.. 110 14.......... 121 16..............................................................3 Gate Electrode Resistance .................................. 116 15............. 110 14...................................4 Manual Copyright © 2009 UC Berkeley .......................
............ 142 A................. 166 A.............................7 Gate Dielectric Tunneling Current Model Parameters............................9 HighSpeed/RF Model Parameters................................................6.....................4 Parameters for Asymmetric and BiasDependent Rds Model ........................ 167 Appendix B: Core Parameters ............ 143 A...... 163 A...................................16 dW and dL Parameters.......... 153 A..........................18 Notes 18 ......................11 LayoutDependent Parasitic Model Parameters ....................................................... 161 A............................................................10 Flicker and Thermal Noise Model Parameters......................................8 Charge and Capacitance Model Parameters...............12 Asymmetric Source/Drain Junction Diode Model Parameters ....................... 145 A................................................................... 154 A...........................A.....17 Range Parameters for Model Application .................................................................5 Impact Ionization Current Model Parameters .15 WellProximity Effect Model Parameters................4 Manual Copyright © 2009 UC Berkeley ................................................... 150 A............................................................................................... 155 A..................................... 144 A...... 170 BSIM4.......... 164 A.......................................6 GateInduced Drain Leakage Model Parameters .......... 148 A..... 159 A............................................. 169 Appendix C: References ...................................................13 Temperature Dependence Parameters ...............................................14 Stress Effect Model Parameters .......................
Effective Oxide Thickness. The continuous scaling of minimum feature size brought challenges to compact modeling in two ways: One is that to push the barriers in making transistors with shorter gate length. (8) better model for pocketimplanted devices in Vth. (2) flexible substrate resistance network for RF modeling. (9) asymmetrical and biasdependent source/drain resistance. Channel Length and Channel Width Chapter 1: Effective Oxide Thickness. (3) a new accurate channel thermal noise model and a noise partition model for the induced gate noise. To meet these challenges.4 Manual Copyright © 2009 UC Berkeley 1 . bulk charge effect model. either internal or external to the intrinsic MOSFET at the user's discretion. as the extension of BSIM3 model. advanced process technologies are used such as nonuniform substrate doping. (7) improved model for steep vertical retrograde doping profiles. BSIM4 has the following major improvements and additions over BSIM3v3: (1) an accurate new model of the intrinsic input resistance for both RF. The second is its opportunities to RF applications. (6) a comprehensive and versatile geometrydependent parasitics model for various source/drain connections and multifinger devices. highfrequency analog and highspeed digital applications. addresses the MOSFET physical effects into sub100nm regime.6. (4) a nonquasistatic (NQS) model that is consistent with the Rgbased RF model and a consistent AC model that accounts for the NQS effect in both transconductances and capacitances. Channel Length and Channel Width BSIM4. and Rout. (5) an accurate gate direct tunneling model for multiple layer gate dielectrics. (10) acceptance of BSIM4.
(18) A new scalable stress effect model for process induced stress effect.velocity saturation. which is smooth over all bias regions and considers the bulk charge effect. (20) A new temperature model format that allows convenient prediction of temperature effects on saturation velocity. (12) a more accurate mobility model for predictive modeling. nonpolySi gate and nonSi channel. BSIM4. (13) a improved gateinduced drain/source leakage (GIDL/GISL) current model considering the work function difference between drain/source and gate. (23) an improved model predicts well the mobility behavior in high k/metal gate structure. (22) A new threshold voltage definition is introduced into CV model to improve subthreshold fitting.6. (16) junction diode breakdown with or without current limiting.4 Manual Copyright © 2009 UC Berkeley 2 . (11) the quantum mechanical chargelayerthickness model for both IV and CV. and S/D resistances.Effective Oxide Thickness. Channel Length and Channel Width anyone of the electrical. (15) different diode IV and CV chrematistics for source and drain junctions. device performance becoming thus a function of the active area geometry and the location of the device in the active area. (14) an improved unified flicker (1/f) noise model. (19) A unified currentsaturation model that includes all mechanisms of current saturation. velocity overshoot and source end velocity limit. mobility. (17) dielectric constant of the gate dielectric as a model parameter. physical gate oxide thickness or equivalent oxide thickness as the model input at the user's choice in a physically accurate manner. (24) a width dependent trapassistant tunneling model is introduced to describe the current density enhancement in narrow device. (21) A improved material model that is suitable to describe nonSiO2 gate insulator.
TOXP could be calculated as following: TOXP = EOT − 3. This selector will be discussed in detail in Chapter 8. For this purpose. It is worth pointing out that the new model parameters: the effective width (Weffeot). Channel Length and Channel Width 1. Based on these parameters. • mrtlMod=1. mrtlMod is a global selector which is used to turn on or off the new material models.Effective Oxide Thickness. Figure 1. the equivalent SiO2 thickness (EOT) is the input parameter.9 × X DC V =VDDEOT . the finite chargelayer thickness can’t be ignored [1]. Here.1) In this case. the physical gate oxide thickness TOXP. BSM4 accepts two of the following methods as the model inputs: • mrtlMod=0.6.V =V =0 gs ds bs EPSRSUB (1.1 Gate Dielectric Model As the gate oxide thickness is vigorously scaled down. 1 Capital and italic alphanumericals in this manual are model parameters.1 illustrates the algorithm and options for specifying the gate dielectric thickness and calculation of the gate dielectric capacitance for BSIM4 model evaluation. the effect of effective gate oxide capacitance Coxeff on IV and CV is modeled [2]. Based on EOT.4 Manual Copyright © 2009 UC Berkeley 3 . BSIM4 models this effect in both IV and CV. and their difference DTOX = TOXE – TOXP are the input parameters. the electrical gate oxide thickness TOXE 1 . temperature (Tempeot) and bias condition (Vddeot) for EOT extraction are also needed in this calculation. BSIM4. for the highk gate dielectric. length (Leffeot). TOXE is equal to EOT.
6. e.2 PolySilicon Gate Depletion When a gate voltage is applied to the polysilicon gate.1 Algorithm for BSIM4 gate dielectric model. NMOS with n+ polysilicon gate. 1.g.Effective Oxide Thickness. its effect cannot be ignored since the gate oxide thickness is small.4 Manual Copyright © 2009 UC Berkeley 4 . BSIM4. Although this depletion layer is very thin due to the high doping concentration of the polysilicon gate. Channel Length and Channel Width Figure 1. a thin depletion layer will be formed at the interface between the polysilicon and the gate oxide.
5 X poly E poly qNGATE ⋅ X = 2ε si poly 2 (1. The device is in the strong inversion region.2. The doping concentration in the n+ polysilicon gate is NGATE and the doping concentration in the substrate is NSUB. NGATE Figure 1. Charge distribution in a MOSFET with the poly gate depletion effect. In the presence of the depletion region.6.4 Manual Copyright © 2009 UC Berkeley 5 . the voltage drop across the gate oxide and the substrate will be reduced.Effective Oxide Thickness.2 shows an NMOSFET with a depletion region in the n+ polysilicon gate. The effective gate voltage can be calculated in the following manner. The depletion width in the substrate is Xd. The voltage drop in the poly gate Vpoly can be calculated as V poly = 0. because part of the gate voltage will be dropped across the depletion region in the gate.2) BSIM4. The depletion width in the poly gate is Xp. Channel Length and Channel Width Figure 1. That means the effective gate voltage will be reduced. Assume the doping concentration in the poly gate is uniform. The positive charge near the interface of the polysilicon gate and the gate oxide is distributed over a finite depletion region with thickness Xp.
3). EPSRGATE =0 means the metal gate.5).6) By solving (1. The gate voltage satisfies Vgs − VFB − Φ s = V poly + Vox (1.2) and (1. BSIM4. Considering the nonsilicon channel or highk gate insulator. From (1.4) where Vox is the voltage drop across the gate oxide and satisfies Vox = EoxTOXE. and there is no depletion effect. Vgse is modified as follows: Vgse 2coxe2 (Vgs − VFB − Φ s ) qε gate NGATE 1+ = VFB + Φ s + − 1 coxe 2 qε gate NGATE (1. Channel Length and Channel Width where Epoly is the maximum electrical field in the poly gate.Effective Oxide Thickness.7) The above discussion is only suitable when mrtlMod=0.3) where Eox is the electric field in the gate oxide. The boundary condition at the interface of poly gate and the gate oxide is EPSROX ⋅ Eox = ε si E poly = 2qε si NGATE ⋅ V poly (1. we get the effective gate voltage Vgse which is equal to Vgse 2 EPSROX 2 (Vgs − VFB− Φ s ) qε si NGATE ⋅ TOXE 2 = VFB + Φ s + − 1 1+ EPSROX 2 qε si NGATE ⋅ TOXE 2 (1.5) where a= EPSROX 2 2qε si NGATE ⋅ TOXE 2 (1. we can obtain a (Vgs − VFB − Φ s − V poly ) − V poly = 0 2 (1.6.4 Manual Copyright © 2009 UC Berkeley 6 .8) Note: Here ε si = EPSRGATE ⋅ EPS 0 .
dW and dL are modeled by dW = dW '+ DWG ⋅ Vgsteff + DWB dW ' = WINT + ( Φ s − Vbseff − Φ s ) (1.12) WL WW WWL + WWN + WLN WWN WLN L W L W dL = LINT + LL LW LWL + LWN + LLN LWN LLN L W L W WINT represents the traditional manner from which "delta W" is extracted (from the intercept of straight lines on a 1/Rds~Wdrawn plot). Channel Length and Channel Width 1. For dL.10) and (1. NF is the number of device fingers. The parameters DWG and DWB are used to account for the contribution of both gate and substrate bias effects.Effective Oxide Thickness. the above geometrical dependencies for dW and dL are turned off.10) (1. BSIM4. Ldrawn and their product term.11) Weff = Weff ' = Wdrawn + XW − 2dW NF Wdrawn + XW − 2dW ' NF The difference between (1. They are meant to allow the user to model each parameter as a function of Wdrawn.4 Manual Copyright © 2009 UC Berkeley 7 .11) is that the former includes bias dependencies.6. LINT represents the traditional manner from which "delta L" is extracted from the intercept of lines on a Rds~Ldrawn plot). The remaining terms in dW and dL are provided for the convenience of the user.9) (1.3 Effective Channel Length and Width The effective channel length and width used in the drain current model are given below where XL and XW are parameters to account the channel length/width offset due to mask/etch effect Leff = Ldrawn + XL − 2dL (1. By default.
The effective channel length Leff for the IV model does not necessarily carry a physical meaning. The Lactive parameter extracted from capacitance is a closer representation of the metallurgical junction length (physical length). which is defined by the effective length (Lactive) and width (Wactive) when the gate to source/drain regions are under flatband condition. Unlike the case of IV.Effective Oxide Thickness. we assume that these dimensions are bias. This Leff is therefore very sensitive to the IV equations and also to the conduction characteristics of the LDD region relative to the channel region. etching and oxidation) on one side.15) (1. the source to drain length can have a very BSIM4. Channel Length and Channel Width MOSFET capacitances can be divided into intrinsic and extrinsic components.6. Lactive and Wactive are defined as Lactive = Ldrawn + XL − 2dL (1. The intrinsic capacitance is associated with the region between the metallurgical source and drain junction.14) (1. Due to the graded source/drain junction profile.16) Wactive = dL = DLC + dW = DWC + Wdrawn + XW − 2dW NF LLC LWC LWLC + LWN + LLN LWN LLN L W L W WLC WWC WWLC + WWN + WLN WWN WLN L W L W The meanings of DWC and DLC are different from those of WINT and LINT in the IV model. The parameter δLeff is equal to the source/drain to gate overlap length plus the difference between drawn and actual POLY CD due to processing (gate patterning. It is just a parameter used in the IV formulation. A device with a large Leff and a small parasitic resistance can have a similar current drive as another with a smaller Leff but larger Rds.4 Manual Copyright © 2009 UC Berkeley 8 .13) (1.dependent.
BSIM4 uses the effective source/drain diffusion width Weffcj for modeling parasitics. WLC. LWC.17) Note: Any compact model has its validation limitation. BSIM4 is its own valid designation limit which is larger than the warning limit. LWLC.4 Manual Copyright © 2009 UC Berkeley 9 . BSIM4 assumes that the DC biasindependent Leff and Weff will be used for the capacitance models. Parameter name Leff LeffCV Weff WeffCV Toxe Toxp Toxm Designed Limitation(m) 1e8 1e8 1e7 1e7 5e10 5e10 5e10 Warning Limitation(m) 1e9 1e9 1e9 1e9 1e10 1e10 1e10 Fatal Limitation(m) 0 0 0 0 0 0 0 BSIM4. and gateinduced drain leakage (GIDL) current. DLC and the length/width dependence parameters (LLC. so does BSIM4. Channel Length and Channel Width strong bias dependence. For users’ reference. shown in following table. WWC and WWLC will be set to the values of their DC counterparts. the fatal limitation in BSIM4 is also shown. such as source/drain resistance. Weffcj is defined as Weffcj = Wdrawn WLC WWC WWLC + XW − 2 ⋅ DWJ + WLN + WWN + WLN WWN NF L W L W (1.Effective Oxide Thickness. LWLC. and DWC.6. We therefore define Lactive to be that measured at flatband voltage between gate to source/drain. WWC and WWLC) are not specified in technology files. gate electrode resistance. LWC. LLC. If DWC. DLC. WLC.
3) If VTH0 isn’t given.6. Vth for long and wide MOSFETs with uniform substrate doping is given by Vth = VFB + Φ s + γ Φ s − Vbs = VTH 0 + γ ( Φ s − Vbs − Φ s ) (2. a new instance parameter DELVTO is added to VTH0 as: If VTH0 is given.1) assumes that the channel doping is constant and the channel length and width are large enough. Modifications have to be made when the substrate doping concentration is not constant and/or when the channel is short. BSIM4. VTH0 is the threshold voltage of the long channel device at zero substrate bias.1) where VFB is the flat band voltage. Equation (2.4 Manual Copyright © 2009 UC Berkeley 10 . or narrow. VTH 0 = VTH 0 + DELVTO (2.1 LongChannel Model With Uniform Doping Accurate modeling of threshold voltage Vth is important for precise description of device electrical characteristics.Threshold Voltage Model Chapter 2: Threshold Voltage Model 2.2) where Nsubstrate is the uniform substrate doping concentration. Consider process variation. and γ is the body bias coefficient given by γ= 2qε si N substrate Coxe (2.
2 NonUniform Vertical Doping The substrate doping profile is not uniform in the vertical direction and therefore γ in (2.4 + k BT NDEP ln q ni (2.8) and (2.9).Threshold Voltage Model VFB = VFB + DELVTO VTH 0 = VFB + Φ s + γ Φ s (2.7) where ni is the intrinsic carrier concentration in the channel region.5) where K1NDEP is the bodybias coefficient for Nsubstrate = NDEP.4 Manual Copyright © 2009 UC Berkeley 11 . The zeroth and 1st moments of the vertical doping profile in (2.8) (2.2) is a function of both the depth from the interface and the substrate bias. NDEP + qD0 qD + K1NDEP ϕ s − Vbs − 1 − ϕ s − Vbs ε si Coxe (2. as D0 = D00 + D01 = ∫ D1 = D10 + D11 = ∫ 0 X dep 0 0 ( N ( x ) − NDEP ) dx + ∫ ( N ( x ) − NDEP ) dx X dep X dep 0 X dep X dep 0 (2.4) 2. NDEP = VTH 0 + K1NDEP ( ϕ s − Vbs − ϕ s ) (2. Vth for nonuniform vertical doping is Vth = Vth . If Nsubstrate is defined to be the doping concentration (NDEP) at Xdep0 (the depletion edge at Vbs = 0).6.6) with a definition of ϕ s = 0.5) are given by (2. C01 BSIM4. it can be shown that D01 is approximately equal to C01Vbs and that D10 dominates D11. Vth . respectively.9) X dep 0 ( N ( x ) − NDEP ) xdx + ∫ ( N ( x ) − NDEP ) xdx By assuming the doping profile is a steep retrograde.
and PHIN are implemented as model parameters for model flexibility.16) 2qε si NDEP Coxe 2qε si NSUB Coxe BSIM4.12) VTH0. etc.14) where γ1 and γ2 are the body bias coefficients when the substrate doping concentration are equal γ1 = γ2 = to NDEP and NSUB.15) (2. Detail information on the doping profile is often available for predictive modeling. K2. BSIM4 allows K1 and K2 to be calculated based on such details as NSUB. and the surface potential is defined as Φ s = 0. Like BSIM3v3. K1. (with the same meanings as in BSIM3v3): K1 = γ 2 − 2K 2 Φ s − VBM K2 = (2. VBM.13) (γ 1 − γ 2 ) ( 2 Φs ( Φ s − VBX − Φ s Φ s − VBM − Φ s + VBM ) ) (2. XT.4 Manual Copyright © 2009 UC Berkeley 12 .5) through (2.9).4 + k BT NDEP ln + PHIN q ni (2. VBX. respectively: (2. Combining (2. we obtain Vth = VTH 0 + K1 ( Φ s − Vbs − Φ s − K 2 ⋅ Vbs ) (2.11) where PHIN = − qD10 ε si (2. Appendix A lists the model selectors and parameters.Threshold Voltage Model represents the profile of the retrograde.10) where K2 = qC01 / Coxe.6.
the above equation is simplified and implemented as for tempMod = 1: Leff ∆Vth ( DITS ) = − nvt ⋅ ln Leff + DVTP 0 ⋅ 1 + e − DVTP1⋅Vds (2.6. Vth is written as Vth = VTH 0 + K1 ( Φ s − Vbs − Φ s ⋅ 1 + ) LPEB − K 2 ⋅ Vbs Leff (2. the doping concentration near the source/drain junctions is higher than that in the middle of the channel.19) For Vds of interest. a Vth rollup will usually result since the effective channel doping concentration gets higher. which changes the body bias effect as well. To consider these effects. Therefore. and is determined by qNDEP ⋅ XT 2 = Φ s − VBX 2ε si (2.4 Manual Copyright © 2009 UC Berkeley 13 .Threshold Voltage Model VBX is the body bias when the depletion width is equal to XT.3 NonUniform Lateral Doping: Pocket (Halo) Implant In this case.17) 2. pocket implant can cause significant draininduced threshold shift (DITS) in longchannel devices [3]: 1 − e −Vds / vt ⋅ Leff ∆Vth ( DITS ) = − nvt ⋅ ln Leff + DVTP0 ⋅ 1 + e − DVTP1⋅Vds ( ( ) ) (2.18) LPE 0 + K 1 1 + − 1 Φ s Leff In addition. as channel length becomes shorter.20) ( ) for tempMod = 2: BSIM4.
when tempMod=0 or 1.21) is used.21) ( ) Note: when tempMod =2. Vth shows a greater dependence on channel length (SCE: shortchannel effect) and drain bias (DIBL: drain induced barrier lowering).(3. Vth change due to SCE and DIBL is modeled [4] ∆Vth ( SCE . DIBL ) = −θ th ( Leff ) ⋅ 2 (Vbi − Φ s ) + Vds (2.4 ShortChannel and DIBL Effects As channel length becomes shorter.23) where Vbi. draininduced threshold voltage shift (DITS) due to pocket implant has no temperature dependence. known as the builtin voltage of the source/drain junctions.22) ( ) 2. Based on the quasi 2D solution of the Poisson equation.23) has a strong dependence on the channel length given by BSIM4.(3.4 Manual Copyright © 2009 UC Berkeley 14 . Leff ∆Vth ( DITS ) = − nvtnom ⋅ ln Leff + DVTP 0 ⋅ 1 + e − DVTP1⋅Vds (2. The shortchannel effect coefficient θth(Leff) in (2. Eq.6. so nominal temperature (TNOM) is used as Eq.22). because the body bias has weaker control of the depletion region.Threshold Voltage Model Leff ∆Vth ( DITS ) = − nvt ⋅ ln Leff + DVTP 0 ⋅ 1 + e − DVTP1⋅Vds (2. is given by Vbi = k BT NDEP ⋅ NSD ln q ni 2 (2. Vth dependence on the body bias becomes weaker as channel length becomes shorter.24) where NSD is the doping concentration of source/drain diffusions.
30) ∆Vth ( SCE ) = −θth ( SCE ) ⋅ (Vbi − Φ s ) with lt changed to BSIM4. ETA0.g.Threshold Voltage Model θth ( Leff ) = 0.6. To increase the model flexibility for different technologies. In BSIM4. and SCE and DIBL are modeled separately. DSUB. and ETAB are introduced.27) Xdep is larger near the drain due to the drain voltage.25) lt is referred to as the characteristic length and is given by lt = ε si ⋅ TOXE ⋅ X dep EPSROX ⋅η (2. Xdep /η represents the average depletion width along the channel. we use θth ( SCE ) = 0.5 ⋅ DVT 0 cosh DVT1⋅ ( Leff lt ) −1 (2. Leff < LMIN). DVT1. DVT2. several parameters such as DVT0.5 cosh ( ) −1 Leff lt (2.4 Manual Copyright © 2009 UC Berkeley 15 .29) (2.28) which results in a phantom second Vth rollup when Leff becomes very small (e.26) with the depletion width Xdep equal to X dep = 2ε si ( Φ s − Vbs ) qNDEP (2. Note that in BSIM3v3 and [4]. To model SCE. the function form of (2.25) is implemented with no approximation. θth(Leff) is approximated with the form of θth ( Leff ) = exp − Leff 2lt Leff + 2 exp − lt (2.
we use θth ( DIBL ) = cosh DSUB ⋅ ( 0. DVT2 and ETAB account for substrate bias effects on SCE and DIBL.4 Manual Copyright © 2009 UC Berkeley 16 .35) DVT1 is basically equal to 1/η.33) ∆Vth ( DIBL ) = −θth ( DIBL ) ⋅ ( ETA0 + ETAB ⋅ Vbs ) ⋅ Vds and lt0 is calculated by lt 0 = ε si ⋅ TOXE ⋅ X dep 0 EPSROX (2.5 Leff lt 0 ) −1 (2. The net result is an increase in Vth.36) BSIM4. This effect becomes very substantial as the channel width decreases and the depletion region underneath the fringing field becomes comparable to the "classical" depletion layer formed from the vertical field. 2.max 2 2CoxeWeff = 3π TOXE Φs Weff (2. respectively. This increase can be modeled as π qNDEP ⋅ X dep .Threshold Voltage Model lt = ε si ⋅ TOXE ⋅ X dep EPSROX ⋅ (1 + DVT 2 ⋅ Vbs ) (2.31) To model DIBL.34) with X dep 0 = 2ε si Φ s qNDEP (2.32) (2.6.5 NarrowWidth Effect The actual depletion region in the channel is always larger than what is usually assumed under the onedimensional analysis due to the existence of fringing fields.
Threshold Voltage Model This formulation includes but is not limited to the inverse of channel width due to the fact that the overall narrow width effect is dependent on process (i.39) The complete Vth model implemented in SPICE is (2.6.ln L + DVTP0.40) Vth = VTH 0 + K1ox ⋅ Φ s − Vbseff − K1⋅ Φ s ( ) 1+ LPEB − K 2 oxVbseff Leff LPE 0 TOXE + K1ox 1 + − 1 Φ s + ( K 3 + K 3B ⋅ Vbseff ) Φs Leff Weff '+ W 0 DVT 0W DVT 0 (V − Φ ) − 0. isolation technology).5 − ( ETA0 + ETAB ⋅Vbseff ) ⋅Vds − nvt .5 ⋅ DVT 0W Leff Weff ' ltw ) −1 ⋅ (Vbi − Φ s ) (2.5 ⋅ + s cosh DVT 1W Leff Weff ' − 1 cosh DVT 1 Leff − 1 bi ltw lt L 0. we must consider the narrow width effect for small channel lengths. Vth change is given by ∆Vth ( Narrow− width1) = ( K 3 + K 3B ⋅ Vbs ) TOXE Φs Weff '+ W 0 (2.width2 ) = − cosh DVT 1W ⋅ ( 0.e.38) with ltw given by ltw = ε si ⋅ TOXE ⋅ X dep EPSROX ⋅ (1 + DVT 2W ⋅ Vbs ) (2. To do this we introduce the following ∆Vth ( Narrow.37) In addition.eff1 + e− DVTP1⋅VDS Leff eff cosh DSUB lt 0 − 1 ( ) ( ) ( ) ( ) where TOXE dependence is introduced in model parameters K1 and K2 to improve the scalability of Vth model over TOXE as BSIM4.4 Manual Copyright © 2009 UC Berkeley 17 .
44) For positive Vbs.42) Note that all Vbs terms are substituted with a Vbseff expression as shown in (2.5 0.0.Threshold Voltage Model K1ox = K1⋅ TOXE TOXM (2. Vbseff = Vbc + 0.4 Manual Copyright © 2009 UC Berkeley 18 . and Vbc is the maximum allowable Vbs and found from dVth/dVbs= 0 to be K12 Vbc = 0. there is need to set an upper bound for the body bias as: (2.95Φ s − Vbseff − δ1 + ( 0.001V.5 ⋅ (Vbs − Vbc − δ1 ) + (Vbs − Vbc − δ1 ) 2 − 4δ1 ⋅ Vbc (2.95Φ s − 0.6.41) and K 2 ox = K 2 ⋅ TOXE TOXM (2.43).95Φ s BSIM4.45) ' Vbseff = 0.9 Φ s − 4 K 22 (2.95Φ s 2 ' − Vbseff − δ1 ) + 4δ1.43) where δ1 = 0. This is needed in order to set a low bound for the body bias during simulations since unreasonable values can occur during SPICE iterations if this expression is not introduced.
Channel Charge and Substhreshold Swing Models
Chapter 3: Channel Charge and Subthreshold Swing Models
3.1 Channel Charge Model
The channel charge density in subthreshold for zero Vds is written as
Voff ' = VOFF + VOFFL Leff
(3.1)
where
Voff ' = VOFF + VOFFL Leff
(3.2)
VOFFL is used to model the length dependence of Voff’ on nonuniform channel doping profiles. In strong inversion region, the density is expressed by
Qchs 0 = Coxe ⋅ (Vgse − Vth )
(3.3)
A unified charge density model considering the charge layer thickness effect is derived for both subthreshold and inversion regions as
Qch 0 = Coxeff ⋅ Vgsteff
(3.4)
where Coxeff is modeled by
Coxeff = Coxe ⋅ Ccen Coxe + Ccen with Ccen =
ε si
X DC
(3.5)
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Channel Charge and Substhreshold Swing Models and XDC is given as
X DC = ADOS × 1.9 × 10−9 m V + 4 (VTH 0 − VFB − Φ s ) 1 + gsteff 2TOXP
0.7× BDOS
(3.6)
Here, ADOS and BDOS are the parameters to describe the density of states in new materials and used to control the charge centroid. In the above equations, Vgsteff the effective (VgseVth) used to describe the channel charge densities from subthreshold to strong inversion, is modeled by
m∗ (Vgse − Vth ) nvt ln 1 + exp nvt = ∗ (1 − m ) (Vgse − Vth ) − Voff 2Φ s exp − m∗ + nCoxe ⋅ qNDEPε si nvt
(3.7)
'
Vgsteff
where
m∗ = 0.5 + arctan ( MINV )
(3.8)
π
MINV is introduced to improve the accuracy of Gm, Gm/Id and Gm2/Id in the moderate inversion region. To account for the drain bias effect, The y dependence has to be included in (3.4). Consider first the case of strong inversion
Qchs ( y ) = Coxeff ⋅ (Vgse − Vth − AbulkVF ( y ) )
(3.9)
VF(y) stands for the quasiFermi potential at any given point y along the channel with respect to the source. (3.9) can also be written as
Qchs ( y ) = Qchs 0 + ∆Qchs ( y )
(3.10)
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Channel Charge and Substhreshold Swing Models The term Qchs(y) = CoxeffAbulkVF(y) is the incremental charge density introduced by the drain voltage at y. In subthreshold region, the channel charge density along the channel from source to drain can be written as
A V ( y) Qchsubs ( y ) = Qchsubs 0 ⋅ exp − bulk F nvt
(3.11)
Taylor expansion of (3.11) yields the following (keeping the first two terms)
A V ( y) Qchsubs ( y ) = Qchsubs 0 1 − bulk F nvt
(3.12)
Similarly, (3.12) is transformed into
Qchsubs ( y ) = Qchsubs 0 + ∆Qchsubs ( y )
(3.13)
where Qchsubs(y) is the incremental channel charge density induced by the drain voltage in the subthreshold region. It is written as
∆Qchsubs ( y ) = −Qchsubs 0 ⋅ AbulkVF ( y ) nvt
(3.14)
To obtain a unified expression for the incremental channel charge density Qch(y) induced by Vds, we assume Qch(y) to be
∆Qch ( y ) = ∆Qchs ( y ) ⋅ ∆Qchsubs ( y ) ∆Qchs ( y ) + ∆Qchsubs ( y )
(3.15)
Substituting Qch(y) of (3.13) and (3.14) into (3.15), we obtain
∆Qch ( y ) = − VF ( y ) Qch 0 Vb
(3.16)
where Vb = (Vgsteff + nvt) / Abulk. In the model implementation, n of Vb is replaced by a typical constant value of 2. The expression for Vb now becomes
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21
19).4 Manual Copyright © 2009 UC Berkeley 22 . written as Cdsc−Term = ( CDSC + CDSCD ⋅Vds + CDSCB ⋅ Vbseff ) ⋅ cosh DVT1 ( 0. Experimental data shows that the subthreshold swing is a function of channel length and the interface state density. These two mechanisms are modeled by the following n = 1 + NFACTOR ⋅ Cdep Coxe + Cdsc−Term + CIT Coxe (3. which determines the channel current at Vgs = 0.21) where CdscTerm.18) 3.Channel Charge and Substhreshold Swing Models Vb = Vgsteff + 2vt Abulk (3. In (3.22) BSIM4.20) vt is the thermal voltage and equal to kBT/q.2 Subthreshold Swing n The drain current equation in the subthreshold region can be expressed as V Vgs − Vth − Voff ' I ds = I 0 1 − exp − ds ⋅ exp nvt vt (3.6. n is the subthreshold swing parameter.17) A unified expression for Qch(y) from subthreshold to strong inversion regions is V ( y) Qch ( y ) = Coxeff ⋅Vgsteff ⋅ 1 − F Vb (3. Voff’ = VOFF + VOFFL / Leff is the offset voltage.19) where I0 = µ W L qε si NDEP 2 vt 2Φ s (3.5 Leff lt ) −1 (3.
21). BSIM4.6. CDSCD and CDSCB are extracted.4 Manual Copyright © 2009 UC Berkeley 23 . it can be seen that subthreshold swing shares the same exponential dependence on channel length as the DIBL effect. Parameters CDSC.Channel Charge and Substhreshold Swing Models represents the coupling capacitance between drain/source to channel. From (3. Parameter NFACTOR is close to 1 and introduced to compensate for errors in the depletion width capacitance calculation. Parameter CIT is the capacitance due to interface states.
To reduce the tunneling current. depending on (the type of the gate and) the bias regime.4 Manual Copyright © 2009 UC Berkeley 24 . either from the conduction band or valence band. Figure 4. The BSIM4 gate tunneling model has been shown to work for multilayer gate stacks as well. This tunneling happens between the gate and silicon beneath the gate oxide.1 shows the schematic gate tunneling current flows.Gate Direct Tunneling Current Model Chapter 4: Gate Direct Tunneling Current Model As the gate oxide thickness is scaled down to 3nm and below. which is partitioned between the source and drain terminals by Igc = Igcs + Igcd. In BSIM4. highk dielectrics are being studied to replace gate oxide. The tunneling carriers can be either electrons or holes. multilayer dielectric stacks are being proposed.6. BSIM4. gate leakage current due to carrier direct tunneling becomes important. In order to maintain a good interface with substrate. or both. and the current between gate and channel (Igc). The third component happens between gate and source/drain diffusion regions (Igs and Igd). the gate tunneling current components include the tunneling current between gate and substrate (Igb).
1.5 (V fbzb − Vgb − 0.1) (4. 2 turns on Igc.02 ) + (V fbzb 2 − Vgb − 0. following Vt (= kT/q) will be replaced by Vtnom(=kTnom/q) 4. When the selectors are set to zero.2) are valid and continuous from accumulation through depletion to inversion. 4.2) Voxdepinv = K1ox Φ s + Vgsteff (4. and Igd.3) and VFBeff = V fbzb − 0.4 Manual Copyright © 2009 UC Berkeley 25 .Gate Direct Tunneling Current Model Figure 4. Igs. Vfbzb is the flatband voltage calculated from zerobias Vth by V fbzb = Vth zeroVbs and Vds − Φ s − K1 Φ s (4.6. igcMod = 1.4) BSIM4.2 Voltage Across Oxide Vox The oxide voltage Vox is written as Vox = Voxacc + Voxdepinv with Voxacc = V fbzb − VFBeff (4. no gate tunneling currents are modeled.1 Model Selectors Two global selectors are provided to turn on or off the tunneling components. When tempMod = 2.1) and (4.02 ) + 0. Shematic gate current components flowing between nMOSFET terminals in version.08V fbzb (4. igbMod = 1 turns on Igb.
5. When tempMod=0.7) Igbinv.75956e7 A/V2. B = 9.Gate Direct Tunneling Current Model 4.45669e11 (g/Fs2)0. or 1.97232e7 A/V2.5.3. B = 7. 4. determined by ECB (Electron tunneling from Conduction Band). and TOXREF ToxRatio = TOXE NTOX ⋅ 1 TOXE 2 (4.1 GatetoSubstrate Current (Igb = Igbacc + Igbinv) Igbacc. and BSIM4. nominal temperature (TNOM) is used to replace the operating temperature in following gate tunneling current equations.6.3 Equations for Tunneling Currents Note: when tempMod = 2. determined by EVB (Electron tunneling from Valence Band).82222e11 (g/Fs2)0. is significant in accumulation and given by I gbacc = Weff Leff ⋅ A ⋅ ToxRatio ⋅ Vgb ⋅ Vaux ⋅ exp − B ⋅ TOXE ( AIGBACC − BIGBACC ⋅ Voxacc ) ⋅ (1 + CIGBACC ⋅ Voxacc ) (4.4 Manual Copyright © 2009 UC Berkeley 26 .5) where the physical constants A = 4. is significant in inversion and given by I gbinv = Weff Leff ⋅ A ⋅ ToxRatio ⋅ Vgb ⋅Vaux ⋅ exp − B ⋅ TOXE ( AIGBINV − BIGBINV ⋅Voxdepinv ) ⋅ (1 + CIGBINV ⋅ Voxdepinv ) (4.8) where A = 3. operating temperature is still used.6) Vgb − V fbzb Vaux = NIGBACC ⋅ vt ⋅ log 1 + exp − NIGBACC ⋅ vt (4.
2 GatetoChannel Current (Igc0) and GatetoS/D (Igs and Igd) Igc0.4 Manual Copyright © 2009 UC Berkeley 27 . Igs and Igd are determined by ECB for NMOS and HVB for PMOS.11) for igcMod = 2: Vgse − VTH Vaux = NIGC ⋅ vt ⋅ log 1 + exp NIGC ⋅ vt (4.Gate Direct Tunneling Current Model − EIGBINV V Vaux = NIGBINV ⋅ vt ⋅ log 1 + exp oxdepinv NIGBINV ⋅ vt (4.97232 A/V2 for NMOS and 3. and for igcMod = 1: Vgse − VTH 0 Vaux = NIGC ⋅ vt ⋅ log 1 + exp NIGC ⋅ vt (4.16645e12 (g/Fs2)0.45669e11 (g/Fs2)0.9) 4.5 for PMOS.5 for NMOS and 1.42537 A/V2 for PMOS. while Igd represents the gate tunneling current between the gate and the drain diffusion region.3.10) where A = 4. respectively. is formulated as Igc0 = Weff Leff ⋅ A ⋅ ToxRatio ⋅ Vgse ⋅Vaux ⋅ exp − B ⋅ TOXE ( AIGC − BIGC ⋅ Voxdepinv ) ⋅ (1 + CIGC ⋅Voxdepinv ) (4.Igs represents the gate tunneling current between the gate and the source diffusion region.6. I gs = Weff DLCIG ⋅ A ⋅ ToxRatioEdge ⋅Vgs ⋅Vgs ' ⋅ exp − B ⋅ TOXE ⋅ POXEDGE ⋅ ( AIGS − BIGS ⋅ Vgs ' ) ⋅ (1 + CIGS ⋅ Vgs ' ) (4.12) Igs and Igd . determined by ECB for NMOS and HVB (Hole tunneling from Valence Band) for PMOS at Vds=0. B = 7.13) and BSIM4.
Partition of Igc To consider the drain bias effect.16) (4.18) Else Vfbsd = 0.45669e11 (g/Fs2)0.97232 A/V2 for NMOS and 3.4 Manual Copyright © 2009 UC Berkeley 28 .0e − 4 2 (4.5 for NMOS and 1.17) (V gd Vfbsd is the flatband voltage between gate and S/D diffusions calculated as If NGATE > 0. and ToxRatioEdge TOXREF = TOXE ⋅ POXEDGE NTOX ⋅ 2 1 (4.42537 A/V2 for PMOS.19) and BSIM4.15) 2 (TOXE ⋅ POXEDGE ) Vgs ' = Vgd ' = (V gs − V fbsd ) + 1. that is Igc = Igcs + Igcd.6.5 for PMOS. and Igcs = Igc0 ⋅ PIGCD ⋅Vdseff + exp ( − PIGCD ⋅ Vdseff ) − 1 + 1. Igc is split into two components.0e − 4 PIGCD 2 ⋅Vdseff 2 + 2.0e − 4 − V fbsd ) + 1.16645e12 (g/Fs2)0.0e − 4 (4. 4.0 V fbsd = k BT NGATE log + VFBSDOFF q NSD (4. Igcs and Igcd.3.0.Gate Direct Tunneling Current Model I gd = Weff DLCIGD ⋅ A ⋅ ToxRatioEdge ⋅ Vgd ⋅ Vgd ' ⋅ exp − B ⋅ TOXE ⋅ POXEDGE ⋅ ( AIGD − BIGD ⋅Vgd ' ) ⋅ (1 + CIGD ⋅ Vgd ' ) (4.3. B = 7.14) where A = 4.
6.21) BSIM4. If the model parameter PIGCD is not specified.0e − 4 (4.4 Manual Copyright © 2009 UC Berkeley 29 .0e − 4 PIGCD 2 ⋅Vdseff 2 + 2. it is given by PIGCD = Vdseff B ⋅ TOXE 1 − 2 Vgsteff 2 ⋅Vgsteff (4.20) where Igc0 is Igc at Vds=0.Gate Direct Tunneling Current Model Igcd = Igc0 ⋅ 1 − ( PIGCD ⋅ Vdseff + 1) ⋅ exp ( − PIGCD ⋅ Vdseff ) + 1.
4 Manual Copyright © 2009 UC Berkeley 30 .1 Bulk Charge Effect The depletion width will not be uniform along channel when a nonzero Vds is applied.2) Note that Abulk is close to unity if the channel length is small and increases as the channel length increases. This effect is called bulk charge effect. BSIM4 uses Abulk to model the bulk charge effect.2 Unified Mobility Model mrtlMod=0 BSIM4.1) A0 ⋅ Leff ⋅ Leff + 2 XJ ⋅ X dep = 1 + F− doping ⋅ Leff 1 − AGS ⋅ Vgsteff Leff + 2 XJ ⋅ X dep 1 ⋅ 2 B0 1 + KETA ⋅ Vbseff + Weff '+ B1 Abulk where the second term on the RHS is used to model the effect of nonuniform doping profiles F− doping = 1 + LPEB Leff K1ox 2 Φ s − Vbseff + K 2 ox − K 3B TOXE Φs Weff '+ W 0 (5.6. Several model parameters are introduced to account for the channel length and width dependences and bias effects.Drain Current Model Chapter 5: Drain Current Model 5. Abulk is formulated by (5. 5. This will cause Vth to vary along the channel.
The mobMod = 0 and 1 models are from BSIM3v3. a universal mobility model.4) For an NMOS transistor with ntype polysilicon gate. threshold voltage.Drain Current Model A good mobility model is critical to the accuracy of a MOSFET model.3) can be rewritten in a more useful form that explicitly relates Eeff to the device parameters Eeff ≈ Vgs + Vth 6TOXE (5. BSIM4. mobility depends on the gate oxide thickness. [5] proposed an empirical unified formulation based on the concept of an effective field Eeff which lumps many process parameters and bias conditions together. (6. phonon scattering is generally the dominant scattering mechanism at room temperature. mobility depends on many process parameters and bias conditions.3) The physical meaning of Eeff can be interpreted as the average electric field experienced by the carriers in the inversion layer.2. For good quality interfaces. is more accurate and suitable for predictive modeling. Eeff is defined by Eeff = QB + Qn / 2 ε si (5. substrate doping concentration. the new mobMod = 2. and surface roughness. The scattering mechanisms responsible for surface mobility basically include phonons. The unified formulation of mobility is then given by µeff = µ0 1 + ( Eeff / E0 ) v (5. coulombic scattering. etc.6.4 Manual Copyright © 2009 UC Berkeley 31 .5) BSIM4 provides three different models of the effective mobility. For example. gate and substrate voltages. In general.2.
Drain Current Model mobMod = 0 (5.6)
µeff =
U0⋅ f (Leff )
2 Vgsteff + 2Vth Vgsteff + 2Vth Vth ⋅TOXE 1+ (UA +UCVbseff ) +UB +UD V + 2 V 2 + 0.0001 TOXE TOXE th gsteff 2
mobMod = 1 (5.7)
µeff =
U0⋅ f (Leff )
2 Vgsteff + 2Vth Vgsteff + 2Vth Vth ⋅TOXE 1+ UA +UB (1+UC ⋅Vbseff ) +UD 2 TOXE TOXE Vgsteff + 2 Vth + 0.0001 2
mobMod = 2 (5.8)
µeff =
U0⋅ f ( Leff )
EU Vgsteff + C0 ⋅ (VTHO −VFB −Φs ) Vth ⋅TOXE 1+ (UA+UC ⋅Vbseff ) +UD Vgsteff + 2 Vth2 + 0.0001 TOXE
where the constant C0 = 2 for NMOS and 2.5 for PMOS.
Leff f ( Leff ) = 1 − UP ⋅ exp − LP
(5.9)
mrtlMod=1 A new expression of the vertical field in channel is adopted: (5.10)
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
32
Drain Current Model
Eeff =
Vgsteff + 2Vth − 2 ⋅ BSIM 4type ⋅ ( PHIG − EASUB − Eg / 2 + 0.45) EOT
⋅
3.9 EPSRSUB
Thus the mobility model is modified as following: mobMod=0
µeff =
U 0 ⋅ f ( Leff ) Vth ⋅ EOT 2 1 + (UA + UC ⋅ Vbseff ) Eeff + UB ⋅ Eeff + UD 2 V gsteff + 2 Vth + 0.00001
2
(5.11)
mobMod=1
µeff =
U 0 ⋅ f ( Leff ) Vth ⋅ EOT 2 1 + (UA ⋅ Eeff + UB ⋅ Eeff )(1 + UC ⋅ Vbseff )UD 2 V + 2 Vth + 0.00001 gsteff
2
(5.12)
Note: There is no changes in mobMod=2 when mtrlMod=1. BSIM4.6.2 introduces a new model to predict the mobility in high k/metal gate structure, in which Coulombic scattering is important. mobMod=3
µ eff =
V gsteff + C 0 .(VTH 0 − V fb − Φ S ) 1 + (UA + UC.Vbseff ) 6.TOXE U 0. f (Leff
)
(5.13)
EU
+
0.5 1 + V gsteff / V gsteff ,Vth
[
UD
]
UCS
Here, Vgsteff,Vth=Vgsteff(Vgse=Vth,Vds=Vbs=0).
5.3 Asymmetric and BiasDependent Source/ Drain Resistance Model
BSIM4 models source/drain resistances in two components: biasindependent diffusion resistance (sheet resistance) and biasdependent LDD resistance. Accurate modeling of the biasdependent LDD resistances is
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
33
Drain Current Model important for deepsubmicron CMOS technologies. In BSIM3 models, the LDD source/drain resistance Rds(V) is modeled internally through the IV equation and symmetry is assumed for the source and drain sides. BSIM4 keeps this option for the sake of simulation efficiency. In addition, BSIM4 allows the source LDD resistance Rs(V) and the drain LDD resistance Rd(V) to be external and asymmetric (i.e. Rs(V) and Rd(V) can be connected between the external and internal source and drain nodes, respectively; furthermore, Rs(V) does not have to be equal to Rd(V)). This feature makes accurate RF CMOS simulation possible. The internal Rds(V) option can be invoked by setting the model selector rdsMod = 0 (internal) and the external one for Rs(V) and Rd(V) by setting rdsMod = 1 (external). rdsMod = 0 (Internal Rds(V))
RDSWMIN + RDSW ⋅ Rds (V ) = 1 PRWB ⋅ Φ s − Vbseff − Φ s + 1 + PRWG ⋅ V gsteff
(
)
(1e6 ⋅W )
effcj
(5.14)
WR
rdsMod = 1 (External Rd(V) and Rs(V))
RDWMIN + RDW ⋅ Rd (V ) = 1 PRWB ⋅ Vbd + − 1 + PRWG ⋅ (Vgd − V fbsd ) RSWMIN + RSW ⋅ Rs (V ) = 1 − PRWB ⋅ Vbs + 1 + PRWG ⋅ V − V ( gs fbsd )
(5.15)
(1e6 ⋅ W ) effcj
WR
⋅ NF
(5.16)
(1e6 ⋅ W )WR ⋅ NF effcj
Vfbsd is the calculated flatband voltage between gate and source/drain as given in Section 4.3.2.
BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
34
17) where µne(y) can be written as µne ( y ) = µeff 1+ Ey Esat (5.6.4 Manual Copyright © 2009 UC Berkeley 35 .16). we get V ( y ) µeff dVF ( y ) I ds ( y ) = WQch 0 1 − F E Vb dy 1+ y Esat (5.19) BSIM4.Drain Current Model The following figure shows the schematic of source/drain resistance connection for rdsMod = 1. The diffusion source/drain resistance Rsdiff and Rddiff models are given in the chapter of layoutdependence models.18) Substituting (6.17) in (6.4 Drain Current for Triode Region Rds(V)=0 or rdsMod=1 (“intrinsic case”) Both drift and diffusion currents can be modeled by I ds ( y ) = WQch ( y ) µne ( y ) dVF ( y ) dy (5. 5.
6.4 Manual Copyright © 2009 UC Berkeley 36 .23) BSIM4. In order to have a continuous velocity model at E = Esat.21) 5.18) is integrated from source to drain to get the expression for linear drain current.5 Velocity Saturation Velocity saturation is modeled by [5] v= µeff E 1 + E Esat E < Esat E ≥ Esat (5. This expression is valid from the subthreshold regime to the strong inversion regime V W µeff Qch 0Vds 1 − ds 2Vb = V L 1 + ds Esat L (5. Esat must satisfy Esat = 2VSAT µeff (5.20) I ds 0 Rds(V) > 0 and rdsMod=0 (“Extrinsic case”) The drain current in this case is expressed by I ds = I ds 0 R I 1 + ds ds 0 Vds (5.Drain Current Model (6.22) = VSAT where Esat corresponds to the critical electrical field at which the carrier velocity becomes saturated.
Drain Current Model 5.27) c = (Vgsteff + 2vt ) Esat Leff + 2 (Vgsteff + 2vt ) Weff VSATCoxe Rds 2 (5. the LDD source/drain resistances are either zero or non zero but not modeled inside the intrinsic channel region.24) 5. It is easy to obtain Vdsat as [7] Vdsat = Esat L(Vgsteff + 2vt ) Abulk Esat L + Vgsteff + 2vt (5.26) (5.1 Intrinsic case In this case. BSIM4.6.28) (5.2 Extrinsic Case In this case.29) λ = A1Vgsteff + A2 λ is introduced to model the nonsaturation effects which are found for PMOSFETs.6.4 Manual Copyright © 2009 UC Berkeley 37 .25) where 1 a = Abulk 2Weff VSATCoxe Rds + Abulk − 1 λ 2 (Vgsteff + 2vt ) λ − 1 + Abulk Esat Leff b = − +3 Abulk (Vgsteff + 2vt ) Weff VSATCoxe Rds (5. nonzero LDD source/drain resistance Rds(V) is modeled internally through the IV equation and symetry is assumed for the source and drain sides. Vdsat is obtained as [7] Vdsat = −b − b 2 − 4ac 2a (5.6.6 Saturation Voltage Vdsat 5.
and SCBE in the fourth region.4 Manual Copyright © 2009 UC Berkeley 38 . The output resistance is very small because the drain current has a strong dependence on the drain voltage.6. Considering only the channel current. DIBL in the third region. The first order derivative reveals more detailed information about the physical mechanisms which are involved in the device operation. The first region is the triode (or linear) region in which carrier velocity is not saturated. is used to ensure a smooth transition near Vdsat from trode to saturation regions.7 SaturationRegion Output Conductance Model A typical IV curve and its output resistance are shown in Figure 6.1. there are several physical mechanisms which affect the output resistance in the saturation region: channel length modulation (CLM).6. BSIM4. Vdseff. and the substrate current induced body effect (SCBE). It will be shown next that CLM dominates in the second region. The other three regions belong to the saturation region.30) where δ (DELTA) is a model parameter.Drain Current Model 5. the IV curve can be divided into two parts: the linear region in which the current increases quickly with the drain voltage and the saturation region in which the drain current has a weaker dependence on the drain voltage. Vdseff is formulated as 1 Vdseff = Vdsat − (Vdsat − Vds − δ ) + 2 (Vdsat − Vds − δ ) 2 + 4δ ⋅ Vdsat (5.3Vdseff Formulation An effective Vds. draininduced barrier lowering (DIBL). These mechanisms all affect the output resistance in the saturation range. but each of them dominates in a specific region. The output resistance curve can be divided into four regions with distinct Rout~Vds dependences. As will be discussed later. 5.
Vds ) ∂Vd Vdsat ⋅ dVd (5.1 General behavior of MOSFET output resistance.31) Vds 1 = I dsat (Vgs . the Early voltage is introduced for the analysis of the output resistance in the saturation region: I ds (Vgs . But the current depends on the drain voltage weakly in the saturation region. Vds ) VA = I dsat ⋅ ∂Vd −1 (5.32) BSIM4.Drain Current Model Figure 5. Vdsat ) + ∫ Vds ∂I ds (Vgs . Vds ) = I dsat (Vgs . The channel current is a function of the gate and drain voltage.6. Vdsat ) ⋅ 1 + ∫ ⋅ dVd Vdsat V A where the Early voltage VA is defined as ∂I ds (Vgs .4 Manual Copyright © 2009 UC Berkeley 39 . In the following.
35) and the F factor to account for the impact of pocket implant technology is F= 1 1 + FPROUT ⋅ Leff Vgsteff + 2vt (5.7.Drain Current Model We assume in the following analysis that the contributions to the Early voltage from all mechanisms are independent and can be calculated separately.4 Manual Copyright © 2009 UC Berkeley 40 . 5.36) and litl in (6. the Early voltage can be calculated by VACLM ∂I ds (Vgs .37) PCLM is introduced into VACLM to compensate for the error caused by XJ since the junction depth XJ cannot be determined very accurately.34) is given by litl = ε siTOXE ⋅ XJ EPSROX (5.6.7.34) Cclm = Vgsteff 1 ⋅ F ⋅ 1 + PVAG PCLM Esat Leff Rds ⋅ I dso V 1 + Leff + dsat Vdseff Esat 1 ⋅ litl (5.33) Based on quasi twodimensional analysis and through integration. we propose VACLM to be VACLM = Cclm ⋅ (Vds − Vdsat ) where (5.1 Channel Length Modulation (CLM) If channel length modulation is the only physical mechanism to be taken into account. Vds ) ∂L = I dsat ⋅ ⋅ ∂L ∂Vd −1 (5.2 DrainInduced Barrier Lowering (DIBL) The Early voltage VADIBLC due to DIBL is defined as BSIM4. 5.
it will not cause any significant change. VADIBLC decreases very quickly (5. but a separate set of parameters are used: θ rout = PDIBLC1 2 cosh ( DROUT ⋅ Leff lt 0 )−2 + PDIBLC 2 (5. 5. Vds ) ∂V = I dsat ⋅ ⋅ th ∂Vth ∂Vd −1 (5. PDIBLC2.1MV/cm).4 Manual Copyright © 2009 UC Berkeley 41 .7. PDIBLCB and DROUT are introduced to correct the DIBL effect in the strong inversion region.40) Parameters PDIBLC1. If PDIBLC2 is put into the threshold voltage model. some electrons coming from the source (in the case of NMOSFETs) will be BSIM4.6. the gate voltage is much larger than the threshold voltage. the gate voltage is equal to the threshold voltage. because PDIBLC2 will be dominant if the channel is long. The reason why DVT0 is not equal to PDIBLC1 and DVT1 is not equal to DROUT is because the gate voltage modulates the DIBL effect.3 Substrate Current Induced Body Effect (SCBE) When the electrical field near the drain is very large (> 0.39) VADIBL = θ rout (1 + PDIBLCB ⋅ Vbseff Vgsteff + 2vt AbulkVdsat 1 − ) AbulkVdsat + Vgsteff + 2vt Vgsteff ⋅ 1 + PVAG Esat Leff where θrout has a similar dependence on the channel length as the DIBL effect in Vth. As channel length decreases.Drain Current Model ∂I ds (Vgs . But in the saturation region where the output resistance is modeled. PDIBLC2 is usually very small.38) VADIBL Vth has a linear dependence on Vds. Drain induced barrier lowering may not be the same at different gate bias. However it is an important parameter in VADIBLC for long channel devices. When the threshold voltage is determined.
A well known Isub model [8] is I sub = B ⋅ litl Ai I ds (Vds − Vdsat ) exp − i Bi Vds − Vdsat (5.Drain Current Model energetic (hot) enough to cause impact ionization. In addition.6. We replace Bi with PSCBE2 and Ai/Bi with PSCBE1/Leff to get the following expression for VASCBE 1 VASCBE = PSCBE1⋅ litl PSCBE 2 exp − Leff Vds − Vdsat (5. The total drain current can now be expressed as follows I ds = I ds − w / o − Isub + I sub = I ds − w / o − Isub ⋅ 1 + Vds − Vdsat Bi Ai exp ( Bi ⋅litl Vds −Vdsat ) (5. The total drain current will change because it is the sum of the channel current as well as the substrate current. The substrate current Isub thus created during impact ionization will increase exponentially with the drain voltage.4 Manual Copyright © 2009 UC Berkeley 42 . The channel length and gate oxide dependence of VASCBE comes from Vdsat and litl.43) We can see that VASCBE is a strong function of Vds.42) The Early voltage due to the substrate current VASCBE can therefore be calculated by VASCBE = B ⋅ litl Bi exp i Ai Vds − Vdsat (5. This is why SCBE is important for devices with high drain voltage bias.44) BSIM4. we also observe that VASCBE is small only when Vds is large. Isub affects the drain current in two ways. This will generate electronhole pairs when these energetic electrons collide with silicon atoms.41) Parameters Ai and Bi are determined from measurement.
VAsat is needed to have continuous drain current and output resistance expressions at the transition point between linear and saturation regions.35). and VA is written as VA = VAsat + VACLM (5.47) where VAsat is A dsat Esat Leff + Vdsat + 2 Rds vsatCoxeWeff Vgsteff ⋅ 1 − 2(V bulkV+ 2v ) gsteff t = 2 Rds vsatCoxeWeff Abulk − 1 + λ (5.48) VAsat VAsat is the Early voltage at Vds = Vdsat.Drain Current Model 5. This barrier can be lowered by the drain bias even in longchannel devices. The Early voltage due to DITS is modeled by VADITS = 1 ⋅ F ⋅ 1 + (1 + PDITSL ⋅ Leff ) exp ( PDITSD ⋅ Vds ) PDITS (5.8 SingleEquation Channel Current Model The final channel current equation for both linear and saturation regions now becomes I ds = I ds 0 ⋅ NF I ds 1 + RVdsdseff 0 V 1 ln A 1 + Cclm VAsat Vds − V dseff ⋅ 1 + VASCBE (5. BSIM4.45) 5. In addition.7.4 Manual Copyright © 2009 UC Berkeley 43 .46) Vds − V dseff ⋅ 1 + VADIBL Vds − V dseff ⋅ 1 + VADITS where NF is the number of device fingers.6. the pocket implant introduces a potential barrier at the drain end of the channel. The Rout degradation factor F is given in (6.4 DrainInduced Threshold Shift (DITS) by Pocket Implant It has been shown that a longchannel device with pocket implant has a smaller Rout than that of uniformlydoped device [3].
51) OV E sat LAMBDA is the velocity overshoot coefficient. 5. An approximate nonlocal velocity field expression has proven to provide a good description of this effect v = vd (1 + λ ∂E E ∂x )= µE 1 + E / Ec (1 + λ ∂E E ∂x ) (5. the velocity overshoot has been observed to be a significant effect even though the supply voltage is scaled down according to the channel length.45) and the new current expression including the velocity overshoot effect is obtained: V I DS ⋅ 1 + dseff L E eff sat = V 1 + dseffOV Leff Esat (5.Drain Current Model 5.49) This relationship is then substituted into (6. As a result. the dc current is controlled by how rapidly carriers are transported across a short lowfield region near the beginning of BSIM4.6. carrier transport through the drain end of the channel is rapid.2 Source End Velocity Limit Model When MOSFETs come to nanoscale.9 New Current Saturation Mechanisms: Velocity Overshoot and Source End Velocity Limit Model 5.1 Velocity Overshoot In the deepsubmicron region.4 Manual Copyright © 2009 UC Berkeley 44 . HD where Vds − Vdseff 1 + Esat ⋅ litl LAMBDA = Esat 1 + ⋅ Leff ⋅ µeff Vds − Vdseff 1 + Esat ⋅ litl 2 − 1 2 + 1 (5.50) I DS .9. because of the high electric field and strong velocity overshoot.9.
so a final Unified current expression with velocity saturation. HD 1 + ( vsHD / vsBT )2 MM 1/ 2 MM (5. Source end velocity limit gives the highest possible velocity which can be given through ballistic transport as: vsBT = 1− r VTL 1+ r (5.0 (5.6.54) The real source end velocity should be the lower of the two.53) where VTL: thermal velocity.4 Manual Copyright © 2009 UC Berkeley 45 . r is the back scattering coefficient which is given: r= Leff XN ⋅ Leff + LC XN ≥ 3. HD Wqs (5. Hydrodynamic transportation gives the source end velocity as : vsHD = I DS .0.55) where MM=2. BSIM4. A compact model is firstly developed to account for this current saturation mechanism.52) where qs is the source end inversion charge density. This is known as injection velocity limits at the source end of the channel.Drain Current Model the channel. velocity overshoot and source velocity limit can be expressed as : I DS = I DS .
and gateinduced drain leakage and source leakage currents (IGIDL and IGISL). and is modeled by I ii = ALPHA0 + ALPHA1⋅ Leff Leff (V BETA0 ds − Vdseff ) exp V −V ds dseff ⋅ I dsNoSCBE (6.1 Iii Model The impact ionization current model in BSIM4 is the same as that in BSIM3v3. parameter ALPHA1 is introduced to improves the Iii scalability. the substrate terminal current consists of the substrate current due to impact ionization (Iii).2.2) 6.Body Current Models Chapter 6: Body Current Models In addition to the junction diode current and gatetobody tunneling current.1) where parameters ALPHA0 and BETA0 are impact ionization coefficients.4 Manual Copyright © 2009 UC Berkeley 46 . and I dsNoSCBE = V Vds − V dseff I ds 0 ⋅ NF 1 1+ ln A ⋅ 1 + Rds I ds 0 VADIBL 1 + Vdseff Cclm VAsat Vds − V dseff ⋅ 1 + VADITS (6.6. 6.2 IGIDL and IGISL Model mtrlMod=0 The GIDL/GISL current and its body bias effect are modeled by [9][10] I GIDL = AGIDL ⋅WeffCJ ⋅ Nf ⋅ Vds − Vgse − EGIDL 3 ⋅ Toxe (6.3) 3 Vdb 3 ⋅ Toxe ⋅ BGIDL ⋅ exp − ⋅ 3 Vds − Vgse − EGIDL CGIDL + Vdb BSIM4.
the work function difference (Vfbsd) between source/drain and channel could be modeled as follows: V fbsd = PHIG − ( EASUB + Eg 0 NSD Eg 0 − BSIM 4typy × MIN 2 . BGIDL. They are explained in Appendix A. WeffCJ and Nf are the effective width of the source/drain diffusions and the number of fingers.6.6) BSIM4.Body Current Models I GISL = AGISL ⋅ WeffCJ ⋅ Nf ⋅ −Vds − Vgde − EGISL 3 ⋅ Toxe (6. BGISL. CGIDL and CGISL account for the bodybias dependence of IGIDL and IGISL respectively. vt ln n 2 i (6.9 exp − ⋅ 3 Vds − Vgse − EGIDL + V fbsd CGIDL + Vdb (6.4) 3 Vsb 3 ⋅ Toxe ⋅ BGISL ⋅ exp − ⋅ 3 −Vds − Vgde − EGISL CGISL + Vsb where AGIDL.5) Moreover. the GIDL/GISL current should be modified as following: I GIDL = AGIDL ⋅ WeffCJ ⋅ Nf ⋅ Vds − Vgse − EGIDL + V fbsd EPSRSUB EOT ⋅ 3. CGISL and EGISL are the model parameters for the source side.9 EPSRSUB ⋅ BGIDL 3 EOT ⋅ Vdb 3. Further explanation of WeffCJ and Nf can be found in the chapter of the layoutdependence model. CGIDL and EGIDL are model parameters for the drain side and AGISL.4 Manual Copyright © 2009 UC Berkeley 47 . mtrlMod=1 In this case.
9 ⋅ exp − 3 Vds − Vgse − EGISL + V fbsd CGISL + Vdb (6.4 Manual Copyright © 2009 UC Berkeley 48 .9 EPSRSUB ⋅ BGISL 3 EOT ⋅ Vdb 3.Body Current Models I GIDS = AGISL ⋅ WeffCJ ⋅ Nf ⋅ Vds − Vgse − EGISL + V fbsd EPSRSUB EOT ⋅ 3.6.7) BSIM4.
singelequation and chargethickness model Matched capMod in BSIM3v3.2. These capacitance models come from BSIM3v3.Capacitance Model Chapter 7: Capacitance Model Accurate modeling of MOSFET capacitance plays equally important role as that of the DC model.wise model) capMod = 1 (singleequation model) capMod = 2 (default model. BSIM4.2 capMod = 1 is no longer supported in BSIM4.2 Intrinsic capMod = 0 + overlap/fringing capMod = 0 Intrinsic capMod = 2 + overlap/fringing capMod = 2 Intrinsic capMod = 3 + overlap/fringing capMod = 2 BSIM4 capacitance models have the following features: • Separate effective channel length and width are used for capacitance models.2 capacitance model parameters are used without change in BSIM4 except that separate CKAPPA parameters are introduced for the sourceside and drainside overlap capacitances.2. Complete model parameters can be found in Appendix A.0. The BSIM3v3.4 Manual Copyright © 2009 UC Berkeley 49 . This chapter describes the methodology and device physics considered in both intrinsic and extrinsic capacitance modeling in BSIM4. The following table maps the BSIM4 capacitance models to those of BSIM3v3. and the BSIM3v3.0.1 General Description BSIM4.6. 7.0. BSIM4 capacitance models capMod = 0 (simple and piece.0 provides three options for selecting intrinsic and overlap/fringing capacitance models.2.
1 Basic Formulation To ensure charge conservation. short/narrow channel and DIBL effects are explicitly considered in capMod = 1 and 2.Capacitance Model • capMod = 0 uses piecewise equations. accumulation charge (Qacc) and substrate depletion charge (Qsub).2. 7. bulk. Setting cvchargeMod = 1 activates the new Vgsteff. terminal charges instead of terminal voltages are used as state variables. Qb.CV calculation which is similar to the Vgsteff formulation in the IV model. where a longchannel Vth is used. • Overlap capacitance comprises two parts: (1) a biasindependent component which models the effective overlap capacitance between the gate and the heavily doped source/drain. and Qd are the charges associated with the gate. capMod = 1 and 2 are smooth and single equation models. • Biasindependent fringing capacitances are added between the gate and source as well as the gate and drain. Qs. BSIM4. The terminal charges Qg.4 Manual Copyright © 2009 UC Berkeley 50 . therefore both charge and capacitance are continous and smooth over all regions.6. • Threshold voltage is consistent with DC part except for capMod = 0. and drain termianls.2 Methodology for Intrinsic Capacitance Modeling 7. source. • A new threshold voltage definition is introduced to improve the fitting in subthreshold region. The gate charge is comprised of mirror charges from these components: the channel charge (Qinv). Therefore. (2) a gatebias dependent component between the gate and the lightly doped source/drain region. those effects such as body bias. respectively.
Capacitance Model The accumulation charge and the substrate charge are associated with the substrate while the channel charge comes from the source and drain terminals Qg = −(Qsub + Qinv + Qacc ) Qb = Qacc + Qsub Q = Q + Q s d inv (7.Vth and dy = dVy Ey (7. The threshold voltage along the channel is modified due to the nonuniform substrate charge by Vth ( y ) = Vth (0) + ( Abulk − 1)Vy Lactive Lactive Qc = Wactive ∫ qc dy = −WactiveCoxe ∫ (Vgt − AbulkVy ) dy 0 0 Lactive Lactive Qg = Wactive ∫ qg dy = WactiveCoxe ∫ (Vgt + Vth − VFB − Φ s − Vy ) dy 0 0 Lactive Lactive Qb = Wactive ∫ qb dy = −WactiveCoxe ∫ Vth − VFB − Φ s + ( Abulk − 1)Vy dy 0 0 (7.4) ( ) where Vgt = Vgse .3) (7.4 Manual Copyright © 2009 UC Berkeley 51 .1) The substrate charge can be divided into two components: the substrate charge at zero sourcedrain bias (Qsub0).5) where Ey is expressed in BSIM4.2) The total charge is computed by integrating the charge along the channel. which is a function of gate to substrate bias. Qg now becomes Qg = −(Qinv + Qacc + Qsub 0 + δ Qsub ) (7.6. and the additional nonuniform substrate charge in the presence of a drain bias (δQsub).
CV Abulk (7.6.6) All capacitances are derived from the charges to ensure charge conservation. IV < Vdsat .CV in general is larger than Vdsat for IV but smaller than the longchannel Vdsat = Vgt / Abulk.4 Manual Copyright © 2009 UC Berkeley 52 . for capacitance modeling.CV = Vgt / Abulk and therefore is independent of channel length. If we define a drain bias.7) where i and j denote the transistor terminals. Vdsat . the channel charge remains constant in saturation region.2 Short Channel Model cvchargeMod=0 The longchannel charge model assumes a constant mobility with no velocity saturation.Capacitance Model I ds = Wactive µeff Coxe Abulk Vds Vds = Wactive µeff Coxe (Vgt − AbulkVy ) E y Vgt − 2 Lactive (7. IV = Vgsteff . Conventional longchannel charge models assume Vdsat. Since there are four terminals.9) Lactive →∞ and Vdsat. Vdsat.CV. there are altogether 16 components. we will find that Vdsat. Since no channel length modulation is considered. Cij satisfies ∑C = ∑C ij i j ij =0 (7.2. In other words. at which the channel charge becomes constant.8) 7.CV < Vdsat .CV is modeled by BSIM4. For each component Cij = ∂Qi ∂V j (7.
CV = NOFF ⋅ nvt ⋅ ln 1 + exp NOFF ⋅ nvt (7.16) π VOFFCVL Leff Voff ' = VOFFCV + It is clear that this new definition is similar to Vgsteff in IV model.5 + arctan ( MINVCV ) (7. a new threshold voltage for CV is introduced as following: m* (Vgse − Vth ) 1 + exp nvt ln nvt 1 − m* (Vgse − Vth ) − Voff ' 2φs exp − qNDEPε Si nvt (7.Capacitance Model Vdsat .14) VgsteffCV = m* + nCoxe ( ) m* = 0.11) Model parameters CLC and CLE are introduced to consider the effect of channellength modulation.12) where F− doping = 1 + LPEB Leff K1ox 2 Φ s − Vbseff + K 2 ox − K 3B TOXE Φs Weff '+ W 0 (7.4 Manual Copyright © 2009 UC Berkeley 53 . BSIM4. Abulk for the capacitance model is modeled by A0 ⋅ Leff B0 1 ⋅ Abulk = 1 + F− doping ⋅ ⋅+ Leff + 2 XJ ⋅ X dep Weff '+ B1 1 + KETA ⋅ Vbseff (7.10) Vgse − Vth − VOFFCV Vgsteff .15) (7.CV CLC Abulk ⋅ 1 + Lactive CLE (7.6.CV = Vgsteff .13) cvchargeMod=1 In order to improve the predictive modeling in the subthreshold region.
CV ) ∂Vgsteff . Concurrently. s . 7. This can result in discontinuities and nonsmoothness at transition regions. The following describes singleequation formulation for charge.CV as Q (Vgst ) = Q (Vgsteff .17) For capacitance modeling C (Vgst ) = C (Vgsteff . The BSIM4 charge and capacitance models are formulated by substituting Vgst with Vgsteff.d .02 ) + (V fbzb 2 − Vgb − 0. the substrate capacitance drops abruptly to zero at threshold voltage. capacitance and voltage modeling in capMod = 1 and 2.08V fbzb (7.b (7.3 Single Equation Formulation Traditional MOSFET SPICE capacitance models use piecewise equations.19) where BSIM4.CV Vg .6.Capacitance Model Note: The default value of cvchargeMod is zero to keep the backward compatibility. since the substrate charge is a constant. VFBeff = V fbzb − 0. (a) Transition from depletion to inversion region The biggest discontinuity is at threshold voltage where the inversion capacitance changes abruptly from zero to Coxe.02 ) + 0.18) (b) Transition from accumulation to depletion region An effective smooth flatband voltage VFBeff is used for the accumulation and depletion regions.5 (V fbzb − Vgb − 0.4 Manual Copyright © 2009 UC Berkeley 54 .CV ) (7.2.
BSIM4. is used to smooth out the transition between linear and saturation regions.2. For capMod = 0.CV − Vds − δ 4 .6.Capacitance Model V fbzb = Vth zeroVbs and Vds − Φ s − K1 Φ s (7. Existing charge partitioning schemes are 0/100.Charge partitioning The inversion charges are partitioned into Qinv = Qs + Qd.5 and 0).02V { } (7.4. Vcveff. VFBCV is used instead (refer to Appendix A).20) A biasindependent Vth is used to calculate Vfbzb for capMod = 1 and 2.CV where V4 = Vdsat . The ratio of Qd to Qs is the charge partitioning ratio.21) 7.CV − 0.5 V4 + V4 2 + 4δ 4Vdsat . δ 4 = 0. (c) Transition from linear to saturation region An effective Vds. 40/60 charge partition This is the most physical model of the three partitioning schemes in which the channel charges are allocated to the source and drain terminals by assuming a linear dependence on channel position y. Vcveff = Vdsat . 0. 50/50 charge partition This is the simplest of all partitioning schemes in which the inversion charges are assumed to be contributed equally from the source and drain terminals.4 Manual Copyright © 2009 UC Berkeley 55 . 50/50 and 40/60 (XPART = 1.
Notice that this charge partitioning scheme will still give drain current spikes in the linear region and aggravate the source current spike problem. 7.6.Capacitance Model Lactive y Qs = Wactive ∫ qc 1 − Lactive 0 Lactive y Qd = Wactive ∫ qc dy Lactive 0 (7. Numerical quantum simulation results in Figure 8.1 indicate the significant charge thickness in all regions of operation. BSIM4.22) dy 0/100 charge partition In fast transient simulations. The discrepancy is more pronounced in thinner Tox devices due to the assumption of inversion and accumulation charge being located at the interface. This partitioning scheme is developed to artificially suppress the drain current spike by assigning all inversion charges in the saturation region to the source electrode. the use of a quasistatic model may result in a large unrealistic drain current spike.4 Manual Copyright © 2009 UC Berkeley 56 .3 ChargeThickness Capacitance Model (CTM) mtrlMod=0 Current MOSFET models in SPICE generally overestimate the intrinsic capacitance and usually are not smooth at Vfb and Vth.
23) where Ccen = ε si / X DC (7.24) BSIM4. XDC. The charge thickness introduces a capacitance in series with Cox as illustrated in Figure 7. Based on numerical selfconsistent solution of Shrődinger.4 Manual Copyright © 2009 UC Berkeley 57 . resulting in an effective Coxeff. Poisson and FermiDirac equations.1 Charge distribution from numerical quantum simulations show significant charge thickness at various bias conditions shown in the inset. Coxeff can be expressed as Coxeff = Coxp ⋅ Ccen Coxp + Ccen (7. CTM is a chargebased model and therefore starts with the DC charge thickness.6.Capacitance Model Figure 7.2 . universal and analytical XDC models have been developed.
(i) XDC for accumulation and depletion The DC charge thickness in the accumulation and depletion regions can be expressed by X DC −0.4 Manual Copyright © 2009 UC Berkeley 58 .25 V − V − VFBeff 1 NDEP = Ldebye exp ACDE ⋅ ⋅ gse bseff 16 3 TOXP 2 ×10 (7.25) where Ldebye is Debye length.2 Chargethickness capacitance concept in CTM. Vgse accounts for the poly depletion effect.Vbseff VFBeff) / TOXP is in units of MV/cm. (ii) XDC of inversion charge The inversion charge layer thickness can be formulated as BSIM4.27) and Xmax = Ldebye / 3.6. = 103TOXE. and XDC is in the unit of cm and (Vgse . For numerical stability.26) X DC = X max − 1 X 0 + X 02 + 4δ x X max 2 ( ) (7.25) is replaced by (8.26) where X 0 = X max − X DC − δ x (7. (8.Capacitance Model Figure 7.
the body charge thickness effect is modeled by including the deviation of the surface potential ФS (biasdependence) from 2 ФB [2] ϕδ = Φ s − 2Φ B = ν t ln 1 + VgsteffCV ⋅ (VgsteffCV + 2 K1ox 2Φ B MOIN ⋅ K1ox 2ν t (7. Their default values are one.32) BSIM4.29) The channel charge density is therefore derived as qinv = −Coxeff ⋅ (Vgsteff .4 Manual Copyright © 2009 UC Berkeley 59 .31) mtrlMod=1 First. (iii) Body charge thickness in inversion In inversion region.28) Here. Through the VFB term.9 × X DC V =VDDEOT .7× BDOS (7.6.28) is found to be applicable to N+ or P+ polySi gates and even other future gate materials.Capacitance Model X DC = ADOS × 1.CV − ϕδ ) eff (7. TOXP should be iteratively calculated by EOT as follows: TOXP = EOT − 3.30) where (7.9 × 10−9 m V + 4 (VTH 0 − VFB − Φ s ) 1 + gsteff 2TOXP 0.V =V =0 gs ds bs EPSRSUB (7. the density of states parameters ADOS and BDOS are introduced to control the charge centroid. equation (7.
4 Manual Copyright © 2009 UC Berkeley 60 .Capacitance Model X DC = ADOS × 1.1 capMod = 0 Accumulation region Qg = Wactive LactiveCoxe (Vgs − Vbs − VFBCV ) Qsub = −Qg (7.40) (7. 7. The other calculations are as same as mtrlMod=0.37) (7.39) Qinv = 0 Strong inversion region Vdsat .42) BSIM4.35) (7. Now Ccen is equal to EPSRSUB/XDC.4.6.41) CLC CLE Abulk ' = Abulk 1 + Leff Vth = VFBCV + Φ s + K1ox Φ s − Vbseff (7.34) (7.4 Intrinsic Capacitance Model Equations 7.cv = Vgs − Vth Abulk ' (7. XDC could be obtained at different gate voltage.36) Qinv = 0 Subthreshold region Qsub 0 4 (Vgs − VFBCV − Vbs ) K1ox 2 = −Wactive LactiveCoxe ⋅ −1 + 1 + 2 K1ox 2 Qg = −Qsub 0 (7.9 ×10−9 + (VTH 0 − VFB − φs ) V 1 + gsteff 2TOXP 0.7× BDOS (7.33) With the calculated TOXP.38) (7.
43) (7.46) 40/60 partitioning: (7.47) 2 (V −V ) A 'V (V −V ) A 'V 2 Abulk 'Vds gs 6 th − bulk ds8 gs th + ( bulk40 ds ) V −V A 'V Qd = −CoxeWactive Lactive gs th − bulk ds + Abulk 'Vds 2 2 2 12 Vgs − Vth − 2 ( ) Qs = − ( Qg + Qb + Qd ) (7.Capacitance Model Linear region V Abulk 'Vds 2 Qg = CoxeWactive Lactive Vgs − VFBCV − Φ s − ds + A 'V 2 12 Vgs − Vth − bulk ds 2 (7.6.48) BSIM4.4 Manual Copyright © 2009 UC Berkeley 61 .44) (1 − Abulk ')Vds − (1 − Abulk ') Abulk 'Vds 2 Qb = CoxeWactive Lactive VFBCV − Vth − Φ s + A 'V 2 12 Vgs − Vth − bulk ds 2 50/50 partitioning: A 'V Abulk '2 Vds 2 Qinv = −CoxeWactive Lactive Vgs − Vth − Φ s − bulk ds + A 'V 2 12 Vgs − Vth − bulk ds 2 Qs = Qd = 0.45) (7.5Qinv (7.
2 capMod = 1 Qg = − ( Qinv + Qacc + Qsub 0 + δ Qsub ) (7.4 Manual Copyright © 2009 UC Berkeley 62 .57) 7.Capacitance Model 0/100 partitioning: 2 Vgs − Vth A 'V ( Abulk 'Vds ) bulk ds + − Qd = −CoxeWactive Lactive 2 4 24 (7.56) (7.51) (7.55) Qs = − ( Qg + Qb + Qd ) 0/100 partitioning: Qd = 0 Qs = − ( Qg + Qb ) (7.53) 40/60 partitioning: Qd = − 4 CoxeWactive Lactive (Vgs − Vth ) 15 (7.52) (1 − Abulk ')Vdsat Qb = −CoxeWactive Lactive VFBCV + Φ s − Vth + 3 50/50 partitioning: 1 Qs = Qd = − CoxeWactive Lactive (Vgs − Vth ) 3 (7.50) Qs = − ( Qg + Qb + Qd ) Saturation region: V Qg = CoxeWactive Lactive Vgs − VFBCV − Φ s − dsat 3 (7.4.54) (7.58) BSIM4.6.49) (7.
62) (7.4 Manual Copyright © 2009 UC Berkeley 63 .cv − bulk cveff 2 (7. cv ( Abulk 'Vcveff ) − 2 3 15 3 ) (7.cv − 2 2 1 − A ' (1 − Abulk ') ⋅ Abulk 'Vcveff bulk = Wactive LactiveCoxe ⋅ Vcveff − A 'V 2 12 ⋅ Vgsteff .60) (7.cv = Vgsteffcv Abulk ' (7.cv − 2 (7.61) Qinv = Qs + Qd Qacc = −Wactive LactiveCoxe ⋅ (VFBeff − V fbzb ) Qsub 0 4 ( Vgse − VFBeff − Vgsteff − Vbseff ) K1ox 2 = − Wactive LactiveCoxe ⋅ ⋅ 1 + 1 + 2 K1ox 2 Vdsat .6.65) δ Qsub 50/50 charge partitioning: Wactive LactiveCoxe 2 2 2 Abulk ' Vcveff 1 Vgsteff .59) (7.67) BSIM4.63) (7.cv − Abulk 'Vcveff + Abulk 'Vcveff 2 12 ⋅ Vgsteff .cv − Abulk 'Vcveff + Abulk 'Vcveff 2 12 ⋅ Vgsteff .64) 2 Abulk '2 Vcveff 1 Qinv = − Wactive LactiveCoxe ⋅ Vgsteff .cv Abulk 'Vcveff 2 2 2 + 2 V ( Abulk 'Vcveff gsteff .cv − 3 Vgsteff .66) QS = QD = − 40/60 charge partitioning: QS = − Wactive LactiveCoxe A 'V 2 Vgsteff .Capacitance Model Qs = − ( Qg + Qb + Qd ) (7.cv − bulk cveff 4 3 2 Vgsteff .
77) Qsub 0 = − Wactive LactiveCoxeff ⋅ 4 ( Vgse − VFBeff − Vbseffs − Vgsteff .cv + Abulk 'Vcveff − Abulk 'Vcveff 2 12 ⋅ Vgsteff .08V fbzb 2 V0 = V fbzb + Vbseff − Vgs − 0.69) QS = − 2 Abulk '2 Vcveff Wactive LactiveCoxe 3 ⋅ Vgsteff .cv − 2 (7.CV − ϕδ − 0.CV − ϕδ − 0.02 1 Vcveff = Vdsat − ⋅ V1 + V12 + 0.3 capMod = 2 Qacc = Wactive LactiveCoxeff ⋅ Vgbacc (7.Capacitance Model 5 3 2 Vgsteff .cv Abulk 'Vcveff 2 2 1 + V gsteff .001) + (V gsteff .78) BSIM4.4.74) (7.cv ) K1ox 2 ⋅ 1 + 1 + K1ox 2 2 (7.6.70) 7.CV − ϕδ ) eff = 0.5 ⋅ (Vgsteff .72) (7.68) QD = − Wactive LactiveCoxe A 'V 2 Vgsteff .02 Vdsat = Vgsteff .73) 1 Vgbacc = ⋅ V0 + V02 + 0.cv ( Abulk 'Vcveff ) − 5 ( Abulk 'Vcveff 2 3 ) (7.76) (V gsteff .71) (7.08Vdsat 2 V1 = Vdsat − Vds − 0.cv − 3 Vgsteff .4 Manual Copyright © 2009 UC Berkeley 64 .001) + Vg 2 (7.cv − bulk cveff 0/100 charge partitioning: Wactive LactiveCoxe 2 2 2 Abulk ' Vcveff 1 ⋅ Vgsteff .cv − ϕδ Abulk ' ( ) (7.cv − 2 (7.75) (7.cv − Abulk 'Vcveff + QD = − Abulk 'Vdveff 2 2 4 ⋅ Vgsteff .
6.79) (7.cv − ϕδ )( Abulk 'Vcveff ) − 15 ( Abulk 'Vcveff 2 3 3 ) BSIM4.cv − ϕδ − bulk cveff 2 (7.cv − ϕδ ) Abulk 'Vcveff 3 2 2 2 + 2 V ( gsteff .81) 2 Wactive LactiveCoxeff Abulk '2 Vcveff 1 Vgsteff .cv − ϕδ ) − 4 (Vgsteff .cv − ϕδ − bulk cveff 3 2 (Vgsteff .Capacitance Model δ Qsub = Wactive LactiveCoxeff 2 1 − A ' (1 − Abulk ') ⋅ Abulk 'Vcveff bulk Vcveff − ⋅ A 'V 2 12 ⋅ Vgsteff .cv − ϕδ − Abulk 'Vcveff + QS = QD = − Abulk 'Vcveff 2 2 12 ⋅ (Vgsteff .4 Manual Copyright © 2009 UC Berkeley 65 .82) QS = − Wactive LactiveCoxeff A 'V 2 Vgsteff .cv − ϕδ ) − eff 2 40/60 partitioning: (7.80) (1 − Abulk ')Vds − (1 − Abulk ') Abulk 'Vds 2 Qb = CoxeWactive Lactive VFBCV − Vth − Φ s + A 'V 2 12 Vgs − Vth − bulk ds 2 50/50 partitioning: (7.
cv − ϕδ ) − Abulk 'Vcveff + QD = − eff Abulk 'Vdveff 2 2 4 ⋅ (Vgsteff .6.Capacitance Model (7. Only the biasindependent outer fringing capacitance (CF) is modeled. If CF is not given.cv − ϕδ ) − eff 2 7.cv − ϕδ ) Abulk 'Vcveff 2 2 1 + V ( gsteff .85) 2 Wactive LactiveCoxeff Abulk '2 Vcveff 3 ⋅ (Vgsteff .5.cv − ϕδ ) − 3 (Vgsteff . it is calculated by BSIM4.4 Manual Copyright © 2009 UC Berkeley 66 .5 Fringing/Overlap Capacitance Models 7.83) QD = − Wactive LactiveCoxeff A 'V 2 Vgsteff .1 Fringing capacitance model The fringing capacitance consists of a biasindependent outer fringing capacitance and a biasdependent inner fringing capacitance.cv − ϕδ )( Abulk 'Vcveff ) − 5 ( Abulk 'Vcveff 2 3 ) 0/100 partitioning: (7.cv − ϕδ + Abulk 'Vcveff − Abulk 'Vcveff 2 12 ⋅ Vgsteff .cv − ϕδ − 2 (7.84) QS = − Wactive LactiveCoxeff 2 2 2 Abulk ' Vcveff 1 ⋅ Vgsteff .cv − ϕδ − bulk cveff 3 2 5 (Vgsteff .
Since the modulation is expected to be very small. This LDD region can be in accumulation or depletion.2 Overlap capacitance model An accurate overlap capacitance model is essential. experimental data show that the overlap capacitance changes with gate to source and gate to drain biases. We use a single equation for both regions by using such smoothing parameters as Vgs. If capMod is nonzero.overlap and Cgd. Biasdependent overlap capacitance model (i) Source side BSIM4. This is especially true for the drain side where the effect of the capacitance is amplified by the transistor gain. otherwise. In other words.overlap. Unlike the case with the intrinsic capacitance.overlap = Csg. the overlap capacitances are reciprocal.overlap for the source and drain side.4 Manual Copyright © 2009 UC Berkeley 67 .86) 7. However.0e − 7 ⋅ log 1 + TOXE (7.Capacitance Model CF = 2 ⋅ EPSROX ⋅ ε 0 π 4.5. In old capacitance models this capacitance is assumed to be bias independent.6. respectively. In a single drain structure or the heavily doped S/D to gate overlap region in a LDD structure the bias dependence is the result of depleting the surface of the source and drain regions.overlap = Cdg. However in LDD MOSFETs a substantial portion of the LDD region can be depleted. Cgs. BSIM4 uses the biasdependent overlap capacitance model.overlap and Vgd. both in the vertical and lateral directions. a simple biasindependent model will be used. This can lead to a large reduction of the overlap capacitance. we can model this region with a constant capacitance.
87) 4Vgs .91) where CGBO is a model parameter. In this case. CGDL. d + Qoverlap .88) (ii) Drain side Qoverlap . Biasindependent overlap capacitance model If capMod = 0.overlap CKAPPAS CGSO ⋅ Vgs + CGSL Vgs − Vgs .overlap = 1 Vgd + δ1 − (Vgd + δ1 )2 + 4δ1 2 ( ) δ1 = 0.Capacitance Model Qoverlap .overlap − −1 + 1 − 2 CKAPPAS Vgs . model parameters CGSL.d Wactive = CGDO ⋅ Vgd (7.overlap − −1 + 1 − 2 CKAPPAD Vgd . a biasindependent overlap capacitance model will be used.02V (7. s Wactive = (7.overlap CKAPPAD + CGDL Vgd − Vgd . CKAPPAS and CKAPPD all have no effect.4 Manual Copyright © 2009 UC Berkeley 68 . g = − ( Qoverlap .90) (iii) Gate Overlap Charge Qoverlap . which represents the gatetobody overlap capacitance per unit channel length.6.89) 4Vgd .overlap = 1 Vgs + δ1 − (Vgs + δ1 )2 + 4δ1 2 ( ) δ1 = 0.02V (7. The gatetosource overlap charge is expressed by BSIM4. s + ( CGBO ⋅ Lactive ) ⋅ Vgb ) (7.
respectively) are not given. d = Wactive ⋅ CGDO ⋅ Vgd (7.93) The gatetosubstrate overlap charge is computed by Qoverlap . they will be calculated.4 Manual Copyright © 2009 UC Berkeley 69 . BSIM4.b = Lactive ⋅ CGBO ⋅ Vgb (7.94) Default CGSO and CGDO If CGSO and CGDO (the overlap capacitances between the gate and the heavily doped source / drain regions.Capacitance Model Qoverlap .6. s = Wactive ⋅ CGSO ⋅ Vgs (7.92) The gatetodrain overlap charge is calculated by Qoverlap . Appendix A gives the information on how CGSO. CGDO and CGBO are calculated.
1 Model Selector One global selector is provided to turn on or off the new material models. which could predict well the nonSiO2 gate insulator.New Material Models Chapter 8: New Material Models The enormous success of CMOS technology in the past is mainly resulted from the continuous scaling of MOSFET device.2 NonSilicon Channel With the three new parameters. Many fundamental problems. One of the effective solutions is to introduce new materials to replace the conventional material (For example. 8.1) BSIM4. while the default value (mtrlMod=0) maintains the backward compatibility. such as increased gate leakage and oxide breakdown.6. the new materials are modeled.4 Manual Copyright © 2009 UC Berkeley 70 . have arisen from this conventional method. BSIM introduces the new material model. When the selector (mtrlMod) is set to one. nonpolySi gate and nonSi channel. Significant progress has been achieved in terms of the understanding of new material properties and their integration into CMOS technology. the silicon oxide gate is substituted by the highk gate insulator). the evolutionary scaling (such as gate dielectric) is based on the shrinking of physical dimensions. Considering the impacts of new materials on the electrical characteristics. the temperaturedependent band gap and intrinsic carriers in nonsilicon channel are described as follow: Eg 0 = BG 0SUB − TBGASUB × Tnom 2 Tnom + TBGBSUB (8. 8. Until very recently.
15) = BG 0 SUB − TBGASUB × 300. TBGASUB and TBGBSUB are the first and second parameters of bandgap change due to temperature.3) (8. BSIM4. 8. which is measured at VDDEOT.7× BDOS (8. BG0SUB is the bandgap of substrate at T=0K.9 ×10−9 + (VTH 0 − VFB − φs ) V 1 + gsteff 2TOXP 0. respectively. the equivalent SiO2 thickness (EOT) is a new input parameter.9 × X DC V =VDDEOT .15 3/ 2 Eg (300. Given this new parameter.4 Manual Copyright © 2009 UC Berkeley 71 .V =V =0 gs ds bs EPSRSUB (8. the density of states parameters ADOS and BDOS are introduced to control the charge centroid.2) (8.6.152 300.4) Tnom ni = NI 0SUB × 300. EPSRSUB is the dielectric constant of substrate relative to vacuum.15) − Eg 0 × exp 2vt Eg = BG 0SUB − TBGASUB × Temp 2 Temp + TBGBSUB Here.3 NonSiO2 Gate insulator For NonSiO2 gate insulator.New Material Models Eg (300.5) Here.6) Here. The inversion charge layer thickness (XDC) is also modified as follows: X DC = ADOS ×1.15 + TBGBSUB (8. the physical gate oxide thickness TOXP could be calculated as follows: TOXP = EOT − 3.
When the gate dielectric and channel are different materials.New Material Models 8.4 NonPoly Silicon Gate Dielectric Two new parameters are introduced to describe the nonpoly silicon gate dielectric. It is worth pointing out that EPSRGATE=0 represents the metal gate and deactivates the ploy depletion effect.9) Furthermore.9 EPSRSUB ⋅ BGIDL 3 EOT ⋅ Vdb 3.4 Manual Copyright © 2009 UC Berkeley 72 .6.9 exp − ⋅ 3 Vds − Vgse − EGISL + V fbsd CGISL + Vdb (8. which is the gate work function.9 ⋅ exp − 3 Vds − Vgse − EGIDL + V fbsd CGIDL + Vdb Vds − Vgse − EGISL + V fbsd EPSRSUB EOT ⋅ 3.8) I GIDS = AGISL ⋅ WeffCJ ⋅ Nf ⋅ (8. vt ln 2 2 ni (8.9 EPSRSUB ⋅ BGISL 3 EOT ⋅ Vdb 3. the flat band voltage at Source/Drain is calculated using the following: V fbsd = PHIG − ( EASUB + Eg 0 NSD Eg 0 − BSIM 4typy × MIN . Another is EPSRGATE. for mtrlMod=1 the mobility degradation uses the new expression of the vertical field in channel as following: BSIM4.7) This new flat band equation improves the GIDL/GISL models as following: I GIDL = AGIDL ⋅ WeffCJ ⋅ Nf ⋅ Vds − Vgse − EGIDL + V fbsd EPSRSUB EOT ⋅ 3. One is PHIG. the dielectric constant of gate relative to vacuum.
10) Eeff = Vgsteff + 2Vth − 2 ⋅ BSIM 4type ⋅ ( PHIG − EASUB − Eg / 2 + 0.9 EPSRSUB Consequently.45) EOT × 3.New Material Models (8.11) mobMod=1 µeff = U 0 ⋅ f ( Leff ) Vth ⋅ EOT 2 1 + (UA ⋅ Eeff + UB ⋅ Eeff )(1 + UC ⋅ Vbseff )UD 2 V + 2 Vth + 0.12) . mobMod=0 and mobMod=1 are changed. when mtrlMod=1. BSIM4.6.00001 gsteff 2 (8. respectively: mobMod=0 µeff = U 0 ⋅ f ( Leff ) Vth ⋅ EOT 2 1 + (UA + UC ⋅Vbseff ) Eeff + UB ⋅ Eeff + UD 2 V + 2 Vth + 0.00001 gsteff 2 (8.4 Manual Copyright © 2009 UC Berkeley 73 .
BSIM4.HighSpeed/RF Models Chapter 9: HighSpeed/RF Models As circuit speed and operating frequency rise.2 NQS model [11] but many improvements are added in BSIM4. The substrate resistance model does not include any geometry 9.4 Manual Copyright © 2009 UC Berkeley 74 . The chargedeficit NQS model comes from BSIM3v3. the need for accurate prediction of circuit performance near cutoff frequency or under very rapid transient operation becomes critical. The transient and AC NQS models are developed from the same fundamental physics: the channel/gate charge response to the external signal are relaxationtime (τ) dependent and the transcapacitances and transconductances (such as Gm) for AC analysis can therefore be expressed as functions of jωτ. the chargedeficit NQS model and the IIR model should not be turned on simultaneously. Thus. The AC NQS model does not require the internal NQS charge node that is needed for the transient NQS model.6.0 provides a set of accurate and efficient highspeed/RF (radio frequency) models which consist of three modules: chargedeficit nonquasistatic (NQS) model. The IIR model considers the effect of channelreflected gate resistance and therefore accounts for the firstorder NQS effect [12]. intrinsicinput resistance (IIR) model (biasdependent gate resistance model). These two models both work with multifinger configuration.1 ChargeDeficit NonQuasiStatic (NQS) Model BSIM4 uses two separate model selectors to turn on or off the chargedeficit NQS model in transient simulation (using trnqsMod) and AC simulation (using acnqsMod). and substrate resistance network model.0. BSIM4. dependence.
The current BSIM4. The resistance R is determined from the RC time constant (τ). One way to capture the NQS effect is to represent the channel with n transistors in series (Figure 10. Figure 9.1d. the gate capacitor node is lumped with the external source and drain nodes (Figure 10. Qdef(t).1 Transient Model The transient chargedeficit NQS model can be turned on by setting trnqsMod = 1 and off by setting trnqsMod = 0. This ignores the finite time for the channel charge to buildup. 9. Figure 10. 1b). In the QuasiStatic (QS) approach. is created to keep track of the amount of deficit/surplus channel charge necessary to reach equilibrium.1c). The BSIM4 chargedeficit NQS model uses Elmore equivalent circuit to model channel charge buildup.4 Manual Copyright © 2009 UC Berkeley 75 .HighSpeed/RF Models MOSFET channel region is analogous to a biasdependent RC distributed transmission line (Figure 10.1.1 QuasiStatic and NonQuasiStatic models for SPICE analysis. An internal node. as illustrated in Figure 9. 1a).2 shows the RC subcircuit of charge deficit NQS model for transient simulation [13]. but it comes at the expense of simulation time.6.
s (t ) ∂t = ∂Qcheq (t ) Qdef (t ) ∂t (9.1) Figure 9. the terminal charge and corresponding charging current are modeled by Qdef (t ) = Qcheq (t ) − Qch (t ) (9.HighSpeed/RF Models source icheq(t) represents the equilibrium channel charging effect. g . Qdef now becomes Qdef ( t ) = Vdef × C fact (9. Considering both the transport and charging component. G and S can be written as iD.6.2 Charge deficit NQS subcircuit for transient analysis.G .G .4) τ 76 BSIM4. the total current related to the terminals D. s (t ) ∂t (9. g . The capacitor C is to be the value of Cfact (with a typical value of Farad [11]) to improve simulation accuracy. S ( DC ) + ∂Qd .4 Manual Copyright © 2009 UC Berkeley .3) and ∂Qd .2) Based on the relaxation time approach. S (t ) = I D.
For example. the smallsignal AC chargedeficit NQS model can be turned on by setting acnqsMod = 1 and off by setting acnqsMod = 0. D.7). For small signals. by substituting (9.1.HighSpeed/RF Models ∂Qd .3) into (9. and Gmbs all become complex quantities.6) considers both the drift and diffusion componets of the channel conduction.4 Manual Copyright © 2009 UC Berkeley 77 . S and B terminals of the device) and the channel transconductances Gm. respectively. each of which dominates in inversion and subthreshold regions.6) where Coxeff is the effective gate dielectric capacitance calculated from the DC model. Gds. Dxpart + Sxpart = 1 and Gxpart = 1. The transit time τ is equal to the product of Rii and WeffLeffCoxe. and Cdi (i stands for any of the G. Qch(t) can be transformed into ∆Qch ( t ) = ∆Qcheq ( t ) 1 + jωτ (9. Csi.6. respectively. 9. where Rii is the intrinsicinput resistance [12] given by I W µ C kT 1 = XRCRG1⋅ ds + XRCRG 2 ⋅ eff eff oxeff B V Rii qLeff dseff (9. it can be shown that the transcapacitances Cgi. it is easy to show that in the frequency domain. Based on (9. now Gm have the form of BSIM4.5).5) τ where D. S xpart Qdef (t ) (9.7) where ω is the angular frequency.2 AC Model Similarly. Note that Rii in (9.Sxpart are charge deficit NQS channel charge partitioning number for terminals D.G. g . s (t ) ∂t = D. G and S. G.
The IIR model considers the relaxationtime effect due to the distributive RC nature of the channel region. the IIR model should not be used together with the chargedeficit NQS model at the same time.6. The model selector rgateMod is used to choose different options. 9.8) and Cdg = Cdg 0 ⋅ ωτ + j− 2 2 1+ ω τ 1+ ω τ Cdg 0 2 2 (9. BSIM4. Thus. biasdependent). no gate resistance is generated.1 General Description BSIM4 provides four options for modeling gate electrode resistance (biasindependent) and intrinsicinput resistance (IIR. 9.9) Those quantities with sub “0” in the above two equations are known from OP (operating point) analysis. and therefore describes the firstorder nonquasistatic effect.2.2 Gate Electrode Electrode and IntrinsicInput Resistance (IIR) Model 9.4 Manual Copyright © 2009 UC Berkeley 78 .2 Model Option and Schematic rgateMod = 0 (zeroresistance): In this case.HighSpeed/RF Models Gm = Gm 0 G ⋅ ωτ + j − m0 2 2 2 2 1+ ω τ 1+ ω τ (9.2.
10) Refer to Chapter 8 for the layout parameters in the above equation. Rgeltd is give by Rgeltd = effcj RSHG ⋅ XGW + 3⋅ NGCON NGCON ⋅ ( Ldrawn − XGL ) ⋅ NF ( W ) (9. BSIM4.10) and the intrinsicinput resistance Rii as given by (9.HighSpeed/RF Models rgateMod = 1 (constantresistance): In this case.6. An internal gate node will be generated.6). trnqsMod = 0 (default) and acnqsMod = 0 (default) should be selected for this case. rgateMod = 2 (IIR model with variable resistance): In this case. only the electode gate resistance (biasindependent) is generated by adding an internal gate node.4 Manual Copyright © 2009 UC Berkeley 79 . the gate resistance is the sum of the electrode gate resistance (9.
3. the gate electrode resistance given by (9.4 Manual Copyright © 2009 UC Berkeley 80 .3 Substrate Resistance Network 9.2 Model Selector and Topology The model selector rbodyMod can be used to turn on or turn off the resistance network. This network is constructed such that little simulation efficiency penalty will result. Note that the substrate resistance parameters as listed in Appendix A should be extracted for the total device.HighSpeed/RF Models rgateMod = 3 (IIR model with two nodes): In this case. so that the overlap capacitance current will not pass through the intrinsicinput resistance. trnqsMod = 0 (default) and acnqsMod = 0 (default) should be selected for this case.3.1 General Description For CMOS RF circuit simulation. BSIM4 offers a flexible builtin substrate resistance network. not on a perfinger basis.6) through two internal gate nodes. 9. it is essential to consider the high frequency coupling through the substrate.10) is in series with the intrinsicinput resistance Rii as given by (9. rbodyMod = 0 (Off): BSIM4.6. 9.
The scalable resistors RBPS and RBPD are evaluated through BSIM4. GBMIN. channel width (W) and number of fingers (NF). In Figure 8. which would otherwise cause poor convergence. three resistors or one resistor as the substrate network. A minimum conductance.4 Manual Copyright © 2009 UC Berkeley 81 . is introduced in parallel with each resistance and therefore to prevent infinite resistance values. rbodyMod = 1 (On): All five resistances in the substrate network as shown schematically below are present simultaneously. into which the impact ionization current Iii and the GIDL current IGIDL flow. Note that the intrinsic model substrate reference point in this case is the internal body node bNodePrime.6. The resistors of the substrate network are scalable with respect to channel length (L). The scalable model allows to account for both horizontal and vertical contacts. GBMIN is merged into each resistance to simplify the representation of the model topology. rbodyMod = 2 (On : Scalable Substrate Network): The schematic is similar to rbodyMod = 1 but all the five resistors in the substrate network are now scalable with a possibility of choosing either five resistors.HighSpeed/RF Models No substrate resistance network is generated at all.3.
13) (9. L RBSBX = RBSBX 0 • −6 10 L RBSBY = RBSBY 0 • −6 10 RBSDBXL W • −6 10 W • −6 10 RBSDBXW • NF RBSDBXNF (9. The calculation for RBDB follows RBSB.16) (9. These resistors are modeled in the same way as RBPB.18) RBSDBYL RBSDBYW • NF RBSDBYNF RBSB = RBSBX • RBSBY RBSBX + RBSBY BSIM4.11) (9.17) (9. These two resistances are scalable and RBPB is given by a parallel combination of these two resistances.HighSpeed/RF Models L RBPS = RBPS 0 • −6 10 L RBPD = RBPD 0 • −6 10 RBPSL W • −6 10 RBPSW • NF RBPSNF RBPDW (9. L RBPBX = RBPBX 0 • −6 10 L RBPBY = RBPBY 0 • −6 10 RBPBXL W • −6 10 W • −6 10 RBPBXW • NF RBPBNF (9. The equations for RBSB are shown below.15) RBPBYL RBPBYW • NF RBPBYNF RBPB = RBPBX • RBPBY RBPBX + RBPBY The resistors RBSB and RBDB share the same scaling parameters but have different scaling prefactors.14) (9. one to the horizontal contacts and other to the vertical contacts.4 Manual Copyright © 2009 UC Berkeley 82 .6.12) RBPDL W • −6 10 • NF RBPDNF The resistor RBPB consists of two parallel resistor paths.
RBPD and RBPB.HighSpeed/RF Models The implementation of rbodyMod = 2 allows the user to chose between the 5R network (with all five resistors). 3R network (with RBPS.12). This converts the 5R schematic to 3R schematic where the substrate network consists of the resistors RBPS. RBPD and RBPB) and 1R network (with only RBPB). then the 5R schematic is converted to 1R network with only one resistor RBPB.4 Manual Copyright © 2009 UC Berkeley 83 .11) and (9.10). BSIM4.6. If the user doesn’t provide both the scaling parameters RBSBX0 and RBSBY0 for RBSB OR both the scaling parameters RBDBX0 and RBDBY0 for RBDB. (9. If the user chooses not to provide either of RBPS0 or RBPD0. The resistor RBPB is then calculated using (9.3 Topology with the substrate resistance network turned on. RBPS. then the conductances for both RBSB and RBDB are set to GBMIN. 5R network is used with the resistor values calculated from the equations aforementioned. RBPD and RBPB are then calculated using (9. The conductances for RBSB and RBDB are set to GBMIN. Figure 9.12). In all other situations. The resistances RBPS and RBPD are set to 1e3 Ohm.
These two modes come from BSIM3v3.1 General Description BSIM4 provides two flicker noise models. 10. which is the default model. A complete list of the noise model parameters and explanations are given in Appendix A. For instance. but the unified model has many improvements. thermal noise due to physical resistances such as the source/ drain.1 Flicker Noise Models 10. When the model selector fnoiMod is set to 0.1.2 Equations fnoiMod = 0 (simple model) The noise density is Sid ( f ) = KF ⋅ I ds AF Coxe Leff 2 f EF (10. A unified physical flicker noise model. it is now smooth over all bias regions and considers the bulk charge effect.1) BSIM4. channel thermal noise and induced gate noise and their correlation. and substrate resistances. will be used if fnoiMod = 1. and shot noise due to the gate dielectric tunneling current.6. a simple flicker noise model which is convenient for hand calculations is invoked. gate electrode.1.Noise Modeling Chapter 10: Noise Modeling The following noise sources in MOSFETs are modeled in BSIM4 for SPICE noise ananlysis: flicker noise (also known as 1/f noise).4 Manual Copyright © 2009 UC Berkeley 84 . 10.
The unified flicker noise model captures this physical process. and Leff and Weff are the effective channel length and width.5) q2 BSIM4.inv ( f ) = + k B Tq 2 µ eff I ds C oxe ( Leff − 2 ⋅ LINTNOI ) Abulk f 2 2 ef * NOIA ⋅ log N 0 + N N + N* ⋅ 10 l 10 NOIC 2 2 + NOIB ⋅ ( N 0 − N l ) + N0 − Nl 2 2 ( ) k B TI ds ∆Lclm NOIA + NOIB ⋅ N l + NOIC ⋅ N l ⋅ 2 W eff ⋅ ( Leff − 2 ⋅ LINTNOI ) 2 f ef ⋅ 1010 Nl + N* ( ) where µeff is the effective mobility at the given bias condition. respectively. fnoiMod = 1 (unified model) The physical mechanism for the flicker noise is trapping/detrappingrelated charge fluctuation in oxide traps.Noise Modeling where f is device operating frequency.6. which results in fluctuations of both mobile carrier numbers and mobilities in the channel.4 Manual Copyright © 2009 UC Berkeley 85 .3) The parameter Nl is the charge density at the drain end given by A V Nl = Coxe ⋅Vgsteff ⋅ 1 − bulk dseff V ν gsteff + 2 t q (10. The parameter N0 is the charge density at the source side given by N 0 = Coxe ⋅ Vgsteff q (10.2) S id .4) N* is given by N* = k BT ⋅ ( Coxe + Cd + CIT ) (10. the noise density is expressed as [14] (10. In the inversion region.
8) 10. the noise density is written as NOIA ⋅ k BT ⋅ I ds 2 Sid . subVt ( f ) = Weff Leff f EF N *2 ⋅1010 (10. The other is the holistic model.6.inv ( f ) Sid .2 Channel Thermal Noise There are two channel thermal noise models in BSIM4. tnoiMod = 0 (charge based) The noise current is given by 2 id = 4k BT ∆f Rds (V ) + µeff Qinv Leff 2 ⋅ NTNOI (10. These two models can be selected through the model selector tnoiMod.inv ( f ) × Sid .2. subvt ( f ) + Sid .6) ∆Lclm Esat = µeff In the subthreshold region. subvt ( f ) (10.4 Manual Copyright © 2009 UC Berkeley 86 .9) BSIM4. One is a chargebased model (default model) similar to that used in BSIM3v3.Noise Modeling where CIT is a model parameter from DC IV and Cd is the depletion capacitance.7) The total flicker noise density is Sid ( f ) = Sid . ∆Lclm is the channel length reduction due to channel length modulation and given by Vds − Vdseff + EM Litl = Litl ⋅ log Esat 2VSAT (10.
In addition. Qinv is modeled by Qinv = Wactive LactiveCoxeff AbulkVdseff Abulk 2Vdseff 2 V ⋅ NF ⋅ gsteff − + A V 2 12 ⋅ Vgsteff − bulk2 dseff (10.1b shows schematically that part of the channel thermal noise source is partitioned to the source side. The noise voltage source partitioned to the source side is given by BSIM4.1a shows the noise source connection for tnoiMod = 0. tnoiMod = 1 (holistic) In this thermal noise model.Noise Modeling where Rds(V) is the biasdependent LDD source/drain resistance. Figure 10.10) ( ) Figure 10.1 Schematic for BSIM4 channel thermal noise modeling. and the parameter NTNOI is introduced for more accurate fitting of shortchannel devices.6. all the shortchannel effects and velocity saturation effect incorporated in the IV model are automatically included. the amplification of the channel thermal noise through Gm and Gmbs as well as the inducedgate noise with partial correlation to the channel thermal noise are all captured in the new “noise partition” model.4 Manual Copyright © 2009 UC Berkeley 87 . hency the name “holistic thermal noise model”. Figure 10.
577 respectively. 10.12) − vd 2 ⋅ ( Gm + Gds + Gmbs ) where θtnoi = RNOIB ⋅ 1 + TNOIB ⋅ Leff Vgsteff ⋅ E L sat eff 2 (10. Shot noise due to various gate tunneling components is modeled as well.3 Other Noise Sources Modeled BSIM4 also models the thermal noise due to the substrate. and source/drain resistances.37 and 0.14) where RNOIB and RNOIA are model parameters with default values 0.Noise Modeling vd 2 = 4k BT ⋅ θtnoi 2 ⋅ Vdseff ∆f I ds (10.13) and β tnoi = RNOIA ⋅ 1 + TNOIA ⋅ Leff Vgsteff ⋅ E L sat eff 2 (10. electrode gate.11) and the noise current source put in the channel region with gate and body amplication is given by id 2 = 4k BT Vdseff ∆f I ds Gds + β tnoi ⋅ ( Gm + Gmbs ) 2 2 (10.4 Manual Copyright © 2009 UC Berkeley 88 .6. BSIM4.
In general.Asymmetric MOS Junction Diode Models Chapter 11: Asymmetric MOS Junction Diode Models 11. XJBVD. BSIM4 models the diode breakdown with current limiting in both forward and reverse operations. the diode IV is modeled as resistancefree with or without breakdown depending on the parameter values of XJBVS or XJBVD. BVS. there are three junction diode IV models.6.1 Junction Diode IV Model In BSIM4. setting dioMod to 1 produces fast convergence. and BVD parameters all have no effect. The model parameters are shown in Appendix A. 11. the diode is modeled exactly the same way as in BSIM3v3. When the IV model selector dioMod is set to 0 ("resistancefree"). When dioMod is set to 2 ("resistanceandbreakdown").1 Source/Body Junction Diode In the following. the equations for the sourceside diode are given.1) BSIM4. • dioMod = 0 (resistancefree) qVbs I bs = I sbs exp − 1 ⋅ fbreakdown + Vbs ⋅ Gmin NJS ⋅ kBTNOM (11.1.2 with currentlimiting feature in the forwardbias region through the limiting current parameters IJTHSFWD or IJTHDFWD. diode breakdown is not modeled for dioMod = 1 and XJBVS. When dioMod is set to 1 ("breakdownfree").4 Manual Copyright © 2009 UC Berkeley 89 .
0.1).Asymmetric MOS Junction Diode Models where Isbs is the total saturation current consisting of the components through the gateedge (Jsswgs) and isolationedge sidewalls (Jssws) and the bottom junction (Jss). no breakdown will be modeled.0. fbreakdown is given by q ⋅ ( BVS + Vbs ) fbreakdown = 1 + XJBVS ⋅ exp − NJS ⋅ k BTNOM (11. The exponential term (11.5) is linearized at both the limiting current IJTHSFWD in the forwardbias mode and the limiting current IJTHSREV in the reversebias mode. The exponential IV term in (11. I sbs = Aseff J ss (T ) + Pseff J ssws (T ) + Weffcj ⋅ NF ⋅ J sswgs (T ) (11.6.2) where the calculation of the junction area and perimeter is discussed in Chapter 12. BSIM4. • dioMod = 1 (breakdownfree) No breakdown is modeled. it is reset to 1.4) • dioMod = 2 (resistanceandbreakdown): Diode breakdown is always modeled.4 Manual Copyright © 2009 UC Berkeley 90 . when XJBVS = 0.0. if XJBVS <= 0.5) For dioMod = 2. qVbs I bs = I sbs exp NJS ⋅ k BTNOM − 1 + Vbs ⋅ Gmin (11.0. qVbs I bs = I sbs exp NJS ⋅ kBTNOM − 1 ⋅ fbreakdown + Vbs ⋅ Gmin (11.5) is linearized at the limiting current IJTHSFWD in the forwardbias model only. In (11. it is reset to 1. and the temperaturedependent current density model is given in Chapter 13.3) In the above equation. If XJBVS < 0.
1. and the temperaturedependent current density model is given in Chapter 12. I sbd = Adeff J sd (T ) + Pdeff J sswd (T ) + Weffcj ⋅ NF ⋅ J sswgd (T ) (11. it is reset to 1.9) • dioMod = 2 (resistanceandbreakdown): BSIM4.9) is linearized at the limiting current IJTHSFWD in the forwardbias model only.6). • dioMod = 0 (resistancefree) qVbd I bd = I sbd exp − 1 ⋅ f breakdown + Vbd ⋅ Gmin NJD ⋅ k BTNOM (11. when XJBVD = 0. but with a separate set of model parameters as explained in detail in Appendix A.6) where Isbd is the total saturation current consisting of the components through the gateedge (Jsswgd) and isolationedge sidewalls (Jsswd) and the bottom junction (Jsd). no breakdown will be modeled. If XJBVD < 0. qVbd I bd = I sbd exp NJD ⋅ k BTNOM − 1 + Vbd ⋅ Gmin (11. fbreakdown is given by q ⋅ ( BVD + Vbd ) fbreakdown = 1 + XJBVD ⋅ exp − NJD ⋅ k BTNOM (11.6.4 Manual Copyright © 2009 UC Berkeley 91 .0.8) In the above equation. In (11.2 Drain/Body Junction Diode The drainside diode has the same system of equations as those for the sourceside diode.0. • dioMod = 1 (breakdownfree) No breakdown is modeled. The exponential IV term in (11.7) where the calculation of the junction area and perimeter is discussed in Chapter 11.Asymmetric MOS Junction Diode Models 11.
0. it is reset to 1.4 Manual Copyright © 2009 UC Berkeley 92 .3 Total Junction Source/Drain Diode Including Tunneling Total diode current including the carrier recombination and trapassisted tunneling current in the spacecharge region is modeled by: (11.10) For dioMod = 2.deff J tss (T ) exp NJTS (T ) ⋅Vtm0 VTSS − Vbs − 1 + g `min ⋅ Vbs − 1 (11.6. if XJBVD <= 0. 11. deff J tssws (T ) exp ⋅ − 1 NJTSSW (T ) ⋅ Vtm0 VTSSWS − Vbs −Vbs VTSS ⋅ − As . qVbd I bd = I sbd exp − 1 ⋅ f breakdown + Vbd ⋅ Gmin NJD ⋅ k BTNOM (11.0.11) I bs _ total = I bs −Vbs VTSSWGS − Weffcj ⋅ NF ⋅ J tsswgs (T ) ⋅ exp ⋅ NJTSSWG (T ) ⋅Vtm0 VTSSWGS − Vbs −Vbs VTSSWS − Ps .deff J tsd (T ) exp NJTSD (T ) ⋅ Vtm0 VTSD − Vbd − 1 + g`min ⋅ Vbd − 1 BSIM4.12) I bd _ total = I bd −Vbd VTSSWGD − Weffcj ⋅ NF ⋅ J tsswgd (T ) ⋅ exp ⋅ NJTSSWGD (T ) ⋅ Vtm0 VTSSWGD − Vbd −Vbd VTSSWD − Pd .Asymmetric MOS Junction Diode Models Diode breakdown is always modeled.10) is linearized at both the limiting current IJTHSFWD in the forwardbias mode and the limiting current IJTHSREV in the reversebias mode. The exponential term (11. deff J tsswd (T ) exp ⋅ − 1 NJTSSWD (T ) ⋅ Vtm0 VTSSWD − Vbd −Vbd VTSD ⋅ − Ad .1.
and sidewall junction capacitance along the gate edge.4 Manual Copyright © 2009 UC Berkeley 93 .2. and Cjbsswg is the unitlength S/B junction sidewall capacitance along the gate edge.2 Junction Diode CV Model Source and drain junction capacitances consist of three components: the bottom junction capacitance.13) are given in Chapter 11. Cjbs is calculated by if Vbs < 0 C jbs Vbs = CJS (T ) ⋅ 1 − PBS (T ) − MJS (11.13) where Cjbs is the unitarea bottom S/B junciton capacitance.15) Cjbssw is calculated by if Vbs < 0 BSIM4.14) otherwise Vbs C jbs = CJS (T ) ⋅ 1 + MJS ⋅ PBS (T ) (11.6. An analogous set of equations are used for both sides but each side has a separate set of model parameters. Cjbssw is the unitlength S/B junction sidewall capacitance along the isolation edge.1 Source/Body Junction Diode The sourceside junction capacitance can be calculated by Cbs = Aseff C jbs + Pseff C jbssw + Weffcj ⋅ NF ⋅ C jbsswg (11. The effective area and perimeters in (11. sidewall junction capacitance along the isolation edge. 11.Asymmetric MOS Junction Diode Models 11.
Cjbdsw is the unitlength D/B junction sidewall capacitance along the isolation edge.4 Manual Copyright © 2009 UC Berkeley 94 .6.20) where Cjbd is the unitarea bottom D/B junciton capacitance.2 Drain/Body Junction Diode The drainside junction capacitance can be calculated by Cbd = Adeff C jbd + Pdeff C jbdsw + Weffcj ⋅ NF ⋅ C jbdswg (11. The effective area and perimeters in (11. Cjbd is calculated by if Vbd < 0 C jbd Vbd = CJD (T ) ⋅ 1 − PBD (T ) − MJD (11.18) otherwise C jbsswg Vbs = CJSWGS (T ) ⋅ 1 − PBSWGS (T ) − MJSWGS (11.16) otherwise Vbs C jbssw = CJSWS (T ) ⋅ 1 + MJSWS ⋅ PBSWS (T ) (11.20) are given in Chapter 12. and Cjbdswg is the unitlength D/B junction sidewall capacitance along the gate edge.2.21) otherwise BSIM4.17) Cjbsswg is calculated by if Vbs < 0 C jbsswg Vbs = CJSWGS (T ) ⋅ 1 − PBSWGS (T ) − MJSWGS (11.Asymmetric MOS Junction Diode Models C jbssw Vbs = CJSWS (T ) ⋅ 1 − PBSWS (T ) − MJSWS (11.19) 11.
23) otherwise Vbd C jbdsw = CJSWD (T ) ⋅ 1 + MJSWD ⋅ PBSWD (T ) (11.26) BSIM4.25) otherwise Vbd C jbdswg = CJSWGD (T ) ⋅ 1 + MJSWGD ⋅ PBSWGD (T ) (11.22) Cjbdsw is calculated by if Vbd < 0 C jbdsw Vbd = CJSWD (T ) ⋅ 1 − PBSWD (T ) − MJSWD (11.4 Manual Copyright © 2009 UC Berkeley 95 .24) Cjbdswg is calculated by if Vbd < 0 C jbdswg Vbd = CJSWGD (T ) ⋅ 1 − PBSWGD (T ) − MJSWGD (11.6.Asymmetric MOS Junction Diode Models Vbd C jbd = CJD (T ) ⋅ 1 + MJD ⋅ PBD (T ) (11.
1 schematically shows the geometry definition for various source/drain connections and source/drain/gate contacts.1 Geometry Definition Figure 12. BSIM4.6. shared. The layout parameters shown in this figure will be used to calculate resistances and source/drain perimeters and areas. It supports modeling of series (such as isolated. 12. or a combination of these two configurations. Note that the narrowwidth effect in the perfinger device with multifinger configuration is accounted for by this model. A complete list of model parameters and selectors can be found in Appendix A.4 Manual Copyright © 2009 UC Berkeley 96 . or merged source/ drain) and multifinger device layout. This model have impact on every BSIM4 submodels except the substrate resistance network model.LayoutDependent Parasitics Models Chapter 12: LayoutDependent Parasitics Models BSIM4 provides a comprehensive and versatile geometry/layoutdependent parasitcs model [15].
LayoutDependent Parasitics Models Figure 12.4 Manual Copyright © 2009 UC Berkeley 97 . The same approach is used for the drain side.2.1 Effective Junction Perimeter and Area In the following.6. The effective junction perimeter on the source side is calculated by BSIM4. 12. only the sourceside case is illustrated.1 Definition for layout parameters.2 Model Formulation and Options 12.
The effective junction area on the source side is calculated by If (AS is given) Aseff = AS Else Aseff computed from NF. DMCG. DMCI. DMDG. DWJ. and MIN. and MIN. where the number of source squares NRS is an instance parameter. geoMod.2 Source/Drain Diffusion Resistance The source diffusion resistance is calculated by If (number of source squares NRS is given) Rsdiff = NRS ⋅ RSH Else if (rgeoMod == 0) Source diffusion resistance Rsdiff is not generated. geoMod.2. DMCG.4 Manual Copyright © 2009 UC Berkeley 98 . DMCGT. RSH. DMCI. DMDG. DMCG. In the above. DMCI. DMDG. Else Rsdiff computed from NF.LayoutDependent Parasitics Models If (PS is given) if (perMod == 0) Pseff = PS else Pseff = PS − Weffcj ⋅ NF Else Pseff computed from NF. DMCGT. 12. Similarly. Pseff and Aseff will be used to calculate junction diode IV and CV. geoMod. DMCGT. and MIN. DWJ.6. the drain diffusion resistance is calculated by BSIM4. DWJ. Pseff does not include the gateedge perimeter.
For multifinger devices.3 Gate Electrode Resistance The gate electrode resistance with multifinger configuration is modeled by Rgeltd = effcj RSHG ⋅ XGW + 3⋅ NGCON NGCON ⋅ ( Ldrawn − XGL ) ⋅ NF ( W ) (12. and MIN.2.1 lists the options for source/drain connections through the model selector geoMod. Even NF=Odd NF=Even NF=Even Table 12.1) 12. Even NF=Odd NF=Odd.6.1 geoMod options. all inside S/D diffusions are assumed shared. Even NF=Odd NF=Odd. DMCI.LayoutDependent Parasitics Models If (number of source squares NRD is given) Rddiff = NRD ⋅ RSH Else if (rgeoMod == 0) Drain diffusion resistance Rddiff is not generated. BSIM4. DWJ. DMDG. Even NF=Odd. DMCGT. Else Rddiff computed from NF.4 Option for Source/Drain Connections Table 12. Even NF=Odd.2.4 Manual Copyright © 2009 UC Berkeley 99 . geoMod. geoMod 0 1 2 3 4 5 6 7 8 9 10 End source isolated isolated shared shared isolated shared merged merged merged sha/iso shared End drain isolated shared isolated shared merged merged isolated shared merged shared sha/iso Note NF=Odd NF=Odd. 12. RSH. DMCG.
5 Option for Source/Drain Contacts Table 12.2 rgeoMod options.4 Manual Copyright © 2009 UC Berkeley 100 .6. rgeoMod 0 1 2 3 4 5 6 7 8 Endsource contact No Rsdiff wide wide point point wide point merged merged Enddrain contact No Rddiff wide point wide point merged merged wide point Table 12.LayoutDependent Parasitics Models 12.2 lists the options for source/drain contacts through the model selector rgeoMod. BSIM4.2.
source/drain resistance.6.Temperature Dependence Model Chapter 13: Temperature Dependence Model Accurate modeling of the temperature effects on MOSFET characteristics is important to predict circuit behavior over a range of operating temperatures (T).3) (13.1 Temperature Dependence of Threshold Voltage The temperature dependence of Vth is modeled by KT1L Vth (T ) = Vth (TNOM ) + KT1 + + KT 2 ⋅ Vbseff Leff T −1 ⋅ TNOM (13.4 Manual Copyright © 2009 UC Berkeley 101 .4) T V fb (T ) = V fb (TNOM ) − KT 1 ⋅ − 1 TNOM VOFF (T ) = VOFF (TNOM ) ⋅ [1 + TVOFF ⋅ (T − TNOM )] VFBSDOFF (T ) = VFBSDOFF (TNOM ) ⋅ [1 + TVFBSDOFF ⋅ (T − TNOM )] 13. BSIM4.2) (13. This chapter presents the BSIM4 temperature dependence models for threshold voltage. The operating temperature might be different from the nominal temperature (TNOM) at which the BSIM4 model parameters are extracted. If TEMPMOD = 0. mobility. and junction diode IV and CV.1) (13. 13. saturation velocity.2 Temperature Dependence of Mobility The BSIM4 mobility model parameters have the following temperature dependences depending on the model selected through TEMPMOD.
U 0 (T ) = U 0 (TNOM ) ⋅ (T TNOM ) UTE (13. U 0 (T ) = U 0 (TNOM ) ⋅ (T TNOM ) UTE (13.12) (13.14) If TEMPMOD = 3.19) UCS (T ) = UCS (TNOM ) ⋅ (T TNOM ) UCSTE UA (T ) = UA (TNOM ) ⋅ (T / TNOM ) UA1 UB (T ) = UB (TNOM ) ⋅ (T / TNOM ) UB1 UC (T ) = UC (TNOM ) ⋅ (T / TNOM ) UC1 and BSIM4.8) UA (T ) = UA (TNOM ) + UA1⋅ (T TNOM − 1) UB (T ) = UB (TNOM ) + UB1⋅ (T TNOM − 1) UC (T ) = UC (TNOM ) + UC1⋅ (T TNOM − 1) and UD (T ) = UD (TNOM ) + UD1⋅ (T TNOM − 1) (13.13) UA (T ) = UA (TNOM ) [1 + UA1⋅ (T − TNOM )] UB (T ) = UB (TNOM ) + UB1⋅ (T TNOM − 1) UC (T ) = UC (TNOM ) [1 + UC1⋅ (T − TNOM )] and UD (T ) = UD (TNOM ) [1 + UD1⋅ (T − TNOM )] (13.16) (13.11) (13.10) (13.18) (13.17) (13.Temperature Dependence Model U 0 (T ) = U 0 (TNOM ) ⋅ (T TNOM ) UTE (13.5) (13.6) (13.15) (13.7) (13.4 Manual Copyright © 2009 UC Berkeley 102 .6.9) If TEMPMOD = 1 or 2.
Temperature Dependence Model UD (T ) = UD (TNOM ) ⋅ (T / TNOM ) UD1 (13. rdsMod = 0 (internal source/drain LDD resistance) RDSW (T ) = RDSW (TNOM ) + PRT ⋅ (T TNOM − 1) RDSWMIN (T ) = RDSWMIN (TNOM ) + PRT ⋅ (T TNOM − 1) (13.24) rdsMod = 1 (external source/drain LDD resistance) RDW (T ) = RDW (TNOM ) + PRT ⋅ (T TNOM − 1) RDWMIN (T ) = RDWMIN (TNOM ) + PRT ⋅ (T TNOM − 1) RSW (T ) = RSW (TNOM ) + PRT ⋅ (T TNOM − 1) (13.4 Manual Copyright © 2009 UC Berkeley 103 .23) (13.21) If TEMPMOD = 1.25) (13.20) It is worth pointing out that tempMod=3 only affects the mobility.27) and BSIM4.22) 13. the temperature dependence of VSAT is modeled by VSAT (T ) = VSAT (TNOM ) [1 − AT ⋅ (T − TNOM )] (13.4 Temperature Dependence of LDD Resistance If TEMPMOD = 0. Other parameters such as Rs and Rd are same as those in tempMod=2.26) (13. the temperature dependence of VSAT is modeled by VSAT (T ) = VSAT (TNOM ) − AT ⋅ (T TNOM − 1) (13.6. 13.3 Temperature Dependence of Saturation Velocity If TEMPMOD = 0.
32) (13.5 Temperature Dependence of Junction Diode IV • Sourceside diode The sourceside saturation current is given by I sbs = Aseff J ss (T ) + Pseff J ssws (T ) + Weffcj ⋅ NF ⋅ J sswgs (T ) (13.34) RDSWMIN (T ) = RDSWMIN (TNOM ) [1 + PRT ⋅ (T − TNOM )] rdsMod = 1 (external source/drain LDD resistance) RDW (T ) = RDW (TNOM ) [1 + PRT ⋅ (T − TNOM )] RDWMIN (T ) = RDWMIN ( TNOM ) [1 + PRT ⋅ (T − TNOM )] RSW (T ) = RSW (TNOM ) [1 + PRT ⋅ ( T − TNOM )] RSWMIN (T ) = RSWMIN (TNOM ) [1 + PRT ⋅ (T − TNOM )] 13.6.29) (13.31) (13.Temperature Dependence Model RSWMIN (T ) = RSWMIN (TNOM ) + PRT ⋅ (T TNOM − 1) (13.28) If TEMPMOD = 1.30) (13.37) BSIM4.35) where (13.4 Manual Copyright © 2009 UC Berkeley 104 . RDSW (T ) = RDSW (TNOM ) [1 + PRT ⋅ (T − TNOM )] rdsMod = 0 (internal source/drain LDD resistance) (13.33) (13.36) Eg (TNOM ) Eg (T ) T − + XTIS ⋅ ln v (TNOM ) vt (T ) TNOM J ss (T ) = JSS (TNOM ) ⋅ exp t NJS (13.
Temperature Dependence Model Eg (TNOM ) Eg (T ) T − + XTIS ⋅ ln v (TNOM ) vt (T ) TNOM J ssws (T ) = JSSWS (TNOM ) ⋅ exp t NJS and Eg (TNOM ) Eg (T ) T − + XTIS ⋅ ln k ⋅ TNOM kb ⋅ T TNOM J sswgs (T ) = JSSWGS (TNOM ) ⋅ exp b NJS (13. • Drainside diode The drainside saturation current is given by I sbd = Adeff J sd (T ) + Pdeff J sswd (T ) + Weffcj ⋅ NF ⋅ J sswgd (T ) (13.7.40) Eg (TNOM ) Eg (T ) T − + XTID ⋅ ln k ⋅ TNOM kb ⋅ T TNOM J sd (T ) = JSD (TNOM ) ⋅ exp b NJD (13.6.38) where Eg is given in Section 12.42) BSIM4.39) where (13.4 Manual Copyright © 2009 UC Berkeley 105 .41) Eg (TNOM ) Eg (T ) T − + XTID ⋅ ln k ⋅ TNOM kb ⋅ T TNOM J sswd (T ) = JSSWD (TNOM ) ⋅ exp b NJD and Eg (TNOM ) Eg (T ) T − + XTID ⋅ ln k ⋅ TNOM kb ⋅ T TNOM J sswgd (T ) = JSSWGD (TNOM ) ⋅ exp b NJD (13.
4 Manual Copyright © 2009 UC Berkeley 106 .exp ⋅ X tsswgs ⋅ 1 − k BT TNOM − Eg (TNOM ) T J tssws (T ) = J tssws (TNOM ) ⋅ exp ⋅ X tssws ⋅ 1 − k BT TNOM − Eg (TNOM ) T J tss (T ) = J tss (TNOM ) ⋅ exp ⋅ X tss ⋅ 1 − k BT TNOM (13.44) (13.49) (13.6.exp ⋅ X tsswgd ⋅ 1 − k BT TNOM − Eg (TNOM ) T J tsd (T ) = J tsd (TNOM ) ⋅ exp ⋅ X tsd ⋅ 1 − k BT TNOM T − 1 NJTSSWG (T ) = NJTSSWG (TNOM ) ⋅ 1 + TNJTSSWG TNOM T − 1 NJTSSW (T ) = NJTSSW (TNOM ) ⋅ 1 + TNJTSSW TNOM T − 1 NJTS (T ) = NJTS (TNOM ) ⋅ 1 + TNTJS TNOM T − 1 NJTSSWGD (T ) = NJTSSWGD(TNOM ) ⋅ 1 + TNJTSSWGD TNOM (13.43) JTWEFF J tsswgs (T ) = J tsswgs (TNOM ) ⋅ + 1 Weffcj − Eg (TNOM ) T .47) (13.51) (13.46) JTWEFF J tsswgd (T ) = J tsswgd (TNOM ) ⋅ + 1 Weffcj − Eg (TNOM ) T .45) (13.53) BSIM4.52) T − 1 NJTSSWD (T ) = NJTSSWD(TNOM ) ⋅ 1 + TNJTSSWD TNOM T NJTSSWD(T ) = NJTSSWD(TNOM ) ⋅ 1 + TNJTSSWD − 1 TNOM (13.50) (13.Temperature Dependence Model • trapassisted tunneling and recombination current (13.48) (13.
59) and PBSWGS (T ) = PBSWGS (TNOM ) − TPBSWG ⋅ (T − TNOM ) (13. while in experiments narrower device shows higher TAT current per width.61) 107 BSIM4.2 introduced a new parameter JTWEFF to describe this phenomenon.4 Manual Copyright © 2009 UC Berkeley .60) • Drainside diode The temperature dependences of zerobias unitlength/area junction capacitances on the drain side are modeled by CJD (T ) = CJD (TNOM ) ⋅ 1 + TCJ ⋅ (T − TNOM ) (13.6.46) are width independent.58) (13.Temperature Dependence Model T NJTSD(T ) = NJTSD (TNOM ) ⋅ 1 + TNTJSD − 1 TNOM (13. Here. 13. Equ. BSIM 4.6.43 and 13.54) The original TAT current densities Jtsswgs and Jtsswgd (i..e.6 Temperature Dependence of Junction Diode CV • Sourceside diode The temperature dependences of zerobias unitlength/area junction capacitances on the source side are modeled by CJS (T ) = CJS (TNOM ) + TCJ ⋅ (T − TNOM ) CJSWS (T ) = CJSWS (TNOM ) + TCJSW ⋅ (T − TNOM ) (13.57) The temperature dependences of the builtin potentials on the source side are modeled by PBS (T ) = PBS (TNOM ) − TPB ⋅ (T − TNOM ) PBSWS (T ) = PBSWS (TNOM ) − TPBSW ⋅ (T − TNOM ) (13. 13.56) and CJSWGS (T ) = CJSWGS (TNOM ) ⋅ 1 + TCJSWG ⋅ (T − TNOM ) (13.55) (13. The backward compatibility is kept when JTWEFF is zero.
16 − 7.62) and CJSWGD (T ) = CJSWGD (TNOM ) ⋅ 1 + TCJSWG ⋅ (T − TNOM ) (13.64) (13.6.15 2 ⋅ k BT (13.65) and PBSWGD (T ) = PBSWGD (TNOM ) − TPBSWG ⋅ (T − TNOM ) (13.69) mrtlMod=1 BSIM4.16 − 7.02 ×10−4 TNOM 2 TNOM + 1108 (13.5565981 − g 300.Temperature Dependence Model CJSWD (T ) = CJSWD (TNOM ) + TCJSW ⋅ (T − TNOM ) (13.7 Temperature Dependences of Eg and ni mrtlMod=0 • Energyband gap of Si (Eg) The temperature dependence of Eg is modeled by Eg (TNOM ) = 1.15 300.63) The temperature dependences of the builtin potentials on the drain side are modeled by PBD (T ) = PBD (TNOM ) − TPB ⋅ (T − TNOM ) PBSWD (T ) = PBSWD (TNOM ) − TPBSW ⋅ (T − TNOM ) (13.67) and Eg (T ) = 1.4 Manual Copyright © 2009 UC Berkeley 108 .02 ×10−4 T 2 T + 1108 (13.66) 13.45e10 ⋅ qE (TNOM ) TNOM TNOM ⋅ ⋅ exp 21.68) • Intrinsic carrier concentration of Si (ni) The temperature dependence of ni is modeled by ni = 1.
Temperature Dependence Model • Energyband gap of nonsilicon channel (Eg) The temperature dependence of Eg is modeled by Eg 0 = BG 0SUB − TBGASUB × Tnom 2 Tnom + TBGBSUB TBGASUB × 300.70) (13.15) = BG 0 SUB − Eg = BG 0SUB − TBGASUB × Temp 2 Temp + TBGBSUB • Intrinsic carrier concentration of nonsilicon channel (ni) Tnom ni = NI 0SUB × 300.4 Manual Copyright © 2009 UC Berkeley 109 .6.152 300.71) (13.15 3/ 2 Eg (300.15) − Eg 0 × exp 2vt (13.73) BSIM4.72) Eg (300.15 + TBGBSUB (13.
body effect. The first one is mobilityrelated and is induced by the band structure modification. threshold voltage.4 Manual Copyright © 2009 UC Berkeley 110 . The mechanical stress effect induced by these process causes MOSFET performance function of the active area size(OD: oxide definition) and the location of the device in the active area. such as DIBL and body effect. BSIM4 considers the influence of stress on mobility. Since the doping profile may be changed due to different STI sizes and stress. were shown in process integration. and DIBL effect. And the necessity of new models to describe the layout dependence of MOS parameters due to stress effect becomes very urgent in advance CMOS technologies. The stress influence on saturation velocity is also experimentally demonstrated.13um technology. Recent years. Influence of stress on mobility has been well known since the 0. strain channel materials have been employed to achieve high device performance. 14. Stressinduced enhancement or suppression of dopant diffusion during the processing is reported. velocity saturation.Stress Effect Model Chapter 14: Stress Effect Model CMOS feature size aggressively scaling makes shallow trench isolation(STI) very popular active area isolatiohn process in advanced technologies.1 Stress Effect Model Development Experimental analysis show that there exist at least two different mechanisms within the influence of stress effect on device characteristics.6. the threshold voltage shift and changes of other secondorder effects. The second one is Vthrelated as a result of doping profile BSIM4.
Stress Effect Model variation. Both of them follow the same 1/LOD trend but reveal different L and W scaling. We have derived a phenomenological model based on these findings by modifying some parameters in the BSIM model. Note that the following equations have no impact on the iteration time because there are no voltagecontrolled components in them. 14.1.1 Mobilityrelated Equations This model introduces the first mechanism by adjusting the U0 and Vsat according to different W, L and OD shapes. Define mobility relative change due to stress effect as :
ρ µ = ∆µeff / µeffo = ( µeff − µeffo ) / µ effo =
eff
µeff −1 µeffo
(14.1)
So,
µeff = 1 + ρµ µeffo
(14.2)
eff
Figure14.1 shows the typical layout of a MOSFET on active layout surrounded by STI isolation. SA, SB are the distances between isolation edge to Poly from one and the other side, respectively. 2D simulation shows that stress distribution can be expressed by a simple function of SA and SB.
Figure 14.1 shows the typical layout of a MOSFET
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Stress Effect Model
Figure 14.2 Stress distribution within MOSFET channel using 2D simulation
Assuming that mobility relative change is propotional to stress distribution. It can be described as function of SA, SB(LOD effect), L, W, and T dependence:
ρ µ eff =
KU0 ⋅ ( Inv _ sa + Inv _ sb ) Kstress _ u 0
(14.3)
where:
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Stress Effect Model
Inv _ sa = 1 SA + 0.5 ⋅ Ldrawn Inv _ sb = 1 SB + 0.5 ⋅ Ldrawn
LKU 0 WKU 0 + Kstress _ u 0 = 1 + LLODKU 0 (Wdrawn + XW + WLOD)WLODKU 0 ( Ldrawn + XL) + PKU 0 Tempera × 1 + TKU 0 ⋅ LLODKU 0 WLODKU 0 ⋅ (Wdrawn + XW + WLOD) ( Ldrawn + XL) TNOM
So that:
µeff = υsattemp =
1 + ρ µ eff ( SA, SB) 1 + ρ µeff ( SAref , SBref )
µeffo υsattempo
(14.5) (14.6)
1 + KVSAT ⋅ ρ µeff ( SA, SB) 1 + KVSAT ⋅ ρ µ eff ( SAref , SBref )
and SAref , SBref are reference distances between OD edge to poly from one and the other side. 14.1.2 Vthrelated Equations Vth0, K2 and ETA0 are modified to cover the doping profile change in the devices with different LOD. They use the same 1/LOD formulas as shown in section(14.1), but different equations for W and L scaling:
VTH 0 = VTH 0original + KVTH0 ⋅ ( Inv _ sa + Inv _ sb − Inv _ saref − Inv _ sbref ) Kstress_vth0 STK2 K 2 = K 2original + ⋅ ( Inv _ sa + Inv _ sb − Inv _ saref − Inv _ sbref ) Kstress_vth0LODK2 STETA0 ETA0 = ETA0original + ⋅ ( Inv _ sa + Inv _ sb − Inv _ saref − Inv _ sbref ) Kstress_vth0LODETA0
(14.7)
Where:
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5 ⋅ L Figure 14.Stress Effect Model (14.3 Multiple Finger Device For multiple finger device.3 Layout of multiple finger MOSFET 14. That is(see Figure14.8) Kstress _ vth0 = 1 + + LKVTH0 WKVTH0 + LLODKVTH ( Ldrawn + XL) (Wdrawn + XW + WLOD ) WLODKVTH LLODKVTH (14.6.2 Effective SA and SB for Irregular LOD General MOSFET has an irregular shape of active area shown in Figure 14.3 To fully describe the shape of OD region will require additional instance BSIM4.5 ⋅ L i =0 1 drawn + i ⋅ ( SD + Ldrawn ) 1 drawn + i ⋅ ( SD + Ldrawn ) NF −1 ∑ SB + 0.3) for the layout for multiple finger device): Inv _ sa = Inv _ sb = 1 NF 1 NF NF −1 i =0 ∑ SA + 0.9) ( Ldrawn + XL) PKVTH0 ⋅ (Wdrawn + XW + WLOD ) WLODKVTH 14.1. the total LOD effect is the average of LOD effect to every finger.4 Manual Copyright © 2009 UC Berkeley 114 .
They are expressed as: n sw i 1 1 =∑ ⋅ SAeff + 0.6. Stress effect model described in Section(14.5 ⋅ Ldrawn i =1 Wdrawn sbi + 0.1) allows an accurate and efficient layout extraction of effective SA and SB while keeping fully compatibility of the LOD model.4 Manual Copyright © 2009 UC Berkeley 115 .4 A typical layout of MOS devices with more instance parameters (swi.5 ⋅ Ldrawn i =1 Wdrawn sa i + 0. However.5 ⋅ Ldrawn n sw i 1 1 =∑ ⋅ SBeff + 0.5 ⋅ Ldrawn (14.Stress Effect Model parameters. this will result in too many parameters in the net lists and would massively increase the readin time and degrade the readability of parameters. [16].10) Figure 14. One way to overcome this difficulty is the concept of effective SA and SB similar to ref. sai and sbi) in addition to the traditional L and W BSIM4.
Some of the ions scattered out of the edge of the photoresist are implanted in the silicon surface near the mask edge. A deep buried layer is also key to forming triplewell structures for isolatedwell NMOSFETs. BSIM4 considers the influence of well proximity effect on threshold voltage. and body effect. it has become possible to provide a relatively heavily doped deep nwell and pwell without affecting the critical devicerelated doping at the surface. This well proximity effect model is developed by the Compact Model Council[19]. altering the threshold voltage of those devices[17]. a deep phosphorus retrograde nwell. The deep well implants provide a low resistance path and suppress parasitic bipolar gain for latchup protection. deep buried layers can affect devices located near the mask edge. With the advent of highenergy implanters and reduced thermal cycle processing. mobility. This effect is called well proximity effect.Well Proximity Effect Model Chapter 15: Well Proximity Effect Model Retrograde well profiles have several key advantages for highly scaled bulk complementary metal oxide semiconductor(CMOS) technology.4 Manual Copyright © 2009 UC Berkeley 116 . and also a triplewell implementation with a deep phosphorus isolation layer below the pwell over a lateral distance on the order of a micrometer[17]. and can also improve soft error rate and noise isolation.6. It is observed a threshold voltage shifts of up to 100 mV in a deep boron retrograde pwell. However. BSIM4.
The guidelines for calculating the instance parameters SCA. SCB.1) µeff = µeff .4 Manual Copyright © 2009 UC Berkeley 117 .1 Well Proximity Effect Model Experimental analysis[17] shows that well proximity effect is strong function of distance of FET from mask edge. SCB. SCC have been developed by the Compact Model Council which can be found at the CMC website [19].Well Proximity Effect Model 15. Well proximity affects threshold voltage. The effect of the well proximity can be described through the following equations : Vth0 = Vth0org + KVTH0WE ⋅ ( SCA + WEB ⋅ SCB + WEC ⋅ SCC ) K 2 = K 2org + K2WE ⋅ ( SCA + WEB ⋅ SCB + WEC ⋅ SCC ) (15. BSIM4.6. Note that the following equations have no impact on the iteration time because there are no voltagecontrolled components in them. mobility and the body effect of the device. A phenomenological model based on these findings has been developed by modifying some parameters in the BSIM model.org ⋅ (1 + KU0WE ⋅ ( SCA + WEB ⋅ SCB + WEC ⋅ SCC ) ) where SCA. SCC are instance parameters that represent the integral of the first/second/third distribution function for scattered well dopant. and electrical quantities influenced by it follow the same geometrical trend.
Global optimization relies on the explicit use of a computer to find one set of model parameters which will best fit the available experimental (measured) data. If BSIM4.1 Optimization strategy There are two main. Parameters which are extracted in this manner might not fit experimental data in all the bias conditions.Parameter Extraction Methodology Chapter 16: Parameter Extraction Methodology Parameter extraction is an important part of model development. but it also treats each parameter as a "fitting" parameter.4 Manual Copyright © 2009 UC Berkeley 118 . Physical parameters extracted in such a manner might yield values that are not consistent with their physical intent. these extraction methodologies are developed specifically with respect to a given parameter’s physical meaning. A combination of a local optimization and the group device extraction strategy is adopted for parameter extraction. The extraction methodology depends on the model and on the way the model is used. Nonetheless. This methodology may give the minimum average error between measured and simulated (calculated) data points. Parameters are extracted from device bias conditions which correspond to dominant physical mechanisms.6. In local optimization. many parameters are extracted independently of one another. 16. different optimization strategies: global optimization and local optimization.
6. This requires measured data from devices with different geometries. etc. If only one set of channel length and width is used. BSIM4. as shown in Figure 16. This strategy will fit one device very well but will not fit other devices with different geometries. Values extracted in this manner will now have some physical relevance. such as those of the gate tunneling current model and RF models. In single device extraction strategy. All devices are measured under the same bias conditions. it will not cover other model parameters. parameters related to channel length and channel width dependencies can not be determined.1 Extraction Requirements One large size device and two sets of smallersized devices are needed to extract parameters.3. experimental data from a single device is used to extract a complete set of model parameters. overall. 16. single device extraction strategy cannot guarantee that the extracted parameters are physical.1. The resulting fit might not be absolutely perfect for any single device but will be better for the group of devices under consideration. predict device performance quite well. Furthermore. it should. It is suggested that BSIM4 use group device extraction strategy. a general extraction methodology is proposed for basic BSIM4 model parameters. Thus. 16.Parameter Extraction Methodology properly executed. In the following.2 Extraction Strategy Two different strategies are available for extracting parameters: single device extraction strategy and group device extraction strategy.3 Extraction Procedure 16.4 Manual Copyright © 2009 UC Berkeley 119 .
Regardless of device geometry. (2) Ids vs.Parameter Extraction Methodology Figure 16. The set of devices with a fixed large channel width but different channel lengths are used to extract parameters which are related to the short channel effects.6. (3) Ids vs. BSIM4. and the body effect coefficients K1 and K2 which depend on the vertical doping concentration distribution. (1) Ids vs.1 Device geometries used for parameter extraction The largesized device (W ≥ 10µm.4 Manual Copyright © 2009 UC Berkeley 120 . Vgs @ Vds = Vdd with different Vbs. Similarly. Vgs @ Vds = 0. the set of devices with a fixed. L ≥ 10µm) is used to extract parameters which are independent of short/narrow channel effects and parasitic resistance. distinct bias conditions. these are: mobility. each device will have to be measured under four. Specifically. Vds @ Vbs = 0V with different Vgs.05V with different Vbs. long channel length but different channel widths are used to extract parameters which are related to narrow width effects. the largesized device threshold voltage VTH0.
4 Manual Copyright © 2009 UC Berkeley 121 . and P30 represent the desired extracted parameter values.Parameter Extraction Methodology (4) Ids vs.2 Optimization The optimization process recommended is a combination of NewtonRaphson's iteration and linearsquares fit of either one. A flow chart of this optimization process is shown in Figure 16.3. BSIM4. P3( m ) ) = 10 1 ∂f sim ∂f ∂f ∆P m + sim ∆P2m + sim ∆P3m 1 ∂P ∂P2 ∂P3 1 (16. (Vbb is the maximum body bias). 16.6. or three variables. P2( m ) . The model equation is first arranged in a form suitable for NewtonRaphson's iteration as shown in (16. P20 . The variable fexp() stands for the experimental data.2.1) The variable fsim() is the objective function to be optimized. P10. P2(m) and P3(m) represent parameter values after the mth iteration. two. P20. P1(m).1): f exp ( P . P30 ) − f sim ( P ( m ) . Vds @ Vbs = Vbb with different Vgs.
for the next iteration such that: Pi ( m +1) = Pi m + ∆Pi ( m ) (16. ∆P1(m) . At this point. the parameters P1.2) where i=1. This process is repeated until the incremental parameter change in parameter values ∆Pi(m) are smaller than a predetermined value.4 Manual Copyright © 2009 UC Berkeley 122 .6.2 Optimization flow To change (16. and P3 have been extracted. 2.Parameter Extraction Methodology Figure 16. BSIM4.1) are divided by ∂fsim / ∂P1.e. This gives the change in P1. in a form of y = a + bx1 + cx2). The (m+1) parameter values for P2 and P3 are obtained in an identical fashion. both sides of (16.1) into a form that a linear leastsquares fit routine can be used (i. 3 for this example. P2.
3. Data: Vth(Vbs) Device & Experimental Data Large Size Device (Large W & L). (Note: Fitting Target Data refers to measurement data used for model extraction. some process parameters have to be provided.1. These procedures are based on a physical understanding of the model and based on local optimization. Vgs @ Vds = 0. They are listed below in Table 16. K1. Input Parameters Names TOXE. UC. or EPSROX NDEP TNOM Ldrawn Wdrawn XJ Physical Meaning Gate oxide thickness and dielectric constant Doping concentration in the channel Temperature at which the data is taken Mask level channel length Mask level channel width Junction depth Table 16. DTOX.3 Extraction Routine Before any model parameters can be extracted.Parameter Extraction Methodology 16.05V at Different Vbs Extracted Experimental Data Vth(Vbs) Step 2 Extracted Parameters & Fitting Target Data UA. K2 Fitting Target Exp.) Step 1 Extracted Parameters & Fitting Target Data VTH0.1 Prerequisite input parameters prior to extraction process The parameters are extracted in the following procedure. UB. 123 BSIM4.4 Manual Copyright © 2009 UC Berkeley .6. EU Devices & Experimental Data Large Size Device (Large W & L). TOXP. Ids vs.
05V at Different Vbs Step 4 Extracted Parameters & Fitting Target Data WINT. DVT1. Rds(RDSW. Ids vs. Data: Strong Inversion region Ids(Vgs.05V at Different Vbs Step 5 Extracted Parameters & Fitting Target Data RDSW. Vgs @ Vds = 0. Vgs. Vbs) Ids vs. Data: Rds(RDSW. Data: Strong Inversion region Ids(Vgs. LPEB Devices & Experimental Data One Set of Devices (Large and Fixed W & 124 BSIM4. W. Vgs. W. LPE0.6. W. W. Vbs) Step 6 Extracted Parameters & Fitting Target Data DVT0.4 Manual Copyright © 2009 UC Berkeley . Vbs) Fitting Target Exp. Vgs @ Vds = 0. Rds(RDSW. Ids vs. Vgs @ Vds = 0. Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed L & Different W).Parameter Extraction Methodology Fitting Target Exp. WR Fitting Target Exp. DVT2. PRWG. PRWB. Vbs) Devices & Experimental Data Rds(RDSW.05V at Different Vbs Step 3 Extracted Parameters & Fitting Target Data LINT. Vbs) Fitting Target Exp. Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Data: Strong Inversion region Ids(Vgs.
Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). L. W) Step 7 Extracted Parameters & Fitting Target Data DVT0W. Vgs @ Vds = 0. Vth(Vbs. W0 Fitting Target Exp.4 Manual Copyright © 2009 UC Berkeley 125 . W) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Vth(Vbs. Data: Subthreshold region Ids(Vgs. Data: Vth(Vbs. W) Step 8 Extracted Parameters & Fitting Target Data K3. W) Vth(Vbs. VOFF. L. VOFFL. W) Step 9 Extracted Parameters & Fitting Target Data MINV. CDSC. K3B. L. L. L.6. DVT1W.05V at Different Vbs Step 10 Extracted Parameters & Fitting Target Data CDSCD Fitting Target Exp. Fitting Target Exp. Data: Vth(Vbs. L.Parameter Extraction Methodology Different L). Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Data: Vth(Vbs. DVT2W Fitting Target Exp. Ids vs. W) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Vgs @ Vbs = Vbb at Different Vds BSIM4. Ids vs. CDSCB Fitting Target Exp. NFACTOR. Data: Subthreshold region Ids(Vgs.
Data: Isat(Vgs. Vds @ Vbs = 0V at Different Vgs Step 13 Extracted Parameters & Fitting Target Data B0. VTL. Vds @ Vbs = 0V at Different Vgs BSIM4. Ids vs. Vgs @ Vds = 0. Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L).Parameter Extraction Methodology Step 11 Extracted Parameters & Fitting Target Data DWB Fitting Target Exp. B1 Fitting Target Exp. AGS.05V at Different Vbs Step 12 Extracted Parameters & Fitting Target Data VSAT.4 Manual Copyright © 2009 UC Berkeley 126 . Ids vs. LC Fitting Target Exp. Data: Isat(Vgs. Data: Strong Inversion region Ids(Vgs. A0. LAMBDA. XN. Vbs)/W A1. Vbs)/W Devices & Experimental Data One Set of Devices (Large and Fixed L & Different W).6. A2 (PMOS Only) Fitting Target Exp. Data Vdsat(Vgs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs.
L).4 Manual Copyright © 2009 UC Berkeley 127 . Vds @ Vbs = 0V at Different Vgs Step 15 Extracted Parameters & Fitting Target Data PSCBE1. Data: Isat(Vgs. PVAG. Vds) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Vbs)/W Devices & Experimental Data One Set of Devices (Large and Fixed L & Different W). PDIBLC2. FPROUT. PSCBE2 Fitting Target Exp. PDIBLC1. Vds @ Vbs = 0V at Different Vgs Step 16 Extracted Parameters & Fitting Target Data PCLM.Parameter Extraction Methodology Step 14 Extracted Parameters & Fitting Target Data DWG Fitting Target Exp. Data: Rout(Vgs. DITSL. θ(DROUT. Vds @ Vbs = 0V at Different Vgs Step 17 BSIM4. Ids vs. DITSD Fitting Target Exp. Ids vs. Ids vs.6. Vds) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Data: Rout(Vgs. DITS.
PDIBLC2. PDIBLC1.6. L) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). PDIBLC1. DVTP1. Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). L. Data: Subthreshold region Ids(Vgs. PDIBLC1. PDIBLC2. PDIBLC2. θ(DROUT. Data: θ(DROUT. Ids vs. PDIBLC1. DSUB.Parameter Extraction Methodology Extracted Parameters & Fitting Target Data DROUT. Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Vgs @ Vds = Vdd at Different Vbs Step 20 Extracted Parameters & Fitting Target Data Devices & Experimental Data 128 BSIM4. ETAB. PDIBLC2 Fitting Target Exp. Data: θ(DROUT.4 Manual Copyright © 2009 UC Berkeley . L) Step 18 Extracted Parameters & Fitting Target Data PDIBLCB Fitting Target Exp. Ids vs. Vgs @ fixed Vgs at Different Vbs Step 19 Extracted Parameters & Fitting Target Data θDIBL(ETA0. L) Fitting Target Exp. DVTP0.
Vds @ Vbs = Vbb at Different Vds Step 23 Extracted Parameters & Fitting Target Data Devices & Experimental Data BSIM4. Vgs @ Vds = Vdd at Different Vbs Step 21 Extracted Parameters & Fitting Target Data KETA Fitting Target Exp. ETAB. Ids vs. Data: θDIBL(ETA0. L) One Set of Devices (Large and Fixed W & Different L). ALPHA1. Vbs)/W Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L).6. DSUB Fitting Target Exp. Data: Isat(Vgs.4 Manual Copyright © 2009 UC Berkeley 129 . ETAB. BETA0 Fitting Target Exp. Ids vs. Ids vs. Vbs)/W Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L).Parameter Extraction Methodology ETA0. Vds @ Vbs = Vbb at Different Vgs Step 22 Extracted Parameters & Fitting Target Data ALPHA0. Data: Iii(Vgs.
W). L. SA. SB. Data: Vth(SA. Idslinear @ Vgs = Vdd.6. L. W). k2(SA.05 Step 24 Extracted Parameters & Fitting Target Data kvth0.Parameter Extraction Methodology ku0. L. Data: k2(SA. SA. Vth(SA. W) Set of Devices ( Different L. eta0(SA. llodku0. SB. L. SB. pku0. SB. Data: Mobility (SA. W. llodvth. steta0. wkvth0. SB. SB. L. pvth0. W. lkvth0. wku0. W) Devices & Experimental Data Set of Devices ( Different L. lodeta0 Fitting Target Exp. lku0. SB). SB). W) Step 25 Extracted Parameters & Fitting Target Data stk2. W) BSIM4. SA. Vds = 0. W. kvsat. tku0. SB. wlodku0 Fitting Target Exp. W) Devices & Experimental Data Set of Devices ( Different L. L. lodk2. SB). wlodvth Fitting Target Exp. L. eta0(SA.4 Manual Copyright © 2009 UC Berkeley 130 .
1 Model Selectors/Controller Parameter name LEVEL (SPICE3 parameter) Description SPICE3 model selector Default value 14 Binnable? NA VERSION Model version number 4.1 Model Selectors/Controller Appendix A: Complete Parameter List A.original model is used If 1. new format used Rds(V) modeled internally through IV equation OFF OFF  MOBMOD 0 NA MTRLMOD RDSMOD 0 NA 0 NA IGCMOD IGBMOD CVCHARGEMOD CAPMOD 0 0 0 2 NA NA NA NA BSIM4.4 Manual Copyright © 2009 UC Berkeley 131 .1 BSIM4.6.6.6.6.BSIM4.4 NA BINUNIT PARAMCHK Binning unit selector Switch for parameter value check Mobility model selector New material model selector Biasdependent source/drain resistance model selector Gatetochannel tunneling current model selector Gatetosubstrate tunneling current model selector Threshold voltage for CVmodel selector Capacitance model selector 1 1 NA NA Note BSIM4 also set as the default model in SPICE3 Berkeley Latest official release Parameters checked If 0.
original model is used If 1. new format used  PERMOD Whether PS/PD (when given) includes the gateedge perimeter Geometrydependent parasitics model selector .BSIM4.6. and how S/D parasitics resistance is computed GEOMOD (Also an instance parameter) 1 (including the gateedge perimeter) 0 (isolated) NA NA  RGEOMOD (Instance parameter only) 0 (no S/D diffusion resistance) NA  BSIM4.6.specifying how the end S/D diffusions are connected Source/drain diffusion resistance and contact model selector specifying the end S/D contact type: point.1 Model Selectors/Controller RGATEMOD (Also an instance parameter) RBODYMOD (Also an instance parameter) TRNQSMOD (Also an instance parameter) ACNQSMOD (Also an instance parameter) FNOIMOD TNOIMOD DIOMOD TEMPMOD Gate resistance model selector Substrate resistance network model selector Transient NQS model selector AC smallsignal NQS model selector Flicker noise model selector Thermal noise model selector Source/drain junction diode IV model selector Temperature mode selector 0 (no gate resistance) 0 ( network off) 0 NA   NA OFF 0 NA OFF 1 0 1 0 NA NA NA No If 0. wide or merged.4 Manual Copyright © 2009 UC Berkeley 132 .
4 Manual Copyright © 2009 UC Berkeley 133 .6.BSIM4.1 Model Selectors/Controller WPEMOD Flag for WPE model (WPEMOD=1 to activate this model 0 NA  BSIM4.6.
0cm3 1.0e9m No EOT 1.5e9m No TOXP Physical gate equivalent oxide thickness Tox at which parameters are extracted Defined as (TOXETOXP) S/D junction depth Bodyeffect coefficient near the surface Bodyeffect coefficient in the bulk Channel doping concentration at depletion edge for zero body bias Substrate doping concentration Poly Si gate doping concentration Source/drain doping concentration Fatal error if not positive TOXE No TOXM TOXE No DTOX XJ GAMMA1 (γ1 in equation) GAMMA2 (γ2 in equation) NDEP 0.5e7m calculated calculated No Yes V1/2 V 1/2 1.6.0m 1.Process Parameters A.7e17cm3 Yes NSUB NGATE NSD 6.2 Process Parameters Parameter name EPSROX Description Gate dielectric constant relative to vacuum Default value 3.0e20cm3 Yes Yes Yes  BSIM4.9 Fatal error if not positive Fatal error if not positive Fatal error if not positive Fatal error if not positive Note1 Note1 Note2 TOXE Electrical gate equivalent oxide thickness Equivalent SiO2 thickness 3.4 Manual Copyright © 2009 UC Berkeley 134 .0e16cm3 0.9 (SiO2) Binnable? No Note Typically greater than or equal to 3.
4 Manual Copyright © 2009 UC Berkeley 135 .Process Parameters VBX XT RSH RSHG Vbs at which the depletion region width equalsXT Doping depth Source/drain sheet resistance Gate electrode sheet resistance calculated (V) 1.0ohm/ square 0.55e7m 0.1ohm/ square No Yes No No Note3 Should not be negative Should not be negative BSIM4.6.
0V 4.7 11.Basic Model Parameters A.05eV 11.6.7 1.7V (NMOS) 0.4 Manual Copyright © 2009 UC Berkeley .0K 1 136 BSIM4.7V(PMOS) 0.5V (NMOS) 1.0V 1.0V Binnable? Yes Note Note4 No Flatband voltage Gate voltage at which EOT is measured Effective gate length at which EOT is measured Effective width at which EOT is measured Temperature at which EOT is measured Nonuniform vertical doping effect on surface potential Electron affinity of substrate Dielectric constant of substrate relative to vacuum Dielectric constant of gate relative to vacuum Intrinsic carrier concentration at T=300.45e16m3 1.15K Bandgap of substrate at T=0K First parameter of bandgap change due to temperature Second parameter of bandgap change due to temperature Density of states parameter to control charge centroid 1.3 Basic Model Parameters Parameter name VTH0 or VTHO DELVTO (Instance parameter only) VFB VDDEOT LEFFEOT WEFFEOT TEMPEOT PHIN EASUB EPSRSUB EPSRSUB NI0SUB BG0SUB TBGASUB TBGBSUB ADOS Description Longchannel threshold voltage at Vbs=0 Zero bias threshold voltage variation Default value 0.5V(PMOS) 1u 10u 27oC Yes No No No No Yes No No No No No No No No Note4  0.16eV 7.02e4eV/K 1108.
0 V1 2.067 m2/(Vs) (NMOS).0  DVTP1 0.032V1 0.0V1 Yes DVT0W DVT1W DVT2W U0 0.6.025 m2/(Vs) PMOS Yes Yes Yes Yes  BSIM4.032V1 0. 0.Basic Model Parameters BDOS K1 K2 K3 K3B W0 LPE0 LPEB VBM DVT0 DVT1 DVT2 DVTP0 Density of states parameter to control charge centroid Firstorder body bias coefficient Secondorder body bias coefficient Narrow width coefficient Body effect coefficient of K3 Narrow width parameter Lateral nonuniform doping parameter at Vbs=0 Lateral nonuniform doping effect on K1 Maximum applied body bias in VTH0 calculation First coefficient of shortchannel effect on Vth Second coefficient of shortchannel effect on Vth Bodybias coefficient of shortchannel effect on Vth First coefficient of draininduced Vth shift due to for longchannel pocket devices First coefficient of draininduced Vth shift due to for longchannel pocket devices First coefficient of narrow width effect on Vth for small channel length Second coefficient of narrow width effect on Vth for small channel length Bodybias coefficient of narrow width effect for small channel length Lowfield mobility 1 0.0V 2.4 Manual Copyright © 2009 UC Berkeley 137 .0 80.53 0.0 0.0 5.5V1/2 0.2 0.74e7m 0.3e6m1 0.0m No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Note5 Note5 Not modeled if binned DVTP0 <=0.5e6m 1.0m 3.
0V1 0.0e4m/s 1.6. 0. 1. 1.4 Manual Copyright © 2009 UC Berkeley 138 .Basic Model Parameters UA Coefficient of firstorder mobility degradation due to vertical field Coefficient of seconorder mobility degradation due to vertical field Coefficient of mobility degradation due to bodybias effect 1.67 NMOS).0e9m/V for MOBMOD =0 and 1.0 (PMOS) Yes  UB UC Yes Yes  UD UCS Mobility Coulumb scattering coefficient Coulombic scattering exponent Mobility channel length coefficient Mobility channel length exponential coefficient Exponent for mobility degradation of MOBMOD=2 Saturation velocity Coefficient of channellength dependence of bulk charge effect Coefficient of Vgs dependence of bulk charge effect Bulk charge effect coefficient for channel width Bulk charge effect width offset Bodybias coefficient of bulk charge effect First nonsaturation effect parameter Second nonsaturation factor Yes Yes  UP LP EU 0(1/m2) 1e8(m) 1.0m 0.047V1 0.67 (NMOS) 1.0 (PMOS) 8.0e19m2/ V2 0.0e15m/V for MOBMOD =2 1.0 0.0465e9 m/V2 for MOBMOD =0 and 2 0.0m2 1.0 Yes Yes Yes Yes  BSIM4.0m Yes Yes  VSAT A0 AGS B0 Yes Yes Yes Yes  B1 KETA A1 A2 0.0465V1 for MOBMOD=1.0V1 1.
0F/m2 2.08V No No Yes Yes Yes  0.0V 1 Yes Yes Yes Yes Yes Yes  BSIM4.0086 0.0 No Yes  1.0F/(Vm2) 0.0m/V 0.0mV 0.3 0.4e4F/m 2 Yes Yes Yes Yes Yes Yes  CDSCB CDSCD PCLM PDIBLC1 PDIBLC2 PDIBLCB 0.0m/V1/2 0.39 0.6.07V1 DROUT 0.08 0.0m 0.4 Manual Copyright © 2009 UC Berkeley 139 .Basic Model Parameters WINT LINT DWG DWB VOFF VOFFL MINV NFACTOR ETA0 ETAB DSUB CIT CDSC Channelwidth offset parameter Channellength offset parameter Coefficient of gate bias dependence of Weff Coefficient of body bias dependence of Weff bias dependence Offset voltage in subthreshold region for large W and L Channellength dependence of VOFF Vgsteff fitting parameter for moderate inversion condition Subthreshold swing factor DIBL coefficient in subthreshold region Bodybias coefficient for the subthreshold DIBL effect DIBL coefficient exponent in subthreshold region Interface trap capacitance coupling capacitance between source/ drain and channel Bodybias sensitivity of Cdsc Drainbias sensitivity of CDSC Channel length modulation parameter Parameter for DIBL effect on Rout Parameter for DIBL effect on Rout Body bias coefficient of DIBL effect on Rout 0.0(F/Vm2) 1.0 0.0m 0.
velocity overshoot will be turned off PDITS Impact of draininduced Vth shift on Rout 0.0V/m0.56 4.0 0.0 No Yes Yes BSIM4.0).24e8V/m 1. Fatal error if binned PDITS negative Fatal error if PDITSL negative If not given or (<=0.0V1 0.5 Yes Yes Yes Yes Yes Yes Not modeled if binned FPROUT not positive Not modeled if binned PDITS=0.4 Manual Copyright © 2009 UC Berkeley 140 .6.01V 0.0V1 Yes PDITSL PDITSD LAMBDA Channellength dependence of draininduced Vth shift for Rout Vds dependence of draininduced Vth shift for Rout Velocity overshoot coefficient 0.0e5m/V 0.0m1 0.Basic Model Parameters DROUT PSCBE1 PSCBE2 PVAG DELTA (δ in equation) FPROUT Channellength dependence of DIBL effect on Rout First substrate current induced bodyeffect parameter Second substrate current induced bodyeffect parameter Gatebias dependence of Early voltage Parameter for DC Vdseff Effect of pocket implant on Rout degradation 0.
source end thermal velocity will be turned off 5e9[m] at room temperatur e  LC Velocity back scattering coefficient Velocity back scattering coefficient 0.6.0 Yes BSIM4.4 Manual Copyright © 2009 UC Berkeley 141 .0).05e5[m/s] Yes If not given or (<=0.0[m] No XN 3.Basic Model Parameters VTL Thermal velocity 2.
0 ohm(µm)WR 100.Parameters for Asymmetric and BiasDependent RModel A.0  No  Yes  No  Yes Yes Yes No  1.0 ohm(µm)WR 0.0 1.0V0.0 ohm(µm)WR 1.0V1 0.6.0 ohm(µm)WR 100. reset to 0.4 Parameters for Asymmetric and BiasDependent Rds Model Parameter name RDSW RDSWMIN RDW RDWMIN RSW RSWMIN PRWG PRWB WR NRS (instance parameter only) NRD (instance parameter only) Description Zero bias LDD resistance per unit width for RDSMOD=0 LDD resistance per unit width at high Vgs and zero Vbs for RDSMOD=0 Zero bias lightlydoped drain resistance Rd(V) per unit width for RDSMOD=1 Lightlydoped drain resistance per unit width at high Vgs and zero Vbs for RDSMOD=1 Zero bias lightlydoped source resistance Rs(V) per unit width for RDSMOD=1 Lightlydoped source resistance per unit width at high Vgs and zero Vbs for RDSMOD=1 Gatebias dependence of LDD resistance Bodybias dependence of LDD resistance Channelwidth dependence parameter of LDD resistance Number of source diffusion squares Number of drain diffusion squares Default value 200.4 Manual Copyright © 2009 UC Berkeley 142 .0 ohm(µm)WR 0.0 Binnable? Yes No Yes Note If negative.5 1.0 ohm(µm)WR 0.0 No  BSIM4.
0/V Binnable? Yes Yes Yes Note  BSIM4.6.5 Impact Ionization Current Model Parameters Parameter name ALPHA0 ALPHA1 BETA0 Description First parameter of impact ionization current Channel length scaling parameter of impact ionization current First Vds dependent parameter of impact ionization current Default value 0.4 Manual Copyright © 2009 UC Berkeley 143 .0/V 0.0m/V 0.Impact Ionization Current Model Parameters A.
6 GateInduced Drain Leakage Model Parameters Parameter name AGIDL Description Preexponential coefficient for GIDL Default value 0.0 Igisl=0.0 if binned AGISL =0.0 if binned BGISL =0.8V AGIDL Yes Yes Yes BGISL Exponential coefficient for GISL BGIDL Yes CGISL EGISL Parameter for bodybias effect on GISL Fitting parameter for band bending for GISL CGIDL EGIDL Yes Yes BSIM4.GateInduced Drain Leakage Model Parameters A.0  BGIDL Exponential coefficient for GIDL 2.5V3 0.0 Igisl=0.3e9V/m Yes CGIDL EGIDL AGISL Paramter for bodybias effect on GIDL Fitting parameter for band bending for GIDL Preexponential coefficient for GISL 0.0 if binned BGIDL =0.0mho Binnable? Yes Note Igidl=0.0 if binned AGIDL =0.4 Manual Copyright © 2009 UC Berkeley 144 .6.0 Igidl=0.
5 Binnable? Yes Yes Note  CIGBACC NIGBACC Yes Yes Fatal error if binned value not positive Fatal error if binned value not positive  AIGBINV BIGBINV CIGBINV EIGBINV NIGBINV 1.36e2 (NMOS) and 9.71e3 (Fs2/g)0.59e4 (PMOS) (Fs2/g)0.5 m1V1 0.4 Manual Copyright © 2009 UC Berkeley 145 .Gate Dielectric Tunneling Current Model Parameters A.1V 3.075V1 1.8e3 (PMOS) (Fs2/g)0.5 m1V1 Yes BIGC Parameter for Igcs and Igcd Yes  BSIM4.006V1 1.49e4 (Fs /g) m1 1.0 2 0.7 Gate Dielectric Parameters Parameter name AIGBACC BIGBACC Tunneling Current Model Description Parameter for Igb in accumulation Parameter for Igb in accumulation Parameter for Igb in accumulation Parameter for Igb in accumulation Parameter for Igb in inversion Parameter for Igb in inversion Parameter for Igb in inversion Parameter for Igb in inversion Parameter for Igb in inversion Parameter for Igcs and Igcd Default value 9.0 Yes Yes Yes Yes Yes AIGC 1.11e2 (Fs2/g)0.71e3 (NMOS) and 7.5 m1V1 0.49e4 (Fs2/g)0.6.5 m1 9.5m1 1.
5 m1V1 0.5m1 1.4 Manual Copyright © 2009 UC Berkeley 146 .0 Yes  AIGS Parameter for Igs Yes  BIGS Parameter for Igs Yes  CIGS Parameter for Igs Yes  DLCIG AIGD Source/drain overlap length for Igs Parameter for Igd Yes Yes  BIGD Parameter for Igd Yes  CIGD Parameter for Igd Yes  DLCIGD NIGC Source/drain overlap length for Igd Parameter for Igcs.59e4 (PMOS) (Fs2/g)0.075 (NMOS) and 0.71e3 (NMOS) and 7.0 Yes BSIM4.8e3 (PMOS) (Fs2/g)0.075 (NMOS) and 0.36e2 (NMOS) and 9.36e2 (NMOS) and 9. Igcd .03 (PMOS) V1 1.59e4 (PMOS) (Fs2/g)0.075 (NMOS) and 0.03 (PMOS) V1 LINT 1.71e3 (NMOS) and 7.Igs and Igd Factor for the gate oxide thickness in source/drain overlap regions Yes Yes Fatal error if binned value not positive Fatal error if binned value not positive POXEDGE 1.Gate Dielectric Tunneling Current Model Parameters CIGC Parameter for Igcs and Igcd 0.5m1 1.8e3 (PMOS) (Fs2/g)0.03 (PMOS) V1 LINT 1.5 m1V1 0.6.
0 Yes Fatal error if binned value not positive Fatal error if not positive  NTOX TOXREF 1.6.0e9m Yes No VFBSDOFF 0.0 3.4 Manual Copyright © 2009 UC Berkeley 147 .Gate Dielectric Tunneling Current Model Parameters PIGCD Vds dependence of Igcs and Igcd Exponent for the gate oxide ratio Nominal gate oxide thickness for gate dielectric tunneling current model only Flatband Voltage Offset Parameter 1.0V Yes BSIM4.
0e7m 0.CV for week to strong inversion Default value 0.0F/m 0.6 LINT (m) WINT (m) 1.4 Manual Copyright © 2009 UC Berkeley 148 .6V CKAPPAS Binnable? No No No F/m Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Note Note6 Note6 Note6 Note7  calculated (F/m) 1.0 0.0 0.0 calculated (F/m) calculated (F/m) 0.0V 1.0V BSIM4.8 Charge and Capacitance Model Parameters Parameter name XPART CGSO CGDO CGBO CGSL CGDL CKAPPAS CKAPPAD CF CLC CLE DLC DWC VFBCV NOFF VOFFCV Description Charge partition parameter Non LDD region sourcegate overlap capacitance per unit channel width Non LDD region draingate overlap capacitance per unit channel width Gatebulk overlap capacitance per unit channel length Overlap capacitance between gate and lightlydoped source region Overlap capacitance between gate and lightlydoped source region Coefficient of biasdependent overlap capacitance for the source side Coefficient of biasdependent overlap capacitance for the drain side Fringing field capacitance Constant term for the short channel model Exponential term for the short channel model Channellength offset parameter for CV model Channelwidth offset parameter for CV model Flatband voltage parameter (for CAPMOD=0 only) CV parameter in Vgsteff.Charge and Capacitance Model Parameters A.CV for weak to strong inversion CV parameter in Vgsteff.6.0F/m 0.
Charge and Capacitance Model Parameters
VOFFCVL MINVCV ACDE 0.0 0.0 1.0m/V Yes Yes Yes 
MOIN
Channellength dependence of VOFFCVL Vgsteff,CV fitting parameter for moderate inversion condition Exponential coefficient for charge thickness in CAPMOD=2 for accumulation and depletion regions Coefficient for the gatebias dependent surface potential
15.0
Yes

BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
149
HighSpeed/RF Model Parameters
A.9 HighSpeed/RF Model Parameters
Parameter name XRCRG1 Default value 12.0 Binnable?
Yes
Description Parameter for distributed channelresistance effect for both intrinsicinput resistance and chargedeficit NQS models
Parameter to account for the excess channel diffusion resistance for both intrinsic input resistance and chargedeficit NQS models Resistance connected between bNodePrime and bNode
XRCRG2
1.0
Yes
Note Warning message issued if binned XRCRG1 <=0.0 
RBPB (Also an instance parameter)
50.0ohm
No
RBPD (Also an instance parameter)
Resistance connected between bNodePrime and dbNode
50.0ohm
No
RBPS (Also an instance parameter)
Resistance connected between bNodePrime and sbNode
50.0ohm
No
RBDB (Also an instance parameter)
Resistance connected between dbNode and bNode
50.0ohm
No
If less than 1.0e3ohm, reset to 1.0e3ohm If less than 1.0e3ohm, reset to 1.0e3ohm If less than 1.0e3ohm, reset to 1.0e3ohm If less than 1.0e3ohm, reset to 1.0e3ohm
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BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
HighSpeed/RF Model Parameters
RBSB (Also an instance parameter) Resistance connected between sbNode and bNode 50.0ohm No If less than 1.0e3ohm, reset to 1.0e3ohm Warning message issued if less than 1.0e20 mho
GBMIN
RBPS0 RBPSL RBPSW RBPSNF RBPD0 RBPDL RBPDW RBPDNF RBPBX0 RBPBXL RBPBXW RBPBXNF RBPBY0 RBPBYL RBPBYW RBPBYNF RBSBX0 RBSBY0 RBDBX0
Conductance in parallel with each of the five substrate resistances to avoid potential numerical instability due to unreasonably too large a substrate resistance Scaling prefactor for RBPS Length Scaling parameter for RBPS Width Scaling parameter for RBPS Number of fingers Scaling parameter for RBPS Scaling prefactor for RBPD Length Scaling parameter for RBPD Width Scaling parameter for RBPD Number of fingers Scaling parameter for RBPD Scaling prefactor for RBPBX Length Scaling parameter forRBPBX Width Scaling parameter for RBPBX Number of fingers Scaling parameter for RBPBX Scaling prefactor for RBPBY Length Scaling parameter forRBPBY Width Scaling parameter for RBPBY Number of fingers Scaling parameter for RBPBY Scaling prefactor for RBSBX Scaling prefactor for RBSBY Scaling prefactor for RBDBX
1.0e12mho
No
50 Ohms 0.0 0.0 0.0 50 Ohms 0.0 0.0 0.0 100 Ohms 0.0 0.0 0.0 100 Ohms 0.0 0.0 0.0 100 Ohms 100 Ohms 100 Ohms
No No No No No No No No No No No No No No No No No No No
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BSIM4.6.4 Manual Copyright © 2009 UC Berkeley
6.0 0.0 0.0 0.HighSpeed/RF Model Parameters RBDBY0 RBSDBXL RBSDBXW RBSDBXNF RBSDBYL RBSDBYW RBSDBYNF Scaling prefactor for RBDBY Length Scaling parameter for RBSBX and RBDBX Width Scaling parameter for RBSBX and RBDBX Number of fingers Scaling parameter for RBSBX and RBDBX Length Scaling parameter for RBSBY and RBDBY Width Scaling parameter for RBSBY and RBDBY Number of fingers Scaling parameter for RBSBY and RBDBY 100 Ohms 0.4 Manual Copyright © 2009 UC Berkeley 152 .0 0.0 0.0 No No No No No No No BSIM4.
Flicker and Thermal Noise Model Parameters A.6.25e41 (eV)1s1EF 3 m for NMOS.5e25 (eV)1s1EF 1 m for PMOS 8.75 (eV)1 1EF s m 4.0 1.188e40 (eV)1s1EF 3 m for PMOS 3.5164 No No 153 BSIM4.5 RNOIA RNOIB 0.0 1. 1.4 Manual Copyright © 2009 UC Berkeley .0 A2EFs1EFF Binnable? No Note  NOIB Flicker noise parameter B No  NOIC EM AF EF KF LINTNOI NTNOI TNOIA TNOIB Flicker noise parameter C Saturation field Flicker noise exponent Flicker noise frequency exponent Flicker noise coefficient Length Reduction Parameter Offset Noise factor for shortchannel devices for TNOIMOD=0 only Coefficient of channellength dependence of total channel thermal noise Channellength dependence parameter for channel thermal noise partitioning Thermal Noise Coefficient Thermal Noise Coefficient No No No No No No No No No  0.0 m 1.5 3.125e26 (eV)1s1EF 1 m for NMOS.0 0.1e7V/m 1. 6.10 Flicker and Thermal Noise Model Parameters Parameter name NOIA Description Flicker noise parameter A Default value 6.577 0.
0m DMCG 0.LayoutDependent Parasitic Model Parameters A.11 LayoutDependent Parasitic Model Parameters Parameter name DMCG DMCI DMDG DMCGT NF (instance parameter only) DWJ MIN (instance parameter only) XGW(Also an instance parameter) XGL Description Distance from S/D contact center to the gate edge Distance from S/D contact center to the isolation edge in the channellength direction Same as DMCG but for merged device only DMCG of test structures Number of device fingers Default value 0.0m 1 Binnable? No No No No No Note Fatal error if less than one  Offset of the S/D junction width Whether to minimize the number of drain or source diffusions for evennumber fingered device Distance from the gate contact to the channel edge DWC (in CVmodel) 0 (minimize the drain diffusion number) 0. if not equal to 1 or 2.4 Manual Copyright © 2009 UC Berkeley 154 .6.0m 0. warning message issued and reset to 1 Offset of the gate length due to variations in patterning XL Channel length offset due to mask/ etch effect XW Channel width offset due to mask/etch effect NGCON(Also Number of gate contacts an instance parameter) BSIM4.0m 0.0m 1 No No No No No No No Fatal error if less than one.0m 0.0m 0.
0V BVD=BVS JSS= 1. reset to 0.12 Asymmetric Source/Drain Junction Diode Model Parameters Parameter name (separate for source and drain side as indicated in the names) IJTHSREV IJTHDREV Description Limiting current in reverse bias region Default value IJTHSREV =0.6.Asymmetric Source/Drain Junction Diode Model Parameters A.0A/m JSWD =JSWS No Note8 BVS BVD Breakdown voltage No JSS JSD Bottom junction reverse saturation current density No If not positive.0 XJBVD =XJBVS BVS=10.1A IJTHDFWD =IJTHSFWD Binnable? No Note If not positive.4 Manual Copyright © 2009 UC Berkeley 155 .0e4A/m2 JSD=JSS JSWS =0. reset to 10.1A IJTHDREV =IJTHSREV IJTHSFWD =0.0V  JSWS JSWD Isolationedge sidewall reverse saturation current density No  BSIM4.1A If not positive. reset to 0.1A IJTHSFWD IJTHDFWD Limiting current in forward bias region No XJBVS XJBVD Fitting parameter for diode breakdown XJBVS=1.
0A/m JTSSWGD =JTSSWGS 0.0 NJTSSWGD =NJTSSWG No  NJTSSW NJTSSWD Nonideality factor for JTSSWS and JTSSWD No  NJTSSWG NJTSSWGD Nonideality factor forJTSSWGS and JTSSWGD No  BSIM4.0 NJTSD =NJTS NJTSSW =20.6.4 Manual Copyright © 2009 UC Berkeley 156 .0A/m JTSD=JTSS JTSSWS =0.Asymmetric Source/Drain Junction Diode Model Parameters JSWGS JSWGD Gateedge sidewall reverse saturation current density JSWGS =0.0A/m2 JTSSWD =JTSSWS JTSSWGS =0.0 No  JTSS JTSD Bottom trapassisted saturation current density No  JTSSWS JTSSWD STI sidewall trapassisted saturation current density No  JTSSWGS JTSSWGD Gateedge sidewall trapassisted saturation current density No  JTWEFF Trapassistant tunneling current density width dependence No  NJTS NJTSD Nonideality factor for JTSS and JTSD NJTS=20.0A/m JSWGD =JSWGS JTSS =0.0 NJTSSWD =NJTSSW NJTSSWG =20.
0 TNJTSD =TNJTS TNJTSSW= 0.02 XTSSWGS =0.02 XTSSWGD =0.02 VTSS=10V VTSD =VTSS VTSSWS =10V VTSSWD =VTSSWS VTSSWGS =10V VTSSWGD =VTSSWGS TNJTS=0.02 XTSSWS =0.02 XTSD=0. JTSD on temperature Power dependence of JTSSWS.0 TNJTSSWD =TNJTSSW TNJTSSWG =0.0 TNJTSSWGD = TNJTSSWG No  XTSSWS. JTSSWGD on temperature No  VTSS VTSD Bottom trapassisted voltage dependent parameter No  VTSSWS VTSSWD STI sidewall trapassisted voltage dependent parameter No  VTSSWGS VTSSWGD Gateedge sidewall trapassisted voltage dependent parameter No  TNJTS TNJTSD Temperature coefficient for NJTS and NJTSD No  TNJTSSW TNJTSSWD Temperature coefficient for NJTSSW and NJTSSWD No  TNJTSSWG Temperature coefficient for TNJTSSWGD NJTSSWG and NJTSSWG No  BSIM4.02 XTSSWD =0. XTSSWD No  XTSSWGS.Asymmetric Source/Drain Junction Diode Model Parameters XTSS. XTSD Power dependence of JTSS.4 Manual Copyright © 2009 UC Berkeley 157 . JTSSWD on temperature XTSS=0.6. XTSSWGD Power dependence of JTSSWGS.
0V PBD=PBS PBSWS =1.0e10 F/m CJSWD =CJSWS CJSWGS =CJSWS CJSWGD =CJSWS MJSWGS =MJSWS MJSWGD =MJSWS PBS=1.0e4 F/m2 CJD=CJS MJS=0.4 Manual Copyright © 2009 UC Berkeley 158 .6.5 MJD=MJS MJSWS =0.0V PBSWD =PBSWS PBSWGS =PBSWS PBSWGD =PBSWS  CJSWGS CJSWGD Gateedge sidewall junction capacitance per unit length No  MJSWGS MJSWGD Gateedge sidewall junction capacitance grading coefficient No  PB Bottom junction builtin potential Isolationedge sidewall junction builtin potential No  PBSWS PBSWD No  PBSWGS PBSWGD Gateedge sidewall junction builtin potential No  BSIM4.33 MJSWD =MJSWS No  MJS MJD MJSWS MJSWD Bottom junction capacitance grating coefficient Isolationedge sidewall junction capacitance grading coefficient Isolationedge sidewall junction capacitance per unit area No No  CJSWS CJSWD No CJSWS= 5.Asymmetric Source/Drain Junction Diode Model Parameters CJS CJD Bottom junction capacitance per unit area at zero bias CJS=5.
Stress Effect Model Parameters A.0e18 (m/V)2 0. NJD Temperature coefficient for UD Temperature coefficient for saturation velocity Temperature coefficient for Rdsw Emission coefficients of junction for source and drain junctions.0.11V 0. NJD=NJS Yes Yes Yes No  BSIM4.6.0ohmm NJS=1. 0.775e3 0.056V1 for MOBMOD=1. respectively 0.4 Manual Copyright © 2009 UC Berkeley 159 .13 Temperature Dependence Parameters Parameter name TNOM Description Temperature at which parameters are extracted Mobility temperature exponent Temperature coefficient of coulombic mobility Temperature coefficient for threshold voltage Channel length dependence of the temperature coefficient for threshold voltage Bodybias coefficient of Vth temperature effect Temperature coefficient for UA Temperature coefficient for UB Temperature coefficient for UC Default value 27oC Binnable? No Note  UTE UCSTE KT1 KT1L 1.056e9m/ V2 for MOBMOD=0 and 2 Yes Yes Yes Yes  UD1 AT PRT NJS.5 4.0Vm Yes Yes Yes Yes KT2 UA1 UB1 UC1 0.0(1/m)2 3.022 1.3e4m/s 0.0e9m/V 1.
0K1 0. respectively 0.0K1 0.4 Manual Copyright © 2009 UC Berkeley 160 .0K1 No  TPB Temperature coefficient of PB Temperature coefficient of TPBSW PBSW Temperature coefficient of TPBSWG PBSWG TCJ Temperature coefficient of CJ Temperature coefficient of TCJSW CJSW Temperature coefficient of TCJSWG CJSWG Temperature coefficient of TVOFF VOFF TVFBSDOFF Temperature coefficient of VFBSDOFF No No No No No No No No  BSIM4.6.Stress Effect Model Parameters XTIS.0V/K 0.0V/K 0. XTID XTIS=3.0V/K 0.0.0K1 0.0K1 0. Junction current temperature exponents for source and drain XTID=XTIS junctions.
Stress Effect Model Parameters A.0 SB (Instance Parameter) Distance between OD edge to Poly from other side 0. stress effect will be turned off If not given or(<=0).0 SD (Instance Parameter) Distance between neighbouring fingers 0.0 >0. stress effect will be turned off For NF>1 :If not given or(<=0).6. stress effect will be turned off >0.14 Stress Effect Model Parameters Parameter name SA (Instance Parameter) Description Distance between OD edge to Poly from one side Default value 0.0[m] 0.0[m] No No  BSIM4.0 Binnable? Note If not given or(<=0).4 Manual Copyright © 2009 UC Berkeley 161 .0 SAref SBref WLOD KU0 Reference distance between OD and edge to poly of one side Reference distance between OD and edge to poly of the other side Width parameter for stress effect Mobility degradation/enhancement coefficient for stress effect 1E06[m] 1E06[m] No No 0.
0 0.6.0[Vm] 0.0 0.0[m] 1.0 0.4 Manual Copyright © 2009 UC Berkeley 162 .0 0.Stress Effect Model Parameters KVSAT Saturation velocity degradation/ enhancement parameter for stress effect Temperature coefficient of KU0 Length dependence of ku0 Width dependence of ku0 Crossterm dependence of ku0 Length parameter for u0 stress effect Width parameter for u0 stress effect Threshold shift parameter for stress effect Length dependence of kvth0 Width dependence of kvth0 Crossterm dependence of kvth0 Length parameter for Vth stress effect Width parameter for Vth stress effect K2 shift factor related to Vth0 change K2 shift modification factor for stress effect eta0 shift factor related to Vth0 change eta0 shift modification factor for stress effect 0.0[m] 1.0 0.0 0.0 0.0[m] No 1<=kvsat <=1 >0 >0 >0 >0 TKU0 LKU0 WKU0 PKU0 LLODKU0 WLODKU0 KVTH0 LKVTH0 WKVTH0 PKVTH0 LLODVTH WLODVTH STK2 LODK2 STETA0 LODETA0 0.0 0.0 0.0 No No No No No No No No No No No No No No No No >0 >0 BSIM4.0 0.0 0.0 0.
0 0. turn off WPE >0.0.0 0. calculated If not given or <=0.0[m] no WEB WEC KVTH0WE K2WE KU0WE SCREF Coefficient for SCB Coefficient for SCC Threshold shift factor for well proximity effect K2 shift factor for well proximity effect Mobility degradation factor for well proximity effect Reference distance to calculate SCA.4 Manual Copyright © 2009 UC Berkeley 163 .0  0. calculated If not given . SCB and SCC 0.WellProximity Effect Model Parameters A. calculated If not given .0 0.0 no 0.15 WellProximity Effect Model Parameters Parameter name SCA (Instance Parameter) SCB (Instance Parameter) SCC (Instance Parameter) SC (Instance Parameter) Description Integral of the first distribution function for scattered well dopant Integral of the second distribution function for scattered well dopant Integral of the third distribution function for scattered well dopant Distance to a single well edge Default value 0.0 0.6.0 >0.0 Binnable? no Note If not given .0 1e6[m] No No Yes Yes Yes No >0 BSIM4.0 no 0.
dW and dL Parameters A.0 mLWN+LLN  LLC LWC LWLC LL LW LWL No No No  WL No WLC BSIM4.0mLWN 1.4 Manual Copyright © 2009 UC Berkeley 164 .0 of width offset Coefficient of length and 0.16 dW and dL Parameters Parameter name WL WLN WW WWN WWL LL LLN LW LWN LWL Description Coefficient of length dependence for width offset Power of length dependence of width offset Coefficient of width dependence for width offset Default name 0.0 0.0 0.0 width cross term dependence mWWN+WLN for width offset 0.0mWLN 1.0mLLN Coefficient of length dependence for length offset Power of length dependence for length offset Coefficient of width dependence for length offset Power of width dependence for length offset Coefficient of length and width cross term dependence for length offset Coefficient of length dependence for CV channel length offset Coefficient of width dependence for CV channel length offset Coefficient of length and width crossterm dependence for CV channel length offset Coefficient of length dependence for CV channel width offset 1.6.0 0.0mWWN Binnable? No No No No No No No No No No Note  Power of width dependence 1.
6.4 Manual Copyright © 2009 UC Berkeley 165 .dW and dL Parameters Coefficient of width dependence for CV channel width offset Coefficient of length and width crossterm dependence for CV channel width offset WW WWL No No  WWC WWLC BSIM4.
Range Parameters for Model Application A.0m 1.0m 1.6.17 Range Parameters for Model Application Parameter name LMIN LMAX WMIN WMAX Description Minimum channel length Maximum channel length Minimum channel width Maximum channel width Default value 0.0m Binnable? No No No No Note  BSIM4.4 Manual Copyright © 2009 UC Berkeley 166 .0m 0.
0. they are calculated by K1 = γ 2 − 2 K 2 Φ s − VBM K2 = (γ 1 − γ 2 ) ( 2 Φs ( Φ s − VBX − Φ s Φ s − VBM − Φ s + VBM ) ) BSIM4.4 Manual Copyright © 2009 UC Berkeley 167 .7e17cm3 and γ1 is calculated from NDEP. If VTH0 is given. NDEP is calculated from NDEP = γ 12Coxe 2 2qε si If both γ1 and NDEP are not given. Note3: If VBX is not given. it is calculated by VTH 0 = VFB + Φ s + K1 Φ s − Vbs where VFB = 1. it is calculated by qNDEP ⋅ XT 2 = Φ s − VBX 2ε si Note4: If VTH0 is not given. NDEP defaults to 1.18 Notes 18 Note1: If γ1 is not given.Notes 18 A. VFB defaults to VFB = VTH 0 − Φ s − K1 Φ s − Vbs Note5: If K1 and K2 are not given.6. it is calculated by 2qε si NDEP Coxe γ2 = 2qε si NSUB Coxe Note2: If NDEP is not given and γ1 is given. it is calculated by γ1 = If γ2 is not given.
it is reset to 1. it is reset to 1. it is reset to 1. if XJBVS < 0. BSIM4. For dioMod = 2. it is calculated by CGBO = 2 ⋅ DWC ⋅ Coxe Note8: For dioMod = 0.0) CGSO = DLC ⋅ Coxe − CGSL if (CGSO < 0. it is calculated by If (DLC is given and > 0.0. if XJBVD <=0.6.Notes 18 Note6: If CGSO is not given. it is reset to 1.0 Else CGSO = 0.0.0.0). CGSO = 0.0. For dioMod = 0.0.4 Manual Copyright © 2009 UC Berkeley 168 .0. For dioMod = 2. if XJBVS <=0.0.0. if XJBVD < 0.6 ⋅ XJ ⋅ Coxe If CGBO is not given.
0.0m 1.0 1.2 0.0e4m/s No Yes Yes Yes Note Fatal error if not positive Fatal error if not positive Note2 Note4 K1 K2 LPE0 DVT0 DVT1 U0 Yes Yes Yes Yes Yes Yes Note5 Note5  VSAT Saturation velocity Yes  BSIM4.7V (NMOS) 0.4 Manual Copyright © 2009 UC Berkeley 169 .7e17cm3 0.067 m2/(Vs) (NMOS).0e9m Binnable? No TOXP TOXE No DTOX XJ NDEP VTH0 or VTHO 0.5V1/2 0.53 0.74e7m 2.6.5e7m 1.Core Parameters Appendix B: Core Parameters Parameter name TOXE Description Electrical gate equivalent oxide thickness Physical gate equivalent oxide thickness Defined as (TOXETOXP) S/D junction depth Channel doping concentration at depletion edge for zero body bias Longchannel threshold voltage at Vbs=0 Firstorder body bias coefficient Secondorder body bias coefficient Lateral nonuniform doping parameter at Vbs=0 First coefficient of shortchannel effect on Vth Second coefficient of shortchannel effect on Vth Lowfield mobility Default value 3.7V (PMOS) 0.025 m2/(Vs) PMOS 8.
vol. p.” Tech.4 Manual Copyright © 2009 UC Berkeley 170 . K. P. 1987. 718721. Electron Devices. Hu. Moon. vol.eecs. pp. Tom Vrotsos. and Y. Monitor. 1993. M. 169172.K. [11] Weidong Liu. K. P. Hui. pp. K. Cheng. 7.1520. 1973. Y. Hu. “Design for suppression of gateinduced drain leakage in LDD MOSFETs using a quasi 2D analytical model. Electron Devices. vol. and Chenming Hu. Semicond.C. “BSIM3v3. Z. [5] J.. “An efficient and accurate compact model for thinoxideMOSFET intrinsic capacitance considering the finite charge layer thickness”. Weidong Liu. Keith Green. Wenn. "HotElectron Induced MOSFET Degradation . [2] Weidong Liu. Cheng. Chen. J. pp.” Tech. Cao. vol. pp. Hu. [8] C. T. 961964. 13. Hu. 171174. Electron Devices.” SolidState Electronics. “An Analysis of the Threshold Voltage for ShortChannel IGFET's.berkeley. 1999. 1980. 1992. Paul Gray." IEEE Trans.W. Huang. Karthik Vasanth. CH Chen. “MOSFET Modeling & BSIM3 User’s Guide. vol. of IEDM. E.1407.” IEEE Trans. 1998. Chan. M. K.” Tech. Jeng. Yachin King. Ko. Dutton. Chen. Hui.H. T. Chan and K. 963966.Y. Dig. P.6. J.“Threshold Voltage Model For DeepSubmicrometer MOSFETs. P.H. J. 1998. H. Electron Devices.” IEEE Tran. Tu. IEEE Trans. “An effective gate resistance model for CMOS RF and noise modeling. Electron Devices. Greenfield and R. Technol. vol. and Chenming Hu.Model. 40. C. S. 1999. Weidong Liu. Neff. Digest of IEDM. C. J. no. of IEDM. vol. ED27. ED46. 1999. P. 1994. pp. 8695. A.Y.” Kluwer Academic Publishers. pp 16941703. May.A.16. Ko.References Appendix C: References [1] Y. Xiaodong Jin.W.” Tech. King. HJ. Hsu. Kamohara. “Modeling of pocket implanted MOSFETs for anomalous analog behavior. 375385. Chan. [10] S. p. Hu. C. Chen. S. Improvement. and Chenming Hu. Jeng. of IEDM. K. Ko. [7] Yuhua Cheng and Chenming Hu. 1985. Dig. F. and Chenming Hu. pp. “A Relaxation time Approach to Model the NonQuasiStatic Transient Effects in MOSFETs.K.” http://wwwdevice. and Chenming Hu. [6] H. M. S. Xiaodong Jin. Parke. Tam. “DC electrical oxide thickness model for quantization of the inversion layer in MOSFETs”. [4] Z. Lee. [12] Xiaodong Jin. Xiaodong Jin. [13] Mansun Chan. R. Ko. pp. C.edu/~bsim3. 32. “Nonplanar VLSI Device Analysis Using the Solution of Poisson's Equation.2 MOSFET Model and Users’ Manual. Huang. Fujioka. Kyle. Ko. BSIM4.” IEEE Trans. Chen. Y. K. Liu. R. Dig. JJ Ou. [9] T. [3] Kanyu M.C. Sci. Liu. Ko. John Krick. and C. 39. P. “The impact of gateinduced drain leakage current on MOSFET scaling.C. Chen.
and Chenming Hu.RouxditBuisson. CICC 2005 [19] CMC Website : http://www. vol. no 9. “Lateral ion implant straggle and mask proximity effect”. 13231333.” IEEE Trans." IEDM 2002.. Electron Devices.. G.edu/~bsim3/bsim4. R.. Cottrell. Johnson. KeWei Su. [16] R..Bouche and O. IEEE Trans. Adler. Brown. “BSIM4. P. Cheng. J. no.org/cmc BSIM4. and Y. pp. ChihChiang Wang..6. "Accurate Modeling of Trench Isolation Induced Mechanical Stress Effect on MOSFET Electrical Performance. [17] Hook. MingJer Chen. and Sally Liu. ShengJier Yang. “Modeling Well Edge Proximity Effect on HighlyScaled MOSFETs”.berkeley.eigroup.0. Mann. 5.eecs. Electron Devices. Xiaodong Jin. HsienTe Chen.Bianchi.1951. Hung. 1990. 37.html. Sept. Ko. “A PhysicsBased MOSFET Noise Model for Circuit Simulators.B. Hoyniak. J. D. Kanyu M.. 2003 [18] YiMing Sheu. Volume 50.A.” http:// wwwdevice. T. pp 1946. 117120.. Hu. C.K. [15] Weidong Liu.References [14] K. Cao. P. pp. E.4 Manual Copyright © 2009 UC Berkeley 171 . C.0 Technical Notes.
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