1

Selection Information FAST/LS TTL Circuit Characteristics Design Considerations, Testing and Applications Assistance Form FAST Data Sheets
FAST AND LS TTL

2

3

4

5

LS Data Sheets Reliability Data Package Information Including Surface Mount

6

7

Selection Information FAST/LS TTL Circuit Characteristics Design Considerations, Testing and Applications Assistance Form FAST Data Sheets
FAST AND LS TTL

1

2

3

4

LS Data Sheets Reliability Data Package Information Including Surface Mount

5

6

7

DATA CLASSIFICATION
Product Preview
This heading on a data sheet

DATA CLASSIFICATION
Product Preview
This heading on a data sheet indicates that the device is in the formative stages or in design (under development). This disclaimer at the bottom of the first page reads: “This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.”

Advance Information
This heading on a data sheet indicates that the device is in sampling, preproduction, or first production stages. The disclaimer at the bottom of the first page reads: “This document contains information on a new product. Specifications and information herein are subject to change without notice.”

Fully Released
A fully released data sheet contains neither a classification heading nor a disclaimer at the bottom of the first page. This document contains information on a product in full production. Guaranteed limits will not be changed without written notice to your local Motorola Semiconductor Sales Office.

FAST AND LS TTL DATA

FAST AND LS TTL

Low Power Schottky (LSTTL) has become the industry standard logic in recent years, replacing the original 7400 TTL with lower power and higher speeds. In addition to offering the standard LS TTL circuits, Motorola offers the FAST Schottky and TTL family. Complete specifications for each of these families are provided in data sheet form. Functional selector guides not only provide an overview of already introduced devices but planned introduction dates of new products. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Fifth Edition First Printing © Motorola Inc., 1992 Previous Edition © Q1/1989 “All Rights Reserved”
MOSAIC and SOIC are trademarks of Motorola Inc. FAST is a trademark of National Semiconductor Corporation.

FAST AND LS TTL DATA

CONTENTS
Page INDEX OF DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii CHAPTER 1 — SELECTION INFORMATION, FAST/LS TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 CHAPTER 2 — CIRCUIT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Family Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAST TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LS TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LS/FAST ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHAPTER 3 — DESIGN CONSIDERATIONS, TESTING AND APPLICATIONS ASSISTANCE FORM . . . . . . . . DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting TTL Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan-In and Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wired-OR Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnection Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEFINITION OF SYMBOLS AND TERMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Switching Parameters and Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TESTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATIONS ASSISTANCE FORM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2 2-2 2-2 2-2 2-3 2-3 2-4 2-4 2-5 2-6 3-1 3-2 3-2 3-2 3-2 3-3 3-4 3-4 3-4 3-5 3-5 3-5 3-6 3-7 3-7 3-7 3-8 3-10 3-10 3-11 3-13

CHAPTER 4 — FAST DATA SHEETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 CHAPTER 5 — LS DATA SHEETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 CHAPTER 6 — RELIABILITY DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 The “Better” Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 “RAP” Reliability Audit Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 CHAPTER 7 — PACKAGE INFORMATION INCLUDING SURFACE MOUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

FAST AND LS TTL DATA i

Device MC54/74F00 MC54/74F02 MC54/74F04 MC54/74F08 MC54/74F10 MC54/74F11 MC54/74F13 MC54/74F14 MC54/74F20 MC54/74F21 MC54/74F32 MC74F37 MC74F38 MC74F40 MC54/74F51 MC54/74F64 MC54/74F74 MC54/74F85 MC54/74F86 MC54/74F109 MC74F112 MC54/74F125 MC54/74F126 MC54/74F132 MC54/74F138 MC54/74F139 MC54/74F148 MC54/74F151 MC54/74F153 MC74F157A MC74F158A MC74F160A MC74F161A MC74F162A MC74F163A MC54/74F164 MC54/74F168 MC54/74F169 MC54/74F174 MC54/74F175 MC54/74F181 MC54/74F182 MC74F194 MC74F195 MC54/74F240 MC54/74F241 MC54/74F242 MC54/74F243 MC54/74F244 MC54/74F245

Description Quad 2-Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 3-Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 3-Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Inverter Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NAND Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NAND Buffer OC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input NAND Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Wide 2/3 Input AND/OR/INVERT Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2-3-2 Input AND/OR/INVERT Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Exclusive/OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual J-K Flip-Flop w/Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual J-K Negative Edge-Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Buffer, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Buffer, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-of-8 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 1-of-4 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Line to 3-Line Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Presettable BCD Decade Counter (Asynchronous Master Reset) . . . . . . . . Synchronous Presettable Binary Counter (Asynchronous Master Reset) . . . . . . . . . . . . . . Synchronous Presettable BCD Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Presettable Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Serial-In, Parallel-Out Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Up/Down Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Up/Down Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex D Flip-Flop, Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Look Ahead Carry Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Parallel Access Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Buffer/Line Driver/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Buffer/Line Driver/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Buffer/Line Driver/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Bidirectional Transceiver/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 4-2 4-4 4-6 4-8 4-10 4-12 4-14 4-14 4-17 4-19 4-21 4-23 4-25 4-27 4-29 4-31 4-33 4-36 4-40 4-42 4-45 4-48 4-48 4-51 4-53 4-56 4-59 4-62 4-64 4-67 4-69 4-71 4-75 4-71 4-75 4-79 4-82 4-82 4-86 4-89 4-92 4-97 4-101 4-104 4-108 4-108 4-112 4-112 4-108 4-115

FAST AND LS TTL DATA ii

Device MC54/74F251 MC54/74F253 MC54/74F256 MC74F257A MC74F258A MC54/74F259 MC74F269 MC54/74F280 MC54/74F283 MC74F299 MC74F323 MC54/74F350 MC54/74F352 MC54/74F353 MC54/74F365 MC54/74F366 MC54/74F367 MC54/74F368 MC54/74F373 MC54/74F374 MC74F377 MC54/74F378 MC54/74F379 MC54/74F381 MC54/74F382 MC54/74F398 MC54/74F399 MC54/74F521 MC54/74F533 MC54/74F534 MC54/74F537 MC54/74F538 MC54/74F539 MC74F543 MC74F544 MC54/74F568 MC54/74F569 MC74F574 MC74F579 MC74F620 MC74F623 MC74F640 MC54/74F646 MC54/74F648 MC74F657A MC74F657B MC74F779 MC74F803 MC54/74F827 MC54/74F828

Description 8-Input Multiplexer/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input Multiplexer/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer, Non-Inverting 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer, Inverting 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Bidirectional Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-Bit Parity Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Universal Shift/Storage Register with Common Parallel I/O Pins . . . . . . . . . . . . . . . . . 8-Input Shift/Storage Register with Synchronous Reset and Common I/O Pins . . . . . . . . . 4-Bit Shifter/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input Multiplexer/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Buffer, Non-Inverting, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Buffer, Inverting, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Buffer, 2/4 Bit, Non-Inverting, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Buffer, 2/4 Bit, Inverting, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Transparent Latch/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal D Flip-Flop/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal D Flip-Flop with Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel D Register, Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Parallel Register, Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Port Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Port Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Transparent Latch/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal D Flip-Flop/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-of-10 Decoder with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-of-8 Decoder with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 1-of-4 Decoder with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Registered Transceiver, Non-Inverting, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Registered Transceiver, Inverting, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decade Up/Down Counter/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Binary Up/Down Counter/3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal D-Type Flip-Flop with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Bidirectional Binary Counter (3-State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Bus Transceiver with 3-State Outputs (Inverting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Bus Transceiver with 3-State Outputs (Non-Inverting) . . . . . . . . . . . . . . . . . . . . . . . . . Octal Bus Transceiver Inverting with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Transceiver/Register with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Transceiver/Register with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker, 3-State . . . . . . . . . . . Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker, 3-State . . . . . . . . . . . 8-Bit Bidirectional Binary Counter (3-State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Driver, Quad D-Type Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-Bit Buffer, Line Driver, Non-Inverting, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-Bit Buffer, Line Driver, Inverting, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 4-117 4-120 4-123 4-127 4-130 4-133 4-138 4-143 4-146 4-150 4-154 4-157 4-161 4-164 4-167 4-167 4-169 4-169 4-171 4-174 4-177 4-180 4-183 4-186 4-191 4-196 4-199 4-202 4-205 4-207 4-210 4-213 4-216 4-219 4-223 4-227 4-227 4-233 4-236 4-240 4-240 4-245 4-248 4-248 4-254 4-254 4-259 4-263 4-266 4-266

FAST AND LS TTL DATA iii

Device MC74F1245 MC74F1803 MC74F3893A SN54/74LS00 SN54/74LS01 SN54/74LS02 SN54/74LS03 SN54/74LS04 SN54/74LS05 SN54/74LS08 SN54/74LS09 SN54/74LS10 SN54/74LS11 SN54/74LS12 SN54/74LS13 SN54/74LS14 SN54/74LS15 SN54/74LS20 SN54/74LS21 SN54/74LS22 SN54/74LS26 SN54/74LS27 SN54/74LS28 SN54/74LS30 SN54/74LS32 SN54/74LS33 SN54/74LS37 SN54/74LS38 SN54/74LS40 SN54/74LS42 SN54/74LS47 SN54/74LS48 SN54/74LS51 SN54/74LS54 SN54/74LS55 SN54/74LS73A SN54/74LS74A SN54/74LS75 SN54/74LS76A SN54/74LS77 SN54/74LS83A SN54/74LS85 SN54/74LS86 SN54/74LS90 SN54/74LS92 SN54/74LS93 SN54/74LS95B SN54/74LS107A SN54/74LS109A SN54/74LS112A

Description Octal Bidirectional Transceiver with 3-State Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Driver (Quad D-Type Flip-Flop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Futurebus Backplane Transceiver (3-State and Open Collector) . . . . . . . . . . . . . . . . Quad 2-Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NAND Gate, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NAND Gate, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Inverter, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input AND Gate, Open Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 3-Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 3-Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 3-Input NAND Gate, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 3-Input AND Gate, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input NAND Gate, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NAND Buffer, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 3-Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NOR Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NOR Buffer, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NAND Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NAND Buffer, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input NAND Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-of-10 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCD to 7-Segment Decoder/Driver, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual AND-OR-INVERT Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2-2-3-Input AND-OR-INVERT Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-Wide 4-Input AND-OR-INVERT Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual J-K Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit D Latch with Q and Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual J-K Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit D Latch with Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Divide-by-12 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual J-K Negative Edge-Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual J-K Edge-Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual J-K Edge-Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 4-269 4-272 4-276 5-2 5-4 5-6 5-8 5-10 5-12 5-14 5-16 5-18 5-20 5-22 5-24 5-24 5-27 5-29 5-31 5-33 5-35 5-37 5-39 5-41 5-43 5-45 5-47 5-49 5-51 5-53 5-56 5-59 5-62 5-64 5-66 5-68 5-71 5-74 5-78 5-74 5-80 5-83 5-87 5-89 5-89 5-89 5-95 5-99 5-101 5-103

FAST AND LS TTL DATA iv

Device SN54/74LS113A SN54/74LS114A SN54/74LS122 SN54/74LS123 SN54/74LS125A SN54/74LS126A SN54/74LS132 SN54/74LS133 SN74LS136 SN54/74LS137 SN54/74LS138 SN54/74LS139 SN54/74LS145 SN54/74LS147 SN54/74LS148 SN54/74LS151 SN54/74LS153 SN54/74LS155 SN54/74LS156 SN54/74LS157 SN54/74LS158 SN54/74LS160A SN54/74LS161A SN54/74LS162A SN54/74LS163A SN54/74LS164 SN54/74LS165 SN54/74LS166 SN54/74LS168 SN54/74LS169 SN54/74LS170 SN54/74LS173A SN54/74LS174 SN54/74LS175 SN54/74LS181 SN54/74LS190 SN54/74LS191 SN54/74LS192 SN54/74LS193 SN54/74LS194A SN54/74LS195A SN54/74LS196 SN54/74LS197 SN54/74LS221 SN54/74LS240 SN54/74LS241 SN54/74LS242 SN54/74LS243 SN54/74LS244 SN54/74LS245

Description Dual J-K Edge-Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual J-K Edge-Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Retriggerable Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Retriggerable Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 3-State Buffer, Low Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 3-State Buffer, High Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Exclusive OR Gate, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-Line to 8-Line Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-of-8 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 1-of-4 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-of-10 Decoder/Driver, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-Input to 4-Line Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Input to 3-Line Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 1-of-4 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 1-of-4 Decoder/Demultiplexer, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer, Non-Inverting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer, Inverting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCD Decade Counter, Asynchronous Reset (9310 Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Binary Counter, Asynchronous Reset (9316 Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCD Decade Counter, Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Binary Counter, Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Shift Register, Serial-In/Parallel Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Parallel-To-Serial Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCD Decade Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Module 16 Binary, Bi-Directional Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 x 4 Register File, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit D-Type Register, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex D-Type Flip-Flop with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad D-Type Flip-Flop with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Up/Down Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Up/Down Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Up/Down Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Up/Down Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Right/Left Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Shift Register (9300 Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal 3-State Driver, Inverting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal 3-State Driver, Non-Inverting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Bus Transceiver, Inverting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Bus Transceiver, Non-Inverting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal 3-State Driver, Non-Inverting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Bus Transceiver, 3-State, Non-Inverting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 5-105 5-107 5-109 5-109 5-117 5-117 5-120 5-123 5-125 5-127 5-130 5-133 5-136 5-139 5-139 5-144 5-147 5-150 5-150 5-154 5-157 5-160 5-160 5-160 5-160 5-166 5-170 5-174 5-178 5-178 5-184 5-188 5-192 5-195 5-198 5-205 5-205 5-213 5-213 5-220 5-224 5-228 5-228 5-234 5-239 5-239 5-243 5-243 5-239 5-246

FAST AND LS TTL DATA v

Device SN54/74LS247 SN54/74LS248 SN54/74LS249 SN54/74LS251 SN54/74LS253 SN54/74LS256 SN54/74LS257B SN54/74LS258B SN54/74LS259 SN54/74LS260 SN54/74LS266 SN54/74LS273 SN54/74LS279 SN54/74LS280 SN54/74LS283 SN54/74LS290 SN54/74LS293 SN54/74LS298 SN54/74LS299 SN54/74LS322A SN54/74LS323 SN54/74LS348 SN54/74LS352 SN54/74LS353 SN54/74LS365A SN54/74LS366A SN54/74LS367A SN54/74LS368A SN54/74LS373 SN54/74LS374 SN54/74LS375 SN54/74LS377 SN54/74LS378 SN54/74LS379 SN54/74LS386 SN54/74LS390 SN54/74LS393 SN74LS395 SN54/74LS398 SN54/74LS399 SN54/74LS490 SN54/74LS540 SN54/74LS541 SN54/74LS569A SN54/74LS623 SN54/74LS640 SN54/74LS641 SN54/74LS642 SN54/74LS645 SN54/74LS669

Description BCD to 7-Segment Decoder/Driver, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCD to 7-Segment Decoder/Driver, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Input Multiplexer, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input Multiplexer, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer, 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer, 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Addressable Latch (9334) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 5-Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Exclusive NOR Gate, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal D-Type Flip-Flop with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Set-Reset Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-Bit Odd/Even Parity Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Full Adder (Rotated LS83A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer with Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Shift/Storage Register, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Shift Register with Sign Extend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Universal Shift/Storage Register, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Input to 3-Line Priority Encoder, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input Multiplexer, 3-State LS352 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Buffer with Common Enable, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Inverter with Common Enable, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Buffer, 4-Bit and 2-Bit, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex-Inverter, 4-Bit and 2-Bit, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Transparent Latch, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal D-Type Flip-Flop, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit D Latch with Q and Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal D-Type Flip-Flop with Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex D-Type Flip-Flop with Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit D-Type Flip-Flop with Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Shift Register, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer with Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer with Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal 3-State Driver, Inverting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal 3-State Driver, Non-Inverting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Binary Up/Down Counter, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Transceiver with Storage, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Bus Transceiver with 3-State Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Bus Transceiver, Open Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Bus Transceiver, Open Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Bus Transceiver with 3-State Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous 4-Bit Up/Down Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 5-248 5-248 5-248 5-254 5-258 5-261 5-265 5-265 5-269 5-273 5-275 5-277 5-280 5-282 5-284 5-288 5-288 5-293 5-297 5-302 5-306 5-311 5-315 5-318 5-322 5-322 5-322 5-322 5-325 5-325 5-330 5-333 5-333 5-333 5-338 5-340 5-340 5-345 5-349 5-349 5-353 5-356 5-356 5-359 5-364 5-367 5-367 5-367 5-367 5-370

FAST AND LS TTL DATA vi

Device SN54/74LS670 SN54/74LS682 SN54/74LS684 SN54/74LS688 SN54/74LS748 SN54/74LS795 SN54/74LS796 SN54/74LS797 SN54/74LS798 SN54/74LS848

Description 4 x 4 Register File, 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Input to 3-Line Priority Encoder (Glitchless) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Buffer (81LS95), 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Buffer (81LS96), 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Buffer (81LS97), 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Buffer (81LS98), 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Input to 3-Line Priority Encoder, 3-State (Glitchless) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 5-374 5-378 5-378 5-378 5-139 5-382 5-382 5-382 5-382 5-311

FAST AND LS TTL DATA vii

FAST AND LS TTL DATA viii

FAST AND LS TTL DATA ix .

Selection Information FAST/LS TTL 1 FAST AND LS TTL .

NOTES: 1.2 125 125 Unit mA mW ns pJ MHz MHz FAST AND LS TTL DATA 1-2 .5 3. is growing rapidly and gaining a significant share of the total TTL logic market. 0% for ac).0 20 – 60 to – 150 – 12 48 FAST 74Fxxx 5 ± 10% 0 to 70 20 – 600 – 1. These design and specification improvements offered by the Motorola FAST family provide the user with better system performance. to Schottky-Clamped logic. and finally to the modern advanced families of TTL logic. Specifications are shown for the following conditions: NOTES: 1.4 2.0 54Fxxx 5 ± 10% – 55 to 125 20 –600 –1. Additionally. and superior line driving capabilities in comparison to these earlier families. a) VCC = 5. C) CL = 50 pF for FAST. 15 pF for LS Symbol IG PG tp — fmax fmax LS 0. They are pin and functionally compatible and can easily be combined in a system to achieve maximum performance at minimum cost. FAST designs incorporate power-down circuitry on all three-state outputs.7 19. TTL Family Comparisons General Characteristics for Schottky TTL Logic (ALL MAXIMUM RATINGS) Characteristic Operating Voltage Range Operating Temperature Range Input Current Symbol VCC TA IIN IIH IIL Output Drive Standard Output IOH IOL ISC IOH Buffer Output IOL ISC 54LSxxx 5 ± 10% – 55 to 125 20 – 400 – 0. low cost. enhanced design flexibility. When compared with the Advanced Schottky family (74AS).4 8.0 Vdc (AC).GENERAL INFORMATION TTL in Perspective Since its introduction. FAST ac characteristics are specified at a heavier capacitive load than the earlier families (50 pF versus 15 pF) to more accurately reflect actual in-circuit performance.0 LS 74LSxxx 5 ± 5% 0 to 70 20 – 400 – 0. TTL has become the most popular form of digital logic.4 4. LS (Low Power Schottky) is currently the more popular and commands by far the largest share of the total TTL logic market. The popularity of these TTL families stem from their ease of use.0 20 – 60 to – 150 – 15 64 – 100 to – 225 Unit Vdc °C µA mA mA mA mA mA mA – 20 to – 100 – 20 to – 100 – 12 12 – 15 24 – 40 to – 225 – 40 to – 225 – 100 to – 225 Speed/Power Characteristics for Schottky TTL Logic(1) (ALL TYPICAL RATINGS) Characteristic Quiescent Supply Current/Gate Power/Gate (Quiescent) Propagation Delay Speed Power Product Clock Frequency (D-F/F) Clock Frequency (Counter) NOTES: 1. allowing the FAST family to be designed and specified with improved noise margins. and more reliable system operation. Motorola offers two modern TTL logic families — LS and FAST™. high-performance TTL family. the state-of-the-art. FAST is manufactured on Motorola’s MOSAIC (oxideisolated) process. b) TA = 25°C NOTES: 1. medium-to-high speed operation. It has evolved from the original gold-doped saturated 7400 logic.0 18 33 40 FAST 1. and buffered outputs on all storage devices. reduced input currents. FAST offers nearly equal performance at a 25 – 50 percent savings in power.0 9. FAST. Two further advantages of FAST are the load specifications and power supply specifications.1 5. Motorola’s dc and ac characteristics for FAST are specified over a full 10% supply voltage range — a significant improvement over the industry standard specifications for the earlier families (5% for dc. It is low-cost and provides moderate performance at low power. FAST offers a 20 – 30 percent improvement in performance over the older Standard Schottky family (74S) with a 75 – 80 percent reduction in power.This process provides FAST with inherent speed/power advantages over the older junction-isolated 74S and 74LS families. and good output drive capability.

Inverting Quad 2-Input NAND Gate Type of Output 2S 2S 2S No. 86 136 386 LS X X X FAST X AND Gates Description Quad 2-Input Triple 3-Input Dual 4-Input Type of Output 2S OC 2S OC 2S No. 4-Input 4-Wide. 74 74A 113A 73A 107A 76A 112 112A 114A 109 109A LS X X X X X X X X X X FAST X OR Gates Description Quad 2-Input Type of Output 2S No.Functional Selection Abbreviations S A B = = = Synchronous Asynchronous Both Synchronous and Asynchronous 2-State Output 3-State Output Open-Collector Output Planned (See FAST/LS Selector Guide. 2-Input 3-Input 4-Wide. 02 27 260 LS X X X FAST X Dual D w/Set & Clear Dual D w/Set & Clear Dual JK w/Set Dual JK w/Clear Same as 73A with Different Pinout Dual JK w/Set & Clear Individual J. CP. SG-60 for latest availability status) Available 2S = 3S = OC = P X = = Inverters Description Hex Type of Output 2S OC No. 04 05 LS X X FAST X Exclusive OR Gates Description Quad 2-Input Type of Output 2S OC 2S No. 4-2-2-3-Input X Schmitt Triggers X X Description Dual 4-Input NAND Gate Hex. 13 14 132 LS X X X FAST X X X Quad 2-Input. High Voltage Triple 3-Input Dual 4-Input 8-Input 13-Input SSI Flip-Flops Description Clock Edge Pos Pos Neg Neg Neg Neg Neg Neg Neg Pos Pos No. 266 LS X FAST AND-OR-INVERT Gates Description Type of Output 2S 2S 2S 2S No. K. 51 54 55 64 LS X X X FAST X NAND Gates Description Quad 2-Input Type of Output 2S OC OC OC 2S OC 2S OC 2S 2S No. CD Inputs Same as 76 with Different Pinout Same as 76A with Different Pinout Same as 112 with Different Pinout Dual JK w/Set & Clear Dual JK w/Set & Clear FAST AND LS TTL DATA 1-3 . 32 LS X FAST X NOR Gates Description Quad 2-Input Triple 3-Input Dual 5-Input Type of Output 2S 2S 2S No. SD. 08 09 11 15 21 LS X X X X X FAST X X X Exclusive NOR Gates Description Quad 2-Input Type of Output OC No. 00 01 03 26 10 12 20 22 30 133 LS X X X X X X X X X X FAST X Dual 2-Wide. 2-3-2-3-Input 2-Wide.

Non-Inverting Dual 4-to-1. 164 165 166 95B 194 194A 195 195A 395 299 323 322A LS X X X X X X X X X X X FAST X X Parallel In-Parallel Out. Non-Inverting Type of Output 2S 2S 3S 3S 2S 2S 3S 3S 2S 3S 2S 3S 2S 3S 2S 2S 2S No. of Bits 8 8 8 4 4 4 4 4 4 8 8 8 Type of Output 2S 2S 2S 2S 2S 2S 2S 2S 3S 3S 3S 3S Mode* SR X X X X X X X X X X X X SL Hold X X X X X X Reset A A A A A A A A S A No. Inverting 1-of-8 1-of-8 with Latch 1-of-10 X X X Dual 4-to-1. 139 155 156 539 138 538 137 42 537 LS X X X X X X X FAST X Quad 2-to-1. Q and Q Outputs Quad Set-Reset Latch Addressable Dual 4-Bit Addressable No. 157 157A 257A 257B 158 158A 258A 258B 153 253 352 353 151 251 298 398 399 LS X X X X X X X X X X X X X X X X X X X X X X X FAST Decoders/Demultiplexers Description Dual 1-of-4 Type of Output 2S 2S OC 3S 2S 3S 2S 2S 3S No. 170 670 LS X X FAST Shift Registers Description Serial In-Parallel Out Parallel In-Serial Out Parallel In-Parallel Out No. Q/O Outputs 399 — Positive edge triggered. Bidirectional Sign Extended Bidirectional * SR = Shift Right * SL = Shift Left X X X X X X X FAST AND LS TTL DATA 1-4 . Non-Inverting Octal. Inverting 8-to-1 Latches Description Transparent.Multiplexers Description Quad 2-to-1. Q Output Only X X Encoders Description 10-to-4-Line BCD 8-to-3-Line Priority Encoder Type of Output 2S 2S 3S 2S 3S No. 147 148 348 748 848 LS X X X X X FAST X X X Register Files Description 4x4 Type of Output OC 3S No. Inverting Transparent. 77 373 573 533 75 375 279 259 256 LS X X FAST X X X X X X X Quad 2-to-1 with Output Register 398 — Positive edge triggered. Non-Inverting Transparent. of Bits 4 8 8 8 4 4 4 8 4 Type of Output 2S 3S 3S 3S 2S 2S 2S 2S 2S No.

of Bits 4 4 6 6 8 8 8 4 4 8 8 4 4 Type of Output 3S 2S 2S 2S 2S 3S 3S 2S 2S 3S 3S 2S 2S Set or Reset A A X A Clock Enable X X No. MSI Flip-Flops/Registers Description D-Type. 145* 47* 48* 247* 248* 249* LS X X X X X X FAST A B B S X 8 Bit Binary. Up/Down Type of Output Load 2S 2S 2S 2S 2S 3S 2S 2S 2S 2S 2S 3S 3S 2S 3S 3S 3S S S S A A S S S S A A S S S S S S Reset A S No. * The 48 and 248 have internal pull up resistors to VCC on their outputs. 90* 196* 290* 390* 490* 92* 93* 197* 293* 393* LS X X X X X X X X X X FAST Cascadable Synchronous Counters — Positive Edge-Triggered Description Decade Decade. Load Set X Reset X X X X X X X X X X No. 160A 162A 168 190 192* 568 161A 163A 169 191 193* 569 569A 669 579 779 269 LS X X X X X X X X X X X X X X X FAST X X X X 4-Bit Binary 4-Bit Binary. Up/Down * The 192 and 193 do not provide a clock enable for synchronous cascading. Up/Down A B A S X X X X Display Decoders/Drivers with Open-Collector Outputs Description 1-of-10 BCD-to-7 Segment No. Inverting D-Type. Non-Inverting No. 173A 377 174 378 273 374 574 398 399 534 564 175 379 LS X X X X X X X X FAST X X X X X X X X X X Quad 2-Port D-Type.Asynchronous Counters — Negative Edge-Triggered Description Decade (2/5) X X Dual Decade (2/5) Dual Decade Modulo 12 (2/6) 4-Bit Binary (2/8) X Dual 4-Bit Binary * The 716 and 718 are positive edge-triggered. Q and Q Outputs A A X X A X X X FAST AND LS TTL DATA 1-5 .

Inverting Bus Pinout No. 85 682 684 521 688 LS X X X X Octal. Inverting X X Octal.Arithmetic Operators Description 4-Bit Adder 4-Bit ALU No. 243 3893A 242 245 645 623 641 1245 620 640 642 646 543 544 657A 657B LS X X X X X X FAST X X X X X X X X X X X X X Octal. Non-Inverting Type of Output 3S 3S 3S 3S 3S 3S OC 3S 3S 3S OC 3S 3S 3S 3S No. 28 33 37 38 40 125 125A 126 126A 365 365A 367 367A 366 366A 368 368A 241 244 541 795 797 240 540 796 798 827 828 LS X X X X X X X X X X X X X X X X X X X X X X X X X X X FAST Look-Ahead Carry Generator 4-Bit Barrel Shifter X X X X Magnitude Comparators Description 4-Bit 8-Bit Type of Output P = Q 2S 2S 2S 2S 2S X X X X X X 8-Bit with Output Enable Parity Generators/Checkers Description 9-Bit Odd Even Parity Generator Checker X VCOs and Multivibrators Description Retriggerable Monostable Multivibrator Dual 122 Precision Non-Retriggerable Monostable Multivibrator X X Transceivers Description Quad. Inverting Hex. 83 283 181 381 382 182 350 LS X X X FAST Buffers/Line Drivers Description X X X X X X Quad 2-Input NOR Quad 2-Input NAND Dual 4-Input NAND Quad. Non-Inverting Quad. Non-Inverting No. 122 123 221 LS X X X FAST 10-Bit Bus Pinout FAST X Hex. 803 1803 LS FAST X X FAST AND LS TTL DATA 1-6 . Non-Inverting 3S 3S 3S 3S 3S 3S 3S 3S 3S 3S 3S 3S 3S 3S No. Non-Inverting Type of Output 2S OC 2S OC 2S 3S 3S P>Q X X X P<Q X No. 280 LS X FAST X Octal. FutureBus Quad. Inverting Register Octal w/ Parity Gen/Checker Clock Drivers Description Quad Matched Propagation Delays Clock Driver No. Inverting Octal. Non-Inverting Register Latch Octal.

Circuit Characteristics 2 FAST AND LS TTL .

CIRCUIT CHARACTERISTICS FAMILY CHARACTERISTICS LS TTL The Low Power Schottky (LSTTL) family combines a current and power reduction improvement over standard 7400 TTL by a factor of 5. FAST circuits contain additional circuitry to provide a flatter power/frequency curve. CIRCUIT FEATURES Circuit features of LS and FAST are best understood by examining the TTL 2-input NAND gate of each family (Figures 2-1a. Also.5K Q3 Figure 2-1a. The input/output circuits of other functions are almost identical.1K Figure 2-1b. The input configuration of FAST uses a lower input current which translates into higher fanout.6K Q2 Q4 5K OUTPUT B D2 D4 15K 2. b). LS00 — 2-Input NAND Gate VCC 35 Ω 10K D5 A D3 D1 D6 B D2 15K 2K 3K Q3 D7 D4 Q1 D8 Q5 D9 Q9 5K OUTPUT D10 10K Q6 Q2 Q4 4.8K Q1 Q5 3. This is accomplished by using Schottky diode clamping to prevent saturation and advanced processing. VCC 110 Ω 18K A D1 D3 7. FAST TTL The FAST Schottky TTL family provides a 75 – 80% power reduction compared to standard Schottky (54/74S) TTL and yet offers a 20 – 40% improvement in circuit performance over the standard Schottky due to the MOSAIC process. F00 — 2-Input NAND Gate FAST AND LS TTL DATA 2-2 .

0 V. Typical Output versus Input Voltage Characteristic FAST AND LS TTL DATA 2-3 . which limits undershoot and helps to control ringing on long signal lines following a HIGH-to-LOW transition.6 0.INPUT CONFIGURATION. Typical transfer characteristics can be found in Figure 2-5 and input threshold variation with temperature information is provided in Table 2-1. These diodes conduct when an input signal goes negative. Compared to the classical multi-emitter structure. This is required due to the high speed response of FAST™ logic. All inputs are provided with clamping diodes. a relatively large device in current bipolar logic technology. OUTPUT VOLTAGE (VOLTS) 0 –100 LS I IN ( µA) –200 –300 –400 TA = 25°C VCC = 5 V 0 0. Both the diode cluster arrangement and the PNP input configuration have breakdown voltage ratings greater than 7.8 1 1. 5 V OUT . Motorola LSTTL circuits do not use the multi-emitter input structure that originally gave TTL its name. PNP Input INPUT CHARACTERISTICS — Figure 2-4 shows the typical input characteristics of LS and FAST™. These diodes are intended only for the suppression of transient currents and should not be used as steady-state clamps in interface applications.6 1.5 1 1. A third input configuration that is sometimes used in LS TTL employs a vertical PNP transistor as shown in Figure 2-3. Most LS elements use a DTL type input circuit with Schottky diodes to perform the AND function. The F00 input configuration utilizes a PN diode (D5 and D6) rather than the PNP transistor. INPUT VOLTAGE (VOLTS) 2 2. This configuration gives a slightly higher input threshold than that of Figure 2-1a. A clamp current exceeding 2. Inputs of this type are tested for leakage with an applied input voltage of 7.8 2 FAST TA = 25°C VCC = 5 V 4 3 LS FAST 2 1 0 0. This arrangement also gives a higher input threshold and has the additional advantage of reducing the amount of current that the signal source must sink.5 Figure 2-4.5 VIN.2 0. VCC VCC Figure 2-2. b. The PN diode results in much better ac noise immunity at the expense of increased input current. as exemplified by D3 and D4 in Figure 2-1a. Typical Input Current versus Input Voltage Figure 2-5. Diode Cluster Input Figure 2-3. which in turn can steal current from internal nodes of an LS circuit and thus cause logic errors.4 1.0 mA and with a duration greater than 500 ns can activate a parasitic lateral NPN transistor. Another input arrangement often used in LS MSI has three diodes connected as shown in Figure 2-2.2 VIN (VOLTS) 1. has an associated capacitance large enough to make the gate input susceptible to ac noise.0 V and the input breakdown voltage is typically 15 V or more.4 0. exemplified by D1 and D2 in Figure 2-1a. The PNP transistor. this circuit is faster and increases the input breakdown voltage.

1 0. FAST™ 3-state outputs have some additional circuitry due to the nature of the environment in which they are used.0K resistor to the output terminals.0 pF for 24 mA outputs and about 12 pF for 64 mA outputs. This arrangement is called a squaring network since it squares up the transfer characteristics (Figure 2-5) by preventing conduction in the phase splitter Q1 until the input voltage rises high enough to allow Q1 to supply base current to Q5. In the high Z state. Typical 3-State Output Control OUTPUT CHARACTERISTICS. which allows the outputs of two or more such circuits to be connected together in a bus application wherein only one output is enabled at any particular time. The addition of Q10 reduces this effect by clamping the base of Q5 low when the device is in the high impedance state. Figure 2-6 shows the extra circuitry used to obtain the “high Z” condition in 3-state outputs. Referring to Figures 2-1a. VCC OUTPUT FROM LOGIC ACTIVE PULLDOWN OUTPUT ENABLE Q10 (FAST ONLY) Q5 FAST ONLY Figure 2-6. D8. The effective capacitive load of a 3-state output tends to increase at high bus rates.3 1.1 Typical Input Threshold Variation With Temperature FAST ALS S LS 1.8 1. both the phase splitter and the Darlington pull-up are turned off. The output circuitry of LSTTL has several features not found in conventional TTL. b. The output pull-up circuit is a 2-transistor Darlington circuit with the base of the output transistor returned through a 5. In this condition the output circuitry is non-conducting. Figure 2-8 shows the HIGH-state output characteristics.3 1.8 Table 2. unlike 74H and 74S where it is returned to ground which is a more power consuming configuration. Figure 2-7 shows the LOW-state output characteristics for LS and FAST™. A few of these features are discussed below. When the Output Enable signal is HIGH. the base of the pull-down output transistor Q5 is returned to ground through Q3 and a pair of resistors instead of through a simple resistor. For LOW IOL values.– 55°C + 25°C 1.5 1. The squaring network also improves the propagation delay by providing a low resistance path to discharge capacitance at the base of Q5 during turn-off.2 OUTPUT CONFIGURATION. the output capacitance is about 5. The F00 output configuration also includes additional circuitry to improve the rise time and decrease the power consumption at high operating frequencies.5 1. D7. which consists of Q9.5 1. As with the input diode clamps. and D9 causes Q5 to off more quickly on LOW to HIGH output transitions. The F00 output includes clamping diodes to limit undershoot and control ringing on long signal lines. these diodes are intended for transient suppression only and should not be used as steady-state clamps. FAST AND LS TTL DATA 2-4 .0 + 125°C 1.3 1.8 1. the pull-down transistor is clamped out of deep saturation to shorten the turn-off delay. An additional feature of many FAST™ 3-state devices is the incorporation of power-up circuitry to guarantee that the output will not sink current if the device is disabled during the application or removal of power. This configuration allows the output to pull up to one VBE below VCC for low values of output current. This circuit.

limits are guaranteed at 25°C.5 V 3 4 Figure 2-7b. VCC = 5. the delay through a logic-element will increase to some extent when multiple outputs switch simultaneously due to inductance internal to the IC package.5 Figure 2-9 Figure 2-10 FAST AND LS TTL DATA 2-5 .25 VCC. OUTPUT CURRENT (mA) Figure 2-7a. The propagation through a logic element depends on power supply voltage. OUTPUT VOLTAGE (VOLTS) V OL . OUTPUT CURRENT (mA) 60 0 50 100 150 200 IOL. Output Low Characteristic 4 V OH. and CL = 15 pF (normally. OUTPUT VOLTAGE (VOLTS) TA = 25°C VCC = 5. OUTPUT CURRENT (mA) –150 0 –50 –100 –150 IOH. Output Low Characteristic TA = 25°C VCC = 5.5 0.0 V.5 V F240 0. ambient temperature.5 V 3 LS240 2 F240 2 LS00 1 F00 1 0 –50 –100 IOH. The effect of each of these parameters on ac propagation is shown in Figures 2-9 through 2-11. Propagation delays are specified with only one output switching. SUPPLY VOLTAGE (V) 5.5 0 0 20 40 IOL. OUTPUT VOLTAGE (VOLTS) V OH. PROPAGATION DELAY CHANGE (ns) t PD .1 V OL .5 V LS00 F00 1 LS240 TA = 25°C VCC = 4. +4 t PD . For LS TTL. PROPAGATION DELAY CHANGE (ns) VCC = 5 V CL = 15 pF LS00 tPLH 0 tPHL –2 +4 TA = +25°C CL = 15 pF LS00 tPLH 0 tPHL –2 +2 +2 –4 –75 –25 +25 +75 TA. resistive load has minimal effect on propagation delay) FAST™ and TTL limits are guaranteed over the commercial or military temperature and supply voltage ranges and with CL = 50 pF. AMBIENT TEMPERATURE (°C) +125 –4 4. Output High Characteristic Figure 2-8b.5 4. and output load. This effect can be seen by comparing Figures 2-11c and 2-11d.75 5 5. OUTPUT VOLTAGE (VOLTS) TA = 25°C VCC = 4. Output High Characteristic AC SWITCHING CHARACTERISTICS. OUTPUT CURRENT (mA) –200 Figure 2-8a.

LOAD CAPACITANCE (pF) 1000 VCC = 5 V TA = 25°C F240 All Outputs Driven 0 0 500 CL. PROPAGATION DELAY (ns) 20 tPLH tPHL 10 tPLH tPHL 10 VCC = 5 V TA = 25°C F240 0 0 500 CL. For device specific values reference the following specifications: LS: FAST: 12MRM 93831A 12MRM 93830A FAST AND LS TTL DATA 2-6 . all of which meet Mil-Std-883C requirements. PROPAGATION DELAY (ns) t PD . PROPAGATION DELAY (ns) t PD . LOAD CAPACITANCE (pF) CL. tester specific information as well as actual device ESD hardness levels are given in controlled documents and are available upon request. CDM). LOAD CAPACITANCE (pF) Figure 2-11a* Figure 2-11b* 20 t PD . MM. It is extremely important to understand that ESD sensitivity values alone are not sufficient when comparing devices. In an attempt to reduce correlation problems between various pieces of test equipment. LOAD CAPACITANCE (pF) 1000 Figure 2-11c* Figure 2-11d* *Data for Figures 2-11a through 2-11c was taken with only one output switching at a time. Electrostatic Discharge (ESD) sensitivity for Motorola TTL is characterized using several methodologies (HBM.20 t PD . Figure 2-11d data was taken with all 8 inputs of the F240 tied together. PROPAGATION DELAY (ns) VCC = 5 V TA = 25°C LS00 12 VCC = 5 V TA = 25°C F00 tPLH 16 9 12 tPLH 8 tPHL 6 tPHL 3 4 0 20 40 60 80 100 50 100 150 200 250 300 CL. LS/FAST ESD CHARACTERISTICS. The continuing improvements of ESD sensitivity through redesigns of Motorola TTL has resulted in minimum ESD levels for all new products and redesigns of >4000 volts for FAST and >3500 volts for LS.

Design Considerations. Testing and Applications Assistance Form 3 FAST AND LS TTL FAST AND LS TTL DATA 3-1 .

5 0. Table 3.4 2.75 2. 93S00 Low Power Schottky TTL 54/74LS Advanced LS TTL.4 2.0 0.0 2. The numbers given above are guaranteed worst-case values.0 2. as well as maximum rated load.5 0.0 2. in new designs. 54/74F 0. Table 3.5 0.4 0.4 2.0 2.3 0.2 represents “worst case” limits and assumes a maximum power supply and temperature variation across the IC’s which are interconnected.5 0.5 Commercial (0 to 70°C) VIL 0.8 0.8 0. 54/74ALS Advanced S TTL.8 0.2c LOW Level Noise Margins (Commercial) To From LS S ALS FAST™ From “VOL” to “VIL” LS 300 300 300 300 S 300 300 300 300 ALS 300 300 300 300 FAST 300 300 300 300 Unit mV mV mV mV Table 3.0 2.5 2.4 0. FAST AND LS TTL DATA 3-2 .0 2.4 VOH 2.5 VIL 0.7 0. For instance.5 2.8 0. NOISE IMMUNITY.8 VIH 2.0 2.2a LOW Level Noise Margins (Military) To From LS S ALS FAST™ From “VOL” to “VIL” LS 300 200 300 200 S 400 300 400 300 ALS 400 300 400 300 FAST 400 300 400 300 Unit mV mV mV mV Table 3.DESIGN CONSIDERATIONS SELECTING TTL LOGIC. When mixing TTL families it is often desirable to know the guaranteed noise immunity for both LOW and HIGH logic levels.8 0. The ratio of ALS to FAST™ will depend on overall system design goals.8 0. Care must be taken when switching multiple gates at high frequencies to assure that their combined dissipation does not exceed package and/or device capabilities.0 VOL 0.0 VOL 0.4 2.7 2.8 0.2 specifies these noise margins for systems containing LS. Note that Table 3. TTL devices are more efficient at high frequencies than CMOS.7 2.0 2.8 2.7 0.3 0.5 0.0 2.2d HIGH Level Noise Margins (Commercial) To From LS S ALS (5% VCC) FAST (5% VCC) ALS (10% VCC) FAST (10% VCC) From “VOH” to “VIH” LS 700 700 750 700 500 500 S 700 700 750 700 500 500 ALS 700 700 750 700 500 500 FAST 700 700 750 700 500 500 Unit mV mV mV mV mV mV POWER CONSUMPTION.8 0. ALS and/or FAST™ TTL. S. TTL Families may be mixed in a system for optimum performance. ALS would commonly be used in non-critical speed paths to minimize power consumption while FAST™ TTL would be used in high speed paths.4 0.8 VIH 2.1 Worst Case TTL Logic Levels Electrical Characteristics Military (– 55 to +125°C) TTL Families TTL HTTL LPTTL STTL LSTTL ALS TTL FAST TTL Standard TTL 9000.8 0.0 2.5 2. Table 3.0 2.4 0. Table 3.5 2.4 2.2b HIGH Level Noise Margins (Military) To From LS S ALS FAST™ From “VOH” to “VIH” LS 500 500 500 500 S 500 500 500 500 ALS 500 500 500 500 FAST 500 500 500 500 Unit mV mV mV mV Table 3. all logic families exhibit increased power consumption at high frequencies. 54/74 High Speed TTL 54/74H Low Power TTL 93L00 (MSI) Schottky TTL 54/74S.8 0. With the exception of ECL.4 0.0 2. Increased noise immunity can be achieved by designing with decreased maximum allowable operating ranges.5 VOH 2.1 lists the guaranteed logic levels for various TTL families and can be used to calculate noise margin.0 2.4 2.7 2.5 0.8 0.5 Unit V V V V V V V V V (5% VCC) (10% VCC) (5% VCC) (10% VCC) VOL and VOH are the voltages generated at the output VIL and VIH are the voltage required at the input to generate the appropriate levels.

L.L. 1 U. The normalized output LOW drive factor is: 8. 12.5 U. is specified as having an input LOW load factor of: 0. 40 µA Relative load and drive factors for the basic TTL families are given in Table 3.25 U.L.L.) = 1.L.L LOW 0. (Also called a fan-in of 1 load. OUTPUT DRIVE Table 3.5 U. 1.) 2.L.4 mA or 0.L.5 U.L. 1 U.5 U.8 mA 40 µA or 0. 1.25 U.5 U.6 mA 40 µA 3.L 0.375 U. 1 U.25 U. 12. INPUT LOAD FAMILY HIGH 74LS00 7400 9000 74H00 74S00 74 ALS 74 FAST 0.4 mA and an IIH of 20 µA.25 U. the input and output loading parameters of all families are normalized to the following values: 1 TTL Unit Load (U. 1.L.L.L. 10 U.L.5 U. 40 µA 2.L.6 mA and the output HIGH drive factor is 800 µA or 20 U. LOW 5 U.25 U. 1 U. Consult the appropriate data sheet for actual characteristics. In order to simplify designing with Motorola TTL devices.L.6 mA in the LOW state (Logic “0”) Input loading and output drive factors of all products described in this handbook are related to these definitions. A 7400 gate.L.L. 25 U.L 0.L. 10 U. The 74LS00 gate which has an IIL of 0. 5 U. has an input LOW load factor of: 0.0625 U.3.3 Values for MSI devices vary significantly from one element to another. 1.L.L.L. The output of the 74LS00 will sink 8. 0. and an input HIGH load factor of or 1 U. 25 U.8 mA and IIH of 40 µA on the CP terminal.FAN-IN AND FAN-OUT.L.0 mA in the LOW state and source 400 µA in the HIGH state.5 U.L.L. 10 U.5 U.L 0. 1.L. 25 U. EXAMPLES — OUTPUT DRIVE 1.L.6 mA and IIH of 40 µA is specified as having an input load factor of 1 U.L.L. an input HIGH load factor of 1. 12. 1. EXAMPLES — INPUT LOAD 1. The output of the 7400 will sink 16 mA in the LOW (logic “0”) state and source 800 µA in the HIGH (logic “1”) state.6 mA 20 µA 40 µA or 0.L.L.L.L.L. HIGH 10 U. The 74LS95B which has a value of IIL = 0. which has a maximum IIL of 1. 1. 20 U. FAST AND LS TTL DATA 3-3 .L.0 mA = 5 U.) = 40 µA in the HIGH state (Logic “1”) 1 TTL Unit Load (U.L.L.6 mA and the output HIGH drive factor is 400 µA or 10 U. The normalized output LOW drive factor is therefore: 16 mA = 10 U. 20 U.25 U.

LS and FAST™ TTL inputs have an average capacitance of 5. UNUSED INPUTS. Connect the unused input to the output of an unused gate that is forced HIGH.5 V) = Output HIGH Voltage Level (2.6 mA 4. each additional function adds approximately 1. = 1 U. = 4 • 0. The pull-up resistor value is chosen from a range between maximum value (established to maintain the required VOH with all the OR tied outputs HIGH) and a minimum value (established so that the OR tie fan-out is not exceeded when only one output is LOW). recommended for normal TTL.9 kΩ can be used.L. The value of the pull-up resistor is determined by considering the fan-out of the OR tie and the number of devices in the OR tie.L.48 mA RX(MIN) = 4. but should be held between 2. For best noise immunity and switching speed. = 2 U. This method. 2.L.5 U. 5. As a rule of thumb. For an input that serves more than one internal function. Two possible ways of handling unused inputs are: 1.0 mA = 0.25 U.4 V) = Power Supply Voltage Example: Four 74LS03 gate outputs driving four other LS gates or MSI inputs. therefore no series resistor. CAUTION: Do not connect an unused LS or FAST ™ input to another input of the same NAND or AND function.L. INPUT CAPACITANCE. MINIMUM AND MAXIMUM PULL-UP RESISTOR VALUES RX(MIN) = VCC(MAX) – VOL IOL – N2(LOW) • 1.35 V = 4. unused TTL inputs should not be left floating. Certain TTL devices are provided with an “open” collector output to permit the Wired-OR (actually Wired-AND) function.25 V – 0.75 V = 742 Ω 6.5 V = 2.) being Driven = Output HIGH Leakage Current = LOW Level Fan-out Current of Driving Element = Output LOW Voltage Level (0.WIRED-OR APPLICATIONS. Connect unused input to VCC.5 pF.4 V Any value of pull-up resistor between 742 Ω and 4. increases the input coupling capacitance and thus reduces the ac noise immunity. LS and FAST™ TTL inputs have a breakdown voltage > 7. = 100 µA = 8.5 V = 8.9 kΩ 0.4 V RX(MAX) = 4 • 100 µA + 2 • 40 µA = where: N1 N2 (HIGH) N2 (LOW) IOH IOL VOL VOH =4 = 4 • 0.6 mA where: Rx N1 N2 IOH = ICEX IOL VOL VOH VCC RX(MAX) = VCC(MIN) – VOH N1 • IOH + N2(HIGH) • 40 µA = External Pull-up Resistor = Number of Wired-OR Outputs = Number of Input Unit Loads (U. This is achieved by connecting open collector outputs together and adding an external pull-up resistor.0 V and require.4 V and the absolute maximum input voltage.4 mA 2.0 mA – 1. The lower values yield the fastest speeds while the higher values yield the lowest power dissipation.0 pF for DIP packages.L.75 V – 2. FAST AND LS TTL DATA 3-4 .

2-4. while the last one to receive a full signal is the one nearest the driver since it must wait for the reflection to complete the transition.g. It is also often necessary to construct load lines to determine reflection waveforms in line driving applications.0 –20 to –100 –15 24 –40 to –225 54Fxxx 5 ± 10% –1. because of the doubling effect. is subtractive and has the effect of reducing the apparent amplitude of the signal. a reflection voltage is generated which has the same amplitude and polarity as the original signal. and as it travels back toward the driver it adds to the line voltage. ground planes give higher distributed capacitance and delays of about 0.4. Exceptions occur in systems using ground planes to reduce ground noise during a logic transition. In the limit. and each capacitance also slows the transition rate of the signal as it passes by. TTL logic is often used in line driving applications which require various termination techniques to maintain signal integrity. This attenuated signal travels to the far end of the interconnection. These range from about 0.15 ns/inch for the type of interconnections normally used in TTL systems. the driver output waveform exhibits noticeable slope changes during a transition.LINE DRIVING — Because of its superior capacitive drive characteristics. The input and output characteristics graphs of section 3 (Figs. This is evidence that during the initial portion of the output voltage transition the driver sees the characteristic impedance of the interconnection (normally 100 Ω to 200 Ω). designers should take into account the finite delay along the interconnections. tending to produce a signal transition having the same rise or fall time as in the no-load condition but with a reduced amplitude.0 ns for FAST™ with a 50 pF load (measured 10 – 90%).0 –20 to –100 –12 12 –40 to –225 LS 74LSxxx 5 ± 5% –0. When an interconnection is long enough that its delay is one-fourth to one-half of the signal transition time. in a worst-case situation. whereupon the signal starts doubling. OUTPUT RISE AND FALL TIMES provide important information in determining reflection waveforms and crosstalk coefficients. A rough but workable approach is to treat the load capacitances as an increase in the intrinsic distributed capacitance of the interconnection. At the instant the reflection arrives at the driver it adds algebraically to the still-rising driver output. Thus.15 to 0.4 8.. accelerating the transition rate and producing the noticeable change in slope. A good approximation for ordinary TTL interconnections is that distributed load capacitance decreases the characteristic impedance by about one-third and increases the delay by one-half. the waveform observed at the driver output is a 2-step signal with a pedestal. e. This characteristic impedance forms a voltage divider with the driver output impedance.22 ns/inch. Parameters associated with this application are listed in Table 3. the input capacitance of each will cause a small reflection having a polarity opposite that of the signal transition. which is essentially an unterminated transmission line. When load circuits are distributed along an interconnection. (ALL MAXIMUM RATINGS) Characteristic Operating Voltage Range Output Drive: Standard Output Symbol VCC IOH IOL ISC IOH Buffer Output IOL ISC 54LSxxx 5 ± 10% –0. FAST AND LS TTL DATA 3-5 . which for transient conditions appears as a resistor returned to the quiescent voltage existing just before the beginning of the transition. Most interconnections on a logic board are short enough that the wiring and load capacitance can be treated as a lumped capacitance for purposes of estimating their effect on the propagation delay of the driving circuit. the attenuated output of the driver has time to reach substantial completion before the reflection arrives. Increasing the distributed capacitance of a transmission line reduces its impedance and increases its delay. if the driver output signal is positive-going the reflection will be positive-going. The successive slowing of the transition rate of the transmitted signal means that it takes longer for the signal to rise or fall to the threshold level of any particular load circuit. 2-7 and 2-8) can be very useful for this purpose. Typical rise and fall times are approximately 6 ns for LS and about 2. INTERCONNECTION DELAYS.4 4. Output rise and fall times become longer as capacitive load is increased. Simultaneously.0 20 FAST 74Fxxx 5 ± 10% –1. the net contribution to the overall delay is twice the delay of the interconnection because the initial part of the signal must travel to the far end of the line and the reflection must return. In this circumstance the first load circuit to receive a full signal is the one at the far end.0 20 –60 to –150 –15 64 –100 to –225 Unit Vdc mA mA mA mA mA mA –60 to –150 –12 48 –100 to –225 Table 3. The series of small reflections.12 to 0.4 Output Characteristics for Schottky TTL Logic If an interconnection is of such length that its delay is longer than half the signal transition time. For those parts of a system in which timing is critical. arriving back at the driver.

Device types having inputs limited to 5.0 V – 0. CHARACTERISTIC Storage Temperature Temperature (Ambient) Under Bias VCC Pin Potential to Ground Pin *Input Voltage (dc) Diode Inputs *Input Current (dc) Voltage Applied to Open Collector Outputs (Output HIGH) High Level Voltage Applied to Disabled 3-State Output Current Applied to Output in Low State (Max) LS – 65°C to + 150°C – 55°C to + 125°C – 0.0 mA – 0. — Multiplexer Inputs.ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired) Functional operation under these conditions is not implied. — Inputs connected to outputs. — Certain Inputs.5 V to + 7.0 V – 0.5 V to + 7. FAST AND LS TTL DATA 3-6 .5 V to + 5.5 V are as follows: SN74LS242/243.5 V to 7.0 V – 30 mA to + 5.5 V maximum limits *are listed below.5 V Twice Rated IOL *Either input voltage limit or input current limit is sufficient to protect the inputs — Circuits with 5.5 V 5.5 V Twice Rated IOL FAST – 65°C to + 150°C – 55°C to + 125°C – 0.5 V to 15 V – 30 mA to + 5.5 V to + 10 V 5.0 mA – 0. SN74LS245 SN74LS640/641/642/645 SN74LS299/322A/323 SN74LS151/251 — Inputs connected to outputs.

Output LOW current — The current flowing into an output which is in the LOW state. Input LOW current — The current flowing out of an input when a specified LOW voltage is applied to that input. Negative voltage limits are specified as absolute values (i. This parameter guarantees the integrity of the input diode which is intended to clamp negative ringing at the input terminal. This value represents the guaranteed input HIGH threshold for the device.. For devices with a pull-up circuit. Maximum input LOW voltage — The maximum allowed input LOW in a system. Output HIGH voltage — The minimum guaranteed voltage at an output terminal for the specified output current IOH and at the minimum value of VCC. Output short-circuit current — The current flowing out of an output which is in the HIGH state when that output is short circuit to ground (or other specified potential). This value represents the guaranteed input LOW threshold for the device. Output off current LOW — The current flowing out of a disabled 3-state output with a specified LOW output voltage applied. Schmitt Trigger) that is interpreted as a VIH as the input transition rises from below VT–(MIN).DEFINITION OF SYMBOLS AND TERMS USED IN THIS DATA BOOK CURRENTS — Positive current is defined as conventional current flow into a device. VIH VIH(MIN) VIL VIL(MAX) VOH(MIN) VOL(MAX) VT+ VT– FAST AND LS TTL DATA 3-7 .0 V). Negative-going threshold voltage — The input voltage of a variable threshold device (ie. Output LOW voltage — The maximum guaranteed voltage at an output terminal sinking the maximum specified load current IOL. Positive-going threshold voltage — The input voltage of a variable threshold device (ie. ICC IIH IIL IOH Supply Current  The current flowing into the VCC supply terminal of a circuit with the specified input conditions and the outputs open. input conditions are chosen to guarantee worst case operation. Minimum input HIGH voltage — The minimum allowed input HIGH in a logic system. the IOH is the current flowing out of an output which is in the HIGH state. Negative current is defined as conventional current flow out of a device. The leakage current flowing into a turned off open collector output with a specified HIGH output voltage applied. Input HIGH current — The current flowing into an input when a specified HIGH voltage is applied to that input. Output HIGH current. When not specified. Input LOW voltage — The range of input voltages recognized by the device as a logic LOW. VCC VIK(MAX) Supply voltage — The range of power supply voltage over which the device is guaranteed to operate within the specified limits.e. Output off current HIGH — The current flowing into a disabled 3-state output with a specified HIGH output voltage applied. Input HIGH voltage — The range of input voltages recognized by the device as a logic HIGH. Schmitt Trigger) that is interpreted as a VIL as the input transition falls from above VT+(MAX). All current limits are specified as absolute values.. IOL IOS IOZH IOZL VOLTAGES — All voltages are referenced to ground. Input clamp diode voltage — The most negative voltage at an input when the specified current is forced out of that input terminal. – 10 V is greater than –1..

3 V for LS and 1. with the output changing from the defined LOW level to the defined HIGH level. on the input and output voltage waveforms. measured the 90% to the 10% points of the waveform. on the input and output voltage waveforms. HIGH-TO-LOW propagation delay time: The time delay between specified reference points. Waveform Fall Time: HIGH to LOW logic transition time.5 V . Enable tPZH Enable tPZH tPHZ VOH ≈ 3. typically 1. with the output changing from the defined HIGH level to the defined LOW level.5 V for FAST. measured from the 10% to 90% points of the waveform. typically 1.5 for LS .3 for FAST Vout FAST AND LS TTL DATA 3-8 . with the 3-state output changing from the defined HIGH level to a high impedance (OFF) state. Reference point on the output voltage waveform is VOH – 0.5 V for LS and VOH – 0. with the 3-state output changing from a high impedance (OFF) state to a HIGH level. Output enable time: Z to HIGH The time delay between the specified reference points on the input and output voltage waveforms.AC SWITCHING PARAMETERS AND WAVEFORMS tPLH LOW-TO-HIGH propagation delay time : The time delay between specified reference points.3 V for LS and 1.3 V for FAST. For Inverting Function For Non-Inverting tPHL VIN Vout tPHL tPLH VIN tPLH tPHL Vout tr tf Waveform Rise Time: LOW to HIGH logic transition time.5 V for FAST. tr 90% 90% tf 10% 10% tPHZ Output disable time: HIGH to Z The time delay between the specified reference points on the input and output voltage waveforms.

Enable tPZL Enable Vout tPZL tPLZ VOZ = 1.5 V . to insure that the device will properly respond to the synchronous signal.tPLZ Output disable time: LOW to Z The time delay between the specified reference points on the input and output voltage waveforms.3 for FAST trec Recovery time Time required between an asynchronous signal (SET. Output enable time: Z to LOW The time delay between the specified reference points on the input and output voltage waveforms with the 3-state output changing from a high impedance (OFF) state to a HIGH level.5 for LS . Asynch Asynch trec Control th Hold Time The interval of time from the active edge of the control signal (usually the clock) to when the data to be recognized is no longer required to ensure proper interpretation of the data. Setup time The interval of time during which the data to be recognized is required to remain constant prior to the active edge of the control signal to ensure proper data recognition. RESET.3 V for FAST. A negative hold time indicates that the data may be removed at some time prior to the active edge of the control signal. CLEAR or PARALLEL load) and the active edge of a synchronous control signal. A negative setup time indicates that data may be initiated sometime after the active transition of the timing pulse and still be recognized.5 V for LS and VOL + 0. Reference point on the output voltage waveform is VOL + 0. with the 3-state output changing from the defined LOW level to a high impedance (OFF) state. ts VIN ts(L) CP th(L) VIN ts(H) CP th(H) FAST AND LS TTL DATA 3-9 .

twL twH fMAX Toggle frequency/operating frequency The maximum rate at which clock pulses meeting the clock requirements (ie. tWL. tf) may be applied to a sequential circuit.7.. or 0.4 V Measure IO Io DUT ICC TEST Measure ICC VCC MAX ± Vo GND or 4.5 V for FAST™) on the leading and trailing edges of a pulse. IIH. Guaranteed maximum clock frequency The lowest possible value for fMAX. VOH AND VOL TESTS Force IOHMAX or IOLMAX Measure VOH or VOL IIHH. and tr.3 V for LS and 1. tWH.5. input conditions are selected to produce a worst case condition. 2. Above this frequency the device may cease to function. IOZH. or IIL DUT + Io Vo Vi IOS TEST VIHMIN or VILMAX Measure IOS DUT VIHMIN or VILMAX DUT VIK TEST Force Ii Measure VIK + Vik – DUT Ii = –18 mA IOH.4 V Measure IIHH. FAST AND LS TTL DATA 3-10 . 5. fMAXmin TESTING DC TEST CIRCUITS The following test circuits and forcing functions represent Motorola’s typical DC test procedures.5 V* DUT Outputs Open *Unless otherwise indicated. and IOZL TESTS Force 5. IIH AND IIL TESTS Force 7. 2.4.tw or tpw Pulse width The time between the specified amplitude points (1.5. or 0.

So although the Trigger threshold of any given device will correlate well between any test system. The following test circuits and conditions represent Motorola’s typical test procedures. Dynamic Noise contribution to apparent input threshold VIN The VIN versus VOUT plot shows the practical effect of testing noise on a logic IC device. and only (for noise reasons above) after setting the device state with a hard level.8 V and 2. For this reason Motorola does not recommend functional testing of TTL devices using threshold levels of 0. Bypassing with both electrolytic and high quality RF type capacitors should be provided on the board. Following these rules will result in cleaner waveforms as well as better correlation between Motorola and the FAST™ TTL consumer. Input threshold voltages should be tested separately. The device will oscillate if the input voltage does not exceed the trigger threshold plus the noise generated by the interaction of the test system or given application with the device. the correlation of “Dynamic” threshold cannot be made directly and will have meaning only in a relative sense. as well as the use of multilayer boards with internal VCC and ground planes is highly recommended for FAST™ TTL.4 V VIH to be applied for functional testing. is the input logic level required to overcome the interactive DYNAMIC NOISE generated by a device switching states. FUNCTIONAL TESTING OF TTL IN A NOISY ENVIRONMENT/“DYNAMIC” THRESHOLD Testing noise (noise generated by the test system itself and noise generated by TTL devices under test interacting with the test system) adds to. Lead lengths for all components should be kept as short as possible (Motorola uses and recommends chip capacitors and resistors for ac test fixtures). A simple number cannot be assigned to this parameter as it is heavily dependent on any given application or test environment. good TTL testing techniques call for hard levels of less than 0. AC waveforms and terminology can be found on pages 3-8 to 3-10.5 V VIL and greater than 2. This is especially true of FAST™ TTL. The amount of interactive DYNAMIC NOISE can be characterized by the difference between the Trigger threshold and the Dynamic threshold of the device under test. Maintaining a 50 Ω environment on the ac test fixture.0 V. VOUT Trigger Threshold VOH VOL Dynamic Threshold Region of output instability. Instead. FAST AND LS TTL DATA 3-11 . The Dynamic threshold (that creates Quiescent outputs). or subtracts from the threshold voltage applied to the TTL device under test.AC TEST CIRCUITS. The actual device Trigger threshold is represented by the initial low to high output transition. Proper testing requires that care be taken in the construction of AC test fixtures.

tPLZ.5 ns 0 to 3 V VIN PULSE GEN 51 Ω DUT 15 pF* VOUT * The specified propagation delay limits can be guaranteed with a 15 ns input rise time on all parameters except those requiring narrow pulse widths. Any frequency measurement over 15 MHz or pulse width less than 30 ns must be performed with a 6 ns input rise time. ALL OTHER R1 500 Ω Optional LS Load (Guaranteed—Not Tested) VCC DUT 50 pF* R2 500 Ω RL *includes all probe and jig capacitance CL FAST AND LS TTL DATA 3-12 .C. O.LS TEST CIRCUITS Test Circuit for Standard Output Devices VCC PULSE GENERATOR SETTINGS (UNLESS OTHERWISE SPECIFIED) LS Frequency = 1 MHz Duty Cycle = 50% 1 TLH (tr) = 6 ns (15)* 1 THL (tf) = 6 ns (15)* Amplitude = 0 to 3 V FAST 1 MHz 50% 2. Test Circuit for Open Collector Output Devices VCC VCC RL VIN PULSE GEN 51 Ω 15 pF* DUT VOUT FAST TEST CIRCUITS +7 V OPEN *includes all probe and jig capacitance tPZL.5 ns 2.

AZ 85202. plots or sketches of relevent inputs and outputs with voltages and time divisions clearly identified for all waveforms are greatly desirable.. Please fill out as much of the form as is possible if you are contacting Motorola for assistance or are sending devices back to Motorola for analysis.. voltage expected.APPLICATIONS ASSISTANCE FORM In the event that you have any questions or concerns about the performance of any Motorola device listed in this catalog. driving devices or devices being driven . does customer have viable alternate vendor(s) for device type? Yes No Alternate vendor’s name 6) Date code(s) and Serial Number(s) of devices returned for correlation — If possible. Mesa. Job Title: Phone/Position: Company: FAST AND LS TTL DATA 3-13 . floating. stimulated but not under test. > Are there specific circumstances that seem to make the questionable unit(s) worse? Better? Temperature VCC Input rise/fall time Output loading (current/capacitance) Others > ATE functional data should include pattern with decoding key and critical parameters such as VCC. Broadway. 1) Name of Person Requesting Correlation: Phone No: 2) Alternate Contact: 3) Device Type (user part number): 4) Industry Generic Device Type: 5) # of devices tested/sampled: # of devices in question*: # returned for correlation: * In the event of 100% failure. whatever . clamps. Func step rate. Ground & VCC measurements should be made as physically close to the device in question as possible. If further information is required.). time to measure. Your information can greatly improve the accuracy of analysis and can dramatically improve the correlation response and resolution time. please contact your local Motorola sales office or the Motorola Help line for assistance. input voltages. low. MOTOROLA Device Correlation/Component Analysis Request Form — Please fill out entire form and return with devices to MOTOROLA INC..g. > VCC and Ground waveforms should be carefully described as these characteristics vary greatly between applications and test systems. Potentially critical information includes: Input waveform timing relationships Input edge rates Input Overshoot or Undershoot — Magnitude and Duration Output Overshoot or Undershoot — Magnitude and Duration > Photographs. under test. It can be used as a self-help diagnostic guideline or for a baseline of information gathering to begin a dialog with Motorola representatives.. caps. high. including any input or output loading conditions (resistors.. R&QA DEPT. please provide one or two “good” units (Motorola’s and/or other vendor) for comparison: 7) Describe USER process that device(s) are questionable in: Incoming component inspection {test system = ?}: Design prototyping: Board test/burn-in: Other (please describe): 8) Please describe the device correlation operating parameters as completely as possible for device(s) in question: > Describe all pin conditions (e. does Customer have other date codes of Motorola devices that pass inspection? Yes No Please specify passing date code(s) if applicable If none. 2200 W.). you can request direct factory assistance. Items 4 thru 8 of the following form contains important questions that can be invaluable in analyzing application or device problems. Dynamic characteristics of Ground and VCC during device switching can dramatically effect input and internal operating levels..

FAST AND LS TTL DATA 3-14 .

FAST Data Sheets FAST AND LS TTL 4 .

0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-2 .5 125 70 –1.MC54/74F00 QUAD 2-INPUT NAND GATE QUAD 2-INPUT NAND GATE VCC 14 13 12 11 10 9 8 FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 GND 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.0 25 25 Max 5. 74 54 74 IOH IOL Output Current — High Output Current — Low 54. 74 54. 74 Min 4.5 –55 0 Typ 5.

3 54F TA = –55°C to +125°C VCC = 5. VIN = 2. VIN = GND VCC = MAX.0 V ± 10% CL = 50 pF Min 2.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay Min 2.0 mA IOH = –1.5 Max 6.0 V ± 10% CL = 50 pF Min 2.0 5.8 –1. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.2 Min 2.7 V VCC = MAX. 2. Output LOW –60 –0.0 mA IOL = 20 mA VCC = 4. IIN = –18 mA IOH = –1.2 Typ Max Unit V V V V V V µA mA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.0 6.0 1. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2. VOUT = 0 V VCC = MAX. VIN = Open NOTES: 1.5 2. use the appropriate value specified under recommended operating conditions for the applicable device type.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total.5 Max 7.5 74F TA = 0°C to 70°C VCC = 5.5 Max 5. Not more than one output should be shorted at a time.50 V VCC = 4.6 –150 2. nor for more than 1 second.MC54/74F00 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54. VIN = 7.5 20 0.0 0. For conditions shown as MIN or MAX.7 0. Output HIGH Total.3 Unit ns ns FAST AND LS TTL DATA 4-3 . VIN = 0.4 1.0 V VCC = MAX.4 1.0 4.75 V VCC = MIN VCC = MAX.8 10.5 V VCC = MAX.

0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-4 . 74 54. 74 Min 4. 74 54 74 IOH IOL Output Current — High Output Current — Low 54.MC54/74F02 QUAD 2-INPUT NOR GATE QUAD 2-INPUT NOR GATE VCC 14 13 12 11 10 9 8 FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 GND 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.5 –55 0 Typ 5.5 125 70 –1.0 25 25 Max 5.

For conditions shown as MIN or MAX.5 20 0.5 2.7 0.5 Max 7.0 V VCC = MAX.3 Unit ns ns FAST AND LS TTL DATA 4-5 . 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.5 74F TA = 0°C to 70°C VCC = 5.5 5. VIN = 7. VOUT = 0 V VCC = MAX. Output LOW –60 –0. use the appropriate value specified under recommended operating conditions for the applicable device type.0 0. nor for more than 1 second. one input low for each gate.8 –1. VIN = 2.0 mA IOL = 20 mA VCC = 4.50 V VCC = 4. 3.5 Max 6.MC54/74F02 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54. Not more than one output should be shorted at a time. VIN = 0.6 13 Min 2.5 6.0 mA IOH = –1.7 V VCC = MAX. Measured with one input high. Output HIGH Total.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay Min 2.0 V ± 10% CL = 50 pF Min 2. VIN = Note 3 NOTES: 1.75 V VCC = MIN VCC = MAX.0 V ± 10% CL = 50 pF Min 2.5 1.5 V VCC = MAX.5 4. VIN = GND VCC = MAX. 2.3 54F TA = –55°C to +125°C VCC = 5.5 1.6 –150 5.5 Max 5.2 Typ Max Unit V V V V V V µA mA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN. IIN = –18 mA IOH = –1. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.5 1.

0 25 25 Max 5. 74 54 74 IOH IOL Output Current — High Output Current — Low 54. 74 54.0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-6 . 74 Min 4.5 –55 0 Typ 5.5 125 70 –1.MC54/74F04 HEX INVERTER HEX INVERTER FAST™ SCHOTTKY TTL VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 GND 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 D SUFFIX SOIC CASE 751A-02 1 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.

75 V VCC = MIN VCC = MAX.0 5.0 V VCC = MAX.7 0. use the appropriate value specified under recommended operating conditions for the applicable device type. VOUT = 0 V VCC = MAX. Output HIGH Total. 2.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total.4 1.0 6. For conditions shown as MIN or MAX.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay Min 2. nor for more than 1 second. IIN = –18 mA IOH = –1.0 V ± 10% CL = 50 pF Min 2.5 74F TA = 0°C to 70°C VCC = 5.8 –1. Output LOW –60 –0.0 0.7 V VCC = MAX.5 V VCC = MAX.2 Typ Max Unit V V V V V V µA mA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.0 V ± 10% CL = 50 pF Min 2. VIN = 0. VIN = 2.5 20 0. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.3 Min 2.0 1.5 Max 5. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2. VIN = Open NOTES: 1. Not more than one output should be shorted at a time.0 4.6 –150 4.0 mA IOL = 20 mA VCC = 4. VIN = GND VCC = MAX.50 V VCC = 4.2 15.3 54F TA = –55°C to +125°C VCC = 5.5 Max 7.5 2.5 MAX 6.0 mA IOH = –1.MC54/74F04 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.4 1.3 Unit ns ns FAST AND LS TTL DATA 4-7 . VIN = 7.

0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-8 . 74 54. 74 Min 4.5 125 70 –1.MC54/74F08 QUAD 2-INPUT AND GATE QUAD 2-INPUT AND GATE VCC 14 13 12 11 10 9 8 FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 GND 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.0 25 25 Max 5. 74 54 74 IOH IOL Output Current — High Output Current — Low 54.5 –55 0 Typ 5.

Output LOW –60 –0.6 5.0 V ± 10% CL = 50 pF Min 3. VIN = 7.0 2.6 –150 8. VIN = GND NOTES: 1.6 6.5 Max 5. Output HIGH Total.50 V VCC = 4.0 V VCC = MAX.5 2.7 0. For conditions shown as MIN or MAX. VIN = 2.3 Unit ns ns FAST AND LS TTL DATA 4-9 .2 Typ Max Unit V V V V V V µA mA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.5 74F TA = 0°C to 70°C VCC = 5. VIN = 0. Not more than one output should be shorted at a time. VOUT = 0 V VCC = MAX. 2.5 20 0.0 2. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.3 54F TA = –55°C to +125°C VCC = 5.3 12. IIN = –18 mA IOH = –1.5 Max 6.0 mA IOL = 20 mA VCC = 4.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total.5 2. VIN = Open VCC = MAX.0 mA IOH = –1.7 V VCC = MAX. use the appropriate value specified under recommended operating conditions for the applicable device type.9 Min 2.0 0. nor for more than 1 second.0 Max 7.MC54/74F08 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.8 –1.0 V ± 10% CL = 50 pF Min 2.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay Min 3. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.5 V VCC = MAX.5 7.75 V VCC = MIN VCC = MAX.

0 25 25 Max 5. 74 54.5 125 70 –1.MC54/74F10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 GND 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. 74 Min 4.0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-10 .5 –55 0 Typ 5. 74 54 74 IOH IOL Output Current — High Output Current — Low 54.

VIN = 7.2 Typ Max Unit V V V V V V µA mA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.5 Max 7.5 2. VIN = 0. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.5 20 0. IIN = –18 mA IOH = –1.3 Unit ns ns FAST AND LS TTL DATA 4-11 .6 –150 2.0 V ± 10% CL = 50 pF Min 2.MC54/74F10 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.0 mA IOL = 20 mA VCC = 4.5 74F TA = 0°C to 70°C VCC = 5.0 5. For conditions shown as MIN or MAX.0 0.0 V ± 10% CL = 50 pF Min 2.4 1. nor for more than 1 second.75 V VCC = MIN VCC = MAX. VIN = 2. Output LOW –60 –0.0 1. Not more than one output should be shorted at a time.50 V VCC = 4. VIN = Open NOTES: 1.4 1.7 0.5 Max 6.0 mA IOH = –1. use the appropriate value specified under recommended operating conditions for the applicable device type.1 7.0 V VCC = MAX.7 V VCC = MAX.3 54F TA = –55°C to +125°C VCC = 5.7 Min 2.5 Max 5. Output HIGH Total. 2. VIN = GND VCC = MAX.5 V VCC = MAX.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2. VOUT = 0 V VCC = MAX.0 6.8 –1.0 4.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay Min 2.

0 25 25 Max 5. 74 54 74 IOH IOL Output Current — High Output Current — Low 54.0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-12 .MC54/74F11 TRIPLE 3-INPUT AND GATE TRIPLE 3-INPUT AND GATE FAST™ SCHOTTKY TTL VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 1 2 3 4 5 6 7 GND N SUFFIX PLASTIC CASE 646-06 1 14 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. 74 Min 4.5 –55 0 Typ 5.5 125 70 –1. 74 54.

2 9. VIN = 2. use the appropriate value specified under recommended operating conditions for the applicable device type. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.5 Max 6.75 V VCC = MIN VCC = MAX.0 V ± 10% CL = 50 pF Min 3.5 54F TA = –55°C to +125°C VCC = 5.2 Typ Max Unit V V V V V V µA mA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.5 7.0 2.0 2. VOUT = 0 V VCC = MAX.0 0.MC54/74F11 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54. IIN = –18 mA IOH = –1. VIN = GND NOTES: 1. 2.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay Min 3.0 V VCC = MAX.8 –1. For conditions shown as MIN or MAX. Not more than one output should be shorted at a time.0 mA IOL = 20 mA VCC = 4.0 V ± 10% CL = 50 pF Min 2.5 20 0.5 2.7 0.0 Max 7.5 V VCC = MAX. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2. Output HIGH Total.7 Min 2. VIN = 7.50 V VCC = 4.6 5. Output LOW –60 –0.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total.5 Unit ns ns FAST AND LS TTL DATA 4-13 .6 6.5 Max 5.6 –150 6.7 V VCC = MAX.0 mA IOH = –1. VIN =Open VCC = MAX. VIN = 0.5 74F TA = 0°C to 70°C VCC = 5. nor for more than 1 second.5 2.

0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-14 . 74 54. They are capable of transforming slowly changing input signals into sharply defined. 74 54 74 IOH IOL Output Current — High Output Current — Low 54.0 25 25 Max 5. jitter-free output signals.5 –55 0 Typ 5. Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output.SCHMITT TRIGGERS DUAL 4-INPUT NAND/HEX INVERTERS The MC54/74F13 and MC54/74F14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels.5 125 70 –1. Additionally. LOGIC AND CONNECTION DIAGRAMS 14 MC54/74F13 MC54/74F14 SCHMITT TRIGGERS DUAL 4-INPUT NAND/HEX INVERTERS FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 1 MC54/74F13 VCC 14 D 13 C 12 N/C 11 B 10 A 9 O 8 14 1 N SUFFIX PLASTIC CASE 646-06 1 A 2 B 3 N/C 4 C 5 D 6 O 7 GND 14 1 D SUFFIX SOIC CASE 751A-02 MC54/74F14 VCC 14 A 13 O 12 A 11 O 10 A 9 O 8 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC 1 A 2 O 3 A 4 O 5 A 6 O 7 GND GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. they have greater noise margin than conventional inverters. The Schmitt trigger uses positive feedback to effectively speed up slow input transitions and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input thresholds (typically 800 mV) is determined internally by resistor ratios and is essentially insensitive to temperature and supply voltage variations. 74 Min 4.

5 3.1 Unit V V V V V V V V V mA mA µA mA mA mA Test Conditions VCC = 5.0 Max 8.7 V VCC = MAX.0 mA IOH = –1.18 20 0.5 3.MC54/74F13 • MC54/74F14 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VT+ VT– VT+–VT– VIH VIL VIK VOH Parameter Positive-Going Threshold Voltage Negative-Going Threshold Voltage Hysteresis Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.0 ns Unit ns FAST AND LS TTL DATA 4-15 . 74 74 VOL IT+ IT– IIH Output LOW Voltage Input Current at Positive-Going Threshold Input Current at Negative-Going Threshold Input HIGH Current –0.0 6. Output HIGH ICCL Power Supply Current Total.0 V VCC = MAX.0 8. For conditions shown as MIN or MAX.0 V Symbol tPLH tPHL tPLH tPHL Propagation Delay F14 Parameter Propagation Delay F13 Min 3.0 Max 7.0 mA IOL = 20 mA VCC = 4.5 Min 1. 2.0 V ± 10% Min 3.5 VCC = 4.6 –150 8. VIN = VT+ VCC = 5. VOUT = 0 V NOTES: 1.0 3. nor for more than 1 second. AC CHARACTERISTICS (CL = 50 pF) 54/74F TA = +25°C VCC = +5.5 0. VIN = VT– VCC = MAX.0 V. Not more than one output should be shorted at a time.5 3.5 2.2 0. VIN = 7.14 –0.0 V Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.0 9. Output LOW F13 F14 F13 F14 –60 4. VIN = 2.5 54F TA = –55°C to +125°C VCC = 5.0 V ± 10% Min 3.5 13 7.0 V.0 23 –0. VIN = 0.0 0.4 2.5 8.5 3.7 0.0 V VCC = 5.7 0.5 3.0 1.0 7.0 8.5 3.0 3.0 7.8 –1.75 VCC = MIN VCC = 5.5 22 10 32 mA VCC = MAX 2.5 V VCC = MAX.8 Typ Max 2.1 IIL IOS ICCH Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total.0 74F TA = 0°C to 70°C VCC = 5.0 Max 9. IIN = –18 mA IOH = –1.0 V VCC = 5. use the appropriate value specified under recommended operating conditions for the applicable device type.5 9.0 8.0 3.

MC54/74F13 • MC54/74F14 FUNCTION TABLE MC54/74F13 Inputs Output FUNCTION TABLE MC54/74F14 Input A L H Output O H L A L X X X H B X L X X H C X X L X H D X X X L H O H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care FAST AND LS TTL DATA 4-16 .

5 125 70 –1.5 –55 0 Typ 5.DUAL 4-INPUT NAND GATE MC54/74F20 DUAL 4-INPUT NAND GATE VCC 14 FAST™ SCHOTTKY TTL 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 GND 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. 74 54 74 IOH IOL Output Current — High Output Current — Low 54. 74 54.0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-17 . 74 Min 4.0 25 25 Max 5.

nor for more than 1 second.3 Unit ns ns FAST AND LS TTL DATA 4-18 .4 1. For conditions shown as MIN or MAX.0 1.75 V VCC = MIN VCC = MAX.7 0.3 54F TA = –55°C to +125°C VCC = 5. Output HIGH Total.0 V ± 10% CL = 50 pF Min 2.50 V VCC = 4.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total. VIN = 7.5 Max 6.2 Typ Max Unit V V V V V V µA mA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN. VOUT = 0 V VCC = MAX.5 74F TA = 0°C to 70°C VCC = 5. VIN = 0. VIN = GND VCC = MAX. use the appropriate value specified under recommended operating conditions for the applicable device type. VIN = Open NOTES: 1.5 Max 5.0 mA IOH = –1.0 mA IOL = 20 mA VCC = 4.0 5. Output LOW –60 –0. IIN = –18 mA IOH = –1.4 1.7 V VCC = MAX. 2.0 6.0 0.0 V VCC = MAX. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.5 20 0. VIN = 2. Not more than one output should be shorted at a time.5 Max 7.0 V ± 10% CL = 50 pF Min 2.1 Min 2.6 –150 1.5 2.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay Min 2.4 5.0 4.8 –1. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.MC54/74F20 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 V VCC = MAX.

5 –55 0 Typ 5.0 25 25 Max 5.DUAL 4-INPUT AND GATE MC54/74F21 CONNECTION DIAGRAM VCC 14 13 12 11 10 9 8 DUAL 4-INPUT AND GATE FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 GND 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. 74 Min 4. 74 54.5 125 70 –1.0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-19 . 74 54 74 IOH IOL Output Current — High Output Current — Low 54.

3 54F TA = –55°C to +125°C VCC = 5.6 6.7 V VCC = MAX.0 2. use the appropriate value specified under recommended operating conditions for the applicable device type.4 Min 2.6 5. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.5 74F TA = 0°C to 70°C VCC = 5.0 V VCC = MAX. nor for more than 1 second. For conditions shown as MIN or MAX.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay Min 2.7 0.0 0. VIN = 0. Output HIGH Total. VIN = GND NOTES: 1.5 Max 6.5 V VCC = MAX.0 2.0 mA IOH = –1. Output LOW –60 –0. VIN = 2.3 Unit ns ns FAST AND LS TTL DATA 4-20 .0 Max 7.0 2. IIN = –18 mA IOH = –1. VIN = Open VCC = MAX.1 6.75 V VCC = MIN VCC = MAX.5 20 0.8 –1. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.5 7. VIN = 7.MC54/74F21 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 2.6 –150 4.5 Max 5.0 mA IOL = 20 mA VCC = 4.50 V VCC = 4.0 V ± 10% CL = 50 pF Min 2.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total. VOUT = 0 V VCC = MAX. Not more than one output should be shorted at a time.2 Typ Max Unit V V V V V V µA mA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN. 2.0 V ± 10% CL = 50 pF Min 2.

5 125 70 –1.5 –55 0 Typ 5. 74 54 74 IOH IOL Output Current — High Output Current — Low 54. 74 54.QUAD 2-INPUT OR GATE MC54/74F32 QUAD 2-INPUT OR GATE VCC 14 13 12 11 10 9 8 FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 GND 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. 74 Min 4.0 25 25 Max 5.0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-21 .

VIN = 2.6 –150 9.5 74F TA = 0°C to 70°C VCC = 5.5 7.0 mA IOL = 20 mA VCC = 4. 2. VIN = 7. Not more than one output should be shorted at a time.6 5.0 mA IOH = –1.7 V VCC = MAX.0 Max 5.0 V ± 10% CL = 50 pF Min 3.0 Max 6.7 0.6 6. Output LOW –60 –0. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.75 V VCC = MIN VCC = MAX.0 0.5 Min 2.MC54/74F32 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay Min 3. For conditions shown as MIN or MAX. VIN = GND NOTES: 1.3 54F TA = –55°C to +125°C VCC = 5. use the appropriate value specified under recommended operating conditions for the applicable device type.0 3.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total.8 –1.0 V VCC = MAX. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.3 Unit ns ns FAST AND LS TTL DATA 4-22 . Output HIGH Total. VIN = 0.0 2. VOUT = 0 V VCC = MAX.2 15.50 V VCC = 4.5 Max 7.5 V VCC = MAX. VIN = 4.0 V ± 10% CL = 50 pF Min 3.5 V VCC = MAX. IIN = –18 mA IOH = –1.5 20 0.5 2.0 3. nor for more than 1 second.2 Typ Max Unit V V V V V V µA mA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.

0 25 Max 5.QUAD 2-INPUT NAND BUFFER MC74F37 QUAD 2-INPUT NAND BUFFER VCC 14 A 13 B 12 Y 11 A 10 B 9 Y 8 FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 1 A 2 B 3 Y 4 A 5 B 6 Y 7 GND 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC74FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4.5 70 –15 64 Unit V °C mA mA FAST AND LS TTL DATA 4-23 .5 0 Typ 5.

4 2. Output HIGH Total. VOUT = 0 V VCC = MAX. use the appropriate value specified under recommended operating conditions for the applicable device type.0 2.50 VCC = 4. AC CHARACTERISTICS 74F TA = +25°C VCC = +5.5 4. nor for more than 1 second. VIN = 0.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total.0 0. 2. Output LOW –100 –1.5 74F TA = 0°C to 70°C VCC = 5.7 V VCC = MAX.0 V VCC = MAX. VIN = 7.2 Typ Max Unit V V V V V V V µA mA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.0 Max 5.0 V ± 10% CL = 50 pF Min 1.55 20 0. VIN = Open NOTES: 1.MC74F37 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 74 VOH VOL IIH Output HIGH Voltage 74 74 Output LOW Voltage Input HIGH Current 2.8 –1.5 5.5 1.7 0.0 Max 6.5 1. IIN = –18 mA IOH = –15 mA IOH = –1.75 V VCC = MIN VCC = MAX.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay Min 1.0 mA IOL = 64 mA VCC = 4 50 V 4.2 –225 6 33 Min 2. VIN = GND VCC = MAX.0 Unit ns ns FUNCTION TABLE Inputs A L L H H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Output B L H L H Y H H H L FAST AND LS TTL DATA 4-24 . For conditions shown as MIN or MAX.5 V VCC = MAX. Not more than one output should be shorted at a time.0 mA IOH = –1. VIN = 2.

5 0 Typ 5. OPEN COLLECTOR FAST™ SCHOTTKY TTL VCC 14 A 13 B 12 Y 11 A 10 B 9 Y 8 J SUFFIX CERAMIC CASE 632-08 14 1 1 A 2 B 3 Y 4 A 5 B 6 Y 7 GND N SUFFIX PLASTIC CASE 646-06 1 14 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC74FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOL Supply Voltage Operating Ambient Temperature Range Output Current — Low Parameter 74 74 74 Min 4. OPEN COLLECTOR QUAD 2-INPUT NAND BUFFER.MC74F38 QUAD 2-INPUT NAND BUFFER.0 25 Max 5.5 70 64 Unit V °C mA FAST AND LS TTL DATA 4-25 .

5 V VCC = MIN.5 Unit ns ns FUNCTION TABLE Inputs A L L H H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Output B L H L H Y H H H L FAST AND LS TTL DATA 4-26 . use the appropriate value specified under recommended operating conditions for the applicable device type. VIN = 0.0 Max 12.0 30 mA mA NOTES: 1.5 1. VOH = MAX VCC = MAX.2 250 Typ Max Unit V V V V µA mA mA µA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.0 V CL = 50 pF Symbol tPLH tPHL Propagation Delay Propagation Delay Parameter Min 7. AC CHARACTERISTICS 74F TA = +25°C VCC = +5. VIN = 7. VIN = Open ICC 7.2 0.5 1.0 0. IIN = –18 mA IOL = 64 mA VCC = MIN VCC = MAX.55 20 0.0 V VCC = MAX. Output LOW Min 2.0 V ± 10% CL = 50 pF Min 7. For conditions shown as MIN or MAX.0 74F TA = 0°C to 70°C VCC = 5. Output HIGH Total.8 –1. VIN = 2.MC74F38 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOL IIH IIL IOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output LOW Voltage Input HIGH Current Input LOW Current Output HIGH Current Power Supply Current Total. VIN = GND VCC = MAX.1 –1.0 Max 13 5.5 5. VIL = MAX VIH = MIN.7 V VCC = MAX.

MC74F40 DUAL 4-INPUT NAND BUFFER DUAL 4-INPUT NAND BUFFER VCC 14 A 13 B 12 N/C 11 C 10 D 9 Y 8 FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 1 A 2 B 3 N/C 4 C 5 D 6 Y 7 GND 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC74FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4.5 0 Typ 5.0 25 Max 5.5 70 –15 64 Unit V °C mA mA FAST AND LS TTL DATA 4-27 .

VIN = 2.0 74F TA = 0°C to 70°C VCC = 5.5 Unit ns ns FUNCTION TABLE Inputs A L X X X H B X L X X H C X X L X H D X X X L H Output Y H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care FAST AND LS TTL DATA 4-28 . VIN = Open NOTES: 1.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total. VOUT = 0 V VCC = MAX. Not more than one output should be shorted at a time.4 2.MC74F40 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Output HIGH Voltage Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 74 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.7 0.0 V ± 10% CL = 50 pF Min 1.0 Max 7.0 2. VIN = 7. nor for more than 1 second.8 –1.50 VCC = 4. use the appropriate value specified under recommended operating conditions for the applicable device type.55 20 0.0 0.0 5.5 V VCC = MAX. VIN = 0.75 V VCC = MIN VCC = MAX. Output LOW –100 –1.0 Max 6. AC CHARACTERISTICS 74F TA = +25°C VCC = +5. 2.5 1.0 V VCC = MAX.5 1. Output HIGH Total.0 5. For conditions shown as MIN or MAX.0 V CL = 50 pF Symbol tPLH tPHL Propagation Delay Propagation Delay Parameter Min 1.7 V VCC = MAX.2 –225 4 17 Min 2. VIN = GND VCC = MAX.0 mA IOL = 64 mA VCC = 4 50 V 4.0 mA IOH = –1.2 Typ Max Unit V V V V V V V µA mA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN. IIN = –18 mA IOH = –15 mA IOH = –1.

2-WIDE 3-INPUT AND-OR-INVERT GATE CONNECTION DIAGRAM VCC 14 1C 13 1B 12 1F 11 1E 10 1D 9 1Y 8 DUAL 2-WIDE 2-INPUT.0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-29 . 74 Min 4.5 125 70 –1.5 –55 0 Typ 5.0 25 25 Max 5. 74 54. 2-WIDE 3-INPUT AND-OR-INVERT GATE FAST™ SCHOTTKY TTL 1 1A 2 2A 3 2B 4 2C 5 2D 6 2Y 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 FUNCTION TABLE For 3-Input Gates Inputs A H X B H X C H X D X H Inputs E X H F X H Output 1Y L L H A H X For 2-Input Gates Inputs B H X C X H D X H Output 2Y L L H 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 All other combinations H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care All other combinations D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC LOGIC SYMBOL 1A 1 1B 12 1C 13 1D 9 1E 10 1F 11 2A 2 2B 3 8 2C 4 2D 5 1Y 2Y 6 GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.MC54/74F51 DUAL 2-WIDE 2-INPUT.74 54 74 IOH IOL Output Current — High Output Current — Low 54.

0 V VCC = MAX.5 74F TA = 0°C to + 70°C VCC = 5.0 0.0 54F TA = –55°C to +125°C VCC = 5.8 5.5 V VCC = MAX.0 V ± 10% CL = 50 pF Min 1.0 7.8 –1.5 1. VIN = 0. D.75 V VCC = MIN VCC = MAX. VOUT = 0 V VIN = GND VIN = 4. F. For conditions shown as MIN or MAX. to nY Min 2. VIN = 2. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.2 Typ Max Unit V V V V V V µA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN. IIN = –18 mA IOH = –1.5 2.0 mA IOL = 20 mA VCC = 4.5 5.5 mA Min 2.5 –0.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation Delay A. B. 2.0 V ± 10% CL = 50 pF Min 1.50 V VCC = 4.5 4.5 V VCC = MAX NOTES: 1.MC54/74F51 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 20 0.0 Max 7.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Total Supply Current ICCH ICCL –60 1.0 Max 6. use the appropriate value specified under recommended operating conditions for the applicable device type.5 4.7 V VCC = MAX. C.5 ns Unit FAST AND LS TTL DATA 4-30 . VIN = 7. E. AC ELECTRICAL CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 1.7 0.6 –150 3. Not more than one output should be shorted at a time.0 Typ Max 5.5 1.0 mA IOH = –1. nor for more than 1 second.

MC54/74F64 4-2-3-2-INPUT AND-OR-INVERT GATE 4-2-3-2-INPUT AND-OR-INVERT GATE VCC 14 13 12 11 10 9 8 FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 GND 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. 74 Min 4.5 125 70 –1. 74 54 74 IOH IOL Output Current — High Output Current — Low 54.0 25 25 Max 5. 74 54.0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-31 .5 –55 0 Typ 5.

5 6. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.50 V VCC = 4.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay Min 2.2 Typ Max Unit V V V V V V µA mA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN. VIN = 0.7 Min 2.0 mA IOH = –1.5 Max 7.0 0.5 74F TA = 0°C to 70°C VCC = 5. VIN = 7. Output LOW –60 –0.5 54F TA = –55°C to +125°C VCC = 5.7 V VCC = MAX. VIN = Note 3 NOTES: 1. 2.5 1. VIN = GND VCC = MAX.5 1.5 4.5 1. For conditions shown as MIN or MAX. VIN = 2. nor for more than 1 second.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total.0 mA IOL = 20 mA VCC = 4.5 20 0. use the appropriate value specified under recommended operating conditions for the applicable device type. VOUT = 0 V VCC = MAX.5 V VCC = MAX.5 5. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 V ± 10% CL = 50 pF Min 2. Output HIGH Total.5 2. ICCL is measured with all inputs of one gate open and remaining inputs grounded.8 4.75 V VCC = MIN VCC = MAX.5 Max 8.5 Max 6.0 V ± 10% CL = 50 pF Min 2.7 0.MC54/74F64 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 Unit ns ns FAST AND LS TTL DATA 4-32 . IIN = –18 mA IOH = –1. 3.0 V VCC = MAX.8 –1. Not more than one output should be shorted at a time.6 –150 2.

Information at the input is transferred to the outputs on the positive edge of the clock pulse. Q) outputs. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse.MC54/74F74 DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC54/74F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q. DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP FAST™ SCHOTTKY TTL • ESD > 4000 Volts J SUFFIX CERAMIC CASE 632-08 14 1 CONNECTION DIAGRAM VCC 14 CD2 13 D2 12 CP2 11 SD2 10 Q2 9 Q2 8 D1 CD1 Q1 CP1 SD1 Q1 CP2 SD2 Q2 D2 CD2 Q2 14 N SUFFIX PLASTIC CASE 646-06 1 1 CD1 2 D1 3 CP1 4 SD1 5 Q1 6 Q1 7 GND 14 1 D SUFFIX SOIC CASE 751A-02 FUNCTION TABLE (Each Half) Input @ tn D L H Asynchronous Inputs: LOW Input to SD sets Q to HIGH level LOW Input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH H = HIGH Voltage Level L = LOW Voltage Level tn = Bit time before clock pulse tn + 1 = Bit time after clock pulse Outputs @ tn + 1 Q L H Q H L ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 2 3 SD1 D1 Q1 CP1 Q1 CD1 1 VCC = PIN 14 GND = PIN 7 6 10 SD2 D2 Q2 CP2 Q2 CD2 13 8 5 12 11 9 FAST AND LS TTL DATA 4-33 . the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. After the Clock Pulse input threshold voltage has been passed.

35 0.5V VCC = MAX VCC = MIN VCC = 4.MC54/74F74 LOGIC DIAGRAM Q Q D CP SD CD NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.5 –0. Not more then one output should be shorted at a time. For conditions shown as MIN or MAX.50 125 70 –1. FAST AND LS TTL DATA 4-34 . use the appropriate value specified under guaranteed operating ranges.8 –150 16 Min 2.0 25 25 Max 5. 74 54 74 IOH IOL Output Current — High Output Current — Low 54. 74 54.8 –1. nor for more than 1 second.0 V VIN = 0.0 mA IOL = 20mA VIN = 2. 74 Min 4.50 V VCC = 4.0 20 mA mA Unit V °C DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54. 2.5 2. 74 VOH VOL IIH Output HIGH Voltage Output LOW Voltage Input HIGH Current 74 2.2 Typ Max Unit V V V V V V µA µA mA mA mA mA VOUT = 0 V VCP = 0 V VCC = MAX VCC = MAX Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1.7 V VIN = 7.0 mA IOH = –1.50 –55 0 Typ 5. GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.6 –1.4 0.5 20 100 IIL Input LOW Current (CP and D Inputs) (CD and SD Inputs) IOS ICC Output Short Circuit Current (Note 2) Power Supply Current –60 10.4 3.0 0.75 V VCC = MIN VCC = MAX NOTES: 1.7 3.

4 2.0 4.MC54/74F74 AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.4 2.0 6.0 11.1 9.2 7.0 ns 1.8 8.5 3.5 8.5 3.0 1.4 2.0 ns 5.0 ns ns Max Unit FAST AND LS TTL DATA 4-35 .5 8.0 V CL = 50 pF Symbol fmax tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Min 100 3.0 2. LOW Recovery Time CDn or SDn to CP Min 2.8 4.5 10.0 3.0 4.0 1.1 ns 10.0 V ± 10% CL = 50 pF Min 100 3.8 4.0 2.8 4. HIGH or LOW Dn to CPn Hold Time. HIGH or LOW Dn to CPn CPn Pulse Width.5 6.0 4.0 2.0 3.5 Max 74F TA = 0°C to 70°C VCC = 5.0 3.8 ns 9.0 4.0 V ± 10% Min 3.0 4.0 V ± 10% CL = 50 pF Min 100 3.0 V Symbol ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Parameter Setup Time.0 Max 54F TA = –55°C to +125°C VCC = 5. HIGH or LOW CDn or SDn Pulse Width.5 7.0V ± 10% Min 2.0 4.5 3.0 Typ Max 54F TA = –55°C to +125°C VCC = 5.0 1.5 Max Unit MHz AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = +5.0 Max 74F TA = 0°C to +70°C VCC = 5.0 6.0 2.0 5.0 4.

IA = B.0 25 25 Max 5. 74 Min 4. “A equal to B” (0A = B).0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-36 . 4-BIT MAGNITUDE COMPARATOR FAST™ SCHOTTKY TTL • High Impedance NPN Base Inputs for Reduced Loading (20 µA in HIGH and LOW States) • Magnitude Comparison of any Binary Words • Serial or Parallel Expansion Without Extra Gating • ESD > 4000 Volts CONNECTION DIAGRAM VCC 16 A3 15 B2 14 A2 13 A1 12 B1 11 A0 10 B0 9 16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 B3 2 IA<B 3 IA=B 4 IA>B 5 A>B 6 A=B 7 A<B 8 GND 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC74FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. For serial (ripple) expansion the 0A > B.5 –55 0 Typ 5. the device will work with any monotonic code. 0A < B Outputs are connected respectively to the IA > B and IA = B inputs of the next most significant comparator. Three Expander Inputs. B0-B3). Operation is not restricted to binary codes. 74 54. “A less than B” (0A < B). the Expander Inputs to the least significant position must be connected as follows: IA < B = IA > B = L. For proper compare operation. 74 54 74 IOH IOL Output Current  High Output Current  Low 54. IA < B.MC54/74F85 4-BIT MAGNITUDE COMPARATOR The MC54/74F85 is a 4-Bit Magnitude Comparator which compares two 4-Bit words (A0-A3. B3 being the most significant inputs. allow cascading without external gates.5 125 70 –1. Refer to applications section of data sheet for high speed method of comparing large words. IA > B. IA = B = H. Three Outputs are provided: “A greater than B” (0A > B). A3. as shown in Figure 1.

For conditions shown as MIN or MAX. Not more than one output should be shorted at a time.0 0. B3 A3 > B3 A3 < B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A2. VIN = 2. 2.1 IIL IOS Input LOW Current Output Short Circuit Current (Note 2) Total Supply Current ICC HIGH VIN = HIGH LOW An = Bn = IA-B = GND: IA>B = IA<B = 4. VIN = 0. FAST AND LS TTL DATA 4-37 .8 –1.50 V VCC = 4.5 V 50 54 mA VCC = MAX –60 –20 –150 V µA mA µA mA Parameter Min 2. nor for more than 1 second.0 V VCC = MAX.75 V IOL = 20 mA.5 V VCC = MAX. B1 X X X X A1 > B1 A1 < B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A0.5 2. B2 X X A2 > B2 A2 < B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A1.7 0. IIN = –18 mA IOH = –1.5 20 0. VOUT = 0 V NOTES: 1.MC54/74F85 FUNCTION TABLE Comparing Inputs A3. VIN = 7. VCC = MIN VCC = MAX.7 V VCC = 0 V.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.0 mA VCC = 4. use the appropriate value specified under recommended operating conditions for the applicable device type. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2. B0 X X X X X X A0 > B0 A0 < B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 IA > B X X X X X X X X H L L X H L Expansion Inputs IA < B X X X X X X X X L H L X H L IA = B X X X X X X X X L L H H L L A>B H L H L H L H L H L L L L H Outputs A<B L H L H L H L H L H L L L H A=B L L L L L L L L L L H H L L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.

Comparison of Two 24-Bit Words FAST AND LS TTL DATA 4-38 . IA<B as a “B” input and setting IA=B low. The ‘F85 can be used as a 5-bit comparator only when the outputs are used to drive the (A0-A3) and (B0-B3) inputs of another ‘F85 device. The expansion inputs are used by labelling IA>B as an “A” input. The parallel technique can be expanded to any number of bits as shown in Table 1.MC54/74F85 (MSB) B23 A23 B22 A22 B21 A21 B20 A20 B19 A19 L B3 A3 B2 A2 B1 A1 B0 A0 IA < B IA = B IA > B A<B A=B A>B NC B18 A18 B17 A17 B16 A16 B15 A15 B14 L A14 B3 A3 B2 A2 B1 A1 B0 A0 IA < B IA = B IA > B A<B A=B A>B NC The parallel expansion scheme shown in Figure 1 demonstrates the most efficient general use of these comparators. B13 A13 B12 A12 B11 A11 B10 A10 B9 L A9 B3 A3 B2 A2 B1 A1 B0 A0 IA < B IA = B IA > B A<B A=B A>B NC B3 A3 B2 A2 B1 A1 B0 A0 A<B A=B A>B A<B A=B A>B OUTPUTS B8 A8 B7 A7 B6 A6 B5 A5 B4 L A4 B3 A3 B2 A2 B1 A1 B0 A0 IA < B IA = B IA > B A<B A=B A>B NC Table 1 Word Length 1–4 Bits Number of Packages 1 2–6 8–31 Typical Speeds 74F 12 ns 22 ns 34 ns B3 A3 B2 A2 B1 A1 (LSB) B0 A0 L H L B3 A3 B2 A2 B1 A1 B0 A0 IA < B IA = B IA > B A<B A=B A>B 5–25 Bits 25–120 Bits Figure 1. In the parallel expansion scheme. the expansion inputs can be used as a fifth input bit position except on the least significant device which must be connected as in the Serial Scheme.

0 5.0 Max 13 ns 15. and IA<B inputs of the next higher stage.0 54F TA = –55°C to +125°C VCC = 5.0 3.5 2.5 14 ns 14.0 Max 14 16. and IA<B are the least significant bit positions. but a propagation delay penalty of about 15 ns is added with each additional stage.0 2.5 5.0 V ± 10% CL = 50 pF Min 5.5 9.0 2.5 3.5 Unit The expansion inputs IA>B.5 2.0 V ± 10% CL = 50 pF Min 5.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter A or B Input to A < B. A3 (15) B3 (1) (5) A2 (13) B2 (14) (2) IA < B IA = B (3) IA > B (4) A1 (12) B1 (11) (7) A>B (6) A=B A<B A0 (10) B0 (9) NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.0 6.5 3.0 7. and A<B outputs of the least significant word are connected to the corresponding IA>B.5 2.5 5.5 2. Figure 2.5 10 11 10 13 10.0 9.5 5. IA=B = HIGH.0 6. Logic Diagram FAST AND LS TTL DATA 4-39 .5 7.5 10.0 Max 11 14 11. IA=B.0 2.5 2. Stages can be added in this manner to any length.5 74F TA = 0°C to + 70°C VCC = 5.0 ns 10 9. IA=B. For proper operation the expansion inputs of the least significant word should be tied as follows: IA>B = LOW.0 3.5 14 7. and IA<B = LOW.5 5.5 3.5 15 15. A=B.0 2.5 2.0 ns 12 9. A > B Output A or B Input to A = B Output IA<B and IA=B Input to A>B Output IA=B Input to A = B Output IA>B and IA=B Input to A<B Output Min 6.5 9.0 6. When used for series expansion.0 3.0 10 8.MC54/74F85 AC ELECTRICAL CHARACTERISTICS 54/74F TA = +25°C VCC = +5. the A>B.5 ns 9.0 2.5 3.

74 54.0 25 25 Max 5.0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-40 . 74 54 74 IOH IOL Output Current — High Output Current — Low 54. 74 Min 4.MC54/74F86 QUAD 2-INPUT EXCLUSIVE-OR GATE QUAD 2-INPUT EXCLUSIVE-OR GATE FAST™ SCHOTTKY TTL VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 1 2 3 4 5 6 7 GND N SUFFIX PLASTIC CASE 646-06 1 14 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.5 –55 0 Typ 5.5 125 70 –1.

VOUT = 0 V 1-Input HIGH 1-Input LOW Inputs LOW VCC = MAX NOTES: 1.0 mA IOH = –1.5 3.4 3. For conditions shown as MIN or MAX.0 3.35 0.0 V ± 10% CL = 50 pF Min 3.8 –1.50 V VCC = 4.0 V ± 10% CL = 50 pF Min 2.0 mA IOL = 20 mA VCC = 4.5 54F TA = –55°C to +125°C VCC = 5.MC54/74F86 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay (Other Input LOW) Propagation Delay (Other Input HIGH) Min 3.0 7.6 –150 23 mA Min 2.0 6. IIN = –18 mA IOH = –1.0 Max 6.5 7.0 3.0 8.5 3.7 3.5 8. Not more than one output should be shorted at a time.0 3.2 5.0 Max 7.4 0.0 3.5 6.2 Typ Max Unit V V V V V V µA µA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.5 2.7 Max 5. use the appropriate value specified under guaranteed operating ranges.0 4. VIN = 0.0 3.0 74F TA = 0°C to 70°C VCC = 5.7 V VCC = MAX.0 Typ 4.75 V VCC = MIN VCC = MAX. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5. VIN = 7. VIN = 2.5 5.5 3. 2.0 ns 7.0 V VCC = MAX.5 20 100 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) –60 15 Power Supply Current y 18 28 –0. nor for more than 1 second.3 4.5 3.5 ns Unit FAST AND LS TTL DATA 4-41 . 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.0 0.5 8.5 V VCC = MAX.

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP FAST™ SCHOTTKY TTL CONNECTION DIAGRAM VCC CD2 16 15 CD CD1 J1 1 CD1 2 J1 J2 14 J K2 13 K CP2 SD2 11 12 CP SD Q2 10 Q Q Q1 7 Q1 8 GND 16 1 16 1 Q2 9 K1 3 K1 CP1 SD1 4 5 Q1 6 Q1 J SUFFIX CERAMIC CASE 620-09 CP1 SD1 N SUFFIX PLASTIC CASE 648-08 FUNCTION TABLE (Each Half) Input @ tn J L L H H Asynchronous Inputs: LOW Input to SD sets Q to HIGH level LOW Input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH H = HIGH Voltage Level L = LOW Voltage Level tn = Bit time before clock pulse tn + 1 = Bit time after clock pulse Output @ tn + 1 Q Q 16 1 K H L H L D SUFFIX SOIC CASE 751B-03 No Change L H H L ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC Toggles LOGIC SYMBOL 5 2 4 3 J SD Q J 11 SD Q 6 14 12 10 CP K C Q D 1 7 CP K CD 15 Q 9 13 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-42 . The JK design allows operation as a D flip-flop (refer to F74 data sheet) by connecting the J and K inputs together. The clocking operation is independent of rise and fall times of the clock waveform.MC54/74F109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC54/74F109 consists of two high-speed. completely independent transition clocked JK flip-flops.

0 mA IOL = 20 mA VIN = 2.0 mA IOH = –1.7 V VIN = 7. GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.5 –55 0 Typ 5.0 V VIN = 0.0 25 25 Max 5.5 V VCC = MAX VCC = MIN VCC = 4.7 3. Not more than one output should be shorted at a time.0 20 mA mA Unit V °C DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54. For conditions shown as MIN or MAX. nor for more than 1 second.7 –0.6 –1. use the appropriate value specified under guaranteed operating ranges. 74 Min 4. 74 54 54 IOH IOL Output Current — High Output Current — Low 54.MC54/74F109 LOGIC DIAGRAM (one half shown) Q Q K J CP SD CD NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.8 –1.35 0. K and CP Inputs) (CD and SD Inputs) IOS ICC Output Short Circuit Current (Note 2) Power Supply Current –60 11.5 2.75 V VCC = MIN VCC = MAX NOTES: 1. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.4 3.5 125 70 –1. 2.50 V VCC = 4.5 20 100 IIL Input LOW Current (J. 74 54.2 Typ Max Unit V V V V V V µA µA mA mA mA mA VOUT = 0 V VCP = 0 V VCC = MAX VCC = MAX Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1. FAST AND LS TTL DATA 4-43 .0 0.4 0.8 –150 17 Min 2.

HIGH or LOW CDn or SDn Pulse Width.0 2.2 5.0 V ± 10% Min 3.5 9.0 7.0 3.0 Typ Max 54F TA = –55°C to +125°C VCC = 5.0 V CL = 50 PF Symbol fmax tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Min 100 3.0 V Symbol ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Parameter Setup Time.0 2. LOW Recovery Time CDn or SDn to CP Min 3.5 3.4 2.5 9. HIGH or LOW Jn or Kn to CPn CPn Pulse Width.0 V ± 10% CL = 50 PF Min 90 3.MC54/74F109 AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 4.8 4.0 ns ns Max Unit FAST AND LS TTL DATA 4-44 .2 7.0 1.5 Typ 125 5.0 9.0 5.0 Max 74F TA = 0°C to +70°C VCC = 5.0 4.4 2.5 Max Unit MHz AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = +5.0 2.5 Max 74F TA = 0°C to +70°C VCC = 5.0 1.0 ns 10.0 3.0 10.5 3.0 ns 5.0 Max 54F TA = –55°C to +125°C VCC = 5.0 1. HIGH or LOW Jn or Kn to CPn Hold Time.0 ns 1.5 3.0 5.3 6.0 1.0 11.0 8.0 4.0 4.0 4.0 7.0 3.0 V ± 10% Min 3.0 4.0 V ± 10% CL = 50 PF Min 70 3.4 2.8 4.8 4.2 8.5 8.0 1.0 ns 9.

provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock.MC74F112 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The MC74F112 contains two independent. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH. respectively. The J and K inputs can change when the clock is in either state without affecting the flip-flop. high-speed JK flip-flops with Direct Set and Clear inputs. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. Synchronous state changes are initiated by the falling edge of the clock. CONNECTION DIAGRAM VCC CD1 CD2 CP2 16 15 14 13 K2 12 J2 11 SD2 10 Q2 9 16 1 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 C K D Q CP J Q SD 1 CP1 2 K1 3 J1 4 SD1 5 Q1 S J D Q CP K Q CD 6 Q1 7 Q2 8 GND 16 N SUFFIX PLASTIC CASE 648-08 1 FUNCTION TABLE (Each Half) Inputs @ tn J L L H H Asynchronous Inputs: LOW Input to SD sets Q to HIGH level LOW Input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH H = HIGH Voltage Level L = LOW Voltage Level tn = Bit time before clock pulse tn + 1 = Bit time after clock pulse Output @ tn + 1 Q Qn L H Qn 16 1 D SUFFIX SOIC CASE 751B-03 K L H L H ORDERING INFORMATION MC74FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 3 1 2 J SD J 10 SD Q 5 11 13 Q 9 CP K Q 6 CP K CD 14 Q 7 12 15 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-45 . Simultaneous LOW signals on SD and CD force both Q and Q HIGH.

0 0.0 mA IOL = 20 mA VCC = MIN VCC = 4. use the appropriate value specified under guaranteed operating ranges.75 V VCC = MIN VCC = MAX.0 mA IOH = –1. VCP = 0 V VCC = MAX.5 20 100 Input LOW Current (J and K Inputs) IIL (CP Inputs) (CD and SD Inputs) IOS ICC Output Short Circuit Current (Note 2) Power Supply Current –60 12 –0.0 –150 19 Min 2. VIN = 7. VIN = 2.4 0.2 Typ Max Unit V V V V V V µA µA mA mA mA mA mA VCC = MAX.5 70 –1. 2.0 20 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 74 VOH VOL IIH Output HIGH Voltage Output LOW Voltage Input HIGH Current 74 2.5 V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1. VIN = 0.0 V NOTES: 1.7 3.MC74F112 LOGIC DIAGRAM (one half shown) Q Q CD J CP SD K GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4. For conditions shown as MIN or MAX.35 0. nor for more than 1 second. FAST AND LS TTL DATA 4-46 .5 0 Typ 5.50 V VCC = 4.8 –1. Not more than one output should be shorted at a time.5 2.4 –3. VOUT = 0 V VCC = MAX.4 3.0 25 Max 5.6 –2.7 V VCC = MAX.

HIGH or LOW Jn or Kn to CPn Hold Time.0 2.5 4.0 2. LOW Recovery Time CDn or SDn to CP Min 4. HIGH or LOW Jn or Kn to CPn CPn Pulse Width.5 2.0 V Symbol ts (H) ts (L) th (H) th (L) tw (H) tw (L) tw (L) trec Parameter Setup Time.0 Typ Max 74F TA = 0°C to +70°C VCC = 5.0 ns 0 0 4.5 Max 74F TA = 0°C to +70°C VCC = 5.0 2.5 6.0 2.5 7.5 6.0 3.MC74F112 AC CHARACTERISTICS 74F TA = +25°C VCC = +5.5 6.5 4.5 ns 7. HIGH or LOW CDn or SDn Pulse Width.0 2.5 4.0 0 0 4.0 ns ns Max Unit FAST AND LS TTL DATA 4-47 .0 7.0 V ± 10% Min 4.5 ns 7.0 3.0 V CL = 50 PF Symbol fmax tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Min 110 2.5 4.0 2.0 V ± 10% CL = 50 PF Min Max Unit MHz AC OPERATING REQUIREMENTS 74F TA = +25°C VCC = +5.5 ns 4.5 5.0 6.

74 54 74 IOH IOL Output Current — High 54 74 Output Current — Low 54 74 Min 4.0 25 25 Max 5. 3-STATE MC54/74F125 VCC 14 4C 13 4A 12 4Y 11 3C 10 3A 9 3Y 8 FAST™ SHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 14 1 1C 2 1A 3 1Y 4 2C 5 2A 6 2Y 7 GND 1 MC54/74F126 VCC 14 4C 13 4A 12 4Y 11 3C 10 3A 9 3Y 8 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 1 1C 2 1A 3 1Y 4 2C 5 2A 6 2Y 7 GND ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.5 –55 0 Typ 5.MC54/74F125 MC54/74F126 3-STATE QUAD BUFFERS • High Impedance NPN Base Inputs for Reduced Loading QUAD BUFFERS.5 125 70 –12 –15 48 64 mA mA Unit V °C FAST AND LS TTL DATA 4-48 .

4 Min 2.MC54/74F125 • MC54/74F126 Function Table MC54/74F125 Inputs C L L H A L H X Output Y L H Z Function Table MC54/74F126 Inputs C H H L A L H X Output Y L H Z L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care Z = High Impedance (off) DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54.0 2.0 mA IOH = –3. nor for more than 1 second. FAST AND LS TTL DATA 4-49 .74 74 VOH Output HIGH Voltage 54 74 54 VOL IOZH IOZL IIH Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0. For conditions shown as MIN or MAX.4 3.55 50 –50 20 100 IIL IOS Input LOW Current Output Short Ciru‘cuit Current Note 2 ICCH F125 ICCL ICCZ ICC F126 ICCH ICCL ICCZ –100 –20 –225 24 40 35 mA 30 48 39 VCC = MAX µA µA mA V µA µA 2.4 2.7 V VOUT = 0.7 3. 2.7 V VIN = 7. use the appropriate value specified under recommended operating conditions for the applicable device type.0 0.75 V VCC = 4.55 V V V 2.2 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –3.5 V VOUT = GND VCC = MAX VCC = MAX VCC = MAX VCC = 0 V VCC = MAX VCC = MAX VCC = MAX VCC = MIN VCC = 4.0 V VIN = 0.50 V NOTES: 1.8 –1. Not more than one output should be shorted at a time.50 V VCC = 4.0 mA IOH = –12 mA IOH = –15 mA IOL = 48 mA IOL = 64 mA VOUT = 2.5 V VIN = 2.0 0.

5 8.0 3.5 9.0 3.0 6.0 3.5 10 7.0 2.5 1.0 4.5 8.0 2.0 3.5 1.5 5.0 V CL = 50 pF Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay.5 9.5 54F TA = 0°C to 70°C VCC = 5.0 3.0 ns ns ns ns ns Unit ns FAST AND LS TTL DATA 4-50 .5 7.0 1.0 3.0 V ± 10% CL = 50 pF Min 1.0 6.0 3.0 9.0 6.0 5.5 8.5 3.5 4.5 3.0 3.5 8.0 5.0 8.5 8.5 5.0 Max 7.5 3.5 3.0 1.5 8.5 8.0 7.0 Typ 4.0 Max 6.0 V ± 10% CL = 50 pF Min 1.0 5.0 7.0 2. nA to nY Output Enable Time to HIGH and LOW level Output Disable Time from HIGH and LOW level Propagation Delay.0 3.0 8.5 Max 6.0 3.5 1.0 3.5 7.0 3.0 9.5 3.5 3.5 6.0 6.0 3.0 3.5 9.0 3. nA to nY Output Enable Time to HIGH and LOW level Output Disable Time from HIGH and LOW level F126 F125 Min 1.5 6.5 1.0 8.5 6.5 9.0 5.5 7.0 7.5 1.5 1.MC54/74F125 • MC54/74F126 AC ELECTRICAL CHARACTERISTICS 54/74F TA = +25 °C VCC = +5.5 8.0 7.0 3.5 9.0 1.0 74F TA = 0°C to + 70°C VCC = 5.5 3.

5 125 70 –1.5 –55 0 Typ 5.0 20 mA mA Unit V °C FUNCTION TABLE Inputs A B L L H L L H H H H = HIGH Voltage level L= LOW voltage level Output Y H H H L FAST AND LS TTL DATA 4-51 .0 25 25 Max 5.74 54. The Schmitt trigger uses positive feedback to effectively speed up slow input transitions and provide different input threshold voltages for positive and negative-going transitions. jitter-free output signals.MC54/74F132 QUAD 2-INPUT NAND SCHMITT TRIGGER The MC54/74F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. In addition. QUAD 2-INPUT NAND SCHMITT TRIGGER FAST™ SHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 14 1 VCC 14 A 13 B 12 Y 11 A 10 B 9 Y 8 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 A 2 B 3 Y 4 A 5 B 6 Y 7 GND 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. they have greater noise margin than conventional NAND gates. Each circuit contains a 2-input Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem-pole output. They are capable of transforming slowly changing input signals into sharply defined. This hysteresis between the positive-going and negative-going input threshold (typically 800 mV) is determined by resistor ratios and is essentially insensitive to temperature and supply voltage variations.74 54 74 IOH IOL Output Current — High Output Current — Low 54.74 Min 4.

0 V VCC = 5.5 3.5 3.0 74F TA = 0°C to +70°C VCC = 5.75 V VCC = MIN Test Conditions VCC = 5.0 Max 9. VIN = 0.0 V ± 10% CL = 50 pF Min 3.0 V VCC = 5.0 V Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.0 mA IOH = –1.7 V VCC = MAX.5 54F TA = –55°C to +125°C VCC = 5.0 6.0 Max 8. IIN = –18 mA IOH = –1.0 V. B to Y Min 3.5 V VCC = MAX NOTES: 1. VIN = 2.1 Unit V V V V V V V V V µA µA µA mA mA mA mA VCC = 5. For conditions shown as MIN or MAX.0 Unit ns FAST AND LS TTL DATA 4-52 .0 0.8 Typ Max 2. nor for more than 1 second. VIN = VT– VCC = MAX. VIN = 7.0 1. 2.0 V VCC = MAX. VIN = VT+ VCC = 5.5 2. Not more than one output should be shorted at a time.0 Typ 5.0V ± 10% CL = 50 pF Min 3.50 V VCC = 4.0 Max 7.5 5.0 7.5 2.0 V CL = 50 pF Symbol tPLH tPHL Parameter Propagation delay A.5 13 –0.0 mA IOL = 20 mA VCC = 4. use the appropriate value specified under recommended operating conditions for the applicable device type.7 0. Supply Current ICCH ICCL –60 8.0 V.4 2.74 74 Output LOW Voltage Input Current at Positive-Going Threshold Input Current at Negative-Going Threshold Input HIGH Current 0 –350 20 0.0 8.5 0. AC ELECTRICAL CHARACTERISTICS 54/74F TA = +25°C VCC = +5.8 –1.5 Min 1.5 V VCC = MAX.7 0.2 0.MC54/74F132 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VT+ VT– VT+–VT– VIH VIL VIK VOH VOL IT+ IT– IIH Parameter Positive-Going Threshold Voltage Negative-Going Threshold Voltage Hysteresis Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Total. VOUT = 0 V VIN = GND VIN = 4.6 –150 12 19.5 3.

This device is ideally suited for high speed bipolar memory chip select address decoding.MC54/74F138 1-OF-8 DECODER/ DEMULTIPLEXER The MC54/74F138 is a high speed 1-of-8 Decoder/Demultiplexer. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or to a 1-of-32 decoder using four F138s and one inverter. • Demultiplexing Capability • Multiple Input Enable for Easy Expansion • Active Low Mutually Exclusive Outputs • Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 O0 15 O1 14 O2 13 O3 12 O4 11 O5 10 O6 9 16 1 1-OF-8 DECODER/ DEMULTIPLEXER FAST™ SHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 16 N SUFFIX PLASTIC CASE 648-08 1 1 A0 2 A1 3 A2 4 E1 5 E2 6 E3 7 O7 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 LOGIC DIAGRAM A2 3 2 ORDERING INFORMATION VCC = PIN 16 GND = PIN 8 = PIN NUMBERS MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC A1 1 A0 4 E1 E2 E3 5 6 LOGIC SYMBOL 1 2 3 456 1 2 3 A0 A1 A2 O0 O1 O2 O3 O4 O5 O6 O7 7 9 10 11 12 13 14 15 15 14 13 12 11 10 9 7 O0 VCC = PIN 16 GND = PIN 8 O7 O6 O5 O4 O3 O2 O1 FAST AND LS TTL DATA 4-53 .

5 3. AC CHARACTERISTICS 54/74F TA = +25 °C Levels of Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay. For conditions shown as MIN or MAX.0 3.0 12.5 3.5 ns ns Unit ns FUNCTIONAL DESCRIPTION The decoder accepts three binary weighted inputs (AO.0 0. VIN = 7.0 3.0 25 25 Max 5. 74 Min 4.5 –55 0 Typ 5.0 3.0 V CL = 50 pF Min 3.0 7.0 mA IOH = –1.0 7. VIN = 2. 74 54 74 Output Current — High Output Current — Low 54.0 V ±10% CL = 50 pF Min 3. VIN = 0.0 mA IOL = 20 mA VCC = 4. Address to Output Enable to Output E1 or E2 Enable to Output E3 3 2 Delay 3 VCC = +5.5 20 0.8 –1.5 V VCC = MAX.0 8. The F138 features three Enable inputs.0 7.5 11 8. FAST AND LS TTL DATA 4-54 .0 V ±10% CL = 50 pF Min 3.7 0.2 Typ Max Unit V V V V V V µA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN. A1. E2) and one active HIGH (E3). The F138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes.5 Max 12 9.0 4.1 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current –60 –0.50 V VCC = 4.5 9. IIN = –18 mA IOH = –1.0 7.6 –150 20 Min 2.0 8.75 V VCC = MIN VCC = MAX.5 9.0 3.7 V VCC = MAX. 74 54.0 4. use the appropriate value specified under recommended operating conditions for the applicable device type.5 8. nor for more than 1 second.0 3. The Enable inputs which are not used must be permanently tied to their appropriate active HIGH or active LOW states. Not more than one output should be shorted at a time.MC54/74F138 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Parameter 54. 2.0 3. two active LOW (E1. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four F138s and one inverter.5 125 70 –1.0 V VCC = MAX.0 3.0 3.0 20 mA mA Unit V °C DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH IIL IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 2.0 4. VOUT = 0 V VCC = MAX NOTES: 1.5 3. All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH.0 8.0 3.5 Max 7. A2) and when enabled provides eight mutually exclusive active LOW outputs (O0–O7).5 8.5 54F TA = +25°C to +125°C VCC = 5.5 74F TA = 0°C to 70°C VCC = 5. 74 74 Output LOW Voltage Input HIGH Current 2.5 Max 8.

MC54/74F138 FUNCTION TABLE Inputs E1 H X X L L L L L L L L E2 X H X L L L L L L L L E3 X X L H H H H H H H H A0 X X X L H L H L H L H A1 X X X L L H H L L H H A2 X X X L L L L H H H H O0 H H H L H H H H H H H O1 H H H H L H H H H H H O2 H H H H H L H H H H H Outputs O3 H H H H H H L H H H H O4 H H H H H H H L H H H O5 H H H H H H H H L H H O6 H H H H H H H H H L H O7 H H H H H H H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care A0 A1 A2 FO4 A3 A4 H 123 A0 A1 A2 E A0 A1 A2 123 E A 0 A 1 A2 123 E A0 A1 A2 123 E F138 O0 O1 O2 O3 O4 O5 O6 O7 F138 O0 O1 O2 O3 O4 O5 O6 O7 F138 O0 O1 O2 O3 O4 O5 O6 O7 F138 O0 O1 O2 O3 O4 O5 O6 O7 O0 O31 FAST AND LS TTL DATA 4-55 .

DUAL 1-OF-4 DECODER FAST™ SHOTTKY TTL • • • • Multifunction Capability Two Completely Independent 1-of-4 Decoders Active Low Mutually Exclusive Outputs Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM VCC 16 Eb 15 A0b 14 A1b 13 O0b 12 O1b 11 O2b 10 O3b 9 J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 1 Ea 2 A0a 3 A1a 4 O0a 5 O1a 6 O2a 7 O3a 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION LOGIC DIAGRAM Ea 1 2 A0a A1a 3 Eb 15 A0b A1b 14 13 MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 1 2 3 15 14 13 E A0 A1 E A0 A1 O0 O1 O2 O3 O0 O1 O2 O3 4 5 6 7 12 11 10 9 4 5 6 7 O3b 12 11 10 9 O0a O1a O2a O3a O0b O1b O2b VCC = Pin 16 GND = Pin 8 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FAST AND LS TTL DATA 4-56 . Each decoder has an active LOW Enable input which can be used as a data input for a 4-output demultiplexer. The device has two independent decoders. each accepting two inputs and providing four mutually exclusive active LOW outputs.MC54/74F139 DUAL 1-OF-4 DECODER The MC54/74F139 is a high speed Dual 1-of-4 Decoder/Demultiplexer. Each half of the F139 can be used as a function generator providing all four miniterms of two variables.

Each decoder has an active LOW Enable (E).5 20 0.0 9.7 V VCC = MAX.0 V VCC = MAX.8 –1.6 –150 20 Min 2. 74 74 2. each of which accepts two binary weighted inputs (AO.5 3.5 V VCC = MAX. Address to Output Enable to Output Min 3.5 125 70 –1.0 74F TA = 0°C to 70°C VCC = 5. The enable can be used as the data input for a 4-output demultiplexer application.5 –55 0 Typ 5.0 20 mA mA Unit V °C DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH IIL IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current 54.5 Max 7.MC54/74F139 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Parameter 54.5 Max 12.0 mA IOH = –1. 2.0 V ±10% CL = 50 pF Min 3. nor for more than 1 second.0 8. IIN = –18 mA IOH = –1. These four miniterms are useful in some applications.0 8. VIN = 2.5 3. The device has two independent decoders.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay. Not more than one output should be shorted at a time. Each half of the F139 generates all four miniterms of two variables.5 2.50 V VCC = 4.0 0.5 9. VOUT = 0 V VCC = MAX 1.0 25 25 Max 5.0 V ±10% CL = 50 pF Min 2.5 ns Unit ns FUNCTIONAL DESCRIPTION The F139 is a high speed dual 1-of-4 decoder/demultiplexer fabricated with the Schottky barrier diode process. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 2.5 Max 8. VIN = 7.0 3. replacing multiple gate functions as shown in Figure 1.5 2. and thereby reducing the number of packages required in a logic network.5 2.75 V VCC = MIN VCC = MAX. 74 54.2 Typ Max Unit V V V V V V µA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.5 54F TA = -55°C to +125°C VCC = 5.0 8.0 mA IOL = 20 mA VCC = 4. use the appropriate value specified under recommended operating conditions for the applicable device type. A1) and provide four mutually exclusive active LOW outputs (O0-O3).0 7. When E is HIGH all outputs are forced HIGH. VIN = 0. 74 Min 4.0 6.5 3.0 7.5 3.1 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current -60 –0. For conditions shown as MIN or MAX.7 0. FAST AND LS TTL DATA 4-57 .5 3. 74 54 74 Output Current — High Output Current — Low 54.5 9.

MC54/74F139 FUNCTION TABLE Inputs E H L L L L A0 X L H L H A1 X L L H H O0 H L H H H O1 H H L H H Outputs O2 H H H L H O3 H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care E A0 A1 E A0 A1 E A0 A1 E A0 A1 O0 O1 E A0 A1 E A0 A1 E A0 A1 E A0 A1 O0 O1 O2 O2 O3 O3 Figure 1. FAST AND LS TTL DATA 4-58 .

MC54/74F148 8-LINE TO 3-LINE PRIORITY ENCODER The MC54/74F148 provides three bits of binary coded output representing the position of the highest order active input. along with an output indicating the presence of any active input. It is easily expanded via input and output enables to provide priority encoding over many bits. 10 11 12 13 1 2 3 4 5 I6 (3) A0 A1 A2 GS (4) (5) (6) A2 15 9 7 6 14 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-59 . • Encodes Eight Data Lines in Priority • Provides 3-Bit Binary Priority Code • Input Enable Capability • Signals When Data Present on Any Input • Cascadable for Priority Encoding of n Bits 8-LINE TO 3-LINE PRIORITY ENCODER FAST™ SHOTTKY TTL CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 EO 15 GS 14 I3 13 I2 12 I1 11 I0 10 A0 9 16 1 J SUFFIX CERAMIC CASE 620-09 16 N SUFFIX PLASTIC CASE 648-08 1 1 I4 2 I5 3 I6 4 I7 5 E1 6 A2 7 A1 8 GND LOGIC DIAGRAM 16 (10) I0 I1 (11) (15) (14) EO GS 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC I2 I3 I4 (12) (9) (13) A0 LOGIC SYMBOL (1) (7) I5 (2) A1 I0 I1 I2 I3 I4 I5 I6 I7 E1 EO I7 E1 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

A0). X = Don’t Care ENABLE A0 A1 A2 A3 FLAG Figure 1.0 20 mA mA Unit V °C FUNCTIONAL DESCRIPTION The F148 8-input priority encoder accepts data from eight active LOW inputs (I0–I7) and provides a binary representation on the three active LOW outputs. this indicates when any input is active. Both EO and GS are in the inactive HIGH state when the Enable Input is HIGH. Application: 16-Input Priority Encoder FAST AND LS TTL DATA 4-60 . A Group Signal output (GS) and Enable Output (EO) are provided along with the three priority data outputs (A2.5 125 70 –1. GS is active LOW when any input is LOW. L = LOW Voltage Level. A priority is assigned to each input so that when two or more inputs are simultaneously active. 74 54 74 IOH IOL Output Current — High Output Current — Low 54.5 –55 0 Typ 5. EO is active LOW when all inputs are HIGH. the input with the highest priority is represented on the output.0 25 25 Max 5.MC54/74F148 GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. A HIGH on the Enable Input (E1) will force all outputs to the inactive (HIGH) state and allow new data to settle without producing FUNCTION TABLE Inputs E1 H L L L L L L L L L I0 X H X X X X X X X L I1 X H X X X X X X L H I2 X H X X X X X L H H I3 X H X X X X L H H H LSB 0 1 2 3 4 5 6 7 E1 ’F148 A0 A1 A2 GS EO A0 0 I4 X H X X X L H H H H I5 X H X X L H H H H H I6 X H X L H H H H H H I7 X H L H H H H H H H GS H H L L L L L L L L A0 H H L H L H L H L H Outputs A1 H H L L H H L L H H A2 H H L L L L H H H H EO H L H H H H H H H H MSB 1 2 3 4 5 6 7 E1 ’F148 A1 A2 GS erroneous information at the outputs. with input line 7 having the highest priority. H = HIGH Voltage Level. A1. 74 54. 74 Min 4. Using the Enable Output along with the Enable Input allows cascading for priority encoding on any number of input signals.

0 7.5 8.5 3. 2.5 2.5 2.5 Max 11 13 8.5 3.0 3.0 9.0 3.35 0.0 2.0 3.5 7.5 10 ns 9.0 2.5 3.MC54/74F148 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.0 10 9.5 20 100 IIL IOS ICC I0.0 8.0 8.5 V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1.5 11 10 10.75 V VCC = MIN VCC = MAX.5 Max 10 ns 12 7.5 2. E1 I1–I7 Output Short Circuit Current (Note 2) Power Supply Current -60 23 –0.0 V NOTES: 1.5 4.0 2.0 V ± 10% CL = 50 pF Min 3.6 –1.0 4.5 54F TA = –55°C to +125°C VCC = 5.8 –1.5 7. VIN = 0 5 V MAX 0.0 0.4 0.5 Typ 7.0 3.0 ns 12 Unit FAST AND LS TTL DATA 4-61 .0 V ± 10% CL = 50 pF Min 3.0 10. VIN = 7. For conditions shown as MIN or MAX.0 6.0 13 74F TA = 0°C to 70°C VCC = 5.0 6.5 7.0 5. VIN = 2. use the appropriate value specified under guaranteed operating ranges.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay In to An Propagation Delay In to EO Propagation Delay In to GS Propagation Delay E1 to An Propagation Delay E1 to GS Propagation Delay E1 to EO Min 3. VOUT = 0 V VCC = MAX.5 9.5 2.0 3.0 2.5 4.0 Max 9. VIN = 4.0 3.4 3.0 5.7 3.5 9.7 V VCC = MAX.0 5.5 4.5 10 9.0 5.5 VCC = MAX.0 2.0 2.0 2.0 8.0 2. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.2 Typ Max Unit V V V V V V µA µA mA mA mA mA VCC = MAX.0 3.50 V VCC = 4.0 3.5 8.0 6. nor for more than 1 second.5 6.0 ns 8.5 3.5 6.0 mA IOH = –1.5 8. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.5 3.0 4.0 mA IOL = 20 mA VCC = MIN VCC = 4.5 ns 9.0 7.0 2.0 8.2 –150 35 Min 2.0 4. Not more than one output should be shorted at a time.0 10.5 ns 8.5 3.0 3.

8-position switch with the switch position controlled by the state of three Select inputs. S1. X = Don’t Care FAST AND LS TTL DATA 4-62 . The F151 can be used as a universal function generator to generate any logic function of four variables. S2. It provides in one package.MC54/74F151 8-INPUT MULTIPLEXER The MC54/74F151 is a high-speed 8-input digital multiplexer. The F151 is a logic implementation of a single pole. L = LOW Voltage Level. the ability to select one line of data from up to eight sources. Both asserted and negated outputs are provided. The logic function provided at the output is: Z = E • (I0 • S0 • S1 • S2 + I1 • S0 • S1 • S2 + I2 • S0 • S1 • S2 + I3 • S0 • S1 • S2 + I4 • S0 • S1 • S2 + I5 • S0 • S1 • S2 + I6 • S0 • S1 • S2 + I7 • S0 • S1 • S2) CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 I4 15 I5 14 I6 13 I7 12 S0 11 S1 10 S2 9 16 1 8-INPUT MULTIPLEXER FAST™ SHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 1 I3 2 I2 3 I1 4 I0 5 Z 6 Z 7 E 8 GND D SUFFIX SOIC CASE 751B-03 LOGIC DIAGRAM I0 S2 S1 S0 E I1 I2 I3 I4 I5 I6 I7 16 1 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL Z Z 12 13 14 15 1 2 3 4 7 I7 I6 I5 Z I4 I3 I2 I1 Z I0 ES S S 0 1 2 11 10 9 VCC = PIN 16 GND = PIN 8 FUNCTION TABLE Inputs E H L L L L L L L L S2 X L L L L H H H H S1 X L L H H L L H H S0 X L H L H L H L H Z H I0 I1 I2 I3 I4 I5 I6 I7 Outputs Z L I0 I1 I2 I3 I4 I5 I6 I7 5 6 H = HIGH Voltage Level. The Enable input (E) is active LOW. S0.

4 3.7 V VCC = MAX. 74 Min 4.50 V VCC = 4.5 8.0 6.75 V VCC = MIN VCC = MAX.0 Max 10 8.35 0.5 2.2 4.0 0.5 3.0 3.5 4.5 1.0 6.0 4.5 2.5 3.5 3.0 mA IOH = –1. 74 54 74 IOH IOL Output Current — High Output Current — Low 54.2 4.5 2.5 7.5 6. VOUT = 0 V VCC = MAX.0 ns 7.5 –55 0 Typ 5.7 3. 74 54.5 10.5 3. use the appropriate value specified under guaranteed operating ranges. VIN = 2.0 3. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.0 2.7 4.5 125 70 –1. For conditions shown as MIN or MAX.8 –1.0 3.5 9.0 9. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5. VIN = 0.0 6.5 7.0 mA IOL = 20 mA VCC = MIN VCC = 4.5 4.5 2.0 3. nor for more than 1 second.0 3.5 ns Unit FAST AND LS TTL DATA 4-63 .5 ns 5.MC54/74F151 GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Sn to Z Propagation Delay Sn to Z Propagation Delay E to Z Propagation Delay E to Z Propagation Delay In to Z Propagation Delay In to Z Min 4. Not more than one output should be shorted at a time.0 25 25 Max 5.0 74F TA = 0°C to 70°C VCC = 5.5 2.0 4.5 V VCC = MAX.0 3.5 9.0 20 mA mA Unit V °C DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 6.0 ns 10 11 ns 8.5 3.5 V NOTES: 1.5 54F TA = –55°C to +125°C VCC = 5.4 0.6 –150 21 Min 2.0 3.0 11.5 3.0 2. VIN = 4. VIN = 7.0 V ±10% CL = 50 pF Min 3.0 17.0 11 7.0 V ±10% CL = 50 pF Min 3.5 –0.0 Max 9.0 5.5 7. 2.2 Typ Max Unit V V V V V V µA µA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1.0 5.0 Max 8.0 2.5 1.1 8.5 20 100 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current –60 13.5 11.5 2.0 V VCC = MAX.5 1.5 14.5 7.1 13 9.0 14 ns 10.5 3.5 2.

74 54.0 25 25 Max 5. 74 54 74 IOH IOL Output Current — High Output Current — Low 54.MC54/74F153 DUAL 4-INPUT MULTIPLEXER The MC54/74F153 is a high-speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section. CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Eb 15 S0 14 I3b 13 I2b 12 I1b 11 I0b 10 Zb 9 DUAL 4-INPUT MULTIPLEXER FAST™ SHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 16 1 Ea 2 S1 3 I3a 4 I2a 5 I1a 6 I0a 7 Za 8 GND 1 LOGIC DIAGRAM Ea I0a 1 6 5 I1a 4 I2a 3 I3a 2 S1 14 S0 10 I0b 11 I1b 12 I2b 13 I3b Eb 15 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC 7 Za VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 9 Zb GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. The two buffered outputs present data in the true (non-inverted) form.5 –55 0 Typ 5. It can select two lines of data from four sources.5 125 70 –1. the F153 can generate any two functions of three variables.0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-64 . 74 Min 4. In addition to multiplexer operation.

The F153 can generate two functions of three variables. use the appropriate value specified under recommended operating conditions for the applicable device type.2 Typ Max Unit V V V V V V µA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA. VCC = MAX VIN = 7. When the Enables (Ea.0 mA IOL = 20 mA VCC = 4.0 V.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current –60 –0.MC54/74F153 FUNCTIONAL DESCRIPTION The MC54/74F153 is a Dual 4-Input Multiplexer. VCC = MAX VOUT = 0 V. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2. VCC = MIN IOL = –1. X = Don’t Care DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 V. 4-position switch. The particular register from which the data came would be determined by the state of the Select Inputs. The two 4-input multiplexer circuits have individual active LOW Enables (Ea. VCC = MAX VIN = GND.8 –1. This is useful for implementing highly irregular random logic. Eb) are HIGH. where the position of the switch is determined by the logic levels supplied to the two Select Inputs.5 2.7 V.7 0.6 –150 20 Min 2.75 V VCC = MIN VIN = 2.5 20 0. S1).50V VCC = 4. L = LOW Voltage Level. 2. VCC = MAX VIN = 0. The logic equations for the outputs are shown below: FUNCTION TABLE Select Inputs S0 X L L H H L L H H S1 X L L L L H H H H E H L L L L L L L L Inputs (a or b) I0 X L H X X X X X X I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H Output Z L L H L H L H L H Za = Ea • (I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 • S0 + I3a • S1 • S0) Zb = Eb • (I0b • S1 • S0 + I1b • S1 • S0 + I2b • S1 • S0 + I3b • S1 • S0) The F153 can be used to move data from a group of registers to a common output bus. the corresponding outputs (Za. The F153 is the logic implementation of a 2-pole.0 0. Not more than one output should be shorted at a time. FAST AND LS TTL DATA 4-65 .0 mA IOL = –1. H = HIGH Voltage Level. It can select two bits of data from up to four sources under the control of the common Select Inputs (S0. VCC = MAX NOTES: 1. nor for more than 1 second. For conditions shown as MIN or MAX. Eb) which can be used to strobe the outputs independently. A less obvious application is as a function generator. Zb) are forced LOW.

5 54F TA = -55°C to +125°C VCC = 5.5 ns ns Unit ns FAST AND LS TTL DATA 4-66 .5 2.5 8.0 Max 10.0 6.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Sn to Zn Propagation Delay En to Zn Propagation Delay In to Zn Min 4.5 Max 14 11 11.0 9.0 V ±10% CL = 50 pF Min 4.0 8.0 7.5 4.0 3.0 8.5 Max 12 10.MC54/74F153 AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.5 9.5 3.0 3.5 4.5 2.5 3.5 3.5 2.5 4.0 9.5 3.0 7.0 74F TA = 0°C to 70°C VCC = 5.5 10.0 V ±10% CL = 50 pF Min 4.5 3.5 2.0 2.5 9.0 7.

• AC Enhanced Version of the F157 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 E 15 I0c 14 I1c 13 Zc 12 I0d 11 I1d 10 Zd 9 J SUFFIX CERAMIC CASE 620-09 16 1 QUAD 2-INPUT MULTIPLEXER FAST™ SHOTTKY TTL 1 S 2 I0a 3 I1a 4 Za 5 I0b 6 I1b 7 Zb 8 GND N SUFFIX PLASTIC CASE 648-08 1 LOGIC DIAGRAM I0a I1a I0b I1b I0c I1c I0d I1d E S 16 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC74FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC Za Zb Zc Zd LOGIC SYMBOL 1 FUNCTION TABLE Inputs E H L L L L S X H H L L I0 X X X L H I1 X L H X X Output Z L L H L H 9 VCC = PIN 16 GND = PIN 8 Zd 12 Zc 7 4 Za Zb S E I0a I1a I0b I1b I0c I1c I0d I1d 15 2 3 5 6 14 13 11 10 H = HIGH Voltage Level. L = LOW Voltage Level.MC74F157A QUAD 2-INPUT MULTIPLEXER The MC74F157A is a high-speed quad 2-input multiplexer. X = Don’t Care FAST AND LS TTL DATA 4-67 . The four buffered outputs present the selected data in the true (non-inverted) form. Four bits of data from two sources can be selected using the common Select and Enable inputs. The F157A can also be used to generate any four of the 16 different functions to two variables.

0 0.7 2.5 2.5 6. A less obvious use is as a function generator.MC74F157A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4.4 Min 2.0 2.5 0 Typ 5.0 11 7.5 V VCC = MAX VCC = MAX VCC = MAX 3.0 5.5 0.5 2.5 74F TA = 0°C to 70°C VCC = 5.5 6.0 20 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH IIL IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 74 74 Output LOW Voltage Input HIGH Current 2. Not more than one output should be shorted at a time. For conditions shown as MIN or MAX. It selects four bits of data from two sources under the control of a common Select input (S).0 3.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay S to Zn Propagation Delay E to Zn Propagation Delay In to Zn Parameter Min 3. AC CHARACTERISTICS 74F TA = +25°C VCC = +5. nor for more than 1 second. The logic equations for the outputs are shown below: Za = E • (I1a • S + I0a • S) Zc = E • (I1c • S + I0c • S) A common use of the F157A is the moving of data from two groups of registers to four common output busses.6 –150 23 V µA µA mA mA mA IOL = 20 mA VIN = 2. The F157A is the logic implementation of a 4-pole. all of the outputs (Z) are forced LOW regardless of all other inputs. The particular register from which the data comes is determined by the state of the Select input.5 V VOUT = 0 V All Inputs = 4. 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input.5 20 100 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current –60 15 –0. The F157A can generate any four of the 16 different functions of two variables with one variable common.5 3.0 6. When E is HIGH.75 V VCC = 4. The Enable input (E) is active LOW.7 V VIN = 7.35 0.0 V VIN = 0.5 3.5 2.0 ns ns Unit ns FUNCTIONAL DESCRIPTION The F157A is a quad 2-input multiplexer.0 3. This is useful for implementing highly irregular logic.0 9. 2.0 25 Max 5.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1.8 –1.5 7.50 V VCC = MIN VCC = MAX NOTES: 1. Zb = E • (I1b • S + I0b • S) Zd = E • (I1d • S + I0d • S) FAST AND LS TTL DATA 4-68 .5 Max 10 7.0 V ±10% CL = 50 pF Min 3.0 mA VCC = MIN VCC = 4. use the appropriate value specified under guaranteed operating ranges.5 70 –1.0 2.5 2.0 Max 11 8.

MC74F158A QUAD 2-INPUT MULTIPLEXER The MC74F158A is a high-speed quad 2-input multiplexer. • AC Enhanced Version of the F158 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 E 15 I0c 14 I1c 13 Zc 12 I0d 11 I1d 10 Zd 9 J SUFFIX CERAMIC CASE 620-09 16 1 QUAD 2-INPUT MULTIPLEXER FAST™ SHOTTKY TTL 1 S 2 I0a 3 I1a 4 Za 5 I0b 6 I1b 7 Zb 8 GND 16 LOGIC DIAGRAM I0a I1a I0b I1b I0c I1c I0d I1d E S N SUFFIX PLASTIC CASE 648-08 1 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC74FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL Za Zb Zc Zd 1 FUNCTION TABLE Inputs E H L L L L S X L L H H I0 X L H X X I1 X X X L H Output Z H H L H L 9 VCC = PIN 16 GND = PIN 8 Zd 12 4 7 Za Zb Zc S E I0a I1a I0b I1b I0c I1c I0d I1d 15 2 3 5 6 14 13 11 10 H = HIGH Voltage Level. L = LOW Voltage Level. It selects four bits of data from two sources using the common Select and Enable inputs. The F158A can also generate any four of the 16 different functions of two variables. The four buffered outputs present the selected data in the inverted form. X = Don’t Care FAST AND LS TTL DATA 4-69 .

50 V VCC = MIN VCC = MAX VCC = MAX.5 2.9 4. The F158A can generate four functions of two variables with one variable in common.5 7.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay S to Z Propagation Delay E to Zn Propagation Delay In to Z Parameter Min 3. AC CHARACTERISTICS 74F TA = +25°C VCC = +5.0 V ±10% CL = 50 pF Min 3.MC74F158A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4.0 2. The Enable input (E) is active LOW.5 0 Typ 5.5 6.0 20 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH IIL IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 74 74 Output LOW Voltage Input HIGH Current 2. When E is HIGH.0 Max 8.5 20 100 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current (Note 3) –60 10 –0.0 Max 9.7 2. nor for more than 1 second.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1. The particular register from which the data comes is determined by the state of the Select input.0 6. The F158A is the logic implementation of a 4-pole.5 70 –1.4 Min 2.6 –150 15 V µA µA mA mA mA IOL = 20 mA VIN = 2.8 –1.0 2.0 V VIN = 0.0 74F TA = 0°C to 70°C VCC = 5.7 V VIN = 7.5 V VOUT = 0 V VCC = MAX VCC = MAX 3. 3. A less obvious use is as a function generator. 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. ICC measured with outputs open and 4. This is useful for implementing gating functions.0 5. 2. VIN = HIGH NOTES: 1. A common use of the F158A is the moving of data from two groups of registers to four common output busses.0 1.0 1.0 2.0 mA VCC = MIN VCC = 4.0 0. FAST AND LS TTL DATA 4-70 .5 7.5 V applied to all inputs.5 6.0 4.35 0.5 0.5 2.5 2. For conditions shown as MIN or MAX. Not more than one output should be shorted at a time.5 2.0 7. use the appropriate value specified under guaranteed operating ranges.0 25 Max 5. all of the outputs (Z) are forced HIGH regardless of all other inputs.0 6.75 V VCC = 4.0 2.5 ns ns Unit ns FUNCTIONAL DESCRIPTION The F158A quad 2-input multiplexer selects four bits of data from two sources under the control of a common Select input (S) and presents the data in inverted form at the four outputs.

SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER The MC74F160A and MC74F162A are high-speed synchronous decade counters operating in the BCD (8421) sequence. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC74F162A has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. X = Don’t Care STATE DIAGRAM 0 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 7 10 2 PE P0 P1 P2 P3 CEP TC CET CP *R Q0 Q1 Q2 Q3 1 14 13 12 11 15 VCC = PIN 16 GND = PIN 8 *MR for MC74F160A *SR for MC74F162A FAST AND LS TTL DATA 4-71 . The MC74F160A has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. L = LOW Voltage Level. • Synchronous Counting and Loading • High-Speed Synchronous Expansion • Typical Count Rate of 120 MHz CONNECTION DIAGRAM VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9 MC74F160A MC74F162A SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER FAST™ SHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 1 *R 2 CP 3 4 P1 5 P2 6 P3 7 CEP 8 GND 16 1 P0 *MR for MC74F160A *SR for MC74F162A D SUFFIX SOIC CASE 751B-03 FUNCTION TABLE SR L H H H H PE X L H H H CET X X H L X CEP X X H X L ACTION ON THE RISING CLOCK EDGE ( Reset (Clear) Load (Pn → Qn) Count (Increment) No Change (Hold) No Change (Hold) ) ORDERING INFORMATION MC74FXXXAJ MC74FXXXAN MC74FXXXAD Ceramic Plastic SOIC LOGIC SYMBOL 9 3 4 5 6 H = HIGH Voltage Level.

with respect to the rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. Conversely. The MC74F160A and MC74F162A use D-type edge-triggered flip-flops and changing the SR. CEP. FAST AND LS TTL DATA 4-72 . synchronous reset (MC74F162A). From state 9 (HLLH) they increment to state 0 (LLLL). Count Enable Parallel (CEP) and Count Enable Trickle (CET) — determine the mode of operation. in order of precedence: asynchronous reset (MC74F160A).MC74F160A • MC74F162A LOGIC DIAGRAM P0 PE MC74F160A CEP CET MC74F162A ONLY TC MC74F162A P1 P2 P3 CP CP MC74F160A ONLY Q0 CP D CP D CD Q Q Q0 DETAIL A DETAIL A DETAIL A MR (MC74F160A) DETAIL A SR (MC74F162A) Q0 Q1 Q2 Q3 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Parallel Enable (PE). Synchronous Reset (SR. provided that the recommended setup and hold times. and CET inputs when the CP is in either state does not cause errors. all changes of the Q outputs (except due to Master Reset of the MC74F160A) occur as a result of. The clock inputs of all flip-flops are driven in parallel through a clock buffer. With PE and MR (MC74F160A) or SR (MC74F162A) HIGH. MC74F162A). count-up and hold. FUNCTIONAL DESCRIPTION The MC74F160A and MC74F162A count modulo-10 in the BCD (8421) sequence. MC74F160A). Thus. parallel load. are observed. PE. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. and synchronous with. CEP and CET permit counting when both are HIGH. the LOW-to-HIGH transition of the CP input signal. as shown in the Function Table. The circuits have four fundamental modes of operation. a LOW signal on either CEP or CET inhibits counting. Five control inputs — Master Reset (MR.

2 – 150 55 Min 2.0 V VCC = MAX.0 mA IOH = –1. For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions for the applicable device type.8 –1.5 0 Typ 5. To implement synchronous multistage counters.7 V VCC = MAX.5 2.4 3. Not more than one output should be shorted at a time. or registers. VIN = 0. or assumes an illegal state when power is applied. Logic Equations: Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET FAST AND LS TTL DATA 4-73 .0 mA IOL = 20 mA VCC = 4.7 3. If a decade counter is preset to an illegal state. it will return to the normal sequence within two counts. nor for more than 1 second.MC74F160A • MC74F162A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4.5 V VCC = MAX. SR Output Short Circuit Current (Note 2) Power Supply Current –60 37 –0.5 20 0. The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in state 9.2 Typ Max Unit V V V V V V µA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. Data. Clock PE. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops. IIN = – 18 mA IOH = –1. CEP.75 V VCC = MIN VCC = MAX. Please refer to the MC74F568 data sheet. the TC outputs can be used with the CEP and CET inputs in two different ways. counters.50 V VCC = 4.1 IIL IOS ICC Input LOW Current MR.6 –1. CET. VIN = 7. In the MC74F160A and MC74F162A decade counters.0 0.0 20 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.4 0. as shown in the State Diagram. 2.5 70 –1.0 25 Max 5. VOUT = 0 V VCC = MAX NOTES: 1. VIN = 2.35 0. the TC output is fully decoded and can only be HIGH in state 9.

HIGH or LOW PE or SR to CP Hold Time.5 8.5 4.5 3.0 0 0 5.0 5.5 3.5 5.0 ns ns ns ns ns 74F TA = 0°C to 70°C VCC = 5.5 3. HIGH or LOW CEP or CET to CP Hold Time.5 13 11.5 10 8.0 0 11.5 2.0 6.0 5.5 2.0 4.0 2.0 5.0 5.5 7.0 11 8.5 9.0 4.5 5.5 Max Min 90 3.5 2.5 11 9.5 8.5 8. Count CP to Qn (PE Input HIGH) Propagation Delay CP to Qn (PE Input LOW) Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay MR to Qn (MC74F160A) Propagation Delay MR to TC (MC74F160A) Min 100 3.0 5.0 0 11 5. MR to CP (MC74F160A) Min 5.0 2.5 ns ns ns ns ns 74F TA = 0°C to 70°C VCC = 5.0 V ± 10% CL = 50 pF Max Unit FAST AND LS TTL DATA 4-74 .0 4.0 5. HIGH or LOW Pn to CP Hold Time.MC74F160A • MC74F162A AC CHARACTERISTICS 74F TA = +25°C VCC = +5.0 2.5 2.5 5.5 12 10. HIGH or LOW CEP or CET to CP Clock Pulse Width (Load) HIGH or LOW Clock Pulse Width (Count) HIGH or LOW MR Pulse Width.5 7.0 5.0 2.5 4.5 3.5 4.0 V CL = 50 pF Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL Parameter Maximum Count Frequency Propagation Delay.5 9.0 ns 6. HIGH or LOW PE or SR to CP Setup Time.0 6.0 4.0 V ± 10% CL = 50 pF Max Unit MHz AC OPERATING REQUIREMENTS 74F TA = +25°C VCC = +5.5 14 14 7.0 7.5 4.5 15 15 8.5 2.0 0 0 5.5 2.0 Max Min 5. LOW (MC74F160A) Recovery Time.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) tH(L) tw(H) tw(L) tw(H) tw(L) tw(L) trec Parameter Setup Time. HIGH or LOW Pn to CP Setup Time.0 5.0 11.

They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC74F161A has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. X = Don’t Care STATE DIAGRAM 0 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 7 10 2 PE P0 P1 P2 P3 CEP TC CET CP *R Q0 Q1 Q2 Q3 1 14 13 12 11 15 VCC = PIN 16 GND = PIN 8 *MR for MC74F161A *SR for MC74F163A FAST AND LS TTL DATA 4-75 .SYNCHRONOUS PRESETTABLE BINARY COUNTER The MC74F161A and MC74F163A are high-speed synchronous modulo-16 binary counters. • Synchronous Counting and Loading • High-Speed Synchronous Expansion • Typical Count Frequency of 120 MHz CONNECTION DIAGRAM 16 MC74F161A MC74F163A SYNCHRONOUS PRESETTABLE BINARY COUNTER FAST™ SHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 1 VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9 16 1 N SUFFIX PLASTIC CASE 648-08 1 *R 2 CP 3 P0 4 P1 5 P2 6 P3 7 CEP 8 GND 16 1 *MR for MC74F161A *SR for MC74F163A D SUFFIX SOIC CASE 751B-03 FUNCTION TABLE SR L H H H H PE X L H H H CET X X H L X CEP X X H X L ACTION ON THE RISING CLOCK EDGE ( Reset (Clear) Load (Pn → Qn) Count (Increment) No Change (Hold) No Change (Hold) ) ORDERING INFORMATION MC74FXXXAJ Ceramic MC74FXXXAN Plastic MC74FXXXAD SOIC LOGIC SYMBOL 9 3 4 5 6 H = HIGH Voltage Level. L = LOW Voltage Level. The MC74F163A has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock.

PE. From state 15 (HHHH) they increment to state 0 (LLLL). Count Enable Parallel (CEP) and Count Enable Trickle (CET) — determine the mode of operation. synchronous reset (MC74F163A). CEP. Thus all changes of the Q outputs (except due to Master Reset of the MC74F161A) occur as a result of. parallel load. provided that the recommended setup and hold times. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. FUNCTIONAL DESCRIPTION The MC74F161A and MC74F163A count in modulo-16 binary sequence. The MC74F161A and MC74F163A use D-type edge-triggered flip-flops and changing the SR. CEP and CET permit counting when both are HIGH. and synchronous with. in order of precedence: asynchronous reset (MC74F161A). count-up and hold. with respect to the rising edge of CP. a LOW signal on either CEP or CET inhibits counting. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. Synchronous Reset (SR. The clock inputs of all flip-flops are driven in parallel through a clock buffer. and CET inputs when the CP is in either state does not cause errors. the LOW-to-HIGH transition of the CP input signal. MC74F163A). Five control inputs  Master Reset (MR. FAST AND LS TTL DATA 4-76 . The circuits have four fundamental modes of operation. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. Conversely. as shown in the Function Table.MC74F161A • MC74F163A LOGIC DIAGRAM P0 PE MC74F161A CEP CET MC74F163A ONLY TC MC74F163A P1 P2 P3 CP CP MC74F161A ONLY Q0 CP D CP D CD Q Q Q0 DETAIL A DETAIL A DETAIL A MR (MC74F161A) DETAIL A SR (MC74F163A) Q0 Q1 Q2 Q3 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. MC74F161A). With PE and MR (MC74F161A) or SR (MC74F163A) HIGH. Parallel Enable (PE). are observed.

50 V VCC = 4. SR Output Short Circuit Current (Note 2) Power Supply Current –60 37 –0. or registers.8 –1. For conditions shown as MIN or MAX.4 0. VOUT = 0 V VCC = MAX NOTES: 1.5 0 Typ 5. VIN = 2.2 Typ Max Unit V V V V V V µA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.4 3.7 3. To implement synchronous multistage counters.0 0.1 IIL IOS ICC Input LOW Current Data. 2.0 V VCC = MAX. The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in state 15. Not more than one output should be shorted at a time.5 V VCC = MAX. VIN = 7. The TC output is subject to decoding spikes due to internal race conditions and is there- fore not recommended for use as a clock or asynchronous reset for flip-flops.5 2.35 0. CEP.5 20 0.7 V VCC = MAX. Clock PE. nor for more than 1 second. Logic Equations: Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET FAST AND LS TTL DATA 4-77 .2 – 150 55 Min 2.0 20 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.0 25 Max 5. VIN = 0. CET. use the appropriate value specified under recommended operating conditions for the applicable device type.5 70 – 1. IIN = – 18 mA IOH = –1. the TC outputs can be used with the CEP and CET inputs in two different ways.6 –1. counters.MC74F161A • MC74F163A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4.75 V VCC = MIN VCC = MAX.0 mA IOH = –1.0 mA IOL = 20 mA VCC = 4.

5 2. LOW (MC74F161A) Recovery Time.0 4.5 12 10.0 7.0 10 7.0 11.0 5.0 5. HIGH or LOW PE or SR to CP Setup Time.5 ns ns ns ns ns 74F TA = 0°C to 70°C VCC = 5.5 2.0 0 11.0 5.5 7.0 2.0 ns ns ns ns ns 74F TA = 0°C to 70°C VCC = 5.0 V CL = 50 pF Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL Parameter Maximum Count Frequency Propagation Delay.5 9.5 2.5 5.5 15 15 8.5 4.5 14 14 7.5 2.0 5.0 11 9.0 2.5 9.5 3.5 5.0 V ± 10% CL = 50 pF Max Unit FAST AND LS TTL DATA 4-78 .0 0 11 5.0 2.5 4. HIGH or LOW Pn to CP Setup Time.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) tw(L) tw(L) trec Parameter Setup Time.0 5.5 2.0 11 8.5 2.0 4.5 Max Min 90 3.0 2. HIGH or LOW PE or SR to CP Hold Time.0 Max Min 5.5 5.5 4.5 7.0 6. HIGH or LOW Pn to CP Hold Time.5 3.5 3. MR to CP (MC74F161A) Min 5. HIGH or LOW CEP or CET to CP Clock Pulse Width (Load) HIGH or LOW Clock Pulse Width (Count) HIGH or LOW MR Pulse Width.0 0 0 5.0 ns 6.5 4.0 8.5 6.0 6.0 4.0 4.0 5. Count CP to Qn (PE Input HIGH) Propagation Delay CP to Qn (PE Input LOW) Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay MR to Qn (MC74F161A) Propagation Delay MR to TC (MC74F161A) Min 100 3. HIGH or LOW CEP or CET to CP Hold Time.5 13 11.MC74F161A • MC74F163A AC CHARACTERISTCS 74F TA = +25°C VCC = +5.0 5.0 5.0 0 0 5.5 8.0 V ± 10% CL = 50 pF Max Unit MHz AC OPERATING REQUIREMENTS 74F TA = +25°C VCC = +5.5 3.

FAST AND LS TTL DATA 4-79 . The device features an asynchronous Master Reset which clears the register. PARALLEL-OUT SHIFT REGISTER The MC54/74F164 is a high-speed 8-bit serial-in/parallel-out shift register. Serial data is entered through a 2-input AND gate synchronous with the LOW-to-HIGH transition of the clock.MC54/74F164 8-BIT SERIAL-IN. PARALLEL-OUT SHIFT REGISTER FAST™ SHOTTKY TTL • • • • Typical Shift Frequency of 90 MHz Asynchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers J SUFFIX CERAMIC CASE 632-08 1 14 CONNECTION DIAGRAM VCC 14 Q7 13 Q6 12 Q5 11 Q4 10 MR 9 CP 8 14 1 N SUFFIX PLASTIC CASE 646-06 1 A 2 B 3 Q0 4 Q1 5 Q2 6 Q3 7 GND 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Inputs Operating Mode Reset (Clear) Shift MR L H H H H A X l l h h B X l h l h Q0 L L L L H Outputs Q1 –Q7 L–L q0–q6 q0–q6 q0–q6 q0–q6 1 2 8 A B CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 3 4 5 6 10 11 12 13 VCC = PIN 14 GND = PIN 7 Ceramic Plastic SOIC MODE SELECT TABLE LOGIC SYMBOL H(h) = HIGH Voltage Levels L(l) = LOW Voltage Levels X = Don’t Care qn = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. setting all outputs LOW independent of the clock. 8-BIT SERIAL-IN.

GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. VIN = 0. VCC = MAX CP = HIGH. VOUT = 0 V A.8 –1.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current –60 35 –0.6 –150 55 Min 2. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2. VIN = 2. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.75 V VCC = MIN VCC = MAX. either of these inputs can be used as an active HIGH Enable for data entry through the other input.0 25 25 Max 5.0 20 mA mA Unit V °C Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A • B) that existed before the rising clock edge.0 0. VIN = 7.5 20 0.0 mA IOH = –1.5 2.7 0.2 Typ Max Unit V V V V V V µA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.5 125 70 –1. B = GND. IIN = –18 mA IOH = –1.0 V VCC = MAX. forcing all Q outputs LOW. 74 Min 4. An unused input must be tied HIGH.0 mA IOL = 20 mA VCC = MIN VCC = 4. use the appropriate value specified under recommended operating conditions for the applicable device type. FAST AND LS TTL DATA 4-80 . A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously. MR = GND NOTES: 1.7 V VCC = MAX. For conditions shown as MIN or MAX.5 V VCC = MAX. Data is entered serially through one of two inputs (A or B). 74 54 74 IOH IOL Output Current  High Output Current  Low 54. nor for more than 1 second.MC54/74F164 LOGIC DIAGRAM A B D Q CD D Q CD D Q CD D Q CD D Q CD D Q CD D Q CD D Q CD CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FUNCTIONAL DESCRIPTION The F164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Not more than one output should be shorted at a time. 2. 74 54.5 –55 0 Typ 5.

0 V Symbol ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec MR Pulse Width.0 5.0 11 14 ns Max Unit MHz ns AC OPERATING REQUIREMENTS 54/74F TA = + 25°C VCC = + 5.0 ns ns ns ns Max Unit FAST AND LS TTL DATA 4-81 .0 V ± 10% CL = 50 pF Min 80 3.0 5.5 11 13 16 Max 74F TA = 0°C to + 70°C VCC = 5.0 5.0 1.0 7.0 V CL = 50 pF Symbol fmax tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay MR to Qn Min 80 3.0 7.0 1.0 1.5 10.0 4.0 10 13 Max 54F TA = –55°C to +125°C VCC = 5.0 V ± 10% Min 7.0 7.0 Typ Max 54F TA = –55°C to +125°C VCC = 5.0 1.0 V ± 10% Min 7. HIGH or LOW Dn to CP CP Pulse Width.0 1.0 4.0 7.0 7. HIGH or LOW Min 7.0 7.0 5. LOW Recovery Time.5 8.5 Typ 90 6.0 7.MC54/74F164 AC CHARACTERISTICS 54/74F TA = + 25°C VCC = + 5.0 7. HIGH or LOW Dn to CP Hold Time.0 V ± 10% CL = 50 pF Min 70 3.0 5.0 7.0 1.0 7.0 4.0 7.5 9.0 5. MR to CP Parameter Setup Time.0 7.0 7.0 Max 74F TA = 0°C to + 70°C VCC = + 5.

the F169 is a modulo-16 binary counter. whether in counting or parallel loading. The F168 is a BCD decade counter. L = LOW Voltage Level. and a U/D input to control the direction of counting. X = Don’t Care STATE DIAGRAMS MC54/74F169 0 1 2 3 4 LOGIC SYMBOL 9 3 4 5 6 PE P0 P1 P2 P3 U/D CEP TC CET CP Q0 Q1 Q2 Q3 14 13 12 11 MC54/74F168 0 1 2 3 15 5 1 7 10 2 10 9 11 15 4 14 13 14 6 15 13 7 VCC = Pin 16 GND = Pin 8 8 7 6 5 12 12 11 10 9 8 COUNT DOWN COUNT UP COUNT DOWN COUNT UP FAST AND LS TTL DATA 4-82 .4-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTERS The MC54/74F168 and MC54/74F169 are fully synchronous 4-stage up/ down counters. All state changes. carry lookahead for easy cascading. • Asynchronous Counting and Loading • Built-In Lookahead Carry Capability • Presettable for Programmable Operation CONNECTION DIAGRAM (TOP VIEW) VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9 16 MC54/74F168 MC54/74F169 4-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTERS FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 1 16 N SUFFIX PLASTIC CASE 648-08 1 1 U/D 2 CP 3 P0 4 P1 5 P2 6 P3 7 CEP 8 GND MODE SELECT TABLE PE L H H H H CEP X L L H X CET X L L X H U/D X H L X X Action on Rising Clock Edge Load (Pn → Qn) Count Up (Increment) Count Down (Decrement) No Change (Hold) No Change (Hold) 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC H = HIGH Voltage Level. Both feature a preset capability for programmable operation. are initiated by the LOW-to-HIGH transition of the clock.

Q0 Q1 Q2 Q3 FAST AND LS TTL DATA 4-83 .MC54/74F168 • MC54/74F169 LOGIC DIAGRAMS MC54/74F168 PE CEP CET P0 P1 P2 P3 T LD AT AF TC LD T BT BF UP DN DETAIL A ENF CP Q ENF U/D UP DN DETAIL A DETAIL A CP CP DETAIL A Q Q0 J CP K Q Q Q1 Q2 Q3 MC54/74F169 PE CEP CET P0 P1 P2 P3 T LD AT AF TC LD T BT BF ENF U/D UP DN UP DN DETAIL A ENF CP DETAIL A J CP K Q Q CP Q DETAIL A DETAIL A CP Q NOTE: These diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Not more than one output should be shorted at a time.5 –55 0 Typ 5.4 0.1 Input LOW Current IIL IOS ICC CET Other Inputs Output Short Circuit Current (Note 2) Power Supply Current –60 –1.0 V NOTES: 1. In order for counting to occur.0 mA IOH = – 1. as indicated in the Mode Select Table.MC54/74F168 • MC54/74F169 FUNCTIONAL DESCRIPTION The F168 and F169 use edge-triggered J-K type flip-flops and have no constraints on changing the control or data input signals in either state of the clock.0 mA IOL = 20 mA VCC = 4. 74 Min 4. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.8 –1. The Terminal Count (TC) output is normally HIGH and goes LOW.35 0. both CEP and CET must be LOW and PE must be HIGH. For this reason the use of TC as a clock signal is not recommended (see logic equations below). 2.5 125 70 –1. The TC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54. provided that CET is LOW.5 V Min 2. the U/D input then determines the direction of counting.50 V VCC = 4.0 0. When PE is LOW.7 V VCC = MAX. VIN = 0. 74 54 74 54.0 25 25 Max 5.5 2. For conditions shown as MIN or MAX.4 3.0 20 mA mA Unit V °C output state is not a function of the Count Enable Parallel (CEP) input level. 74 54.5 20 0. when a counter reaches zero in the Count Down mode or reaches 9 (15 for the F169) in the Count Up mode.7 3.2 Typ Max Unit V V V V V V µA mA Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. 1) Count Enable = CEP • CET • PE 2) Up: (′F168): TC = Q0 • Q1 • Q2 • Q3 • (Up) • CET (′F169): TC = Q0 • Q1 • Q2 • Q3 • (Up) • CET 3) Down: TC = Q0 • Q1 • Q2 • Q3 • (Down) • CET DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. the F168 will return to the legitimate sequence within two counts. which can occur when power is turned on or via parallel loading. VIN = 7.75 V VCC = MIN VCC = MAX. The parallel load operation takes precedence over other operations. If an illegal state occurs. there exists the possibility of decoding spikes on TC. The TC output of the F168 decade counter can also be LOW in the illegal states 11. 13. and 15. IIN = – 18 mA IOH = – 1. FAST AND LS TTL DATA 4-84 . the data on the P0-P3 inputs enters the flip-flops on the next rising edge of the clock. VOUT = 0 V VCC = MAX mA VCC = MAX.2 –0. nor for more than 1 second. Since the TC signal is derived by decoding the flip-flop states.6 –150 52 mA mA VCC= MAX. VIN = 2. use the appropriate value specified under recommended operating conditions for the applicable device type.

5 17 12.0 10.0 4.5 17.0 V CL = 50 pF Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay CP to Qn (PE HIGH or LOW) Propagation Delay CP to TC Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay U/D to TC Propagation Delay U/D to TC (F169) (F168) (F169) (F168) Min 100 3.5 11 7.0 5.0 V Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Setup Time.MC54/74F168 • MC54/74F169 AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 0 0 10 10 0 0 13.0 5.5 3. HIGH or LOW (F169) U/D to CP Hold time.0 0 0 12.5 2.5 12 Max Unit MHz ns ns ns ns ns ns AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = +5.5 7.5 3.0 V ± 10% Min 5.0 12.5 7.5 4.0 7.5 4.0 4.0 0 0 8.0 Max 74F TA = 0°C to 70°C VCC = 5.0 0 0 5.0 2.5 4.0 0 0 8. HIGH or LOW Pn to CP Setup Time.0 5.0 4.0 5.0 3.0 2.5 18 13.5 14 18 13.5 5.5 3.0 5. HIGH or LOW Pn to CP Hold Time.0 5.5 5.5 Max Unit ns ns ns ns ns ns ns ns ns ns FAST AND LS TTL DATA 4-85 .5 2.5 18.0 8.5 11.5 8.5 13 17 12.0 3.5 3.5 Max 60 3.5 15.5 12.0 4.0 4.5 13.0 9.0 V ± 10% CL = 50 pF Min Max 74F TA = 0°C to 70°C VCC = 5.5 3.5 13 54F TA = –55°C to +125°C VCC = 5.0 3.0 8.5 4.0 0 0 11 16.0 9.0 4.0 0 0 5.0 5.0 11 16 11 10.0 4.5 18 12.0 2.0 3.5 19 13.0 6.5 6.0 Max 54F TA = –55°C to +125°C VCC = 5.5 11 15.0 5.0 3.0 0 0 9.5 3.0 5.0 9.0 V ± 10% Min 4.5 8.5 11 6.5 9.0 V ± 10% CL = 50 pF Min 85 3.5 2. HIGH or LOW (F168) U/D to CP Setup Time. HIGH or LOW PE to CP Setup Time.5 4.0 8.0 10 13.5 3. HIGH or LOW PE to CP Hold Time.0 8.5 4.5 4.5 4.5 4. HIGH or LOW U/D to CP CP Pulse Width HIGH or LOW Min 4. HIGH or LOW CEP or CET to CP Hold Time HIGH or LOW CEP or CET to CP Setup Time.5 4.

MC54/74F174 HEX D FLIP-FLOP WITH MASTER RESET The MC54/74F174 is a high-speed hex D flip-flop. The F174 is useful for applications where only the true output is required and the Clock and Master Reset are common to all storage elements. The F174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. • Six Edge-triggered D-type Inputs • Buffered Positive Edge-triggered Common Clock • Buffered. The state of each D input. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Asynchronous Common Reset 16 1 HEX D FLIP-FLOP WITH MASTER RESET FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q5 15 D5 14 D4 13 Q4 12 D3 11 Q3 10 CP 9 N SUFFIX PLASTIC CASE 648-08 1 16 16 1 D SUFFIX SOIC CASE 751B-03 1 MR 2 Q0 3 D0 4 D1 5 Q1 6 D2 7 Q2 8 GND ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC FUNCTION TABLE Inputs @ tn. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. is transferred to the corresponding flig-flop’s Q output. The device has a Master Reset to simultaneously clear all flip-flops. one setup time before low-to-high clock transition. The device is used primarily as a 6-bit edge-triggered storage register. MR = H Dn H L tn = Bit time before clock pulse tn + 1 = Bit time after clock pulse H = HIGH Voltage Level L = LOW Voltage Level Outputs @ tn + 1 Qn H 14 L 13 11 6 4 3 D5 D4 D3 D2 D1 D0 Q5 Q4 Q3 Q2 Q1 Q0 CP MR 9 1 15 12 10 7 5 2 LOGIC SYMBOL VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-86 .

1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current – 60 30 –0. VIN = 7.6 –150 45 Min 2. nor for more than 1 second. Not more than one output should be shorted at a time.5 –55 0 Typ 5. 74 Min 4. VIN = 2.5 125 70 –1. 74 54.0 mA IOL = – 1.50 V VCC = 4.5 2.7 V VCC = MAX.7 0.0 20 mA mA Unit V °C DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.0 0.0 25 25 Max 5. For conditions shown as MIN or MAX.8 –1.5 20 0.MC54/74F174 LOGIC DIAGRAM MR CP D5 D4 D3 D2 D1 D0 D Q D Q D Q D CP CD Q D CP CD Q D Q CP CD CP CD CP CD CP CD Q5 Q4 Q3 Q2 Q1 Q0 GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. Dn = MR = 4.0 mA IOL = 20 mA VCC = 4. FAST AND LS TTL DATA 4-87 . IIN = – 18 mA IOL = – 1. 2. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2. VIN = 0.75 V VCC = MIN VCC = MAX. use the appropriate value specified under recommended operating conditions for the applicable device type.5 V VCC = MAX. VOUT = 0 V VCC = MAX.2 Typ Max Unit V V V V V V µA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.5 V. CP = NOTES: 1.0 V VCC = MAX. 74 54 74 IOH IOL Output Current — High Output Current — Low 54.

0 max 74F TA = 0°C to +70°C VCC = 5.0 6.0 Max 74F TA = 0°C to +70°C VCC = 5.0 5.0 V ± 10% CL = 50 pF Min 80 3.0 V CL = 50 pF Symbol fmax tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay MR to Qn Min 100 3.0 4.0 5.0 6.0 V ± 10% CL = 50 pF Min 80 3.0 1.MC54/74F174 AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 6.0 10.0 V ± 10% Min 4.0 1. HIGH or LOW MR Pulse Width LOW Recovery Time MR to CP Min 4.5 5.0 12.0 Typ 140 5.5 4. HIGH or LOW Dn to CP Hold Time.0 5.0 10 14 Max 54F TA = –55°C to +125°C VCC = 5.5 7.5 4.0 0 0 4.0 V Symbol ts(H) ts (L) th(H) th(L) tw(H) tw(L) tw(L) trec Parameter Setup Time.0 0 0 4.0 5.5 4.0 4.0 Typ Max 54F TA = –55°C to +125°C VCC = 5.0 11.0 9.0 16.5 5.0 15.0 5.0 4.0 10 8.5 5.0 ns Max Unit MHz ns AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = +5.0 ns ns ns ns Max Unit FAST AND LS TTL DATA 4-88 .0 V ± 10% Min 4.0 5.0 4. HIGH or LOW Dn to CP CP Pulse Width.

independent of the Clock or D inputs when LOW. A Master Reset input resets all flip-flops. MR = H Dn L H Qn L H Outputs @ tn + 1 Qn H L ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 1 9 tn = Bit time before clock positive-going transition tn + 1 = Bit time after clock positive-going transition H = HIGH Voltage Level L = LOW Voltage Level 3 2 6 7 11 10 14 15 MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 CP D0 D1 D2 D3 4 5 12 13 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-89 .MC54/74F175 QUAD D FLIP-FLOP The MC54/74F175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where both true and complementary outputs are required and clock and clear inputs are common to all flip-flops. • Four Edge-triggered D-type Inputs • Buffered Positive Edge-triggered Common Clock • Buffered Asynchronous Common Reset • True and Complementary Outputs • ESD > 4000 Volts 16 QUAD D FLIP-FLOP FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 16 N SUFFIX PLASTIC CASE 648-08 1 1 MR 2 Q0 3 Q0 4 D0 5 D1 6 Q1 7 Q1 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 FUNCTION TABLE Inputs @ tn. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided.

5 125 70 –1.5 –0.50 V VCC = 4.8 –1.0 V VIN = 0. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. 2.7 3. nor for more than 1 second. FAST AND LS TTL DATA 4-90 . 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2. 74 Min 4.7 V VIN = 7. The four flip-flops will store the state of their individual D inputs. The Clock and Master Reset are common.5 V CP = VCC = MIN VCC = 4.4 3.0 0. For conditions shown as MIN or MAX. on the LOW-to-HIGH clock (CP) transition.5 20 100 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current –60 22. FUNCTIONAL DESCRIPTION The F175 consists of four edge-triggered D flop-flops with individual D inputs and Q and Q outputs.0 mA IOH = – 1.0 25 25 Max 5.MC54/74F175 LOGIC DIAGRAM MR CP D3 D2 D1 D0 D CP CD Q Q D Q D Q D Q CP Q CD CP Q CD Q CP CD Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.2 Typ Max Unit V V V V V V µA µA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = – 1.0 mA IOL = 20 mA VIN = 2.5 V VOUT = 0 V Dn = MR = 4. use the appropriate value specified under guaranteed operating ranges. one setup time before.5 –55 0 Typ 5.35 0.4 0.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX NOTES: 1.0 20 mA mA Unit V °C Q outputs to follow.6 –150 34 Min 2. Not more than one output should be shorted at a time. 74 54 74 IOH IOL Output Current — High Output Current — Low 54. 74 54. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 2. The F175 is useful for general logic applications where a common Master Reset and Clock are acceptable. causing individual Q and GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.

0 V ± 10% CL = 50 pF Min 100 3.5 11.0 10 4.5 Max 54F TA = –55°C to +125°C VCC = 5.0 1.0 1.0 1.0 5.0 5.0 ns Min 100 3.0 5.0 V ± 10% Min 3.0 6.0 ns ns ns ns Max Unit FAST AND LS TTL DATA 4-91 .0 5.5 15 Max 74F TA = 0°C to +70°C VCC = 5.0 Typ Max 54F TA = –55°C to +125°C VCC = 5.0 1.5 8.5 4. MR to CP Min 3.5 4.0 V ± 10% CL = 50 pF Min 100 3. LOW Recovery Time.MC54/74F175 AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5. HIGH or LOW Dn to CP CP Pulse Width.0 4.0 3.0 5.0 4.5 4.0 V CL = 50 pF Symbol fmax tPLH tPHL tPHL tPLH Parameter Maximum Clock Frequency Propagation Delay CP to Qn or Qn Propagation Delay MR to Qn Propagation Delay MR to Qn 4.5 9.0 9.0 6.5 8. HIGH or LOW MR Pulse Width.0 1.5 Typ 140 5.0 5.0 5.0 1.0 3.0 4.0 V Symbol ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Parameter Setup Time.0 Max 74F TA = 0°C to +70°C VCC = 5.5 10.5 9.0 5.0 4. HIGH or LOW Dn to CP Hold Time.0 4.5 7.0 4.0 3.0 6.5 4.0 V ± 10% Min 3.0 5.5 8.5 13 ns Max Unit MHz ns AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = +5.

ie.5 – 55 Typ 5.MC54/74F181 4-BIT ARITHMETIC LOGIC UNIT The MC54/74F181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations. Plus Twelve Other Arithmetic Operations • Provides all 16 Logic Operations of Two Variables. It is 40% faster than the Schottky ALU and only consumes 30% as much power. ie. Add.0 5. 74 54.5 125 Unit V °C mA V mA FAST AND LS TTL DATA 4-92 . 74 54. Compare. • Provides 16 Arithmetic Operations. NOR. Compare. 74 0 25 70 –1. 74 54 Min 4. Subtract. NAND.5 20 Parameter 54. Exclusive-OR. Plus Ten Other Logic Operations • Full Lookahead for High-Speed Arithmetic Operation on Long Words 4-BIT ARITHMETIC LOGIC UNIT FAST™ SCHOTTKY TTL CONNECTION DIAGRAM VCC A1 24 23 B1 22 A2 21 B2 20 A3 19 B3 18 G Cn+4 17 16 P 15 A = B F3 14 13 24 1 N SUFFIX PLASTIC CASE 724-03 ORDERING INFORMATION 1 B0 2 A0 3 S3 4 S2 5 S1 6 S0 7 Cn 8 M 9 F0 10 F1 11 12 F2 GND MC54/74FXXXN Plastic GUARANTEED OPERATING RANGES Symbol VCC TA IOH VOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current — High Output Voltage — High A = B output Output Current — Low 54.0 25 Max 5. Double. AND. OR.

MC54/74F181 LOGIC SYMBOLS ACTIVE-HIGH OPERANDS 2 1 23 22 21 20 19 18 A0 B0 A1 B1 A2 B2 A3 B3 Cn Cn + 4 M A=B S0 S1 G S2 S3 P F0 9 F1 10 F2 11 F3 13 VCC = PIN 24 GND = PIN 12 ACTIVE-LOW OPERANDS 2 1 23 22 21 20 19 18 A0 B0 A1 B1 A2 B2 A3 B3 Cn Cn + 4 M A=B S0 S1 G S2 S3 P F0 9 F1 10 F2 11 F3 13 7 8 6 5 4 3 16 14 17 15 7 8 6 5 4 3 16 14 17 15 LOGIC DIAGRAM Cn M A0 B0 A1 B1 A2 B2 A3 B3 S0 S1 S2 S3 F0 F1 A=B F2 F3 P Cn + 4 G FAST AND LS TTL DATA 4-93 .

0 V VCC = MIN VCC = MIN. When the Mode Control input (M) is HIGH. Thus. while G indicates that F is 16 or more.8 2. When speed requirements are not stringent. An incoming carry adds a one to each operation. the carries are enabled and the device performs arithmetic operations on the two 4-bit words.5 20 V V µA µA mA mA VIN = 0 5 V 0. use the appropriate value specified under guaranteed operating ranges. Not more than one output should be shorted at a time.0 mA IOL = 20 mA VIN = 2. FUNCTIONAL DESCRIPTION The F181 is a 4-bit high-speed parallel Arithmetic Logic Unit (ALU). while G indicates that F is less than zero.4 Min 2. The Function Table lists the arithmetic operations that are performed without a carry in. nor for more than 1 second.5 VCC = MAX 2. When the Mode Control input is LOW. The A = B signal can be used with the Cn + 4 signal to indicate A > B and A < B. For high-speed operation the device is used in conjunction with a carry lookahead circuit.8 –1. A = B VCC = 4.6 –1. The Function Table lists these operations. 2. select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn + 4 output.2 250 Typ Max Unit V V V µA V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA VOH = 5. P and G are not affected by carry in. The A = B output is open collector and can be wired-AND with other A = B outputs to give a comparison for more than four bits.5 V VCC = 4. One carry lookahead package is required for each group of four F181 devices. As indicated.4 0. P indicates that F is zero or less. all internal carries are inhibited and the device performs logic operations on the individual bits as listed. a carry out means borrow. FAST AND LS TTL DATA 4-94 . For conditions such as MIN or MAX.35 0. For either case the table lists the operations that are performed to the operands labeled inside the logic symbol.4 – 3. 74 Output HIGH Voltage 74 Output LOW Voltage Input HIGH Current 100 M Input A and B Inputs IIL Input LOW Current S0 – 3 Inputs Cn Input IOS ICC Output Short Circuit Current (Note 2) Power Supply Current – 60 43 – 2. In the Subtract mode. it can perform all the 16 possible logic operations or 16 different arithmetic operations on active-HIGH or active-LOW operands.5 V IOH = –1.75 V VCC = MIN VCC = MAX NOTES: 1. Because subtraction is actually performed by complementary addition (1s complement).5 3.0 0. Controlled by the four Function Select inputs (S0 – S3) and the Mode Control input (M). this device can be used with either active-LOW inputs producing active-LOW outputs or with active-HIGH inputs producing active-HIGH outputs. In the Add mode. it can be used in a simple Ripple Carry mode by connecting the Carry output (Cn + 4) signal to the Carry input (Cn) of the next unit.0 mA IOH = –1.7 3. The A = B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the Subtract mode. or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). Carry lookahead can be provided at various levels and offers high-speed capability over extremely long word lengths.7 V VIN = 7. P indicates that F is 15 or more.0 –150 65 mA mA mA mA VOUT = 0 V VCC = MAX VCC = MAX – 0.MC54/74F181 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOH VOL IIH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output Current — HIGH 54. thus a carry is generated when there is no underflow and no carry is generated when there is underflow.

0 4.0 3.5 10.0 3.0 11 7.0 3.5 10 15 14 16 15 10.5 4.5 9.5 3.5 74F TA = 0 to +70°C VCC = 5.5 10 12 12 9.0 3.0 4.5 8.5 10.0 5.5 10 10 12 12 11.5 4.5 3.5 9.5 8.5 12 14 14 11 12 31 14.5 9.0 3.0 5.0 3.0 3.0 3.5 9.0 13 12 14 13 8.0 3.0 4.0 3.5 7.5 11 11 13 13 12.0 V ±10% CL = 50 pF Min 3.0 3.5 7.0 V ±10% CL = 50 pF Min 3.0 5.0 3.0 10 11 11 10.0 5.5 9.0 4.0 9.0 4.0 11 7.0 3.0 Max 10.0 3.0 3.5 4.0 5.0 3.0 3.5 10.0 3.0 3.MC54/74F181 AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 3.0 5.5 7.0 3.0 11 7.5 11 13 13 10 11 29 13.0 3.0 3.5 8.5 4.0 5.0 4.0 3.5 4.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Path Cn to Cn + 4 A or B to Cn + 4 A or B to Cn + 4 Cn to F A or B to G A or B to G A or B to P A or B to P Ai or Bi to Fi Ai or Bi to Fi Any A or B to Any F Any A or B to Any F A or B to F A or B to A = B FAST AND LS TTL DATA 4-95 .0 4.5 54F TA = –55 to +125°C VCC = 5.0 3.0 3.0 3.5 8.5 9.0 Sum Dif Any Sum Dif Sum Dif Sum Dif Sum Dif Logic Dif 5.0 3.5 8.0 5.0 3.5 4.5 3.5 8.0 10 27 12.0 3.0 8.5 8.5 9.0 3.0 5.0 3.0 4.0 3.0 3.0 V CL = 50 pF Mode Min 3.0 3.5 11.0 Max 8.5 8.0 3.5 9.5 10.0 4.0 3.0 3.0 5.5 9.0 Max 9.0 14 13 15 14 9.0 7.0 4.0 4.0 3.5 9.0 4.0 4.0 4.5 7.0 5.0 4.

**Arithmetic operations expressed in 2s complement notation. H = HIGH Voltage Level L = LOW Voltage Level FAST AND LS TTL DATA 4-96 .MC54/74F181 FUNCTION TABLE Mode Select Inputs S3 L L L L L L L L H H H H H H H H S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H Active-LOW Operands & Fn Outputs Logic (M = H) A AB A+B Logic 1 A+B B A⊕B A+B AB A⊕B B A+B Logic 0 AB AB A Arithmetic** (M = L) (Cn = L) A minus 1 AB minus 1 AB minus 1 minus 1 A plus (A + B) AB plus (A + B) A minus B minus 1 A+B A plus (A + B) A plus B AB plus (A + B) A+B A plus A* AB plus A AB minus A A Active-HIGH Operands & Fn Outputs Logic (M = H) A A+B AB Logic 0 AB B A⊕B AB A+B A⊕B B AB Logic 1 A+B A+B A Arithmetic** (M = L) (Cn = H) A A+B A+B minus 1 A plus AB (A + B) plus AB A minus B minus 1 AB minus 1 A plus AB A plus B (A + B) plus AB AB minus 1 A plus A* (A + B) plus A (A + B) plus A A minus 1 *Each bit is shifted to the next more significant position.

• Provides Lookahead Carries Across a Group of Four ALUs • Multi-level Lookahead High-speed Arithmetic Operation Over Long Word Lengths CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 P2 15 G2 14 Cn 13 Cn + x Cn + y 12 11 G 10 Cn + z 9 16 1 CARRY LOOKAHEAD GENERATOR FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 1 G1 2 P1 3 G0 4 P0 5 G3 6 P3 7 P 8 GND 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 LOGIC DIAGRAM ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC Cn G0 P0 G1 P1 G2 P2 G3 P3 LOGIC SYMBOL 13 Cn P0 G0 12 Cn + x Cn + y Cn + z G P 11 9 Cn + x Cn + y Cn + z P1 G1 P2 G2 P3 G3 G 10 4 3 2 1 15 14 6 5 VCC = PIN 16 GND = PIN 8 P 7 FAST AND LS TTL DATA 4-97 .MC54/74F182 CARRY LOOKAHEAD GENERATOR The MC54/74F182 is a high-speed carry lookahead generator. It is generally used with the F181. F381 or 29F01 4-bit arithmetic logic unit to provide highspeed lookahead over word lengths of more than four bits.

0 25 25 Max 5.0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-98 .MC54/74F182 FUNCTION TABLE Inputs Cn X L X H X X L X X H X X X L X X X H G0 H H L X X H H X L X X X H H X X L X X X X H X X X L H X X X L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Outputs G2 P2 G3 P3 Cn+x L L H H Cn+y Cn+z G P P0 H X X L X H X X X L X X H X X X X L G1 P1 H H H L X X X H H H X L X X X X H H X X L X H X X X L L X H X X X X L L X X H X X X X L X H X X L H H H H L X X X X H H H X L X X H X X X X L L L X H X X X X L L X X H X L H H H H L X X X H X X X X L L L X X X H L L L L H H H L L L L H H H H H H H H L L L L H H H H L GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.74 54 74 IOH IOL Output Current — High Output Current — Low 54.5 –55 0 Typ 5.5 125 70 –1. 74 54. 74 Min 4.

2 54F TA = –55°C to +125°C VCC = 5.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Cn to Cn + x.5 V All Other Inputs = GND VCC = MAX VCC = MAX VCC = MAX mA VIN = 0.5 ns 10 9. Cn + y.5 1.6 –4. P1 Inputs G0.0 6.5 10.9 Max 8. G1.5 9.7 6.6 6.75 V VCC = MIN VCC = MAX VCC = MAX NOTES: 1. or G2 to Cn + x. Cn + z Propagation Delay G0.5 V VCC = MAX Min 2. Cn + z Propagation Delay P0. nor for more than 1 second.5 V All Other Inputs = GND G0. P0.4 –9.5 2.0 2.0 V ± 10% CL = 50 pF Min 3.7 V VIN = 7.4 0.0 3. G2 Inputs G1 Input IOS ICCH ICCL Output Short Circuit Current (Note 2) Power Supply Current (All Outputs HIGH) Power Supply Current (All Outputs LOW) –60 18.0 mA IOH = –1.8 –8.0 mA IOL = 20 mA VIN = 2.5 Max 10.5 3.0 0.5 Max 9.6 –150 28 36 mA mA mA VOUT = 0 V P3.4 –3. use the appropriate value specified under guaranteed operating ranges.0 ns ns Unit FAST AND LS TTL DATA 4-99 .5 6. or P2 to Cn + x. No more than one output should be shorted at a time.0 8. G3 = 4.5 2.5 1. Cn + z Min 3.5 11 10. For conditions shown as MIN or MAX.5 1. 74 74 Output LOW Voltage Input HIGH Current 2.5 6. Cn + y.0 3.0 V VCC = MIN VCC = 4.5 5.0 2.5 1.5 20 100 Cn Input P3 Input IIL Input LOW Current P2 Input G3.35 0. P1. 2.0 8.7 3.7 6. G1.8 –1. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 9.5 2.5 1. G2 = 4.5 2.0 5.5 Typ 6.2 Typ Max Unit V V V V V V µA µA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1.0 2.5 1.8 6.0 3.2 3.4 23.MC54/74F182 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.50 V VCC = 4. Cn + y.4 3.5 74F TA = 0°C to +70°C VCC = 5.2 –2.0V ± 10% CL = 50 pF Min 3.5 –1.

5 2.5 9. 32-Bit ALU with Ripple Carry Between 16-Bit Lookahead ALUs FAST AND LS TTL DATA 4-100 .0 2.5 12. Figure 1.5 Typ 7.5 2. There are several possible arrangements for the carry interconnects.5 74F TA = 0°C to +70°C VCC = 5. Cn + y. The critical speed path follows the circled numbers. Carries are rippled between lookahead blocks.5 11 7.0 1. or P3 to G Propagation Delay Gn to G Propagation Delay Pn to P Min 2. The logic equations provided at the output are: Cn + x = G0 + P0Cn Cn + y = G1 + P1G0 + P1P0Cn Cn + z = G2 + P2G1 + P2P1G0 + P2P1P0Cn G = G3 + P3G2 + P3P2G1 + P3P2P1G0 P = P3P2P1P0 Also.0 2.7 5.5 5.5 54F TA = –55°C to +125°C VCC = 5.3 5.5 2.0 10. The connections (Figure 1) to and from the ALU to the carry lookahead generator are identical in both cases.7 4.0 2.0 11. B 1 ALU** G P C16 Cn Cn + 4 ALU** G P Cn ALU** G P 5 Cn Cn + 4 ALU** G P 2 Cn ALU** G P Cn ALU** G P Cn Cn + 4 ALU** Cn Cn + 4 ALU** F 6 COUT (C32) CIN P0 G0 P1 G1 P2G2 P3 G3 Cn F182 G Cn + x Cn + y Cn + zP 3 P0 G0 P1 G1 P2 G2 P3 G3 Cn F182 G Cn + x Cn + y Cn + z P 4 ** ALUs may be either F181.0V ± 10% CL = 50 pF Min 2.5 8. but all achieve about the same speed.5 9. Cn A.0 1.0 1. the F182 can be used with binary ALUs in an activeLOW or active-HIGH input operand mode.9 6. P2.5 2.5 ns 6.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay P1.5 ns 8.0 2.5 7.0 2.5 2. A 28-bit ALU is formed by dropping the last F181 or F381.5 Max 12. or 2901A.5 Max 11 ns 9.MC54/74F182 AC CHARACTERISTICS (Continued) 54/74F TA = +25°C VCC = +5.5 Unit FUNCTIONAL DESCRIPTION The F182 carry lookahead generator accepts up to four pairs of active-LOW Carry Propagate (P0-P3) and carry Generate (G0-G3) signals and an active-HIGH Carry input (Cn) and provides anticipated active-HIGH carries (Cn + x.0 V ± 10% CL = 50 pF Min 2.0 8. F381.5 2. Cn + z) across four groups of binary adders. The F182 also has active-LOW Carry Propagate (P) and Carry Generate (G) outputs which may be used for further levels of lookahead.0 2.1 Max 10 8.5 7.

parallel load and hold operations. with respect to the clock rising edge. It may be used in serial-serial. pn. CONNECTION DIAGRAM VCC 16 Q0 15 Q1 14 Q2 13 Q3 12 CP 11 S1 10 S0 9 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC74FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC 1 MR 2 DSR 3 P0 4 P1 5 P2 6 P3 8 7 DSL GND FUNCTION TABLE Operating p g Mode Reset Hold Shift Left Shift Right Parallel Load Inputs MR L H H H H H H S1 X I h h I I h S0 X I I I h h h DSR X X X X I h X DSL X X I h X X X Pn X X X X X X pn Q0 L q0 q1 q1 L H p0 Outputs Q1 L q1 q2 q2 q0 q0 p1 Q2 L q2 q3 q3 q1 q1 p2 Q3 L q3 L H q2 q2 p3 1 15 14 13 12 LOGIC SYMBOL 11 10 9 CP S1 S0 DSR MR P0 Q0 P1 Q1 P2 Q2 P3 DSL Q3 2 3 4 5 6 7 I = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition. provided only that the recommended setup and hold times. Parallel data (P0 – P3) and Serial data (DSR. with added features of shift left without external connections and hold (do nothing) modes of operation. shift left. parallel-serial. and parallel-parallel data register transfers. qn = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. Signals applied to the Select (S0.MC74F194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER The MC74F194 is a high-speed 4-bit bidirectional universal shift register. shift left. S1) inputs determine the type of operation. DSL) inputs can change when the clock is in either state. shift right. serial-parallel. A LOW signal on Master Reset (MR) overrides all other inputs and forces the outputs LOW. sequential building block. 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER FAST™ SCHOTTKY TTL • • • • Typical Shift Frequency of 150 MHz Asynchronous Master Reset Hold (Do Nothing) Mode Fully Synchronous Serial or Parallel Data Transfers 16 1 FUNCTIONAL DESCRIPTION The F194 contains four edge-triggered D flip-flops and the necessary interstage logic to synchronously perform shift right. Signals on the Select. The F194 is similar in operation to the S195 universal shift register. as shown in the Function Table. h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-101 . it is useful in a wide variety of applications. are observed. As a high-speed multifunctional.

6 –150 2.5 0 Typ 5.0 0.4 Min 2.7 V VIN = 7.5 20 V V µA µA mA mA 2.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1.5 V VCC = 4. DSR.0 25 Max 5.5 70 – 1.5 V VOUT = 0 V Sn.0 20 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH IIL IOS Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 74 Output HIGH Voltage 74 Output LOW Voltage Input HIGH Current 100 Input LOW Current Output Short Circuit Current (Note 2) – 60 – 0. use the appropriate value specified under guaranteed operating ranges. nor for more than 1 second.7 3. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4. DSL = 4.MC74F194 LOGIC DIAGRAM P0 S1 S0 P1 P2 P3 DSR DSR S Q0 S Q1 S Q2 S Q3 CP R CLEAR CP MR Q0 CP R CLEAR CP R CLEAR CP R CLEAR Q1 Q2 Q3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.4 0.0 V VIN = 0.8 – 1.5 V Pn = Gnd. For conditions such as MIN or MAX. FAST AND LS TTL DATA 4-102 . 2. CP = VCC = MIN VCC = 4.0 mA IOH = –1.0 mA IOL = 20 mA VIN = 2.35 0. MR.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX ICC Power Supply Current 33 46 mA VCC = MAX NOTES: 1. Not more than one output should be shorted at a time.5 3.

0 7.0 Max 74F TA = 0 to +70°C VCC = 5.0 8. HIGH or LOW Pn or DSR or DSL to CP Set up Time.0 V Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) trec Parameter Set up Time. HIGH or LOW Sn to CP CP Pulse Width HIGH MR Pulse Width LOW Recovery Time MR to CP Min 4.0 ns 1.0 1.0 ns ns ns Max Unit FAST AND LS TTL DATA 4-103 .5 4.0 4.5 12 Max 74F TA = 0 to +70°C VCC = 5.0 V ±10% Min 4.0 8.5 8.0 14 Max Unit MHz ns ns AC OPERATING REQUIREMENTS 74F TA = +25°C VCC = +5.5 7.0 0 0 5. HIGH or LOW Sn to CP Hold Time.MC74F194 AC CHARACTERISTICS 74F TA = +25°C VCC = +5.5 3.0 7. HIGH or LOW Pn or DSR or DSL to CP Hold Time.0 V CL = 50 pF Symbol fmax tPLH tPHL tPHL Parameter Maximum Shift Frequency Propagation Delay CP to Qn Propagation Delay MR to Qn Min 105 3.0 4.0 0 0 8.0 8.0 V ±10% CL = 50 pF Min 90 3.0 9.0 5.0 ns 0 0 5.0 3.5 4.5 5.0 8.

Dn. and is shifted 1 bit in the direction Q0-Q1-Q2-Q3 following each LOW-to-HIGH clock transition.MC74F195 4-BIT PARALLEL ACCESS SHIFT REGISTER The functional characteristics of the MC74F195 4-Bit Parallel Access Shift Register are indicated in the Logic Diagram and Function Table. It performs serial. After the LOW-to-HIGH clock transition. and by tying the two pins together the simple D-type input is made for general applications. • Shift Right and Parallel Load Capability • J-K (D-Type) Inputs to First Stage • Complement Output from Last Stage • Asynchronous Master Reset 4-BIT PARALLEL ACCESS SHIFT REGISTER FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION CONNECTION DIAGRAM DIP VCC 16 Q0 15 Q1 14 Q2 13 Q3 12 Q3 11 CP 10 PE 9 MC74FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 9 2 1 MR 2 J 3 K 4 D0 5 D1 6 D2 7 D3 8 GND 10 3 J 4 5 6 7 PE D0 D1 D2 D3 11 Q3 CP K MR Q0 Q1 Q2 Q3 1 15 14 13 12 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-104 . data on the parallel inputs (D0-D3) is transferred to the respective Q0-Q3 outputs. All parallel and serial data transfers are synchronous. and storage applications. The MC74F195 utilizes edge-triggering. The J and K inputs provide the flexibility of the JK type input is made for special applications. counting. serial-to-parallel. independent of any other input condition. or parallel-to-serial data transfers at very high speeds. K. The device appears as four common clocked D flip-flops when the PE input is LOW. which are controlled by the state of the Parallel Enable (PE) input. The MC74F195 operates in two primary modes. The device is useful in a wide variety of shifting. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW. there is no restriction on the activity of the J. and PE inputs for logic operation. Shift left operation (Q3-Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input LOW. occurring after each LOW-to-HIGH clock transition. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is HIGH. therefore. other than the setup and hold time requirements. parallel. shift right (Q0-Q1) and parallel load.

MC74F195 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current  High Output Current  Low Parameter 74 74 74 74 Min 4. Toggle First Stage Shift.0 20 Unit V °C mA mA LOGIC DIAGRAM J PE K D0 D1 D2 D3 CP MR R RD Q R RD R RD R RD Q CP S Q Q0 CP S Q Q1 CP S Q Q2 CP S Q Q3 Q3 FUNCTION TABLE Inputs Operating Modes Asynchronous Reset Shift. Retain First Stage Parallel Load MR L H H H H H CP X ↑ ↑ ↑ ↑ ↑ PE X h h h h l J X h l h l X K X h l l h X Dn X X X X X dn Q0 L H L q0 q0 d0 Q1 L q0 q0 q0 q0 d1 Outputs Q2 L q1 q1 q1 q1 d2 Q3 L q2 q2 q2 q2 d3 Q3 H q2 q2 q2 q2 d3 H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care dn (qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition.0 25 Max 5.5 0 Typ 5.5 70 –1. ↑ = LOW-to-HIGH clock transition FAST AND LS TTL DATA 4-105 . Reset First Stage Shift. Set First Stage Shift.

5 3.6 –150 38 mA mA mA Min 2.5 Max Min 90 2. use the appropriate value specified under guaranteed operating ranges. nor for more than 1 second.5 V VCC = 4.0 3.MC74F195 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2. 2.5 2.8 –1. MR to Q Parameter Min 105 2.5 V VCC = MAX NOTES: 1. AC CHARACTERISTICS 54/74F TA = + 25°C VCC = + 5.7 V VIN = 7.5 2.7 0.0 8.5 2.75 V VCC = 4. MR to Q Propagation Delay.0 10 10.5 3.0 V CL = 50 pF Symbol fmax tPLH tPHL tPHL tPLH Propagation Delay CP to Q/Q Propagation Delay. For conditions shown as MIN or MAX.0 0.0 11 11 ns ns 74F TA = 0°C to + 70°C VCC = 5.0 3.0 8.0 V VCC = MAX VOUT = 0 V VCC = MAX VCC = MAX Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1.2 Typ Max Unit V V V V V V µA IOL = 20 mA VIN = 2. Not more than one output should be shorted at a time.0 V ± 10% CL = 50 pF Max Unit MHz ns FAST AND LS TTL DATA 4-106 .0 9.0 mA VCC = MIN VCC = 4.0 7.5 20 100 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current –60 –0.

HIGH or LOW PE to CP Hold Time.0 V ± 10% CL = 50 pF Max Unit ns FAST AND LS TTL DATA 4-107 .0 1. K.0 5.0 V CL = 50 pF Symbol ts (H) ts (L) th (H) th (L) ts (H) ts (L) th (H) th (L) tw (H) tw (L) trec CP Pulse Width.0 9.0 1. LOW Recovery Time.0 8.0 Max Min 4.5 5. K. HIGH or LOW PE to CP Setup Time.0 0 0 5.0 4. HIGH or LOW J.0 ns ns ns ns ns ns 74F TA = 0°C to + 70°C VCC = 5. D to CP Parameter Setup Time.0 7. MR to CP Hold Time. D to CP Min 4.0 0 0 5.0 4.0 9.0 8.MC74F195 AC OPERATING REQUIREMENTS 74F TA = + 25°C VCC = + 5.0 0 0 8. HIGH or LOW J. HIGH MR Pulse Width.

and bus-oriented transmitters/receivers which provide improved PC board density. F241 and F244 are octal buffers and line drivers designed to be employed as memory address drivers. • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Outputs Sink 64 mA • 15 mA Source Current • Input Clamp Diodes Limit High-Speed Termination Effects • ESD > 4000 Volts MC54/74F240 MC54/74F241 MC54/74F244 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL CONNECTION DIAGRAMS J SUFFIX CERAMIC CASE 732-03 1 MC54/74F240 VCC OEb Ya0 20 19 18 Ib0 17 Ya1 16 Ib1 15 Ya2 14 Ib2 13 Ya3 12 Ib3 11 20 N SUFFIX PLASTIC CASE 738-03 20 1 1 2 3 Yb0 4 Ia1 5 Yb1 6 Ia2 7 Yb2 8 Ia3 9 10 DW SUFFIX SOIC CASE 751D-03 OEa Ia0 Yb3 GND 20 1 VCC OEb Ya0 20 19 18 MC54/74F241 Ib0 Ya1 Ib1 Ya2 17 16 15 14 Ib2 13 Ya3 Ib3 12 11 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 1 OEa 2 Ia0 3 Yb0 4 Ia1 5 Yb1 6 Ia2 7 Yb2 8 Ia3 9 10 Yb3 GND MC54/74F244 VCC OEb Ya0 Ib0 Ya1 Ib1 Ya2 20 19 18 17 16 15 14 Ib2 13 Ya3 12 Ib3 11 1 OEa 2 Ia0 3 Yb0 4 Ia1 5 Yb1 6 Ia2 7 Yb2 8 Ia3 9 10 Yb3 GND FAST AND LS TTL DATA 4-108 .OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS The F240. clock drivers.

X = Don’t Care. L = LOW Voltage Level. 74 54 74 IOH IOL Output Current — High 54 74 Output Current — Low 54 74 Min 4.MC54/74F240 • MC54/74F241 • MC54/74F244 FUNCTION TABLE MC54/74F240 Inputs OEa L L H Ia L H X OEb L L H Ib L H X Outputs Ya H L Z Yb H L Z FUNCTION TABLE MC54/74F241 Inputs OEa L L H Ia L H X OEb H H L Ib L H X Outputs Ya L H Z Yb L H Z FUNCTION TABLE MC54/74F244 Inputs OEa Ia L L L H H X OEb Ib L L L H H X Outputs Ya L H Z Yb L H Z H = HIGH Voltage Level.5 125 70 –12 –15 48 64 mA mA Unit V °C FAST AND LS TTL DATA 4-109 .0 25 25 Max 5.5 –55 0 Typ 5. Z = High Impedance GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.

74 74 54 74 VOL Output LOW Voltage 54 74 IOZH IOZL IIH Output Off Current HIGH Output Off Current LOW Input HIGH Current 2.2 Typ Max Unit V V V V V V V V V µA µA µA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –3. nor for more than 1 second.0 0.4 2.4 Min 2.55 50 –50 20 100 IIL Input LOW Current Data Inputs F241. For conditions shown as MIN or MAX. Not more than one output should be shorted at a time.4 3. use the appropriate value specified under recommended operating conditions for the applicable device type.0 –225 –275 35 60 75 90 75 90 mA VCC = MAX mA mA VOUT = GND VCC = MAX mA 3.7 V VIN = 7.8 –1.6 –1. F244 ICCZ Power Supply Current OFF F240 F241. F244 –100 –100 –1.75 V VCC = 4.MC54/74F240 • MC54/74F241 • MC54/74F244 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.0 V VIN = 0.0 mA IOH = –12 mA IOH = –15 mA IOL = 48 mA IOL = 64 mA VOUT = 2.7 2.0 0.50 V VCC = 4.7 V VOUT = 0. 2.50 V VCC = 4.0 2. F244 ICCL Power Supply Current LOW F240 F241.5 V VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MIN VCC = 4. F244 Other IOS Output Short Circuit Current (Note 2) ICCH Power Supply Current HIGH 74 54 F240 F241.5 V VIN = 2.0 mA IOH = –3. FAST AND LS TTL DATA 4-110 .55 0.50 V VCC = MIN NOTES: 1.

5 Max 5.0 2.5 Typ 5.5 1.5 2.0 54F TA = -55°C to +125°C VCC = 5.5 4.0 2.5 1.0 8.5 2.0 4.0 74F TA = 0°C to +70°C VCC = 5.5 ns ns Unit ns AC CHARACTERISTICS – MC54/74F241 54/74F TA = +25°C VCC = +5.0 Max 6.5 7.0 Typ 4.0 7.0 7.5 7.0 2.0 V ± 10% CL = 50 pF Min 2. Data to Output Min 2.5 74F TA = 0°C to +70°C VCC = 5.5 Max 8.5 2.MC54/74F240 • MC54/74F241 • MC54/74F244 AC CHARACTERISTICS – MC54/74F240 54/74F TA = +25°C VCC = +5.0 4.0 2.0 V ± 10% CL = 50 pF Min 2.5 54F TA = -55°C to +125°C VCC = 5.0 V ± 10% CL = 50 pF Min 2.0 2.0 Max 6.0 2. Data to Output Min 2.0 2.0 2.0 7.0 Max 7.0 7.0 6.0 6.0 4.0 4.0 Max 6.3 5.5 2.0 4.7 8.5 2.5 3.0 2.0 2.0 2.0 1.2 5.5 2.3 8.5 2.4 4.0 V ± 10% CL = 50 pF Min 2.0 6.7 7.0 2.0 V ± 10% CL = 50 pF Min 2.0 10.5 2.5 ns ns Unit ns AC CHARACTERISTICS – MC54/74F244 54/74F TA = +25°C VCC = +5.2 6.0 5.0 4.0 8.0 2.2 5.0 Max 9.7 7.7 5.0 2.0 4.0 2.5 2.7 8.0 2.0 6.0 1.5 74F TA = 0°C to +70°C VCC = 5.0 2.0 2.1 3.0 6.5 6.0 2.7 10 6.0 Typ 4.0 54F TA = -55°C to +125°C VCC = 5.5 2.5 4.5 6.0 6.0 V CL = 50 pF Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Output Enable Time Parameter Propagation Delay.0 4.5 7. Data to Output Min 2.3 9.0 2.0 6.0 5.0 V ± 10% CL = 50 pF Min 2.9 4.5 2.2 6.0 2.0 7.0 2.0 12.5 13.5 2.0 7.5 6.0 2.0 V CL = 50 pF Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Output Enable Time Parameter Propagation Delay.5 1.2 5.3 5.2 9.0 ns ns Unit ns FAST AND LS TTL DATA 4-111 .4 4.2 5.5 12.0 V CL = 50 pF Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Output Enable Time Parameter Propagation Delay.0 2.5 Max 5.7 5.0 Max 6.5 6.5 2.5 7.

5 –55 0 Typ 5.74 54 74 IOH IOL Output Current — High 54 74 Output Current — Low 54 74 Min 4.0 25 25 Max 5. • 2-Way Asynchronous Data Bus Communication • Input Clamp Diodes Limit High-Speed Termination Effects • ESD > 4000 Volts MC54/74F242 MC54/74F243 QUAD BUS TRANSCEIVERS WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL MC54/74F242 (TOP VIEW) VCC 14 OE2 13 NC 12 1B 11 2B 10 3B 9 4B 8 14 1 J SUFFIX CERAMIC CASE 632-08 1 OE1 2 NC 3 1A 4 2A 5 3A 6 4A 7 GND 14 1 N SUFFIX PLASTIC CASE 646-06 MC54/74F243 (TOP VIEW) VCC 14 OE2 13 NC 12 1B 11 2B 10 3B 9 4B 8 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC 1 OE1 2 NC 3 1A 4 2A 5 3A 6 4A 7 GND GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.5 125 70 –12 –15 48 64 mA mA Unit V °C FAST AND LS TTL DATA 4-112 .QUAD BUS TRANCEIVERS WITH 3-STATE OUTPUTS The MC54/74F242 and MC54/74F243 are Quad Bus Transmitters/Receivers designed for 4-line asynchronous 2-way data communication between data buses.

7 0.0 -1.0 mA IOL = 48 mA IOL = 64 mA VOUT = 2.0 mA IOH = –3.5 V VOUT = 0 V VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MIN VCC = 4. 74 74 VOL Output LOW Voltage 54 74 IOZH Output Off Current HIGH 2.0 IOZL Output Off Current LOW Enable IIH Input HIGH Current Data Data Enable IIL Input LOW Current Enable Data IOS Output Short Circuit Current (Note 2) ICCH Power Supply Current HIGH ICCL Power Supply Current LOW ICCZ Power Supply Current OFF 74 54 F242 F243 F242 F243 F242 F243 –100 –100 –1.7 V VIN = 5. For conditions shown as MIN or MAX.50 V VCC = 4.8 –1. Z = HIGH Impedance DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH voltage Input LOW Voltage Input Clamp Diode Voltage 54 VOH Output HIGH Voltage 74 54.1 -1.2 Typ Max Unit V V V V V V V V V µA mA mA µA µA mA mA mA mA mA mA mA mA mA mA mA mA Outputs HIGH Outputs LOW Outputs OFF VCC = MAX VCC = MAX VCC = MAX Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –12 mA IOH = –15 mA IOH = –3. L = LOW Voltage Level .0 2.0 V VIN = 0. X = Don’t Care.0 0.75 V VCC = MIN NOTES: 1. 2. nor for more than 1 second. FAST AND LS TTL DATA 4-113 .7 V VIN = 2. Not more than one output should be shorted at a time.5 V VOUT = 0.0 2.50 V VCC = 4.MC54/74F242 • MC54/74F243 FUNCTION TABLE – MC54/74F242 Inputs OE1 L L H H D L H X X Output H L Z Z Inputs OE2 L L H H D X X L H Output Z Z H L FUNCTION TABLE – MC54/74F243 Inputs OE1 L L H H D L H X X Output L H Z Z Inputs OE2 L L H H D X X L H Output Z Z L H H = HIGH Voltage Level.5 V VIN = 0.55 0.50 V VCC = 4.55 70 1.5 V VIN = 7.4 2.0 0. use the appropriate value specified under recommended operating conditions for the applicable device type.5 V VIN = 2.6 20 70 1.7 V VOUT = 5.6 –225 –275 60 80 75 90 75 90 Min 2.

5 8.5 2.0 5.0 V CL = 50 pF Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Parameter Propagation Delay.7 5.5 Max 7.5 1.5 6.3 8.0 6.0 1.0 1.0 ns ns Unit ns AC CHARACTERISTICS – MC54/74F243 54/74F TA = +25°C VCC = +5.2 5.0 V ± 10% CL = 50 pF Min 2.7 7.0 2.5 8.5 2.0 1.0 V ±10% CL = 50 pF Min 2.5 7.0 6.0 2.5 Max 8.5 54F TA = -55°C to +125°C VCC = 5.5 7.5 1.5 ns ns Unit ns FAST AND LS TTL DATA 4-114 .0 2.7 4.0 1.5 2.2 5.7 10 6.0 6.5 Max 9.0 4.0 1.0 2.0 2.MC54/74F242 • MC54/74F243 AC CHARACTERISTICS – MC54/74F242 54/74F TA = +25°C VCC = +5.0 2.5 54F TA = -55°C to +125°C VCC = 5.0 Max 6. Data to Output Output Enable Time Min 2.0 2.5 74F TA = 0°C to 70°C VCC = 5.3 6.5 74F TA = 0°C to 70°C VCC = 5.5 Max 5.0 2.5 12.0 10.5 2.0 4.0 2.0 2.0 7.0 4.7 8.5 Max 6.5 12 6.0 V CL = 50 pF Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Parameter Propagation Delay.5 6.0 V ± 10% CL = 50 pF Min 2.0 5.5 12.7 9.0 1.5 2.5 1.2 6.0 V ±10% CL = 50 pF Min 2. Data to Output Output Enable Time Min 2.0 2.5 2.5 1.0 4.

5 125 70 –3. The Output Enable input. Receive (active LOW) enables data from B ports to A ports. 74 54 74 IOH IOL IOH IOL Output Current — High Output Current — Low An Outputs An Outputs Bn Outputs Bn Outputs 54. when HIGH. Current sinking capability is 24 mA at the A ports and 64 mA at the B ports. • Noninverting Buffers • Bidirectional Data Path • B Outputs Sink 64 mA • ESD > 4000 Volts CONNECTION DIAGRAM (TOP VIEW) VCC 20 OE 19 B0 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 OCTAL BIDIRECTIONAL TRANSCEIVER WITH 3-STATE INPUTS/OUTPUTS FAST™ SCHOTTKY TTL 20 1 J SUFFIX CERAMIC CASE 732-03 N SUFFIX PLASTIC CASE 738-03 20 1 20 1 T/R 2 A0 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 GND 1 DW SUFFIX SOIC CASE 751D-03 FUNCTION TABLE Inputs OE L L H T/R L H X Output Bus B Data to Bus A Bus A Data to Bus B High-Z State H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXDW Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. Transmit (active HIGH) enables data from A ports to B ports.3 MC54/74F245 OCTAL BIDIRECTIONAL TRANSCEIVER WITH 3-STATE INPUTS/OUTPUTS The MC54/74F245 contains eight noninverting bidirectional buffers with 3-state outputs and is intended for bus-oriented applications. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirectional transceiver.5 –55 0 Typ 5.0 24 20 –12 –15 48 64 mA mA mA mA Unit V °C Output Current — High Output Current — Low mA FAST AND LS TTL DATA 4-115 .0 25 25 Max 5. 74 74 54 54 74 54 74 Min 4. disables both A and B ports by placing them in a high-Z condition.

use the appropriate value specified under recommended operating conditions for the applicable device type.5 2.5 6.5 3. Bn Outputs 54 74 IOZH + IIH IOZL + IIL Output Off Current HIGH Output Off Current LOW OE.0 3.5 Unit ns ns ns FAST AND LS TTL DATA 4-116 .0 6.0 8.5 2. 2.5 V VIN = 2.5 2.0 –0.4 2.0 10 8.5 2.5 8.0 mA IOH = –3. 74 74 54.0 0.8 –1.0 V VIN = 5. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 V ± 10% CL = 50 pF Min 2.5 V VCC = MAX VCC = MAX VCC = MAX VCC = MIN VCC = MIN VCC = MIN VCC = 4. T/R Inputs An.35 0. Outputs HIGH VCC = MAX.5 3. Bn Inputs T/R Input IIL IOS Input LOW Current Output Short Circuit Current (Note 2) ICCH ICCL ICCZ Power Supply Current HIGH Power Supply Current LOW Power Supply Current OFF OE Input An Outputs Bn Outputs –60 –100 2. Not more than one output should be shorted at a time.3 3.0 mA IOH = –3. For conditions shown as MIN or MAX.0 8.0 2.0 Max 7.5 3.4 2.50 V VCC = 4.0 V CL = 50 pF Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay An to Bn or Bn to An Output Enable Time Output Disable Time Min 2.0 3. Bn Outputs 74 54 74 VOL Output LOW Voltage.7 V VOUT = 0.0 7.5 0.35 0. T/R Inputs IIH Input HIGH Current OE.5 2.0 0.0 3.0 V ± 10% CL = 50 pF Min 2.5 0.3 3.0 8.5 2.5 2.0 9.50 V VCC = 4.5 7. Outputs LOW VCC = MAX. Outputs OFF NOTES: 1.5 2.5 2.4 Min 2.0 7.2 –150 –225 90 120 110 3.2 Typ Max Unit V V V V V V V V V V V V V µA mA µA µA mA mA mA mA mA mA mA mA VIN = 0.5 54F TA = -55°C to +125°C VCC = 5.0 7.5 74F TA = 0°C to +70°C VCC = 5.7 2.0 Max 8.0 mA IOH = –3.55 70 –650 20 100 1. An Outputs 54.5 V VOUT = GND VOUT = GND VCC = MAX VCC = MAX VCC = MAX Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –3.7 2.0 6. 74 VOH Output HIGH Voltage.50 V VCC = MAX.75 V VCC = 4.MC54/74F245 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage.55 0.0 9.0 mA IOH = –12 mA IOH = –15 mA IOL = 20 mA IOL = 24 mA IOL = 48 mA IOL = 64 mA VOUT = 2.7 V VIN = 7.4 3. An Outputs 54 74 VOL Output LOW Voltage.8 –1.0 Max 6.75 V VCC = 4.

When it is activated. When the outputs of the 3-state devices are tied together. The Output Enable input (OE) is active LOW. MC54/74F251 8-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL • Multifunctional Capacity • On-Chip Select Logic Decoding • Inverting and Noninverting 3-State Outputs FUNCTIONAL DESCRIPTION This device is a logical implementation of a single-pole.8-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The MC54/74F251 is a high-speed 8-input digital multiplexer. in one package. Both assertion and negation outputs are provided. It provides. the logic function provided at the output is: Z = OE • (I0 • S0 • S1 • S2 + I1 • S0 • S1 • S2 + I2 • S0 • S1 • S2 + I3 • S0 • S1 • S2 + I4 • S0 • S1 • S2 + I5 • S0 • S1 • S2 + I6 • S0 • S1 • S2 + I7 • S0 • S1 • S2 + When the Output Enable is HIGH. Both assertion and negation outputs are provided. both outputs are in the high impedance (high Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. S2. S1. J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION CONNECTION DIAGRAM VCC 16 I4 15 I5 14 I6 13 I7 12 S0 11 S1 10 S2 9 MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 9 10 11 1 I3 2 I2 3 I1 4 I0 5 Z 6 Z 7 OE 8 GND 6 S2 S1 S0 OE I0 I1 I2 I3 I4 I5 I6 I7 VCC = PIN 16 GND = PIN 8 7 4 3 2 1 15 14 13 12 5 FAST AND LS TTL DATA 4-117 . It can be used as a universal function generator to generate any logic function of four variables. all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. the ability to select one bit of data from up to eight sources. The Output Enable signals should be designed to ensure there is no overlap in the active LOW portion of the enable voltages. 8-position switch with the switch position controlled by the state of three Select inputs. S0.

74 54. 74 Min 4. 74 54 74 IOH IOL Output Current — High Output Current — Low 54.5 125 70 –3.0 25 25 Max 5.MC54/74F251 FUNCTION TABLE Inputs OE H L L L L L L L L S2 X L L L L H H H H S1 X L L H H L L H H S0 X L H L H L H L H Z Z I0 I1 I2 I3 I4 I5 I6 I7 Outputs Z Z I0 I1 I2 I3 I4 I5 I6 I7 H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance LOGIC DIAGRAM I0 S2 S1 I1 I2 I3 I4 I5 I6 I7 S0 OE Z Z GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.0 24 mA mA Unit V °C FAST AND LS TTL DATA 4-118 .5 -55 0 Typ 5.

2 Typ Max Unit V V V V V V µA µA µA µA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –3. 2.5 10.5 54F TA = -55 °Cto +125°C VCC = 5.5 V OE = GND OE.0 4.0 5.0 mA IOL = 24 mA VOUT = 2.0 6.0 2.0 2.5 7.2 4.5 V VOUT = 0 V In. 74 74 VOL IOZH IOZL IIH Output LOW Voltage Output Off Current — HIGH Output Off Current — LOW Input HIGH Current 2.0 3.35 0.0 5.0 3.50 V VCC = 4.0 Max 9.0 6.5 7.5 8.5 9.0 2.5 9.0 3.0 2.5 10 9.8 –1.0 mA IOH = –3.0 3.5 4.5 10.0 3.0 3. For conditions shown as MIN or MAX. Not more than one output should be shorted at a time. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 3.7 4.5 4.5 8.0 2.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Sn to Zn Propagation Delay Sn to Zn Propagation Delay In to Z Propagation Delay In to Z Output Enable Time OE to Z Output Disable Time OE to Z Output Enable Time OE to Z Output Disable Time OE to Z Min 4.5 6.5 4.5 7.0 V ± 10% CL = 50 pF Min 4.0 3.0 7.5 V VIN = 2.0 3.0 Max 9.5 5.2 3.0 10 10 7.7 V VIN = 7.0 8.5 8.2 4.5 3.0 3.5 3.0 0.0 V ±10% CL = 50 pF Min 3.5 3.0 9.5 3.5 1.0 10.0 7.5 8.0 1.5 3.5 4.7 3.0 4.0 8.0 3.5 14 10.0 V VIN = 0.0 11.0 8.4 3.5 4.0 3.6 –150 22 24 Min 2.5 V VCC = MAX VCC = MAX VCC = MIN VCC = 4.0 8.0 5.0 3.4 0.0 3.4 2.5 13 9.0 2.7 V VOUT = 0. In = 4.5 3.0 1.0 4.0 2. nor for more than 1 second.5 6.5 16.0 74F TA = 0°C to 70°C VCC = 5.0 4. use the appropriate value specified under guaranteed operating ranges.5 3. Sn = 4.5 9.0 9.0 Max 8.5 3.0 3.5 50 –50 20 100 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current –60 15 16 –0.MC54/74F251 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 7.5 ns ns ns ns ns ns ns Unit ns FAST AND LS TTL DATA 4-119 .0 3.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX NOTES: 1.5 7.0 3.

5 –55 0 Typ 5. allowing the outputs to interface directly with bus-oriented systems.5 125 70 –3. 74 54 74 IOH IOL Output Current — High Output Current — Low 54. The outputs may be individually switched to a high-impedance state with a HIGH on the respective Output Enable (OE) inputs. 74 Min 4. MC54/74F253 DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 OEb 15 S0 14 I3b 13 I2b 12 I1b 11 I0b 10 Zb 9 16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 1 OEa 2 S1 3 I3a 4 I2a 5 I1a 6 I0a 7 Za 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Parameter Supply Voltage Operating Ambient Temperature Range 54.0 24 mA mA Unit V °C FAST AND LS TTL DATA 4-120 .0 25 25 Max 5.DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The MC54/74F253 is a Dual 4-Input Multiplexer with 3-State Outputs. It can select two bits of data from four sources using common select inputs. 74 54.

force the outputs to a high impedance (high Z) state. all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. They select two bits from four sources selected by common Select Inputs (S0. The F253 is the logic implementation of a 2-pole. Za = OEa • (I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 • S0 + 13a • S1 • S0) Zb = OEb • (I0b • S1 • S0 + I1b • S1 • S0 + I2b • S1 • S0 + I3b • S1 • S0) If the outputs of 3-state devices are tied together. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so that there is no overlap. where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown below: FUNCTION TABLE Select Inputs S0 X L L H H L L H H S1 X L L L L H H H H I0 X L H X X X X X X Data Inputs I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H Output Enable OE H L L L L L L L L Output Z Z L H L H L H L H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance (off) Address inputs S0 and S1 are common to both sections. OEb) inputs which. FAST AND LS TTL DATA 4-121 .MC54/74F253 LOGIC DIAGRAM OEb 15 13b 13 12b 12 11b 11 10b 10 S0 14 S1 2 13a 3 12a 4 11a 5 10a 6 OEa 1 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Zb 9 Za 7 FUNCTIONAL DESCRIPTION The F253 contains two identical 4-input Multiplexers with 3-State Outputs. when HIGH. S1). 4-position switch. The 4-input multiplexers have individual Output Enable (OEa.

4 2.0 3.5 9.0 2.0 2.7 0.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5. Sn. VCC = MAX In.5 2.5 V VOUT = 0 V OEn = GND IO = 4. Output HIGH ICC Total.50 V VCC = 4. Sn.0 6.0 V ± 10% CL = 50 pF Min 3. 74 74 VOL IOZH IOZL IIH Output LOW Voltage Output Off Current — HIGH Output Off Current — LOW Input HIGH Current 2.0 74F TA = 0°C to +70°C VCC = 5.7 V VIN = 7.0 7.0 8.6 –150 Min 2.5 V.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Parameter Propagation Delay Sn to Zn Propagation Delay In to Zn Output Enable Time Min 4.0 2.0 2.0 Max 13.2 Typ Max Unit V V V V V V µA µA µA µA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –3.5 V.5 3.5 3.0 8.0 V ± 10% CL = 50 pF Min 4.0 9.5 2.5 8.0 ns ns ns Unit ns FAST AND LS TTL DATA 4-122 .5 2.5 V VIN = 2.0 V VIN = 0.0 2.5 10 8.0 Max 11. I1 – I3 = GND In.0 3. Output LOW Total at HIGH-Z 16 23 23 mA –60 –0.0 2. OEn = GND VCC = MAX OEn = 4.0 mA IOH = –3.0 8.5 3.5 2.0 6.0 3. Sn = GND VCC = MAX VCC = MAX VCC = MIN VCC = 4.0 10 10 6.5 2.0 9.0 Max 15 11 9.0 6.0 5.0 7.0 3.MC54/74F253 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 3.5 2.0 7.0 2.5 50 –50 20 100 IIL IOS Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total.0 0.8 –1.0 54F TA = -55°C to +125°C VCC = 5.0 mA IOL = 24 mA VOUT = 2.7 V VOUT = 0.

q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared. In the addressable latch mode. In the clear mode. In the dual 1-of-4 decoding or demultiplexing mode (MR = E = LOW). the enable should be held HIGH (inactive) while the address lines are changing. data at the Data (D) inputs is written into the addressed latches. addressed outputs will follow the level of the D inputs with all other outputs LOW. • Combines Dual Demultiplexer and 8-Bit Latch • Serial-to-Parallel Capability • Output from Each Storage Bit Available • Random (Addressable) Data Entry • Easily Expandable • Common Clear Input • Useful as Dual 1-of-4 Active HIGH Decoder CONNECTION DIAGRAM VCC 16 MR 15 E 14 Db 13 Q3b 12 Q2b 11 Q1b 10 Q0b 9 D SUFFIX SOIC CASE 751B-03 DUAL 4-BIT ADDRESSABLE LATCH FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 1 A0 2 A1 3 Da 4 Q0a 5 Q1a 6 Q2a 8 7 Q3a GND ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Outputs Ceramic Plastic SOIC FUNCTION TABLE Inputs Operating Mode Master Reset Demulti lex Demultiplex (Active HIGH Decoder when D = H) Store (Do Nothing) Addressable Latch MR L L L L L H H H H H E H L L L L H L L L L D X d d d d X d d d d A0 X L H L H X L H L H A1 X L L H H X L L H H Q0 L Q=d L L L q0 Q=d q0 q0 q0 Q1 L L Q=d L L q1 q1 Q=d q1 q1 Q2 L L L Q=d L q2 q2 q2 Q=d q2 Q3 L L L L Q=d q3 q3 q3 q3 Q=d LOGIC SYMBOL 3 Da 1 2 A0 13 Db E 14 15 A1 MR Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b 4 5 6 7 9 10 11 12 H = HIGH Voltage Level Steady State L = LOW Voltage Level Steady State X = Immaterial d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition.MC54/74F256 DUAL 4-BIT ADDRESSABLE LATCH The MC54/74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Clear and Enable inputs (see Function Table). FAST AND LS TTL DATA 4-123 . To eliminate the possibility of entering erroneous data in the latches. In the memory mode. The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states. all latches remain in their previous states and are unaffected by the Data or Address inputs. all outputs are LOW and uneffected by the Address and Data inputs.

5 –55 Typ 5.MC54/74F256 LOGIC DIAGRAM E Da A0 A1 MR Db Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.0 25 Max 5. 74 54. 74 54 Min 4.5 125 Unit V °C mA mA FAST AND LS TTL DATA 4-124 .0 20 Parameter 54. 74 0 25 70 –1. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current — High Output Current — Low 54.

5 20 V V µA mA mA mA mA mA 2. Output LOW – 60 – 0. VOUT = 0 V VCC = MAX VCC = MAX ICC NOTES: 1. nor for more than 1 second.7 0. For conditions shown as MIN or MAX.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.1 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total. Not more than one output should be shorted at a time.0 0. VIN = 0. Total Output HIGH Total.6 –150 42 60 2.8 –1. use the appropriate value specified under recommended operating conditions for the applicable device type.0 mA IOL = 20 mA VCC = MIN VCC = 4. 2.5 Min 2. VIN = 7. VIN = 2.5 V VCC = MAX.75 V VCC = MIN VCC = MAX.MC54/74F256 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH IIL IOS Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54. IIN = –18 mA IOL = –1.7 V VCC = MAX.0 mA IOL = –1. 74 Output HIGH Voltage 74 Output LOW Voltage Input HIGH Current 0.0 V VCC = MAX. FAST AND LS TTL DATA 4-125 .

FAST AND LS TTL DATA 4-126 .0 5.MC54/74F256 AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.5 Max 12 7.5 11 11. HIGH or LOW Dn to E Hold Time.5 4.5 10 7.0 4.0 2.0 9.5 11.5 15. 2.5 2.0 2.0 3.5 3.0 4. HIGH or LOW Dn to E Setup Time.0 0 0 4.0 V ±10% CL = 50 pF Min 4.0 4.5 7.0 V Symbol ts( ) (H) ts(L) th( ) (H) th(L) ts( ) (H) ts(L) th( ) (H) th(L) tW tW Parameter Setup Time.5 Max 13 8.0 4.5 74F TA = 0 to 70°C VCC = 5.5 14.0 3.0 14 9.0 Max 74F TA = 0 to 70°C VCC = 5.0 Max ns ns ns ns ns ns Unit NOTES: 1.0 Max 54F TA = –55 to +125°C VCC = 5.0 3.0 5.5 10 10 Unit ns ns ns ns AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = +5.5 3.0 V ±10% Min 5.5 9.0 Max 10.0 V ± 5% Min 4.5 4. The Address to Enable setup time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is 1.0 4.0 4.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Propagation Delay g y E to Qn Propagation Delay g y Dn to Qn Propagation Delay g y An to Qn Propagation Delay MR to Qn Min 4.0 2. The Address to Enable hold time is the time after the LOW-to-HIGH Enable transition that the Address must be stable so that the correct latch is addressed 1.0 7.0 0 0 4.0 3.0 0 0 4.0 4.0 54F TA = –55 to +125°C VCC = 5.0 3.0 2.0 2.5 3.0 4. addressed and the other latches are not affected.0 4.0 V ± 5% CL = 50 pF Min 4.5 8.0 4.5 4.0 4. and the other latches are not affected.5 2.0 4.0 2.0 3.0 4.0 3. HIGH or LOW ( ) A to E(a) Hold Time HIGH or LOW A to E(b) E Pulse Width MR Pulse Width Min 4.

Four bits of data from two sources can be selected using a common Data Select input. • Multiplexer Expansion by Tying Outputs Together • Non-Inverting 3-State Outputs • Input Clamp Diodes Limit High-Speed Termination Effects • AC Enhanced Version of the F257 CONNECTION DIAGRAM VCC 16 OE 15 I0c 14 I1c 13 Zc 12 I0d 11 I1d 10 Zd 9 16 1 QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 16 N SUFFIX PLASTIC CASE 648-08 1 1 S 2 I0a 3 I1a 4 Za 5 I0b 6 I1b 7 Zb 8 GND LOGIC DIAGRAM OE I0a I1a I0b I1b I0c I1c I0d I1d S 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXAJ Ceramic MC74FXXXAN Plastic MC74FXXXAD SOIC LOGIC SYMBOL 1 Za Zb Zc Zd 4 Za Zb Zc Zd S OE I0a I1a I0b I1b I0c I1c I0d I1d 15 2 3 5 6 14 13 11 10 FUNCTION TABLE Output Enable OE H L L L L Select Input S X H H L L Data Inputs I0 X X X L H I1 X L H X X Outputs Z Z L H L H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance 7 12 9 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-127 . The four outputs present the selected data in true (non-inverted) form. allowing the outputs to interface directly with bus oriented systems. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input.MC74F257A QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The MC74F257 is a quad 2-input multiplexer with 3-state outputs.

75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX FUNCTIONAL DESCRIPTION The F257A is a quad 2-input multiplexer with 3-state outputs. When the Select input is LOW.5 V OE.0 –0.8 –1.0 0. Not more than one output should be shorted at a time.5 V VIN = 2.5 V VOUT = 0 V S. 2. I1x = 4. Designers should ensure the Output Enable signals to 3-state devices whose outputs are tied together are designed so there is no overlap. I0x. FAST AND LS TTL DATA 4-128 .MC74F257A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4. all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. I1x = 4.5 22 mA I1x = 4.7 V VIN = 7. S = GND ICCZ 15 23 S.7 V VOUT = 0.5 V NOTES: 1.6 –150 15 mA mA Min 2.3 0. I0x = GND OE.4 2. use the appropriate value specified under guaranteed operating ranges.0 V VIN = 0. the I0x inputs are selected and when Select is HIGH.3 3.0 24 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 74 74 VOL IOZH IOZL IIH Output LOW Voltage Output OFF Current — HIGH Output OFF Current — LOW Input HIGH Current 2. nor for more than 1 second.50 V VCC = 4. I0x = GND ICCL Power Supply Current 14. For conditions shown as MIN or MAX.35 0.0 mA IOH = –3.5 0 Typ 5. The device is the logic implementation of a 4-pole.5 V OE. 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input.5 70 –3. The data on the selected inputs appears at the outputs in true (non-inverted) form. the I1x inputs are selected. If the outputs are tied together. The logic equations for the outputs are shown below: Za = OE • (I1a • S + I0a • S) Zb = OE • (I1b • S + I0b • S) Zc = OE • (I1c • S + I0c • S) Zd = OE • (I1d • S + I0d • S) When the Output Enable input (OE) is HIGH.0 mA IOL = 24 mA VOUT = 2.2 Typ Max Unit V V V V V V µA µA µA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –3. the outputs are forced to a high impedance OFF state. VCC = MIN VCC = 4.0 25 Max 5. It selects four bits of data from two sources under control of a Common Data Select input.5 50 –50 20 100 IIL IOS ICCH Input LOW Current Output Short Circuit Current (Note 2) –60 9.7 3.

0 6.5 2.0 2.5 7.5 9.5 2.0 2.0 2.5 2.MC74F257A AC CHARACTERISTICS 74F TA = +25°C VCC = +5.5 2.0 74F TA = 0°C to 70°C VCC = 5.0 3.0 7.0 V ± 10% CL = 50 pF Min 1.0 3.0 Max 6.0 8.0 6.0 10.0 6.0 ns ns ns Unit ns FAST AND LS TTL DATA 4-129 .0 7.5 8.0 7.0 2.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay In to Zn Propagation Delay S to Zn Output Enable Time Parameter Min 1.5 7.0 2.0 2.5 5.0 Max 5.5 2.0 6.5 2.

The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input. The four outputs present the selected data in the complement (inverted) form. allowing the outputs to interface directly with bus-oriented systems. Four bits of data from two sources can be selected using a common Data Select input. • Multiplexer Expansion by Tying Outputs Together • Inverting 3-State Outputs • AC Enhanced Version of the F258 CONNECTION DIAGRAM (TOP VIEW) VCC 16 OE 15 I0c 14 I1c 13 Zc 12 I0d 11 I1d 10 Zd 9 16 MC74F258A QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 1 1 S 2 I0a 3 I1a 4 Za 5 I0b 6 I1b 7 Zb 8 GND 16 1 N SUFFIX PLASTIC CASE 648-08 LOGIC DIAGRAM OE I0a I1a I0b I1b I0C I1C I0D I1C S 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXAJ Ceramic MC74FXXXAN Plastic MC74FXXXAD SOIC LOGIC SYMBOL 1 S 4 Za Zb Zc Zd 7 12 Zb Zc Zd Za OE I0a I1a I0b I1b I0c I1c I0d I1d 15 2 3 5 6 14 13 11 10 9 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-130 .QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The MC74F258A is a quad 2-input multiplexer with 3-state outputs.

5 V NOTES: 1.7 2. 2.5 V OE.MC74F258A FUNCTION TABLE Output Enable OE H L L L L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance Select Input S X H H L L I0 X X X L H Data Inputs I1 X L H X X Output Z Z H L H L GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4.5 V µA µA µA µA mA mA IOL = 24 mA VOUT = 2. I1x = 4.7 V VIN = 7.5 0 Typ 5.3 17 S.0 24 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 74 74 VOL IOZH IOZL IIH Output LOW Voltage Output OFF Current — HIGH Output OFF Current — LOW Input HIGH Current 2. I0x.5 V VIN = 2. S = GND ICCZ 11.5 V OE.5 50 –50 20 100 IIL IOS ICCH Input LOW Current Output Short Circuit Current (Note 2) –60 6. I0x = GND ICCL Power Supply Current 15. I1x = 4.5 70 –3.4 0. Not more than one output should be shorted at a time.2 3.2 –0.75 V VCC = MIN VCC = MIN VCC = MAX VCC = MAX VCC = MAX 0.0 mA VCC = MIN VCC = 4.0 25 Max 5. For conditions shown as MIN or MAX.7 V VOUT = 0.0 Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –3.8 –1. nor for more than 1 second. use the appropriate value specified under guaranteed operating ranges.6 –150 9. I0x = GND OE. Min 2.1 23 mA I1x = 4.5 V VOUT = 0 V S.35 0.3 V V V VCC = MAX VCC = MAX VCC = MAX FAST AND LS TTL DATA 4-131 .0 V VIN = 0.

5 1.5 2.0 8.0 2.0 V ± 10% CL = 50 pF Min 2.0 7.0 7.0 3. The data on the selected inputs appears at the outputs in inverted form.5 7.3 4.5 Max 5.0 8. FAST AND LS TTL DATA 4-132 .5 2.0 6. the outputs are forced to a high impedance OFF state. The F258A is the logic implementation of a 4-pole.0 7.0 6.0 1.0 2.0 5. When the Select input is LOW.0 2. Designers should ensure the Output Enable signals to 3-state devices whose outputs are tied together are designed so there is no overlap.0 2.MC74F258A AC CHARACTERISTICS 74F TA = +25°C VCC = +5.0 7. It selects four bits of data from two sources under control of a common Select input (S). If the outputs of the 3-state devices are tied together. the I1x inputs are selected.5 2.0 1.0 1.5 8.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay In to Zn Propagation Delay S to Zn Output Enable Time Parameter Min 2.0 74F TA = 0°C to 70°C VCC = 5.0 6.5 2. all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input.0 ns ns ns Unit ns FUNCTIONAL DESCRIPTION The F258A is a quad 2-input multiplexer with 3-state outputs. The logic equations for the outputs are shown below: Za = OE • (I1a • S + I0a • S) Zb = OE • (I1b • S + I0b • S) Zc = OE • (I1c • S + I0c • S) Zd = OE • (I1d • S + I0d • S) When the Output Enable input (OE) is HIGH. the I0x inputs are selected and when Select is HIGH.5 Max 6.0 7.0 3.

this should only be done while in the memory mode. When operating the MC54/74F259 as an addressable latch. changing more than one bit of the address could impose a transient wrong address. In the addressable latch mode. It is a multifunctional device capable of storing single line data in eight addressable latches. data on the Data line (D) is written into the addressed latch. • Serial-to-Parallel Conversion • Eight Bits of Storage with Output of Each Bit Available • Random (Addressable) Data Entry • Active High Demultiplexing or Decoding Capability • Easily Expandable • Common Clear 8-BIT ADDRESSABLE LATCH FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 16 FUNCTIONAL DESCRIPTION The MC54/74F259 has four modes of operation as shown in the Mode Select Table. The Truth Table below summarizes the operations of the MC54/74F259. The device also incorporates an active LOW Common Clear for resetting all latches. In the one-of-eight decoding or demultiplexing mode. and also a 1-of-8 decoder and demultiplexer with active HIGH outputs. 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION CONNECTION DIAGRAM VCC 16 MR 15 E 14 D 13 Q7 12 Q6 11 Q5 10 Q4 9 MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 14 13 1 2 3 D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 4 5 6 7 9 10 11 12 E 15 MR 1 A0 2 A1 3 A2 4 Q0 5 Q1 6 Q2 7 Q3 8 GND FAST AND LS TTL DATA 4-133 .MC54/74F259 8-BIT ADDRESSABLE LATCH The MC54/74F259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. In the clear mode all outputs are LOW and unaffected by the address and data inputs. as well as an active LOW Enable. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states in the memory mode. the addressed output will follow the state of the D input with all other outputs in the LOW state. Therefore. All the latches remain in their previous state and are unaffected by the Data or Address inputs.

MC54/74F259 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current — High Output Current — Low 54.5 125 Unit V °C mA mA Q7 Q6 Q5 MR Q4 A2 A1 Q3 A0 Q2 Q1 D E Q0 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74 0 25 70 –1. 74 54.0 25 Max 5. 74 54 Min 4.0 20 Parameter 54. FAST AND LS TTL DATA 4-134 .5 –55 Typ 5.

FAST AND LS TTL DATA 4-135 .MC54/74F259 MODE SELECT TABLE E L H L H MR H H L L Mode Addressable Latch Memory Active HIGH 8-Channel Demultiplexer Clear H = HIGH Voltage Level L = LOW Voltage Level FUNCTION TABLE Operating Mode Master Reset Demultiplex (Active HIGH Decoder when D = H) Inputs MR L L L L • • • L H H H H • • • H E H L L L • • • L H L L L • • • L D X d d d • • • d X d d d • • • d A0 X L H L • • • H X L H L • • • H A1 X L L H • • • H X L L H • • • H A2 X L L L • • • H X L L L • • • H Q0 L Q=d L L • • • L q0 Q=d q0 q0 • • • q0 Q1 L L Q=d L • • • L q1 q1 Q=d q1 • • • q1 Q2 L L L Q=d • • • L q2 q2 q2 Q=d • • • q2 Outputs Q3 L L L L • • • L q3 q3 q3 q3 • • • q3 Q4 L L L L • • • L q4 q4 q4 q4 • • • q4 Q5 L L L L • • • L q5 q5 q5 q5 • • • q5 Q6 L L L L • • • L q6 q6 q6 q6 • • • q6 Q7 L L L L • • • Q=d q7 q7 q7 q7 • • • Q=d Store (Do Nothing) Addressable Latch H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition. q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.

5 4.5 8.5 13 9.8 –1. VOUT = 0 V VCC = MAX VCC = MAX ICC NOTES: 1.5 Min 2.5 Max 12 7.5 2.7 V VCC = MAX.0 3. IIN = –18 mA IOL = –1. 74 Output HIGH Voltage 74 Output LOW Voltage Input HIGH Current 0. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.0 45 4.0 10 7.7 0.0 mA IOL = –1.VIN = 7. nor for more than 1 second. use the appropriate value specified under recommended operating conditions for the applicable device type.0 3. VIN = 2.0 0.0 6.0 3.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Propagation Delay E to Qn Propagation Delay g y Dn to Qn Propagation Delay g y An to Qn Propagation Delay g y MR to Qn Min 4. Not more then one output should be shorted at a time.5 4.0 45 4.5 Max 13 8.5 20 V V µA mA mA mA mA mA 2.5 74F TA = 0 to + 70°C VCC = 5.5 9.5 4.5 3.5 3.0 3.0 V ±10% CL = 50 pF Min 4.6 –150 46 75 2. Total Output HIGH Total.0 90 9.5 3. For conditions shown as MIN or MAX.5 2.0 54F TA = –55 to + 125°C VCC = 5.0 V VCC = MAX.0 mA IOL = 20 mA VCC = MIN VCC = 4.0 V ±10% CL = 50 pF Min 4.5 10 Unit ns ns ns ns FAST AND LS TTL DATA 4-136 .5 15. 2.0 9.5 V VCC = MAX.75 V VCC = MIN VCC = MAX.0 50 5.1 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total.0 3.5 7. VIN = 0.5 11 11 5 11.0 3. Output LOW – 60 – 0.0 14.5 11.MC54/74F259 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH IIL IOS Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54.0 3.0 Max 10.

b. HIGH or LOW Dn to E Hold Time.0 2. HIGH or LOW Dn to E Setup Time.MC54/74F259 AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = +5. The Address to Enable setup time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected.0 Max 54F TA = –55 to +125°C VCC = 5.0 4.0 4.0 ±10% Min 5.0 2.0 V Symbol ts(H) ts(L) ( ) th(H) th(L) ts(H) ts(L) ( ) th(H) th(L) tW tW Parameter Setup Time.0 4. The Address to Enable hold time is the time after the LOW-to-HIGH Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected.0 4.0 4.0 0 0 4.0 2. HIGH or LOW A to E(b) E Pulse Width Min 4.0 4.0 0 0 4.0 2.0 4.0 4.0 0 0 4. FAST AND LS TTL DATA 4-137 .0 2.0 4.0 4.0 Max 74F TA = 0 to +70 °C VCC = 5.0 Max Unit ns ns ns ns ns ns MR Pulse Width a.0 V ±10% Min 4. HIGH or LOW A to E(a) Hold Time.0 4.0 2.0 5.

0 25 Max 5. • Synchronous Counting and Loading • Built-In Lookahead Carry Capability • Count Frequency 115 MHz Typical • Supply Current 95 mA Typical PIN ASSIGNMENT PE 24 P0 23 P1 22 P2 21 P3 20 VCC 19 P4 18 P5 17 P6 16 P7 15 TC CET 14 13 24 1 8-BIT BIDIRECTIONAL BINARY COUNTER FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 758-01 1 U/D 2 Q0 3 Q1 4 Q2 5 Q3 8 6 7 Q4 GND Q5 9 Q6 10 Q7 11 12 CP CEP 24 1 N SUFFIX PLASTIC CASE 724-03 24 1 DW SUFFIX SOIC CASE 751E-03 ORDERING INFORMATION MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current  High Output Current  Low Parameter 74 74 74 74 Min 4.5 0 Typ 5. are initiated by the rising edge of the clock. carry look-ahead for easy cascading and a U/D input to control the direction of counting. whether in counting or parallel loading.MC74F269 8-BIT BIDIRECTIONAL BINARY COUNTER The MC74F269 is a fully synchronous 8-stage up/down counter featuring a preset capability for programmable operation.5 70 –1. All state changes.0 20 Unit V °C mA mA FAST AND LS TTL DATA 4-138 .

PE = CET = CEP = U/D = GND: CP = ↑ FAST AND LS TTL DATA 4-139 .6 –150 120 mA 125 VCC = MAX 74 2.5 V: CP = ↑ 4. VCC = 4.7 V VCC = MAX. 3. VIN = 0. 2. For conditions shown as MIN or MAX.2 100 V V µA mA mA Min 2.5 V VCC = MAX.7 74 3. VOUT = 0 V (Note 3) (Note 4) NOTES: 1. PE = CET = CEP = U/D = GND: Pn = 4.5 –1. Not more than one output should be shorted at a time. use the appropriate value specified under guaranteed operating conditions for the applicable device type. Terminal Count Up is with all Qn outputs HIGH and Terminal Count Down is with all (a) = Qn outputs LOW. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless otherwise specified) Limits Symbol VOH VOL VIK IIH IIL IOS ICC Parameter Output HIGH Voltage Output LOW Voltage Input Clamp Diode Voltage Input HIGH Current 20 Input LOW Current Output Short Circuit Current (Note 2) Total Supply Current (total) ICCH ICCL – 60 93 98 – 0.35 0.0 mA 10 Typ Max Unit Test Conditions VCC = 4.MC74F269 FUNCTION TABLE Inputs Operating Mode Parallel Load Count Up Count Down Hold Do Nothing CP ↑ ↑ ↑ ↑ ↑ ↑ U/D X X h l X X CEP X X l l h X CET X X l l X h PE l l h h h h Pn l h X X X X Outputs Qn L H Count Up Count Down qn qn TC ( ) (a) (a) (a) (a) ( ) (a) H H = HIGH voltage level steady state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level steady state l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition X = Don’t care q = Lower case letters indicate the state of the referenced output prior to the LOW-to-HIGH clock transition ↑ = LOW-to-HIGH clock transition (a) = The TC is LOW when CET is LOW and the counter is at Terminal Count.4 0. nor for more than 1 second.0 V VIN = 2.5 V VCC = MIN.75 V IOL = 20 mA.5 V IOH = –1. IIN = –18 mA VCC = MAX VIN = 7.5 V VCC = 4.

MC74F269 LOGIC DIAGRAM P0 DETAIL A Q0 P1 P2 DETAIL A Q1 DETAIL A Q2 Q3 DETAIL A P3 DETAIL A Pn DATA D CP Q Q P4 DETAIL A Q4 P5 PE CLOCK P6 DETAIL A Q5 DETAIL A Q6 P7 CE CP U/D CEP CET DETAIL A Q7 TC FAST AND LS TTL DATA 4-140 .

0 V CL = 50 pF Min Set-up Time.0 3.5 9.5 6.0 4.0 9.0 5.0 6.0 4.0 9.0 1.0 5. HIGH or LOW CET.5 1.0 7.5 0 0 4. HIGH or LOW P to CP Hold Time.5 5.5 11 10 10 10 10 Max Unit MHz ns ns ns ns ns AC SETUP REQUIREMENTS 74F TA = +25°C VCC = +5.0 7. HIGH or LOW PE to CP Hold Time.0 0 0 4.0 4.0 5. HIGH or LOW U/D to CP Hold Time.0 V ±10% CL = 50 pF Min 2.0 Typ Max Unit ns ns ns ns ns ns ns ns ns Parameter Symbol ts( ) (H) ts(L) th( ) (H) th(L) ts( ) (H) ts(L) th( ) (H) th(L) ts( ) (H) ts(L) th( ) (H) th(L) ts( ) (H) ts(L) th( ) (H) th(L) tw( ) (H) tw(L) FAST AND LS TTL DATA 4-141 . CEP to CP Set-up Time.0 4.MC74F269 AC ELECTRICAL CHARACTERISTICS 74F TA = +25°C VCC = +5.0 4.5 0 0 6. HIGH or LOW CET.0 2.0 2. CEP to CP Hold Time.5 9.0 5. HIGH or LOW P to CP Set-up Time.5 3.0 9.5 Typ Max 74F TA = 0°C to +70°C VCC = +5.0 3.5 4.5 4.5 3.5 5.5 0 0 5.5 5. HIGH or LOW PE to CP Set-up Time.0 9.5 5.5 5.5 10.0 8.0 7.5 6.0 10 10 10 9.0 5.5 7.5 5.0 V ±10% CL = 50 pF Min 85 3.5 0 0 7.0 5.0 1.5 4.0 3.5 Typ Max 74F TA = 0°C to +70°C VCC = +5.5 4.0 9.0 V CL = 50 pF Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay g y CP to Qn (Load) PE = LOW Propagation Delay g y CP to Qn (Count) PE = HIGH Propagation Delay g y CP to TC Propagation Delay g y CET to TC Propagation Delay g y U/D to TC Min 100 3.0 0 0 4.5 4. HIGH or LOW U/D to CP Clock Pulse Width CP 2.0 4.5 10 10.5 4.5 9.0 1.5 2.

MC74F269 TIMING DIAGRAM PE P0 P1 P2 P3 P4 P5 P6 P7 CP U/D CEP AND CET Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TC 253 254 255 0 1 2 2 1 0 255 254 253 LOAD COUNT UP INHIBIT COUNT DOWN FAST AND LS TTL DATA 4-142 .

MC54/74F280 9-BIT PARITY GENERATOR/ CHECKER The MC54/74F280 is a high-speed parity generator/checker that accepts nine bits of input data and detects whether an even or an odd number of these inputs is HIGH. FAST AND LS TTL DATA 4-143 . the Sum Even output is LOW. The Sum Odd output is the complement of the Sum Even output. If an odd number is HIGH. 9-BIT PARITY GENERATOR/CHECKER FAST™ SCHOTTKY TTL CONNECTION DIAGRAM VCC 14 I5 13 I4 12 I3 11 I2 10 I1 9 I0 8 14 1 J SUFFIX CERAMIC CASE 632-08 1 I6 2 I7 3 NC 4 I8 5 ∑E 6 ∑O 7 GND 14 1 N SUFFIX PLASTIC CASE 646-06 LOGIC DIAGRAM I8 I7 I6 I5 I4 I3 I2 I1 I0 D SUFFIX SOIC CASE 751A-02 14 1 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 8 9 10 11 12 13 1 2 4 I0 I1 I2 I3 I4 I5 I6 I7 I8 ΣO ΣO ΣE 6 ΣE 5 VCC = PIN 14 GND = PIN 7 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. If an even number of inputs is HIGH. the Sum Even output is HIGH.

0 mA IOL = 20 mA VCC = MAX. VIN = 7.0 0.5 V VCC = MAX.5 2.MC54/74F280 FUNCTION TABLE Number of HIGH Inputs I0-I8 0. Not more than one output should be shorted at a time.35 0. 74 74 VOL IIH Output Low Voltage Input HIGH Current 2.2 Typ Max Unit V V V V V V µA µA mA mA mA Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. 74 54. VOUT = 0 V VCC = MAX VCC = 4.7 3. FAST AND LS TTL DATA 4-144 . 4. 2.4 3.5 V VCC = 4. 9 H = HIGH Voltage Level. 8 1.6 –150 38 Min 2.7 V VCC = MAX.4 0.5 20 100 IIL IOS ICC Input LOW Current Short Circuit Current (Note 2) Power Supply Current –60 25 –0. 3. IIN = –18 MA IOH = –1.0 25 25 Max 5.0 20 mA mA Unit V °C DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54. 2. 74 Min 4. L = LOW Voltage Level Outputs ∑ Even H L ∑ Odd L H GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.5 -55 0 Typ 5. VIN = 0.0 mA IOH = 1. 5.8 –1. VIN = 2.75 V VCC = MIN NOTES: 1. 7. For conditions shown as MIN or MAX. 74 54 74 IOH IOL Output Current — High Output Current — Low 54. 6. use the appropriate value specified under recommended operating conditions for the applicable device type.0 V VCC = MAX.5 125 70 –1. nor for more than 1 second.

MC54/74F280 AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.5 Max 16 17 16 17 ns Unit ns FAST AND LS TTL DATA 4-145 .5 4.5 4.5 4.5 Max 20 21 20 21 74F TA = 0°C to +70°C VCC = 5.5 4.5 4.5 Max 15 16 15 16 54F TA = –55°C to +125°C VCC = 5.5 4.5 4.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay In to ∑E Propagation Delay In to ∑O Min 4.0 V ±10% CL = 50 pF Min 4.0 V ±10% CL = 50 pF Min 4.5 4.5 4.

Figure C shows a way of dividing the F283 into a 2-bit and a 1-bit adder. B0 can be arbitrarily assigned to pins 5. Figure E shows one method of implementing a 5-input majority gate. The outputs S0. they do not influence S2.MC54/74F283 4-BIT BINARY FULL ADDER (With Fast Carry) The MC54/74F283 high-speed 4-bit binary full adder with internal carry lookahead. Figure B shows how to make a 3-bit adder. the intermediate carries of the F283 are not brought out for use as inputs or outputs. whether HIGH or LOW.Thus C0. Due to pin limitations. S1 and S2 present a binary number equal to the number of inputs I1–I5 that are true. When three or more of the inputs I1–I5 are true. CONNECTION DIAGRAM VCC 16 B2 15 A2 14 S2 13 A3 12 B3 11 S3 10 C4 9 13 10 S2 S3 C4 9 J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 7 C0 4 1 S0 S1 A0 B0 A1 B1 A2 B2 A3 B3 5 6 3 2 14 15 12 11 VCC = PIN 16 GND = PIN 8 1 S1 2 B1 3 A1 4 S0 5 A0 6 B0 7 C0 8 GND FAST AND LS TTL DATA 4-146 . an intermediate stage. The third stage adder (A2. the carry from the third adder. other means can be used to effectively insert a carry into. B0–B3) and a Carry input (C0). B2. S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing out the carry from the second stage on S2. Due to the symmetry of the binary add function. or bring a carry out from. The F283 will operate with either active-HIGH or active-LOW operands (positive or negative logic). accepts two 4-bit binary words (A0–A3. Figure D shows a method of implementing a 5-input encoder. Tying the operand inputs of the fourth adder (A3. The binary weight of the various inputs and outputs is indicated by the subscript numbers. A0. Note that as long as A2 and B2 are the same. Similarly. Using somewhat the same principle. See Figure A. the output M5 is true. 4-BIT BINARY FULL ADDER (With Fast Carry) FAST™ SCHOTTKY TTL FUNCTIONAL DESCRIPTION The F283 adds two 4-bit binary words (A plus B) plus the incoming carry C0. The binary sum appears on the Sum (S0–S3) and outgoing carry (C4) outputs. B3) LOW makes S3 dependent only on. the F283 can be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). 20 (A0 + B0 + C0) + 21 (A1 + B1) + 22 (A2 + B2) + 23 (A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4 Where (+) = plus Interchanging inputs of equal weight does not affect the operation. However. and equal to. Note that if C0 is not used it must be tied LOW for active-HIGH logic or tied HIGH for active-LOW logic. It generates the binary Sum outputs (S0–S3) and the Carry output (C4) from the most significant bit. where the inputs are equally weighted. when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. 6 and 7. representing powers of two.

GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current — High Output Current — Low 54. Active-HIGH versus Active-LOW Interpretation C0 Logic Levels Active HIGH Active LOW L 0 1 A0 L 0 1 A1 H 1 0 A2 L 0 1 A3 H 1 0 B0 H 1 0 B1 L 0 1 B2 L 0 1 B3 H 1 0 S0 H 1 0 S1 H 1 0 S2 L 0 1 S3 L 0 1 C4 H 1 0 Active HIGH: 0 + 10 + 9 = 3 + 16 Active LOW: 1 + 5 + 6 = 12 + 0 FAST AND LS TTL DATA 4-147 . 74 0 — — 25 — — 70 –1.5 125 Unit V °C mA mA Figure A.MC54/74F283 LOGIC DIAGRAM C0 A0 B0 A1 B1 A2 B2 A3 B3 S0 S1 S2 S3 C4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74 54.5 – 55 Typ 5.0 25 Max 5. 74 54 Min 4.0 20 Parameter 54.

5 20 V V µA µA mA mA mA mA VOUT = 0 V Inputs = 4.5 V VCC = MIN VCC = 4.5 V VCC = 4.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1.5 3.0 mA IOL = 20 mA VIN = 2. For conditions such as MIN or MAX. 5-Input Majority Gate DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54.6 –1. 3-Bit Adder Figure C. nor for more than 1 second. 2-Bit and 1-Bit Adders I3 I3 I1 I2 L I4 I5 A0 B0 A1 B1 A2 B2 A3 B3 A0 B0 A1 B1 A2 B2 A3 B3 C0 S0 20 S1 21 S2 22 S3 C4 C0 S0 S1 S2 S3 C4 I1 I2 I4 I5 M5 Figure D.5 V VCC = MAX VCC = MAX 2.0 V VIN = 0. 74 Output HIGH Voltage 74 Output LOW Voltage Input HIGH Current 100 Input LOW Current C0 Input A and B Inputs IOS ICC Output Short Circuit Current (Note 2) Power Supply Current – 60 36 – 0.7 3.4 Min 2.2 –150 55 2.4 0. 2. use the appropriate value specified under guaranteed operating ranges.35 0.7 V VIN = 7. Not more than one output should be shorted at a time.MC54/74F283 C10 L A0 B0 A1 B1 A2 B2 A3 B3 C0 S0 S1 S2 S3 C3 C4 C0 A0 B0 A1 B1 A0 B0 A1 B1 C0 S0 S0 S1 S1 S2 C2 S3 S10 A10 B10 A2 B2 A3 B3 C4 C11 Figure B. 5-Input Encoder Figure E. FAST AND LS TTL DATA 4-148 .0 mA IOH = –1.8 –1.0 0.75 V VCC = MIN VCC = MAX IIL VCC = MAX NOTES: 1.

5 4.5 7.MC54/74F283 AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 V ±10% CL = 50 pF Min 3.0 Max 14 14 14 14 10.5 8.0 5.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay C0 to Sn Propagation Delay An or Bn to Sn Propagation Delay C0 to C4 Propagation An or Bn to C4 Min 3.0 7.0 3.0 3.5 3.0 3.0 8.3 Max 9.5 4.5 3.5 7.0 3.5 10.0 7.0 3.5 9.0 3.0 54F TA = –55 to +125°C VCC = 5.0 V ±10% CL = 50 pF Min 3.0 3.5 8.5 10 10.5 8.5 3.0 7.5 9.5 3.0 Unit ns ns ns ns FAST AND LS TTL DATA 4-149 .5 10.0 Max 10.5 7.0 Typ 7.0 3.5 10 74F TA = 0 to +70°C VCC = 5.0 3.4 5.7 5.5 4.5 10.0 7.0 3.5 3.0 3.0 3.5 9.5 3.7 5.

MC74F323 8-INPUT SHIFT/STORAGE REGISTER WITH SYNCHRONOUS RESET AND COMMON I/O PINS The MC74F323 is an 8-Bit Universal Shift/Storage Register with 3-state outputs. All modes are activated on the LOW-to-HIGH transition of the clock.5 70 –1. Its function is similar to the F299 with the exception of Synchronous Reset. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. shift left. Four modes of operation are possible: hold (store). Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading.0/– 3. shift right and parallel load. 8-INPUT SHIFT/STORAGE REGISTER WITH SYNCHRONOUS RESET AND COMMON I/O PINS FAST™ SCHOTTKY TTL • Common I/O For Reduced Pin Count • Four Operation Modes: Shift Left. A separate active LOW Master Reset is used to reset the register. Shift Right.0 25 Max 5. Parallel Load and Store • Separate Continuous Inputs and Outputs from Q0 and Q7 Allow Easy Cascading • Fully Synchronous Reset • 3-State Outputs for Bus Oriented Applications • Input Clamp Diodes Limit High-Speed Termination Effects 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 CONNECTION DIAGRAM VCC 20 S1 19 DS7 Q7 18 17 I/O7 I/O5 I/O3 I/O1 CP 16 15 14 13 12 DS0 11 20 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION 1 S0 2 3 4 5 6 8 7 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 9 10 SR GND MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4.5 0 Typ 5.0 20/24 Unit V °C mA mA FAST AND LS TTL DATA 4-150 .

7 2. .0 V VIN = 5. load and reset operations can still occur. nor for more than 1 second.7 VCC = MAX VIN = 7. 2.0 –1. Hold H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW-to-HIGH clock transition. A HIGH signal on either OE1 or OE2 disables the 3-state buffers and puts the I/O pins in the high impedance state. shift left. VIN = 2 7 V MAX 2. VOUT = 0.0 mA 30 IOL = 20 mA IOL = 24 mA VCC = 4.5 V VCC = MIN VCC = MAX. Q0 → Q1. For conditions shown as MIN or MAX. IIN = –18 mA VCC = 4. Inputs can change when the clock is in either state provided only that the recommended set-up and hold times.5 2.75 V IOH = – 3. High-Level Voltage Applied Off-State Output Current. All flip-flop outputs are brought out through 3-state buffers to separate I/O pins that also serve as data inputs in the parallel load mode.0 0. FUNCTIONAL DESCRIPTION The MC74F323 contains eight edge-triggered D-type flips-flops and the interstage logic necessary to perform synchronous reset. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. The type of operation is determined by S0 and S1. etc.4 Min 2.4 0. hold.MC74F323 FUNCTION TABLE Inputs SR L H H H H S1 X H L H L S0 X H H L L CP ↑ ↑ ↑ ↑ X Response Synchronous Reset: Q0–Q7 = LOW Parallel Load: I/On → Qn Shift Right: DS0 → Q0. All other state changes are initiated by the LOW-to-HIGH CP transition.75 V VCC = 4. S1 Other Inputs 2. Low-Level Voltage Applied Output Short Circuit Current (Note 2) Total Supply Current – 60 S0. The 3-state buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.1 1.5 V IOH = –1. FAST AND LS TTL DATA 4-151 .7 V VOUT = 5. shift right.7 2.6 70 1.5 V VCC = MAX VOUT = 0 V Outputs Disabled NOTES: 1. use appropriate value specified under recommended operating conditions for the applicable device type.2 – 0.8 –1. Shift Left: DS7 → Q7. In this condition the shift.5 VCC = MAX VOUT = 2. parallel load and hold operations.2 Typ Max Unit V V V V V V µA mA mA µA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.0 mA 10 VCC = 4. etc.5 20 70 0. Q7 → Q6. relative to the rising edge of CP. as shown in the Function Table.0 – 0.5 V VCC = MAX.5 0. Not more than one output should be shorted at a time.6 –150 95 3.5 V VCC = MAX. VIN = 0 5 V MAX 0. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Q0/Q7 VOH Output HIGH Voltage I/O VOL Output LOW Voltage 74 74 74 74 Q0/Q7 I/O Q0/Q7 IIH Input HIGH Current I/O Q0/Q7 I/O IIL IOZH IOZL IOS ICC Input LOW Current Off-State Output Current. are observed. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words.

0 V CL = 50 pF Min Max 70 3.0 9.0 2.0 7.5 9.0 2.0 Max Unit ns ns ns ns ns ns ns S1 19 S0 1 LOGIC DIAGRAM VCC = PIN 20 GND = PIN 10 = PIN NUMBERS 18 DS7 DS0 SR CP 11 9 12 8 2 3 6 14 5 15 4 16 Q0 OE1 OE2 D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q 17 Q7 7 13 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 FAST AND LS TTL DATA 4-152 . HIGH or LOW S0 or S1 to CP Set-Up Time.0 11 8.0 2.0 3.5 4.5 Symbol fMAX tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Input Frequency Propagation Delay CP to Q0 or Q7 Propagation Delay CP to I/On Output Enable Time to HIGH or LOW Level Output Disable Time to HIGH or LOW Level Unit MHz ns ns ns ns AC SETUP REQUIREMENTS 74F TA = +25°C VCC = +5.5 3.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Set-Up Time.0 6.0 Typ Max 74F TA = 0°C to +70°C VCC = +5. HIGH or LOW I/On.0 10 10 0.0 11 7. DS7 to CP Set-Up Time. Min 8.MC74F323 AC ELECTRICAL CHARACTERISTICS 74F TA = +25°C VCC = +5. HIGH or LOW S0 or S1 to CP Hold Time.5 3. DS0.0 7.0 5. DS7 to CP Hold Time.5 0.0 0.0 0. HIGH or LOW SR to CP CP Pulse Width HIGH or LOW Width. DS0.5 8.5 8.5 0.0 10 10 0.0 5. HIGH or LOW I/On.0 V ±10% CL = 50 pF Min Max 70 3.0 2.0 8.5 3.0 5.0 7.0 0.5 5.5 74F TA = 0°C to +70°C VCC = +5.5 5.0 2.5 4. HIGH or LOW SR to CP Hold Time.0 3.0 2.0 10 9.0 7.0 2.0 5.0 5.0 2.0 10 6.5 3.0 V ±10% CL = 50 pF Min 8.0 0.5 10 12 9.

or end around. data outputs will follow selected data inputs. Outputs O0–O3 are 3-state. A 7-bit data word is introduced at the In inputs and is shifted according to the code applied to the select inputs S0. etc. Shifting by more than three places is accomplished by paralleling the 3-state outputs of different packages and using the Output Enable (OE) inputs as a third Select level. sign-extend or end-around (barrel) shift functions. 1. For expansion to longer words. where the sign bit is repeated during a shift down. arithmetic.MC54/74F350 4-BIT SHIFTER (With 3-State Outputs) The MC54/74F350 is a specialized multiplexer that accepts a 4-bit word and shifts it 0. 4-BIT SHIFTER (With 3-State Outputs) FAST™ SCHOTTKY TTL • Linking Inputs for Word Expansion • 3-State Outputs for Extending Shift Range FUNCTIONAL DESCRIPTION The F350 is operationally equivalent to a 4-input multiplexer with the inputs connected so that the select code causes successive one-bit shifts of the data word. with zeros pulled in at either or both ends of the shifting field. When OE is LOW. 2 or 3 places on words of any length. This internal connection makes it possible to perform shifts of 0. where the data word forms a continuous loop. This feature allows shifters to be cascaded on the same output lines or to a common bus. four packages a 16-bit word. three linking inputs are provided for lower-order bits. S1. 1. LOGIC EQUATIONS O0 = S0 S1 I0 + S0 S1 l–1 + S0 S1 I–2 + S0 S1 I–3 O1 = S0 S1 I1 + S0 S1 I0 + S0 S1 l–1 + S0 S1 I–2 O2 = S0 S1 I2 + S0 S1 I1 + S0 S1 I0 + S0 S1 I–1 O3 = S0 S1 I3 + S0 S1 I2 + S0 S1 I1 + S0 S1 I0 TRUTH TABLE Inputs OE H L L L L S1 X L L H H S0 X L H L H O0 Z I0 I–1 I–2 I–3 O1 Z I1 I0 I–1 I–2 Outputs O2 Z I2 I1 I0 I–1 O3 Z I3 I2 I1 I0 J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 13 9 10 OE S1 S0 I–3 I–2 O0 I–1 O1 I0 O2 I1 O3 I2 I3 VCC = PIN 16 GND = PIN 8 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial 1 2 3 4 5 6 7 CONNECTION DIAGRAM VCC 16 O0 15 O1 14 OE 13 O2 12 O3 11 S0 10 S1 9 15 14 12 11 1 I–3 2 I–2 3 I–1 4 I0 5 I1 6 I2 7 I3 8 GND FAST AND LS TTL DATA 4-153 . as determined by two Select (S0. thus two packages can shift an 8-bit word. the data outputs will be forced to the high-impedance state. controlled by an active-LOW output enable (OE). the F350 can perform zero-backfill. 2 or 3 places. when HIGH. With appropriate interconnections. The shift function can be logical. S1) inputs.

7 V VOUT = 0.3 0.MC54/74F350 LOGIC DIAGRAM I–3 I–2 I–1 I0 I1 I2 I3 S1 S0 OE O0 Symbol VCC TA IOH IOL Supply Voltage O1 Parameter O2 Min 54.5 V VCC = 4.0 25 25 — — Max 5. 74 54. Not more than one output should be shorted at a time.5 V VIN = 2. 74 Output HIGH Voltage 74 Output LOW Voltage Output OFF Current — HIGH Output OFF Current — LOW Input HIGH Current 100 Input LOW Current Output Short Circuit Current (Note 2) – 60 22 26 26 –1.0 0.7 V VIN = 7.3 Min 2.5 V VOUT = 0 V Outputs HIGH Outputs LOW Outputs OFF VCC = MAX VCC = MIN VCC = 4.7 3.0 V VIN = 0.35 0.8 –1.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = – 3. NOTES: 2. 74 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IOZH IOZL IIH IIL IOS ICCH ICCL ICCZ Power Supply Current Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54.0 mA IOL = 24 mA VOUT = 2. use the appropriate value specified under guaranteed operating ranges. For conditions such as MIN or MAX. 74 54 4.2 –150 35 41 42 mA 2.5 – 55 0 — — O3 Typ 5. FAST AND LS TTL DATA 4-154 .5 125 70 – 3.5 50 – 50 20 V V µA µA µA mA mA 2.0 mA IOH = – 3.4 3.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX NOTES: 1. nor for more than 1 second.0 24 Unit V °C mA mA GUARANTEED OPERATING RANGES Operating Ambient Temperature Range 74 Output Current — High Output Current — Low 54.

0 5.5 6.0 9.5 4.0 74F TA = 0 to +70°C VCC = 5.5 Max 7.0 V ±10% CL = 50 pF Min 3.5 4. Zero Backfill 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND S0 S1 OE S0 S1 OE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Y0 Y1 Y2 Y3 I–3 I–2 I–1 I0 I1 I2 I3 S0 S1 OE Y0 Y1 Y2 Y3 I–3 I–2 I–1 I0 I1 I2 I3 S0 S1 OE Y0 Y1 Y2 Y3 I–3 I–2 I–1 I0 I1 I2 I3 S0 S1 OE Y0 Y1 Y2 Y3 I–3 I–2 I–1 I0 I1 I2 I3 S1 L L H H S0 L H L H NO SHIFT SHIFT 1 PLACE SHIFT 2 PLACES SHIFT 3 PLACES FAST AND LS TTL DATA 4-155 .0 2.0 13.5 10 8.0 2.0 2.MC54/74F350 AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 3.5 11 7.0 6.5 4.0 2.0 9.0 2.5 4.0 2.0 2.5 8.5 7.5 Unit ns ns ns ns APPLICATIONS 16-Bit Shift-Up 0 to 3 Pieces.5 10 10.0 10 6.5 5.5 Max 7.5 4.0 1.5 Max 6.0 2.0 5.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay In to 0n Propagation Delay Sn to On Out ut Output Enable Time Out ut Output Disable Time Min 3.0 3.5 11 9.0 V ±10% CL = 50 pF Min 3.0 2.0 1.5 54F TA = –55 to +125°C VCC = 5.5 7.5 4.0 3.0 1.

MC54/74F350 8-Bit End Around Shift 0 to 7 Pieces 0 1 2 3 4 5 6 7 S0 S1 I–3 I–2 I–1 I0 I1 I2 I3 S0 S1 I–3 I–2 I–1 I0 I1 I2 I3 S0 S1 I–3 I–2 I–1 I0 I1 I2 I3 S0 S1 I–3 I–2 I–1 I0 I1 I2 I3 OE S0 S1 S2 S2 Y0 Y1 Y2 Y3 OE Y0 Y1 Y2 Y3 OE Y0 Y1 Y2 Y3 OE Y0 Y1 Y2 Y3 0 1 2 3 4 5 6 7 S2 L L L L H S1 L L H H L S0 L H L H L NO SHIFT SHIFT END AROUND 1 SHIFT END AROUND 2 SHIFT END AROUND 3 SHIFT END AROUND 4 S2 H H H S1 L H H S0 H L H SHIFT END AROUND 5 SHIFT END AROUND 6 SHIFT END AROUND 7 13-Bit Twos Complement Scaler 12 11 10 9 8 7 6 5 4 3 2 1 S S0 S1 I–3 I–2 I–1 I0 I1 I2 I3 S0 S1 I–3 I–2 I–1 I0 I1 I2 I3 S0 S1 I–3 I–2 I–1 I0 I1 I2 I3 OE S0 S1 Y0 Y1 Y2 Y3 OE Y0 Y1 Y2 Y3 OE Y0 Y1 Y2 Y3 12 11 10 9 8 7 6 5 4 3 2 1 S S1 L L H H S0 L÷8 H÷4 L÷2 H NO CHANGE SCALE 1/8 1/4 1/2 1 FAST AND LS TTL DATA 4-156 .

• Inverted Version of the F153 • Separate Enables for Each Multiplexer • Input Clamp Diode Limits High-Speed Termination Effects CONNECTION DIAGRAM (TOP VIEW) VCC 16 Eb 15 S0 14 I3b 13 I2b 12 I1b 11 I0b 10 Zb 9 16 1 DUAL 4-INPUT MULTIPLEXER FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 1 Ea 2 S1 3 I3a 4 I2a 5 I1a 6 I0a 7 Za 8 GND 16 1 N SUFFIX PLASTIC CASE 648-08 LOGIC DIAGRAM Ea I0a I1a I2a I3a S1 S0 I0b I1b I2b I3b Eb 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 2 S1 14 S0 Ea I0a I1a I2a I3a I0b I1b I2b I3b Eb 1 6 5 4 3 10 11 12 13 15 7 Za Za Zb 9 VCC = PIN 14 GND = PIN 7 Zb FAST AND LS TTL DATA 4-157 . It can select two bits of data from four sources.MC54/74F352 DUAL 4-INPUT MULTIPLEXER The MC54/74F352 is a very high speed dual 4-input multiplexer with common Select inputs and individual Enable inputs for each section. The F352 is the functional equivalent of the F153 except with inverted outputs. The two buffered outputs present data in the inverted (complementary) form.

Eb) which can be used to strobe the outputs independently.MC54/74F352 GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. Za = Ea • (I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 • S0 + I3a • S1 • S0) Zb = Eb • (I0b • S1 • S0 + I1b • S1 • S0 + I2b • S1 • S0 + I3b • S1 • S0) FUNCTION TABLE Select Inputs S0 X L L H H L L H H S1 X L L L L H H H H E H L L L L L L L L Inputs (a or b) I0 X L H X X X X X X I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H Output Z H H L H L H L H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care FAST AND LS TTL DATA 4-158 . A less obvious application is as a function generator.55 0 Typ 5. When the Enables (Ea.0 25 25 Max 5. It selects two bits of data from up to four sources under the control of the common Select inputs (S0. the corresponding outputs (Za. Eb) are HIGH.0 20 Unit V °C mA mA FUNCTIONAL DESCRIPTION The F352 is a dual 4-input multiplexer. 74 54 74 IOH IOL Output Current — High Output Current — Low 54.The two 4-input multiplexer circuits have individual active-LOW Enables(Ea. The F352 can generate two functions of three variables. This is useful for implementing highly irregular random logic. The particular register from which the data came would be determined by the state of the Select inputs.5 . 74 54. 74 Min 4.5 125 70 –1. Zb) are forced HIGH. The logic equations for the outputs are shown below: The F352 can be used to move data from a group of registers to a common output bus. S1).

For conditions shown as MIN or MAX.0 1.5 3.0 2.7 V VIN = 7.5 8.2 Typ Max Unit V V V V V V µA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1.0 V VIN = 0.5 2.5 V VOUT = 0 V VIN = GND VIN = HIGH VCC = MAX VCC = MAX VCC = MAX VCC = MIN VCC = 4.0 0.5 7.0 3.0 74F TA = 0°C to + 70°C VCC = 5.0 2.35 0.0 V ± 10% CL = 50 pF Min 3.5 Typ 7.0 1.5 20 100 IIL IOS ICCH ICCL Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current –60 9.0 Max 14 11 10 9.0 7.3 –0.5 3.0 mA IOH = –1. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.0 2.7 3.3 13.4 7.5 2.0 5.0 8.0 7.5 9.MC54/74F352 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.0 5.75 V VCC = MIN VCC = MAX NOTES: 1. use the appropriate value specified under guaranteed operating ranges.0 V ± 10% CL = 50 pF Min 3.50 V VCC = 4.5 54F TA = 55°C to +125°C VCC = 5. nor for more than 1 second.0 Max 12.9 3.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Sn to Zn Propagation Delay En to Zn Propagation Delay In to Zn Min 3.5 1.6 –150 14 20 mA mA mA Min 2.0 4.0 Max 11 8. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 8.0 2. Not more than one output should be shorted at a time.0 2. 2.0 mA IOL = 20 mA VIN = 2.0 2.5 2.8 –1.0 9.4 3.5 2.0 5.4 0.0 4.5 2.0 ns ns Unit ns FAST AND LS TTL DATA 4-159 .

OEb) inputs which. It can select two bits of data from four sources using common Select inputs.DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The MC54/74F353 is a dual 4-input multiplexer with 3-state outputs. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so that there is no overlap. when HIGH. all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (OE) inputs. They select two bits from four sources selected by common Select inputs (S0. MC54/74F353 DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS • Inverted Version of F253 • Multifunction Capability • Separate Enables for Each Multiplexer J SUFFIX CERAMIC CASE 620-09 16 1 FUNCTIONAL DESCRIPTION The MC54/74F353 contains two identical 4-input multiplexers with 3-state outputs. allowing the outputs to interface directly with bus-oriented systems. force the outputs to a high impedance (high Z) state. S1).The 4-input multiplexers have individual Output enable (OEa. The logic equations for the outputs are shown below: Za=OEa • (I0a • S1 • S0 +I1a • S1 • S0 + I2a • S1 • S0 + I3a • S1 • S0) Zb=OEb• (I0b • S1 • S0 + I1b • S1 • S0 + I2b•S1•S0+I3b•S1•S0) If the outputs of 3-state devices are tied together. 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION CONNECTION DIAGRAM (TOP VIEW) VCC 16 OEb 15 S0 14 I3b 13 I2b 12 I1b 11 I0b 10 Zb 9 MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 2 S1 1 OEa 2 S1 3 I3a 4 I2a 5 I1a 6 I0a 7 Za 8 GND 7 Za 14 S0 OEa I0a I1a I2a I3a I0b I1b I2b I3b OEb 1 6 5 4 3 10 11 12 13 15 9 VCC = PIN 16 GND = PIN 8 Zb FAST AND LS TTL DATA 4-160 .

5 –55 0 Typ 5.0 24 mA mA Unit V °C FAST AND LS TTL DATA 4-161 .0 25 25 Max 5. 74 Min 4.5 125 70 –3.MC54/74F353 FUNCTION TABLE Select Inputs S0 X L L H H L L H H S1 X L L L L H H H H I0 X L H X X X X X X Data Inputs I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H Output Enable OE H L L L L L L L L Output Z (Z) H L H L H L H L Address inputs S0 and S1 are common to both sections. 74 54. 74 54 74 IOH IOL Output Current  High Output Current  Low 54. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care (Z) = High Impedance LOGIC DIAGRAM OEb I3b I2b I1b I0b S0 S1 I3a I2a I1a I0a OEa Zb Za GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.

0 ns ns Unit ns FAST AND LS TTL DATA 4-162 .7 3.0 8.2 Typ Max Unit V V V V V V µA µA µA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –3.0 0.0 V ± 10% CL = 50 pF Min 3.0 2. Sn.MC54/74F353 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 V VOUT = 0 V In.5 8. Not more than one output should be shorted at a time.5 2.5 2.0 1.5 9.0 1.4 2.35 0. nor for more than 1 second.3 13.0 5.5 V VCC = MAX VCC = MAX VCC = MAX VCC = MIN VCC = 4. For conditions shown as MIN or MAX.0 6.3 15 –0.0 3.0 1.0 V VIN = 0.6 –150 14 20 23 mA mA mA Min 2.5 10.5 1.0 3.0 4.3 0.5 V VCC = 4.3 3.5 7.0 2.5 V VIN = 2.0 1.0 6.5 Max 12. Sn = GND OEn = 4. 2.5 8.7 V VIN = 7.0 3.0 2.0 5.0 2.7 V VOUT = 0.0 V ± 10% CL = 50 pF Min 3.0 3.5 Max 14 11 9.5 7.5 50 –50 20 100 IIL IOS ICCH ICCL ICCZ Power Supply Current Input LOW Current Output Short Circuit Current (Note 2) –60 9.5 3.5 2.0 9. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 54F TA = .75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX NOTES: 1.0 8.5 1.0 3.0 Max 11 8.0 mA IOH = –3.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Parameter Propagation Delay Sn to Zn Propagation Delay In to Zn Output Enable Time Min 3. use the appropriate value specified under recommended operating conditions for the applicable device type.0 7. OEn = GND In.0 mA IOL = 24 mA VOUT = 2.0 10.55°C to + 125°C VCC = 5.0 3. 74 74 VOL IOZH IOZL IIH Output LOW Voltage Output OFF Current — HIGH Output OFF Current — LOW Input HIGH Current 2.0 2.0 3.8 –1.0 74F TA = 0°C to + 70°C VCC = 5.0 9.

0 25 25 Max 5. 3-STATE F366 HEX BUFFER/DRIVER GATED ENABLE INVERTING.11 HEX BUFFER/DRIVER GATED ENABLE NONINVERTING AND INVERTING. 3-STATE FAST™ SCHOTTKY TTL 1 OE1 2 I 3 O 4 I 5 O 6 I 7 O 8 GND 16 MC54/74F366 VCC OE2 16 15 I 14 O 13 I 12 O 11 I 10 O 9 J SUFFIX CERAMIC CASE 620-09 1 16 1 N SUFFIX PLASTIC CASE 648-08 1 OE1 2 I 3 O 4 I 5 O 6 I 7 O 8 GND 16 1 FUNCTION TABLE Inputs OE1 L L X H OE2 L L H X I L H X X O L H Z Z Outputs O H L Z Z H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.5 –55 0 Typ 5. 3-STATE CONNECTION DIAGRAM MC54/74F365 VCC OE2 16 15 I 14 O 13 I 12 O 11 I 10 O 9 MC54/74F365 MC54/74F366 F365 HEX BUFFER/DRIVER GATED ENABLE NONINVERTING.74 54 74 IOH IOL Output Current — High 54 74 Output Current — Low 54 74 Min 4.5 125 70 –12 –15 48 64 mA mA Unit V °C FAST AND LS TTL DATA 4-163 .

5 V VIN = 2.0 V ± 10% CL = 50 pF Min 2.0 4.0 54F TA = –55°C to +125°C VCC = 5.5 5.5 5. nor for more than 1 second.0 2.5 4.0 1.75 V VCC = 4.55 0.4 2.4 0.0 6.5 V VOUT = GND VCC = MAX VCC = MAX VCC = MAX VCC = 0 V VCC = MAX VCC = MAX VCC = MIN VCC = 4.5 Max 8.0 1.0 2.0 0.5 V VCC = 4.0 mA IOH = –12 mA IOH = –15 mA IOL = 48 mA IOL = 64 mA VOUT = 2.0 2.0 7.0 V VIN = 0. 2.0 6.4 3.5 7.5 9. For conditions shown as MIN or MAX.0 3.5 1.0 V ± 10% CL = 50 pF Min 2.0 3.5 6.5 1.0 4.0 3. use the appropriate value specified under recommended operating conditions for the applicable device type.0 3.5 Typ 4.74 74 VOH Output HIGH Voltage 54 74 VOL Output LOW Voltage 54 74 IOZH IOZL IIH Output OFF Current–HIGH Output OFF Current–LOW Input HIGH Current 2.0 9.5 V VCC = MAX NOTES: 1.5 8.5 5.0 1.0 3.5 V VCC = 4.8 –1.5 6.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay In to On Propagation Delay In to On Output Enable Time to HIGH and LOW Level Output Disable Time from HIGH and LOW Level F366 F365 Min 2.0 7.5 6.0 8.5 8.0 4.5 11 10.5 Max 7.55 50 –50 20 100 IIL IOS Input LOW Current Output Short Circuit Current (Note 2) ICCH F365 ICCL ICCZ ICC F366 ICCH ICCL ICCZ –100 –20 –225 35 62 48 25 62 48 mA VCC = MAX 3.4 Min 2.5 7. Not more than one output should be shorted at a time.0 2.5 5.0 2.0 mA IOH = –3.35 0.5 74F TA = 0°C to +70°C VCC = 5.0 2.7 2.0 6.0 Max 6.MC54/74F365 • MC54/74F366 DC CHARACTERISTICS OVER OPERATING TRMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54.5 10 9.5 ns ns ns Unit ns FAST AND LS TTL DATA 4-164 .2 Typ Max V V V V V V V V V µA µA µA µA µA mA Unit Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –3.7 V VIN = 7.7 V VOUT = 0.5 1.0 0.5 7.0 3. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 3.0 6.0 4.0 2.

NONINVERTING 3-STATE F368 HEX BUFFER/DRIVER 4-BIT PLUS 2-BIT. 3-STATE CONNECTION DIAGRAMS MC54/74F367 VCC OE2 16 15 I 14 O 13 I 12 O 11 I 10 O 9 MC54/74F367 MC54/74F368 F367 HEX BUFFER/DRIVER 4-BIT PLUS 2-BIT. 74 54 74 IOH IOL Output Current — High 54 74 Output Current — Low 54 74 Min 4.5 125 70 –12 –15 48 64 mA mA Unit V °C FAST AND LS TTL DATA 4-165 . INVERTING 3-STATE FAST™ SCHOTTKY TTL 1 OE1 2 I 3 O 4 I 5 O 6 I 7 O 8 GND 16 MC54/74F368 VCC OE2 16 15 I 14 O 13 I 12 O 11 I 10 O 9 J SUFFIX CERAMIC CASE 620-09 1 16 1 N SUFFIX PLASTIC CASE 648-08 1 OE1 2 I 3 O 4 I 5 O 6 I 7 O 8 GND 16 1 FUNCTION TABLE Inputs OE L L H I L H X O L H Z Outputs O H L Z H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.HEX BUFFER/DRIVER 4-BIT PLUS 2-BIT.0 25 25 Max 5.5 –55 0 Typ 5. NONINVERTING AND INVERTING.

5 9.8 –1.5 8.0 3.5 4.5 6.5 10 8.0 1.75 V VCC = 4.0 2.7 V VOUT = 0.0 2.5 74F TA = 0°C to +70°C VCC = 5.0 3.0 V ± 10% CL = 50 pF Min 2.5 Typ 4.5 6.0 2.5 ns ns ns Unit ns FAST AND LS TTL DATA 4-166 .7 2.0 7.5 7.0 54F TA = –55°C to +125°C VCC = 5.5 3.5 3.5 8.5 6.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay In to On Propagation Delay In to On Output Enable Time to HIGH and LOW Level Output Disable Time from HIGH and LOW Level F368 F367 Min 2.0 7.0 2.5 V VCC = 4.0 1.4 3.4 0. 74 74 VOH Output HIGH Voltage 54 74 VOL Output LOW Voltage 54 74 IOZH IOZL IIH Output Off Current HIGH Output Off Current LOW Input HIGH Current 2.5 7.5 V VCC = MAX NOTES: 1.0 2.5 V VOUT = GND VCC = MAX VCC = MAX VCC = MAX VCC = 0 V VCC = MAX VCC = MAX VCC = MIN VCC = 4.0 7.5 8.0 mA IOH = –12 mA IOH = –15 mA IOL = 48 mA IOL = 64 mA VOUT = 2.MC54/74F367 • MC54/74F368 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54.5 1.0 1.5 9.5 4.5 3.0 mA IOH = –3.5 1.0 2.55 0.0 V ± 10% CL = 50 pF Min 2.0 Max 6.0 7.5 V VCC = 4.4 Min 2.2 Typ Max Unit V V V V V V V V V µA µA µA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –3. nor for more than 1 second.0 2. Not more than one output should be shorted at a time.4 2.5 Max 8.55 50 –50 20 100 IIL IOS Input LOW Current Output Short Circuit Current (Note 2) ICCH F367 ICCL ICCZ ICC F368 ICCH ICCL ICCZ –100 –20 –225 35 62 48 25 62 48 mA VCC = MAX µA mA 3.0 6.0 5.5 5.5 5. For conditions shown as MIN or MAX.7 V VIN = 7.5 1.0 V VIN = 0. use the appropriate value specified under recommended operating conditions for the applicable device type. 2.0 0.5 6. AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 3.0 8.0 3.5 5.5 Max 7.0 6.0 2.0 2.0 0.35 0.5 5.5 V VIN = 2.0 2.

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL • Eight Latches in a Single Package • 3-State Outputs for Bus Interfacing • ESD > 4000 Volts CONNECTION DIAGRAM (TOP VIEW) VCC 20 O7 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 LE 11 20 1 J SUFFIX CERAMIC CASE 732-03 N SUFFIX PLASTIC CASE 738-03 20 1 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND 20 LOGIC SYMBOL 3 4 7 8 13 14 17 18 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 11 1 D0 D1 D2 D3 D4 D5 D6 D7 LE OE O0 O1 O2 O3 O4 O5 O6 O7 2 5 6 9 12 15 16 19 VCC = PIN 20 GND = PIN 10 GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.MC54/74F373 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS The MC54/74F373 consists of eight latches with 3-state outputs for bus organized system applications.0 24 mA mA Unit V °C FAST AND LS TTL DATA 4-167 . 74 Min 4. Data appears on the bus when the Output Enable (OE) is LOW.0 25 25 Max 5. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH.5 125 70 –3. When LE is LOW. 74 54 74 IOH IOL Output Current — HIGH Output Current — LOW 54. 74 54. When OE is HIGH the bus output is in the high impedance state.5 –55 0 Typ 5. the data that meets the setup times is latched.

e. use the appropriate value specified under recommended operating conditions for the applicable device type. 2.5 V VOUT = 0 V OE = 4.7 3.0 V VIN = 0.4 2. In this condition the latches are transparent.0 mA IOL = 24 mA VOUT = 2. Not more than one output should be shorted at a time..35 0. When (OE) is LOW.3 3. i.8 –1.7 V VIN = 7. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.0 0.5 V VIN = 2. For conditions shown as MIN or MAX. When OE is HIGH the buffers are in the high impedance mode.2 Typ Max Unit V V V V V V µA µA µA µA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = – 3.7 V VOUT = 0. but this does not interfere with entering new data into the latches.5 50 –50 20 100 IIL IOS ICCZ Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current (All Outputs OFF) –60 35 –0.0 mA IOH = – 3. When LE is LOW the latches store the information that was present on the D inputs one setup time preceding the HIGH-to-LOW transition of LE.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX NOTES: 1. FAST AND LS TTL DATA 4-168 . 74 74 VOL IOZH IOZL IIH Output LOW Voltage Output OFF Current — HIGH Output OFF Current — LOW Input HIGH Current 2. When the Latch Enable (LE) input is HIGH. a latch output will change state each time its D input changes. LOGIC DIAGRAM D0 D GO LE D1 D GO D2 D GO D3 D GO D4 D GO D5 D GO D6 D GO D7 D GO OE O0 O1 O2 O3 O4 O5 O6 O7 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.MC54/74F373 FUNCTIONAL DESCRIPTION The F373 contains eight D-type latches with 3-state output buffers.5 V VCC = 4.3 0. the buffers are in the bi-state mode. The 3-state buffers are controlled by the Output Enable (OE) input.5 V Dn. nor for more than 1 second.6 –150 55 Min 2. data on the Dn inputs enters the latches. LE = GND VCC = MIN VCC = 4.

5 1. HIGH Min 2.0 6.7 9.MC54/74F373 AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5. HIGH or LOW Dn to LE Hold Time.0 5.0 3.8 Max 7.6 4.0 54F TA = –55°C to +125°C VCC = 5.5 7.0 Typ Max 54F TA = –55°C to +125°C VCC = 5.0 3.0 13 8.0 2. HIGH or LOW Dn to LE LE Pulse Width.0 1.0 1.0 2.5 Typ 5.0 5.5 Max 8.0 6.0 6.5 1.5 1.0 6.0 5.0 12 8.0 2.5 13.0 2.0 2.0 5.0 11.0 V ± 10% CL = 50 pF Min 3.5 6.0 5.0 3.0 74F TA = 0°C to +70°C VCC = 5.0 3.0 2.5 10 10 7.0 2.5 6.0 ns ns ns Unit ns AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = +5.3 3.0 3.0 V Symbol ts(H) ts(L) th(H) th(L) tw(H) Parameter Setup Time.0 3.0 3.0 3.0 11 7.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Parameter Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time Min 3.0 2.5 7.5 3.0 2.5 Max 8.0 ns ns Max Unit FAST AND LS TTL DATA 4-169 .0 2.0 5.0 V ± 10% Min 2.5 6.0 1.0 V ± 10% Min 2.0 15 8.5 7.0 V ± 10% CL = 50 pF Min 3.0 Max 74F TA = 0°C to +70°C VCC = 5.0 3.0 2.2 5.0 2.

MC54/74F374 OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS The MC54/74F374 is a high-speed. OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL • • • • Edge-triggered D-Type Inputs Buffered Positive Edge-triggered Clock 3-State Outputs for Bus-Oriented Applications ESD > 4000 Volts CONNECTION DIAGRAM (TOP VIEW) VCC 20 O7 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 CP 11 20 1 J SUFFIX CERAMIC CASE 732-03 N SUFFIX PLASTIC CASE 738-03 20 1 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND 20 FUNCTION TABLE Inputs Dn H L X H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance 1 DW SUFFIX SOIC CASE 751D-03 Outputs CP OE L L X H On H L Z ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC LOGIC SYMBOL 3 4 7 8 13 14 17 18 11 1 D0 D1 D2 D3 D4 D5 D6 D7 CP OE O0 O1 O2 O3 O4 O5 O6 O7 2 5 6 9 12 15 16 19 VCC = PIN 20 GND = PIN 10 FAST AND LS TTL DATA 4-170 . A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.

the outputs go to the high impedance state.6 –150 86 Min 2.5 V VCC = 4.2 Typ Max Unit V V V V V V µA µA µA µA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = – 3.7 V VIN = 7. Not more than one output should be shorted at a time.0 mA IOL = 24 mA VOUT = 2. 2.3 3. With the Output Enable (OE) LOW.7 V VOUT = 0. LOGIC DIAGRAM D0 CP CP D Q Q D1 D2 D3 D4 D5 D6 D7 CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q OE O0 O1 O2 O3 O4 O5 O6 O7 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54. use the appropriate value specified under recommended operating conditions for the applicable device type.5 50 –50 20 100 IIL IOS ICCZ Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current (All Outputs OFF) –60 55 –0.8 –1. VCC = MIN VCC = 4. Operation of the OE input does not affect the state of the flip-flops.3 0.5 V NOTES: 1. The buffered clock and buffered Output Enable are common to all flip-flops. = GND OE = 4.0 mA IOH = – 3.0 V VIN = 0.7 3. For conditions shown as MIN or MAX. nor for more than 1 second.4 2.35 0. the contents of the eight flip-flops are available at the outputs.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX FAST AND LS TTL DATA 4-171 .MC54/74F374 FUNCTIONAL DESCRIPTION The F374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-state true outputs. When the OE is HIGH.0 0.5 V VIN = 2.5 V VOUT = 0 V Dn. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. 74 74 VOL IOZH IOZL IIH Output LOW Voltage Output OFF Current — HIGH Output OFF Current — LOW Input HIGH Current 2.

5 8.0 6. 74 54 74 IOH IOL Output Current — HIGH Output Current — LOW 54.0 10.0 7.0 4. 74 Min 4.0 5.0 2.0 V ± 10% Min 2.5 11 14 10 8.0 6.0 2.0 2.0 2.0 V Symbol ts (H) ts (L) th (H) th (L) tw (H) tw (L) Parameter Setup Time.5 7.5 ns ns Max Unit MHz ns AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = +5.0 7.0 2.0 4.0 5.0 2.0 2.0 2.0 ns ns Max Unit FAST AND LS TTL DATA 4-172 .0 2.0 24 mA mA Unit V °C AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 2.5 –55 0 Typ 5.0 4.5 8.8 5.5 Typ Max 54F TA = –55°C to +125°C VCC = 5.0 25 25 Max 5.0 V ± 10% CL = 50 pF Min 70 4.0 6.MC54/74F374 GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.0 V ± 10% Min 2.3 4.0 2.0 2.5 9. HIGH or LOW Dn to CP CP Pulse Width.0 Max 74F TA = 0°C to +70°C VCC = 5.5 7.0 10 10 12. HIGH or LOW Dn to CP Hold Time.0 2.5 7.5 8.0 Typ Max 54F TA = –55°C to +125°C VCC = 5.0 V CL = 50 pF Symbol fmax tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Parameter Maximum Clock Frequency Propagation Delay CP to On Output Enable Time Min 100 4.0 V ± 10% CL = 50 pF Min 60 4. 74 54.5 Max 74F TA = 0°C to +70°C VCC = 5.0 2.5 6.0 7.0 2.0 6.5 125 70 –3. HIGH or LOW Min 2.5 2.5 11.0 2.0 2.0 2.0 6.0 2.0 2.3 8.

The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is LOW. l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition. ↑ = LOW-to-HIGH clock transition FAST AND LS TTL DATA 4-173 . The register consists of eight D-Type Flip-Flops with individual D inputs and Q outputs.MC74F377 OCTAL D FLIP-FLOP WITH ENABLE The MC74F377 is a high-speed 8-Bit Register. h = HIGH voltage level one setup time prior to the LOW-to-HIGH Clock transition. • High Impedance NPN Base Inputs for Reduced Loading (20 µA in • • • • • HIGH and LOW States) Ideal for Addressable Register Applications Enable for Address and Data Synchronization Applications Eight Edge-Triggered D Flip-Flops Buffered Common Clock See: MC74F373 for Transparent Latch Version MC74F374 for 3-State Version OCTAL D FLIP-FLOP WITH ENABLE FAST™ SCHOTTKY TTL 20 1 J SUFFIX CERAMIC CASE 732-03 CONNECTION DIAGRAM (TOP VIEW) VCC 20 Q7 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 13 Q4 12 CP 11 20 1 N SUFFIX PLASTIC CASE 738-03 20 1 E 2 Q0 3 D0 4 D1 5 Q1 6 Q2 7 D2 8 D3 9 Q3 10 GND 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC FUNCTION TABLE Inputs Operating Mode Load “1” Load “0” Hold (do nothing) CP ↑ ↑ ↑ X E l l h H Dn h l X X Outputs Qn H L No Change No Change H = HIGH voltage level steady state. L = LOW voltage level steady state. This device is supplied in a 20-pin package. X = Don’t Care.

0 0.35 0. The register is fully edge-triggered.7 0. For conditions shown as MIN or MAX.5 9. CP = ↑ Min 2.0 4.0 Typ 120 6.5 7.0 V ± 10% CL = 50 pF Min 100 4. AC ELECTRICAL CHARACTERISTICS 74F TA = +25°C VCC = +5.5 0 Typ 5.0 25 Max 5.7 V VIN = 0. The E input must be stable one setup time prior to the LOWto-HIGH clock transition for predictable operation.5 2. when the Enable (E) is LOW. The common buffered Clock (CP) input loads all flip-flops simultaneously. use the appropriate value specified under recommended operating conditions for the applicable device type.MC74F377 FUNCTIONAL DESCRIPTION The MC74F377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs.5 V VCC = 4.5 V.7 VOL IIH IIL IOS ICC Output LOW Voltage Input HIGH Current Input LOW Current Output Short Circuit Current (Note 2) Total Supply Current –60 ICCH ICCL 55 70 2. 2. nor for more than 1 second.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MAX NOTES: 1. is transferred to the corresponding flip-flop’s Q output.0 mA VCC = MIN VCC = 4.5 V VOUT = 0 V Dn = 4.5 2.0 8. Not more than one output should be shorted at a time. CP = ↑. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — HIGH Output Current — LOW Parameter 74 74 74 74 Min 4.0 V CL = 50 pF Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay CP to Qn Min 110 4. The state of each D input.5 70 –1.5 20 –20 –150 72 90 V µA µA mA mA mA IOL = 20 mA VIN = 2.8 –1. E = GND Dn = E = GND.0 Max 74F TA = 0 to +70°C VCC = 5.5 Max Unit MHz ns FAST AND LS TTL DATA 4-174 .0 4.0 10 10.0 20 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. one setup time before the LOW-to-HIGH clock transition.

0 1.0 1.0 5.MC74F377 LOGIC DIAGRAM D0 (3) E (1) D1 (4) D2 (7) D3 (8) D4 (13) D5 (14) D6 (17) D7 (18) D CP v Q D CP v Q D CP v Q D CP v Q D CP v Q D CP v Q D CP v Q D CP v Q (11) CP (2) Q0 VCC = PIN 20 GND = PIN 10 (5) Q1 (6) Q2 (9) Q3 (12) Q4 (15) Q5 (16) Q6 (19) Q7 AC OPERATING REQUIREMENTS 74F TA = +25°C VCC = 5.0 0 0 4.0 V ± 10% CL = 50 pF Typ Max Unit ns FAST AND LS TTL DATA 4-175 . HIGH or LOW Dn to CP Hold Time.5 4. HIGH or LOW Dn to CP Setup Time. HIGH or LOW E to CP Hold Time.0 4.0 Typ Max Min 3.0 ns ns ns ns 74F TA = 0°C to +70°C VCC = 5.0 0 0 5.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Setup Time.0 3.0 2.0 1.0 3.0 2.0 1. HIGH or LOW E to CP Clock Pulse Width HIGH or LOW Min 3.5 4.

PARALLEL D REGISTER WITH ENABLE FAST™ SCHOTTKY TTL • • • • 6-Bit High-Speed Parallel Register Positive Edge-Triggered D-Type Inputs Fully Buffered Common Clock and Enable Inputs Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM (TOP VIEW) VCC 16 Q5 15 D5 14 D4 13 Q4 12 D3 11 Q3 10 CP 9 J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 1 E 2 Q0 3 D0 4 D1 5 Q1 6 D2 7 Q2 8 GND ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC FUNCTION TABLE Inputs E H L L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance Output Dn X H L Qn No Change H L CP LOGIC SYMBOL 14 13 11 6 4 3 1 D5 D4 D3 D2 D1 D0 E Q5 Q4 Q3 Q2 Q1 Q0 CP 9 15 12 10 7 5 2 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-176 . The F378 consists of six edge-triggered D-type flip-flops with individual D inputs and Q outputs. new data is entered into the register on the LOWto-HIGH transition of the CP input. The Clock (CP) and Enable (E) inputs are common to all flip-flops. When the E input is LOW.. This device is similar to the F174 but with common Enable rather than common Master Reset. This circuit is designed to prevent false clocking by transitions on the E input. When the E input is HIGH the register will retain the present data independent of the CP input.MC54/74F378 PARALLEL D REGISTER WITH ENABLE The MC54/74F378 is a 6-bit register with a buffered common enable.

74 54.5 2.75 V VCC = MIN VCC = MAX.5 20 0.5 –55 0 Typ 5. 2.8 –1.0 0. VIN = 7.5 125 70 –1. 74 Min 4. Not more than one output should be shorted at a time. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.6 –150 45 Min 2. For conditions shown as MIN or MAX.0 20 mA mA Unit V °C DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.7 V VCC = MAX.0 V VCC = MAX. 74 54 74 IOH IOL Output Current — HIGH Output Current — LOW 54.0 mA IOL = 20 mA VCC = 4. VOUT = 0 V VCC = MAX.50 V VCC = 4.7 0. VCP = 0 V NOTES: 1.MC54/74F378 LOGIC DIAGRAM D0 CP D1 D2 D3 D4 D5 CP E D Q CP E D Q CP E D Q CP E D Q CP E D Q CP E D Q E Q0 Q1 Q2 Q3 Q4 Q5 GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current – 60 30 –0.0 25 25 Max 5.0 mA IOL = – 1. VIN = 2. VIN = 0.2 Typ Max Unit V V V V V V µA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN. FAST AND LS TTL DATA 4-177 . IIN = –18 mA IOL = – 1. nor for more than 1 second. use the appropriate value specified under recommended operating conditions for the applicable device type.5 V VCC = MAX.

0 2.0 max 74F TA = 0°C to +70°C VCC = 5.0 2.0 4.0 0 0 6.0 ns 2.0 6.5 8.0 2.0 V Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Setup Time.0 0 0 6.0 3.0 2.0 3. HIGH or LOW E to CP Hold Time.0 6.5 Max Unit MHz ns AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = 5.0 7.MC54/74F378 AC CHARACTERISTICS 54/74F TA = +25°C VCC = 5.5 Max 54F TA = –55°C to +125°C VCC = 5. HIGH or LOW Dn to CP Setup Time.5 9.5 9.0 4.0 V ± 10% Min 4.0 4.0 6.0 4.0 V ± 10% CL = 50 pF Min 80 3.0 0 0 6.5 Typ 140 5.0 6.0 V ± 10% CL = 50 pF Min 80 3.5 Max 74F TA = 0°C to +70°C VCC = 5. HIGH or LOW Dn to CP Hold Time. HIGH or LOW E to CP CP Pulse Width.0 4.5 8.0 V CL = 50 pF Symbol fmax tPLH tPHL Parameter Maximum Input Frequency Propagation Delay CP to Qn Min 80 3.0 4.0 ns ns Max Unit FAST AND LS TTL DATA 4-178 .0 Typ Max 54F TA = –55°C to +125°C VCC = 5.5 10.0 V ± 10% Min 4.0 3. HIGH or LOW Min 4.0 6.5 6.0 2.0 6.

The Dn and E inputs can change when the clock is in either state. provided that the recommended setup and hold times are observed. This device is similar to the F175 but features the common Enable rather than common Master Reset. QUAD PARALLEL REGISTER WITH ENABLE FAST™ SCHOTTKY TTL • • • • Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Buffered Common Enable Input True and Complement Outputs CONNECTION DIAGRAM (TOP VIEW) VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 1 E 2 Q0 3 Q0 4 D0 5 D1 6 Q1 7 Q1 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 FUNCTION TABLE Inputs E H L L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care NC = No Change ORDERING INFORMATION Outputs Dn X H L Qn NC H L Qn NC L H 13 12 5 4 1 MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC CP LOGIC SYMBOL Q3 Q2 Q1 Q0 15 14 10 11 7 6 2 3 D3 D2 D1 D0 E 9 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-179 . the register will retain the present data independent of the CP input. When E is HIGH. The Clock (CP) and Enable (E) inputs are common to all flip-flops. This circuit is designed to prevent false clocking by transitions on the E input. The F379 consists of four edge-triggered D-type flip-flops with individual D inputs and Q and Q outputs.MC54/74F379 QUAD PARALLEL REGISTER The MC54/74F379 is a 4-bit register with a buffered common enable.

74 Min 4. use the appropriate value specified under recommended operating conditions for the applicable device type.5 125 70 –1.75 V VCC = MIN VCC = MAX.0 25 25 Max 5. 74 54. CP = NOTES: 1. D = E = GND.1 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current –60 28 –0. 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.7 V VCC = MAX.0 V VCC = MAX. VIN = 2.5 V VCC = 4.5 2. VIN = 7.0 mA IOL = – 1.5 V VCC = MAX.7 0. 74 54 74 IOH IOL Output Current — HIGH Output Current — LOW 54.5 –55 0 Typ 5. 2. IIN = – 18 mA IOL = – 1. Not more than one output should be shorted at a time. VOUT = 0 V VCC = MAX. VIN = 0.0 mA IOL = 20 mA VCC = 4.MC54/74F379 LOGIC DIAGRAM D0 CP CP E Q E Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q D E Q Q CP D E Q Q CP D E Q Q CP D D1 D2 D3 GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54. For conditions shown as MIN or MAX.8 –1.0 20 mA mA Unit V °C DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.2 Typ Max Unit V V V V V V µA mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN. FAST AND LS TTL DATA 4-180 .0 0. nor for more than 1 second.6 –150 40 Min 2.5 20 0.

0 2.0 6.0 Typ Max 54F TA = –55°C to +125°C VCC = 5.0 6.5 5.0 V CL = 50 pF Symbol fmax tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay CP to Qn. HIGH or LOW Dn to CP Hold Time. HIGH or LOW Min 3.0 V ± 10% Min 3.0 V Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Setup Time.0 8.5 8.0 4. Qn Min 100 3.0 4.0 2.5 Max 74F TA = 0°C to +70°C VCC = 5.5 5.0 5.MC54/74F379 AC CHARACTERISTICS 54/74F TA = +25°C VCC = 5.0 max 74F TA = 0°C to +70°C VCC = 5.0 1.5 5.0 1.0 3.0 V ± 10% CL = 50 pF Min 90 3.0 ns 2. HIGH or LOW E to CP CP Pulse Width. HIGH or LOW Dn to CP Setup Time.0 3.0 6.0 2.0 2.5 Max Unit MHz ns AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = 5.0 1.0 6.0 1.0 1.0 6.0 V ± 10% CL = 50 pF Min 100 3.0 7.0 5.0 1.0 4.0 5.0 Typ 140 5.0 6.0 ns ns Max Unit FAST AND LS TTL DATA 4-181 . HIGH or LOW E to CP Hold Time.5 6.5 9.0 6.0 V ± 10% Min 3.5 10.5 Max 54F TA = –55°C to +125°C VCC = 5.0 3.0 2.

5 125 Unit V °C mA mA FAST AND LS TTL DATA 4-182 .5 – 55 Typ 5. 4-BIT ARITHMETIC LOGIC UNIT FAST™ SCHOTTKY TTL • • • • Low Input Loading Minimizes Drive Requirements Performs Six Arithmetic and Logic Functions Selectable Low (Clear) and High (Preset) Functions Carry Generate and Propagate Outputs for use with Carry Lookahead Generator CONNECTION DIAGRAM VCC A2 20 19 B2 18 A3 17 B3 16 Cn 15 P 14 G 13 F3 12 F2 11 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 1 A1 2 B1 3 A0 4 B0 5 S0 6 S1 7 S2 8 F0 9 F1 10 GND 20 LOGIC SYMBOL 3 4 1 2 19 18 17 16 A0 B0 A1 B1 A2 B2 A3 B3 15 7 6 5 Cn S2 S1 S0 G P F0 8 F1 9 F2 11 F3 12 13 14 VCC = PIN 20 GND = PIN 10 DW SUFFIX SOIC CASE 751D-03 1 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current — High Output Current — Low 54. 74 54. 74 0 25 70 – 1. refer to the F382 ALU data sheet.0 20 Parameter 54. 74 54 Min 4. A and B.MC54/74F381 4-BIT ARITHMETIC LOGIC UNIT The MC54/74F381 performs three arithmetic and three logic operations on two 4-bit words. Two additional Select input codes force the Function outputs LOW or HIGH. Carry Propagate and Generate outputs are provided for use with the F182 Carry Lookahead Generator for high-speed expansion to longer word lengths.0 25 Max 5. For ripple expansion.

MC54/74F381 LOGIC DIAGRAM Cn B0 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. F0 A0 B1 F1 A1 B2 F2 A2 B3 F3 A3 P F381 ONLY S0 G OVR S1 Cn+4 F382 ONLY S2 FAST AND LS TTL DATA 4-183 .

nor for more than 1 second. An extensive listing of input and output levels is shown in the Truth Table. with output levels in the same convention. as shown in Figure 1.5 V VIN = 0. LOW for active-LOW operands) into the Cn input of the least significant package. it is necessary to force a carry (HIGH for active-HIGH operands.35 0. FUNCTION SELECT TABLE Select S0 L H L H L H L H S1 L L H H L L H H S2 L L L L H H H H Operation Clear B Minus A A Minus B A Plus B A⊕B A+B AB Preset H = HIGH Voltage Level L = LOW Voltage Level FAST AND LS TTL DATA 4-184 . Other Inputs HIGH VCC = MAX VCC = MAX VCC = MIN VCC = 4.0 mA IOH = –1. Note that an F382 ALU is used for the most significant package.5 20 V V µA µA mA mA mA mA 2. 2.6 – 2.0 mA IOL = 20 mA VIN = 2. The Carry Generate (G) and Carry Propagate (P) outputs supply input signals to the F182 carry lookahead generator for expansion to longer word length.5 3. FUNCTIONAL DESCRIPTION Signals applied to the Select inputs S0–S2 determine the mode of operation.7 3.0 V VIN = 0.4 0.5 V VCC = 4. as indicated in the Function Select Table.4 Min 2.MC54/74F381 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54. 74 Output HIGH Voltage 74 Output LOW Voltage Input HIGH Current 100 Input LOW Current S0–S2 Inputs Other Inputs IOS ICC Output Short Circuit Current (Note 2) Power Supply Current –60 59 – 0.5 V VOUT = 0 V S0–S2 = GND. For conditions such as MIN or MAX.4 –150 89 2. The circuit performs the arithmetic functions for either active-HIGH or active-LOW operands. In the Subtract operating modes.8 –1.0 0. Typical delays for Figure 1 are given in Figure 2.7 V VIN = 7.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1. Not more than one output should be shorted at a time.75 V VCC = MIN VCC = MAX IIL VCC = MAX NOTES: 1. use the appropriate value specified under guaranteed operating ranges.

5 4.2 ns 6.5 74F TA = 0 to +70°C VCC = 5.2 6.0 2.3 8.5 2.2 ns 6.0 3. OVR 7.0 4.5 13 14.5 Unit ns ns ns ns ns ns FAST AND LS TTL DATA 4-185 .5 3.0 4.8 10.5 12 13.5 12.5 4.5 4.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Cn to Fi Propagation Delay Any A or B to Any F Propagation Si to Fi Propagation Delay Ai or Bi to G Propagation Delay Ai or Bi to P Propagation Delay Si to G or P Min 2.2 8.4 ns Figure 2.5 Typ 8.0 4.5 9.5 ns Output p Cn + 4.5 4.2 ns — 8. OVR Total Delay Toward F 7.8 7.5 16 12 13 13.0 4.5 4.0 15 11 20 13 9.2 6.5 4.MC54/74F381 A0–A3 4 CIN 3 SELECT 3 F0–F3 G0 P0 Cn Cn+z F4–F7 G1 P1 Cn+y F8–F11 G2 P2 Cn+z F12–F15 A B Cn F381 S F G P 3 B0–B3 4 A4–A7 4 A B Cn F381 S F G P 3 B4–B7 4 A8–A11 B8–B11 4 A B Cn F381 S F G P 3 4 A12–A15 B12–B15 4 4 COUT OVERFLOW A B Cn Cn+4 F382 S OVR F F182 CLA Figure 1.0 V ±10% CL = 50 pF Min 2.5 10.0 3.5 14 10 11 11.0 ns 21.2 Max 12 8.5 15 16.5 2.5 54F TA = – 55 to +125°C VCC = 5.5 4.0 2.0 4. 16-Bit Lookahead Carry ALU Expansion Path Segment Ai or Bi to P Pi to Cn + j (’F182) Cn to F Cn to Cn + 4 .5 3.5 4.5 3. 16-Bit Delay Tabulation AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.4 8.7 10.0 3.5 Max 15 11 18 14 23.4 6.0 3.5 4.5 7.5 4.1 5.0 3.2 ns 8.0 2.5 4.1 ns — 21.5 Max 13 9.5 4.0 10 10.0 4.0 16 12 21.0 3.0 V ±10% CL = 50 pF Min 2.5 2.

MC54/74F381 TRUTH TABLE INPUTS FUNCTION CLEAR S0 0 S1 0 S2 0 Cn X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X An X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bn X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F0 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 1 1 1 F1 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 1 1 1 OUTPUTS F2 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 1 1 1 F3 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 1 1 1 G 0 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 P 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 B MINUS A 1 0 0 A MINUS B 0 1 0 A PLUS B 1 1 0 A⊕B 0 0 1 A+B 1 0 1 AB 0 1 1 PRESET 1 1 1 1 = HIGH Voltage Level 0 = LOW Voltage Level X = Immaterial FAST AND LS TTL DATA 4-186 .

For high-speed expansion using a Carry Lookahead Generator.0 20 Parameter 54. 4-BIT ARITHMETIC LOGIC UNIT FAST™ SCHOTTKY TTL • • • • • Performs Six Arithmetic and Logic Functions Selectable Low (Clear) and High (Preset) Functions LOW Input Loading Minimizes Drive Requirements Carry Output for Ripple Expansion Overflow Output for Twos Complement Arithmetic CONNECTION DIAGRAM VCC A2 20 19 B2 18 A3 17 B3 16 Cn Cn+4 OVR F3 15 14 13 12 F2 11 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 1 A1 2 B1 3 A0 4 B0 5 S0 6 S1 7 S2 8 F0 9 F1 10 GND 20 LOGIC SYMBOL 3 4 1 2 19 18 17 16 DW SUFFIX SOIC CASE 751D-03 1 A0 B0 A1 B1 A2 B2 A3 B3 15 7 6 5 Cn S2 S1 S0 Cn+4 OVR F0 8 F1 9 F2 11 F3 12 14 13 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current — High Output Current — Low 54.5 – 55 Typ 5. 74 54. A and B. An Overflow output is provided for convenience in twos complement arithmetic. 74 54 Min 4. 74 0 25 70 –1.MC54/74F382 4-BIT ARITHMETIC LOGIC UNIT The MC54/74F382 performs three arithmetic and three logic operations on two 4-bit words. refer to the F381 data sheet. A Carry output is provided for ripple expansion.0 25 Max 5. Two additional Select input codes force the Function outputs LOW or HIGH.5 125 Unit V °C mA mA FAST AND LS TTL DATA 4-187 .

F0 A0 B1 F1 A1 B2 F2 A2 B3 F3 A3 P F381 ONLY S0 G OVR S1 Cn+4 F382 ONLY S2 FAST AND LS TTL DATA 4-188 .MC54/74F382 LOGIC DIAGRAM Cn B0 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

MC54/74F382 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54. The circuit performs the arithmetic functions for either active HIGH or active LOW operands. In the Subtract operating modes. 74 Output HIGH Voltage 74 Output LOW Voltage Input HIGH Current 100 Input LOW Current S0–S2 Inputs IIL Other Inputs Cn Input IOS ICC Output Short Circuit Current (Note 2) Power Supply Current – 60 54 – 0.5 20 V V µA µA mA mA mA mA mA VOUT = 0 V S0. For conditions such as MIN or MAX.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –1. it is necessary to force a carry (HIGH for active HIGH operands.5 V VCC = 4. a HIGH signal on OVR indicates overflow in twos complement operation.0 –150 81 2. as indicated in the Function Select Table.7 V VIN = 7.5 3.0 0. use the appropriate value specified under guaranteed operating ranges.4 Min 2. Ripple expansion is illustrated in Figure 1.5 V 05 VCC = MAX 2. Not more than one output should be shorted at a time.4 – 3. An extensive listing of input and output levels is shown in the Truth Table. with output levels in the same convention.35 0. FUNCTIONAL DESCRIPTION Signals applied to the Select inputs S0–S2 determine the mode of operation. LOW for active LOW operands) into the Cn input of the least significant package.75 V VCC = MIN VCC = MAX NOTES: 1. nor for more than 1 second. The overflow output OVR is the Exclusive-OR of Cn + 3 and Cn+4. Other Inputs GND VCC = MAX VCC = MAX VIN = 0. FUNCTION SELECT TABLE Select S0 L H L H L H L H S1 L L H H L L H H S2 L L L L H H H H Operation Clear B Minus A A Minus B A Plus B A⊕B A+B AB Preset L = LOW Voltage Level H = HIGH Voltage Level FAST AND LS TTL DATA 4-189 .0 mA IOH = –1. Cn = HIGH.0 V VCC = MIN VCC = 4.7 3.4 0. Typical delays for Figure 1 are given in Figure 2.8 –1.6 – 2. 2.0 mA IOL = 20 mA VIN = 2.

0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Cn to Fi Propagation Delay Any A or B to Any F Propagation Delay Si to Fi Propagation Delay Ai or Bi to Cn + 4 Propagation Delay Si to OVR or Cn + 4 Propagation Delay Cn to Cn + 4 Propagation Delay Cn to OVR Propagation Delay Ai or Bi to OVR Min 3.3 ns 6.6 6.7 10.3 8.5 3.5 13.5 54F TA = –55 to +125°C VCC = 5.4 8.0 2.5 5.1 ns Figure 2.0 3.5 17.5 8.0 6.0 4.0 9.5 8.0 16.5 5.5 3.0 3.5 11.5 3.0 3.5 3.0 3.1 5.0 7.0 3.5 9.5 10.5 4.1 11.5 3. 16-Bit Ripple Carry ALU Expansion Path Segment Ai or Bi to Cn + 4 Cn to Cn + 4 Cn to Cn + 4 Cn to F Cn to Cn + 4.5 9.5 4.2 ns Output p Cn + 4.0 V ±10% CL = 50 pF Min 3.2 11 8. 16-Bit Delay Tabulation AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.3 ns — 8.5 2.5 19.5 3.1 — 27.2 6.0 16 12 16 21.0 10 12 11 16.5 3.MC54/74F382 A0–A3 4 Cin 3 B0–B3 4 A4–A7 4 B4–B7 4 A8–A11 B8–B11 4 4 A12–A15 B12–B15 4 4 Cout OVERFLOW A B Cn Cn+4 F382 S 3 3 A B Cn Cn+4 F382 S 3 A B Cn Cn+4 F382 S 3 A B Cn Cn+4 F382 S OVR SELECT F0–F3 F4–F7 F8–F11 F12–F15 Figure 1.5 74F TA = 0 to 70°C VCC = 5.5 Max 13 9.0 3.0 ns 27.5 9.0 4. OVR Total Delay Toward F 6.5 6.0 4.5 10.5 12 8.0 11 10 15.5 ns 6.3 ns 8.5 5.5 2.5 2.5 4.0 4.5 3.5 11.5 Unit ns ns ns ns ns ns ns ns FAST AND LS TTL DATA 4-190 .5 ns 6.0 7.0 7.5 Typ 8.5 12.0 2.5 15 11 12 14 13 18.5 2.0 4.0 5.5 3.0 4.3 ns 6.0 2.5 6.0 15 11 15 20.5 6.5 12.5 6.5 13 9.5 2.0 V ±10% CL = 50 pF Min 3.5 2.5 Max 15 11 18 14 21 23.5 6. OVR 6.5 6.0 7.0 Max 12 8.

MC54/74F382 TRUTH TABLE INPUTS Function CLEAR S0 0 S1 0 S2 0 Cn 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X 0 X 1 X X X 0 1 X X X 0 1 X X X 0 1 An X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1 Bn X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 F0 0 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 F1 0 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 F2 0 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 OUTPUTS F3 0 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 OVR 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 Cn + 4 1 1 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 B MINUS A 1 0 0 A MINUS B 0 1 0 A PLUS B 1 1 0 A⊕B 0 0 1 A+B 1 0 1 AB 0 1 1 PRESET 1 1 1 1 = HIGH Voltage Level 0 = LOW Voltage Level X = Immaterial FAST AND LS TTL DATA 4-191 .

• Select Inputs from Two Data Sources • Fully Positive Edge-Triggered Operation • Both True and Complement Outputs CONNECTION DIAGRAM (TOP VIEW) VCC 20 Qd 19 Qd 18 I0d 17 I1d 16 I1c 15 I0c 14 Qc 13 Qc 12 CP 11 20 QUAD 2-PORT REGISTER FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 732-03 1 1 S 2 Qa 3 Qa 4 I0a 5 I1a 6 I1b 7 I0b 8 Qb 9 Qb 10 GND 20 1 N SUFFIX PLASTIC CASE 738-03 LOGIC DIAGRAM 20 I0a S I1a D CP Qa Qa DW SUFFIX SOIC CASE 751D-03 1 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC I0b D I1b CP Qb Qb LOGIC SYMBOL I0c D I1c CP Qc Qc 1 I0d D I1d CP Qd Qd 11 S CP I0a I1a I0b I1b I0c I1c I0d I1d 4 5 7 6 14 15 17 16 Qa Qa Qb Qb Qc Qc Qd Qd 2 3 9 8 12 13 19 18 CP NOTES: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flipflops on the rising edge of the clock. VCC = PIN 20 GND = PIN 10 FAST AND LS TTL DATA 4-192 .MC54/74F398 QUAD 2-PORT REGISTER The MC54/74F398 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops.

74 74 VOL IIH Output LOW Voltage Input HIGH Current 2. one setup time prior to the LOW-to-HIGH clock transition X = Don’t Care GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.5 20 100 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current –60 25 –0. FAST AND LS TTL DATA 4-193 .0 mA IOL = 20 mA VIN = 2. It will select four bits of data from either of two sources (Ports) under control of a common Select input (S).5 2.35 0.0 20 mA mA Unit V °C DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 –55 0 Typ 5.5 V VCC = 4. 74 54. H = HIGH Voltage Level L = LOW Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition I = LOW Voltage Level.7 V VIN = 7. For conditions shown as MIN or MAX. 2.6 –150 38 Min 2.0 mA IOH = – 1.0 0.5 125 70 –1.8 –1.5 V VOUT = 0 V VCC = MAX VCC = MAX VCC = MAX VIN = GND CP = VCC = MIN VCC = 4.MC54/74F398 FUNCTIONAL DESCRIPTION The MC54/74F398 is a high-speed quad 2-port register.4 0.4 3. use the appropriate value specified under guaranteed operating ranges. The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP). I1x) and Select input (S) must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation. Not more than one output should be shorted at a time. nor for more than 1 second.75 V VCC = MIN VCC = MAX NOTES: 1.7 3. The Data inputs (I0x. The 4-bit DFUNCTION TABLE Inputs S I I h h I0 I h X X I1 X X I h Outputs Q L H L H Q H L H L type output register is fully edge-triggered. 74 54 74 IOH IOL Output Current – High Output Current – Low 54.2 Typ Max Unit V V V V V V µA µA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = – 1. The MC54/74F398 has both Q and Q outputs.0 25 25 Max 5. 74 Min 4.0 V VIN = 0.

HIGH or LOW In to CP Setup Time.0 3. HIGH or LOW S to CP CP Pulse Width HIGH or LOW Min 3.5 10.0 Typ Max 54F TA = –55°C to +125°C VCC = 5.5 11.0 V ±10% CL = 50 pF Min 80 3.0 1.0 3.0 V ±10% Min 4.0V Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Setup Time.0 Typ 140 5.5 1.5 Max 54F TA = –55°C to +125°C VCC = 5.0 7.5 0 0 4.0 9.0 8.5 0 0 4.0 7.0 3. HIGH or LOW In to CP Hold Time. HIGH or LOW S to CP Hold Time.5 1.0 1.7 6.0 1.0 V CL = 50 pF Symbol fmax tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay CP to Q or Q Min 100 3.5 8.0 5.5 Max 74F TA = –0°C to 70°C VCC = 5.8 7.0 V ±10% CL = 50 pF Min 100 3.MC54/74F398 AC CHARACTERISTICS 54/74F TA = + 25°C VCC = +5.0 3.0 V ±10% Min 3.0 Max 74F TA = –0°C to 70°C VCC = 5.0 8.0 ns ns ns ns Max Unit ns FAST AND LS TTL DATA 4-194 .0 3.5 9.5 4.0 5.0 Max Unit MHz ns AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = +5.0 1.5 10.5 0 0 4.5 7.5 10.

A common Select input determines which of the two 4-bit words is accepted.MC54/74F399 QUAD 2-PORT REGISTER The MC54/74F399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip flops. QUAD 2-PORT REGISTER FAST™ SCHOTTKY TTL • Select Inputs from Two Data Sources • Fully Positive Edge-Triggered Operation CONNECTION DIAGRAM (TOP VIEW) VCC 16 Qd 15 I0d 14 I1d 13 I1c 12 I0c 11 Qc 10 CP 9 J SUFFIX CERAMIC CASE 620-09 16 1 1 S 2 Qa 3 I0a 4 I1a 5 I1b 6 I0b 7 Qb 8 GND 16 1 N SUFFIX PLASTIC CASE 648-08 LOGIC DIAGRAM I0a S I1a D CP Qa 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC I0b D I1b CP Qb LOGIC SYMBOL I0c D I1c CP 1 D I1d CP 2 CP NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. with only the Q outputs of the flip-flops available. The selected data enters the flipflops on the rising edge of the clock. The MC54/74F399 is the 16-pin version of the MC54/74F398. Qc 3 4 6 5 11 12 14 13 I0d Qd S CP I0a I1a I0b I1b I0c I1c I0d I1d 9 Qa Qb 7 Qc 10 Qd 15 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-195 .

0 mA IOH = – 1. The 4-bit DFUNCTION TABLE Inputs S I I h h I0 I h X X I1 X X I h Output Q L H L H type output register is fully edge-triggered.35 0.7 3.0 V VIN = 0.2 Typ Max Unit V V V V V V µA µA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = – 1. nor for more than 1 second.4 3. 2.0 25 25 Max 5.0 0.75 V VCC = MIN VCC = MAX NOTES: 1. The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP). 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2. H = HIGH Voltage Level L = LOW Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Don’t Care GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.5 20 100 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current –60 22 –0.4 0.0 mA IOL = 20 mA VIN = 2.5 V VCC = 4.8 –1.5 2.6 –150 34 Min 2.5 125 70 – 1. I1x) and Select input (S) must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation. 74 54 74 IOH IOL Output Current  High Output Current  Low 54. use the appropriate value specified under guaranteed operating ranges.7 V VIN = 7. 74 54. FAST AND LS TTL DATA 4-196 . It will select four bits of data from either of two sources (Ports) under control of a common Select input (S). Not more than one output should be shorted at a time.0 20 mA mA Unit V °C DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.5 –55 0 Typ 5. 74 Min 4. The Data inputs (I0x. For conditions shown as MIN or MAX.5 V VOUT = 0 V VCC = MAX VCC = MAX VCC = MAX VIN = GND CP = VCC = MIN VCC = 4.MC54/74F399 FUNCTIONAL DESCRIPTION The MC54/74F398 is a high-speed quad 2-port register.

0 Max Unit MHz ns AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = +5.0 V ± 10% Min 4.0 5.0 V ± 10% CL = 50 pF Min 100 3.8 7.0 8.5 Max 54F TA = –55°C to +125°C VCC = 5.0 V ± 10% Min 3.0 3.5 10.0 5.0 7.0 1.5 1. HIGH or LOW S to CP Hold Time.5 1.5 11.5 4.5 0 0 4.0 V ± 10% CL = 50 pF Min 80 3.0 1.0 1.0 3.5 9.5 0 0 4.5 7.5 0 0 4.5 9.0 9.0 7.0 Max 74F TA = 0°C to 70°C VCC = 5. HIGH or LOW In to CP Setup Time.0 3.5 9.MC54/74F399 AC CHARACTERISTICS 54/74F TA = + 25°C VCC = +5.0V CL = 50 pF Symbol fmax tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay CP to Q Min 100 3.0 3.5 Max 74F TA = 0°C to 70°C VCC = 5.5 8. HIGH or LOW S to CP CP Pulse Width HIGH or LOW Min 3.0 8.0 Typ Max 54F TA = –55°C to + 125°C VCC = 5.0 1.0 Typ 140 5.7 6.0 ns ns ns ns Max Unit ns FAST AND LS TTL DATA 4-197 . HIGH or LOW In to CP Hold Time.0V Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Setup Time.0 3.

74 54.MC54/74F521 8-BIT IDENTITY COMPARATOR The MC54/74F521 is an expandable 8-bit comparator.0 25 25 Max 5. It compares two words of up to eight bits each and provides a LOW output when the two words match bit for bit.5 125 70 –1. 74 Min 4.5 –55 0 Typ 5. 74 54 74 IOH IOL Output Current  High Output Current  Low 54. • Compares Two 8-Bit Words in 6. The expansion input IA = B also serves as an active-LOW enable input.5 ns Typical • Expandable to Any Word Length • 20-Pin Package CONNECTION DIAGRAM (TOP VIEW) VCC 20 OA = B 19 B7 18 A7 17 B6 16 A6 15 B5 14 A5 13 B4 12 A4 11 8-BIT IDENTITY COMPARATOR FAST™ SCHOTTKY TTL 20 1 J SUFFIX CERAMIC CASE 732-03 1 IA = B 2 A0 3 B0 4 A1 5 B1 6 A2 7 B2 8 A3 9 B3 10 GND 20 1 N SUFFIX PLASTIC CASE 738-03 20 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54.0 20 mA mA Unit V °C FAST AND LS TTL DATA 4-198 .

74 74 VOL Output LOW Voltage 2.7 3.7 V VIN = 7.4 3.5 20 IIH IIL IOS ICC Input HIGH Current Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current – 60 21 100 –0.0 mA IOL = 20 mA VIN = 2.8 –1. use the appropriate value specified under guaranteed operating ranges.75 V VCC = MIN VCC = MAX NOTES: 1.0 mA IOH = – 1. For conditions shown as MIN or MAX.4 0.6 –150 32 Min 2.MC54/74F521 LOGIC DIAGRAM A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 IA = B NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.5 2.0 0. 2. Not more than one output should be shorted at a time. LOGIC SYMBOL 1 IA = B B7 A7 B6 A6 B5 A5 B4 OA = B A4 B3 A3 B2 A2 B1 A1 B0 A0 VCC = PIN 20 GND = PIN 10 OA = B 19 18 17 16 15 14 13 12 11 9 8 7 6 5 4 3 2 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH PARAMETER Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54.2 Typ Max Unit V V V V V V µA µA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = – 18 mA IOH = – 1.0 V VIN = 0. FAST AND LS TTL DATA 4-199 . nor for more than 1 second.35 0.5 V VCC = 4.5 V VOUT = 0 V IA = B = GND VCC = MAX VCC = MAX VCC = MAX VCC = MIN VCC = 4.

A2 = B2.5 Max 11 11 7... IA = B OA = B IA = B Parallel Expansion A0 B0 A7 B7 .. IA = B OA = B A16 B16 A23 B23 .5 10 74F TA = 0°C to +70°C VCC = 5.. A7 B7 A8 B8 A15 B15 ....0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay An or Bn to OA = B Propagation Delay IA = B to OA = B Min 2....5 3...5 9.... IA = B OA = B OA = B A16 B16 A23 B23 .5 3.....0 2...0 V ± 10% CL= 50 pF Min 2. Output A..5 5.5 3.5 6.5 Max 15 12 8..0 V ± 10% CL= 50 pF Min 2.5 Typ 6.5 4.0 2. IA = B OA = B A8 B8 A15 B15 . etc...0 54F TA = –55°C to +125°C VCC = 5..5 10 ns Unit ns Ripple Expansion A0 B0 ENABLE LOW .0 2.5 3. A1 = B1..... B A = B* A≠B A = B* A≠B OA = B L H H H AC CHARACTERISTICS 54/74F TA = +25°C VCC = +5.. IA = B OA = B Figure 1.MC54/74F521 FUNCTION TABLE Inputs IA = B L L H H H = HIGH Voltage Level L = LOW Voltage Level *A0 = B0...5 3.5 3.0 Max 10 10 6.. Applications FAST AND LS TTL DATA 4-200 .

For description and logic diagram please see the F373 data sheet. the data that meets the setup times is latched.MC54/74F533 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS The MC54 / 74F533 consists of eight latches with 3-state outputs for bus organized system applications.5 – 55 Typ 5. except that the outputs are inverted.The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW. The F533 is the same as the F373. OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL • Eight Latches in a Single Package • 3-State Outputs for Bus Interfacing • ESD Protection > 4000 Volts J SUFFIX CERAMIC CASE 732-03 1 CONNECTION DIAGRAM VCC O7 20 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 LE 11 20 20 1 N SUFFIX PLASTIC CASE 738-03 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 10 20 1 O3 GND DW SUFFIX SOIC CASE 751D-03 LOGIC SYMBOL 3 4 7 8 13 14 17 18 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC VCC = PIN 20 GND = PIN 10 D0 D1 D2 D3 D4 D5 D6 D7 11 1 LE OE O0 O1 O2 O3 O4 O5 O6 O7 2 5 6 9 12 15 16 19 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current — High Output Current — Low 54.0 25 Max 5. When OE is HIGH the bus output is in the high-impedance state.5 125 Unit V °C mA mA FAST AND LS TTL DATA 4-201 . 74 54 Min 4.0 24 Parameter 54. Data appears on the bus when the Output Enable (OE) is LOW. 74 54. 74 0 25 70 – 3.

0 mA IOL = 24 mA VOUT = 2.0 7.0 2.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX NOTES: 1.0 2.0 2.8 – 1.0 mA IOH = – 3.0 12.0 6. 2.0 10 7. nor for more than 1 second.MC54/74F533 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IOZH IOZL IIH IIL IOS ICCZ Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54. Not more than one output should be shorted at a time.0 3.0 3.3 0.0 5.0 5.0 3.5 50 – 50 20 V V µA µA µA mA mA mA 2.5 74F TA = 0 to + 70°C VCC = 5.0 Max 74F TA = 0 to + 70°C VCC = 5.3 Min 2.5 Unit ns ns ns ns AC OPERATING REQUIREMENTS 54 / 74F TA = + 25°C VCC = + 5.0 14 9.0 2.0 V Symbol ts (H) ts (L) th (H) th (L) tw (H) Parameter Setup Time.4 3.0 2.0 3.0 13 8.0 3.0 3. 74 Output HIGH Voltage 74 Output LOW Voltage Output OFF Current — HIGH Output OFF Current — LOW Input HIGH Current 100 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current – 60 41 – 0.5 6.0 3.35 0.5 Max 9.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = – 18 mA IOH = – 3.0 V VIN = 0.5 9.0 3.5 Max 10 8.6 –150 61 2.5 V VOUT = 0 V OE = 4.0 3.7 V VIN = 7.0 V ± 10% CL = 50 pF Min 4.0 V ± 10% CL = 50 pF Min 4.0 3. LE = Gnd VCC = MIN VCC = 4.0 2.5 1.0 3. use the appropriate value specified under guaranteed operating ranges. AC CHARACTERISTICS 54 / 74F TA = + 25°C VCC = + 5. HIGH or LOW Dn to LE Hold Time.0 11 7.5 5.5 Max 12 9.0 2.0 6.0 1.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time Output Disable Time Min 4.0 Max Unit ns ns ns FAST AND LS TTL DATA 4-202 .0 5.0 0.5 54F TA = – 55 to + 125°C VCC = 5.5 7.0 V ± 10% Min 2.0 6.0 6.7 3.0 1.0 8.0 2.5 V VCC = 4.5 1.5 7.0 11 8.0 2.7 V VOUT = 0.0 3.5 1.5 V VIN = 2. For conditions such as MIN or MAX.5 V Dn.0 1. HIGH or LOW Dn to LE LE Pulse Width HIGH Min 2.0 V ± 10% Min 2.0 Max 54F TA = – 55 to + 125°C VCC = 5.

low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. 74 54 Min 4.0 24 Parameter 54. OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL • Edge-Triggered D-Type Inputs • Buffered Positive Edge-Triggered Clock • 3-State Outputs for Bus Oriented Applications CONNECTION DIAGRAM VCC O7 20 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 CP 11 20 1 J SUFFIX CERAMIC CASE 732-03 20 N SUFFIX PLASTIC CASE 738-03 1 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 10 O3 GND 20 1 DW SUFFIX SOIC CASE 751D-03 LOGIC SYMBOL 3 4 7 8 13 14 17 18 ORDERING INFORMATION D0 D1 D2 D3 D4 D5 D6 D7 11 1 CP OE O0 O1 O2 O3 O4 O5 O6 O7 2 5 6 9 12 15 16 19 VCC = PIN 20 GND = PIN 10 MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current — High Output Current — Low 54.5 125 Unit V °C mA mA FAST AND LS TTL DATA 4-203 . The F534 is the same as the F374 except that the outputs are inverted.MC54/74F534 OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS The MC54 / 74F534 is a high-speed.5 – 55 Typ 5. 74 0 25 70 – 3.0 25 Max 5. 74 54. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.

The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition.7 3.5 V VOUT = 0 V Dn = Gnd OE = 4. When the OE is HIGH.5 V VCC = 4.35 0. 2.3 Min 2.8 – 1. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IOZH IOZL IIH IIL IOS ICCZ Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54. FAST AND LS TTL DATA 4-204 .0 mA IOH = – 3. 74 Output HIGH Voltage 74 Output LOW Voltage Output OFF Current — HIGH Output OFF Current — LOW Input HIGH Current 100 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current – 60 55 – 0. For conditions such as MIN or MAX. FUNCTIONAL DESCRIPTION The F534 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-state true outputs.7 V VIN = 7.7 V VOUT = 0.3 0.5 50 – 50 20 V V µA µA µA mA mA mA 2.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = – 18 mA IOH = – 3. With the Output Enable (OE) LOW. the contents of the eight flip-flops are available at the outputs.5 V VCC = MIN VCC = 4.5 V VIN = 2.6 –150 86 2.0 V VIN = 0. Operation of the OE input does not affect the state of the flip-flops. Not more than one output should be shorted at a time.0 mA IOL = 24 mA VOUT = 2.MC54/74F534 LOGIC DIAGRAM D0 CP CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q D1 D2 D3 D4 D5 D6 D7 OE O0 O1 O2 O3 O4 O5 O6 O7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.0 0.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX NOTES: 1. the outputs go to the high impedance state.4 3. nor for more than 1 second. use the appropriate value specified under guaranteed operating ranges. The buffered clock and buffered Output Enable are common to all flip-flops.

0 4.0 7.0 V CL = 50 pF Symbol fmax tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay CP to On Output Enable Time Output Disable Time Min 100 4.0 6.0 V ± 10% Min 2.0 2.5 6.0 2.0 6.0 2.5 Max 74F TA = 0 to + 70°C VCC = 5.5 11.0 2.0 V Symbol ts (H) ts (L) th (H) th (L) tw (H) tw (L) Parameter Setup Time.0 7. HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW Min 2.0 2.0 2.0 2.5 7.0 2.0 2.0 2.0 6.0 ns Max Unit FAST AND LS TTL DATA 4-205 .5 11 14 10 8.5 Typ Max 54F TA = – 55 to + 125°C VCC = 5.MC54/74F534 AC CHARACTERISTICS 54 / 74F TA = + 25°C VCC = + 5.0 V ± 10% CL = 50 pF Min 60 4.0 2.5 2.5 7.3 4.5 9.0 2.0 10 10 12.5 8.0 6.0 Typ Max 54F TA = – 55 to + 125°C VCC = 5.0 5.0 2.0 2.0 10.5 ns 8.0 2.0 5.0 6.0 2.3 8.0 V ± 10% Min 2. HIGH or LOW Dn to CP Hold Time.0 2.5 Max Unit MHz ns AC OPERATING REQUIREMENTS 54 / 74F TA = + 25°C VCC = + 5.0 ns 2.5 8.0 4.0 7.0 V ± 10% CL = 50 pF Min 70 4.8 5.0 4.0 2.0 Max 74F TA = 0 to + 70°C VCC = 5.5 7.0 2.

same polarity as the P input). Input codes greater than BCD nine cause all outputs to go to the inactive state (i..MC54/74F537 1-OF-10 DECODER WITH 3-STATE OUTPUTS The MC54 / 74F537 is a one-of-ten decoder/demultiplexer with four active HIGH BCD inputs and ten mutually exclusive outputs. Two input enables. A polarity control input determines whether the outputs are active LOW or active HIGH. FAST AND LS TTL DATA 4-206 . and a HIGH signal on the Output Enable (OE) input forces all outputs to the high impedance state. active HIGH E2 and active LOW E1. The MC54 / 74F537 has 3-state outputs. 1-OF-10 DECODER WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL • • • • • Demultiplexing Capability 3-State Outputs Multiple Input Enable for Expansion Polarity Control Input ESD Protection > 4000 Volts CONNECTION DIAGRAM DIP (TOP VIEW) VCC O3 20 19 O4 18 A3 17 A2 16 E1 15 E2 14 O9 13 O8 12 O7 11 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 20 DW SUFFIX SOIC CASE 751D-03 1 1 O2 2 O1 3 O0 4 P 5 OE 6 A0 7 A1 8 O5 9 10 O6 GND ORDERING INFORMATION LOGIC DIAGRAM A3 A2 A1 A0 E1 E2 P 15 14 5 MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC LOGIC SYMBOL 4 6 7 16 17 P A0 A1 A2 A3 E1 E2 OE O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 3 2 1 19 18 8 9 11 12 13 OE O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 VCC = PIN 20 GND = PIN 10 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.e. are available for demultiplexing data to the selected output in either non-inverted or inverted form.

0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay An to On Propagation Delay E1 to On Propagation Delay E2 to On Propagation Delay P to On Output Enable Time OE to On Output Disable Time OE to On Min 4. E1 = GND OE.0 4.5 ns 17 12 8.0 4.5 V VCC = 4.0 9.5 Typ Max 14 11 11 11 11.0 8.4 Min 2. 74 0 25 70 – 3.5 V VCC = MAX.0 1.0 25 Max 5.5 2.0 V ± 10% CL = 50 pF Min 3. VIN = 2.5 1.0 2. 74 Output HIGH Voltage 74 Output LOW Voltage Output OFF Current — HIGH Output OFF Current — LOW Input HIGH Current 0.5 2.5 V VCC = MIN VCC = 4. VIN = 0.5 50 – 50 20 V V µA µA µA mA mA mA mA 2.0 4.0 4.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = – 18 mA IOH = – 3.0 4.0 Unit FAST AND LS TTL DATA 4-207 .7 0. E2.0 3.5 4.MC54/74F537 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current — High Output Current — Low 54.0 4.0 7.0 3.0 6.0 6. 74 54.0 V ± 10% CL = 50 pF Min 3.5 21 13 11 10 8 8 74F TA = 0 to 70°C VCC = 5.0 6.5 4.0 1.5 – 55 Typ 5.8 – 1.0 3.5 4.5 2.0 mA IOH = – 3.0 1.5 11.7 V VCC = MAX.0 Max 19 15 14 14 15 14.1 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current – 60 44 – 0. VIN = 7. 74 54 Min 4.5 16 11.0 3.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX.5 4.0 5.0 1.5 2.0 1.0 mA IOL = 24 mA VOUT = 2.5 125 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IOZH IOZL IIH IIL IOS ICCZ Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54.0 5.0 5.0 V VCC = MAX.5 2. P = HIGH AC CHARACTERISTICS 54 / 74F TA = + 25°C VCC = + 5.6 –150 66 2.5 54F TA = –55 to +125°C VCC = 5. VOUT = 0 V VCC = MAX: A0 – A3.0 24 Parameter 54.0 3.5 3.0 Max 16 12 ns 12 12 13 12.7 V VOUT = 0.0 5.0 0.0 ns 7.5 7.

MC54/74F537 TRUTH TABLE INPUTS FUNCTION OE HIGH Impedance Disable H L L L L L L Active HIGH Out ut Output (P = L) L L L L L L L L L L L L Active LOW Out ut Output (P = H) L L L L L L L L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance OUTPUTS A2 X X X L L L L H H H H L L X H L L L L H H H H L L X H A1 X X X L L H H L L H H L L H X L L H H L L H H L L H X A0 X X X L H L H L H L H L H X X L H L H L H L H L H X X H L L L L L L L L L L L L H H H H H H H H H H H L H L L L L L L L L L L H L H H H H H H H H H H L L H L L L L L L L L L H H L H H H H H H H H H 00 Z 01 Z 02 Z O3 Z 04 Z 05 Z 06 Z 07 Z 08 Z 09 Z E1 X H X L L L L L L L L L L L L L L L L L L L L L L L L E2 X X L H H H H H H H H H H H H H H H H H H H H H H H H A3 X X X L L L L L L L L H H H H L L L L L L L L H H H H Out uts Outputs Equal P In ut Input L L L H L L L L L L L L H H H L H H H H H H H H L L L L H L L L L L L L H H H H L H H H H H H H L L L L L H L L L L L L H H H H H L H H H H H H L L L L L L H L L L L L H H H H H H L H H H H H L L L L L L L H L L L L H H H H H H H L H H H H L L L L L L L L H L L L H H H H H H H H L H H H L L L L L L L L L H L L H H H H H H H H H L H H FAST AND LS TTL DATA 4-208 .

FAST AND LS TTL DATA 4-209 . A polarity control input (P) determines whether the outputs are active LOW or active HIGH.MC54/74F538 1-OF-8 DECODER WITH 3-STATE OUTPUTS The MC54 / 74F538 decoder/demultiplexer accepts three Address (A0 – A2) input signals and decodes them to select one of eight mutually exclusive outputs. or for data demultiplexing to 1-of-8 or 1-of-16 destinations. 1-OF-8 DECODER WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL • • • • • Output Polarity Control Data Demultiplexing Capability Multiple Enables for Expansion 3-State Outputs ESD Protection > 4000 Volts CONNECTION DIAGRAM DIP (TOP VIEW) VCC O3 20 19 O4 18 A2 17 E1 16 E2 15 E3 14 E4 13 P 12 O7 11 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 1 O2 2 O1 3 O0 4 5 6 A0 7 A1 8 O5 9 10 20 1 DW SUFFIX SOIC CASE 751D-03 OE1 OE2 O6 GND ORDERING INFORMATION LOGIC DIAGRAM A2 A1 A0 E1 E2 E3 E4 16 15 14 13 4 5 OE1 OE2 O0 O1 O2 O3 O4 O5 O6 O7 E1 E2 E3 E4 OE1 OE2 O0 O1 O2 O3 O4 O5 O6 O7 3 2 1 14 18 VCC = PIN 20 GND = PIN 10 8 9 11 MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC LOGIC SYMBOL 12 P 6 A0 7 17 A1 A2 P Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. A HIGH Signal on either of the active LOW Output Enable (OE) inputs forces all outputs to the high impedance state. Two active HIGH and two active LOW input enables are available for easy expansion to 1-of-32 decoding with four packages.

8 – 1.0 3.5 2.0 0.5 2.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN. VOUT = 0 V VCC = MAX: A0 – A2.0 1. P = HIGH AC CHARACTERISTICS 54 / 74F TA = + 25°C VCC = + 5.4 Min 2.0 1.5 – 55 Typ 5.5 ns 13 12.5 13 16 8.0 1.5 11 10 11.5 3.0 6. 74 54 Min 4.5 54F TA = –55 to +125′C VCC = 5.0 mA IOH = – 3.0 3.5 3.7 V VCC = MAX.5 V VCC = 4.0 Max 17 16.5 V VCC = MAX.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay An to On Propagation Delay E1 or E2 to On Propagation Delay E3 or E4 to On Propagation Delay P to On Output Enable Time OE1 or OE2 to On Output Disable Time OE1 or OE2 to On Min 4.0 3.0 3.0 V VCC = MAX.0 3.5 4.6 –150 56 2. E3.5 V VCC = 4.0 3.0 4.5 3.5 9.5 4. OE2.5 15 11.5 3.0 5.0 25 Max 5.0 Max 14 13.5 12.0 Typ 11 7.0 V ± 10% CL = 50 pF Min 4. 74 Output HIGH Voltage 74 Output LOW Voltage Output OFF Current — HIGH Output OFF Current — LOW Input HIGH Current 0.0 5.5 9.5 12 12 12.5 50 – 50 20 V V µA µA µA mA mA mA mA 2.5 15 14.5 4.5 13 ns 16.5 2.0 8. 74 0 25 70 – 3.5 6.0 1.5 15 18.5 13. VIN = 0.5 8.0 10. 74 54.7 0. E4.0 24 Parameter 54.0 4.1 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current – 60 37 – 0.5 125 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IOZH IOZL IIH IIL IOS ICCZ Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54.0 4.5 74F TA = 0 to 70°C VCC = 5.0 5.7 V VOUT = 0.MC54/74F538 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current — High Output Current — Low 54.0 1.5 4.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX.0 mA IOL = 24 mA VOUT = 2.0 4.5 3.5 6.5 13.5 12. E2 = GND OE1.5 15.0 1. VIN = 7.0 9.0 3.0 4.0 3.5 12 11 15 ns 7. VIN = 2.0 Max 13 12.5 11 5. E1. IIN = – 18 mA IOH = – 3.0 V ± 10% CL = 50 pF Min 4.5 Unit FAST AND LS TTL DATA 4-210 .

MC54/74F538 TRUTH TABLE INPUTS FUNCTION OE1 High Impedance H X L L L L L L L L L L L L L L L L L L L L OE2 X H L L L L L L L L L L L L L L L L L L L L E1 X X H X X X L L L L L L L L L L L L L L L L E2 X X X H X X L L L L L L L L L L L L L L L L E3 X X X X L X H H H H H H H H H H H H H H H H E4 X X X X X L H H H H H H H H H H H H H H H H A2 X X X X X X L L L L H H H H L L L L H H H H A1 X X X X X X L L H H L L H H L L H H L L H H A0 X X X X X X L H L H L H L H L H L H L H L H H L L L L L L L L H H H H H H H L H L L L L L L H L H H H H H H O0 Z Z O1 Z Z O2 Z Z O3 Z Z O4 Z Z O5 Z Z O6 Z Z O7 Z Z OUTPUTS Disable Out uts Outputs Equal P In ut Input Active HIGH Output (P = L) L L H L L L L L H H L H H H H H L L L H L L L L H H H L H H H H L L L L H L L L H H H H L H H H L L L L L H L L H H H H H L H H L L L L L L H L H H H H H H L H L L L L L L L H H H H H H H H L Active LOW Output (P = H) H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance FAST AND LS TTL DATA 4-211 .

MC54/74F539 DUAL 1-OF-4 DECODER WITH 3-STATE OUTPUTS The MC54 / 74F539 contains two independent decoders. data is routed to the selected output in non-inverted form in the active LOW mode or in inverted form in the active HIGH mode. An active LOW input Enable (E) is available for data demultiplexing. A HIGH Signal on the active LOW Output Enable (OE) input forces the 3-state outputs to the high impedance state. Each accepts two Address (A0 – A1) input signals and decodes them to select one of four mutually exclusive outputs. DUAL 1-OF-4 DECODER WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL • • • • • Demultiplexing Capability 3-State Outputs Two Completely Independent 1-of-4 Decoders Input Clamp Diodes Limit High Speed Termination Effects ESD Protection > 4000 Volts CONNECTION DIAGRAM DIP (TOP VIEW) VCC O3b A1b A0b 20 19 18 17 Eb 16 Ea 15 OEa Pa 14 13 O0a O1a 12 11 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 1 2 3 4 Pb 5 6 7 8 9 10 20 1 O2b O1b O0b OEb A0a A1a O3a O2a GND DW SUFFIX SOIC CASE 751D-03 LOGIC DIAGRAM (1/2 SHOWN) A1 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC A0 E LOGIC SYMBOL 13 6 7 P A0 A1 P 15 14 E DECODER a OE O0 O1 O2 O3 12 11 9 8 4 17 18 OE 16 O0 O1 O2 O3 5 E DECODER b OE Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. VCC = PIN 20 GND = PIN 10 P A0 A1 O0 O1 O2 O3 3 2 1 19 FAST AND LS TTL DATA 4-212 . A polarity control input (P) determines whether the outputs are active HIGH (P = L) or active LOW (P = H).

5 12.5 1.0 3. VOUT = 0 V VCC = MAX.5 125 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IOZH IOZL IIH IIL IOS ICCZ Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54.0 2.5 19.5 1.0 0.0 25 Max 5.5 74F TA = 0 to 70°C VCC = 5.5 2.0 2.0 V ± 10% CL = 50 pF Min 3.5 11.0 3.7 0.7 V VOUT = 0.0 4.6 –150 60 2.5 16 14 13.5 9.5 V VCC = 4.5 3.5 – 55 Typ 5.5 3.5 10 15.5 10 6.1 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current – 60 40 – 0. E = GND OE. VIN = 0.5 50 – 50 20 V V µA µA µA mA mA mA mA 2.0 3.5 14.0 mA IOH = – 3.0 8.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay An to On Propagation Delay E to On Propagation Delay P to On Propagation Delay P to On Output Enable Time OE to On Output Disable Time OE to On Min 3.8 – 1.5 11.7 V VCC = MAX.0 3. 74 0 25 70 – 3.0 3.0 4. 74 54.0 3.4 Min 2.0 V VCC = MAX.5 13. VIN = 7.0 3.0 4.MC54/74F539 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current — High Output Current — Low 54.0 mA IOL = 24 mA VOUT = 2.0 3.0 Typ Max 12.5 11.5 13 12 11.5 V VCC = 4.0 2.0 7.5 3.0 1. VIN = 2.5 10.0 3.5 ns 6.5 10.5 Unit ns ns ns ns FAST AND LS TTL DATA 4-213 . P = HIGH AC CHARACTERISTICS 54 / 74F TA = + 25°C VCC = + 5.5 3.0 2.0 1.5 Max 13.5 2. A1.5 Max 18. 74 54 Min 4.5 3.5 12.0 1. 74 Output HIGH Voltage 74 Output LOW Voltage Output OFF Current — HIGH Output OFF Current — LOW Input HIGH Current 0. A0 .5 7.0 54F TA = –55 to +125°C VCC = 5.0 2.0 24 Parameter 54.5 9.5 8.5 9.5 8.5 4.5 V VCC = MAX. IIN = – 18 mA IOH = – 3.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX.0 3.5 11 11 9.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.0 3.0 V ± 10% CL = 50 pF Min 3.5 5.5 9.

MC54/74F539 TRUTH TABLE (each half) Inputs Function High Impedance Disable Active HIGH Output (P = L) Active LOW Output (P = H) H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance Outputs A1 X X L L H H L L H H A0 X X L H L H L H L H H L L L L H H H L H L L H L H H O0 Z O1 Z On = P L L H L H H L H L L L H H H H L O2 Z O3 Z OE H L L L L L L L L L E X H L L L L L L L L FAST AND LS TTL DATA 4-214 .

The A outputs are guaranteed to sink 20 mA while the B outputs are rated for 64 mA. OCTAL REGISTERED TRANSCEIVER.0 / – 15 24 / 64 Unit V °C mA mA FAST AND LS TTL DATA 4-215 . 3-STATE FAST™ SCHOTTKY TTL • • • • • • • • • • • Combines 74F245 and 74F373 Type Functions in One Chip 8-Bit Octal Transceiver Non-Inverting Back-to-Back Registers for Storage Separate Controls for Data Flow in Each Direction Glitchless Outputs During 3-State Power Up or Power Down Operation High Impedance Outputs in Power Off State A Outputs Sink 24 mA and Source 3.5 0 Typ 5.MC74F543 OCTAL REGISTERED TRANSCEIVER. The MC74F543 has a noninverting data path.0 mA B Outputs Sink 64 mA and Source 15 mA See F544 for Inverting Version ESD Protection > 4000 Volts PIN ASSIGNMENT VCC EBA 24 23 B0 22 B1 21 B2 20 B3 19 B4 18 B5 17 B6 16 B7 LEAB OEAB 15 14 13 24 1 N SUFFIX PLASTIC CASE 724-03 24 1 DW SUFFIX SOIC CASE 751E-03 ORDERING INFORMATION MC74FXXXN Plastic MC74FXXXDW SOIC 1 2 3 4 A1 5 A2 6 A3 7 A4 8 A5 9 A6 10 A7 11 12 LEBA OEBA A0 EAB GND GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4. NON-INVERTING. LEBA) and Enable (OEAB.0 25 Max 5. NON-INVERTING.5 70 – 3. OEBA) inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Separate Latch Enable (LEAB. 3-STATE The MC74F543 Octal Registered Transceivers contain two sets of data flowing in either direction.

2 Typ Max Unit V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN. VIN = 7.MC74F543 FUNCTION TABLE Inputs OEXX H L L L L L L EXX X H H L L L L LEXX X L L H H L L Data X l h l h L H Outputs Z Z Z L H L H Status Outputs disabled Outputs disabled Data latched Data latched Transparent H = HIGH voltage level: h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): L = LOW Voltage Level: I = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): X = Don’t care: Z = HIGH impedance state. a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs.4 A0 – A7 VOH Output HIGH Voltage B0 – B7 A0 – A7 VOL Output LOW Voltage B0 – B7 74 I/O Pins IIH Input HIGH Current Control Pins 20 EAB. LEBA. VOUT = 0. With EAB LOW.0 mA 30 IOH = – 15 mA IOL = 24 mA IOL = 64 mA –0. for example.75 V VCC = 4.7 V VOUT = 5. and OEBA inputs.5 V VCC = MIN VCC = MAX. For conditions shown as MIN or MAX.5 V 0.0 0. FAST AND LS TTL DATA 4-216 . DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 2. Control of data flow from B to A is similar. with separate input and controls for each set. VIN = 2. For data flow from A to B.5 V NOTES: 1. IIN = – 18 mA VCC = 4.8 – 1. VIN = 0 5 V MAX 0.0 0. as indicated in the Function Table.5 VOUT = 2. High-Level Voltage Applied Off-State Output Current.0 100 V mA µA 74 74 74 2. FUNCTIONAL DESCRIPTION The MC74F543 contains two sets of eight D-type latches.35 0.7 V IOZH IOZL IOS VCC = MAX VCC = MAX.5 3.55 1. nor for more than 1 second. the 3-State B output buffers are active and reflects the data present at the output of the A latches.0 – 600 –150 mA –225 100 125 125 mA VCC = MAX VCC = MAX. a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent. 2. VIN = 5.2 mA VCC = MAX. use the appropriate value specified under recommended operating conditions for the applicable device type.4 V V V IOH = – 3. With EAB and OEAB both LOW. VOUT = 0 V MAX µA mA µA – 1. Low-Level Voltage Applied Output Short Circuit Current (Note 2) An Outputs Bn Outputs ICCH ICC Total Supply Current ICCL ICCZ – 60 – 100 70 95 95 – 0.7 2. the A-to-B Enable (EAB) Input must be LOW in order to enter data from A0 – A7 or take data from B0 – B7.0 V VCC = MAX.4 0.5 V VCC = MAX. but using the EBA. Not more than one output should be shorted at a time.73 Parameter Min 2.5 V VCC = 4. EBA IIL Input LOW Current Other Inputs Off-State Output Current.6 70 1.

5 10 12 9.0 3.5 7.5 5.0 4.0 Typ Max 74F TA = 0°C to + 70°C VCC = + 5.0 3.5 8.5 Max Unit MHz ns ns ns ns ns AC OPERATING REQUIREMENTS 74F TA = + 25°C VCC = + 5.5 3.0 7.5 7.5 6.0 Typ 100 5.MC74F543 AC ELECTRICAL CHARACTERISTICS 74F TA = + 25°C VCC = + 5.5 7.5 12.5 12.5 4.5 2.5 8.0 V CL = 50 pF Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay Transparent Mode An to Bn or Bn to An Propagation Delay LEBA to An Propagation Delay LEAB to Bn Output Enable Time to OEBA or OEAB to An or Bn EBA or EAB to An or Bn Output Disable Time to OEBA or OEAB to An or Bn EBA or EAB to An or Bn Min 70 3.0 4.5 2.0 4. HIGH or LOW An or Bn to LEBA or LEAB Hold Time.0 4.5 3.5 6.0 V ± 10% CL = 50 pF Min 70 3.0 7.5 11 11 11 11 9.0 V ± 10% CL = 50 pF Min 3.0 Typ Max Unit ns ns ns FAST AND LS TTL DATA 4-217 .0 8. B to A Pulse Width.0 10.5 8.5 3.5 4.5 3.5 4.0 5. LOW Min 3.5 4.5 4.5 Max 74F TA = 0°C to + 70°C VCC = + 5.5 3. HIGH or LOW An to Bn to LEBA or LEAB Latch Enable.0 3.0 3.5 12.0 8.5 8.0 3.0 2.0 8.5 9.5 12.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) tw(L) Parameter Setup Time.0 2.0 8.5 4.

MC74F543 LOGIC DIAGRAM DETAIL A D Q LE A0 B0 Q D LE B1 B2 DETAIL A X 7 B3 B4 B5 B6 B7 A1 A2 A3 A4 A5 A6 A7 OEBA OEAB EBA LEBA EAB LEAB NOTE: Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FAST AND LS TTL DATA 4-218 .

The MC74F544 has an inverting data path. LEBA) and Enable (OEAB.5 0 — — Typ 5. OCTAL REGISTERED TRANSCEIVER. INVERTING. 3-STATE FAST™ SCHOTTKY TTL • • • • • • • • • • • Combines 74F245 and 74F373 Type Functions in One Chip 8-Bit Octal Transceiver Inverting Back-to-Back Registers for Storage Separate Controls for Data Flow in Each Direction Glitchless Outputs During 3-State Power Up or Power Down Operation High Impedance Outputs in Power Off State A Outputs Sink 24 mA and Source 3. The A outputs are guaranteed to sink 24 mA while the B outputs are rated for 64 mA.0 25 — — Max 5.MC74F544 OCTAL REGISTERED TRANSCEIVER. OEBA) inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. INVERTING.0 mA B Outputs Sink 64 mA and Source 15 mA See F543 for Noninverting Version ESD Protection > 4000 Volts 24 1 N SUFFIX PLASTIC CASE 724-03 24 1 DW SUFFIX SOIC CASE 751E-03 PIN ASSIGNMENT VCC EBA 24 23 B0 22 B1 21 B2 20 B3 19 B4 18 B5 17 B6 16 B7 LEAB OEAB 15 14 13 ORDERING INFORMATION MC74FXXXN Plastic MC74FXXXDW SOIC 1 2 3 4 A1 5 A2 6 A3 7 A4 8 A5 9 A6 10 A7 11 12 LEBA OEBA A0 EAB GND GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL DC Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4. 3-STATE The MC74F544 Octal Registered Transceivers contain two sets of D-Type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB.5 70 – 3.0 / – 15 24 / 64 Unit V °C mA mA FAST AND LS TTL DATA 4-219 .

8 – 1. Not more than one output should be shorted at a time.4 2.5 V IOH = – 3.75 V IOH = – 15 mA IOL = 24 mA VCC = 4.7 VCC = MAX. nor for more than 1 second. the 3-State B output buffers are active and reflect the inverted data present at the output of the A latches.35 0.5 V VCC = MIN IOL = 64 mA VCC = MAX. VOUT = 0.0 100 20 70 – 1. LEBA.6 70 – 600 –150 –225 105 130 125 mA VCC = MAX Unit V V V V V V V mA µA µA µA mA µA µA mA Test Conditions (Note 1) Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN. and OEBA inputs. 2. FUNCTIONAL DESCRIPTION The MC74F544 contains two sets of eight D-type latches. as indicated in the Function Table. With EAB and OEAB both LOW. FAST AND LS TTL DATA 4-220 .0 V VCC = MAX.73 — 3.55 1.4 — — — — — — — — — — 70 95 95 Max — 0. For conditions shown as MIN or MAX.5 V VCC = MAX. but using the EBA. for example.4 — 0. VOUT = 0 V MAX ICC Total Supply Current NOTES: 1. Control of data flow from B to A is similar. a LOW signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent.0 — — — — — — — — — — – 60 – 100 — — — Typ — — – 0. EBA Other Inputs Parameter Min 2. VIN = 5. use the appropriate value specified under recommended operating conditions for the applicable device type.7 2.0 mA 30 VCC = 4.5 VCC = MAX. a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs.7 V VCC = MAX. With EAB LOW. VIN = 0 5 V MAX 0. Low-Level Voltage Applied Output Short Circuit Current (Note 2) An Outputs Bn Outputs ICCH ICCL ICCZ EAB. the A-to-B Enable (EAB) input must be LOW in order to enter data from A0 – A7 or take data from B0 – B7. VIN = 2 7 V MAX 2.5 0. IIN = – 18 mA VCC = 4.5 V VCC = MAX.MC74F544 FUNCTION TABLE Inputs OEXX H X L L L L L L L EXX X H ↑ ↑ L L L L L LEXX X X L L ↑ ↑ L L H Data X X l h l h L H X Outputs Z Z Z Z H L H L NC Status Outputs disabled Outputs disabled Outputs disabled Data latched Data latched Transparent Hold H = HIGH voltage level: h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): L = LOW voltage level: l = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): X = Don’t care: Z = HIGH impedance state: NC = No Change.2 – 0. with separate input and controls for each set.2 — — — 0.0 — — 2. VIN = 7. VOUT = 2. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage A0 – A7 B0 – B7 VOL Output LOW Voltage A0 – A7 B0 – B7 74 74 74 74 I/O Pins IIH Input HIGH Current Control Pins Control Pins I/O Pins IIL IOZH IOZL IOS Input LOW Current Off-State Output Current Off-State Output Current. For data flow from A to B.

0 3. B to A Pulse Width.0 4.5 14. LOW Min 3.5 10.5 10.5 6.5 10 12 9.5 Typ — — — — — — — — — — Max 9.0 3.5 8.0 4.0 3.0 V ± 10% CL = 50 pF Min 3.0 6. HIGH or LOW An to Bn to LEBA or LEAB Latch Enable.5 14.0 3.5 13 9.5 Typ — — — — — Max — — — — — Unit ns ns ns FAST AND LS TTL DATA 4-221 .0 3.0 2.0 8.5 74F TA = 0 °C to + 70°C VCC = + 5.0 2.5 1.MC74F544 AC ELECTRICAL CHARACTERISTICS 74F TA = + 25°C VCC = + 5.0 10.0 7.5 9.5 7.0 6.5 13 9. HIGH or LOW An or Bn to LEBA or LEAB Hold Time.0 3.0 4.0 1.5 Max 10.0 V ± 10% CL = 50 pF Min 2.0 3.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Transparent Mode An to Bn or Bn to An Propagation Delay LEBA to An Propagation Delay LEAB to Bn Output Enable Time OEBA or OEAB to An or Bn EBA or EAB to An or Bn Output Disable Time OEBA or OEAB to An or Bn EBA or EAB to An or Bn Parameter Min 2.0 1.0 6.0 7.0 4.0 6.0 4.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) tw(L) Parameter Setup Time.0 Typ — — — — — Max — — — — — 74F TA = 0°C to + 70°C VCC = + 5.5 1.0 3.5 Unit ns ns ns ns ns AC OPERATING REQUIREMENTS 74F TA = + 25°C VCC = + 5.0 6.0 4.

FAST AND LS TTL DATA 4-222 .MC74F544 LOGIC DIAGRAM D Q LE A0 DETAIL A D Q LE B0 A1 A2 A3 A4 A5 A6 A7 DETAIL A X 7 B1 B2 B3 B4 B5 B6 B7 OEBA OEAB EBA EAB LEBA LEAB NOTE: Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

MC54/74F568 MC54/74F569 4-BIT BIDIRECTIONAL COUNTERS (WITH 3-STATE OUTPUTS) FAST™ SCHOTTKY TTL • 4-Bit Bidirectional Counting • • • • • • F568 Decade Counter F569 Binary Counter Synchronous Counting and Loading Lookahead Carry Capability for Easy Cascading Preset Capability for Programmable Operation 3-State Outputs for Bus Organized Systems Master Reset (MR) Overrides All Other Inputs Synchronous Reset (SR) Overrides Counting and Parallel Loading 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 CONNECTION DIAGRAM VCC TC 20 19 CC 18 OE 17 O0 16 O1 15 O2 14 O3 CET 13 12 PE 11 20 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 1 U/D 2 CP 3 P0 4 P1 5 P2 6 P3 8 7 CEP MR 9 10 SR GND LOGIC SYMBOL 11 3 4 5 6 P3 PE P0 P1 P2 1 7 12 2 17 U/D CEP CC CET TC CP OE MR SR 8 9 O0 O1 O2 O3 16 15 14 13 18 19 FAST AND LS TTL DATA 4-223 . reversible counters with 3-state outputs. For maximum flexibility there are both synchronous and master asynchronous reset inputs as well as both Clocked Carry (CC) and Terminal Count (TC) outputs. They feature preset capability for programmable operation.4-BIT BIDIRECTIONAL COUNTERS (WITH 3-STATE OUTPUTS) The MC54/ 74F568 and MC54/74F569 are fully synchronous. resetting or parallel loading. the F569 is a binary counter. and a U/D input to control the direction of counting. All state changes except Master Reset are initiated by the rising edge of the clock. A HIGH signal on the Output Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting. carry lookahead for easy cascading. The F568 is a BCD decade counter.

Two types of outputs are provided as overflow/underflow indicators.The F569 counts in the modulo-16 binary sequence. To implement synchronous multistage counters. Conversely.15 for the F569) in the Up mode. The F568 and F569 use edge-triggered flip-flops and changing the SR. a HIGH signal on either CEP or CET inhibits counting. Parallel Enable (PE). 74 54 74 54. The CC output is normally HIGH. Figure A shows the connections for simple ripple carry. CEP and CET permit counting when both are LOW.MC54/74F568 • MC54/74F569 Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54. parallel load. A HIGH signal on OE forces O0–O3 to the High Z state but does not prevent counting. For such applications.0 25 25 Max 5. registers or counters. count and hold. the Clocked Carry (CC) output is provided. plus the cumulative CET to TC delays of the intermediate stages. Synchronous Reset (SR). The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. From state 9 (HLLH) it will increment to 0 (LLLL) in the Up mode.5 – 55 0 Typ 5. the CC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. loading or resetting. whether by counting or presetting. 74 Min 4. LOGIC EQUATIONS: Count Enable = CEP⋅CET⋅PE Up (’F568): TC = Q0⋅Q1⋅Q2⋅Q3⋅(Up)⋅CET (’F569): TC = Q0⋅Q1⋅Q2⋅Q3⋅(Up)⋅CET Down (Both): TC = Q0⋅Q1⋅Q2⋅Q3⋅(Down)⋅CET CC TRUTH TABLE Inputs SR L X X X X H PE X L X X X H CEP X X H X X L CET X X X H X L TC* X X X X H L CP X X X X X Output CC H H H H H * = TC is generated internally L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care = Low Pulse FUNCTION TABLE Inputs MR L h h h h h h SR X l h h h H H PE X X l h h H H CEP X X X l l H X CET X X X l l X H U/D X X X h l X X CP X ↑ ↑ ↑ ↑ X X Operating Mode Asynchronous reset Synchronous reset Parallel load Count up (increment) Count down (decrement) Hold (do nothing) H = HIGH voltage level h = HIGH voltage level one setup prior to the Low-to-High Clock transition L = LOW voltage level l = LOW voltage level one setup prior to the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition FAST AND LS TTL DATA 4-224 . With MR. Since this final cycle takes 10 (F568) or 16 (F569) clocks to complete. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. TC will then remain LOW until a state change occurs. plus the CET to CP setup time of the last stage. synchronous reset. there is plenty of time for the ripple to progress through the intermediate stages. For faster clock rates. in the Down mode it will decrement from 0 to 15. are observed. to start its final cycle. the parallel data outputs O0–O3 are active and follow the flip-flop Q outputs. This total delay plus setup time sets the upper limit on clock frequency. 74 54. or min to max in the Down mode. A LOW signal on SR overrides counting and parallel loading and allows the Q outputs to go LOW on the next rising edge of CP. Five control inputs — Master Reset (MR). All state changes (except due to Master Reset) occur synchronously with the LOWto-HIGH transition of the Clock Pulse (CP) input signal. PE. in order of precedence: asynchronous reset. CEP . CET or U/D inputs when the CP is in either state does not cause errors. when the counter reaches zero in the Down mode. determine the mode of operation. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode. as shown in the CC Truth Table. When CEP. SR and PE HIGH. or reaches maximum (9 for the F568. CET.5 125 70 – 3. in Down mode it will decrement from 0 to 9. The circuits have five fundamental modes of operation. When the Output Enable (OE) is LOW. or until U/D or CET is changed. and TC are LOW. the carry lookahead connections shown in Figure B are recommended. The clock inputs of all flip-flops are driven in parallel through a clock buffer. provided that the recommended setup and hold times. Count Enable Parallel (CEP) and Count Enable Trickle (CET) — plus the Up/Down (U/D) input. in which the clock period must be longer than the CP to TC delay of the first stage.0 24 Unit V °C mA mA FUNCTIONAL DESCRIPTION The F568 counts modulo-10 in the BCD (8421) sequence. with respect to the rising edge of CP. the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation. The Terminal Count (TC) output is normally HIGH and goes LOW providing CET is LOW. as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces the flip-flop Q outputs LOW. From state 15 it will increment to state 0 in the Up mode.

LOGIC DIAGRAMS MC54/74F568 MC54/74F569 P0 P1 P2 P3 P0 P1 P2 P3 PE PE CEP CEP CET CET T LD T LD AT AF TC AT AF TC MC54/74F568 • MC54/74F569 FAST AND LS TTL DATA CC LD T BT BF U/D DETAIL A DETAIL A CP UP DN SR UP DN CP ENF CD Q SR ENF UP DETAIL A DETAIL A CP CP J Q CP K CD Q SR DETAIL A MR OE O1 O2 O3 O0 O1 Q CD 4-225 ENF CC LD T BT BF DETAIL A DN CP ENF CD Q SR DETAIL A CP U/D UP DN SR CP CP J CP K CD Q Q SR DETAIL A Q CD MR OE O0 O2 O3 Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. .

8 – 1.5 V VIN = 2.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX Unit Test Conditions IIL IOS ICC mA mA mA VCC = MAX. Multistage Counter with Ripple Carry COUNT CET TC CP CET TC CET TC CET TC CET CP TO ALL STAGES Figure B.2 Typ Max V V V V Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.7 V VOUT = 0. nor for more than 1 second.0 V VCC = 4. 2. For conditions such as MIN or MAX. CET Others Output Short Circuit Current (Note 2) Power Supply Current (ALL Outputs OFF) – 60 –1.5 V VOUT = 0 V VCC = MAX VCC = MAX NOTES: 1.3 2.4 3.0 0.6 –150 67 2. Multistage Counter with Lookahead Carry COUNT CET TC L CP TO ALL STAGES CEP CET TC CEP CET TC CEP CET TC CEP CET CP DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min VIH VIL VIK VOH VOL IOZH IOZL IIH Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54.7 V VIN = 7. FAST AND LS TTL DATA 4-226 . IIN = – 18 mA IOH = – 3. VIN = 0.3 0. use the appropriate value specified under recommended operating conditions for the applicable device type. Not more than one output should be shorted at a time.0 mA IOH = – 3. 74 Output HIGH Voltage 74 Output LOW Voltage Output OFF Current — HIGH Output OFF Current — LOW Input HIGH Current 100 Input LOW Current PE.7 3.5 V VCC = 4.MC54/74F568 • MC54/74F569 Figure A.0 mA IOL = 24 mA VOUT = 2.2 –0.5 50 – 50 20 V V µA µA µA 2.3 0.

5 4.0 5.0 9.0 11 16 11 10.0 9.0 Max 74F TA = 0 to + 70°C VCC = 5.0 9.0 5.5 4.5 11.5 12 8.0 5.0 8.0 2.5 4.0 6.MC54/74F568 • MC54/74F569 STATE DIAGRAMS MC54/74F568 0 1 2 3 0 1 MC54/74F569 2 3 4 15 10 9 11 14 13 15 4 13 14 5 6 7 8 7 6 5 12 12 11 10 9 8 COUNT DOWN COUNT UP COUNT DOWN COUNT UP AC CHARACTERISTICS 54 / 74F TA = + 25°C VCC = + 5.5 3.5 2.5 3.5 7.0 6.0 2.0 8.0 5.0 1.0 2.5 8.0 1.5 15.5 4.0 10 13.5 11 13 7.5 3.0 7.0 7.5 7.5 3.5 8.0 8.0 V ± 10% CL = 50 pF Min 60 3.0 4.0 Max Unit MHz ns ns ns ns ns ns ns ns ns ns FAST AND LS TTL DATA 4-227 .5 7.5 11 6.5 4.5 4.5 13 17.5 3.5 6.0 2.5 13.0 12.5 4.0 10 8.5 14 18.0 4.5 2.0 2.0 5.5 13 9.5 2.5 2.0 6.5 19 13.5 4.0 1.0 3.5 4.5 2.0 2.0 7.5 8.0 2.0 4. CET to CC Propagation Delay MR to On Output Enable Time OE to On Output Disable Time OE to On Min 100 3.0 Max 54F TA = – 55 to + 125°C VCC = 5.5 2.5 14.5 9.5 12.5 12.0 3.0 V ± 10% CL = 50 pF Min 85 3.0 2.5 18 12.5 2.5 4.5 4.0 3.0 2.0 8.0 2.5 2.5 2.5 3.5 4.0 10.0 2.5 15.0 V CL = 50 pF Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay CP to On (PE HIGH or LOW) Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay U/D to TC (′F568) Propagation Delay U/D to TC (′F569) Propagation Delay CP to CC Propagation Delay CEP.0 8.0 5.5 13.0 2.

HIGH or LOW SR to CP CP Pulse Width HIGH or LOW MR Pulse Width. HIGH or LOW Pn to CP Setup Time.0 6.0 3.5 ns 0 0 4.0 6.5 7.5 18.0 0 0 8.5 6.0 ns ns ns ns ns ns Max Unit FAST AND LS TTL DATA 4-228 . LOW MR Recovery Time Min 4.5 6.0 V ± 10% Min 5.5 6.MC54/74F568 • MC54/74F569 AC OPERATING REQUIREMENTS 54 / 74F TA = + 25°C VCC = + 5.0 7.5 4.0 8.0 0 0 11 9.0 3.5 13.0 Max 74F TA = 0°C to + 70°C VCC = 5.5 3. HIGH or LOW CEP or CET to CP Setup Time.0 8. HIGH or LOW SR to CP Hold Time.0 9.0 6.5 3.0 4.5 5.0 7. HIGH or LOW PE to CP Setup Time.0 4.0 0 0 4.5 ns 3. HIGH or LOW CEP or CET to CP Hold Time.0 8.5 0 0 6.5 5.0 ns 0 0 12.0 0 0 10 8.0 5.5 8.0 V Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Parameter Setup Time.5 3.0 ns 0 0 9. HIGH or LOW U/D to CP Setup Time.0 0 0 11 16. HIGH or LOW U/D to CP (F568) Setup Time.0 V ± 10% Min 4.5 10 0 0 12 10.5 11 7. HIGH or LOW U/D to CP (F569) Hold Time. HIGH or LOW PE to CP Hold Time.5 17.5 12.0 5.0 Max 54F TA = – 55°C to + 125°C VCC = 5. HIGH or LOW Pn to CP Hold Time.0 0 0 10 10 0 0 13.

• Broadside Pinout Version of F374 • Edge-Triggered D-Type Inputs • Buffered Positive Edge-Triggered Clock • 3-State Outputs for Bus Oriented Applications • ESD Protection > 4000 Volts OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL PIN ASSIGNMENT VCC O0 20 19 O1 18 O2 17 O3 16 O4 15 O5 14 O6 13 O7 12 CP 11 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 1 OE 2 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 GND 20 1 DW SUFFIX SOIC CASE 751D-03 LOGIC SYMBOL 2 3 4 5 6 7 8 9 ORDERING INFORMATION D0 11 CP D1 D2 D3 D4 D5 D6 D7 MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 1 OE O0 19 O1 18 O2 17 O3 16 O4 15 O5 14 O6 13 O7 12 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL DC Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4.0 25 — — Max 5.0 24 Unit V °C mA mA FAST AND LS TTL DATA 4-229 .MC74F574 OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS The MC74F574 is a high-speed.5 0 — — Typ 5. This device is functionally identical to the F374 except for the pinouts. low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered clock (CP) and Output Enable (OE) are common to all flip-flops.5 70 3.

2. VIN = 7. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition.2 — Unit V V V V IOH = – 3. the outputs go to the high impedance state.5 20 V V µA mA µA µA mA mA Min 2.8 – 1. With the Output Enable (OE) LOW. Not more than one output should be shorted at a time.MC74F574 FUNCTION TABLE Inputs OE L L L H H CP ↑ ↑ ↑ ↑ X Dn l h X Dn X Internal Register L H NC Dn X Outputs Operating Mode Q0–Q7 L H NC Z Z Load and read register Hold Disable outputs H = HIGH voltage level h = HIGH voltage level one set-up time prior to the Low-to-High clock transition L = LOW voltage level l = LOW voltage level one set-up time prior to the Low-to-High clock transition NC = No change X = Don’t care Z = High impedance “off” state ↑ = Low-to-High clock transition ↑ = Not a Low-to-High clock transition FUNCTIONAL DESCRIPTION The MC74F574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-state true outputs. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH IIL IOZH IOZL IOS ICCZ Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. IIN = – 18 mA VCC = MIN VCC = 4.5 V NOTES: 1. VOUT = 0 V VCC = MAX Dn – GND. use the appropriate value specified under recommended operating conditions for the applicable device type. the contents of the eight flip-flops are available at the outputs. FAST AND LS TTL DATA 4-230 .7 V VCC = MAX.7 V VCC = MAX.6 50 –50 –150 86 — — — — — — 0. OE = 4. nor for more than 1 second. The buffered clock and buffered Output Enable are common to all flip-flops.0 V VCC = MAX.7 Output LOW Voltage Input HIGH Current — Input LOW Current Output Off Current — HIGH Output Off Current — LOW Output Short Circuit Current (Note 2) Power Supply Current (All Outputs OFF) — — — – 60 — — — — — — 55 100 – 0.4 Typ — — — — Max — 0. When the OE is HIGH.75 V VCC = MIN VCC = MAX. For conditions shown as MIN or MAX. VIN = 0. Operation of the OE input does not affect the state of the flip-flops.5 V VCC = MAX. VIN = 2. VOUT = 2.0 mA 30 IOL = 24 mA Test Conditions (Note 1) Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.0 — — 2. VOUT = 0.5 V VCC = MAX.

5 8.5 1.0 5.0 1.5 3.5 2.0 74F TA = 0°C to + 70°C VCC = +5.5 2.5 9.0 5.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Setup Time.0 2.5 6.0 5.0 5.5 Unit MHz ns ns ns AC OPERATING CHARACTERISTICS 54 / 74F TA = + 25°C VCC = + 5. HIGH or LOW Dn to CP Hold Time.0 V CL = 50 pF Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay CP to On Output Enable Time Output Disable Time Min 100 2.0 5.5 1.0 9.5 1.5 3. HIGH to LOW Dn to CP CP Pulse Width HIGH or LOW Min 2.5 74F TA = 0°C to + 70°C VCC = +5.5 10.0 2.5 2.5 2.0 6.0 10.0 Typ — — — — — — Max — — — — — — Min 2.5 8.0 V ± 10% CL = 50 pF Min 70 2.0 Max — 8.0 3.5 2.0 V ± 10% CL = 50 pF Typ — — — — — — Max — — — — — — Unit ns ns ns FAST AND LS TTL DATA 4-231 .0 2.0 Typ — — — — — — — Max — 8.5 5.MC74F574 LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 CP CP Q D Q CP Q D Q CP Q D Q CP Q D Q CP Q D Q CP Q D Q CP Q D Q CP Q D Q OE O0 O1 O2 O3 O4 O5 O6 O7 AC ELECTRICAL CHARACTERISTICS 54 / 74F TA = + 25°C VCC = + 5.0 2.

0 –3. carry look-ahead for easy cascading and a U/D input to control the direction of counting. TC output is not recommended for use as a clock or asynchronous reset due to the possibility of decoding spikes.MC74F579 8-BIT BIDIRECTIONAL BINARY COUNTER (3-STATE) The MC74F579 is a fully synchronous 8-stage up/down counter with multiplexed 3-state I/O ports for bus-oriented applications. are initiated by the rising edge of the clock. 8-BIT BIDIRECTIONAL BINARY COUNTER (3-STATE) FAST™ SCHOTTKY TTL • • • • • • • • • • • Multiplexed 3-State I/O Ports For Bus-oriented Applications Built-In Cascading Carry Capability Count Frequency 115 MHz Typ Supply Current 100 mA Typ Fully Synchronous Operation U/D Pin to Control Direction of Counting Separate Pins for Master Reset and Synchronous Reset Center Power Pins to Reduce Effects of Package Inductance See F269 for 24-Pin Separate I/O Port Version See F779 for 16-Pin Version ESD Protection > 4000 Volts PIN ASSIGNMENT MR 20 SR CEP CET VCC TC 19 18 17 16 15 U/D 14 PE 13 CS 12 OE 11 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 20 1 DW SUFFIX SOIC CASE 751D-03 1 2 3 4 5 6 8 9 10 7 CP I/O0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 ORDERING INFORMATION MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC LOGIC SYMBOL 13 PE 1 18 17 11 CP CEP CET OE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 2 3 4 5 6 7 8 9 12 CS 20 MR 19 SR 14 U/D TC 15 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low TC I/On TC I/On Parameter Min 4. It features a preset capability for programmable operation. except for the case of asynchronous reset.0 20 24 Unit V °C mA mA FAST AND LS TTL DATA 4-232 . All state changes.5 0 Typ 5.5 70 –1.0 25 Max 5.

In any sequence of parameter tests.0 mA VIL = MAX VIH = MIN IOL = 20 mA IOL = 24 mA VCC = 4.5 V. TA = 25°C. IOS tests should be performed last.0 V VCC = 5 5 V VIN = 2 7 V 5. For conditions shown as MIN or MAX. For IOS testing.5 V VIL = MAX VIH = MIN VCC = 4.2 1.6 70 µA VCC = 5 5 V 5.4 I/On TC VOL VIK Output LOW Voltage I/On Input Clamp Diode Voltage I/On others IIH Input HIGH Current I/On others IIL IOZH IOZL IOS Input LOW Current OFF-State Current High-Level Voltage Applied OFF-State Current Low-Level Voltage Applied I/On –600 – 60 –80 95 105 105 –150 135 145 150 mA VCC = MAX mA Except I/On 70 20 –0.5 V VCC = 4. VIN = 0. the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. 2.5 V VCC = 4.7 V Output Short Circuit Current (Note 3) ICCH ICC Total Supply Current (total) ICCL ICCZ NOTES: 1.75 V VCC = 4. 2.0 100 V mA µA µA mA VCC = 5 5 V 5.3 3.35 0 35 0.5 V.7 VOH Output HIGH Voltage 2. FAST AND LS TTL DATA 4-233 .4 V Typ (2) Max Unit Test Conditions (Note 1) IOH = – 1.MC74F579 FUNCTION TABLE MR X X X L H H H H H H SR X X X X L H H H H H CS H L L X X L PE X H H X X L CEP X X X X X X H X L L CET X X X X X X X H L L U/D X X X X X X X X H L OE X H L X X X X X X X CP X X X X ↑ ↑ ↑ ↑ ↑ ↑ Function I/O0 to I/O7 in Hi-Z (PE disabled) I/O0 to I/O7 in Hi-Z Flip-Flop outputs appear on I/O lines Asynchronous reset for all flip-flops Synchronous reset for all flip-flops Parallel load all flip-flops Hold Hold (TC held high) Count up Count down (not LL) (not LL) (not LL) (not LL) H = High voltage level L = Low voltage level X = Don’t care ↑ = Low-to-High clock transition (not LL) = CS and PE should never both be low voltage at the same time DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) 74F Symbol Parameter Min 2.5 VOUT = 0.0 mA VIL = MAX VIH = MIN IOH = – 3. Not more than one output should be shorted at a time. VOUT = 0 V –0.7 3.5 05 V 2.7 VCC = 5.0 V. IIN = – 18 mA VIN = 5.73 – 1. Otherwise. 3.5 V. use the appropriate value specified under guaranteed operating conditions for the applicable device type. All typical values are at VCC = 5.5 V VOUT = 2.5 0.5 V VCC = MAX.5 TC 2. prolonged shorting of a HIGH output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests.5 V VIN = 7.75 V VCC = 4.3 V 3.

5 3.0 4.0 8.5 9.0 5.5 6.5 3.0 1.0 11 9.0 1.5 10.0 3.0 Max Unit MHz ns ns ns ns ns ns ns ns ns AC SETUP REQUIREMENTS 74F TA = + 25°C VCC = + 5.0 2. PE to I/On Output Enable Time to HIGH or LOW Level OE to I/On Output Disable Time to HIGH or LOW Level OE to I/On Min 100 5.5 10.0 10 10 0 0 5.0 10 10.0 9. SR or CS to CP Setup Time.5 8.5 6.0 8.0 7. SR or CS to CP Hold Time.5 3.5 5.0 1.5 5.5 3.0 4.0 3.5 10.0 5.5 3.5 11 11.5 9. HIGH or LOW I/On to CP Hold Time.0 3.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw tw(L) trec Parameter Setup Time.5 4. HIGH or LOW PE. HIGH or LOW CET. HIGH or LOW I/On to CP Setup Time. HIGH or LOW CET.0 2.5 6.0 Typ Max 74F TA = 0°C to + 70°C VCC = +5.MC74F579 AC ELECTRICAL CHARACTERISTICS 74F TA = + 25°C VCC = + 5.5 11.5 11 11 9.0 1.0 7. CEP to CP CP Pulse Width MR Pulse Width MR Recovery Time Min 3.5 9. HIGH or LOW PE.5 8.5 9.0 4.0 5.0 4.5 10.5 4.5 Typ Max Unit ns ns ns ns ns ns ns ns ns FAST AND LS TTL DATA 4-234 .5 11.5 7. CEP to CP Hold Time.0 6.5 11.0 4.0 0 0 4.0 V CL = 50 pF Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay CP to I/On Propagation Delay CP to TC Propagation Delay U/D to TC Propagation Delay CET to TC Propagation Delay MR to I/On Output Enable Time to HIGH or LOW Level CS.0 4.0 1.5 3.0 9.0 4.5 4. PE to I/On Output Disable Time to HIGH or LOW Level CS.5 5.0 9.5 6.5 8.0 1.0 V ± 10% CL = 50 pF Min 80 5.0 4.0 Typ Max 74F TA = 0°C to + 70°C VCC = +5.5 0 0 5.5 10.0 8.0 V ± 10% CL = 50 pF Min 4.0 4.5 4.5 5.5 0 0 6.0 4.5 10 10 8.5 3.

MC74F579 LOGIC DIAGRAM SR PE CE OE I/O0 LOAD CONTROL CPMR DETAIL A I/O1 DETAIL A I/O2 DETAIL A I/O3 DETAIL A I/O4 DETAIL A I/O5 DETAIL A I/O6 DETAIL A I/O7 U/D CEP CET DETAIL A DOWN UP TC TOGGLE DATA CP MR MR LOAD D CP Q Q Q Q Detail A FAST AND LS TTL DATA 4-235 .

The control function implementation allows for maximum flexibility in timing.OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS (INVERTING AND NONINVERTING) The MC74F620 is an octal bus transceiver featuring inverting 3-state buscompatible outputs in both send and receive directions. providing very good capacitive drive characteristics. • High Impedance NPN base inputs for reduced loading (70 µA in High and Low states) • Ideal for Applications which Require High Output drive and minimal bus loading • Octal Bidirectional Bus Interface • 3-State Buffer Outputs Sink 64 mA and Source 15 mA • – F620 Inverting – F623 Noninverting • ESD Protection > 4000 Volts MC74F620 MC74F623 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS (INVERTING AND NONINVERTING) FAST™ SCHOTTKY TTL 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 20 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC PIN ASSIGNMENTS VCC OEBA B0 20 19 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 VCC OEBA B0 20 19 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 F620 F623 1 2 OEAB A0 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 GND 1 2 OEAB A0 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 GND FAST AND LS TTL DATA 4-236 . The BN outputs are capable of sinking 64 mA and sourcing up to 15 mA. These octal bus transceivers are designed for asynchronous two-way communication between data busses. Thus. These devices allow data transmission from the A bus to the B bus or from B bus to A bus. The Enable inputs can be used to disable the device so that the busses are effectively isolated. The dual-enable configuration gives the MC74F620 and MC74F623 the capability to store data by the simultaneous enabling of OEBA and OEAB. Each output reinforces its input in this transceiver configuration. when both control inputs are enabled and all other data sources to the two sets of the bus lines are at high impedance. depending upon the logic levels at the Enable inputs (OEBA and OEAB). both sets of bus lines (16 in all) will remain at their last states. The MC74F623 is a non-inverting version of the MC74F620.

0 –15 24 64 Unit V °C mA mA mA mA FAST AND LS TTL DATA 4-237 .0 25 — — — — Max 5.5 0 — — — — Typ 5.MC74F620 • MC74F623 LOGIC SYMBOLS 2 A0 1 19 OEAB OEBA B0 18 B1 17 B2 16 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 1 OEAB OEBA B0 18 B1 17 B2 16 2 A0 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 F620 B3 15 B4 14 B5 13 B6 12 B7 11 19 F623 B3 15 B4 14 B5 13 B6 12 B7 11 FUNCTION TABLE Inputs OEBA L H H L OEAB L H L H F620 B data to A bus A data to B bus Z B data to A bus A data to B bus Operating Modes F623 B data to A bus A data to B bus Z B data to A bus A data to B bus H = HIGH voltage level: L = LOW voltage level: X = Don’t care: Z = High impedance “off” state GUARANTEED OPERATING RANGES Limits Symbol VCC TA IOH IOH IOL IOL DC Supply Voltage Operating Ambient Temperature Range Output Current  High Output Current  High Output Current  Low Output Current  Low An Outputs Bn Outputs An Outputs Bn Outputs Parameter 74 74 74 74 74 74 Min 4.5 70 –3.

0 mA IOL = 24 mA IOL = 64 mA VCC = MAX VCC = MAX VCC = 4.2 — — — — — 0.0 V VCC = MAX.5 V VCC = MAX.MC74F620 • MC74F623 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 74 An VOH Output HIGH Voltage Bn 74 74 74 74 VOL VOL IOZH + IIH IOZL + IIL Output LOW Voltage Output LOW Voltage Output Off Current HIGH Output Off Current LOW OEBA.8 –1. use the appropriate value specified under recommended operating conditions for the applicable device type.0 — — 2.4 2. nor for more than 1 second.7 2. OEAB Others IIL IOS Input LOW Current Output Short Circuit Current (Note 2) Non I/O Pins A0–A7 B0–B7 ICCH ICC Power Supply Current F620 ICCL ICCZ ICC Power Supply Current F623 An Bn 74 74 2.55 70 –70 20 100 1.5 V VCC = 4.3 3. VOUT = GND MAX Vout = HIGH Vout = LOW Vout = HIGH Z VCC = MAX VCC = MAX Unit V V V V V V V V V V µA µA µA µA mA µA Test Conditions (Note 1) Guaranteed as a HIGH Signal Guaranteed as a LOW Signal VCC = MIN.0 –20 –150 mA –225 92 110 92 120 mA mA VCC = MAX.3 3.75 V VCC = 4.7 2.0 mA IOH = –3. IIN = –18 mA IOH = –3.0 mA IOH = –3.4 2.5 V VCC = 4.7 V VOUT = 0.7 V VCC = 0 V.4 — 0.5 V NOTES: 1. VIN = 7.0 mA IOH = –15. VIN = 5. Not more than one output should be shorted at a time.75 V VCC = 4.35 — — — — — — — — — — — — — Max — 0.5 V VCC = MIN VCC = MIN VOUT = 2. VIN = 2.0 — — — — — — — — –60 –100 — — — — Typ — — — 3. OEAB IIH Input HIGH Current OEBA.4 3. 2. VIN = 0. FAST AND LS TTL DATA 4-238 . For conditions shown as MIN or MAX.50 0.0 mA IOH = –3.5 V VCC = MAX.

MC74F620 • MC74F623 LOGIC DIAGRAMS F620 19 OEBA OEAB 1 OEBA OEAB 1 19 F623 2 A0 18 B0 A0 2 18 B0 3 A1 17 B1 A1 3 17 B1 4 A2 16 4 B2 A2 16 B2 A3 5 15 B3 A3 5 15 B3 6 A4 14 B4 A4 6 14 B4 7 A5 13 B5 A5 7 13 B5 A6 8 12 B6 A6 8 12 B6 A7 9 11 B7 A7 9 11 B7 FAST AND LS TTL DATA 4-239 .

5 4. OEAB to Bn Parameter Min 2.0 3.0 7.5 4.5 10.5 1.5 Unit ns ns ns ns ns AC ELECTRICAL CHARACTERISTICS For F623 74F TA = +25°C VCC = +5.0 10.5 6.5 5.5 7.5 3.5 12.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Propagation Delay An to Bn Propagation Delay Bn to An Output Enable Time to High or Low level.0 2.5 74F TA = 0°C to +70°C VCC = +5.5 11.0 V ±10% CL = 50 pF Min 2.0 2.5 3.0 Typ — — — — — — — — — — — — Max 6.5 9.0 3.5 1.0 2.5 3.0 7. OEAB to Bn Output Disable Time to High or Low level.5 9.5 10.0 V ±10% CL = 50 pF Min 2.5 5.5 7.5 1.5 7.5 9.5 10.5 3.0 3.5 3.0 2.5 6.5 3.5 11.0 10.5 11.0 1.0 3.0 Unit ns ns ns ns ns ns FAST AND LS TTL DATA 4-240 .0 3.0 7.0 8.0 2.0 10. OEBA to An Output Disable Time to High or Low level.MC74F620 • MC74F623 AC ELECTRICAL CHARACTERISTICS For F620 74F TA = +25°C VCC = +5.5 4.0 74F TA = 0°C to +70°C VCC = +5.5 3.0 11.0 11.0 4.5 2.5 5.5 3.5 10.5 1.5 8.0 9.0 10.5 10. OEAB to Bn Output Disable Time to High or Low level.5 2.0 Typ — — — — — — — — — — — — Max 5.0 1.0 V CL = 50 pF Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Parameter Propagation Delay An to Bn and Bn to An Output Enable Time to High or Low level.5 7.5 9.0 1.0 2.5 6. OEAB to Bn Min 2. OEBA to An Output Enable Time to High or Low level.0 Typ — — — — — — — — — — Max 6.0 1.5 7.5 1.0 10.0 9.5 Typ — — — — — — — — — — Max 7.5 10. OEBA to An Output Disable Time to High or Low level.0 3.0 4.5 7.0 6.0 2.5 4.5 4. OEBA to An Output Enable Time to High or Low level.

B0–B7. The device features an Output Enable (OE) input for easy cascading and Transmit/Receive (T/R) input for direction control. OCTAL BUS TRANSCEIVER. INVERTING WITH 3-STATE OUTPUTS The MC74F640 is an octal transceiver featuring inverting 3-state bus compatible outputs in both transmit and receive directions. The B port outputs are capable of sinking 64 mA and sourcing 15 mA. have been designed to prevent output bus loading if the power is removed from the device. INVERTING WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL • High-Impedance NPN Base Inputs for Reduced Loading • Ideal for Applications which Require High-Output Drive and Minimal • • • • Bus Loading Inverting Version of F245 Octal Bidirectional Bus Interface 3-State Buffer Outputs Sink 64 mA and Source 15 mA ESD Sensitive — 4000 V HBM J SUFFIX CERAMIC CASE 732-03 1 (70 µA in High and Low States) 20 PIN ASSIGNMENT VCC OE 20 19 B0 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 20 1 N SUFFIX PLASTIC CASE 738-03 20 1 DW SUFFIX SOIC CASE 751D-03 1 T/R 2 A0 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 GND ORDERING INFORMATION MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC FUNCTION TABLE Inputs OE L L H T/R L H X Outputs Bus B data to Bus A Bus A data to Bus B Z H = High Voltage Level L = Low Voltage Level X = Don’t Care Z = High Impedance “Off” State LOGIC SYMBOL 2 3 4 5 6 7 A5 8 9 A0 A1 1 19 T/R OE B0 B1 18 17 A2 A3 A4 A6 A7 B2 B3 B4 16 15 14 B5 13 B6 B7 12 11 FAST AND LS TTL DATA 4-241 . providing very good capacitive drive characteristics.MC74F640 OCTAL BUS TRANSCEIVER. The 3-state outputs.

0 mA IOH = –15 mA IOL = 24 mA IOL = 64 mA VCC = MAX VCC = MAX VCC = 4.8 –1. Not more than one output should be shorted at a time.0 0.75 V VCC = 4. T/R IIH Input HIGH Current OE. VIN = 5.5 V VCC = MAX. FAST AND LS TTL DATA 4-242 .4 2.0 25 Max 5.4 3. For conditions shown as MIN or MAX. VOUT = GND MAX Vout = HIGH T/R = 4. VIN = 2.0 –15 24 64 Unit V °C mA mA mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 74 An VOH Output HIGH Voltage Bn 74 74 74 74 VOL VOL IOZH + IIH IOZL + IIL Output LOW Voltage Output LOW Voltage Output Off Current HIGH Output Off Current LOW OE.0 0.5 V VCC = MIN VCC = MIN VOUT = 2. 2. IIN = –18 mA IOH = –3.5 V VCC = 4.75 V VCC = 4. VIN = 7.5 V Vout = HIGH Z VCC = MAX 3.MC74F640 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOH IOL IOL DC Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — High Output Current — Low Output Current — Low An Outputs Bn Outputs An Outputs Bn Outputs Parameter 74 74 74 74 74 74 Min 4.0 mA IOH = –3.3 3.0 mA IOH = –3.5 V NOTES: 1.7 V VOUT = 0. T/R Others IIL IOS Input LOW Current Output Short Circuit Current2 OE.5 V VCC = 4.55 70 – 70 40 100 1.7 V VCC = 0 V.5 0.4 2. nor for more than 1 second.35 0. VIN = 0.5 70 –3.0 mA IOH = –3.0 – 40 –150 mA – 225 85 120 100 mA VCC = MAX.7 2.2 Typ Max Unit V V V V V V V V V V µA µA µA µA mA µA Test Conditions1 Guaranteed as a HIGH Signal Guaranteed as a LOW Signal VCC = MIN.0 V VCC = MAX. T/R A0 – A7 B0 – B7 ICCH ICC Power Supply Current ICCL ICCZ – 60 –100 An Bn 74 74 2.5 0 Typ 5.3 3.4 Min 2.7 2.5 V Vout = LOW T/R = 0 V OE = 4. use the appropriate value specified under recommended operating conditions for the applicable device type.5 V VCC = MAX.

5 1.0 1.0 V CL = 50 pF RL = 500 Ω Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay An to Bn.5 13 12 9.0 7.0 7.0 Typ Max 7.0 V ±10% CL = 50 pF RL = 500 Ω Typ Max 8.0 1.0 5.0 3.0 74F TA = 0°C to +70°C VCC = +5.5 Unit ns ns ns FAST AND LS TTL DATA 4-243 . Bn to An Output Enable Time to High or Low Level Output Disable Time to High or Low Level Min 2.MC74F640 LOGIC DIAGRAM A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 OE 19 T/R 1 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7 VCC = PIN 20 GND = PIN 10 AC ELECTRICAL CHARACTERISTICS 74F TA = +25°C VCC = +5.0 Min 2.0 5.0 1.0 1.5 1.0 11 11 8.5 6.5 6.0 3.

MC54/74F646 MC54/74F648 OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL • • • • Independent Registers for A and B Multiplexed Real-Time and Stored Data Choice of True (F646) and Inverting (F648) Data Paths 3-State Outputs PIN ASSIGNMENTS VCC CPBA SBA OE 24 23 22 21 B0 20 B1 19 B2 18 B3 17 B4 16 B5 15 B6 14 B7 13 24 1 J SUFFIX CERAMIC CASE 758-01 F646 24 1 N SUFFIX PLASTIC CASE 724-03 1 2 3 CPAB SAB DIR 4 A0 5 A1 B0 20 6 A2 B1 19 7 A3 B2 18 8 A4 B3 17 9 A5 B4 16 10 A6 B5 15 11 12 A7 GND B6 14 B7 13 24 1 VCC CPBA SBA OE 24 23 22 21 DW SUFFIX SOIC CASE 751E-03 F648 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 1 2 3 CPAB SAB DIR 4 4 A0 5 5 A1 6 6 A2 7 8 7 A3 9 8 A4 10 9 A5 11 A7 10 A6 11 12 A7 GND 4 5 6 7 8 9 10 11 A7 LOGIC SYMBOLS 1 2 3 23 22 21 A A1 A2 CPAB 0 SAB DIR CPBA SBA OE B0 B1 B2 20 19 18 A3 A4 A5 A6 F646 B3 B4 17 16 B5 B6 B7 15 14 13 1 2 3 23 22 21 A A1 A2 CPAB 0 SAB DIR CPBA SBA OE B0 B1 B2 20 19 18 A3 A4 A5 A6 F648 B3 B4 17 16 B5 B6 B7 15 14 13 This document contains information on a product under development. Output Enable (OE) and DIR pins are provided to control the transceiver function. data present at the high impedance port may be stored in either the A or the B register or in both. A data may be stored in the B register and/or B data may be stored in the A register. Motorola reserves the right to change or discontinue this product without notice. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. The select controls can multiplex stored and real-time (transparent mode) data. In the transceiver mode. and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. In the isolation mode (OE HIGH). FAST AND LS TTL DATA 4-244 . The direction control determines which bus will receive data when the enable OE is Active LOW.Product Preview OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS These devices consist of bus transceiver circuits with 3-state D-type flip-flops.

i..5 –55 0 — — — — Typ 5. 74 54 74 54 74 54 74 Min 4. H = HIGH voltage level L = LOW voltage level X = Don’t Care ↑ = Low-to-High transition GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter DC Supply Voltage Operating Ambient Temperature Range Output Current  High Output Current  Low 54. data at the *bus pins will be stored on every low-to-high transition of the appropriate clock inputs.e. Data input functions are always enabled.MC54/74F646 • MC54/74F648 FUNCTION TABLE Inputs OE bar H H H H L L L L L L L L DIR X X X X H H H H L L L L CPAB H or L ↑ X ↑ X ↑ H or L ↑ X X X X CPBA H or L X ↑ ↑ X X X X X ↑ H or L ↑ SAB X X X X L L H H X X X X SBA X X X X X X X X L L H H Data I/O* Operation/Function Operation/F nction A0–A7 Input Input Input Input Input Input Input Input Output Output Output Output B0–B7 Input Input Input Input Output Output Output Output Input Input Input Input Isolation Store An Data in A Register Store Bn Data in B Register Store An/Bn Data in A/B Register An to Bn — Real Time (Transparent Mode) Store An Data in A Register A Register to Bn (Stored Mode) Clock An Data to Bn and into A Register Bn to An — Real Time (Transparent Mode) Store Bn Data in B Register B Register to An (Stored Mode) Clock An Data to Bn and into B Register *The data output function may be enabled or disabled by various signals at the OE bar and DIR inputs.0 25 25 — — — — Max 5.5 125 70 –12 –15 48 64 Unit V °C mA mA FAST AND LS TTL DATA 4-245 .

MC54/74F646 • MC54/74F648 LOGIC DIAGRAM F646 OE DIR CPBA SBA SAB CPAB 1 OF 8 CHANNELS C0 A0 D0 B0 D0 C0 TO 7 OTHER CHANNELS FAST AND LS TTL DATA 4-246 .

MC54/74F646 • MC54/74F648 LOGIC DIAGRAM F648 OE DIR CPBA SBA SAB CPAB 1 OF 8 CHANNELS C0 A0 D0 B0 D0 C0 TO 7 OTHER CHANNELS FAST AND LS TTL DATA 4-247 .

Bn) Parameter Min 2. nor for more than 1 second.7 V VCC = MAX.MC54/74F646 • MC54/74F648 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54/74 74 VOH Output HIGH Voltage An. Bn 54 74 54 VOL Output LOW Voltage An.7 V VCC = MAX.8 –1.0 mA IOH = –15.5 V VCC = 4.7 2.0 2. VIN = 5.55 0. VOUT = 0.0 V VCC = MAX. VIN = 0.0 — — — — — — — — –100 — — — Typ — — — — — — — — — — — — — — — — — — — Max — 0.0 –600 70 –650 –225 135 150 150 mA Unit V V V V V V V V V µA µA mA µA µA µA mA Test Conditions (Note 1) Guaranteed as a HIGH Signal Guaranteed as a LOW Signal VCC = MIN. Bn) IIL IIH + IOZH IIL + IOZL IOS Input LOW Current Output Leakage Current Output Leakage Current Output Short Circuit Current (Note 2) ICCH ICC Power Supply Current ICCL ICCZ Non I/O Pins I/O (An. VOUT = GND Vout = HIGH Vout = LOW Vout = HIGH Z VCC = MAX NOTES: 1.55 20 100 1.2 — — — — 0.5 V VCC = 4. For conditions shown as MIN or MAX. 2.5 V VCC = MAX VOUT = 2.75 V VCC = 4. VIN = 7.0 mA IOL = 48 mA IOL = 64 mA VCC = 4. IIN = –18 mA IOH = –3. FAST AND LS TTL DATA 4-248 .5 V VCC = MAX.4 2.5 V VCC = MIN VCC = MIN VCC = MAX. Not more than one output should be shorted at a time. Bn 74 Non I/O Pins IIH Input HIGH Current Non I/O Pins I/O (Aa. VIN = 2.0 — — 2.5 V VCC = MAX. Bn) I/O (An.0 mA IOH = –3. use the appropriate value specified under recommended operating conditions for the applicable device type.0 mA IOH = –12.

0 2.0 1.5 74F TA = 0°C to +70°C VCC = +5.0 2.0 2.5 8.0 1.5 7.0 6.5 Unit MHz ns ns ns ns ns ns ns ns AC OPERATING REQUIREMENTS 54/74F TA = +25°C VCC = +5.0 V CL = 50 pF RL = 500 Ω Symbol ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Setup Time.0 54F TA = –55°C to +125°C VCC = +5.0 2.0 0.0 8.0 5.0 1.0 2.0 5.0 Max — 8.0 2.0 2.5 8.0 10.0 7.5 9. HIGH or LOW Bus to Clock Clock Pulse Width HIGH or LOW Min 4.0 0.0 0.0 5.5 7.5 8.0 7.0 1.0 5.0 2.0 1.0 8.0 1.0 0.0 7.0 7.5 9.5 9.0 10.0 1.0 1.0 4.0 4.0 2.0 2.5 8.0 2.0 2.0 1.0 2.5 8.5 7.0 7.0 2. HIGH or LOW Bus to Clock Hold Time.5 8.0 0.0 Max — 8.0 2.5 7.5 9.0 2.0 2.5 8.0 2.0 V ±10% CL = 50 pF RL = 500 Ω Min 5.0 7.5 9.0 8.0 5.0 9.0 2.0 7.0 2.0 9.0 6.0 Max — 7.0 1.0 1.0 2.0 2.5 9.0 7.0 9.0 2.5 9.0 9.5 9.0 2.0 9.0 2.0 4.0 V ±10% CL = 50 pF RL = 500 Ω Min 75 2.0 10.5 8.0 1.0 1.MC54/74F646 • MC54/74F648 AC ELECTRICAL CHARACTERISTICS 54/74F TA = +25°C VCC = +5.0 V ±10% CL = 50 pF RL = 500 Ω Min 5.0 V ±10% CL = 50 pF RL = 500 Ω Min 90 2.5 7.0 0.0 1.5 7.0 7.0 7.0 2.0 1.0 Max — — — — — — 54F TA = –55°C to +125°C VCC = +5.0 4.0 Max — — — — — — Unit ns ns ns FAST AND LS TTL DATA 4-249 .0 V CL = 50 pF RL = 500 Ω Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay Clock to Bus Propagation Delay Bus to Bus (F646) Propagation Delay Bus to Bus (F648) Propagation Delay SBA or SAB to An or Bn Output Enable Time OE to An or Bn Output Disable Time OE to An or Bn Output Enable Time DIR to An or Bn Output Disable Time DIR to An or Bn Min 100 2.0 2.0 1.0 Max — — — — — — 74F TA = 0°C to +70°C VCC = +5.0 1.0 1.

Sink 64 mA and Source 15 mA • 15 mA Source Current • Input Diodes for Termination Effects • Glitchless Outputs During Power Up and Power Down • High Impedance Outputs During Power Off • ESD Protection > 4000 Volts PIN ASSIGNMENT OE 24 B0 23 B1 22 B2 21 B3 GND GND B4 20 19 18 17 B5 16 B6 15 B7 PARITY 14 13 24 1 OCTAL BIDIRECTIONAL TRANSCEIVER WITH 8-BIT PARITY GENERATOR CHECKER (3-STATE OUTPUTS) FAST™ SCHOTTKY TTL 24 1 J SUFFIX CERAMIC CASE 758-01 24 1 N SUFFIX PLASTIC CASE 724-03 DW SUFFIX SOIC CASE 751E-03 ORDERING INFORMATION MC74FXXXAJ/BJ MC74FXXXAN/BN MC74FXXXADW/BDW Ceramic Plastic SOIC 1 T/R 2 A0 3 A1 4 A2 5 A3 6 8 7 A4 VCC A5 9 A6 10 11 12 A7 ODD/ ERROR EVEN LOGIC SYMBOL 2 3 4 5 6 8 9 10 1 24 11 A0 A1 T/R OE EVEN/ODD B0 B1 A2 A3 A4 A5 A6 A7 PARITY ERROR 13 12 B2 B3 B4 B5 B6 B7 23 22 21 20 17 16 15 14 FAST AND LS TTL DATA 4-250 . ERROR. Transmit (active HIGH) enables data from A ports to B ports. The Transmit/Receiver (T/R) input determines the direction of the data flow through the bidirectional transceivers. These devices are intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 24 mA at the A ports and 64 mA at the B ports. Receive (active LOW) enables data from B ports to A ports.MC74F657A. • High-Impedance NPN Base Input for Reduced Loading (20 µA in HIGH and LOW States) • Ideal in Applications Where High Output Drive and Light Bus Loading are Required (IIL is 20 µA versus Fast std of 600 µA) • Combines F245 and F280A Functions in One Package • 3-State Outputs • B Outputs. The A and B options are faster versions of the F657 and contain eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker.B OCTAL BIDIRECTIONAL TRANSCEIVER WITH 8-BIT PARITY GENERATOR CHECKER (3-STATE OUTPUTS) The MC74F657A and MC74F657B are Octal Bidirectional Transceivers with an 8-bit parity Generator/Checker and 3-state outputs. PARITY.

7 Don’t Care H = HIGH Voltage Level.5 70 –3.0/–15 24/64 Unit V °C mA mA FUNCTION TABLE Number of Inputs That are High OE L L L L L L T/R H H L L L L Inputs Even/Odd H L H H L L Input/Output Parity H L H L H L Error Z Z H L L H Outputs Outputs Mode Transmit Transmit Receive Receive Receive Receive 0. 6.MC74F657A. 5. B GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4. 4. Z = HIGH impedance state. 3. L = LOW Voltage Level. FAST AND LS TTL DATA 4-251 .5 0 Typ 5. 2. X = Don’t Care. 8 Number of Inputs That are High OE L L L L L L H T/R H H L L L L X Inputs Even/Odd H L H H L L X Input/Output Parity L H H L H L Z Error Z Z L H H L Z Outputs Outputs Mode Transmit Transmit Receive Receive Receive Receive Z 1.0 25 Max 5.

7 µA VCC = MAX. VOUT = 0. 2. FAST AND LS TTL DATA 4-252 .5 V VCC = 4. VIN = 0 5 V MAX 0. VOUT = 0.0 V VCC = 5. ERROR 74 74 74 74 2.5 V.5 V IOH = –15 mA IOL = 24 mA IOL = 64 mA VCC = MIN T/R. OE. VIN = 5.4 V V V µA IOH = –3. nor for more than 1 second. VOUT = 2.4 0.7 V 1.7 2.73 Parameter Min 2. PARITY EVEN/ODD T/R.5 V VCC = MAX. For conditions shown as MIN or MAX. Bn Outputs. OE Off-State Current HIGH Level Voltage Applied Off-State Current LOW Level Voltage Applied Off-State Output Current.0 0. IIN = –18 mA VCC = 4.2 Typ Max Unit V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.8 –1.0 mA 30 –0. Low-Level Voltage Applied Output Short Circuit Current (Note 2) ERROR –50 An Outputs PARITY.7 V IOS NOTES: 1. VOUT = 0 V A0–A7 B0–B7 B0 B7 PARITY –40 70 µA –70 50 µA VCC = MAX. Not more than one output should be shorted at one time.5 V VCC = MAX.0 0. B DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage All Outputs VOH Output O t t HIGH V lt Voltage B0–B7 PARITY. OE EVEN/ODD IIL IIH +IOZH IIL +IOZL IOZH IOZL Input LOW Current T/R.4 V 2.75 V VCC = 4. High-Level Voltage Applied Off-State Output Current. VOUT = 2.35 0. VIN = 5. VIN = 2 7 V MAX 2.0 mA IIH Input HIGH Current B0–B7. VIN = 7.5 0. EVEN/ODD A0–A7 VCC = 0 V.0 20 40 –20 µA 3.5 V VCC = MAX.5 V.MC74F657A.55 100 2. ERROR ICCH ICC Total Supply Current ICCL ICCZ –60 –100 90 106 98 –150 mA –225 135 150 145 mA VCC = MAX VCC = MAX. ERROR A0–A7 VOL Output LOW Voltage B0–B7 PARITY. use appropriate value specified under recommended operating conditions for the applicable device type.5 V VCC = 5.5 VCC = MAX.

5 7.0 9.5 4.5 4.0 Max 7.0 2.5 6.0 6.0 4.5 6.5 7.0 2.5 4.0 13 13 10.0 4.0 2.5 Unit ns ns ns ns ns ns ns FAST AND LS TTL DATA 4-253 .0 8.5 18 18 14 14 8.0 7.5 7.5 16 16 12 12 8.0 5.0 2.5 4.0 2.5 15 15 11 11 7.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay An to Bn or Bn to An Propagation Delay An to PARITY Propagation Delay EVEN/ODD to PARITY.0 Typ Max 6.0 2. ERROR Propagation Delay Bn to ERROR Propagation Delay PARITY to ERROR Output Enable Time to HIGH or LOW Level Output Disable Time from HIGH or LOW Level Min 2.0 6.0 7.5 6.5 8.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay An to Bn or Bn to An Propagation Delay An to PARITY Propagation Delay EVEN/ODD to PARITY.0 Max 6.0 2. B F657A AC ELECTRICAL CHARACTERISTICS 74F TA = +25°C VCC = +5.0 2.0 7.0 4.5 4.0 7.0 2.0 74F TA = 0°C to +70°C VCC = +5.5 Unit ns ns ns ns ns ns ns F657B AC ELECTRICAL CHARACTERISTICS 74F TA = +25°C VCC = +5.5 13 13 8.0 Typ Max 7.5 10.0 7.0 6.5 4.0 11.0 4.0 10 8.0 5.5 2.0 2.5 2.0 4.5 11.5 14 14 11 11.0 8.0 6.0 6. ERROR Propagation Delay Bn to ERROR Propagation Delay PARITY to ERROR Output Enable Time to HIGH or LOW Level Output Disable Time from HIGH or LOW Level Min 2.0 7.5 19 19 15 15 9.0 3.0 2.MC74F657A.0 2.0 3.5 7.0 2.0 6.0 2.5 6.0 2.0 2.0 2.0 74F TA = 0°C to +70°C VCC = +5.0 4.5 3.5 6.0 5.0 V ± 10% CL = 50 pF Min 2.0 4.5 7.0 6.5 6.5 4.0 2.0 V ± 10% CL = 50 pF Min 2.0 3.

MC74F657A. B LOGIC DIAGRAM T/R OE A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 EVEN/ODD PARITY ERROR FAST AND LS TTL DATA 4-254 .

All control functions (hold.5 0 Typ 5. The TC output is not recommended for use as a clock or asynchronous reset due to the possibility of decoding spikes.MC74F779 8-BIT BIDIRECTIONAL BINARY COUNTER (3-STATE) The MC74F779 is a fully synchronous 8-stage up/down counter with multiplexed 3-state I/O ports for bus-oriented applications. The device also features carry look-ahead for easy cascading. count up. When CET is High the data outputs are held in their current state and TC is held high.0 mA Unit V °C IOL FAST AND LS TTL DATA 4-255 .0 24 mA Min 4. count down. S1). synchronous load) are controlled by two mode pins (S0. • Multiplexed 3-State I/O Ports For Bus-oriented Applications • Built-In Look-Ahead Carry Capability • Count Frequency 145 MHz Typ • Supply Current 90 mA Typ • Fully Synchronous Operation • Separate Pins for Master Reset and Synchronous Reset • Center Power Pins to Reduce Effects of Package Inductance • See F269 for 24-Pin Separate I/O Port Version • See F579 for 20-Pin Version • ESD Protection > 4000 Volts PIN ASSIGNMENT I/O0 16 CP 15 CET 14 VCC 13 TC 12 S0 11 S1 10 OE 9 16 1 8-BIT BIDIRECTIONAL BINARY COUNTER (3-STATE) J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 1 I/O1 2 I/O2 3 I/O3 4 GND 5 I/O4 6 I/O5 7 I/O6 8 I/O7 ORDERING INFORMATION MC74FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 11 S0 14 15 9 CET CP OE 10 S1 TC 12 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 2 3 4 5 6 7 8 9 GUARANTEED OPERATING RANGES Symbol VCC TA IOH Supply Voltage Operating Ambient Temperature Range Output Current — High I/O0–I/O7 TC Output Current — Low I/O0–I/O7 TC 74 20 Parameter 74 74 74 –1.0 25 Max 5. All state changes are initiated by the rising edge of the clock.5 70 –3.

0 mA VIL = MAX VIH = MIN IOH = –3.75 V VCC = 4.73 –1.75 V VCC = 4.MC74F779 FUNCTION TABLE S1 X X L (not LL) H L H = High voltage level L = Low voltage level X = Don’t care ↑ = Low-to-High clock transition (not LL) = S1 and S2 should never be Low voltage level at the same time in the hold mode only.7 VOH Output HIGH Voltage 2.5 V VCC = MAX.5 V VOUT = 2. For conditions shown as MIN or MAX.7 3.5 VOUT = 0.0 100 V mA µA µA VCC = 5 5 V 5. Not more than one output should be shorted at a time.6 70 µA VCC = 5 5 V 5. TA = 25°C. VOUT = 0 V –0. IIN = –18 mA VIN = 5. S0 X X L CET X X X H OE H L H X X X CP X X ↑ ↑ ↑ ↑ I/Oa to I/Oh in Hi-Z Operating Mode Flip-flop outputs appear on I/O lines Parallel load all flip-flops Hold (TC held High) Count up Count Down L H L L DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) 74F Symbol Parameter TC 2. use the appropriate value specified under guaranteed operating conditions for the applicable device type.35 0 35 0. FAST AND LS TTL DATA 4-256 .7 VCC = 5.5 V VIL = MAX VIH = MIN VCC = 4. VIN = 0.4 Min 2.5 V Typ (Note 2) Max Unit Test Conditions (Note 1) IOH= –1. 2. 2.7 V mA NOTES: 1. 3.5 V VCC = 4.5 V VCC = 4.3 V 3.0 mA VIL= MAX VIH = MIN IOL = 20 mA IOL = 24 mA VCC = 4.5 V.4 I/On TC VOL VIK Output LOW Voltage I/On Input Clamp Diode Voltage I/On others IIH Input HIGH Current I/On others IIL IOZH IOZL IOS Input LOW Current OFF-State Current High-Level Voltage Applied OFF-State Current Low-Level Voltage Applied Output Short Circuit Current (Note 3) ICCH ICC Total Supply Current (total) ICCL ICCZ I/On –600 –60 –80 82 91 97 –150 116 128 136 mA VCC = MAX mA Except I/On 70 20 –0.0 V. All typical values are at VCC = 5.5 V.5 05 V 2.5 V VIN = 7.3 3.0 V VCC = 5 5 V VIN = 2 7 V 5.5 V.2 1.5 0.

5 7.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Set-up time.0 5.0 9.0 V ±10% CL = 50 pF Min 80 4. HIGH or LOW CET to CP Hold time.0 5.5 4.5 7.0 2.5 0 0 4.5 1.0 0 0 8.0 6.0 10. HIGH or LOW CET to CP Set-up time.0 V CL = 50 pF Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay CP to I/On Propagation Delay CP to TC Propagation Delay CET to TC Enable Time from High or Low Level Disable Time from High or Low Level Min 125 4.0 Typ Max 74F TA = 0°C to +70°C VCC = +5.5 4.0 3.5 2.5 8.0 4.0 1.0 6.5 4.5 5.0 1. HIGH or LOW I/On to CP Hold time.0 1.5 0 0 8.0 V ±10% CL = 50 pF Min 5.5 9.0 5.5 4.0 8.5 2.5 10.0 Typ Max 74F TA = 0°C to +70°C VCC = +5.0 2.0 6.5 8.MC74F779 AC ELECTRICAL CHARACTERISTICS 74F TA = +25°C VCC = +5.0 Typ Max Unit ns ns ns ns ns ns ns FAST AND LS TTL DATA 4-257 .0 9.5 3.0 9.0 5.5 8.0 1.5 7.0 5.0 2.0 4.5 2.0 Max Unit MHz ns ns ns ns ns AC SETUP REQUIREMENTS 74F TA = +25°C VCC = +5.5 4.5 5. HIGH or LOW Sn to CP Hold time.0 11 11 10 10 7. HIGH or LOW Sn to CP Clock Pulse Width Min 5.0 8.0 8. HIGH or LOW I/On to CP Set-up time.5 1.5 4.0 0 0 4.

MC74F779 LOGIC DIAGRAM S0 S1 LOAD CONTROL UP DOWN OE I/O0 CP DETAIL A I/O1 DETAIL A I/O2 DETAIL A I/O3 DETAIL A I/O4 DETAIL A I/O5 DETAIL A I/O6 DETAIL A DETAIL A I/O7 CET TC TOGGLE DATA CP MR LOAD D CP Q Q Q Q Detail A FAST AND LS TTL DATA 4-258 .

With a buffered clock (CP) input that is common to all flip-flops. providing multiple outputs that are synchronous. 1994 REV 3 . quad D-type flip-flop featuring separate D-type inputs. the F803 is useful in high-frequency systems as a clock driver. and inverting outputs with closely matched propagation delays.MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document from Logic Marketing Clock Driver Quad D Type Flip Flop MC74F803 CLOCK DRIVER QUAD D-TYPE FLIP-FLOP WITH MATCHED PROPAGATION DELAYS With Matched Propagation Delays The MC74F803 is a high-speed. Inc.0 25 — — Max 5.5 70 –20 24 Unit V °C mA mA 8 1 D SUFFIX SOIC CASE 751A-03 LOGIC SYMBOL 4 D0 CP O0 O1 O2 O3 5 D1 10 D2 11 D3 LOGIC DIAGRAM D0 CP CP D Q CP D Q CP D Q CP D Q D1 D2 D3 3 VCC = PIN 14 GND = PINS 1 AND 7 NC = PINS 2 AND 13 6 9 12 O0 O1 O2 O3 11/93 © Motorola. • • • • Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Matched Outputs for Synchronous Clock Driver Applications Outputs Guaranteed for Simultaneous Switching Pinout: 14-Lead Plastic (Top View) VCC 14 NC 13 O3 12 D3 11 D2 10 O2 9 CP 8 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 1 GND 2 NC 3 O0 4 D0 5 D1 6 O1 7 GND 14 GUARANTEED OPERATION RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Min 4. low-power. the duty cycles of the output waveforms in a clock driver application are symmetrical within 1.0 to 1. Because of the matched propagation delays.5 nanoseconds.5 0 — — Typ 5.

at most. O3 Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Variation (see Note 3) Propagation Delay Skew |tPLH Actual – tPHL Actual| for O1 Only Propagation Delay Skew |tPLH Actual – tPHL Actual| for O0. 1 nanosecond.0 — — 2. the IOH specification at 2.5 — — IIH IIL IOS ICC Input HIGH Current Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current — — 70 mA VCC = MAX — — –60 Typ — — — — 0. The buffered clock is common to all flip-flops and the following specifications allow for outputs switching simultaneously. 2. For conditions such as MIN or MAX. and O3 outputs vary by at most 1. see Note 1) CL = 50 pF Symbol fmax tPLH tPHL tPv tps O1 tps O0. O3 (0. capacitive load.8 to 2.0 1.5 20 100 –0.5 volts is guaranteed to be at least – 20 milliamps. O3 tos trise.. Not more than one output should be shorted at a time. O2. and number of outputs switching simultaneously) the variation from device to device is guaranteed to be less than or equal to the maximum.5 3.35 — — — — Max — 0.0 V) Rise/Fall Time for O0.5 1. For a given set of conditions (i.5 V VOUT = 0 V VCC = MIN VCC = 4. O2.7 V VIN = 7.0 V) Parameter Min 70 3.8 to 2. O2. tfall O0.0 V VIN = 0. 3. and the LOW-to-HIGH and HIGH-toLOW propagation delays of the O1 output vary by. the device is ideal for use as a divideby-two driver for high-frequency clock signals that require symmetrical duty cycles. 1. Where tp On and tp Om are the actual propagation delays (any combination of high or low) for two separate outputs from a given high transition of CP.MC74F803 FUNCTIONAL DESCRIPTION The F803 consists of four positive edge-triggered flip-flops with individual D-type inputs and inverting outputs.5 4.e.5 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MAX * Normal test conditions for this device are all four outputs switching simultaneously. O2.0 V ± 10%. In addition. the output-to-output skew is a maximum of 1.5 Unit MHz ns ns ns ns ns ns ns 1.0 3. The maximum frequency of the clock input is 70 megahertz. 2.5 nanoseconds.5 3. temperature.0 1.8 – 1. O2.6 –150 mA mA Unit V V V V V µA Test Conditions* Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –20 mA IOL = 24 mA VIN = 2. AC CHARACTERISTICS (TA = 0 to 70°C.0 — — — — — — Max — 7. Two outputs of the 74F803 can be tied together and the IOH doubles. use the appropriate value specified under guaranteed operating ranges. nor for more than 1 second. VCC.0 2. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Min 2. If their inputs are identical. The test conditions used are all four outputs switching simultaneously. tfall O1 trise. MOTOROLA 299 TIMING SOLUTIONS BR1333 — REV 4 . These outputs are very useful as clock drivers for circuits with less stringent requirements. multiple outputs can be tied together and the IOH is commensurately increased.5 nanoseconds.0 2. Therefore. VCC = 5.0 2. The AC characteristics described above (except for O1) are also guaranteed when two outputs are tied together. O3 Output to Output Skew (see Note 2) |tp On – tp Om| Rise/Fall Time for O1 (0.0 4. The four flip-flops store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition.5 CL = 100 pF Min 50 3.2 — 0.0 — — — — — — Max — 10 4. Finally. The difference between the LOW-toHIGH and HIGH-to-LOW propagation delays for the O0.

0 — — — — CL = 100 pF Min 4.0 6.0 — 2.0 3.0 Max — — 12 — — — — Unit ns ns ns ns The combination of the setup time (ts) requirement and maximum propagation delay (tp) are guaranteed to be within this limit for all conditions.0 — 2. HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW Parameter Min 3.0 8.0 7.0 V ± 10%) CL = 50 pF Symbol ts(H) ts(L) tf th(H) th(L) tw(H) tw(L) Setup Time. 74F803 INTERFACE AS CLOCK TO MC68020 SYSTEM MC68020/MC68030 E1 CLK VCC 33CLK1 14 MC74F803 4 5 10 74F04 1 2 11 1 D0 D1 D2 D3 CP 8 33CLK CLK 66 MHz O0 O1 O2 O3 3 6 9 33CLK2 (40 mA OUTPUT DRIVE) 12 7 RT C2 MC68881/MC68882 CLK VCC RU TIMING SOLUTIONS BR1333 — REV 4 MOTOROLA 300 .0 8.0 4.0 2. HIGH or LOW Dn to CP tp + ts (see Note) Hold Time. APPLICATION NOTE The closely matched outputs of the MC74F803 provide an ideal interface for the clock input of Motorola’s high-frequency microprocessors.0 2.MC74F803 AC OPERATING REQUIREMENTS (TA = 0 to 70°C.0 Max — — 9. VCC = 5.

115 0.010) M N T A S M J 14 PL 0.92 3.040 -TSEATING PLANE K F G D 14 PL 0.052 0.25 (0.039 A F C N H G D SEATING PLANE NOTE 4 L J K M D SUFFIX SOIC PACKAGE CASE 751A-02 -A14 8 -B1 7 P 7 PL 0. 3. DIM F MAY NARROW TO 0.750 0.19 0.75 3. NEW STANDARD 646-06.62 BSC ° ° 15 0 1. 3.785 0.010) M T B S N SUFFIX PLASTIC PACKAGE CASE 646-06 14 8 B 1 7 NOTES: 1.18 7.770 0.MC74F803 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 632-08 8 -A14 -B1 7 C L NOTES: 1. 1982. DIMENSIONING AND TOLERANCING PER ANSI Y14.80 6. 3.100 BSC 0. 751A-01 IS OBSOLETE.100 BSC 0. ROUNDED CORNERS OPTIONAL.337 0.75 0.25 1.5M. MAXIMUM MOLD PROTRUSION 0. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.229 0.78 2.008 0.095 0.015 0.054 0. 2.01 INCHES MIN MAX 0.10 0.69 0.065 0.35 1.280 0. 5. DIMENSION “L” TO CENTER OF LEADS WHEN FORMED PARALLEL.020 0. 6.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.5M.23 5.015 0.40 2.54 BSC 0.69 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.019 G C SEATING PLANE R X 45° D 14 PL 0.260 0.055 0. CONTROLLING DIMENSION: INCH.00 1.050 BSC 0.38 2.21 4.56 6.010) M B M NOTES: 1. 632-01 THRU -07 OBSOLETE. 2.49 0.240 0.020 0.60 3.014 0.08 3.015 0.004 0.170 0.157 0.39 1.25 ° ° 0 7 5.040 0.200 0.39 1.049 0.019 0.43 7.009 0.015 0.76 (0.125 0.80 4. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 18.145 0.009 ° ° 7 0 0.65 1.244 0.50 INCHES MIN MAX 0.715 0.51 INCHES MIN MAX 0.20 0. DIMENSIONS “A” AND “B” ARE DATUMS AND “T” IS A DATUM SURFACE.344 0.35 0.32 2.94 7.25 0.16 19.010 0.54 BSC 1.55 8.15 (0.94 0.25 (0. 4.05 19.155 0.53 1.62 BSC 0° 10° 0.41 0.008 0.27 BSC 0.300 BSC 0° 10° 0. 4.02 1. 4.010) M K T B S M F J A S MOTOROLA 301 ◊ CODELINE TO BE PLACED HERE *MC74F803/D* MC74F803/D TIMING SOLUTIONS BR1333 — REV 4 .38 0. 5.25 (0. 5. 2. DIMENSION “B” DOES NOT INCLUDE MOLD FLASH.015 0.008 0. DIMENSIONING AND TOLERANCING PER ANSI Y14.20 0.11 6.006) PER SIDE.070 0.185 0. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.31 3.068 0.50 0. NEW STANDARD 632-08. LEADS WITHIN 0. DIM A B C D F G J K L M N MILLIMETERS MIN MAX 19.10 6. 646-05 OBSOLETE.245 0. 1982.40 1.13 mm (0.25 (0.01 0. CONTROLLING DIMENSION: MILLIMETER.150 0. NEW STANDARD 751A-02.016 0.25 0.300 BSC ° ° 15 0 0.38 0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION.021 0.135 0.

or other applications intended to support or sustain life. No. Nishi-Gotanda. Hong Kong. damages.MC74F803 Motorola reserves the right to make changes without further notice to any products herein. employees. 2 Dai King Street.O. and distributors harmless against all claims. intended. EUROPE: Motorola Ltd. England. Buyer shall indemnify and hold Motorola and its officers. Motorola and are registered trademarks of Motorola. and reasonable attorney fees arising out of. Motorola makes no warranty. Tokyo 141 Japan. nor does Motorola assume any liability arising out of the application or use of any product or circuit. including “Typicals” must be validated for each customer application by customer’s technical experts. Silicon Harbour Center. Phoenix. Shinagawa-ku. Milton Keynes. ASIA-PACIFIC: Tai Po.T. “Typical” parameters can and do vary in different applications. subsidiaries. Tai Po Industrial Estate. All operating parameters. Blakelands. Motorola does not convey any license under its patent rights nor the rights of others. JAPAN: Nippon Motorola Ltd. and expenses. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application. any claim of personal injury or death associated with such unintended or unauthorized use. ASIA-PACIFIC: Motorola Semiconductors H. costs. P. Inc. Inc. Arizona 85036. 4-32-1. and specifically disclaims any and all liability. Literature Distribution Centers: USA: Motorola Literature Distribution. TIMING SOLUTIONS BR1333 — REV 4 MOTOROLA 302 . or authorized for use as components in systems intended for surgical implant into the body... affiliates. N. MK14 5BP. European Literature Centre. representation or guarantee regarding the suitability of its products for any particular purpose.. or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. is an Equal Opportunity/Affirmative Action Employer. Motorola products are not designed. Box 20912. 88 Tanners Drive. even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. including without limitation consequential or incidental damages. Motorola. directly or indirectly.K. Ltd..

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OE1 OE2 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 23 22 21 20 19 18 17 16 15 14 FAST AND LS TTL DATA 4-264 . The F827 and F828 are functionally and pin compatible to AMD’s 29827 and 29828. Bus and Clock Lines • Outputs Sink 64 mA • 15 mA Source Current • Flow Through Pinout Architecture for Microprocessor Oriented Applications CONNECTION DIAGRAMS (TOP VIEW) VCC O0 24 23 O1 22 O2 21 O3 20 O4 19 O5 18 O6 17 O7 16 O8 15 O9 OE2 14 13 24 MC54/74F827 MC54/74F828 10-BIT BUFFERS/LINE DRIVERS (WITH 3-STATE OUTPUTS) FAST™ SCHOTTKY TTL 24 1 J SUFFIX CERAMIC CASE 758-01 1 N SUFFIX PLASTIC CASE 724-03 F827 1 OE1 2 D0 3 D1 O1 22 4 D2 O2 21 5 D3 O3 20 6 D4 O4 19 7 D5 O5 18 8 D6 O6 17 9 D7 O7 16 10 D8 O8 15 11 12 D9 GND O9 OE2 14 13 24 1 DW SUFFIX SOIC CASE 751E-03 VCC O0 24 23 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC F828 LOGIC SYMBOL 1 OE1 2 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 D8 11 12 D9 GND 1 13 F827 2 3 4 5 6 7 8 9 10 11 LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OE1 OE2 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 23 22 21 20 19 18 17 16 15 14 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 F828 2 3 4 5 6 OE1 OE2 O9 O8 O7 O6 O5 O4 O3 O2 O1 O0 1 13 7 8 9 10 11 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. • 3-State Outputs Drive Memory Address. The 10-bit buffers have NOR output enables for maximum control flexibility.10-BIT BUFFERS/LINE DRIVERS (WITH 3-STATE OUTPUTS) The MC54/74F827 and MC54/74F828 10-bit bus buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. The F828 is an inverting version of the F827.

5 125 70 –12 mA Unit V °C FUNCTION TABLE Inputs Outputs On OE L L H Dn H L X F827 H L Z F828 L H Z Function Transparent Transparent High Z H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance FAST AND LS TTL DATA 4-265 . 74 54 74 54 IOH Min 4.0 25 25 — Max 5.MC54/74F827 • MC54/74F828 GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage* Operating Ambient g Temperature Range Output Current — High 74 54 IOL Output Current — Low 74 — — — — — — –15 48 64 mA Parameter 54.5 –55 0 — Typ 5.

5 9.5 4.5 10 9.0 3.0 8.5 2.0 — — 2.0 2.0 V ± 10% CL = 50 pF F Min 2.0 54F TA = – 55°C to +125 C 55 C +125°C VCC = 5.0 1.7 — — — — — — 0.0 Output Disable Time 1.0 V VIN = 0.5 9.0 8.0 V CL = 50 pF F Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay. use the appropriate value specified under recommended operating conditions for the applicable device type.0 8.0 1.5 4.0 3.5 9. For conditions shown as MIN or MAX.5 9.5 8.0 ns ns ns ns ns ns Unit FAST AND LS TTL DATA 4-266 .0 mA IOH = –3. AC CHARACTERISTICS 54/74F TA = +25°C +25 C VCC = +5.7 V VOUT = 0.5 9.5 2. g y.0 9.8 –1. Not more than one output should be shorted at a time.0 10 9.5 4.5 10 9. 74 74 54 VOL IOZH IOZL IIH IIL IOS ICCH Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current — Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current y HIGH Power Supply Current y LOW Power Supply Current OFF F828 — — 70 mA F827 F828 F827 F828 F827 ICCZ — –100 — — — — — — — — — — — — — 100 –20 –225 70 45 100 85 90 — — — — — — — — 0.0 1.75 V VCC = MIN VCC = MAX VCC = MAX VCC = 0 V VCC = MAX VCC = MAX VCC = MIN VCC = MIN ICCL NOTES: 1.0 2.5 4.0 2.5 2.0 3. 2.5 Max 9.0 2. Data to Output Output Enable Time F827 Min 2.0 1.5 Max 8.5 Max 10 10 11 10. Data to Output Output Enable Time F828 1.0 9.0 10 9.5 8.55 V V V Min 2.0 2.0 2.MC54/74F827 • MC54/74F828 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54 74 VOH Output HIGH Voltage 54.0 3.55 50 –50 20 V µA µA µA µA µA mA mA Outputs HIGH mA mA Outputs LOW mA mA Outputs OFF VCC = MAX VCC = MAX VCC = MAX 2.0 2.0 8.0 3.0 mA IOL = 48 mA IOL = 64 mA VOUT = 2.0 3.0 74F TA = 0°C to 70 C 0 C 70°C VCC = 5.0 V ± 10% CL = 50 pF F Min 2.2 — — Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = –18 mA IOH = –12 mA IOH = –15 mA IOH = –3.4 2.5 11 10 11 10.0 2.5 4.0 1.0 9.0 1. g y. nor for more than 1 second.0 2.7 V VIN = 7.0 2.5 V VOUT = 0 V VCC = 4.5 V VIN = 2.0 1.5 4.0 8.0 Output Disable Time Propagation Delay.5 7.5 8.0 Typ — — — — — Max — 0.5 9.

0 25 — — — — Max 5. disables both A and B ports by placing them in a high-Z condition. Transmit (active HIGH) enables data from A ports to B ports. when HIGH. Current sinking capability is 24 mA at the A ports and 64 mA at the B ports.0 24 –15 64 Unit V °C mA mA mA mA FAST AND LS TTL DATA 4-267 .5 0 — — — — Typ 5. The Transmit/ Receive (T/R) input determines the direction of data flow through the bidirectional transceiver.MC74F1245 OCTAL BIDIRECTIONAL TRANSCEIVER WITH 3-STATE INPUTS/OUTPUTS The MC74F1245 contains eight noninverting bidirectional buffers with 3-state outputs and is intended for bus-oriented applications. • Noninverting Buffers • Bidirectional Data Path • B Outputs Sink 64 mA • High Impedance Inputs for Reduced Loading • Same Function and Pinout as the F245 • ESD Protection > 4000 Volts PIN ASSIGNMENT VCC OE 20 19 B0 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 20 1 OCTAL BIDIRECTIONAL TRANSCEIVER WITH 3-STATE INPUTS/OUTPUTS FAST™ SCHOTTKY TTL 20 1 J SUFFIX CERAMIC CASE 732-03 N SUFFIX PLASTIC CASE 738-03 20 1 DW SUFFIX SOIC CASE 751D-03 1 T/R 2 A0 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 GND LOGIC SYMBOL 2 3 4 5 6 7 8 9 ORDERING INFORMATION MC74FXXXXJ Ceramic MC74FXXXXN Plastic MC74FXXXXDW SOIC A0 A1 A2 A3 A4 A5 A6 A7 19 1 OE T/R B0 B1 B2 B3 B4 B5 B6 B7 18 17 16 15 14 13 12 11 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL IOH IOL Parameter DC Supply Voltage Operating Ambient Temperature Range Output Current  High Output Current  Low Output Current  High Output Current  Low An Outputs An Outputs Bn Outputs Bn Outputs 74 74 74 74 74 74 Min 4. Receive (active LOW) enables data from B ports to A ports. The Output Enable input.5 70 –3.

MC74F1245 FUNCTION TABLE Inputs OE L L H T/R L H X An A=B Inputs Z Inputs/Outputs Bn Inputs B=A Z H = HIGH voltage level: L = LOW voltage level: X = Don’t care: Z = HIGH impedance “off” state. LOGIC DIAGRAM A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 VCC = PIN 20 GND = PIN 10 19 OE T/R 1 18 B0 17 B1 16 B2 B3 15 B4 14 13 B5 12 B6 11 B7 FAST AND LS TTL DATA 4-268 .

VIN = 2.0 8.35 — — — — — — — — — Max — 0.7 2.7 V VCC = MAX.MC74F1245 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 74 Output HIGH Voltage An Outputs 74 74 VOH Output HIGH Voltage Bn Outputs 74 74 VOL VOL IOZH IOZL Output LOW Voltage An Outputs Output LOW Voltage Bn Outputs Output Off Current HIGH Output Off Current LOW OE.75 V VCC = 4.4 3.0 Max 7.5 7. nor for more than 1 second.5 V VCC = MAX. Bn Inputs OE. VOUT = GND MAX IOH = –3.8 –1. T/R Inputs IIH Input HIGH Current An.0 9.7 2. VIN = 5.5 8.0 10.0 4.0 11.0 9.5 1.5 V VCC = MAX.0 — — 2. VIN = 2.0 mA 30 Test Conditions (Note 1) Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.0 –40 Unit V V V V V V V V V V µA µA µA µA µA mA mA µA µA mA mA VCC = MAX.0 Max 6.5 2.0 8.3 3. Bn Inputs Output Short Circuit Current (Note 2) An Outputs Bn Outputs ICCH ICC Power Supply Current ICCL ICCZ — –60 –100 — — — — — — — — — –70 –150 –225 120 120 130 mA VCC = MAX An Inputs OE.0 mA 30 IOH = –15 mA IOL = 24 mA IOL = 64 mA VCC = MAX IOH = –3.5 3.0 2.0 — — — — — — — — — — Typ — — –0.0 10.5 0.3 3.73 3.7 V VCC = 0 V.4 2.4 2. VIN = 7. T/R Inputs Bn Inputs IIHH IIL Input HIGH Current Input LOW Current An.0 Unit ns ns ns FAST AND LS TTL DATA 4-269 . use the appropriate value specified under recommended operating conditions for the applicable device type.0 V ±10% CL = 50 pF Min 1.0 74F TA = 0°C to +70°C VCC = +5.5 V VCC = 4.5 3.75 V VCC = 4. VOUT = 0.5 1.5 V VCC = MIN VOUT = 2.5 IOS NOTES: 1.0 2.55 70 –70 40 70 100 1.7 V VCC = MAX. IIN = –18 mA VCC = 4. AC ELECTRICAL CHARACTERISTICS 74F TA = +25°C VCC = +5.0 V VCC = 0 V.4 — 0.5 V VCC = 4.0 V CL = 50 pF Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Transparent Mode An to Bn or Bn to An Output Enable Time Output Disable Time Min 2. For conditions shown as MIN or MAX. VIN = 0 5 V MAX 0. Not more than one output should be shorted at a time. VIN = 5.0 1. T/R Inputs 74 74 Min 2.0 2.0 11. 2.0 2.2 — — — — — 0.5 V VCC = 0 V.

13 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays This document contains information on a new product. NC = Pins 2. quad D-type flip-flop featuring separate D-type inputs and inverting outputs with closely matched propagation delays. providing multiple outputs that are synchronous. 11/93 © Motorola. With a buffered clock (CP) input that is common to all flipflops. Specifications and information herein are subject to change without notice. GND = Pins 1. 1994 REV 3 .0 nanoseconds. the MC74F1803 is useful in high-frequency systems as a clock driver. the duty cycles of the output waveforms in a clock driver application are symmetrical within 2.7. low-power. • • • • Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Matched Outputs for Synchronous Clock Driver Applications Outputs Guaranteed for Simultaneous Switching Pinout: 14-Lead Plastic (Top View) VCC 14 NC 13 O3 12 D3 11 D2 10 O2 9 CP 8 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-03 1 GND 2 NC 3 O0 4 D0 5 D1 6 O1 7 GND LOGIC SYMBOL 4 D0 5 D1 10 D2 11 D3 LOGIC DIAGRAM 8 D0 D1 D2 D3 O0 CP CP D Q CP D Q CP D Q CP D Q 3 VCC = PIN 14 GND = PINS 1 AND 7 NC = PINS 2 AND 13 6 9 12 O1 O2 O3 CP O0 O1 O2 O3 VCC = Pin 14.MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document from Logic Marketing Advance Information Clock Driver Quad D Type Flip Flop MC74F1803 CLOCK DRIVER QUAD D-TYPE FLIP-FLOP WITH MATCHED PROPAGATION DELAYS With Matched Propagation Delays The MC74F1803 is a high-speed. Because of the matched propagation delays. Inc.

6 –150 70 Unit V V V V V µA µA mA mA mA Test Conditions 1.0 – – 2. VIN = 0.0 – 2. In addition.0 V VCC = MAX. multiple outputs can be tied together and the IOH is commensurately increased. AC OPERATING REQUIREMENTS (TA = 0°C to +70°C: VCC = +5.5 V VCC = MAX.8 –1.2 Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN.2 – 0.0 7. Two outputs of the MC74F1803 can be tied together and the IOH doubles. Therefore. The four flip-flops store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition.0 – – – – Unit ns ns ns ns TIMING SOLUTIONS BR1333 — REV 4 MOTOROLA 310 .0 6.0 2. The maximum frequency of the clock input is 70 megahertz and the LOW-to-HIGH and HIGH-to-LOW GUARANTEED OPERATION RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter Min 4. 2.MC74F1803 FUNCTIONAL DESCRIPTION The MC74F1803 consists of four positive edge-triggered flip-flops with individual D-type inputs and inverting outputs. the IOH specification at 2. VIN = 7.0 25 — — Max 5.5 70 –20 24 Unit V °C mA mA propagation delays of the On output vary by at most.35 – – – – – Max – 0.5 – – – IIL IOS ICC Input LOW Current Output Short Circuit Current 3 Power Supply Current – –60 – Typ – – – – 0. VOUT = 0 V VCC = MAX 1 For conditions shown as MIN or MAX. the output-to-output skew is a maximum of 2. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage An Outputs Output LOW Voltage An Outputs Input HIGH Current 74 74 Min 2.5 20 100 –0. HIGH or LOW: Dn to CP Cp Pulse Width HIGH or LOW Min 3.5 volts is guaranteed to be at least –20 milli-amps.0 V ±10%: RL = 500 Ω) CL = 50 pF Symbol ts(H) ts(L) tf th(H) th(L) tw(H) tw(L) Parameter Setup Time. the device is ideal for use as a divide-by-two driver for high-frequency clock signals that require symmetrical duty cycles. VIN = 2.5 0 — — Typ 5. IIN = –18 mA IOH = –20 mA IOL = 24 mA VCC =4.0 3.7 V VCC = MAX. HIGH or LOW: Dn to CP tp + ts 1 Hold Time. 3 Not more than one output should be shorted at a time. nor for more than 1 second. 2 Normal test conditions for this device are all four outputs switching simultaneously. If their inputs are identical.5 V VCC = MIN VCC = MAX. use the appropriate value specified under recommended operating conditions for the applicable device type.0 nanoseconds.0 Max – – 9. Finally. The buffered clock is common to all flip-flops and the following specifications allow for outputs switching simultaneously.0 nanoseconds.

MC74F1803 1 The combination of the setup time (ts) requirement and maximum propagation delay (tp) are guaranteed to be within this limit for all conditions. MOTOROLA 311 TIMING SOLUTIONS BR1333 — REV 4 .

O3.0 3..0 – – – – – Max – 7. The AC characteristics described above are also guaranteed when two outputs are tied together.0 3. O2. Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Variation Propagation Delay Skew |tPLH Actual – tPHL Actual| for O0. TYPICAL MC74F1803 APPLICATION VCC 33 MHz Clock 14 4 5 10 74F04 1 11 2 1 CP 8 CLK D0 D1 MC74F1803 D2 D3 O0 O1 O2 O3 3 6 9 12 7 33 MHz Clock 33 MHz Clock (40 mA Output Drive) 66 MHz TIMING SOLUTIONS BR1333 — REV 4 MOTOROLA 312 . O3. tfall O1. 2 Where tp On and tp Om are the actual propagation delays (any combination of high or low) for two separate outputs from a given high transition of CP. tos trise. capacitive load.0 V) Parameter Min 70 3. O3. 3 For a given set of conditions (i. trise.e.8 to 2. O3 Output to Output Skew 2 |tp On – tp Om| Rise/Fall Time for O1 (0.0 V) Rise/Fall Time for O1.8 to 2. O2.0 2. O2.5 3. and number of outputs switching simultaneously) the variation from device to device is guaranteed to be less than or equal to the maximum.5 Unit MHz ns ns ns ns ns ns 1 The test conditions used are all four outputs switching simultaneously. temperature. O1.0 V ±10%: RL = 500 Ω) 1 CL = 50 pF Symbol fmax tPLH tPHL tPv tps O0.0 2. (0. O1. VCC. tfall O0. O2.MC74F1803 AC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C: VCC = +5.

62 10° 0° BSC 0. Motorola. 6.5M. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.157 0. nor does Motorola assume any liability arising out of the application or use of any product or circuit. Motorola products are not designed. affiliates.92 3. Motorola does not convey any license under its patent rights nor the rights of others. NEW STANDARD 646-06.25 INCHES MIN MAX 0.25 0. 3. 5.75 8.49 0.54 BSC 1.115 0. or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.008 0.260 0.19 0.13 mm (0. 4.009 ° ° 0 7 0. Motorola makes no warranty.78 2. MAXIMUM MOLD PROTRUSION 0.69 4.100 BSC 0. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 18.715 0. or other applications intended to support or sustain life. All operating parameters.69 0.80 0.770 0.185 0.55 4.38 0.095 0. 3. even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.00 3. NEW STANDARD 751A-02.015 0. directly or indirectly.016 0. employees.MC74F1803 OUTLINE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 646-06 14 8 B 1 7 NOTES: 1.240 0. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14. representation or guarantee regarding the suitability of its products for any particular purpose.006) PER SIDE.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION.244 0. 646-05 OBSOLETE.25 0. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.60 3.019 G C SEATING PLANE R X 45° D 14 PL 0. DIMENSION “B” DOES NOT INCLUDE MOLD FLASH.150 0. including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola and are registered trademarks of Motorola.38 2.015 0. LEADS WITHIN 0.40 1.50 0. Buyer shall indemnify and hold Motorola and its officers.35 1.135 0. is an Equal Opportunity/Affirmative Action Employer.015 0. Inc. 4.16 19.050 BSC 0.229 0. and specifically disclaims any and all liability. 2.068 0.80 1. subsidiaries.344 0. “Typical” parameters can and do vary in different applications.25 (0.010) M B M NOTES: 1.75 1.20 0. costs.25 0.040 0.15 (0.010 0.004 0.014 0.41 0.53 1.008 0.049 0.10 ° ° 7 0 6. DIMENSIONS “A” AND “B” ARE DATUMS AND “T” IS A DATUM SURFACE.20 5. DIMENSION “L” TO CENTER OF LEADS WHEN FORMED PARALLEL.02 1. Inc.145 0.052 0.43 7. and expenses.27 BSC 0. and reasonable attorney fees arising out of.35 0. CONTROLLING DIMENSION: MILLIMETER. any claim of personal injury or death associated with such unintended or unauthorized use. MOTOROLA 313 ◊ CODELINE TO BE PLACED HERE *MC74F1803/D* MC74F1803/D TIMING SOLUTIONS BR1333 — REV 4 .337 0.019 0. intended.01 INCHES MIN MAX 0.32 2. 751A-01 IS OBSOLETE.39 1.56 6. ROUNDED CORNERS OPTIONAL. damages.25 (0.009 0.021 0. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application. or authorized for use as components in systems intended for surgical implant into the body.054 0. 2.300 BSC 0° 10° 0.010) M K T B S M F J A S Motorola reserves the right to make changes without further notice to any products herein. including without limitation consequential or incidental damages.070 0.039 A F C N H G D SEATING PLANE NOTE 4 L J K M D SUFFIX SOIC PACKAGE CASE 751A-02 -A14 8 -B1 7 P 7 PL 0.10 6. and distributors harmless against all claims. 1982.

O. N. Phoenix. No.. 88 Tanners Drive. MK14 5BP. Box 20912. Tokyo 141 Japan. P. Arizona 85036.. Milton Keynes. 4-32-1.K.. ASIA-PACIFIC: Motorola Semiconductors H. Tai Po Industrial Estate.MC74F1803 Literature Distribution Centers: USA: Motorola Literature Distribution. Nishi-Gotanda. Ltd.. ASIA-PACIFIC: Tai Po.T. TIMING SOLUTIONS BR1333 — REV 4 MOTOROLA 314 . 2 Dai King Street. Blakelands. Hong Kong. Silicon Harbour Center. EUROPE: Motorola Ltd. England. JAPAN: Nippon Motorola Ltd. Shinagawa-ku. European Literature Centre.

The MC74F3893A interfaces to “Backplane Transceiver Logic” (BTL). BTL features a reduced (1 V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading (< 5 pF). This results in a high bandwidth.1 Futurebus Standards • Built-In Precision Band-Gap (BG) Reference Provides Accurate Receiver Threshold and Improved Noise Immunity • Glitch-Free Power Up/Power Down Operation On All Outputs • Pin and Function Compatible with NSC DS3893A and Signetics 74F3893 • Separate Bus Ground Returns for Each Driver to Minimize Ground Noise • MOS and TTL Compatible High Impedance Inputs PINOUT: 20-LEAD PLCC (TOP VIEW) I/O0 18 BUS GND BG GND VCC D0 R0 19 20 1 2 3 4 D1 5 6 7 D2 8 R2 BUS I/O1 GND 17 16 I/O2 15 I/O3 14 13 12 11 10 9 BUS GND RE DE R3 D3 QUAD FUTUREBUS BACKPLANE TRANSCEIVER (3 STATE + OPEN COLLECTOR) FAST™ SCHOTTKY TTL 19 3 4 8 FN SUFFIX PLASTIC CASE 775-02 ORDERING INFORMATION MC74FXXXXAFN Plastic LOGIC SYMBOL 2 11 12 DE D0 4 D1 7 D2 9 D3 RE I/O0 I/O1 I/O2 I/O3 R0 R1 R2 R3 18 17 15 14 3 5 8 10 R1 LOGIC GND FAST AND LS TTL DATA 4-276 . therefore noise margins are excellent. so is its receiver threshold region. BTL offers low power consumption. The MC74F3893A has four TTL outputs (Rn) on the receiver side with a common Receive Enable input (RE). Although the voltage swing is much less for BTL. The four I/O pins (Bus side) are futurebus compatible. • Quad Backplane Transceiver • Drives Heavily Loaded Backplanes with Equivalent Load Impedances Down to 10 ohms • Futurebus Drivers Sink 100 mA • Reduced Voltage Swing (1 Volt) Produces Less Noise and Reduces Power Consumption • High Speed Operation Enhances Performance of Backplane Buses and Facilitates Incident Wave Switching • Compatible with IEEE 896 and IEEE 1194.MC74F3893A QUAD FUTUREBUS BACKPLANE TRANSCEIVER (3 STATE + OPEN COLLECTOR) The MC74F3893A is a quad backplane transceiver and is intended to be used in very high speed bus systems. low ground bounce. It has four data inputs (Dn) which are also TTL. and are designed to drive heavily loaded backplanes with load impedances as low as 10 ohms. sink a minimum of 100 mA. therefore BTL propagation delays are short. low capacitive loading. reliable backplane. These data inputs are NANDed with the Data Enable input (DE). reduced EMI and crosstalk. Incident wave switching is employed. All outputs are designed to be glitch-free during power up and power down. superior noise margin and short propagation delays.

550 — — — Max 5. RECOMMENDED OPERATING CONDITIONS Limits Symbol VCC VIH VIL IIK VTH IOH IOL TA Supply Voltage High-Level Input Voltage Low-Level Input Voltage Input Clamp Current Bus Input Threshold Output Current  High Output Current  Low Operating Ambient Temperature Range I/On Only Rn Only Dn. Parameter Min 4.475 — — 0 Typ 5.5 — 0.8 –18 1.0 — — — 1.16. Transmit to Bus Receive. I/On = Inputs H = HIGH voltage level: L = LOW voltage level: X = Don’t care: Z = HIGH impedance “Off” state.5 2. DE RE DE.0 100 70 Unit V V V mA V mA mA °C FAST AND LS TTL DATA 4-277 .MC74F3893A LOGIC DIAGRAM D0 2 18 I/O0 R0 3 D1 4 17 I/O1 5 R1 12 D2 7 15 RE I/O2 R2 8 D3 9 14 I/O3 R3 DE 10 11 VCC = PIN 1: LOGIC GND = PIN 6 BUS GND = PIN 13.625 –3. 19: BG GND = PIN 20 FUNCTION TABLE Inputs DE H H H L L L RE L L H H L L Dn L H L H X X Input/Output I/On H L Dn H H L Outputs Rn L H Z Z L H Operating Mode Transmit to Bus Receiver 3-State.0 — — 1.

2.73 — — — — — — — — — — 55 3. II = IIK VCC = MAX: VI = 7.5 1.8 V.0 V: RT = 10Ω: RE = 2. 3. For conditions shown as MIN or MAX. Not more than one output should be shorted at a time.75 V : RE = 0 V: VO = 2.5 Dn = 4.5 V VCC = 0 V: DN = DE = 0.5 V V µA µA µA VCC = MAX or 0 V: DN = DE = 0 8 V: 0.0 1.5V: RE = 2.MC74F3893A DC CHARACTERISTICS (Over Recommended Operating Free-Air Temperature Range Unless otherwise specified) Limits Symbol VOH Parameter High-Level Output Voltage Rn Min 2. Low-Level Voltage Applied Output Short Circuit Current (Note 3) Supply Current (Total ) I/On VCC = MAX: Dn = DE = 0.0 V Dn = 1. IOS tests should be performed last. RE = 0. HighLevel Voltage Applied Off-State Output Current. All typical values are at VCC = 5.0 mA Dn = DE = VIH: IOL = 100 mA Dn = DE = VIH: IOL = 80 mA V — — — — — — — — –250 — Rn — –80 — — –0.8 V: IOH = MAX VCC = MAX: DN = DE = 0.3 V. prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests.5V: DE = 4 5 V 4.0 V: DE = RE = Dn = VCC VCC = MAX: DE = RE = Dn = 2. TA = + 25°C.0 mA I/On = 10 mA VOHB High-Level Output Bus Voltage I/On 1.0 V VCC = MIN. For testing IOS.2 V: RE = 0 V: I/On = 1. In any sequence of parameter tests.75 0.0 V.8 V: IOL = 6.0 V VCC = MAX: VO = 0.35 1. use the appropriate value specified under recommended operating conditions for the applicable device type. DE I/On RE IIL Low-Level Input Current Dn DE IILB IOZH IOZL IOS ICC Low-Level I/O Bus Current (Power On) Off-State Output Current.2 –1.2 V: VO = 0 V: RE = 0.8 V: VT = 2.2 100 20 100 –100 –200 –500 100 20 –20 –200 80 mA mA µA µA VCC = MAX: VI = 0.5 V: RE = 2. RE.9 — — V VOL VOLB Output LOW Voltage Rn I/On — 0.0 V IOH = MAX VCC = MIN: VIN = 1.8 V: I/On = 0. the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values.8 RE = 2.8 V VCC = MAX: (RE = VIH or VIL) VCC = MAX: µA NOTES: 1.0 — 0. Otherwise.1 2. FAST AND LS TTL DATA 4-278 .8 V: I/On = 1.9 VOCB VIK II IIH IIHB Driver Output Positive Clamp Voltage Input Clamp Diode Voltage I/On Input Current at Maximum Input Voltage High Level Input Current High-Level I/O Bus Current (Power Off) Dn.75 — 1.5 Typ (2) — Max — Unit V Test Conditions (Note 1) VCC = MIN: VIL = 1.2 V Low Level Output Bus Voltage V 0. RE = 0.

0 — Unit ns ns AC ELECTRICAL CHARACTERISTICS for Receiver Enable 74F TA = +25°C VCC=+5.0 1.0V CL = 50 pF RL = 500 Ω Symbol tPZH tPZL tPHZ tPLZ Parameter Output Enable to High or Low Level RE to Rn Output Disable From High or Low Level RE to Rn Min — — — — Typ — — — — Max — — — — 74F TA = 0°C to +70°C VCC=+5.0V.0 7.0V CD = 30 pF RT = 10 Ω Min 1.MC74F3893A AC ELECTRICAL CHARACTERISTICS for Receiver and Receiver Enable 74F TA = +25°C VCC=+5.0 — Max 7.0 2.0 5.0 8. VT=+2.0K Ω Min 2.0 Max — — — — — — — 74F TA = 0°C to +70°C VCC=+5.0 8.0 Max — — — 74F TA = 0°C to +70°C VCC=+5.0 1.0 7.0 1. 90% to 10% Skew Between Receivers in Same Package Min — — — — — — — Typ — — — — — — 1.0 1.0 8.0 7.0V ±10% CL = 50 pF RL = 500 Ω Min 2.0 — Max 8.0 1.0 5.0 1.0 1.0V CL = 50 pF RL = 1.0 12.0V ±10%.0 Unit ns ns FAST AND LS TTL DATA 4-279 .0V CD = 30 pF RT = 10 Ω Symbol tPLH tPHL tPLH tPHL tTLH tTHL tDskew Parameter Propagation Delay Dn to I/On Propagation Delay DE to I/On Dn to I/On Transition Time 10% to 90%.0K Ω Symbol tPLH tPHL tDskew Parameter Propagation Delay I/On to Rn Skew Between Receivers in Same Package Min — — — Typ — — 1.VT=+2.0 2.0 — Unit ns ns ns ns AC ELECTRICAL CHARACTERISTICS for Receiver 74F TA = +25°C VCC=+5.0 Max 12.0V ±10% CL = 50 pF RL = 1.

FAST AND LS TTL DATA 4-280 .

FAST AND LS TTL LS Data Sheets 5 .

LS Data Sheets 5 .

0 5.25 125 70 – 0.4 4.0 25 25 Max 5.5 5.0 8.75 – 55 0 Typ 5.5 4.SN54/74LS00 QUAD 2-INPUT NAND GATE • ESD > 3500 Volts QUAD 2-INPUT NAND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 GND 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. 74 54 74 Min 4.0 Unit V °C mA mA FAST AND LS TTL DATA 5-2 .

Input to Output Min Typ 9. IIN = – 18 mA VCC = MIN. VIN = VIL or VIH per Truth Table 0.4 0.7 3.5 2. Output LOW Note 1: Not more than one output should be shorted at a time.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.7 V VCC = MAX.5 V V V V V µA mA mA mA IIH IIL IOS ICC VCC = MAX.0 mA VCC = VCC MIN.SN54/74LS00 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. VIN = VIH or VIL per Truth Table IOL = 4.4 mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.4 – 20 –100 1.8 – 0.4 V VCC = MAX VCC = MAX – 0. VIN = 0.6 4.0 10 Max 15 15 Unit ns ns Test Conditions VCC = 5.7 V 0. VIN = 7.5 20 – 1.0 mA IOL = 8.5 3.35 0. nor for more than 1 second. VIN = 2.5 0.0 Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.65 2. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.0 V VCC = MAX. IOH = MAX.0 V CL = 15 pF FAST AND LS TTL DATA 5-3 . Input to Output Turn-On Delay. Min 2. Output HIGH Total.25 0.

5 4. 74 54 74 Min 4.0 25 25 Max 5.SN54/74LS01 QUAD 2-INPUT NAND GATE • ESD > 3500 Volts QUAD 2-INPUT NAND GATE VCC 14 13 * * * 12 11 10 * J SUFFIX CERAMIC CASE 632-08 5 6 7 GND * OPEN COLLECTOR OUTPUTS N SUFFIX PLASTIC CASE 646-06 1 14 1 LOW POWER SCHOTTKY 9 8 1 2 3 4 14 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54.25 125 70 5.0 5.5 4.0 8.0 Unit V °C V mA FAST AND LS TTL DATA 5-4 .75 – 55 0 Typ 5.5 5.

VIN = 2. Input to Output Min Typ 17 15 Max 32 28 Unit ns ns Test Conditions VCC = 5.4 V µA V Min 2.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VOH = MAX IOL = 4.4 0.1 Input LOW Current Power Supply Current Total.0 mA VCC = VCC MIN. 74 0.5 100 0. Input to Output Turn-On Delay. Output HIGH Total. 74 54.0 V VCC = MAX. VIN = 7.0 0.8 – 1.0 mA IOL = 8.25 – 0.4 V VCC = MAX mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.4 1.65 0. VIN = VIL or VIH per Truth Table VCC = MAX.SN54/74LS01 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Current Output LOW Voltage 74 Input HIGH Current 0.0 V CL = 15 pF. VIN = 0.6 4. RL = 2.35 0.5 20 IIH IIL ICC V µA mA mA 54. IIN = – 18 mA VCC = MIN. Output LOW – 0.7 V VCC = MAX.0 kΩ FAST AND LS TTL DATA 5-5 .

25 125 70 – 0.5 4.4 4. 74 54 74 Min 4.0 8.0 5.0 25 25 Max 5.5 5.SN54/74LS02 QUAD 2-INPUT NOR GATE QUAD 2-INPUT NOR GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.0 Unit V °C mA mA FAST AND LS TTL DATA 5-6 .75 – 55 0 Typ 5.

4 V VCC = MAX VCC = MAX – 0.SN54/74LS02 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.7 V 0.4 – 20 –100 3. Input to Output Turn-On Delay.4 mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.0 Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.8 – 0.65 2. VIN = 0. IIN = – 18 mA VCC = MIN. nor for more than 1 second. VIN = VIL or VIH per Truth Table 0.2 5.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total. VIN = VIH or VIL per Truth Table IOL = 4.5 2.35 0.5 3. Output LOW Note 1: Not more than one output should be shorted at a time.0 mA IOL = 8.5 20 – 1. Min 2.0 mA VCC = VCC MIN.25 0.7 3. Output HIGH Total.7 V VCC = MAX.4 0.0 V CL = 15 pF FAST AND LS TTL DATA 5-7 . 74 VOL Output LOW Voltage 74 Input HIGH Current 0.0 V VCC = MAX.5 V V V V V µA mA mA mA IIH IIL IOS ICC VCC = MAX. VIN = 2.5 0. VIN = 7. IOH = MAX. Input to Output Min Typ 10 10 Max 15 15 Unit ns ns Test Conditions VCC = 5.

0 5.5 4.25 125 70 5.0 8.5 5.0 Unit V °C V mA FAST AND LS TTL DATA 5-8 .75 – 55 0 Typ 5.0 25 25 Max 5.5 4. 74 54 74 Min 4.SN54/74LS03 QUAD 2-INPUT NAND GATE • ESD > 3500 Volts QUAD 2-INPUT NAND GATE VCC 14 13 12 * 11 10 9 * 8 LOW POWER SCHOTTKY * 1 2 3 4 5 6 * 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 * OPEN COLLECTOR OUTPUTS N SUFFIX PLASTIC CASE 646-06 1 14 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54.

74 0. RL = 2. Output LOW – 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 mA IOL = 8.4 0.4 V VCC = MAX mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay. VIN = VIL or VIH per Truth Table VCC = MAX.1 Input LOW Current Power Supply Current Total. Output HIGH Total. VIN = 0.65 0. VIN = 2.35 0.0 V CL = 15 pF. Input to Output Turn-On Delay.SN54/74LS03 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Current Output LOW Voltage 74 Input HIGH Current 0. 74 54. VOH = MAX IOL = 4.4 V µA V Min 2.0 mA VCC = VCC MIN.5 20 IIH IIL ICC V µA mA mA 54.8 – 1.6 4.7 V VCC = MAX.5 100 0. VIN = 7.4 1.0 0.25 – 0.0 V VCC = MAX. Input to Output Min Typ 17 15 Max 32 28 Unit ns ns Test Conditions VCC = 5.0 kΩ FAST AND LS TTL DATA 5-9 . IIN = – 18 mA VCC = MIN.

0 Unit V °C mA mA FAST AND LS TTL DATA 5-10 .5 4.25 125 70 – 0.5 5.SN54/74LS04 HEX INVERTER HEX INVERTER VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.4 4.0 25 25 Max 5.75 – 55 0 Typ 5.0 5.0 8. 74 54 74 Min 4.

4 –100 2. VIN = 2.0 V CL = 15 pF FAST AND LS TTL DATA 5-11 . IOH = MAX. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.6 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.0 0.0 10 Max 15 15 Unit ns ns Test Conditions VCC = 5.4 6.65 3. Input to Output Turn-On Delay.0 V VCC = MAX. VIN = 0. nor for more than 1 second. VIN = 7.5 – 0.5 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay. VIN = VIL or VIH per Truth Table VCC = MAX.35 0.25 0.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.8 – 1. VIN = VIH or VIL per Truth Table IOL = 4. IIN = – 18 mA VCC = MIN.7 V VCC = MAX. Input to Output Min Typ 9.0 mA VCC = VCC MIN.SN54/74LS04 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.5 20 IIH IIL IOS ICC V µA mA mA mA 2. Output LOW – 20 – 0.4 V V 2.5 V V Min 2. Output HIGH Total.5 0.7 3.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 mA IOL = 8.

74 54 74 Min 4.25 125 70 5.0 Unit V °C V mA FAST AND LS TTL DATA 5-12 .75 – 55 0 Typ 5.SN54/74LS05 HEX INVERTER HEX INVERTER VCC 14 13 12 * 11 10 * 9 * 8 LOW POWER SCHOTTKY * 1 2 3 * 4 5 * 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 * OPEN COLLECTOR OUTPUTS 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54.5 4.0 8.5 4.0 5.5 5.0 25 25 Max 5.

VIN = 2. RL = 2.0 0.SN54/74LS05 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Current Output LOW Voltage 74 Input HIGH Current 0. IIN = – 18 mA VCC = MIN. VOH = MAX IOL = 4.4 V VCC = MAX mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay. 74 54.65 0.4 6.1 Input LOW Current Power Supply Current Total.5 100 0.6 0.0 V CL = 15 pF.7 V VCC = MAX. Input to Output Min Typ 17 15 Max 32 28 Unit ns ns Test Conditions VCC = 5. Input to Output Turn-On Delay.4 2. Output HIGH Total.25 – 0.0 V VCC = MAX. VIN = 0. VIN = VIL or VIH per Truth Table VCC = MAX.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.8 – 1. 74 0. VIN = 7.0 kΩ FAST AND LS TTL DATA 5-13 .35 0.0 mA IOL = 8.5 20 IIH IIL ICC V µA mA mA 54.4 V µA V Min 2. Output LOW – 0.0 mA VCC = VCC MIN.

0 5.5 4. 74 54 74 Min 4.25 125 70 – 0.0 Unit V °C mA mA FAST AND LS TTL DATA 5-14 .SN54/74LS08 QUAD 2-INPUT AND GATE QUAD 2-INPUT AND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 5.0 25 25 Max 5.75 – 55 0 Typ 5.0 8.4 4.

Input to Output Turn-On Delay. Input to Output Min Typ 8.8 8. Output HIGH Total.5 0.5 2.7 V VCC = MAX.0 V CL = 15 pF FAST AND LS TTL DATA 5-15 .25 0.0 Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. IOH = MAX.65 2. Min 2. VIN = VIL or VIH per Truth Table 0.8 mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.7 V 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.8 – 0. nor for more than 1 second. Output LOW Note 1: Not more than one output should be shorted at a time.4 0.0 10 Max 15 20 Unit ns ns Test Conditions VCC = 5. VIN = 7.7 3. VIN = VIH or VIL per Truth Table IOL = 4.SN54/74LS08 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.5 3.5 V V V V V µA mA mA mA IIH IIL IOS ICC VCC = MAX. VIN = 2.0 mA IOL = 8.0 mA VCC = VCC MIN.0 V VCC = MAX.35 0. IIN = – 18 mA VCC = MIN.4 – 20 – 100 4.5 20 – 1.4 V VCC = MAX VCC = MAX – 0. VIN = 0.

SN54/74LS09 QUAD 2-INPUT AND GATE QUAD 2-INPUT AND GATE VCC 14 13 12 * 11 10 9 * 8 LOW POWER SCHOTTKY * 1 2 3 4 5 6 * 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 * OPEN COLLECTOR OUTPUTS 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54.5 4.0 5.0 8.75 – 55 0 Typ 5.0 Unit V °C V mA FAST AND LS TTL DATA 5-16 . 74 54 74 Min 4.5 4.5 5.25 125 70 5.0 25 25 Max 5.

Input to Output Turn-On Delay. VIN = 7. VIN = 0. Output HIGH Total. Input to Output Min Typ 20 17 Max 35 35 Unit ns ns Test Conditions VCC = 5.4 V µA V Min 2. VIN = VIL or VIH per Truth Table VCC = MAX.65 0.4 V VCC = MAX mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.1 Input LOW Current Power Supply Current Total.0 V CL = 15 pF.0 kΩ FAST AND LS TTL DATA 5-17 . RL = 2.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.25 – 0.5 100 0.8 – 1.4 4.SN54/74LS09 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Current Output LOW Voltage 74 Input HIGH Current 0.0 mA VCC = VCC MIN.0 mA IOL = 8.5 20 IIH IIL ICC V µA mA mA 54.7 V VCC = MAX. Output LOW – 0. 74 54. VOH = MAX IOL = 4. IIN = – 18 mA VCC = MIN. VIN = 2.35 0. 74 0.0 0.0 V VCC = MAX.8 0.8 8.

5 5.0 5.4 4.5 4.0 25 25 Max 5.SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. 74 54 74 Min 4.0 8.0 Unit V °C mA mA FAST AND LS TTL DATA 5-18 .25 125 70 – 0.75 – 55 0 Typ 5.

0 0. VIN = 2. IIN = – 18 mA VCC = MIN.0 mA IOL = 8.0 V VCC = MAX. Output LOW – 20 – 0.5 0. VIN = 0. Input to Output Min Typ 9.5 20 IIH IIL IOS ICC V µA mA mA mA 2.7 3.65 3.5 – 0.35 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 10 Max 15 15 Unit ns ns Test Conditions VCC = 5.8 – 1.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.7 V VCC = MAX.4 –100 1.0 V CL = 15 pF FAST AND LS TTL DATA 5-19 . Output HIGH Total.5 V V Min 2. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.SN54/74LS10 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.3 0.5 0.4 V V 2. VIN = 7.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time. nor for more than 1 second. VIN = VIH or VIL per Truth Table IOL = 4.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.25 0. Input to Output Turn-On Delay. IOH = MAX.0 mA VCC = VCC MIN.2 3. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.

SN54/74LS11 TRIPLE 3-INPUT AND GATE TRIPLE 3-INPUT AND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.0 Unit V °C mA mA FAST AND LS TTL DATA 5-20 .0 25 25 Max 5.5 4.25 125 70 – 0.0 5.5 5.0 8.4 4.75 – 55 0 Typ 5. 74 54 74 Min 4.

0 10 Max 15 20 Unit ns ns Test Conditions VCC = 5.0 mA IOL = 8.4 V V 2.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.5 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.0 V VCC = MAX. VIN = 0.0 mA VCC = VCC MIN. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.6 6.5 – 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total. Input to Output Min Typ 8.5 20 IIH IIL IOS ICC V µA mA mA mA 2.7 V VCC = MAX.25 0.8 – 1. VIN = 7.SN54/74LS11 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. Input to Output Turn-On Delay. Output HIGH Total. VIN = 2.65 3. Output LOW – 20 – 0.4 –100 3.35 0.0 V CL = 15 pF FAST AND LS TTL DATA 5-21 . VIN = VIH or VIL per Truth Table IOL = 4.5 0. IOH = MAX.5 V V Min 2.6 0. IIN = – 18 mA VCC = MIN. nor for more than 1 second.7 3.0 0. VIN = VIL or VIH per Truth Table VCC = MAX.

5 5.5 4.0 8.0 5. 74 54 74 Min 4.0 Unit V °C V mA FAST AND LS TTL DATA 5-22 .SN54/74LS12 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 13 * 12 11 10 9 * * J SUFFIX CERAMIC CASE 632-08 14 1 LOW POWER SCHOTTKY 8 1 2 3 4 5 6 7 GND * OPEN COLLECTOR OUTPUTS 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54.25 125 70 5.75 – 55 0 Typ 5.0 25 25 Max 5.5 4.

Output HIGH Total. IIN = – 18 mA VCC = MIN.1 Input LOW Current Power Supply Current Total.4 3. 74 54.0 0.SN54/74LS12 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Current Output LOW Voltage 74 Input HIGH Current 0. VIN = 2.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.25 – 0. 74 0.4 V VCC = MAX mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.7 V VCC = MAX.0 V CL = 15 pF. VOH = MAX IOL = 4.0 mA IOL = 8.65 0. RL = 2. VIN = 0. Input to Output Min Typ 17 15 Max 32 28 Unit ns ns Test Conditions VCC = 5. Input to Output Turn-On Delay.0 V VCC = MAX.5 20 IIH IIL ICC V µA mA mA 54.35 0. VIN = 7. Output LOW – 0.3 0.5 100 0.4 1.4 V µA V Min 2.8 – 1.0 mA VCC = VCC MIN. VIN = VIL or VIH per Truth Table VCC = MAX.0 kΩ FAST AND LS TTL DATA 5-23 .

75 – 55 0 Typ 5. This hysteresis between the positive-going and negative-going input thresholds (typically 800 mV) is determined internally by resistor ratios and is essentially insensitive to temperature and supply voltage variations. and provide different input threshold voltages for positive and negative-going transitions. Additionally.0 5.SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN54LS / 74LS13 and SN54LS / 74LS14 contain logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels.0 8.25 125 70 – 0.4 4.0 Unit V °C mA mA FAST AND LS TTL DATA 5-24 .5 4. they have greater noise margin than conventional inverters. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions.0 25 25 Max 5. jitter-free output signals. 74 54 74 Min 4.5 5. They are capable of transforming slowly changing input signals into sharply defined. LOGIC AND CONNECTION DIAGRAMS VCC 14 13 SN54 / 74LS13 12 11 10 9 8 SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/ HEX INVERTER LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 1 2 3 4 5 6 7 GND 14 1 D SUFFIX SOIC CASE 751A-02 VCC 14 13 SN54 / 74LS14 12 11 10 9 8 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC 1 2 3 4 5 6 7 GND GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output.

0 mA.9 8.0 16 7.6 4. VOUT = 0 V Note 1: Not more than one output should be shorted at a time. VIN = VT– VCC = MAX. VIN = 7.SN54/74LS13 • SN54/74LS14 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VT+ VT– VT+ – VT– VIK VOH Parameter Positive-Going Threshold Voltage Negative-Going Threshold Voltage Hysteresis Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.0 V.0 V VCC = 5.0 20 0.5 0. AC CHARACTERISTICS (TA = 25°C) Max Symbol tPLH tPHL Parameter Propagation Delay. IIN = – 18 mA VCC = MIN.5 V mA mA µA mA mA mA 2.0 V CL = 15 pF 3V VIN 0V tPHL tPLH 1.6 0.1 12 6. IOL = 8. AC Waveforms FAST AND LS TTL DATA 5-25 .25 0.18 1. Input to Output LS13 22 27 LS14 22 22 Unit ns ns Test Conditions VCC = 5.5 Min 1.0 V. 74 VOL IT+ IT– IIH IIL IOS Output LOW Voltage 74 Input Current at Positive-Going Threshold Input Current at Negative-Going Threshold Input HIGH Current 0.4 – 1.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current LS13 Total.35 – 0.6 V 0. VIN = 2. VIN = VT+ VCC = 5. Total Output LOW LS14 LS13 LS14 2.8 V VOUT 1.65 3.0 V VCC = MAX. IOL = 4.5 Typ Max 2.8 – 0.4 V V 2.7 3. Output T t l O t t HIGH ICC Total.0 21 mA VCC = MAX – 20 – 0.4 0.0 V VCC = 5.4 –100 0. IOH = – 400 µA VIN = VIL MIN µA. Input to Output Propagation Delay.0 1.3 V 1.4 V VCC = MAX.0 V VCC = MIN.0 V VCC = MIN.0 mA. VIN = 2.3 V Figure 1. nor for more than 1 second.1 Unit V V V V V Test Conditions VCC = 5. VCC = MIN.0 V VCC = 5.4 0. VIN = 0.7 V VCC = MAX. VIN = 2.14 – 0.

8 2 Figure 2. Threshold Voltage and Hysteresis versus Power Supply Voltage 1.SN54/74LS13 • SN54/74LS14 5 V O .9 V T . POWER SUPPLY VOLTAGE (VOLTS) 5.4 0 4. OUTPUT VOLTAGE (VOLTS) 4 VCC = 5 V TA = 25°C 3 2 1 0 0 0. Threshold Voltage Hysteresis versus Temperature FAST AND LS TTL DATA 5-26 .5 Figure 3.9 0.95 1.2 VT– 0. INPUT VOLTAGE (VOLTS) 1.6 1.1 0.25 VCC. AMBIENT TEMPERATURE (°C) VT+ 125° Figure 4. THRESHOLD VOLTAGE (VOLTS) ∆ V T.3 1. VIN versus VOUT Transfer Function 2 V T .5 1. HYSTERESIS (VOLTS) TA = 25°C VT+ 1.7 – 55° VT– ∆ VT 0° 25° 75° TA.75 5 5.7 1. HYSTERESIS (VOLTS) 1.8 ∆ VT 0.5 4. THRESHOLD VOLTAGE (VOLTS) ∆ V T.2 VIN.4 0.

SN54/74LS15 TRIPLE 3-INPUT AND GATE TRIPLE 3-INPUT AND GATE VCC 14 13 * 12 11 10 9 * * J SUFFIX CERAMIC CASE 632-08 14 1 LOW POWER SCHOTTKY 8 1 2 3 4 5 6 7 GND * OPEN COLLECTOR OUTPUTS 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54.0 8.0 5.5 4.25 125 70 5.5 5.0 25 25 Max 5.5 4.75 – 55 0 Typ 5. 74 54 74 Min 4.0 Unit V °C V mA FAST AND LS TTL DATA 5-27 .

74 54. Output LOW – 0. 74 0.1 Input LOW Current Power Supply Current Total.7 V VCC = MAX.4 V VCC = MAX mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.6 6. Input to Output Min Typ 20 17 Max 35 35 Unit ns ns Test Conditions VCC = 5. Output HIGH Total.65 0.6 0. VIN = 2.0 0.4 V µA V Min 2.0 V VCC = MAX.25 – 0.0 mA IOL = 8.0 kΩ FAST AND LS TTL DATA 5-28 .0 mA VCC = VCC MIN. VIN = VIL or VIH per Truth Table VCC = MAX. Input to Output Turn-On Delay.35 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.5 20 IIH IIL ICC V µA mA mA 54.4 3. VIN = 7. VOH = MAX IOL = 4.8 – 1.5 100 0.SN54/74LS15 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Current Output LOW Voltage 74 Input HIGH Current 0.0 V CL = 15 pF. RL = 2. VIN = 0. IIN = – 18 mA VCC = MIN.

25 125 70 – 0. 74 54 74 Min 4.5 5.0 25 25 Max 5.0 8.0 Unit V °C mA mA FAST AND LS TTL DATA 5-29 .75 – 55 0 Typ 5.4 4.0 5.SN54/74LS20 DUAL 4-INPUT NAND GATE DUAL 4-INPUT NAND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 4.

VIN = 2. IOH = MAX.0 mA IOL = 8.8 2.4 V V 2. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay. Output HIGH Total. VIN = 0.5 – 0.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.4 –100 0. nor for more than 1 second.65 3.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.7 3. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.25 0.0 V VCC = MAX.0 0. VIN = 7.0 V CL = 15 pF FAST AND LS TTL DATA 5-30 .8 – 1. VIN = VIH or VIL per Truth Table IOL = 4. IIN = – 18 mA VCC = MIN.0 10 Max 15 15 Unit ns ns Test Conditions VCC = 5.35 0. Input to Output Min Typ 9.5 V V Min 2.5 20 IIH IIL IOS ICC V µA mA mA mA 2.0 mA VCC = VCC MIN.5 0. Output LOW – 20 – 0. VIN = VIL or VIH per Truth Table VCC = MAX.7 V VCC = MAX.SN54/74LS20 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.5 0. Input to Output Turn-On Delay.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.2 0.

25 125 70 – 0.0 25 25 Max 5. 74 54 74 Min 4.0 5.0 8.0 Unit V °C mA mA FAST AND LS TTL DATA 5-31 .5 4.4 4.5 5.SN54/74LS21 DUAL 4-INPUT AND GATE DUAL 4-INPUT AND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.75 – 55 0 Typ 5.

AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.0 mA IOL = 8. VIN = 2.4 0. VIN = 0.SN54/74LS21 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.0 mA VCC = VCC MIN.5 0. Output HIGH Total. Input to Output Turn-On Delay.0 10 Max 15 20 Unit ns ns Test Conditions VCC = 5.4 4.5 0.7 V VCC = MAX.5 V V Min 2. nor for more than 1 second. Output LOW – 20 – 0. VIN = VIL or VIH per Truth Table VCC = MAX. IIN = – 18 mA VCC = MIN.5 20 IIH IIL IOS ICC V µA mA mA mA 2.5 – 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total. VIN = 7.4 V V 2. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.4 –100 2.0 0.7 3.35 0. Input to Output Min Typ 8.0 V VCC = MAX.25 0.65 3. VIN = VIH or VIL per Truth Table IOL = 4.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 V CL = 15 pF FAST AND LS TTL DATA 5-32 . IOH = MAX.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.8 – 1.

0 8.5 5.75 – 55 0 Typ 5.25 125 70 55 4.0 25 25 Max 5. 74 54 74 Min 4.0 5.0 Unit V °C V mA FAST AND LS TTL DATA 5-33 .5 4.SN54/74LS22 DUAL 4-INPUT NAND GATE DUAL 4-INPUT NAND GATE VCC 14 13 12 11 10 9 * 8 LOW POWER SCHOTTKY * 1 2 3 4 5 6 7 GND * OPEN COLLECTOR OUTPUTS 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54.

65 0. VIN = 2. Input to Output Turn-On Delay.2 0. VIN = 0. 74 54. IIN = – 18 mA VCC = MIN. VIN = 7.0 mA IOL = 8. Input to Output Min Typ 17 15 Max 32 28 Unit ns ns Test Conditions VCC = 5.0 V CL = 15 pF.4 V VCC = MAX mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.8 2.0 kΩ FAST AND LS TTL DATA 5-34 .1 Input LOW Current Power Supply Current Total. RL = 2. VOH = MAX IOL = 4. 74 0.25 – 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. Output LOW – 0.4 0. VIN = VIL or VIH per Truth Table VCC = MAX.4 V µA V Min 2.SN54/74LS22 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Current Output LOW Voltage 74 Input HIGH Current 0. Output HIGH Total.0 mA VCC = VCC MIN.7 V VCC = MAX.5 20 IIH IIL ICC V µA mA mA 54.8 – 1.0 V VCC = MAX.35 0.5 100 0.0 0.

25 125 70 15 4.75 – 55 0 Typ 5.5 5.0 Unit V °C V mA FAST AND LS TTL DATA 5-35 . 74 54 74 Min 4.SN54/74LS26 QUAD 2-INPUT NAND BUFFER • ESD > 3500 Volts QUAD 2-INPUT NAND BUFFER VCC 14 13 12 * 11 10 9 * 8 LOW POWER SCHOTTKY * 1 2 3 4 5 6 * 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 * OPEN COLLECTOR OUTPUTS N SUFFIX PLASTIC CASE 646-06 1 14 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54.0 8.5 4.0 5.0 25 25 Max 5.

VOH = MAX VCC = MIN.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.7 V VCC = MAX. Input to Output Min Typ 17 15 Max 32 28 Unit ns ns Test Conditions VCC = 5.5 1000 V µA µA V Min 2.1 Input LOW Current Power Supply Current Total. RL = 2. 74 54. IIN = – 18 mA VCC = MIN.0 mA VCC = VCC MIN.4 – 0. 74 Output HIGH Current 54. Output HIGH Total.4 1. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. VIN = VIL or VIH per Truth Table VCC = MAX. VOH = 12 V IOL = 4. VIN = 2.0 kΩ FAST AND LS TTL DATA 5-36 .0 V VCC = MAX.5 20 IIH IIL ICC V µA mA mA 0.8 – 1. Output LOW – 0.0 mA IOL = 8.6 4.0 V CL = 15 pF.4 0. Input to Output Turn-On Delay. VIN = 7. VIN = 0.SN54/74LS26 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54.4 V VCC = MAX mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.65 0.35 0.25 50 0.0 0.

5 5.0 25 25 Max 5.0 8.0 5.75 – 55 0 Typ 5.4 4.SN54/74LS27 TRIPLE 3-INPUT NOR GATE TRIPLE 3-INPUT NOR GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 4. 74 54 74 Min 4.0 Unit V °C mA mA FAST AND LS TTL DATA 5-37 .25 125 70 – 0.

IIN = – 18 mA VCC = MIN.5 V V V V V µA mA mA mA IIH IIL IOS ICC VCC = MAX.5 0.SN54/74LS27 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.5 3.35 0.25 0.0 V CL = 15 pF FAST AND LS TTL DATA 5-38 .4 0.4 – 20 –100 4.7 3.0 mA IOL = 8.5 2.0 6. Min 2.4 V VCC = MAX VCC = MAX – 0. VIN = 7. VIN = 2. Output HIGH Total.65 2. IOH = MAX.8 mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay. VIN = VIL or VIH per Truth Table 0. Input to Output Turn-On Delay. Output LOW Note 1: Not more than one output should be shorted at a time.7 V VCC = MAX.0 Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.7 V 0.0 mA VCC = VCC MIN.5 20 – 1. VIN = VIH or VIL per Truth Table IOL = 4.8 – 0. nor for more than 1 second. Input to Output Min Typ 10 10 Max 15 15 Unit ns ns Test Conditions VCC = 5. VIN = 0. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.0 V VCC = MAX.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.

5 5. 74 54 74 Min 4.SN54/74LS28 QUAD 2-INPUT NOR BUFFER QUAD 2-INPUT NOR BUFFER VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.2 12 24 Unit V °C mA mA FAST AND LS TTL DATA 5-39 .0 25 25 Max 5.25 125 70 – 1.5 4.0 5.75 – 55 0 Typ 5.

4 0.5 2. nor for more than 1 second.5 20 – 1.7 V 0. IIN = – 18 mA VCC = MIN.8 – 0.SN54/74LS28 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.4 V VCC = MAX VCC = MAX – 0.65 2. IOH = MAX. Output LOW Note 1: Not more than one output should be shorted at a time.0 V VCC = MAX. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. Output HIGH Total.35 0.4 – 30 –130 3. Min 2.5 0.8 mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay Min Typ 12 12 Max 24 24 Unit ns ns Test Conditions VCC = 5. VIN = VIL or VIH per Truth Table 0.0 V CL = 45 pF. VIN = 2. VIN = 0.5 3.7 V VCC = MAX.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total. VIN = 7.6 13.5 V V V V V µA mA mA mA IIH IIL IOS ICC VCC = MAX.0 Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN. RL = 667 Ω FAST AND LS TTL DATA 5-40 .7 3.25 0.

74 54 74 Min 4.5 5.75 – 55 0 Typ 5.25 125 70 – 0.0 25 25 Max 5.5 4.0 Unit V °C mA mA FAST AND LS TTL DATA 5-41 .0 5.0 8.SN54/74LS30 8-INPUT NAND GATE 8-INPUT NAND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.4 4.

5 2.65 2.5 3. IIN = – 18 mA VCC = MIN. VIN = VIH or VIL per Truth Table IOL = 4.8 – 0.25 0.5 1. VIN = VIL or VIH per Truth Table 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.5 20 – 1. VIN = 2. Input to Output Turn-On Delay.1 mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.0 mA VCC = VCC MIN. Output HIGH Total.7 V VCC = MAX. nor for more than 1 second. VIN = 7. VIN = 0.0 13 Max 15 20 Unit ns ns Test Conditions VCC = 5.5 0.35 0.4 V VCC = MAX VCC = MAX – 0.7 3. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.SN54/74LS30 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.4 0.5 V V V V V µA mA mA mA IIH IIL IOS ICC VCC = MAX.0 mA IOL = 8.0 V CL = 15 pF FAST AND LS TTL DATA 5-42 .4 – 20 –100 0. Input to Output Min Typ 8.0 Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. Min 2. Output LOW Note 1: Not more than one output should be shorted at a time.7 V 0.0 V VCC = MAX. IOH = MAX.

0 5.0 Unit V °C mA mA FAST AND LS TTL DATA 5-43 .5 4.75 – 55 0 Typ 5.0 8.5 5.4 4. 74 54 74 Min 4.0 25 25 Max 5.25 125 70 – 0.SN54/74LS32 QUAD 2-INPUT OR GATE QUAD 2-INPUT OR GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.

0 Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.8 – 0.2 9.7 V VCC = MAX.4 0.5 20 – 1.35 0.5 0.5 V V V V V µA mA mA mA IIH IIL IOS ICC VCC = MAX. nor for more than 1 second. VIN = 2.7 V 0.4 – 20 –100 6.25 0. Output LOW Note 1: Not more than one output should be shorted at a time. VIN = 0.5 2. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.5 3. IOH = MAX.0 V CL = 15 pF FAST AND LS TTL DATA 5-44 .SN54/74LS32 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. Output HIGH Total.65 2. VIN = VIL or VIH per Truth Table 0.0 mA VCC = VCC MIN.7 3. VIN = VIH or VIL per Truth Table IOL = 4. Input to Output Turn-On Delay. IIN = – 18 mA VCC = MIN.0 mA IOL = 8. Min 2.0 V VCC = MAX. Input to Output Min Typ 14 14 Max 22 22 Unit ns ns Test Conditions VCC = 5.8 mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay. VIN = 7.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.4 V VCC = MAX VCC = MAX – 0.

75 – 55 0 Typ 5.5 4.0 25 25 Max 5.0 5.SN54/74LS33 QUAD 2-INPUT NOR BUFFER QUAD 2-INPUT NOR BUFFER VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY * * 1 2 3 4 * 5 * J SUFFIX CERAMIC CASE 632-08 14 1 6 7 GND * OPEN COLLECTOR OUTPUTS 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54. 74 54 74 Min 4.5 12 24 Unit V °C V mA FAST AND LS TTL DATA 5-45 .5 5.25 125 70 5.

IIN = – 18 mA VCC = MIN.0 V VCC = MAX. Output LOW – 0. Output HIGH Total.7 V VCC = MAX. 74 54.8 0. VOH = MAX IOL = 12 mA IOL = 24 mA VCC = VCC MIN.0 0.4 V VCC = MAX mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.0 V. Input to Output Min Typ 20 18 Max 32 28 Unit ns ns Test Conditions VCC = 5.4 3.4 V µA V Min 2.65 0. VIN = 7.6 13. RL = 667 Ω CL = 45 pF FAST AND LS TTL DATA 5-46 .5 20 IIH IIL ICC V µA mA mA 54.25 – 0. VIN = VIL or VIH per Truth Table VCC = MAX. 74 0. VIN = 0.SN54/74LS33 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Current Output LOW Voltage 74 Input HIGH Current 0.35 0. VIN = 2.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. Input to Output Turn-On Delay.1 Input LOW Current Power Supply Current Total.5 250 0.8 – 1.

74 54 74 Min 4.25 125 70 – 1.2 12 24 Unit V °C mA mA FAST AND LS TTL DATA 5-47 .0 5.5 4.75 – 55 0 Typ 5.0 25 25 Max 5.SN54/74LS37 QUAD 2-INPUT NAND BUFFER QUAD 2-INPUT NAND BUFFER VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 5.

25 0. VIN = 2. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.5 2.7 V VCC = MAX. VIN = 0.5 20 – 1.4 0. VIN = VIL or VIH per Truth Table 0. VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN. Output HIGH Total. Min 2.7 3. Input to Output Turn-On Delay. Output LOW Note 1: Not more than one output should be shorted at a time. RL = 667 Ω CL = 45 pF FAST AND LS TTL DATA 5-48 .5 0.65 2.5 3. IOH = MAX.8 – 0. nor for more than 1 second.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total. VIN = 7. IIN = – 18 mA VCC = MIN.0 Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.4 – 30 –130 2.0 12 mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.0 V VCC = MAX.SN54/74LS37 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.0 V.4 V VCC = MAX VCC = MAX – 0. Input to Output Min Typ 12 12 Max 24 24 Unit ns ns Test Conditions VCC = 5.5 V V V V V µA mA mA mA IIH IIL IOS ICC VCC = MAX.35 0.7 V 0.

5 5.5 12 24 Unit V °C V mA FAST AND LS TTL DATA 5-49 .25 125 70 5.75 – 55 0 Typ 5.SN54/74LS38 QUAD 2-INPUT NAND BUFFER QUAD 2-INPUT NAND BUFFER VCC 14 13 12 * 11 10 9 * 8 LOW POWER SCHOTTKY * 1 2 3 4 5 6 * 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 * OPEN COLLECTOR OUTPUTS 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54.0 25 25 Max 5.0 5.5 4. 74 54 74 Min 4.

Input to Output Min Typ 20 18 Max 32 28 Unit ns ns Test Conditions VCC = 5.0 12 0.35 0.4 V VCC = MAX mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.25 – 0. VIN = 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 0.5 250 0. VIN = 2.4 2.5 20 IIH IIL ICC V µA mA mA 54.0 V. Output LOW – 0.8 – 1.0 V VCC = MAX.65 0.4 V µA V Min 2. Input to Output Turn-On Delay. RL = 667 Ω CL = 45 pF FAST AND LS TTL DATA 5-50 . VIN = 7.1 Input LOW Current Power Supply Current Total. VOH = MAX IOL = 12 mA IOL = 24 mA VCC = VCC MIN. 74 0. Output HIGH Total.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.SN54/74LS38 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Current Output LOW Voltage 74 Input HIGH Current 0. IIN = – 18 mA VCC = MIN.4 V VCC = MAX. 74 54.

0 5.5 5.2 12 24 Unit V °C mA mA FAST AND LS TTL DATA 5-51 .75 – 55 0 Typ 5. 74 54 74 Min 4.SN54/74LS40 DUAL 4-INPUT NAND BUFFER DUAL 4-INPUT NAND BUFFER VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 4.0 25 25 Max 5.25 125 70 – 1.

0 0.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.0 V VCC = MAX. IIN = – 18 mA VCC = MIN. Output HIGH Total.SN54/74LS40 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.7 3.8 – 1. VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN.5 0.4 –130 1.5 V V Min 2.0 V. nor for more than 1 second.35 0.0 0. Input to Output Min Typ 12 12 Max 24 24 Unit ns ns Test Conditions VCC = 5.5 20 IIH IIL IOS ICC V µA mA mA mA 2. VIN = 7. IOH = MAX. Input to Output Turn-On Delay.25 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total. VIN = 2. VIN = VIL or VIH per Truth Table VCC = MAX. VIN = 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 6.65 3.5 0.7 V VCC = MAX. Output LOW – 30 – 0. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay. RL = 667 Ω CL = 45 pF FAST AND LS TTL DATA 5-52 .5 – 0.4 V V 2.

L. 16 1 A0 – A3 0 to 9 Address Inputs Outputs.5 U.L. ONE-OF-TEN DECODER LOW POWER SCHOTTKY • • • • Multifunction Capability Mutually Exclusive Outputs Demultiplexing Capability Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 A0 15 A1 14 A2 13 A3 12 9 11 8 10 7 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. for Military (54) and 5 U. 16 1 J SUFFIX CERAMIC CASE 620-09 1 0 2 1 3 2 4 3 5 4 6 5 7 6 8 GND 16 1 N SUFFIX PLASTIC CASE 648-08 PIN NAMES LOADING (Note a) HIGH LOW 0.) = 40 µA HIGH/1.L.SN54/74LS42 ONE-OF-TEN DECODER The LSTTL / MSI SN54 / 74LS42 is a Multipurpose Decoder designed to accept four BCD inputs and provide ten mutually exclusive outputs. Active LOW (Note b) 0.L. The LS42 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.6 mA LOW. ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC LOGIC DIAGRAM A0 15 A1 14 A2 13 A3 12 LOGIC SYMBOL 15 14 13 12 A0 A1 A2 A3 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 9 10 11 1 2 3 4 5 6 7 9 10 11 VCC = PIN 16 GND = PIN 8 0 1 2 3 4 5 6 7 8 9 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FAST AND LS TTL DATA 5-53 . D SUFFIX SOIC CASE 751B-03 NOTES: a) 1 TTL Unit Load (U.L. 5(2.25 U.L.5 U. b) The Output LOW drive factor is 2. 10 U.L.5) U. for Commercial (74) Temperature Ranges.

0 5.75 – 55 0 Typ 5. 74 54 74 Min 4. The logic design of the LS42 ensures that all outputs are HIGH when binary codes greater than nine are applied to the inputs. The active LOW outputs facilitate addressing other MSI units with LOW input enables.0 8.0 Unit V °C mA mA FAST AND LS TTL DATA 5-54 .5 5.SN54/74LS42 FUNCTIONAL DESCRIPTION The LS42 decoder accepts four active HIGH BCD inputs and provides ten mutually exclusive active LOW outputs. as shown by logic symbol or diagram. TRUTH TABLE A0 L H L H L H L H L H L H L H L H A1 L L H H L L H H L L H H L L H H A2 L L L L H H H H L L L L H H H H A3 L L L L L L L L H H H H H H H H 0 L H H H H H H H H H H H H H H H 1 H L H H H H H H H H H H H H H H 2 H H L H H H H H H H H H H H H H 3 H H H L H H H H H H H H H H H H 4 H H H H L H H H H H H H H H H H 5 H H H H H L H H H H H H H H H H 6 H H H H H H L H H H H H H H H H 7 H H H H H H H L H H H H H H H H 8 H H H H H H H H L H H H H H H H 9 H H H H H H H H H L H H H H H H H = HIGH Voltage Level L = LOW Voltage Level GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. The A3 input can also be used as the Data input in an 8-output demultiplexer application. The most significant input A3 produces a useful inhibit function when the LS42 is used as a one-of-eight decoder.0 25 25 Max 5.5 4.25 125 70 – 0.4 4.

7 V VCC = MAX.7 3.5 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 mA IOL = 8.3 V tPHL 1. VIN = 2.0 V CL = 15 pF Test Conditions AC WAVEFORMS VIN 1. VIN = 7.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-55 .4 V V 2.4 –100 13 0.0 mA VCC = VCC MIN. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay (2 Levels) Propagation Delay (3 Levels) Min Typ 15 15 20 20 Max 25 25 30 30 Unit ns ns Figure 2 Figure 1 VCC = 5.3 V tPHL 1.3 V VOUT VOUT 1. IOH = MAX.8 – 1.5 – 0.5 V V Min 2.5 0.0 V VCC = MAX. nor for more than 1 second.0 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = 0.35 0.3 V 1.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. VIN = VIH or VIL per Truth Table IOL = 4. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.25 0.3 V tPLH 1.3 V tPLH 1. IIN = – 18 mA VCC = MIN.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.65 3.3 V VIN 1.SN54/74LS42 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.

6 mA LOW. The relative positive-logic output levels.0 U.25 U. are shown in the truth tables. 0.L. This device also contains an overriding blanking input (BI) which can be used to control the lamp intensity by varying the frequency and duty cycle of the BI input signal or to inhibit the outputs. They offer active LOW. B.25 U.L. input buffers and seven AND-OR-INVERT gates. Open-Collector 8 GND LOW 0.L. C.5) U.L. 15 (7.L. as well as conditions required at the auxiliary inputs. The SN54 / 74LS47 incorporates automatic leading and / or trailing-edge zero-blanking control (RBI and RBO).SN54/74LS47 BCD TO 7-SEGMENT DECODER/DRIVER The SN54 / 74LS47 are Low Power Schottky BCD to 7-Segment Decoder / Drivers consisting of NAND gates. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement available to the seven decoding AND-OR-INVERT gates. The remaining NAND gate and three input buffers provide lamp test. 0. 2.L.5 U.L. for Commercial (74) Temperature Ranges.25 U. 0. to g BCD Inputs Ripple-Blanking Input Lamp-Test Input Blanking Input or Ripple-Blanking Output Outputs 2 C 3 4 5 6 D 7 A HIGH 0. high sink current outputs for driving indicators directly.L. Indicator segments requiring up to 24 mA of current may be driven directly from the SN74LS47 high performance output transistors. D RBI LT BI / RBO a.L. 0.L. Output configurations of the SN54 / 74LS47 are designed to withstand the relatively high voltages required for 7-segment indicators. These outputs will withstand 15 V with a maximum reverse current of 250 µA. BCD TO 7-SEGMENT DECODER/ DRIVER LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 • • • • • Lamp Intensity Modulation Capability (BI/RBO) Open Collector Outputs Lamp Test Provision Leading / Trailing Zero Suppression Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 f 15 g 14 a 13 b 12 c 11 d 10 e 9 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC LOGIC SYMBOL 7 1 2 6 3 5 1 B PIN NAMES A. 0.) = 40 µA HIGH.L. 1. depending on the state of the auxiliary inputs. decodes this data to drive a 7-segment display indicator. 1.5 U.5 V The Output LOW drive factor is 7.L. 0. b) Output current measured at VOUT = 0.5 U. blanking input / ripple-blanking output and ripple-blanking input.L. for Military (54) and 15 U.2 U. Display patterns for BCD input counts above nine are unique symbols to authenticate input conditions.L. A B C D LT RBI BI/ f g RBO LT BI / RBO RBI LOADING (Note a) a b c d e 13 12 11 10 9 15 14 4 VCC = PIN 16 GND = PIN 8 NOTES: a) 1 Unit Load (U. FAST AND LS TTL DATA 5-56 . The circuits accept 4-bit binary-coded-decimal (BCD) and. Lamp test (LT) may be performed at any time which the BI / RBO node is a HIGH level.75 U.5 U.5 U.

(B) When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level regardless of the state of any other input condition. and a LOW level is applied to lamp test input. and D are at LOW level. X = input may be HIGH or LOW. and ripple-blanking input (RBI) must be open or at a HIGH level if blanking of a decimal 0 is not desired. The blanking out (BI) must be open or held at a HIGH level when output functions 0 through 15 are desired.SN54/74LS47 LOGIC DIAGRAM a A b B INPUT C D d BLANKING INPUT OR RIPPLE-BLANKING OUTPUT d c c OUTPUT b a e e f LAMP-TEST INPUT RIPPLE-BLANKING INPUT f g g 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS TRUTH TABLE INPUTS DECIMAL OR FUNCTION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT OUTPUTS LT H H H H H H H H H H H H H H H H X H L RBI H X X X X X X X X X X X X X X X X L X D L L L L L L L L H H H H H H H H X L X C L L L L H H H H L L L L H H H H X L X B L L H H L L H H L L H H L L H H X L X A L H L H L H L H L H L H L H L H X L X BI/RBO H H H H H H H H H H H H H H H H L L H a L H L L H L H L L L H H H L H H H H L b L L L L L H H L L L H H L H H H H H L c L L H L L L L L L L H L H H H H H H L d L H L L H L L H L H L L H L L H H H L e L H L H H H L H L H L H H H L H H H L f L H H H L L L H L L H H L L L H H H L g H H L L L L L H L L L L L L L H H H L NOTE A A B C D H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial NOTES: (A) BI/RBO is wire-AND logic serving as blanking Input (BI) and/or ripple-blanking output (RBO). all segment outputs go to a HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition). (C) When ripple-blanking input (RBI) and inputs A. C. all segment outputs go to a LOW level. (D) When the blanking input/ripple-blanking output (BI/RBO) is open or held at a HIGH level. FAST AND LS TTL DATA 5-57 . B. with the lamp test input at HIGH level.

6 3. IOH = – 50 µ µA. 74 74 2.7 V VCC = MAX.4 0. VO (off) = 15 V IO (on) = 12 mA IO (on) = 24 mA VCC = MAX.3 V tPLH 1.0 25 25 Max 5.1 – 1.0 13 Min 2.4 –2.2 42 0.8 – 1.3 V 1.6 mA IOL = 3. VIN = VIN or VIL per Truth Table IOL = 1.4 0.0 54.2 15 12 24 Unit V °C µA mA V mA Off-State Output Voltage a to g On-State Output Current a to g On-State Output Current a to g DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IO (off) VO ( ) (on) IIH IIL IOS BI / RBO ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage BI / RBO Voltage.4 V VCC = MAX.0 0.25 0.3 V tPHL 1.0 5.25 0. nor for more than 1 second.3 7.5 20 0. RBI Input To Segment Output Min Typ Max 100 100 100 100 Unit ns ns ns ns Test Conditions VCC = 5.5 Typ Max Unit V V V V V V µA V V µA mA mA mA mA Test Conditions Guaranteed Input HIGH Theshold Voltage for All Inputs Guaranteed Input LOW Threshold Voltage g for All Inputs VCC = MIN.3 V VOUT VIN VIN 1.5 5.2 – 0.75 – 55 0 Typ 5.5 4.4 24 54 74 – 0. VIN = 7.0 V VCC = MAX.7 0.3 V tPHL VOUT 1.3 V 1.SN54/74LS47 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL VO (off) IO (on) Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low BI / RBO BI / RBO BI / RBO Parameter 54 74 54 74 54. 74 54 74 Min 4. VIN = 0.65 4. Output LOW Voltage g BI / RBO Off-State Output Current a thru g On-State Output Voltage g a thru g Input HIGH Current Input LOW Current BI / RBO Any Input except BI / RBO Output Short Circuit Current (Note 1) Power Supply Current – 0.0 V CL = 15 pF AC WAVEFORMS 1.35 0. VIN = VIN or VIL per Truth Table. VIN = VIN or VIL per Truth Table VCC = MAX. Address Input to Segment Output Propagation Delay. VOUT = 0 V VCC = MAX Note 1: Not more than one output should be shorted at a time. IIN = – 18 mA VCC = MIN.25 125 70 – 50 1.35 54.2 mA VCC = MIN.5 250 0. 74 54 74 54.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-58 . AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPHL tPLH tPHL tPLH Parameter Propagation Delay. VIN = 2.3 V tPLH 1. VIN = VIH or VIL per Truth Table VCC = MAX. 74 74 0.

as well as conditions required at the auxiliary inputs. depending on the state of the auxiliary inputs. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement available to the seven decoding AND-OR-INVERT gates. The relative positive logic output levels. Lamp Test (LT) may be activated any time when the BI / RBO node is HIGH.SN54/74LS48 BCD TO 7-SEGMENT DECODER The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND gates. input buffers and seven AND-OR-INVERT gates. are shown in the truth tables. decodes this data to drive other components. The LS48 circuit incorporates automatic leading and / or trailing edge zero-blanking control (RBI and RBO). The remaining NAND gate and three input buffers provide lamp test. blanking input/rippleblanking input for the LS48. Both devices contain an overriding blanking input (BI) which can be used to control the lamp intensity by varying the frequency and duty cycle of the BI input signal or to inhibit the outputs. • Lamp Intensity Modulation Capability (BI/RBO) • Internal Pull-Ups Eliminate Need for External Resistors • Input Clamp Diodes Eliminate High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 f 15 g 14 a 13 b 12 c 11 d 10 e 9 D SUFFIX SOIC CASE 751B-03 BCD TO 7-SEGMENT DECODER LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 1 B 2 C 3 4 5 6 D 7 A 8 GND ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD a LT BI / RBO RBI LOGIC DIAGRAM Ceramic Plastic SOIC A b B INPUT C D d BLANKING INPUT OR RIPPLE-BLANKING OUTPUT c OUTPUT LOGIC SYMBOL 7 1 2 6 3 5 A B C D LT RBI SN54 / 74LS48 a b c d e BI/ f g RBO e 13 12 11 10 9 15 14 4 VCC = PIN 16 GND = PIN 8 RIPPLE-BLANKING INPUT LAMP-TEST INPUT f g FAST AND LS TTL DATA 5-59 . The circuit accepts 4-bit binary-coded-decimal (BCD) and.

X=input may be HIGH or LOW. 0.75 U. 0. D RBI LT BI / RBO BI BCD Inputs Ripple-Blanking (Active Low) Input Lamp-Test (Active Low) Input Blanking Input or RippleBlanking Output (Active Low) Blanking (Active Low) Input 0.L. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS TRUTH TABLE SN54 / 74LS48 INPUTS DECIMAL OR FUNCTION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT OUTPUTS LT H H H H H H H H H H H H H H H H X H L RBI H X X X X X X X X X X X X X X X X L X D L L L L L L L L H H H H H H H H X L X C L L L L H H H H L L L L H H H H X L X B A L L H L H L BI / RBO H H H H H H H H H H H H H H H H L L H a H L H H L H L H H H L L L H L L L L H b H H H H H L L H H H L L H L L L L L H c H H L H H H H H H H L H L L L L L L H d H L H H L H H L H L H H L H H L L L H e H L H L L L H L H L H L L L H L L L H f H L L L H H H L H H L L H H H L L L H g L L H H H H H L H H H H H H H L L L H NOTE 1 1 H H L L H L H L H H L L H L H L H H L L H L H L H H X L X X L X NOTES: (1) BI/RBO is wired-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO).L.6 mA LOW b) Outut current measured at VOUT = 0. for Military (54).5 U.25 U. 0.L. 0.L.L.L. (2) When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level.L.2 U. and D are at LOW level. Open-Collector LOADING (Note a) LOW 0.L. C. 3. 0.5 U. (3) When ripple-blanking input (RBI) and inputs A.25 U.75 (1. 0.5 U.L.5 V Output LOW drive factor is SN54LS / 74LS48: 1. B. 1. B.25 U. The blanking out (BI) must be open or held at a HIGH level when output functions 0 through 15 are desired.5 U.L.L. and a LOW level is applied to lamp-test input. 0. 2(1) U. all segment outputs go to a HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition). 3.L. (4) When the blanking input/ripple-blanking output (BI/RBO) is open or held at a HIGH level.L.L.SN54/74LS48 PIN NAMES HIGH A. with the lamp test input at HIGH level. for Commercial (74). all segment outputs go to a LOW level.L.5 U. (48) NOTES: a) Unit Load (U.25) U. and ripple-blanking input (RBI) must be open or at a HIGH level if blanking of a decimal 0 is not desired.25 U.75 U. 0.) = 40 µA HIGH / 1. C.25 U.L. regardless of the state of any other input condition. 2 3 4 FAST AND LS TTL DATA 5-60 .

LOW-to-HIGH Level Output from A Input Propagation Delay Time. IOH = – 50 µ µA.5 20 0. AC CHARACTERISTICS (VCC = 5.0 0. VIN = 7.6 mA IOL = 3.7 0.0 1.4 – 1.4 0.4 V VCC = MAX. per Truth Table VCC = MIN.0 kΩ 60 pF.0 V. 74 54.2 Unit V °C µA µA mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH IO VOL VOL IIH IIL IIL ICC IOS Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output Current a to g Output LOW Voltage a to g Output LOW Voltage g BI / RBO Input HIGH Current (Except BI / RBO) Input LOW Current (Except BI / RBO) Input LOW Current BI / RBO Power Supply Current Short Circuit Current BI / RBO (Note 1) – 0.0 5.5 V µA mA V V V V µA mA mA mA mA mA Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 6. VIN = 0.25 125 70 – 100 – 50 2.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.1 – 0. VIN = 2.0 mA IOL = 1.8 – 1. 74 74 2.2 38 –2.4 24 – 1. VIN = VIH or U.0 mA IOL = 6.0 V VCC = MAX.SN54/74LS48 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOH IOL IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — High Output Current — Low Output Current — Low a to g BI / RBO a to g BI / RBO BI / RBO Parameter 54 74 54 74 54.L. IIN = – 18 mA VCC = MIN.6 3. VO = 0.0 V VIL = VIL MAX VCC = MAX.0 54 74 Min 2.0 25 25 Max 5. LOW-to-HIGH Level Output from RBI Input Min Typ Max 100 100 100 100 Unit ns CL = 15 pF RL = 4.3 25 54. VIH = 2.0 kΩ 40 pF. HIGH-to-LOW Level Output from A Input Propagation Delay Time.85 V Input Conditioner as for VOH IOL = 2. 74 74 54. HIGH-to-LOW Level Output from RBI Input Propagation Delay Time.75 – 55 0 Typ 5.3 4.5 4.7 V VCC = MAX. nor for more than 1 second.2 mA VCC = MIN. 74 54 74 54 74 Min 4.4 0.5 5. ns ns CL = 15 pF RL = 6.5 0.0 V VIL = VIL MAX VCC = MAX.0 0.2 42 – 2. TA = 25°C) Limits Symbol tPHL tPLH tPHL tPLH Parameter Propagation Delay Time. VIH = 2. ns Test Conditions FAST AND LS TTL DATA 5-61 . VIN = 0.

5 4.5 5.4 4.25 125 70 – 0.0 25 25 Max 5. 74 54 74 Min 4.0 5.0 8.0 Unit V °C mA mA FAST AND LS TTL DATA 5-62 .SN54/74LS51 DUAL 2-WIDE 2-INPUT/ 3-INPUT AND-OR-INVERT GATE DUAL 2-WIDE 2-INPUT / 3-INPUT AND-OR-INVERT GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 2 3 4 5 6 7 GND 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.75 – 55 0 Typ 5.

0 mA IOL = 8.4 –100 1. nor for more than 1 second. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.5 20 IIH IIL IOS ICC V µA mA mA mA 2.5 – 0.35 0.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.0 V CL = 15 pF FAST AND LS TTL DATA 5-63 . Output LOW – 20 – 0.0 V VCC = MAX. Input to Output Min Typ 12 12. VIN = 2.7 3.0 0.5 0.0 mA VCC = VCC MIN. VIN = 7.5 V V Min 2.4 V V 2. IOH = MAX.8 0.5 0. Output HIGH Total. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay. VIN = VIH or VIL per Truth Table IOL = 4.6 2. VIN = 0.25 0. VIN = VIL or VIH per Truth Table VCC = MAX. IIN = – 18 mA VCC = MIN.65 3.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.SN54/74LS51 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.7 V VCC = MAX.8 – 1.5 Max 20 20 Unit ns ns Test Conditions VCC = 5.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total. Input to Output Turn-On Delay.

SN54/74LS54 3-2-2-3-INPUT AND-OR-INVERT GATE 3-2-2-3-INPUT AND-OR-INVERT GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 2 3 4 5 6 7 GND 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.0 8.5 4.0 5.5 5.0 25 25 Max 5.25 125 70 – 0.0 Unit V °C mA mA FAST AND LS TTL DATA 5-64 .4 4.75 – 55 0 Typ 5. 74 54 74 Min 4.

0 0. VIN = 2.35 0.6 2.65 3.8 – 1. Input to Output Min Typ 12 12.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.5 – 0. IOH = MAX.4 V V 2.SN54/74LS54 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.5 V V Min 2. nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.7 V VCC = MAX.0 mA VCC = VCC MIN.4 –100 1. VIN = 7.0 V CL = 15 pF FAST AND LS TTL DATA 5-65 . Output HIGH Total. Output LOW – 20 – 0.5 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total. Input to Output Turn-On Delay. IIN = – 18 mA VCC = MIN.0 V VCC = MAX. VIN = 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 mA IOL = 8.5 Max 20 20 Unit ns ns Test Conditions VCC = 5. VIN = VIH or VIL per Truth Table IOL = 4.5 20 IIH IIL IOS ICC V µA mA mA mA 2.7 3. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.5 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 0.25 0.

0 Unit V °C mA mA FAST AND LS TTL DATA 5-66 .SN54/74LS55 2-WIDE 4-INPUT AND-OR-INVERT GATE 2-WIDE 4-INPUT AND-OR-INVERT GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 2 3 4 5 6 7 GND 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.0 5. 74 54 74 Min 4.0 25 25 Max 5.75 – 55 0 Typ 5.5 5.4 4.25 125 70 – 0.0 8.5 4.

4 V V 2.SN54/74LS55 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. VIN = 2.5 0.0 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.35 0.8 1.25 0.65 3.5 0.4 –100 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.7 V VCC = MAX.0 V VCC = MAX.3 0. VIN = VIH or VIL per Truth Table IOL = 4. IOH = MAX.5 Max 20 20 Unit ns ns Test Conditions VCC = 5. VIN = VIL or VIH per Truth Table VCC = MAX.0 mA IOL = 8. Output HIGH Total.5 V V Min 2.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = 7. IIN = – 18 mA VCC = MIN. Input to Output Min Typ 12 12. Input to Output Turn-On Delay. nor for more than 1 second.5 20 IIH IIL IOS ICC V µA mA mA mA 2. VIN = 0.5 – 0.0 V CL = 15 pF FAST AND LS TTL DATA 5-67 .7 3.8 – 1. Output LOW – 20 – 0.0 mA VCC = VCC MIN.

The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed. K C Q D 2 13 10 K C Q D 6 8 VCC = PIN 4 GND = PIN 11 FAST AND LS TTL DATA 5-68 .SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J. clear. h = HIGH Voltage Level L. These dual flip-flops are designed so that when the clock goes HIGH. h (q) = prior to the HIGH to LOW clock transition. DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 Q 13 (8) Q 12 (9) 1 CLEAR 2 (6) K 3 (10) 1 (15) CLOCK (CP) J 14 (7) 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD OUTPUTS K X h h l l Q L q L H q Q H q H L q Ceramic Plastic SOIC MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE CD Reset (Clear) Toggle Load “0” (Reset) Load “1” (Set) Hold L H H H H J X h l h l LOGIC SYMBOL 14 1 3 J CP Q 12 7 5 J CP Q 9 H. Input data is transferred to the outputs on the negative-going edge of the clock pulse. the inputs are enabled and data will be accepted. I = LOW Voltage Level X = Don’t Care l. and clock inputs. h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time l. K.

4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.0 8. VIN = VIH or VIL per Truth Table IOL = 4. VIN = 2.8 –100 6.5 4.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay. 74 54 74 Min 4.5 V V Min 2. g y Clock to Output Min 30 Typ 45 15 15 20 20 Max Unit MHz ns Figure 1 ns Test Conditions Figure 1 VCC = 5.7 3. Clock – 20 0.4 V V 2.5 – 0.0 25 25 Max 5.5 5.5 20 60 80 V µA 2. 74 VOL Output LOW Voltage 74 J.0 5.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. VCC = 5.65 3.4 4.7 V IIL IOS ICC mA mA mA VCC = MAX.25 125 70 – 0. VIN = 7.0 FAST AND LS TTL DATA 5-69 .4 – 0. nor for more than 1 second.0 mA VCC = VCC MIN.5 0. K Clear Clock Input LOW Current Short Circuit Current (Note 1) Power Supply Current J. VIN = 0.8 – 1. IOH = MAX.35 0. AC CHARACTERISTICS (TA = 25°C.SN54/74LS73A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.3 0.0 mA VCC = MAX. VIN = VIL or VIH per Truth Table VCC = MAX. K Clear Clock IIH Input HIGH Current J.0 V 50 F CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW tW ts th Parameter Clock Pulse Width High Clear Pulse Width Setup Time Hold Time Min 20 25 20 0 Typ Max Unit ns ns ns Figure 1 ns Test Conditions Figure 1 Figure 2 VCC = 5 0 V 5.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.75 – 55 0 Typ 5.4 – 0. K Clear.25 0. IIN = – 18 mA VCC = MIN.0 V 0.1 0.5 0.0 mA IOL = 8.

3 V *The shaded areas indicate when the input is permitted to change for predictable output performance. Set and Clear to Output Delays.3 V tW(L) 1. Clock Pulse Width tW SET 1. Data Set-Up and Hold Times.3 V Figure 2.3 V tPLH 1.SN54/74LS73A AC WAVEFORMS J or K * th(L) = 0 ts(L) CP 1.3 V tW CLEAR tPLH 1.3 V tPHL 1.3 V tPLH 1.3 V th(H) = 0 1.3 V tW(H) tPHL Q 1.3 V ts(H) tPLH 1. Figure 1.3 V 1.3 V tPHL Q 1.3 V Q 1.3 V 1. Set and Clear Pulse Widths FAST AND LS TTL DATA 5-70 . Clock to Output Delays.3 V tPHL Q 1.3 V 1 fMAX 1.

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) 14 1 J SUFFIX CERAMIC CASE 632-08 SET (SD) 4 (10) Q 5 (9) CLEAR (CD) 1 (13) CLOCK 3 (11) D 2 (12) 14 N SUFFIX PLASTIC CASE 646-06 1 Q 6 (8) 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Load “1” (Set) Load “0” (Reset) L H L H H SD H L L H H D X X X h l Q H L H H L Q L H H L H OUTPUTS SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 2 3 D SD Q CP CD Q 1 VCC = PIN 14 GND = PIN 7 6 5 12 11 10 D SD Q CP CD Q 13 8 9 * Both outputs will be HIGH while both SD and CD are LOW.SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. I = LOW Voltage Level X = Don’t Care i. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. If the levels at the set and clear are near VIL maximum then we cannot guarantee to meet the minimum level for VOH. h (q) = prior to the HIGH to LOW clock transition. Each flip-flop has individual clear and set inputs. and also complementary Q and Q outputs. h = HIGH Voltage Level L. FAST AND LS TTL DATA 5-71 . h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time i. the D input signal has no effect. H. but the output states are unpredictable if SD and CD go HIGH simultaneously.

0 mA IOL = 8.5 20 40 0.25 0.0 8. Clock Set.7 54 74 – 0.0 V FAST AND LS TTL DATA 5-72 .4 4. Clear IIL IOS ICC Input LOW Current Data.4 Min 2.5 Typ Max Unit V V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.65 3. 74 VOL Output LOW Voltage 74 Input High Current Data.75 – 55 0 Typ 5.0 V mA mA mA VCC = MAX.0 Typ Max Unit ns ns ns Figure 1 ns ns Figure 1 Test Conditions Figure 1 Figure 2 VCC = 5.0 25 25 Max 5. Set Data Setup Time — HIGH Data Setup Time — LOW Hold Time Parameter Min 25 25 20 20 5. Clock Set.5 3.7 V IIH mA VCC = MAX. nor for more than 1 second.35 0.1 0. VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN.25 125 70 – 0.5 0. VIN = 0.0 V 50 F CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW (H) tW (L) ts th Clock Clear. VCC = 5.SN54/74LS74A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. 74 54 74 Min 4.5 4. IOH = MAX.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Clock. Clear Data.7 0.5 5.2 – 0.4 – 0.8 – 1. IIN = – 18 mA VCC = MIN.8 –100 8. VIN = 7.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54 74 54. VIN = VIL or VIH per Truth Table VCC = MAX. AC CHARACTERISTICS (TA = 25°C.0 5.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. Clock Set.0 0. Clear. VIN = 2. Clear Output Short Circuit Current (Note 1) Power Supply Current – 20 0. Clock Clear Set to Output Min 25 Typ 33 13 25 25 40 Max Unit MHz ns ns Test Conditions Figure 1 Figure 1 VCC = 5.0 V µA 2.5 2.

3 V tPHL Q 1.3 V 1 fMAX CP tPHL Q 1.3 V Figure 2.3 V Q 1.3 V tPLH 1.SN54/74LS74A AC WAVEFORMS D* 1.3 V tW(H) 1.3 V 1.3 V 1. Figure 1.3 V tPHL 1. Set and Clear Pulse Widths FAST AND LS TTL DATA 5-73 .3 V tPHL 1.3 V Q *The shaded areas indicate when the input is permitted to change for predictable output performance.3 V th(H) ts(H) tW(L) 1. Clock to Output Delays.3 V th(L) ts(L) 1.3 V tW CLEAR tPLH 1. Clock Pulse Width tW SET 1.3 V tPLH 1.3 V tPLH 1. Data Set-Up and Hold Times. Set and Clear to Output Delays.

0 U.L. 5 (2. The SN54 / 74LS75 features complementary Q and Q output from a 4-bit latch and is available in the 16-pin packages. 1 Enable Input Latches 2.L. the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the Enable is permitted to go HIGH. 14 1 N SUFFIX PLASTIC CASE 646-06 NOTES: a) 1 Unit Load (U.5 U. 1.L.0 U.L. 3 Latch Outputs (Note b) Complimentary Latch Outputs (Note b) 0. For higher component density applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package with Q outputs omitted.L.0 U.0 U.L. 10 U.) = 40 µA HIGH.5 U.L.L. 2. b) The Output LOW drive factor is 2.L. When the Enable goes LOW. 10 U.4-BIT D LATCH The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. 14 1 D SUFFIX SOIC CASE 751A-02 TRUTH TABLE (Each latch) ORDERING INFORMATION tn D H L tn + 1 Q H L NOTES: tn = bit time before enable negative-going transition tn+1 = bit time after enable negative-going transition SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC FAST AND LS TTL DATA 5-74 .L.5) U. 2.L.L. 1. CONNECTION DIAGRAMS DIP (TOP VIEW) Q0 16 Q1 15 Q1 14 E0–1 GND 13 12 Q2 11 Q2 10 Q3 9 16 SN54/74LS75 SN54/74LS77 4-BIT D LATCH LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 1 SN54 / 74LS75 N SUFFIX PLASTIC CASE 648-08 1 1 Q0 Q0 14 2 D0 Q1 13 3 D1 4 5 E2–3 VCC NC 10 6 D2 Q2 9 7 D3 Q3 8 8 Q3 16 E0–1 GND 12 11 16 1 D SUFFIX SOIC CASE 751B-03 SN54 / 74LS77 J SUFFIX CERAMIC CASE 632-08 14 1 1 D0 PIN NAMES 2 D1 3 E2–3 4 VCC 5 D2 6 D3 7 NC LOADING (Note a) HIGH LOW 0.L. for Military (54) and 5 U.25 U. Information present at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will follow the data input as long as the Enable remains HIGH. 5 (2. for Commercial (74) Temperature Ranges. D1–D4 E0–1 E2–3 Q1–Q4 Q1–Q4 Data Inputs Enable Input Latches 0.5) U.

VIN = 0. VIN = 7. VIN = VIL or VIH per Truth Table VCC = MAX. nor for more than 1 second.5 20 80 V µA 2.65 3.4 –1.0 15 14 16 7.35 0. Enable to Q Propagation Delay.8 – 1.0 0.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay.7 3.5 – 0. 74 VOL Output LOW Voltage 74 D Input E Input IIH Input HIGH Current D Input E Input Input LOW Current Short Circuit Current (Note 1) Power Supply Current D Input E Input – 20 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. Data to Q Propagation Delay.0 V 0. VCC = 5.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. IOH = MAX.25 0.5 V V Min 2. VIN = 2.4 V V 2. IIN = – 18 mA VCC = MIN.7 V IIL IOS ICC mA mA mA VCC = MAX.0 12 7. Enable to Q Min Typ 15 9.SN54/74LS75 LOGIC SYMBOLS SN54/74LS75 2 D0 E0–1 E2–3 3 D1 6 D2 7 D3 VCC = PIN 5 GND = PIN 12 12 3 1 SN54/74LS77 2 D1 5 D2 6 D3 VCC = PIN 4 GND = PIN 11 NC = PIN 7.1 0.0 V CL = 15 pF Test Conditions FAST AND LS TTL DATA 5-75 . AC CHARACTERISTICS (TA = 25°C.5 0.0 mA IOL = 8. 10 13 4 D0 E0–1 E2–3 Q0 14 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 16 1 15 14 10 11 9 8 Q1 13 Q2 9 Q3 8 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.0 Max 27 17 20 15 27 25 30 15 Unit ns ns ns ns VCC = 5.6 –100 12 mA VCC = MAX. VIN = VIH or VIL per Truth Table IOL = 4.5 0. Data to Q Propagation Delay.4 – 0.0 mA VCC = VCC MIN.

35 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.5 V V Min 2.65 3.0 10 10 Max 19 17 18 18 Unit ns ns VCC = 5.5 – 0.8 – 1. VCC = 5. VIN = VIL or VIH per Truth Table VCC = MAX. Enable to Q Min Typ 11 9.0 mA VCC = VCC MIN. AC CHARACTERISTICS (TA = 25°C.4 – 0.1 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = 0. IIN = – 18 mA VCC = MIN.25 0.SN54/74LS77 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.0 V) Limits Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay.0 V 0.5 0.5 20 80 V µA 2.0 0.4 V V 2.0 mA IOL = 8. Data to Q Propagation Delay.6 –100 13 mA VCC = MAX. IOH = MAX. nor for more than 1 second.7 V IIL IOS ICC mA mA mA VCC = MAX.5 0. VIN = VIH or VIL per Truth Table IOL = 4. VIN = 2.0 V CL = 15 pF Test Conditions FAST AND LS TTL DATA 5-76 . 74 VOL Output LOW Voltage 74 D Input E Input IIH Input HIGH Current D Input E Input Input LOW Current Short Circuit Current (Note 1) Power Supply Current D Input E Input – 20 0. VIN = 7.7 3.4 –1.

74 54 74 Min 4. FAST AND LS TTL DATA 5-77 . HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition.3 V tPLH tPLH 1.0 Unit V °C mA mA AC SETUP REQUIREMENTS (TA = 25°C. VCC = 5.3 V DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.3 V 1.3 V ts E 1.3 V tPLH Q tPLH 1.0 V Test Conditions AC WAVEFORMS D 1.25 125 70 – 0.4 4.5 4.SN54/74LS75 D SN54/74LS77 LOGIC DIAGRAM DATA ENABLE TO OTHER LATCH Q (SN54/74LS75 ONLY) Q GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.0 25 25 Max 5.3 V 1.75 – 55 0 Typ 5.0 8.3 V 1.3 V tPHL tPHL Q tPHL tPHL 1.3 V th 1. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from HIGH-to-LOW and still be recognized.5 5.0 5.0 V) Limits Symbol tW ts th Parameter Enable Pulse Width High Setup Time Hold Time Min 20 20 0 Typ Max Unit ns ns ns VCC = 5.

K. the inputs are enabled and data will be accepted.SN54/74LS76A DUAL JK FLIP-FLOP WITH SET AND CLEAR The SN54 / 74LS76A offers individual J. DUAL JK FLIP-FLOP WITH SET AND CLEAR LOW POWER SCHOTTKY MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Toggle Load “0” (Reset) Load “1” (Set) Hold L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H q L H q Q L H H q H L q OUTPUTS 16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 *Both outputs will be HIGH while both SD and CD are LOW. h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the HIGH-to-LOW clock transition 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC LOGIC DIAGRAM LOGIC SYMBOL Q Q 16 1 CLEAR (CD) J SET (SD) K 4 K CP J C Q D 3 CLOCK (CP) VCC = PIN 5 GND = PIN 13 14 2 SD Q 15 12 6 9 K CP J C Q D 8 10 7 SD Q 11 FAST AND LS TTL DATA 5-78 .h = HIGH Voltage Level L. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. but the output states are unpredictable if SD and CD go HIGH simultaneously. H.l = LOW Voltage Level X = Immaterial l. Clock Pulse. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions. These dual flip-flops are designed so that when the clock goes HIGH. Direct Set and Direct Clear inputs.

0 mA VCC = MAX.5 – 0. 74 54 74 Min 4. IIN = – 18 mA VCC = MIN.5 5. VIN = 0. VIN = VIL or VIH per Truth Table VCC = MAX. Clock Clear Set to Output 15 20 ns Min 30 Typ 45 15 20 Max Unit MHz ns VCC = 5.0 V 50 F CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW tW ts th Parameter Clock Pulse Width High Clear Set Pulse Width Setup Time Hold Time Min 20 25 20 0 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.4 – 0.0 mA VCC = VCC MIN. K Clear.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = 7.5 4. VCC = 5.0 5.5 V V Min 2.4 V V 2.0 Test Conditions FAST AND LS TTL DATA 5-79 .5 0.35 0.7 V IIL IOS ICC mA mA mA VCC = MAX. Clock – 20 0. AC CHARACTERISTICS (TA = 25°C. VIN = 2.5 20 60 80 V µA 2.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. K Clear Clock Input LOW Current Short Circuit Current (Note 1) Power Supply Current J.8 –100 6.0 0.0 V 0.5 0.3 0. K Clear Clock IIH Input HIGH Current J.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Clock.25 0. Clear.25 125 70 – 0.4 – 0.4 4.SN54/74LS76A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.75 – 55 0 Typ 5.7 3.1 0. VIN = VIH or VIL per Truth Table IOL = 4.8 – 1.65 3. nor for more than 1 second.0 8. IOH = MAX.0 mA IOL = 8.0 25 25 Max 5. 74 VOL Output LOW Voltage 74 J.

L. 0.L. 4-BIT BINARY FULL ADDER WITH FAST CARRY LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 1 A4 2 Σ3 3 A3 4 B3 5 VCC 6 Σ2 7 B2 8 A2 LOADING (Note a) HIGH LOW 0.L. It generates the binary Sum outputs ∑1 – ∑4) and the Carry Output (C4) from the most significant bit.L. The LS83A operates with either active HIGH or active LOW operands (positive or negative logic).5) U. 0.L. 0. 10 U. 1. 16 1 D SUFFIX SOIC CASE 751B-03 NOTES: a) 1 TTL Unit Load (U.L.5 U.0 U.) = 40 µA HIGH/1. CONNECTION DIAGRAM DIP (TOP VIEW) B4 16 Σ4 15 C4 14 C0 13 GND 12 B1 11 A1 10 Σ1 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 10 U.L. 5 (2.6 mA LOW.SN54/74LS83A 4-BIT BINARY FULL ADDER WITH FAST CARRY The SN54 / 74LS83A is a high-speed 4-Bit binary Full Adder with internal carry lookahead. The SN54 / 74LS283 is recommended for new designs since it is identical in function with this device and features standard corner power pins. b) The Output LOW drive factor is 2.25 U.L. ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC LOGIC DIAGRAM C0 A1 13 10 B1 11 A2 8 B2 7 A3 3 B3 4 A4 1 B4 16 VCC = PIN 5 GND = PIN 12 = PIN NUMBERS LOGIC SYMBOL 10 11 8 7 3 4 1 16 B1 A2 B2 A3 B3 A4 B4 C4 ∑1∑2 ∑3 ∑4 C4 9 6 2 15 14 13 C0 14 C1 C2 C3 9 6 2 15 14 ∑1 ∑2 ∑3 ∑4 C4 FAST AND LS TTL DATA 5-80 .0 U.5 U.L.5 U.5 U.L.5) U.L. for Commercial (74) Temperature Ranges. It accepts two 4-bit binary words (A1 – A4.L. for Military (54) and 5 U. B1 – B4) and a Carry Input (C0). 16 1 PIN NAMES N SUFFIX PLASTIC CASE 648-08 A1 – A4 B1 – B4 C0 Σ1 – Σ4 C4 Operand A Inputs Operand B Inputs Carry Input Sum Outputs (Note b) Carry Output (Note b) 1. 5 (2.L.

Note that with active HIGH Inputs. can be arbitrarily assigned to pins 10.5 5.SN54/74LS83A FUNCTIONAL DESCRIPTION The LS83A adds two 4-bit binary words (A plus B) plus the incoming carry.0 8. FUNCTIONAL TRUTH TABLE C (n–1) L L L L H H H H An L L H H L L H H Bn L H L H L H L H ∑n L H H L H L L H Cn L L L H L H H H C1 — C3 are generated internally C0 — is an external input C4 — is an output generated internally GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. Example: C0 Logic Levels Active HIGH Active LOW L 0 1 A1 L 0 1 A2 H 1 0 A3 L 0 1 A4 H 1 0 B1 H 1 0 B2 L 0 1 B3 L 0 1 B4 H 1 0 ∑1 H 1 0 ∑2 H 1 0 ∑3 L 0 1 ∑4 L 0 1 C4 H 1 0 (10+9 = 19) (carry+5+6 = 12) Interchanging inputs of equal weight does not affect the operation. thus C0. B1.0 25 25 Max 5. etc. C0 + (A1+B1)+2(A2+B2)+4(A3+B3)+8(A4+B4) = ∑1+2∑2+4∑3+8∑4+16C4 Where: (+) = plus Due to the symmetry of the binary add function the LS83A can be used with either all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). The binary sum appears on the sum outputs (∑1 – ∑4) and outgoing carry (C4) outputs. A1. Carry Input can not be left open.75 – 55 0 Typ 5.25 125 70 – 0. 11.0 Unit V °C mA mA FAST AND LS TTL DATA 5-81 . 13.5 4.4 4.0 5. 74 54 74 Min 4. but must be held LOW when no carry in is intended.

Any A or B Input to C4 Output Min Typ 16 15 15 15 11 15 11 12 Max 24 24 24 24 17 22 17 17 Unit ns ns ns ns VCC = 5. VIN = 0. C0 Input to C4 Output Propagation Delay.4 V VCC = MAX mA VCC = MAX Note 1: Not more than one output should be shorted at a time. C0 Input to any Σ Output Propagation Delay.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-82 .25 0. VIN = VIL or VIH per Truth Table IIH 20 40 0.5 V µA 2.1 0.3 V tPHL 1.7 V mA VCC = MAX.35 0.5 V V Min 2. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay. IOH = MAX. VIN = 2.3 V tPLH 1.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.3 V VOUT 1.0 0.0 mA IOL = 8.8 –100 39 34 34 VCC = MAX.3 V tPHL 1.5 0.3 V tPLH 1.5 35 0.5 V – 20 0.7 3.4 V V 2.5 V. IIN = – 18 mA VCC = MIN.3 V VIN 1.8 – 1.5 25 – 0.SN54/74LS83A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. nor for more than 1 second.0 mA VCC = VCC MIN.0 V mA mA VCC = MAX. Any A or B Input to Σ Outputs Propagation Delay. VIN = 7.0 V F CL = 15 pF Figures 1 and 2 Test Conditions AC WAVEFORMS VIN 1.4 – 0. 74 VOL Output LOW Voltage 74 Input HIGH Current C0 A or B C0 A or B IIL IOS ICC Input LOW Current C0 A or B Output Short Circuit Current (Note 1) Power Supply Current All Inputs Grounded All Inputs at 4. VIN = VIH MIN MAX per Truth Table IOL = 4. Except B All Inputs at 4.3 V VOUT 1.2 – 0.65 3.

OA < B.5 U. Expander Inputs A Greater Than B Output (Note b) B Greater Than A Output (Note b) A Equal to B Output (Note b) 1.L. 4-BIT MAGNITUDE COMPARATOR LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 • Easily Expandable • Binary or BCD Comparison • OA > B. Operation is not restricted to binary codes. IA < B. For serial (ripple) expansion. B0 – B3). Refer to Applications section of data sheet for high speed method of comparing large words. each word having four Parallel Inputs (A0 – A3.5 U. Three Expander Inputs. IA < B. For proper compare operation. 10 U. B0 – B3 IA = B IA < B.5) U. for Commercial (74) Temperature Ranges.6 mA LOW.L. The Truth Table on the following page describes the operation of the SN54 / 74LS85 under all possible logic conditions. 10 U.L. IA = B = H.5 U. The lower five lines describe the operation under abnormal conditions on the cascading inputs. IA = B.L.L.5) U. “A equal to B” (OA = B).L.SN54/74LS85 4-BIT MAGNITUDE COMPARATOR The SN54 / 74LS85 is a 4-Bit Magnitude Camparator which compares two 4-bit words (A. LOW 0. The upper 11 lines describe the normal operation under all conditions that will occur in a single device or in a series expansion scheme.75 U. 4 2 3 10 12 13 15 9 11 14 1 A0 A1 A2 A3 B0 B1 B2 B3 OA>B IA>B OA<B IA<B OA=B IA=B VCC = PIN 16 GND = PIN 8 5 7 6 NOTES: a) 1 TTL Unit Load (U. allow cascading without external gates.L. FAST AND LS TTL DATA 5-83 .L. 1.L. OA < B and OA = B Outputs are connected respectively to the IA > B.L.75 U.L.L. A3. the device will work with any monotonic code. A > B. IA > B OA > B OA < B OA = B Parallel Inputs A = B Expander Inputs A < B. 5 (2. D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC 1 B3 2 3 IA<B IA=B 8 4 5 6 7 IA>B OA>B OA=B OA<B GND LOGIC SYMBOL PIN NAMES LOADING (Note a) HIGH A0 – A3. b) The Output LOW drive factor is 2. and IA = B Inputs of the next most significant comparator. 5 (2. 0. the Expander Inputs to the least significant position must be connected as follows: IA < B= IA > B = L. 5 (2. B3 being the most significant inputs.L.L. and OA = B Outputs Available CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 A3 15 B2 14 A2 13 A1 12 B1 11 A0 10 B0 9 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. for Military (54) and 5 U. IA > B. Three Outputs are provided: “A greater than B” (OA > B).) = 40 µA HIGH/1. “A less than B” (OA < B).L. 10 U. 0. 0.5) U.5 U. the OA > B.25 U. as shown in Figure 1. B). These conditions occur when the parallel expansion technique is used.

B1 X X X X A1>B1 A1<B1 A1=B1 A1=B1 A1=B1 A1=B1 A1=B1 A1=B1 A1=B1 A0.B3 A3>B3 A3<B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A2.4 4.25 125 70 – 0.B0 X X X X X X A0>B0 A0<B0 A0=B0 A0=B0 A0=B0 A0=B0 A0=B0 CASCADING INPUTS IA>B X X X X X X X X H L X H L IA<B X X X X X X X X L H X H L IA=B X X X X X X X X L L H L L OA>B H L H L H L H L H L L L H OUTPUTS OA<B L H L H L H L H L H L L H OA=B L L L L L L L L L L H L L H = HIGH Level L = LOW Level X = IMMATERIAL GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.0 8.0 Unit V °C mA mA FAST AND LS TTL DATA 5-84 .5 5.B2 X X A2>B2 A2<B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A1.SN54/74LS85 LOGIC DIAGRAM A3 (15) B3 (1) (5) OA>B A2 B2 (13) (14) (2) A<B (3) A=B (4) A>B A1 B1 (12) (11) (6) OA=B (7) OA<B A0 B0 (10) (9) TRUTH TABLE COMPARING INPUTS A3.75 – 55 0 Typ 5.0 5. 74 54 74 Min 4.5 4.0 25 25 Max 5.

2. Table 1 WORD LENGTH 1 – 4 Bits 5 – 24 Bits 25 – 120 Bits NUMBER OF PKGS.SN54/74LS85 A n3 A n2 A n1 B n3 B n2 B n1 An A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 OA > B IA > B IA < B SN54/74LS85 OA < B OA = B IA = B Bn L L H A0 A1 A2 A3 B0 B1 B2 B3 IA > B OA > B IA < B SN54/74LS85 OA < B OA = B IA = B A>B A<B A=B L = LOW LEVEL H = HIGH LEVEL Figure 1. Comparison of Two 24-Bit Words FAST AND LS TTL DATA 5-85 . see Table 1. L L H A19 B19 L INPUTS A5 A6 A7 A8 B5 B6 B7 B8 A0 A1 A2 A3 B0 B1 B2 B3 OA > B IA > B #4 IA < B OA < B IA = B OA = B A10 A11 A12 A13 B10 B11 B12 B13 A0 A1 A2 A3 B0 B1 B2 B3 OA > B IA > B #3 OA < B IA < B IA = B OA = B A15 A16 A17 A18 B15 B16 B17 B18 A0 A1 A2 A3 B0 B1 B2 B3 OA > B IA > B #2 OA < B IA < B IA = B OA = B A4 B4 L A9 B9 NC L A14 B14 NC L NC A0 A1 A2 A3 B0 B1 B2 B3 IA > B OA > B IA < B OA < B #6 IA = B OA = B OUTPUTS MSB = MOST SIGNIFICANT BIT LSB = LEAST SIGNIFICANT BIT L = LOW LEVEL H = HIGH LEVEL NC = NO CONNECTION Figure 2. six levels of device delay result when comparing two 24-bit words. Comparing Two n-Bit Words APPLICATIONS Figure 2 shows a high speed method of comparing two 24-bit words with only two levels of device delay. The parallel technique can be expanded to any number of bits. 1 2–6 8 – 31 INPUTS (LSB) A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 IA > B OA > B #5 OA < B IA < B IA = B OA = B (MSB) A20 A21 A22 A23 B20 B21 B22 B23 A0 A1 A2 A3 B0 B1 B2 B3 IA > B OA > B IA < B #1 OA < B IA = B OA = B NC NOTE: The SN54/74LS85 can be used as a 5-bit comparator only when the outputs are used to drive the A0–A3 and B0–B3 inputs of another SN54/74LS85 as shown in Figure 2 in positions #1. 3. With the technique shown in Figure 1. and 4.

3 V VIN 1.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. 74 VOL Output LOW Voltage 74 Input HIGH Current A < B. VIN = 2.0 mA IOL = 8.3 – 0.3 V tPLH 1.7 3.2 –100 20 VCC = MAX.0 0.5 25 – 0.35 0. A > B Other Inputs Output Short Circuit Current (Note 1) Power Supply Current – 20 0.5 35 0. A > B Any A or B to A = B A < B or A = B to A > B A = B to A = B A > B or A = B to A < B Min Typ 24 20 27 23 14 11 13 13 14 11 Max 36 30 45 45 22 17 20 26 22 17 Unit ns ns ns ns ns VCC = 5.0 mA VCC = VCC MIN.3 V VOUT 1.3 V tPLH 1. AC CHARACTERISTICS (TA = 25°C.SN54/74LS85 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Any A or B to A < B. VIN = VIL or VIH per Truth Table IIH 20 60 0.5 V µA 2. A > B Other Inputs A < B. A > B Other Inputs IIL IOS ICC Input LOW Current A < B.5 V V Min 2. VCC = 5. IIN = – 18 mA VCC = MIN.3 V Figure 3 Figure 4 FAST AND LS TTL DATA 5-86 . IOH = MAX. VIN = VIH MIN MAX or VIL per Truth Table IOL = 4.4 – 1.25 0.3 V tPHL 1.4 V V 2. VIN = 7.5 0.1 0.7 V mA VCC = MAX. nor for more than 1 second.0 V mA mA mA VCC = MAX.3 V VOUT 1. VIN = 0.3 V tPHL 1.8 – 1.65 3.0 V CL = 15 pF Test Conditions AC WAVEFORMS VIN 1.

74 54 74 Min 4.4 4.0 8.0 5.5 4.0 Unit V °C mA mA FAST AND LS TTL DATA 5-87 .SN54/74LS86 QUAD 2-INPUT EXCLUSIVE OR GATE QUAD 2-INPUT EXCLUSIVE OR GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 2 3 4 5 6 7 GND 1 14 N SUFFIX PLASTIC CASE 646-06 1 TRUTH TABLE IN A L L H H B L H L H OUT Z L H H L 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.0 25 25 Max 5.5 5.25 125 70 – 0.75 – 55 0 Typ 5.

7 3. VIN = 7. VIN = VIH or VIL per Truth Table IOL = 4.5 0.5 40 IIH IIL IOS ICC V µA mA mA mA mA 2.25 0. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. nor for more than 1 second.0 V VCC = MAX.35 0.7 V VCC = MAX.2 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. IOH = MAX. VIN = 0.4 V V 2. Other Input HIGH Min Typ 12 10 20 13 Max 23 17 30 22 Unit ns ns VCC = 5. VIN = VIL or VIH per Truth Table VCC = MAX.8 –100 10 0. Other Input LOW Propagation Delay. VIN = 2. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.SN54/74LS86 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.5 – 0.0 0. IIN = – 18 mA VCC = MIN.8 – 1.0 V CL = 15 pF Test Conditions FAST AND LS TTL DATA 5-88 .65 3.0 mA VCC = VCC MIN.5 0.0 mA IOL = 8.5 V V Min 2.

L.25 U. 5 (2. Each counter has a divide-by-two section and either a divide-by-five (LS90). LOW 1. 4-BIT BINARY COUNTER LOW POWER SCHOTTKY • Low Power Consumption .L. 1.L. Temperature Ranges. . 0.5) U.5 U. .5 U. 5 (2. Each section can be used separately or tied together (Q to CP) to form BCD. 10 U. d. The Output LOW drive factor is 2. Typically 45 mW • High Count Rates .5 U.0 U. Binary • Input Clamp Diodes Limit High Speed Termination Effects PIN NAMES LOADING (Note a) HIGH CP0 CP1 CP1 MR1. modulo-12. 10 U.DECADE COUNTER.L. 13 LS92 LS93 14 1 FAST AND LS TTL DATA 5-89 . 4. b. 0.L. BCD. .5 U. 13 14 1 CP0 CP1 MR Q0 Q1 Q2 Q3 1 2 2 3 12 9 8 11 VCC = PIN 5 GND = PIN 10 NC = PIN 4.5) U. LOGIC SYMBOL LS90 6 7 1 2 MS CP0 CP1 MR Q0 Q1 Q2 Q3 1 2 2 3 12 9 8 11 VCC = PIN 5 GND = PIN 10 NC = PINS 4.5 U. ÷6 (LS92).5 U. divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs.L. 0. (54) and 5 U. MS2 Q0 Q1. 0. Bi-Quinary. 0.L.L. 3. 1 TTL Unit Load (U. DIVIDE-BY-TWELVE COUNTER.L. DIVIDE-BY-TWELVE COUNTER. Q3 Clock (Active LOW going edge) Input to ÷2 Section Clock (Active LOW going edge) Input to ÷5 Section (LS90). SN54 / 74LS92 and SN54 / 74LS93 are high-speed 4-bit ripple type counters partitioned into two sections. . The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.L.L. All of the counters have a 2-input gated Master Reset (Clear). 13 14 1 CP0 CP1 MR Q0 Q1 Q2 Q3 1 2 6 7 12 11 9 8 VCC = PIN 5 GND = PIN 10 NC = PINS 2. Q2.L.L.0 U. 0. 7. ÷8 (LS93) Sections (Note b) 0.L. ÷6 Section (LS92) Clock (Active LOW going edge) Input to ÷8 Section (LS93) Master Reset (Clear) Inputs Master Set (Preset-9. 4-BIT BINARY COUNTER The SN54 / 74LS90. and the LS90 also has a 2-input gated Master Set (Preset 9). for commercial (74) b. bi-quinary. or modulo-16 counters. .L. 6. MR2 MS1.6 mA LOW. Typically 42 MHz • Choice of Counting Modes . To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.L. 14 14 1 J SUFFIX CERAMIC CASE 632-08 N SUFFIX PLASTIC CASE 646-06 1 2. c. 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC NOTES: a. SN54/74LS90 SN54/74LS92 SN54/74LS93 DECADE COUNTER.5 U.L.) = 40 µA HIGH/1.25 U. . LS90) Inputs Output from ÷2 Section (Notes b & c) Outputs from ÷5 (LS90). Divide-by-Twelve. for Military.

LOGIC DIAGRAM LS92 CONNECTION DIAGRAM DIP (TOP VIEW) CP1 1 14 CP0 13 NC 12 Q0 11 Q1 10 GND 9 Q2 8 Q3 CP0 14 J Q J Q J Q J Q NC 2 NC 3 NC 4 VCC 5 MR1 6 CP KC Q D 1 CP KC Q D CP KC Q D CP KC Q D CP1 6 MR1 MR2 12 7 11 9 8 MR2 7 Q3 Q0 Q1 Q2 NC = NO INTERNAL CONNECTION = PIN NUMBERS VCC = PIN 5 GND = PIN 10 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. FAST AND LS TTL DATA 5-90 . LOGIC DIAGRAM LS93 CONNECTION DIAGRAM DIP (TOP VIEW) CP1 1 14 CP0 13 NC 12 Q0 11 Q3 10 GND 9 Q1 8 Q2 CP0 14 J CP Q J CP Q J CP Q J CP Q MR1 2 MR2 3 NC 4 VCC 5 NC 6 KC Q D 1 KC Q D KC Q D KC Q D CP1 MR1 MR2 2 12 3 9 8 11 Q0 Q1 Q2 Q3 = PIN NUMBERS VCC = PIN 5 GND = PIN 10 NC 7 NC = NO INTERNAL CONNECTION NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.SN54/74LS90 • SN54/74LS92 • SN54/74LS93 LOGIC DIAGRAM LS90 MS1 MS2 6 7 CONNECTION DIAGRAM DIP (TOP VIEW) CP1 1 14 CP0 13 NC 12 Q0 11 Q3 10 GND 9 Q1 8 Q2 14 S J DQ CP KC Q D S J DQ CP KC Q D S J DQ CP KC Q D S R DQ CP SC Q D MR1 2 MR2 3 NC 4 VCC 5 MS1 6 CP0 1 CP1 MR1 MR2 2 12 3 9 8 11 MS2 7 Q3 Q0 Q1 Q2 = PIN NUMBERS VCC = PIN 5 GND = PIN 10 NC = NO INTERNAL CONNECTION NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

FAST AND LS TTL DATA 5-91 . the devices may be operated in various counting modes. BCD Decade (8421) Counter — The CP1 input must be externally connected to the Q0 output. Q2. divide-by-six (LS92). The CP0 input receives the incoming count and Q3 produces a symmetrical divide-by-twelve square wave output. The input count is then applied to the CP1 input and a divide-byten square wave is obtained at output Q0. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter. decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. or divide-by-eight (LS93) section. The CP1 input is used to obtain divide-by-three operation at the Q1 and Q2 outputs and divide-by-six operation at the Q3 output. Simultaneous divisions of 2. and Q3 outputs as shown in the truth table. 3-Bit Ripple Counter— The input count pulses are applied to input CP1. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. 4. LS92 A. and 8 are available at the Q1. A gated AND asynchronous Master Reset (MR1 • MR2) is provided on all counters which overrides and clocks and resets (clears) all the flip-flops. LS93 A. Q1. Q2. B. B. The first flip-flop is used as a binary element for the divide-by-two function (CP0 as the input and Q0 as the output). Since the output from the divide-by-two section is not internally connected to the succeeding stages. LS92. Divide-By-Two and Divide-By-Six Counter —No external interconnections are required. and 16 are performed at the Q0. The CP1 input is used to obtain binary divide-by-five operation at the Q3 output. Each section has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW clock transition.SN54/74LS90 • SN54/74LS92 • SN54/74LS93 FUNCTIONAL DESCRIPTION The LS90. Simultaneous frequency divisions of 2. Each device consists of four master/slave flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five (LS90). Modulo 12. 4. B. Divide-By-Two and Divide-By-Five Counter — No external interconnections are required. C. Divide-By-Twelve. The Q0 output of each device is designed and specified to drive the rated fan-out plus the CP1 input of the device. Therefore. and Q3 outputs. 8. The CP0 input receives the incoming count and a BCD count sequence is produced. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3 output must be externally connected to the CP0 input. Divide-By-Twelve Counter — The CP1 input must be externally connected to the Q0 output. and Binary Counters respectively. A gated AND asynchronous Master Set (MS1 • MS2) is provided on the LS90 which overrides the clocks and the MR inputs and sets the outputs to nine (HLLH). 4-Bit Ripple Counter — The output Q0 must be externally connected to input CP1. and LS93 are 4-bit ripple type Decade. LS90 A. The input count pulses are applied to input CP0. The first flip-flop is used as a binary element for the divide-by-two function.

SN54/74LS90 • SN54/74LS92 • SN54/74LS93 LS90 MODE SELECTION RESET / SET INPUTS MR1 MR2 MS1 MS2 H H X L X L X H H X X L X L L X H L X X L X L H X L L X Q0 L L H OUTPUTS Q1 Q2 Q3 L L H LS92 AND LS93 MODE SELECTION RESET INPUTS MR1 MR2 H L H L H H L L Q0 L OUTPUTS Q1 Q2 Q3 L L L L L L L Count Count Count Count L L Count Count Count H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care LS90 BCD COUNT SEQUENCE OUTPUT COUNT 0 1 2 3 4 5 6 7 8 9 Q0 L H L H L H L H L H Q1 L L H H L L H H L L Q2 L L L L H H H H L L Q3 L L L L L L L L H H LS92 TRUTH TABLE OUTPUT COUNT 0 1 2 3 4 5 6 7 8 9 10 11 Q0 L H L H L H L H L H L H Q1 L L H H L L L L H H L L Q2 L L L L H H L L L L H H Q3 L L L L L L H H H H H H LS93 TRUTH TABLE OUTPUT COUNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q0 L H L H L H L H L H L H L H L H Q1 L L H H L L H H L L H H L L H H Q2 L L L L H H H H L L L L H H H H Q3 L L L L L L L L H H H H H H H H NOTE: Output Q0 is connected to Input CP1 for BCD count. NOTE: Output Q0 is connected to Input CP1. NOTE: Output Q0 is connected to Input CP1. FAST AND LS TTL DATA 5-92 .

0 0.5 V V Min 2. VIN = 2.4 – 3.4 V IOS ICC mA mA VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.0 mA VCC = VCC MIN.8 – 1.0 8. IIN = – 18 mA VCC = MIN.7 3.35 0.1 Input LOW Current MS.5 4.65 3.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 5.75 – 55 0 Typ 5. nor for more than 1 second.7 V VCC = MAX.0 25 25 Max 5.4 – 2.5 – 0.5 5. VIN = 7.0 V IIL mA VCC = MAX.5 20 IIH V µA mA 2.4 V V 2. MR CP0 CP1 (LS90.2 – 1. LS92) CP1 (LS93) Short Circuit Current (Note 1) Power Supply Current – 20 – 0. VIN = VIH or VIL per Truth Table IOL = 4. VIN = 0.0 mA IOL = 8.4 4.SN54/74LS90 • SN54/74LS92 • SN54/74LS93 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 0. VIN = VIL or VIH per Truth Table VCC = MAX. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. FAST AND LS TTL DATA 5-93 .25 125 70 – 0.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.25 0.5 0. IOH = MAX. 74 54 74 Min 4.6 –100 15 0.

3 V tW 1.3 V Figure 1 *The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.0 V.3 V tW 1.3 V CP Q0 • Q3 (LS90) tPLH 1.3 V trec 1.SN54/74LS90 • SN54/74LS92 • SN54/74LS93 AC CHARACTERISTICS (TA = 25°C.3 V 1.3 V CP tPHL Q 1. VCC = 5.3 V tW 1.3 V tPLH 1. CL = 15 pF) Limits LS90 Symbol fMAX fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter CP0 Input Clock Frequency CP1 Input Clock Frequency Propagation Delay.3 V tPHL Q 1.3 V Figure 2 Figure 3 FAST AND LS TTL DATA 5-94 .3 V trec 1.0 V) Limits LS90 Symbol tW tW tW tW trec Parameter CP0 Pulse Width CP1 Pulse Width MS Pulse Width MR Pulse Width Recovery Time MR to CP Min 15 30 15 15 25 15 25 15 25 Max Min 15 30 LS92 Max Min 15 30 LS93 Max Unit ns ns ns ns ns RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognize and transfer HIGH data to the Q outputs AC WAVEFORMS *CP 1. VCC = 5.3 V MS 1. MR & MS 1. CP0 Input to Q0 Output CP0 Input to Q3 Output CP1 Input to Q1 Output CP1 Input to Q2 Output CP1 Input to Q3 Output MS Input to Q0 and Q3 Outputs MS Input to Q1 and Q2 Outputs MR Input to Any Output Min 32 16 10 12 32 34 10 14 21 23 21 23 20 26 26 16 18 48 50 16 21 32 35 32 35 30 40 40 26 40 26 40 Typ Max Min 32 16 10 12 32 34 10 14 10 14 21 23 16 18 48 50 16 21 16 21 32 35 LS92 Typ Max Min 32 16 10 12 46 46 10 14 21 23 34 34 16 18 70 70 16 21 32 35 51 51 LS93 Typ Max Unit MHz MHz ns ns ns ns ns ns ns ns AC SETUP REQUIREMENTS (TA = 25°C.

L.L. 74 54 74 Min 4. for Military (54) and 5 U.25 125 70 – 0.L.5) U.L.25 U.) = 40 µA HIGH/1. NOTES: a.5 U. Expandable Shift Right Synchronous Shift Left Capability Synchronous Parallel Load Separate Shift and Load Clock Inputs Input Clamp Diodes Limit High Speed Termination Effects 14 1 J SUFFIX CERAMIC CASE 632-08 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 Q0 13 Q1 12 Q2 11 Q3 10 CP1 9 CP2 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L. The data is transferred from the serial or parallel D inputs to the Q outputs synchronous with the HIGH to LOW transition of the appropriate clock input. 14 1 N SUFFIX PLASTIC CASE 646-06 VCC = PIN 14 GND = PIN 7 1 DS 2 P0 3 P1 4 P2 5 P3 6 S 7 GND 14 1 D SUFFIX SOIC CASE 751A-02 PIN NAMES LOADING (Note a) HIGH LOW 0. 10 U.L. 0. 4-BIT SHIFT REGISTER LOW POWER SCHOTTKY • • • • • Synchronous.L.0 Unit V °C mA mA FAST AND LS TTL DATA 5-95 .SN54/74LS95B 4-BIT SHIFT REGISTER The SN54/74LS95B is a 4-Bit Shift Register with serial and parallel synchronous operating modes.0 5. 0.L.L. The Output LOW drive factor is 2.25 U.25 U.5 5.75 – 55 0 Typ 5.5 U.0 25 25 Max 5. The LS95B is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.5 U. The serial shift right and parallel load are activated by separate clock inputs which are selected by a mode control input. 1 TTL Unit Load (U. 0. for Commercial (74) Temperature Ranges.6 mA LOW.25 U.L. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 U.5 U. 0.L.L.L. 0.L.L. ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC S DS P0 – P3 CP1 CP2 Q0 – Q3 Mode Control Input Serial Data Input Parallel Data Inputs Serial Clock (Active LOW Going Edge) Input Parallel Clock (Active LOW Going Edge) Input Parallel Outputs (Note b) 0.4 4. 5 (2.5 U. 0. 0. 0. b.25 U.0 8.5 4.

Q1 to Q2. The serial or parallel mode of operation is controlled by a Mode Control input (S) and two Clock Inputs (CP1) and (CP2). A left-shift is accomplished by externally connecting Q3 to P2. and operating the LS95B in the parallel mode (S = HIGH). S should only change states when both Clock inputs are LOW. CP1 is enabled. h = HIGH Voltage Level one set-up time prior to the HIGH to LOW clock transition. The serial (right-shift) or parallel data transfers occur synchronous with the HIGH to LOW transition of the selected clock input. When the Mode Control input (S) is LOW. or changing S from HIGH to LOW while CP1 is HIGH and CP2 is LOW will not cause any changes on the register outputs. Pn = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the Pn = HIGH to LOW clock transition. MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE S Shift Parallel Load L L H X L L H H L L H H L L L L H H H H CP1 CP2 X X DS I h X X X X X X X X X Pn X X Pn X X X X X X X X Q0 L H P0 Q1 q0 q0 P1 Q2 q1 q1 P2 Q3 q2 q2 P3 OUTPUTS Mode Change No Change No Change No Change Undetermined Undetermined No Change Undetermined No Change L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care I = LOW Voltage Level one set-up time prior to the HIGH to LOW clock transition. A HIGH to LOW transition on enabled CP2 transfers parallel data from the P0 – P3 inputs to the Q0 – Q3 outputs. and Q2 to Q3 respectively (right-shift). It has a Serial (DS) and four Parallel (P0 – P3) Data inputs and four Parallel Data outputs (Q0 – Q3). CP2 is enabled. Q2 to P1. However. FAST AND LS TTL DATA 5-96 . For normal operation. A HIGH to LOW transition on enabled CP1 transfers the data from Serial input (DS) to Q0 and shifts the data in Q0 to Q1.SN54/74LS95B LOGIC DIAGRAM P0 6 2 P1 3 P2 4 P3 5 S 1 DS 9 CP1 8 CP2 R R R R S VCC = PIN 14 GND = PIN 7 = PIN NUMBERS Q 13 S Q 12 S Q 11 S Q 10 Q0 Q1 Q2 Q3 FUNCTIONAL DESCRIPTION The LS95B is a 4-Bit Shift Register with serial and parallel synchronous operating modes. changing S from LOW to HIGH while CP2 is HIGH. When the Mode Control input (S) is HIGH. and Q1 to P0.

VIN = 7.0 mA IOL = 8.4 –100 21 0. VIN = VIH or VIL per Truth Table IOL = 4.8 – 1.SN54/74LS95B DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.7 3.35 0.0 V VCC = MAX.4 V V 2.0 mA VCC = VCC MIN.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VCC = 5. IOH = MAX.0 0.5 – 0.0 V Test Conditions FAST AND LS TTL DATA 5-97 .1 Input HIGH Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0. IIN = – 18 mA VCC = MIN.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.5 0.5 0.0 V 50 CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C.65 3.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. VIN = 0. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. nor for more than 1 second. VIN = VIL or VIH per Truth Table VCC = MAX.5 V V Min 2.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency CP to Output 21 32 ns Min 25 Typ 36 18 27 Max Unit MHz ns VCC = 5. VCC = 5.7 V VCC = MAX. VIN = 2.0 V) Limits Symbol tW ts th ts th CP Pulse Width Data Setup Time Data Hold Time Mode Control Setup Time Mode Control Hold Time Parameter Min 20 20 20 20 20 Typ Max Unit ns ns ns ns ns VCC = 5. AC CHARACTERISTICS (TA = 25°C.25 0.

D 1.3 V 1. ts(H) 1.3 V 1. AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance.3 V 1.3 V 1. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from HIGH to LOW and still be recognized.3 V Figure 1 (H → L ONLY) (L → H ONLY) (L → H ONLY) S ts(H) ts(L) 1.3 V 1.3 V l/fmax tW 1.SN54/74LS95B DESCRIPTION OF TERMS SETUP TIME(ts) —is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from HIGH to LOW in order to be recognized and transferred to the outputs.3 V th(H) *The Data Input is (DS for CP1) or (Pn for CP2).3 V tW 1.3 V 1.3 V Figure 2 FAST AND LS TTL DATA 5-98 .3 V 1.3 V tPLH 1.3 V th(L) CP1 1.3 V ts(L) 1.3 V th(L) ts(L) 1.3 V CP1 or CP2 tPHL Q 1.3 V tW ts(H) ts(L) th(H) CP2 1.3 V STABLE ts(H) th(L OR H) 1. HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH to LOW that the logic level must be maintained at the input in order to ensure continued recognition.

14 1 J SUFFIX CERAMIC CASE 632-08 1 J1 2 Q1 3 Q1 4 K1 5 Q2 6 Q2 7 GND 14 1 N SUFFIX PLASTIC CASE 646-06 LOGIC SYMBOL 1 1 J Q 3 8 J 2 Q 5 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION 12 CP 9 CP SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC 4 K CD 13 Q 2 11 K CD 10 Q 6 VCC = PIN 14 GND = PIN 7 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. The SN54 / 74LS107A is the same as the SN54 / 74LS73A but has corner power pins.0 25 25 Max 5. DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 CD1 13 CP1 12 K2 11 CD2 10 CP2 9 J2 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.75 – 55 0 Typ 5.0 5. Output changes are initiated by the HIGH-to-LOW transition of the clock. K.25 125 70 – 0.5 4.5 5. A LOW signal on CD input overrides the other inputs and makes the Q output LOW. Direct Clear and Clock Pulse inputs.0 Unit V °C mA mA FAST AND LS TTL DATA 5-99 . 74 54 74 Min 4.SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J.0 8.4 4.

K Clear Clock IIH Input HIGH Current J. 74 VOL Output LOW Voltage 74 J. AC CHARACTERISTICS (TA = 25°C. IOH = MAX.4 V V 2.25 0. K Clear and Clock – 20 0. VIN = 0.5 0.1 0. VCC = 5.8 – 1.8 –100 6. g y Clock to Output Min 30 Typ 45 15 15 20 20 Max Unit MHz ns ns VCC = 5. nor for more than 1 second.5 – 0. VIN = VIL or VIH per Truth Table VCC = MAX. VIN = 7.4 – 0.5 V V Min 2.0 mA VCC = VCC MIN.4 – 0. K Clear Clock Input LOW Current Short Circuit Current (Note 1) Power Supply Current J. VIN = VIH or VIL per Truth Table IOL = 4.0 V 0.0 mA VCC = MAX.3 0.7 V IIL IOS ICC mA mA mA VCC = MAX.0 Test Conditions FAST AND LS TTL DATA 5-100 .7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.5 0. VCC = 5.0 V 50 CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C.0 mA IOL = 8.35 0.0 0.5 20 60 80 V µA 2.0 V) Limits Symbol tW tW ts th Parameter Clock Pulse Width Clear Pulse Width Setup Time Hold Time Min 20 25 20 0 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.65 3.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. IIN = – 18 mA VCC = MIN.SN54/74LS107A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay. VIN = 2.7 3.

but the output states are unpredictable if SD and CD go HIGH simultaneously.SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. h (q) = one set-up time prior to the LOW to HIGH clock transition. LOGIC DIAGRAM DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY SET (SD) 5(11) CLEAR (CD) 1(15) CLOCK 4(12) Q 6(10) J SUFFIX CERAMIC CASE 620-09 16 1 J 2(14) K 3(13) Q 7(9) 16 1 N SUFFIX PLASTIC CASE 648-08 16 MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Load “1” (Set) Hold Toggle Load “0” (Reset) L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H H q q L Q L H H L q q H OUTPUTS 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 5 2 4 3 J SD Q CP K C Q D 1 VCC = PIN 16 GND = PIN 8 11 6 14 J SD Q 12 CP 7 13 K C Q D 15 9 10 * Both outputs will be HIGH while both SD and CD are LOW. H. h = HIGH Voltage Level L. FAST AND LS TTL DATA 5-101 . h (q) = Lower case letters indicate the state of the referenced input (or output) l. I = LOW Voltage Level X = Don’t Care l. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. The clocking operation is independent of rise and fall times of the clock waveform.

0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Clock Clear Set to Output Clock. K. AC CHARACTERISTICS (TA = 25°C.8 – 100 8.25 0.5 0.65 35 3.SN54/74LS109A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.7 0.4 Min 2.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.5 V V V V Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. Clear J.2 – 0. Clock Set.0 V 50 CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C. VIN = VIH MIN MAX or VIL per Truth Table IOL = 4. VCC = 5.0 Test Conditions FAST AND LS TTL DATA 5-102 . 74 54 74 Min 4.4 4.25 125 70 – 0. IOH = MAX.5 20 40 0.7 54 74 – 0.0 8.4 – 0.0 0.5 4. VCC = 5. Min 25 Typ 33 13 25 25 40 Max Unit MHz ns ns VCC = 5. Clock Set.0 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.35 0.0 mA VCC = VCC MIN. VIN = VIL or VIH per Truth Table VCC = MAX. VIN = 0. VIN = 2. K.75 – 55 0 Typ 5.5 3. Clock Set.0 25 25 Max 5.0 V) Limits Symbol tW ts th Parameter Clock High Clear. nor for more than 1 second. Clear Output Short Circuit Current (Note 1) Power Supply Current – 20 0. VIN = 7.8 – 1.0 5. Clear IIL IOS ICC Input LOW Current J.0 V mA mA mA VCC = MAX. K.5 2.0 V µA 25 2.1 0. Set Pulse Width Data Setup Time — HIGH Data Setup Time — LOW Hold time Min 25 20 20 5. Clear. IIN = – 18 mA VCC = MIN.7 V IIH mA VCC = MAX.5 5.0 mA IOL = 8.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Out ut Output HIGH Voltage 54 74 54. 74 VOL Output LOW Voltage 74 Input HIGH Current J.

Input data is transferred to the outputs on the negative-going edge of the clock pulse. and asynchronous set and clear inputs to each flip-flop. clock. h = HIGH Voltage Level L. H. h (q) = Lower case letters indicate the state of the referenced input (or output) l. When the clock goes HIGH. but the output states are unpredictable if SD and CD go HIGH simultaneously. the inputs are enabled and data will be accepted. h (q) = one set-up time prior to the HIGH to LOW clock transition. DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 620-09 16 1 Q 5(9) 6(7) Q CLEAR (CD) 15(14) J 3(11) 1(13) CLOCK (CP) SET (SD) 4(10) K 2(12) 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Toggle Load “0” (Reset) Load “1” (Set) Hold L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H q L H q Q L H H q H L q OUTPUTS SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 3 1 2 J CP K CD Q 15 VCC = PIN 16 GND = PIN 8 SD Q 5 13 11 J CP 7 10 SD Q 9 * Both outputs will be HIGH while both SD and CD are LOW. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. 6 12 K C Q D 14 FAST AND LS TTL DATA 5-103 .SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J. I = LOW Voltage Level X = Don’t Care l. K.

Set Pulse Width Setup Time Hold Time Min 20 25 20 0 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.5 4.0 V IIL IOS ICC Input LOW Current mA mA mA VCC = MAX.7 V mA VCC = MAX. K Set.7 0.5 3.0 0.3 0.0 mA IOL = 8.1 0.4 Min 2. 74 54 74 Min 4. VCC = 5.8 – 100 6.0 8.7 54 74 – 0. Set to Output Min 30 Typ 45 15 15 20 20 Max Unit MHz ns ns VCC = 5. IOH = MAX.5 2. K Clear. VIN = 0.25 0.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Out ut Output HIGH Voltage 54 74 54. Clk – 20 0. AC CHARACTERISTICS (TA = 25°C.4 4. VCC = 5. Clear Clock J.0 5.25 125 70 – 0. VIN = 7. Clock g y Clear.65 35 3. VIN = VIL or VIH per Truth Table VCC = MAX. IIN = – 18 mA VCC = MIN.SN54/74LS112A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. K Set.0 V) Limits Symbol tW tW ts th Parameter Clock Pulse Width High Clear.0 Test Conditions FAST AND LS TTL DATA 5-104 . Set.75 – 55 0 Typ 5.0 mA VCC = VCC MIN.5 20 60 80 0. VIN = VIH MIN MAX or VIL per Truth Table IOL = 4.4 – 0.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay. VIN = 2.4 – 0.0 25 25 Max 5.35 0.4 V VCC = MAX VCC = MAX Short Circuit Current (Note 1) Power Supply Current Note 1: Not more than one output should be shorted at a time. 74 VOL Output LOW Voltage 74 J.5 V V V V Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 V 50 CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C.5 0. nor for more than 1 second.5 5. Clear Clock IIH Input HIGH Current J.8 – 1.0 V µA 25 2.

the inputs are enabled and data will be accepted. 6 12 K VCC = PIN 14 GND = PIN 7 FAST AND LS TTL DATA 5-105 . These monolithic dual flip-flops are designed so that when the clock goes HIGH. and clock inputs. set.SN54/74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS113A offers individual J. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum setup times are observed. DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 1 Q 5(9) 6(8) Q N SUFFIX PLASTIC CASE 646-06 1 J 3(11) 1(13) CLOCK (CP) SET (SD) 4(10) K 2(12) 14 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE SD Set Toggle Load “0” (Reset) Load “1” (Set) Hold L H H H H J X h l h l K X h h l l Q H q L H q Q L q H L q 3 1 2 J CP K Q OUTPUTS SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 SD Q 5 13 11 J CP Q 8 10 SD Q 9 H. K. h = HIGH Voltage Level L. I = LOW Voltage Level X = Don’t Care l. h (q) = Lower case letters indicate the state of the referenced input (or output) l. Input data is transferred to the outputs on the negative-going edge of the clock pulse. h (q) = one set-up time prior to the HIGH to LOW clock transition.

25 0. VCC = 5.5 20 60 80 0.65 3.5 V V V V Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = 2. VIN = 0.7 0.35 0.75 – 55 0 Typ 5. 74 VOL Output LOW Voltage 74 J.7 54 74 – 0.0 5. VCC = 5. 74 54 74 Min 4. IOH = MAX.0 25 25 Max 5. Clock g y Set to Output Min 30 Typ 45 15 15 20 20 Max Unit MHz ns ns VCC = 5. K Set.0 V 50 F CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C.0 8.4 – 0.0 V µA 2. Clock – 20 0.8 – 100 6.4 V VCC = MAX VCC = MAX Short Circuit Current (Note 1) Power Supply Current Note 1: Not more than one output should be shorted at a time.4 4.5 0.SN54/74LS113A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. K Set Clock IIH Input HIGH Current J.0 mA IOL = 8.8 – 1.0 V) Limits Symbol tW tW ts th Parameter Clock Pulse Width High Set Pulse Width Setup Time Hold Time Min 20 25 20 0 Typ Max Unit ns ns ns ns VCC = 5 0 V 5. VIN = VIH MIN MAX or VIL per Truth Table IOL = 4.4 – 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 mA VCC = VCC MIN.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay. nor for more than 1 second.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Out ut 54 74 54.1 0. K Set Clock J.5 25 2.0 Test Conditions FAST AND LS TTL DATA 5-106 .7 V mA VCC = MAX.5 5.3 0.5 4.0 0.0 V IIL IOS ICC Input LOW Current mA mA mA VCC = MAX. AC CHARACTERISTICS (TA = 25°C. IIN = – 18 mA VCC = MIN.4 Min 2.5 35 3. VIN = 7.25 125 70 – 0.

H. h (q) = one set-up time prior to the HIGH to LOW clock transition. and set inputs. Input data is transferred to the outputs on the negative-going edge of the clock pulse. K. DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 Q 5(9) 6(8) Q 1 CLEAR (CD) TO OTHER FLIP-FLOP 4(10) SET (SD) K 2(12) 14 1 N SUFFIX PLASTIC CASE 646-06 J 3(11) 13 CLOCK (CP) 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Toggle Load “0” (Reset) Load “1” (Set) Hold L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H q L H q Q L H H q H L q 3 13 2 1 VCC = PIN 14 GND = PIN 7 OUTPUTS SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 J CP K CD Q SD Q 5 11 J CP 6 12 K C Q D 8 10 SD Q 9 * Both outputs will be HIGH while both SD and CD are LOW. I = LOW Voltage Level X = Don’t Care l. h (q) = Lower case letters indicate the state of the referenced input (or output) l. but the output states are unpredictable if SD and CD go HIGH simultaneously. FAST AND LS TTL DATA 5-107 .SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS114A offers common clock and common clear inputs and individual J. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed. the inputs are enabled and data will be accepted. h = HIGH Voltage Level L. These monolithic dual flip-flops are designed so that when the clock goes HIGH.

5 25 2.3 0.6 – 100 6.0 0. 74 VOL Output LOW Voltage 74 J.75 – 55 0 Typ 5. g y Clear.5 Typ Max Unit V V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.25 0.8 – 1.0 V 2.4 4. VIN = 0.5 35 3.7 0. VIN = VIL or VIH per Truth Table µA VCC = MAX.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Out ut 54 74 54. VCC = 5.0 Test Conditions FAST AND LS TTL DATA 5-108 .0 mA VCC = VCC MIN.4 – 0. Set Pulse Width Setup Time Hold Time Min 20 25 20 0 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.0 V) Limits Symbol tW tW ts th Parameter Clock Pulse Width High Clear.5 5.0 mA IOL = 8.25 125 70 – 0. K Set Clear. K Set Clear Clock J. Clock.1 0.65 3.5 0. AC CHARACTERISTICS (TA = 25°C. VIN = 7.0 V 50 F CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C.0 5.0 25 25 Max 5. nor for more than 1 second.SN54/74LS114A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. VCC = 5.4 Min 2. VIN = VIH MIN MAX or VIL per Truth Table IOL = 4.7 V mA VCC = MAX.4 V VCC = MAX VCC = MAX Output Short Circuit Current (Note 1) Power Supply Current Note 1: Not more than one output should be shorted at a time.5 4. Set to Output Min 30 Typ 45 15 15 20 20 Max Unit MHz ns ns VCC = 5. 74 54 74 Min 4.5 20 60 120 160 0.8 – 0.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay.0 V IIL IOS ICC Input LOW Current mA mA mA VCC = MAX.8 – 1.0 8. IIN = – 18 mA VCC = MIN. VIN = 2.6 0. Clock – 20 0.7 54 74 – 0. K Set Clear Clock IIH Input HIGH Current J. IOH = MAX.35 0.

4. connect Rint to VCC. up to 100% Duty Cycle Internal Timing Resistors on LS122 16 1 J SUFFIX CERAMIC CASE 620-09 SN54 / 74LS123 (TOP VIEW) (SEE NOTES 1 THRU 4) 1 Rext/ 1 VCC Cext Cext 16 15 14 1Q 13 2Q 12 2 CLR 11 CLR Q Q 4 1Q 5 2Q 6 2 Cext 8 7 2 GND Rext/ Cext 14 1 16 1 2B 10 2A 9 16 1 N SUFFIX PLASTIC CASE 648-08 Q CLR Q 1 1A 2 1B 3 1 CLR D SUFFIX SOIC CASE 751B-03 J SUFFIX CERAMIC CASE 632-08 SN54 / 74LS122 (TOP VIEW) (SEE NOTES 1 THRU 4) VCC 14 Rext/ Cext 13 NC 12 Cext 11 NC 10 Rint 9 Rint Q CLR Q 1 A1 2 A2 3 B1 4 B2 5 CLR 6 Q 7 GND Q 8 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 NC — NO INTERNAL CONNECTION. The basic pulse width is programmed by selection of external resistance and capacitance values. To obtain variable pulse widths. RETRIGGERABLE MONOSTABLE MULTIVIBRATORS LOW POWER SCHOTTKY • • • • • Overriding Clear Terminates Output Pulse Compensated for VCC and Temperature Variations DC Triggered from Active-High or Active-Low Gated Logic Inputs Retriggerable for Very Long Output Pulses. 2. connect an external variable resistance between Rint/Cext and VCC. For improved pulse width accuracy connect an external resistor between Rext/Cext and VCC with Rint open-circuited.SN54/74LS122 SN54/74LS123 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS These dc triggered multivibrators feature pulse width control by three methods. the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC FAST AND LS TTL DATA 5-109 . 3. or be reduced by use of the overriding clear. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. To use the internal timing resistor of the LS122. NOTES: 1. Once triggered. An external timing capacitor may be connected between Cext and Rext/Cext (positive).

SN54/74LS122 • SN54/74LS123 LS122 FUNCTIONAL TABLE INPUTS CLEAR L X X X H H H H H H H ↑ ↑ A1 X H X X L L X X H ↓ ↓ L X A2 X H X X X X L L ↓ ↓ H X L B1 X X L X ↑ H ↑ H H H H H H B2 X X X L H ↑ H ↑ H H H H H OUTPUTS Q L L L L Q H H H H CLEAR L X X H H ↑ LS123 FUNCTIONAL TABLE INPUTS A X H X L ↓ L B X X L ↑ H H OUTPUTS Q L L L Q H H H TYPICAL APPLICATION DATA The output pulse tW is a function of the external components. Rext remote should be kept as close to the monostable as possible. It should be noted that the Cext pin is internally connected to ground on the LS122 and LS123. Remember.45 Rext (kΩ) Cext + 11. the change in K with respect to Rext is negligible.45 If Cext is on pF and Rext is in kΩ then tW is in nanoseconds. If VCC is tied to VRC. and 12 show how this can be done. Care should be taken to keep Rext and Cext as close to the monostable as possible with a minimum amount of inductance between the Rext/Cext junction and the Rext/Cext pin. the changes in Rext and Cext with temperature are not calculated and included in the graph. The switching diode is not needed for electrolytic capacitance application and should not be used on the LS122 and LS123. 11.6 Rext In order to trim the output pulse width.05 Cext (pF). but not on the LS221. For values of Cext ≥ 1000 pF. If Cext ≤ 1000 pF the graph shown on Figure 8 can be used to determine the output pulse width. it is necessary to include a variable resistor between VCC and the Rext/Cext pin or between VCC and the Rext pin of the LS122. Figure 7 shows how K will vary with VCC and temperature. Variations on VCC or VRC can cause the value of K to change. must not occur before Cext is discharged or the retrigger pulse will not have any effect. FAST AND LS TTL DATA 5-110 . the output pulse at VCC = 5. Figure 9 shows how K will change for Cext ≤ 1000 pF if VCC and VRC are connected to the same power supply. and 3) is given by tW = K Rext Cext where K is nominally 0. Cext and Rext or Cext and Rint on the LS122. if Cext is hard-wired externally to ground. The discharge time of Cext in nanoseconds is guaranteed to be less than 0. Figures 5 and 6 show the behavior of the circuit shown in Figures 1 and 2 if separate power supplies are used for VCC and VRC.05 Cext (pF) + 0. As long as Cext ≥ 1000 pF and 5K ≤ Rext ≤ 260K (SN74LS122 / 123) or 5K ≤ Rext ≤ 160 K (SN54LS122 / 123). refer to Figure 4. Good groundplane and adequate bypassing should be designed into the system for optimum performance to insure that no false triggering occurs. it is suggested that Cext be kept ≥ 1000 pF. as shown in Figure 3. For the smallest possible deviation in output pulse widths from various devices. Retriggering of the part. To find the value of K for Cext ≥ 1000 pF. substitution of a LS221 onto a LS123 socket will cause the LS221 to become non-functional. Figure 10. Therefore. 2. as can the temperature of the LS123. The Cext terminal of the LS122 and LS123 is an internal connection to ground.22 Cext (pF) and is typically 0.0 V and VRC = 5. The pulse width tW in nanoseconds is approximated by tW = 6 + 0. LS122. however for the best system performance Cext should be hard-wired to ground.0 V (see Figures 1.

74 54. 74 5.25 125 70 – 0.75 – 55 0 Typ 5.4 4.SN54/74LS122 • SN54/74LS123 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Rext Cext Rext / Cext Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low External Timing Resistance External Capacitance Wiring Capacitance at Rext / Cext Terminal Parameter 54 74 54 74 54.0 8.5 5.0 25 25 Max 5.5 4.0 5. 74 54 74 54 74 54.0 Min 4.0 5.0 180 260 No Restriction 50 pF Unit V °C mA mA kΩ WAVEFORMS RETRIGGER PULSE B INPUT (See Application Data) Q OUTPUT tW OUTPUT WITHOUT RETRIGGER EXTENDING PULSE WIDTH B INPUT CLEAR INPUT CLEAR PULSE OUTPUT WITHOUT CLEAR PULSE Q OUTPUT OVERRIDING THE OUTPUT PULSE FAST AND LS TTL DATA 5-111 .

A to Q g y Propagation Delay. IOH = MAX.0 mA VCC = VCC MIN.5 Max 33 ns 45 44 ns 56 45 ns 27 200 5.0 Min Typ 23 32 23 34 28 20 116 4.0 V VCC = MAX. A to Q Propagation Delay.5 V V Min 2.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tW min tWQ Parameter Propagation Delay.0 0.0 V) Limits Symbol tW Pulse Width Parameter Min 40 Typ Max Unit ns Test Conditions FAST AND LS TTL DATA 5-112 . VIN = 7.0 kΩ RL = 2. nor for more than 1 second.65 3. VIN = VIL or VIH per Truth Table VCC = MAX. VIN = 0.35 0.5 0. VCC = 5. AC CHARACTERISTICS (TA = 25°C. CL = 15 pF.8 – 1. VIN = 2. B to Q g y Propagation Delay.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. B to Q Propagation Delay. Rext = 10 kΩ.4 V V 2.1 Input LOW Current Short Circuit Current (Note 1) LS122 ICC Power Supply Current LS123 20 – 20 – 0.SN54/74LS122 • SN54/74LS123 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. Clear to Q A or B to Q A to B to Q 4.0 ns µs Cext = 1000 pF.7 3. RL = 2. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.5 0.25 0.4 V VCC = MAX Note 1: Not more than one output should be shorted at a time.0 kΩ Rext = 5. IIN = – 18 mA VCC = MIN.4 –100 11 mA VCC = MAX 0. Clear to Q g y Propagation Delay.0 kΩ Cext = 0 CL = 15 pF Unit Test Conditions AC SETUP REQUIREMENTS (TA = 25°C.0 mA IOL = 8.5 20 IIH IIL IOS V µA mA mA mA 2.5 – 0. VCC = 5. VIN = VIH or VIL per Truth Table IOL = 4.7 V VCC = MAX.

45 0.1 µF Pout 0.4 K 0.35 0.1 0.5 0. Cext ( µF) 1 0.1 µF Pin Figure 1 Figure 2 Pin Pout tW RETRIGGER Figure 3 10 5K ≤ Rext ≤ 260K EXTERNAL CAPACITANCE.001 0.01 0.SN54/74LS122 • SN54/74LS123 VCC VRC Rext Cext Cext CLR B2 B1 A2 A1 51 Ω Rext/ Cext LS122 Q GND VCC Q Pout VCC VCC VRC Rext VCC Cext Cext Rext/ VCC Cext Q CLR 1/2 LS123 B Pin 51 Ω A Q GND 0.3 0.55 Figure 4 FAST AND LS TTL DATA 5-113 .

55 Cext = 1000 pF – 55°C 25°C K 0.4 125°C 0.45 70°C K 0. K versus VCC VRC Figure 6.5 – 55°C 0. K versus VCC and VRC 100000 10000 t W .5 5 5.35 4.5 0.55 VRC = 5 V Cext = 1000 pF 0.35 4.5 0. K versus VRC VCC = VRC Figure 7.35 4.4 125°C 0.5 – 55°C 0°C 25°C 70°C 0.5 VCC Figure 5.5 5 5.5 0.55 VCC = 5 V Cext = 1000 pF 0.SN54/74LS122 • SN54/74LS123 0.5 5 5.4 0°C 0. OUTPUT PULSE WIDTH (ns) Rext = 260 kΩ Rext = 160 kΩ 1000 100 Rext = 80 kΩ Rext = 40 kΩ Rext = 20 kΩ Rext = 10 kΩ Rext = 5 kΩ 10 1 10 100 1000 Cext.45 K 0. EXTERNAL TIMING CAPACITANCE (pF) Figure 8 FAST AND LS TTL DATA 5-114 .45 0°C 25°C 70°C 125°C 0.

5 4.65 Cext = 200 pF – 55°C 0.75 5 VCC VOLTS 5. LS123 Remote Trimming Circuit FAST AND LS TTL DATA 5-115 .55 125°C 0.6 0°C 25°C 70°C K 0.25 5.5 Figure 9 VCC Rext REMOTE PIN 7 OR 15 Cext PIN 6 OR 14 Rext Figure 10.5 4.SN54/74LS122 • SN54/74LS123 0.

LS122 Remote Trimming Circuit with Rint FAST AND LS TTL DATA 5-116 . LS122 Remote Trimming Circuit Without Rext VCC Rext REMOTE PIN 9 PIN 13 PIN 11 Figure 12.SN54/74LS122 • SN54/74LS123 VCC PIN 9 OPEN Rext PIN 13 Cext PIN 11 Rext REMOTE Figure 11.

5 4.0 5.0 25 25 Max 5.0 – 2.6 12 24 Unit V °C mA mA FAST AND LS TTL DATA 5-117 .25 125 70 – 1.5 5.QUAD 3-STATE BUFFERS VCC 14 E 13 D 12 O 11 E 10 D 9 O 8 SN54/74LS125A SN54/74LS126A QUAD 3-STATE BUFFERS LOW POWER SCHOTTKY 1 E 2 D 3 O 4 E 5 D 6 O 7 GND J SUFFIX CERAMIC CASE 632-08 LS125A VCC 14 E 13 D 12 O 11 E 10 D 9 O 8 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 1 E 2 D 3 O 4 E 5 D 6 O 7 GND 14 1 LS126A D SUFFIX SOIC CASE 751A-02 TRUTH TABLES LS125A INPUTS E L L H D L H X OUTPUT L H (Z) INPUTS E H H L D L H X OUTPUT L H (Z) LS126A ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care (Z) = High Impedance (off) GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54 74 54 74 Min 4.75 – 55 0 Typ 5.

nor for more than 1 second. VIN = 7.4 –225 20 mA VCC = MAX 0.0 0. IOH = MAX.65 0. VCC = 5.35 0. Figures 4 5 4. VOUT = 0.SN54/74LS125A • SN54/74LS126A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. VIN = 2.0 7.1 Input LOW Current Short Circuit Current (Note 1) LS125A Power Supply Current LS126A 22 – 40 – 0. IIN = – 18 mA VCC = MIN.0 9. VE = 4.4 V VCC = MAX. VCC = 5.5 V V Min 2.8 – 1.7 V VCC = MAX.5 20 – 20 20 V µA µA µA mA mA mA 2. VIN = 0. 5 3 Figures 4 5 4.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.4 V V 2.25 0.0 F RL = 667 Ω Figures 3 5 3.0 V CL = 5 0 pF 5.0 V VCC = MAX.4 – 0.4 0. VE = 0 V Note 1: Not more than one output should be shorted at a time. VIN = VIL or VIH per Truth Table VCC = MAX.0 12 16 15 21 Max 15 15 ns 18 18 20 ns 25 25 ns 35 20 ns 25 20 ns 25 FIgures 3.4 V VCC = MAX. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPLH tPHL tPHL tPZH Output Enable Time to HIGH Level Output Enable Time to LOW Level Output Disable Time from HIGH Level Output Disable Time from LOW Level Propagation Delay.5 V VIN = 0 V. VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN. 74 VOL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.0 8.4 V VCC = MAX VIN = 0 V.0 V CL = 45 pF F RL = 667 Ω Figure 2 Unit Test Conditions tPZL tPHZ tPLZ FAST AND LS TTL DATA 5-118 . g y Data to Output Parameter LS125A LS126A LS125A LS126A LS125A LS126A LS125A LS126A LS125A LS126A LS125A LS126A Min Typ 9. VOUT = 2.

3 V tPLZ ≈ 1.3 V VOUT Figure 3 Figure 4 VCC RL SW1 TO OUTPUT UNDER TEST 5 kΩ CL SW2 Figure 5 SWITCH POSITIONS SYMBOL tPZH tPZL tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed FAST AND LS TTL DATA 5-119 .3 V 1.3 V VE 1.3 V VOL 0.3 V tPLH 1.5 V 1.3 V 0.3 V tPHZ > VOH ≈ 1.3 V Figure 1 Figure 2 VE 1.3 V tPLH 1.3 V tPHL 1.3 V VE tPZH 1.3 V VE tPZL VOUT 1.5 V 1.3 V 1.3 V VOUT VOUT 1.3 V tPHL 1.SN54/74LS125A • SN54/74LS126A VIN VIN 1.

Additionally. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions. the gate will respond to the transitions of the other input as shown in Figure 1. and provide different input threshold voltages for positive and negative-going transitions. they have greater noise margin than conventional NAND Gates.SN54/74LS132 QUAD 2-INPUT SCHMITT TRIGGER NAND GATE The SN54 / 74LS132 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels.95 1. They are capable of transforming slowly changing input signals into sharply defined.4 0. This hysteresis between the positive-going and negative-going input thresholds (typically 800 mV) is determined internally by resistor ratios and is essentially insensitive to temperature and supply voltage variations. jitterfree output signals. VIN versus VOUT Transfer Function FAST AND LS TTL DATA 5-120 .2 VIN.8 2 Figure 1. QUAD 2-INPUT SCHMITT TRIGGER NAND GATE LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 14 1 LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 13 12 11 10 9 8 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 2 3 4 5 6 7 GND 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC 5 V O . Each circuit contains a 2-input Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output. As long as one input remains at a more positive voltage than VT+ (MAX). INPUT VOLTAGE (VOLTS) 1. OUTPUT VOLTAGE (VOLTS) 4 VCC = 5 V TA = 25°C 3 2 1 0 0 0.

VIN = VT– VCC = MAX.0 mA.65 3.14 – 0. nor for more than 1 second. IIN = – 18 mA VCC = MIN.0 25 25 Max 5.3 V 1.5 0.0 V VCC = MIN.0 V.0 5.6 0. VIN = 0 V VCC = MAX.5 Typ Max 2.2 – 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay. IOL = 4.5 V Note 1: Not more than one output should be shorted at a time.75 – 55 0 Typ 5.25 0.3 V Figure 2.5 V mA mA µA mA mA mA mA mA 2. VIN = VT+ VCC = 5.4 4.0 V CL = 15 pF VOUT 1.5 5.25 125 70 – 0.4 V – 1. VIN = 0. Input to Output Turn-On Delay.1 Input LOW Current Output Short Circuit Current (Note 1) Power Supply Current Total. 74 VOL IT+ IT– IIH IIL IOS ICC Output LOW Voltage 74 Input Current at Positive-Going Threshold Input Current at Negative-Going Threshold Input HIGH Current 0.0 1. VCC = MIN.8 V Min Typ Max 22 22 Unit ns ns Test Conditions VCC = 5.0 V VCC = MIN.1 Unit V V V V Test Conditions VCC = 5.0 8. Output LOW – 20 5. Output HIGH Total.0 V VCC = 5.7 V VCC = MAX.4 V VCC = MAX.0 V VCC = MAX.4 –100 11 14 0.35 – 0.5 Min 1.0 V VCC = 5. VIN = 2.4 0.0 V.0 V VCC = 5. Input to Output 3V VIN 0V tPHL tPLH 1.SN54/74LS132 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. VIN = 2.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VT+ VT– VT + – VT– VIK VOH Parameter Positive-Going Threshold Voltage Negative-Going Threshold Voltage Hysteresis Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. VIN = 7.8 – 0.6 V 0. VOUT = 0 V VCC = MAX. IOH = – 400 µA VIN = VIL MIN µA.4 V 2. AC Waveforms FAST AND LS TTL DATA 5-121 .0 mA.5 4.4 0.18 20 0. VIN = 4. IOL = 8. VIN = 2.7 3.9 8. 74 54 74 Min 4.

5 Figure 3.5 1.25 VCC.7 – 55° VT– ∆ VT 0° 25° 75° TA. Threshold Voltage and Hysteresis versus Power Supply Voltage 1. POWER SUPPLY VOLTAGE (VOLTS) 5.7 1. THRESHOLD VOLTAGE (VOLTS) ∆ V T. HYSTERESIS (VOLTS) 1.75 5 5.5 4. THRESHOLD VOLTAGE (VOLTS) ∆ V T. HYSTERESIS (VOLTS) TA = 25°C VT+ 1.9 V T .1 0. Threshold Voltage and Hysteresis versus Temperature FAST AND LS TTL DATA 5-122 .4 0 4.6 1.3 1.8 ∆ VT 0.SN54/74LS132 2 V T .2 VT– 0.9 0. AMBIENT TEMPERATURE (°C) VT+ 125° Figure 4.

0 8.75 – 55 0 Typ 5.5 4.5 5.SN54/74LS133 13-INPUT NAND GATE 13-INPUT NAND GATE VCC 16 15 14 13 12 11 10 9 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 8 GND J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. 74 54 74 Min 4.0 25 25 Max 5.25 125 70 – 0.0 5.4 4.0 Unit V °C mA mA FAST AND LS TTL DATA 5-123 .

5 35 0.5 25 – 0. nor for more than 1 second. VIN = 7.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.25 0.0 V VCC = MAX.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.8 – 1.0 mA VCC = VCC MIN.4 –100 0.4 V V 2.5 1.35 0. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. VIN = 2.5 20 IIH IIL IOS ICC V µA mA mA mA 2.0 0. VIN = 0. VIN = VIL or VIH per Truth Table VCC = MAX.7 3.5 0. Output HIGH Total. VIN = VIH MIN MAX or VIL per Truth Table IOL = 4. Output LOW – 20 – 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 mA IOL = 8. IIN = – 18 mA VCC = MIN.65 3. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.1 0.5 V V Min 2. Input to Output Turn-On Delay. Input to Output Min Typ 10 40 Max 15 59 Unit ns ns Test Conditions VCC = 5. IOH = MAX.7 V VCC = MAX.0 V CL = 15 pF FAST AND LS TTL DATA 5-124 .SN54/74LS133 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.

5 8.SN74LS136 QUAD 2-INPUT EXCLUSIVE OR GATE QUAD 2-INPUT EXCLUSIVE OR GATE LOW POWER SCHOTTKY VCC 14 13 12 * 11 10 9 * J SUFFIX CERAMIC CASE 632-08 14 8 * 1 2 3 4 5 6 * 7 GND 1 * OPEN COLLECTOR OUTPUTS N SUFFIX PLASTIC CASE 646-06 1 TRUTH TABLE IN A L L H H B L H L H OUT Z L H H L 14 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter Min 4.75 0 Typ 5.0 Unit V °C V mA FAST AND LS TTL DATA 5-125 .25 70 5.0 25 Max 5.

IIN = – 18 mA VCC = MIN.8 10 0.0 0.0 V CL = 15 pF.5 100 0.0 mA VCC = VCC MIN.8 – 1.35 Input HIGH Current 0.4 Typ Max Unit V V V µA V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.0 V VCC = MAX. VOH = MAX IOL = 4. RL = 2. VIN = 0.25 Output LOW Voltage 0.5 40 IIH IIL ICC V µA mA mA mA – 0. VIN = VIL or VIH per Truth Table VCC = MAX.7 V VCC = MAX.65 Min 2. Other Input LOW Propagation Delay.0 kΩ Test Conditions FAST AND LS TTL DATA 5-126 . VIN = 2. Other Input HIGH Min Typ 18 18 18 18 Max 30 30 30 30 Unit ns ns VCC = 5.0 mA IOL = 8. VIN = 7.4 V VCC = MAX AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay.2 Input LOW Current Power Supply Current – 0.SN74LS136 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Current 0.

0 8.25 125 70 – 0.0 5. 74 54 74 Min 4.0 25 25 Max 5.4 4.5 5.75 – 55 0 Typ 5.0 Unit V °C mA mA FAST AND LS TTL DATA 5-127 .SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/ DEMULTIPLEXERS WITH ADDRESS LATCHES DATA OUTPUTS VCC 16 Y0 15 Y0 A B C GL G2 G1 Y1 14 Y1 Y2 13 Y2 Y3 12 Y3 Y4 11 Y4 Y5 10 Y5 Y6 Y7 16 1 LOW POWER SCHOTTKY Y6 9 J SUFFIX CERAMIC CASE 620-09 1 A 2 B SELECT 3 C 4 GL 5 G2 ENABLE 6 G1 8 7 Y7 GND OUTPUT 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 4.

L = low level.SN54/74LS137 FUNCTION TABLE INPUTS OUTPUTS ENABLE GL X X L L L L L L L L H G1 X L H H H H H H H H H G2 H X L L L L L L L L L C X X L L L L H H H H X SELECT B X X L L H H L L H H X A X X L H L H L H L H X Y0 H H L H H H H H H H Y1 H H H L H H H H H H Y2 H H H H L H H H H H Y3 H H H H H L H H H H Y4 H H H H H H L H H H Y5 H H H H H H H L H H Y6 H H H H H H H H L H Y7 H H H H H H H H H L Output corresponding to stored address. X = irrelevant A (1) (15) (14) Y0 Y1 (13) SELECT INPUTS B (2) (12) Y2 Y3 DATA OUTPUTS (11) C (3) (10) Y4 Y5 (9) GL ENABLE INPUTS (4) (7) G2 G1 (5) (6) Y6 Y7 FAST AND LS TTL DATA 5-128 . H H = high level. L. all others.

0 V.7 V VCC = MAX.7 0.5 20 0. B. AC CHARACTERISTICS (VCC = 5. C to Y Propagation Delay Time.0 mA VCC = VCC MIN.35 0. Enable GL to Y Levels of Delay 2 4 3 3 2 2 3 3 3 4 Limits Min Typ 11 25 16 19 13 16 14 18 18 25 Max 17 38 24 29 21 27 21 27 27 38 Unit ns ns ns ns ns VCC = 5. Enable G2 to Y Propagation Delay Time. VIN = 2. TA = 25°C) Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Time. Enable G1 to Y Propagation Delay Time. A.1 – 0.8 – 1.5 2. B. A.0 V CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C.4 Min 2.0 V VCC = MAX. VIN = VIH MIN MAX or VIL per Truth Table IOL = 4. C Hold Time.7 54 74 – 0. VIN = VIL or VIH per Truth Table IIH IIL IOS ICC VCC = MAX. C to Y Propagation Delay Time.0 V) Limits Symbol tW ts th Parameter Pulse Width — Enable at GL Setup Time. B. VCC = 5. IIN = – 18 mA VCC = MIN. A.5 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.65 35 3.0 0.5 V V V V Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = 0.0 mA IOL = 8. IOH = MAX. B.SN54/74LS137 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Out ut Output HIGH Voltage 54 74 54. nor for more than 1 second. C Min 15 10 10 Typ Max Unit ns ns ns VCC = 5. 74 VOL Output LOW Voltage 74 Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 0.5 3. A. VIN = 7.25 0.0 V Test Conditions FAST AND LS TTL DATA 5-129 .4 –100 18 V µA mA mA mA mA 25 2.

ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC NOTES: a) 1 TTL Unit Load (U.1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. SN54/74LS138 1-OF-8 DECODER / DEMULTIPLEXER LOW POWER SCHOTTKY • • • • • Demultiplexing Capability Multiple Input Enable for Easy Expansion Typical Power Dissipation of 32 mW Active Low Mutually Exclusive Outputs Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 O0 15 O1 14 O2 13 O3 12 O4 11 O5 10 O6 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.5 U.5 U. for Commercial (74) Temperature Ranges. 0.L.5) U.5 U. The LS138 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.) = 40 µA HIGH/1.L.25 U. 16 1 PIN NAMES A0 – A2 E1.L. 16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 1 A0 2 A1 3 A2 4 E1 5 E2 6 E3 7 O7 8 GND LOADING (Note a) HIGH LOW 0.L.5 U.L.25 U.25 U. for Military (54) and 5 U.L. b) The Output LOW drive factor is 2. 0.L. This device is ideally suited for high speed bipolar memory chip select address decoding.6 mA LOW.L. LOGIC DIAGRAM A2 3 2 A1 1 A0 4 E1 E2 E3 5 6 LOGIC SYMBOL VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 1 2 3 456 12 3 A0 A1 A2 E O0 O1 O2 O3 O4 O5 O6 O7 15 14 13 12 11 10 9 7 VCC = PIN 16 GND = PIN 8 7 9 10 11 12 13 14 15 O7 O6 O5 O4 O3 O2 O1 O0 FAST AND LS TTL DATA 5-130 .L. 0.L.L. 0. E2 E3 O0 – O7 Address Inputs Enable (Active LOW) Inputs Enable (Active HIGH) Input Active LOW Outputs (Note b) D SUFFIX SOIC CASE 751B-03 0. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. 10 U. 5 (2.

) The LS138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. E2) and one active HIGH (E3).SN54/74LS138 FUNCTIONAL DESCRIPTION The LS138 is a high speed 1-of-8 Decoder/Demultiplexer fabricated with the low power Schottky barrier diode process. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four LS138s and one inverter. two active LOW (E1. A1. The Enable inputs which are not used must be permanently tied to their appropriate active HIGH or active LOW state. All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. (See Figure a. The decoder accepts three binary weighted inputs (A0. A2) and when enabled provides eight mutually exclusive active LOW Outputs (O0 – O7). TRUTH TABLE INPUTS E1 H X X L L L L L L L L E2 X H X L L L L L L L L E3 X X L H H H H H H H H A0 X X X L H L H L H L H A1 X X X L L H H L L H H A2 X X X L L L L H H H H O0 H H H L H H H H H H H O1 H H H H L H H H H H H O2 H H H H H L H H H H H OUTPUTS O3 H H H H H H L H H H H O4 H H H H H H H L H H H O5 H H H H H H H H L H H O6 H H H H H H H H H L H O7 H H H H H H H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care A0 A1 A2 LS04 A3 A4 H 123 A0 A1 A2 LS138 O0 O1 O2 O3 O4 O5 O6 O7 E A0 A1 A2 LS138 O0 O1 O2 O3 O4 O5 O6 O7 123 E A0 A1 A2 LS138 O0 O1 O2 O3 O4 O5 O6 O7 123 E A0 A1 A2 LS138 O0 O1 O2 O3 O4 O5 O6 O7 123 E O0 O31 Figure a FAST AND LS TTL DATA 5-131 . The LS138 features three Enable inputs.

0 0.3 V tPHL VOUT 1.3 V VOUT VIN 1.4 –100 10 V µA mA mA mA mA 2.0 mA IOL = 8.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-132 . VIN = VIL or VIH per Truth Table IIH IIL IOS ICC VCC = MAX.35 0.65 3.3 V tPLH 1.7 V VCC = MAX.25 0.0 5. VIN = 0.3 V tPLH 1.5 5.4 Min 2.7 0.5 4. VIN = 2. AC CHARACTERISTICS (TA = 25°C) Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Address to Output Propagation Delay Address to Output Propagation Delay E1 or E2 Enable to Output Propagation Delay E3 Enable to Output Levels of Delay 2 2 3 3 2 2 3 3 Limits Min Typ 13 27 18 26 12 21 17 25 Max 20 41 27 39 18 32 26 38 Unit ns ns ns ns Test Conditions VCC = 5.0 25 25 Max 5.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Out ut 54 74 54.4 4.5 0. 74 54 74 Min 4.3 V 1.5 25 2.5 V V V V Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. IIN = – 18 mA VCC = MIN.75 – 55 0 Typ 5.0 V VCC = MAX.5 35 3.0 V CL = 15 pF AC WAVEFORMS VIN 1. nor for more than 1 second. VIN = VIH MIN MAX or VIL per Truth Table IOL = 4. IOH = MAX.5 20 0.7 54 74 – 0.25 125 70 – 0.1 – 0.3 V tPHL 1.8 – 1.0 8.SN54/74LS138 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. 74 VOL Output LOW Voltage 74 Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 0.3 V 1. VIN = 7.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.0 mA VCC = VCC MIN.

SN54/74LS139 DUAL 1-OF-4 DECODER / DEMULTIPLEXER LOW POWER SCHOTTKY • • • • • • Schottky Process for High Speed Multifunction Capability Two Completely Independent 1-of-4 Decoders Active Low Mutually Exclusive Outputs Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Eb 15 AOb 14 A1b 13 O0b 12 O1b 11 O2b 10 O3b 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. A1 E O0 – O3 Address Inputs Enable (Active LOW) Input Active LOW Outputs (Note b) 0. each accepting two inputs and providing four mutually exclusive active LOW Outputs.5 U.L.L. LOGIC DIAGRAM Ea 1 2 LOGIC SYMBOL 1 2 3 15 14 13 A0a A1a 3 15 Eb 14 A0b A1b 13 E A0 A1 E A0 A1 DECODER a O0 O1 O2 O3 DECODER b O0 O1 O2 O3 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 4 5 6 7 12 11 10 9 VCC = PIN 16 GND = PIN 8 4 5 6 7 12 11 10 9 O0a O1a O2a O3a O0b O1b O2b O3b FAST AND LS TTL DATA 5-133 . The device has two independent decoders. 0. D SUFFIX SOIC CASE 751B-03 PIN NAMES A0.L.) = 40 µA HIGH/1.25 U.L.L. for Commercial (74) Temperature Ranges.5 U. 5 (2.L. Each half of the LS139 can be used as a function generator providing all four minterms of two variables.5) U. The LS139 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. for Military (54) and 5 U. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC NOTES: a) 1 TTL Unit Load (U.L.5 U. b) The Output LOW drive factor is 2.L.DUAL 1-OF-4 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS139 is a high speed Dual 1-of-4 Decoder /Demultiplexer.L. 10 U.25 U. J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 1 Ea 2 A0a 3 A1a 4 O0a 5 O1a 6 O2a 7 8 16 1 O3a GND LOADING (Note a) HIGH LOW 0. Each decoder has an active LOW Enable input which can be used as a data input for a 4-output demultiplexer. 0.6 mA LOW.

5 4.0 5.SN54/74LS139 FUNCTIONAL DESCRIPTION The LS139 is a high speed dual 1-of-4 decoder/demultiplexer fabricated with the Schottky barrier diode process. A1) and provide four mutually exclusive active LOW outputs (O0 – O3).5 5.0 Unit V °C mA mA FAST AND LS TTL DATA 5-134 . TRUTH TABLE INPUTS E H L L L L A0 X L H L H A1 X L L H H O0 H L H H H OUTPUTS O1 H H L H H O2 H H H L H O3 H H H H L E A0 A1 E A0 A1 E A0 A1 E A0 A1 E O0 A0 A1 E O1 A0 A1 E O2 A0 A1 E O3 A0 A1 O0 O1 O2 O3 H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Figure a GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. The device has two independent decoders. Each half of the LS139 generates all four minterms of two variables. Each decoder has an active LOW Enable (E). replacing multiple gate functions as shown in Fig. a.25 125 70 – 0. each of which accept two binary weighted inputs (A0. The enable can be used as the data input for a 4-output demultiplexer application. 74 54 74 Min 4. When E is HIGH all outputs are forced HIGH.0 8.75 – 55 0 Typ 5.4 4.0 25 25 Max 5. These four minterms are useful in some applications. and thereby reducing the number of packages required in a logic network.

7 0. nor for more than 1 second.3 V tPLH 1.5 2.5 V V V V Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.5 0. VIN = 7.35 0.0 0.3 V tPHL VOUT 1. VIN = 0.4 Min 2. VIN = VIH MIN MAX or VIL per Truth Table IOL = 4.5 20 0.3 V 1.0 mA VCC = VCC MIN.3 V 1.0 mA IOL = 8. VIN = VIL or VIH per Truth Table IIH IIL IOS ICC VCC = MAX.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.0 V VCC = MAX.5 3.1 – 0.25 0.0 V CL = 15 pF Test Conditions AC WAVEFORMS VIN 1.3 V tPHL 1.8 – 1.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-135 .4 –100 11 V µA mA mA mA mA 25 2.65 35 3. IOH = MAX. AC CHARACTERISTICS (TA = 25°C) Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Address to Output Propagation Delay Address to Output Propagation Delay Enable to Output Levels of Delay 2 2 3 3 2 2 Limits Min Typ 13 22 18 25 16 21 Max 20 33 29 38 24 32 Unit ns ns ns VCC = 5.7 54 74 – 0.SN54/74LS139 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Out ut Output HIGH Voltage 54 74 54.3 V VOUT VIN 1. IIN = – 18 mA VCC = MIN. VIN = 2. 74 VOL Output LOW Voltage 74 Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 0.3 V tPLH 1.7 V VCC = MAX.

5 U.) = 40 µA HIGH/1.L. It is designed for use as indicator/relay drivers or as an open-collector logic circuit driver.L.5) U. All outputs remain off for all invalid binary input conditions. P1.5 U. This device is fully compatible with all TTL families. is designed to accept BCD inputs and provide appropriate outputs to drive 10-digit incandescent displays. P3 Q0 to Q9 BCD Inputs Outputs (Note b) LOADING (Note a) HIGH 0.L. 16 1 D SUFFIX SOIC CASE 751B-03 NOTES: a) 1 TTL Unit Load (U. • Low Power Version of 54 / 74145 • Input Clamp Diodes Limit High Speed Termination Effects 1-OF-10 DECODER / DRIVER OPEN-COLLECTOR LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 P0 15 P1 14 P2 13 P3 12 Q9 11 Q8 10 Q7 9 16 1 J SUFFIX CERAMIC CASE 620-09 16 N SUFFIX PLASTIC CASE 648-08 1 1 Q0 2 Q1 3 Q2 4 Q3 5 Q4 6 Q5 7 Q6 8 GND PIN NAMES P0. 15 (7. b) The Output LOW drive factor is 2. Each of the high breakdown output transistors will sink up to 80 mA of current. P2.25 U.6 mA LOW. Open Collector LOW 0.L. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC DIAGRAM P0 INPUTS P1 P2 P3 LOGIC SYMBOL 15 14 13 12 P0 P1 P2 P3 INPUT INVERTERS 0 0 1 1 2 2 3 3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 1 2 3 4 5 6 DECODE/DRIVER GATES Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 7 9 10 11 VCC = PIN 16 GND = PIN 8 OUTPUTS FAST AND LS TTL DATA 5-136 . for Military (54) and 15 U. for Commercial (74) Temperature Ranges.L.L. 1-of-10 Decoder/Driver. Typical power dissipation is 35 mW.SN54/74LS145 1-OF-10 DECODER/DRIVER OPEN-COLLECTOR The SN54 / 74LS145.

25 125 70 15 12 24 Unit V °C V mA FAST AND LS TTL DATA 5-137 .5 5.75 – 55 0 Typ 5.5 4.0 5.SN54/74LS145 TRUTH TABLE INPUTS P3 L L L L L L L L H H H H H H H H P2 L L L L H H H H L L L L H H H H P1 L L H H L L H H L L H H L L H H P0 L H L H L H L H L H L H L H L H Q0 L H H H H H H H H H H H H H H H Q1 H L H H H H H H H H H H H H H H Q2 H H L H H H H H H H H H H H H H Q3 H H H L H H H H H H H H H H H H OUTPUTS Q4 H H H H L H H H H H H H H H H H Q5 H H H H H L H H H H H H H H H H Q6 H H H H H H L H H H H H H H H H Q7 H H H H H H H L H H H H H H H H Q8 H H H H H H H H L H H H H H H H Q9 H H H H H H H H H L H H H H H H H = HIGH Voltage Level L = LOW Voltage Level GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54. 74 54 74 Min 4.0 25 25 Max 5.

3 V tPHL 1.3 V tPLH 1. IIN = – 18 mA VCC = MIN.1 – 0. 74 54. VIN = 0. VOH = MAX IOL = 12 mA IOL = 24 mA IOL = 80 mA VCC = VCC MIN.0 0. 74 IIH IIL ICC Input HIGH Current Input LOW Current Power Supply Current 0.35 2. VIN = GND AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPHL tPLH Propagation Delay Pn Input to Qn Output Parameter Min Typ Max 50 50 Unit ns Test Conditions VCC = 5.0 20 0.3 V tPHL 1. 74 Output LOW Voltage 74 54.7 V VCC = MAX. VIN = VIL or VIH per Truth T bl T h Table VCC = MAX.8 – 1.4 V VCC = MAX.3 54 74 – 0.SN54/74LS145 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Current 54.3 V VOUT 1.25 0.0 V CL = 45 pF AC WAVEFORMS VIN 1.7 0.3 V tPLH 1.4 13 V µA V V V µA mA mA mA Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = 2.3 V VIN 1.3 V VOUT 1.4 0.5 3. VIN = 7.5 250 0.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-138 .0 V VCC = MAX.65 Min 2.

They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. 12 and 13 (inputs 1. 11. The glitch occurs on the negative going transition of the EI input when data inputs 0 – 7 are at logical ones. The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). 2. (2) Pins 1. 6. SN54 / 74LS147 (TOP VIEW) OUTPUT VCC 16 NC 15 D 14 D 4 5 1 4 2 5 6 3 6 7 4 7 8 5 8 C 6 C B 7 B 8 GND 3 13 3 INPUTS 2 12 2 1 11 1 9 10 9 A OUTPUT A 9 SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC INPUTS OUTPUTS SN54 / 74LS148 SN54 / 74LS748 (TOP VIEW) OUTPUTS VCC 16 EO 15 EO 4 5 1 4 2 5 6 3 6 INPUTS 7 4 7 EI 5 E1 A2 6 A2 GS 14 GS 3 13 3 INPUTS 2 12 2 1 11 1 0 10 0 A0 A1 7 A1 8 GND OUTPUT A0 9 OUTPUTS FAST AND LS TTL DATA 5-139 . 7) have a fan-in of 3 on the LS748 versus a fan-in of 2 on the LS148. The only ac difference is that tPHL from EI to EO is changed from 40 to 45 ns. 2. 3. Both devices have data inputs and outputs which are active at the low logic level. By providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allowed without needing external circuitry. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. 4. The SN54 / 74LS748 is a proprietary Motorola part incorporating a built-in deglitcher network which minimizes glitches on the GS output.10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54 / 74LS148 are Priority Encoders. 5. The only dc parameter differences between the LS148 and the LS748 are that (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 on the LS148. 3. 4. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level.

X = Irrelevant FUNCTIONAL BLOCK DIAGRAMS 1 (11) 0 (12) (9) (13) 2 (1) 3 (2) (7) B 4 A 1 (10) (15) (11) (14) EO GS 2 3 (12) (8) A0 4 5 (13) (1) (7) 6 7 (3) 5 (4) (6) 6 (2) A1 (3) C 8 9 (5) 7 (10) (14) D (4) (5) EI (6) A2 SN54 / 74LS147 SN54 / 74LS148 FAST AND LS TTL DATA 5-140 .SN54/74LS147 • SN54/74LS148 • SN54/74LS748 SN54 / 74LS148 SN54 / 74LS748 FUNCTION TABLE OUTPUTS 6 H X X X L H H H H H 7 H X X L H H H H H H 8 H X L H H H H H H H 9 H L H H H H H H H H D H L L H H H H H H H C H H H L L L L H H H B H H H L L H H L L H A H L H L H L H L H L EI H L L L L L L L L L 0 X H X X X X X X X L 1 X H X X X X X X L H INPUTS 2 X H X X X X X L H H 3 X H X X X X L H H H 4 X H X X X L H H H H 5 X H X X L H H H H H 6 X H X L H H H H H H 7 X H L H H H H H H H A2 H H L L L L H H H H OUTPUTS A1 H H L L H H L L H H A0 H H L H L H L H L H GS H H L L L L L L L L EO H L H H H H H H H H SN54 / 74LS147 FUNCTION TABLE INPUTS 1 H X X X X X X X X L 2 H X X X X X X X L H 3 H X X X X X X L H H 4 H X X X X X L H H H 5 H X X X X L H H H H H = HIGH Logic Level. L = LOW Logic Level.

SN54/74LS147 • SN54/74LS148 • SN54/74LS748 FUNCTIONAL BLOCK DIAGRAMS (continued) G31 (10) 0 (11) 1 G2 (12) 2 G3 (13) 3 G4 4 (1) G5 5 6 (2) G6 (3) G7 7 EI (4) G8 (5) G1 G12 G11 G10 G9 G13 (15) (14) G29 (9) G18 EO GS A0 (7) G23 A1 (6) G28 A2 SN54 / 74LS748 FAST AND LS TTL DATA 5-141 .

FAST AND LS TTL DATA 5-142 .7 3.35 0.0 25 25 Max 5.8 – 1.4 4.0 5.5 4.5 V VCC = MAX. IOH = MAX.0 V IIL mA VCC = MAX.5 V Note 1: Not more than one output should be shorted at a time.8 – 1. nor for more than 1 second.2 – 100 17 20 V 2.65 3. All Inputs = 4.0 mA IOL = 8.7 V IIH mA VCC = MAX. VIN = 2. VIN = VIL or VIH per Truth Table µA VCC = MAX.4 V V 2.8 – 0.0 8.2 0. VIN = VIH or VIL per Truth Table IOL = 4.3 – 0.0 mA VCC = VCC MIN. 74 VOL Output LOW Voltage 74 Input HIGH Current All Others Input 0 (LS748) Inputs 1 – 7 (LS148) Inputs 1 – 7 (LS748) All Others Input 0 (LS748) Inputs 1 – 7 (LS148) Inputs 1 – 7 (LS748) Input LOW Current All Others Input 0 (LS748) Inputs 1 – 7 (LS148) Inputs 1 – 7 (LS748) Short Circuit Current (Note 1) Power Supply Current Output HIGH Output LOW – 20 0.5 – 0.5 5.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.1 0.5 0.SN54/74LS147 • SN54/74LS148 • SN54/74LS748 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. Inputs 7 & E1 = GND All Other Inputs = 4.4 V IOS ICCH ICCL mA mA mA VCC = MAX VCC = MAX. VIN = 7.75 – 55 0 Typ 5.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = 0.25 125 70 – 0. IIN = – 18 mA VCC = MIN. 74 54 74 Min 4.5 0.2 0.5 V V Min 2.5 20 40 40 60 0.0 0.25 0.4 – 0.

0 25 35 9. TA = 25°C) SN54 / 74LS147 Symbol tPLH tPHL tPLH tPHL Any Any From (Input) Any To (Output) Any Limits Waveform In-phase output Out-of-phase output Min Typ 12 12 21 15 Max 18 ns 18 33 ns 23 CL = 15 pF. A1. A0 A1 or A2 Limits Waveform In-phase output Out-of-phase output Out-of-phase output In-phase output In-phase output In-phase output In-phase In phase output Min Typ 14 15 20 16 7. RL = 2.SN54/74LS147 • SN54/74LS148 • SN54/74LS748 AC CHARACTERISTICS (VCC = 5. A1.0 kΩ Unit Test Conditions FAST AND LS TTL DATA 5-143 .0 V.0 kΩ Unit Test Conditions SN54 / 74LS148 SN54 / 74LS748 Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL EI EO EI GS EI A0. A1. A0 A1 or A2 From (Input) 1 thru 7 To (Output) A0. A0 A1 or A2 0 thru 7 GS 0 thru 7 EO 1 thru 7 A0.0 16 12 12 14 12 28 30 Max 18 ns 25 36 ns 29 18 ns 40 55 ns 21 25 ns 25 17 ns 36 21 40 45 ns (LS148) (LS748) CL = 15 pF. F RL = 2.

5 U.L.L. 10 U. Both assertion and negation outputs are provided.L.25 U.L.L. LOW 0.5 U. 0.5 U. b) The Output LOW drive factor is 2. for Military (54) and 5 U. The LS151 can be used as a universal function generator to generate any logic function of four variables. It provides.SN54/74LS151 8-INPUT MULTIPLEXER The TTL / MSI SN54 / 74LS151 is a high speed 8-input Digital Multiplexer.5) U. the ability to select one bit of data from up to eight sources. 0.L.25 U. for Commercial (74) Temperature Ranges.5) U. 10 U. 0.L.L.L. LOGIC SYMBOL 7 4 3 2 1 15 14 13 12 E I0 I1 I2 I3 I4 I5 I6 I7 S0 S1 S2 Z Z 6 5 NOTES: a) 1 TTL Unit Load (U.25 U. in one package. 11 10 9 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-144 .) = 40 µA HIGH/1.L.L. 5 (2. 0.5 U. 8-INPUT MULTIPLEXER LOW POWER SCHOTTKY • • • • • Schottky Process for High Speed Multifunction Capability On-Chip Select Logic Decoding Fully Buffered Complementary Outputs Input Clamp Diodes Limit High Speed Termination Effects J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 I4 15 I5 14 I6 13 I7 12 S0 11 S1 10 S2 9 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 1 I3 2 I2 3 I1 4 I0 5 Z 6 Z 7 E 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC PIN NAMES S0 – S2 E I0 – I7 Z Z Select Inputs Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output (Note b) Complementary Multiplexer Output (Note b) LOADING (Note a) HIGH 0. 5 (2.L.L.6 mA LOW.

SN54/74LS151
LOGIC DIAGRAM
S2 S1 S0 E
11 7 9 10

I0
4

I1
3

I2
2

I3
1

I4
15

I5
14

I6
13

I7
12

VCC = PIN 16 GND = PIN 8 = PIN NUMBERS

6

5

Z

Z

FUNCTIONAL DESCRIPTION The LS151 is a logical implementation of a single pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both assertion and negation outputs are provided. The Enable input (E) is active LOW. When it is not activated, the negation output is HIGH and the assertion output is LOW regardless of all other inputs. The logic function provided at the output is:

Z = E ⋅ (I0 ⋅ S0 ⋅ S1 ⋅ S2 + ⋅ I1 ⋅ S0 ⋅ S1 ⋅ S2 + I2 ⋅ S0 ⋅ S1 ⋅ S2 + I3 ⋅ S0 ⋅ S1 ⋅ S2 + I4 ⋅ S0 ⋅ S1 ⋅ S2 + I5 ⋅ S0 ⋅ S1 ⋅ S2 + I6 ⋅ S0 ⋅ S1 ⋅ S2 + I7 ⋅ S0 ⋅ S1 ⋅ S2). The LS151 provides the ability, in one package, to select from eight sources of data or control information. By proper manipulation of the inputs, the LS151 can provide any logic function of four variables and its negation.

TRUTH TABLE
E H L L L L L L L L L L L L L L L L S2 X L L L L L L L L H H H H H H H H S1 X L L L L H H H H L L L L H H H H S0 X L L H H L L H H L L H H L L H H I0 X L H X X X X X X X X X X X X X X I1 X X X L H X X X X X X X X X X X X I2 X X X X X L H X X X X X X X X X X I3 X X X X X X X L H X X X X X X X X I4 X X X X X X X X X L H X X X X X X I5 X X X X X X X X X X X L H X X X X I6 X X X X X X X X X X X X X L H X X I7 X X X X X X X X X X X X X X X L H Z H H L H L H L H L H L H L H L H L Z L L H L H L H L H L H L H L H L H

H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care

FAST AND LS TTL DATA 5-145

SN54/74LS151
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 0.35 0.5 20 0.1 – 0.4 – 100 10 V µA mA mA mA mA 2.5 2.7 54 74 – 0.65 3.5 3.5 0.25 0.4 Min 2.0 0.7 0.8 – 1.5 Typ Max Unit V V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH , , or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

IIH IIL IOS ICC

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)
Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Select to Output Z Propagation Delay Select to Output Z Propagation Delay Enable to Output Z Propagation Delay Enable to Output Z Propagation Delay Data to Output Z Propagation Delay Data to Output Z Min Typ 27 18 14 20 26 20 15 18 20 16 13 12 Max 43 30 23 32 42 32 24 30 32 26 21 20 Unit ns ns ns ns ns ns Test Conditions

VCC = 5.0 V CL = 15 pF

AC WAVEFORMS
VIN 1.3 V tPHL VOUT 1.3 V 1.3 V tPLH 1.3 V VOUT VIN 1.3 V tPHL 1.3 V tPLH 1.3 V 1.3 V

Figure 1

Figure 2

FAST AND LS TTL DATA 5-146

DUAL 4-INPUT MULTIPLEXER
The LSTTL / MSI SN54 / 74LS153 is a very high speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section. It can select two bits of data from four sources. The two buffered outputs present data in the true (non-inverted) form. In addition to multiplexer operation, the LS153 can generate any two functions of three variables. The LS153 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.

SN54/74LS153

• • • •

DUAL 4-INPUT MULTIPLEXER
LOW POWER SCHOTTKY

Multifunction Capability Non-Inverting Outputs Separate Enable for Each Multiplexer Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 Eb 15 S0 14 I3b 13 I2b 12 I1b 11 I0b 10 Zb 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16

J SUFFIX CERAMIC CASE 620-09
1

1 Ea

2 S1

3 I3a

4 I2a

5 I1a

6 I0a

7 Za

8 GND LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L.

16 1

N SUFFIX PLASTIC CASE 648-08

PIN NAMES S0 E I0, I1 Z Common Select Input Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output (Note b)

0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L.

16 1

D SUFFIX SOIC CASE 751B-03

NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

LOGIC DIAGRAM
Ea I0a
1 6 5

I1a
4

I2a
3

I3a
2

S1
14

S0
10

I0b
11

I1b
12

I2b
13

I3b Eb
15

LOGIC SYMBOL

1

6 5 4 3

10 11 12 13 15 I0b I1b I2b I3b Eb

14 2

Ea I0a I1a I2a I3a S0 Sa Za 7

Zb 9

7

Za

VCC = PIN 16 GND = PIN 8 = PIN NUMBERS

VCC = PIN 16 GND = PIN 8
9

Zb

FAST AND LS TTL DATA 5-147

SN54/74LS153
FUNCTIONAL DESCRIPTION The LS153 is a Dual 4-input Multiplexer fabricated with Low Power, Schottky barrier diode process for high speed. It can select two bits of data from up to four sources under the control of the common Select Inputs (S0, S1). The two 4-input multiplexer circuits have individual active LOW Enables (Ea, Eb) which can be used to strobe the outputs independently. When the Enables (Ea, Eb) are HIGH, the corresponding outputs (Za, Zb) are forced LOW. The LS153 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two Select Inputs. The logic equations for the outputs are shown below. Za = Ea ⋅ (I0a ⋅ S1 ⋅ S0 + I1a ⋅ S1 ⋅ S0 + I2a ⋅ S1 ⋅ S0 + I3a ⋅ S1 ⋅ S0) Zb = Eb ⋅ (I0b ⋅ S1 ⋅ S0 + I1b ⋅ S1 ⋅ S0 + I2b ⋅ S1 ⋅ S0 + I3b ⋅ S1 ⋅ S0) The LS153 can be used to move data from a group of registers to a common output bus. The particular register from which the data came would be determined by the state of the Select Inputs. A less obvious application is a function generator. The LS153 can generate two functions of three variables. This is useful for implementing highly irregular random logic.

TRUTH TABLE
SELECT INPUTS S0 X L L H H L L H H S1 X L L L L H H H H E H L L L L L L L L INPUTS (a or b) I0 X L H X X X X X X I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H OUTPUT Z L L H L H L H L H

H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care

GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

FAST AND LS TTL DATA 5-148

SN54/74LS153
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.4 – 100 10 0.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)
Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Data to Output Propagation Delay Select to Output Propagation Delay Enable to Output Min Typ 10 17 19 25 16 21 Max 15 26 29 38 24 32 Unit ns ns ns Figure 2 Figure 1 Figure 2 VCC = 5.0 V CL = 15 pF Test Conditions

AC WAVEFORMS

VIN

1.3 V tPHL

1.3 V tPLH 1.3 V

VIN

1.3 V tPHL

1.3 V tPLH 1.3 V

VOUT

1.3 V

VOUT

1.3 V

Figure 1

Figure 2

FAST AND LS TTL DATA 5-149

DUAL 1-OF-4 DECODER/ DEMULTIPLEXER
The SN54 / 74LS155 and SN54 / 74LS156 are high speed Dual 1-of-4 Decoder/Demultiplexers. These devices have two decoders with common 2-bit Address inputs and separate gated Enable inputs. Decoder “a” has an Enable gate with one active HIGH and one active LOW input. Decoder “b” has two active LOW Enable inputs. If the Enable functions are satisfied, one output of each decoder will be LOW as selected by the address inputs. The LS156 has open collector outputs for wired-OR (DOT-AND) decoding and function generator applications. The LS155 and LS156 are fabricated with the Schottky barrier diode process for high speed and are completely compatible with all Motorola TTL families.

SN54/74LS155 SN54/74LS156

DUAL 1-OF-4 DECODER / DEMULTIPLEXER
LS156-OPEN-COLLECTOR LOW POWER SCHOTTKY

• • • • • •

Schottky Process for High Speed Multifunction Capability Common Address Inputs True or Complement Data Demultiplexing Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts

J SUFFIX CERAMIC CASE 620-09
16 1

16

N SUFFIX PLASTIC CASE 648-08
1

CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 Eb 15 Eb 14 A0 13 O3b 12 O2b 11 O1b 10 O0b 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

16 1

D SUFFIX SOIC CASE 751B-03

ORDERING INFORMATION
1 Ea 2 Ea 3 A1 4 O3a 5 O2a 6 O1a 8 7 O0a GND SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

LOGIC SYMBOL
PIN NAMES A0, A1 Ea, Eb Ea O0 – O3 Address Inputs Enable (Active LOW) Inputs Enable (Active HIGH) Input Active LOW Outputs (Note b) LOADING (Note a) HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 0 1 1 2 13 3 14 15

E DECODER a 2 3

A0 A1

A0 A1 0 1

E DECODER b 2 3

NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. The HIGH level drive for the LS156 must be established by an external resistor.

7

6

5

4

9 VCC = PIN 16 GND = PIN 8

10 11 12

FAST AND LS TTL DATA 5-150

SN54/74LS155 • SN54/74LS156
LOGIC DIAGRAM
1

Ea Ea
2 13

A0

A1
3 14

Eb Eb
15

VCC = PIN 16 GND = PIN 8 = PIN NUMBERS

7

6

5

4

9

10

11

12

O0a

O1a

O2a

O3a

O0b

O1b

O2b

O3b

FUNCTIONAL DESCRIPTION The LS155 and LS156 are Dual 1-of-4 Decoder/Demultiplexers with common Address inputs and separate gated Enable inputs. When enabled, each decoder section accepts the binary weighted Address inputs (A0, A1) and provides four mutually exclusive active LOW outputs (O0 – O3). If the Enable requirements of each decoder are not met, all outputs of that decoder are HIGH. Each decoder section has a 2-input enable gate. The enable gate for Decoder “a” requires one active HIGH input and one active LOW input (Ea•Ea). In demultiplexing applications, Decoder “a” can accept either true or complemented data by using the Ea or Ea inputs respectively. The enable gate for Decoder “b” requires two active LOW inputs (Eb•Eb). The LS155 or LS156 can be used as a 1-of-8 Decoder/Demultiplexer by tying Ea to Eb and relabeling the common connection as (A2). The other Eb and Ea are connected together to form the common enable. The LS155 and LS156 can be used to generate all four minterms of two variables. These four minterms are useful in some applications replacing multiple gate functions as shown in Fig. a. The LS156 has the further advantage of being able to

AND the minterm functions by tying outputs together. Any number of terms can be wired-AND as shown below. f = (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) where E = Ea + Ea; E = Eb + Eb
E A0 A1 E A0 A1 E A0 A1 E A0 A1 E O0 A0 A1 E O1 A0 A1 E O2 A0 A1 E O3 A0 A1 O0

O1

O2

O3

Figure a

TRUTH TABLE
ADDRESS A0 X X L H L H A1 X X L L H H ENABLE “a” Ea L X H H H H Ea X H L L L L O0 H H L H H H OUTPUT “a” O1 H H H L H H O2 H H H H L H O3 H H H H H L ENABLE “b” Eb H X L L L L Eb X H L L L L O0 H H L H H H OUTPUT “b” O1 H H H L H H O2 H H H H L H O3 H H H H H L

H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care

FAST AND LS TTL DATA 5-151

SN54/74LS155
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.4 – 100 10 0.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)
Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Address, Ea or Eb to Output Propagation Delay Address to Output Propagation Delay Ea to Output Min Typ 10 19 17 19 18 18 Max 15 30 26 30 27 27 Unit ns ns ns Figure 1 Figure 2 Figure 1 VCC = 5.0 V CL = 15 pF Test Conditions

AC WAVEFORMS
VIN 1.3 V tPHL VOUT 1.3 V 1.3 V tPLH 1.3 V VOUT 1.3 V tPHL 1.3 V 1.3 V tPLH 1.3 V

VIN

Figure 1

Figure 2

FAST AND LS TTL DATA 5-152

SN54/74LS156
GUARANTEED OPERATING RANGES
Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 5.5 4.0 8.0 Unit V °C V mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Current Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Power Supply Current – 0.4 10 0.35 0.5 20 IIH IIL ICC V µA mA mA mA 54, 74 54, 74 0.25 – 0.65 0.8 – 1.5 100 0.4 V µA V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, VOH = MAX IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX

AC CHARACTERISTICS (TA = 25°C)
Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Address, Ea or Eb to Output Propagation Delay Address to Output Propagation Delay Ea to Output Min Typ 25 34 31 34 32 32 Max 40 51 46 51 48 48 Unit ns ns ns Figure 1 Figure 2 Figure 1 VCC = 5.0 V CL = 15 pF RL = 2.0 kΩ Test Conditions

AC WAVEFORMS
VIN 1.3 V tPHL VOUT 1.3 V 1.3 V tPLH 1.3 V VOUT 1.3 V tPHL 1.3 V 1.3 V tPLH 1.3 V

VIN

Figure 1

Figure 2

FAST AND LS TTL DATA 5-153

QUAD 2-INPUT MULTIPLEXER
The LSTTL / MSI SN54 / 74LS157 is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs present the selected data in the true (non-inverted) form. The LS157 can also be used to generate any four of the 16 different functions of two variables. The LS157 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.

SN54/74LS157

• • • • • •

QUAD 2-INPUT MULTIPLEXER
LOW POWER SCHOTTKY

Schottky Process for High Speed Multifunction Capability Non-Inverting Outputs Input Clamp Diodes Limit High Speed Termination Effects Special Circuitry Ensures Glitch Free Multiplexing ESD > 3500 Volts CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 E 15 I0c 14 I1c 13 Zc 12 I0d 11 I1d 10 Zd 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16

J SUFFIX CERAMIC CASE 620-09
1

1 S

2 I0a

3 I1d

4 Za

5 I0b

6 I1b

7 Zb

8 GND LOADING (Note a) HIGH LOW 0.5 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L.

16 1

N SUFFIX PLASTIC CASE 648-08

PIN NAMES S E I0a – I0d I1a – I1d Za – Zd Common Select Input Enable (Active LOW) Input Data Inputs from Source 0 Data Inputs from Source 1 Multiplexer Outputs (Note b)

1.0 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 10 U.L.

16 1

D SUFFIX SOIC CASE 751B-03

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.

LOGIC DIAGRAM
I0a
2 3

I1a
5

I0b
6

I1b
14

I0c
13

I1c
11

I0d
10

I1d E S
15 1

LOGIC SYMBOL
15 2 3 5 6 14 13 11 10

E I0a I1a I0b I1b I0c I1c I0d I1d 1 S Za Zb Zc Zd

4

7

12

9

4

7

12

9

VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Zd

VCC = PIN 16 GND = PIN 8

Za

Zb

Zc

FAST AND LS TTL DATA 5-154

SN54/74LS157
FUNCTIONAL DESCRIPTION The LS157 is a Quad 2-Input Multiplexer fabricated with the Schottky barrier diode process for high speed. It selects four bits of data from two sources under the control of a common Select Input (S). The Enable Input (E) is active LOW. When E is HIGH, all of the outputs (Z) are forced LOW regardless of all other inputs. The LS157 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select Input. The logic equations for the outputs are:

Za = E ⋅ (I1a ⋅ S + I0a ⋅ S) Zc = E ⋅ (I1c ⋅ S + I0c ⋅ S)

Zb = E ⋅ (I1b ⋅ S + I0b ⋅ S) Zd = E ⋅ (I1d ⋅ S + I0d ⋅ S)

A common use of the LS157 is the moving of data from two groups of registers to four common output busses. The particular register from which the data comes is determined by the state of the Select Input. A less obvious use is as a function generator. The LS157 can generate any four of the 16 different functions of two variables with one variable common. This is useful for implementing highly irregular logic.

TRUTH TABLE
ENABLE E H L L L L
H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care

SELECT INPUT S X H H L L

INPUTS I0 X X X L H I1 X L H X X

OUTPUT Z L L H L H

GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

FAST AND LS TTL DATA 5-155

SN54/74LS157
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current I0, I1 E, S I0, I1 E, S IIL IOS ICC Input LOW Current I0, I1 E, S Short Circuit Current (Note 1) Power Supply Current – 20 0.35 0.5 20 40 0.1 0.2 – 0.4 – 0.8 – 100 16 V µA 2.5 2.7 54 74 – 0.65 3.5 3.5 0.25 0.4 Min 2.0 0.7 0.8 – 1.5 V V V V Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V

IIH

mA

VCC = MAX, VIN = 7.0 V

mA mA mA

VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)
Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Data to Output Propagation Delay Enable to Output Propagation Delay Select to Output Min Typ 9.0 9.0 13 14 15 18 Max 14 14 20 21 23 27 Unit ns ns ns Figure 2 Figure 1 Figure 2 VCC = 5.0 V CL = 15 pF Test Conditions

AC WAVEFORMS
VIN 1.3 V tPHL VOUT 1.3 V 1.3 V tPLH 1.3 V VOUT 1.3 V tPHL 1.3 V 1.3 V tPLH 1.3 V

VIN

Figure 1

Figure 2

FAST AND LS TTL DATA 5-156

QUAD 2-INPUT MULTIPLEXER
The LSTTL / MSI SN54L / 74LS158 is a high speed Quad 2-input Multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs present the selected data in the inverted form. The LS158 can also generate any four of the 16 different functions of two variables. The LS158 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.

SN54/74LS158

• • • • • •

QUAD 2-INPUT MULTIPLEXER
LOW POWER SCHOTTKY

Schottky Process for High Speed Multifunction Capability Inverted Outputs Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts Special Circuitry Ensures Glitch Free Multiplexing CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 E 15 I0c 14 I1c 13 Zc 12 I0d 11 I1d 10 Zd 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16

J SUFFIX CERAMIC CASE 620-09
1

1 S

2 I0a

3 I1a

4 Za

5 I0b

6 I1b

7 Zb

8 GND LOADING (Note a) HIGH LOW 0.5 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L.

16 1

N SUFFIX PLASTIC CASE 648-08

PIN NAMES S E I0a – I0d I1a – I1d Za – Zd Common Select Input Enable (Active LOW) Input Data Inputs from Source 0 Data Inputs from Source 1 Inverted Outputs (Note b)

1.0 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 10 U.L.

16 1

D SUFFIX SOIC CASE 751B-03

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.

LOGIC DIAGRAM
I0a
2 3

I1a
5

I0b
6

I1b
14

I0c
13

I1c
11

I0d
10

I1d E S
15 1

LOGIC SYMBOL
15 2 3 5 6 14 13 11 10

E I0a I1a I0b I1b I0c I1c I0d I1d 1 S Za Zb Zc Zd

4

7

12

9

4

7

12

9

VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Zd

VCC = PIN 16 GND = PIN 8

Za

Zb

Zc

FAST AND LS TTL DATA 5-157

SN54/74LS158
FUNCTIONAL DESCRIPTION The LS158 is a Quad 2-input Multiplexer fabricated with the Schottky barrier diode process for high speed. It selects four bits of data from two sources under the control of a common Select Input (S) and presents the data in inverted form at the four outputs. The Enable Input (E) is active LOW. When E is HIGH, all of the outputs (Z) are forced HIGH regardless of all other inputs. The LS158 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is deter-

mined by the logic levels supplied to the Select Input. A common use of the LS158 is the moving of data from two groups of registers to four common output busses. The particular register from which the data comes is determined by the state of the Select Input. A less obvious use is as a function generator. The LS158 can generate four functions of two variables with one variable common. This is useful for implementing gating functions.

TRUTH TABLE
ENABLE E H L L L L
H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care

SELECT INPUT S X L L H H

INPUTS I0 X L H X X I1 X X X L H

OUTPUT Z H H L H L

GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

FAST AND LS TTL DATA 5-158

nor for more than 1 second.5 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Data to Output Propagation Delay Enable to Output Propagation Delay Select to Output Min Typ 7.25 0. VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN.7 0.3 V tPHL 1. I1 E. S I0. IIN = – 18 mA VCC = MIN.1 0.3 V 1.8 – 1. VIN = 0. I1 E. S Short Circuit Current (Note 1) Power Supply Current – 20 0.3 V 1.SN54/74LS158 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54 74 54. VIN = 2.5 V V V V Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.4 – 0.8 – 100 8.0 10 11 18 13 16 Max 12 15 17 24 20 24 Unit ns ns ns Figure 2 Figure 1 Figure 2 VCC = 5.3 V VOUT 1.0 V CL = 15 pF Test Conditions AC WAVEFORMS VIN 1.3 V tPLH 1.2 – 0.0 mA IOL = 8. IOH = MAX. I1 E.5 20 40 0. 74 VOL Output LOW Voltage 74 Input HIGH Current I0.0 0. All other input combinations. VIN = 7.65 3.5 2. All outputs open.7 V VCC = MAX. ICC Power Supply Current 11 mA VCC = MAX Note 1: Not more than one output should be shorted at a time.5 V.0 V IIH mA mA mA VCC = MAX. S IIL IOS ICC Input LOW Current I0.4 V VCC = MAX VCC = MAX All inputs at 4.3 V VIN Figure 1 Figure 2 FAST AND LS TTL DATA 5-159 .4 Min 2.3 V tPHL VOUT 1. VIN = VIL or VIH per Truth Table VCC = MAX.35 0.3 V tPLH 1.7 54 74 – 0.5 3. All outputs open.0 V µA mA 2.

0. 0. 0.25 U.0 U. the clock and all other control inputs.25 U. 0.L.L.0 U.25 U.5 U. 0. 0. 0. *MR for LS160A and LS161A *SR for LS162A and LS163A 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC 1 *R 2 CP 3 P0 4 P1 5 P2 6 P3 8 7 CEP GND PIN NAMES PE P0 – P3 CEP CET CP MR SR Q0 – Q3 TC Parallel Enable (Active LOW) Input Parallel Inputs Count Enable Parallel Input Count Enable Trickle Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Synchronous Reset (Active LOW) Input Parallel Outputs (Note b) Terminal Count Output (Note b) LOADING (Note a) HIGH 1.L.L.L.L. for Commercial (74) Temperature Ranges.L.BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS The LS160A / 161A / 162A / 163A are high-speed 4-bit synchronous counters. for Military (54) and 5 U.L. 5 (2. They are edge-triggered.25 U. 0.5 U. but is active only during the rising clock edge.L. 0. The LS160A and LS162A count modulo 10 (BCD). synchronously presettable. LOGIC SYMBOL 9 3 4 5 6 7 10 2 PE P0 P1 P2 P3 CEP CET CP TC 15 *R Q0 Q1 Q2 Q3 NOTES: a) 1 TTL Unit Load (U.L.L.L. LOW 0. 10 U.) The LS160A and LS161A have an asynchronous Master Reset (Clear) input that overrides. 5 (2.5 U. The LS161A and LS163A count modulo 16 (binary.L. 0.L.5 U. 1. BCD (Modulo 10) Asynchronous Reset Synchronous Reset LS160A LS162A Binary (Modulo 16) LS161A LS163A SN54/74LS160A SN54/74LS161A SN54/74LS162A SN54/74LS163A BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 • • • • • • Synchronous Counting and Loading Two Count Enable Inputs for High Speed Synchronous Expansion Terminal Count Fully Decoded Edge-Triggered Operation Typical Count Rate of 35 MHz ESD > 3500 Volts CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L. memory addressing. 1 14 13 12 11 VCC = PIN 16 GND = PIN 8 *MR for LS160A and LS161A *SR for LS162A and LS163A FAST AND LS TTL DATA 5-160 .5) U. and cascadable MSI building blocks for counting.L. and is independent of. 1.L. b) The Output LOW drive factor is 2.L.L.5 U.L.0 U.5 U.5 U.5 U.5) U. 10 U. frequency division and other applications.L.6 mA LOW.) = 40 µA HIGH/1. The LS162A and LS163A have a Synchronous Reset (Clear) input that overrides all other control inputs.

HHHH for the Binary counters). 14. it will return to its normal sequence within two clock pulses. The AND feature of the two Count Enable inputs (CET • CEP) allows synchronous cascading without external gating and without delay accumulation over any practical number of bits or digits. 12. If loaded with a code in excess of 9 they return to their legitimate sequence within two counts. 13. The MR pin should never be left open. to reset the counter synchronously after reaching a predetermined value. The LS161A and LS163A count modulo 16 following a binary sequence. and PE inputs are HIGH. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care FAST AND LS TTL DATA 5-161 . as explained in the state diagram. the counters will synchronously load the data from the parallel inputs into the flip-flops on the LOW to HIGH transition of the clock. From this state they increment to state 0 (LLLL). They generate a TC output when the CET input is HIGH while the counter is in state 9 (HLLH). They generate a TC when the CET input is HIGH while the counter is in state 15 (HHHH). As long as the set-up time requirements are met. there are no special timing or activity constraints on any of the mode control or data inputs. 11. With the PE held HIGH. States 10 through 15 do not generate a TC output. but will not count beyond 9. The Terminal Count (TC) output is HIGH when the Count Enable Trickle (CET) input is HIGH while the counter is in its maximum count state (HLLH for the BCD counters. Note that TC is fully decoded and will. be HIGH only for one count state.g. The Master Reset (MR) of the LS160A and LS161A is asynchronous. or 15. If not used. CEP and PE. This simplifies the design from race-free logic controlled reset circuits. If preset to state 10.SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A STATE DIAGRAM LS160A • LS162A 0 1 2 3 4 0 LS161A • LS163A LOGIC EQUATIONS 1 2 3 4 15 5 15 5 14 6 14 6 Count Enable = CEP • CET • PE TC for LS160A & LS162A = CET • Q0 • Q1 • Q2 • Q3 TC for LS161A & LS163A = CET • Q0 • Q1 • Q2 • Q3 Preset = PE • CP + (rising clock edge) Reset = MR (LS160A & LS161A) Reset = SR • CP + (rising clock edge) Reset = (LS162A & LS163A) 13 7 13 7 12 11 10 9 8 12 11 10 9 8 NOTE: The LS160A and LS162A can be preset to any state. and resetting the four counter flip-flops on the LOW to HIGH transition of the clock. the LOW to HIGH transition of the Clock input (CP). and synchronous with. Either the CEP or CET can be used to inhibit the count sequence. The Count Mode is enabled when the CEP. Count Enable Parallel (CEP) and Count Enable Trickle (CET) — select the mode of operation as shown in the tables below. therefore. MODE SELECT TABLE *SR L H H H H PE X L H H H CET X X H L X CEP X X H X L Action on the Rising Clock Edge ( RESET (Clear) LOAD (Pn → Qn) COUNT (Increment) NO CHANGE (Hold) NO CHANGE (Hold) ) *For the LS162A and *LS163A only. a LOW on either the CEP or CET inputs at least one set-up time prior to the LOW to HIGH clock transition will cause the existing output states to be retained. From this state they increment to state 0 (LLLL). the MR pin should be tied through a resistor to VCC. overriding CET. The counters consist of four edge-triggered D flip-flops with the appropriate data routing networks feeding the D inputs. Three control inputs — Parallel Enable (PE). it overrides all other input conditions and sets the outputs LOW. or to a gate output which is permanently set to a HIGH logic level.. The active LOW Synchronous Reset (SR) input of the LS162A and LS163A acts as an edge-triggered control input. When the MR is LOW. e. The LS160A and LS162A count modulo 10 following a binary coded decimal (BCD) sequence. CET. When the PE is LOW. All changes of the Q outputs (except due to the asynchronous Master Reset in the LS160A and LS161A) occur as a result of. FUNCTIONAL DESCRIPTION The LS160A / 161A / 162A / 163A are 4-bit synchronous counters with a synchronous Parallel Enable (Load) feature.

25 125 70 – 0. IOH = MAX. CEP.4 – 0. VIN = 2. VIN = 0.0 V IIH mA mA mA VCC = MAX. CET IIL IOS ICC Input LOW Current MR.7 54 74 – 0. 74 VOL Output LOW Voltage 74 Input HIGH Current MR. Clock PE. VIN = VIH or VIL per Truth Table IOL = 4.4 4.65 3. Clock PE.5 V V V V Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.25 0. VIN = 7. CET Short Circuit Current (Note 1) Power Supply Current Total.8 – 1.0 25 25 Max 5. CET MR.0 mA IOL = 8.7 V VCC = MAX. FAST AND LS TTL DATA 5-162 . Clock PE.4 Min 2. Output HIGH Total.35 0. nor for more than 1 second.5 5. 74 54 74 Min 4. CEP.SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.2 – 0. CEP.5 3.1 0. Output LOW – 20 0.75 – 55 0 Typ 5.5 0.0 mA VCC = VCC MIN.5 4.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.5 2. Data.0 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 8. Data.8 – 100 31 32 V µA mA 2.0 Unit V °C mA mA LS160A and LS161A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54 74 54. IIN = – 18 mA VCC = MIN.5 20 40 0. Data.7 0.0 5.

CEP. VIN = VIL or VIH per Truth Table VCC = MAX. CET. VIN = 2. IIN = – 18 mA VCC = MIN. SR CET Short Circuit Current (Note 1) Power Supply Current Total. 74 VOL Output LOW Voltage 74 Input HIGH Current Data.4 Min 2.5 3.1 0. Clock PE. VIN = VIH or VIL per Truth Table IOL = 4.7 V VCC = MAX.0 20 35 35 24 27 14 14 28 Max Unit MHz ns ns ns ns VCC = 5.4 – 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. SR Data.0 V IIH mA mA mA VCC = MAX. AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Clock to TC Propagation Delay Clock to Q Propagation Delay CET to TC MR or SR to Q Min 25 Typ 32 20 18 13 18 9. nor for more than 1 second. SR IIL IOS ICC Input LOW Current Data. PE.8 – 1.0 9.25 0.7 54 74 – 0.65 3. Output LOW – 20 0.5 20 40 0. VIN = 0. CEP. CET. CEP. Output HIGH Total.SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A LS162A and LS163A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54 74 54.2 – 0. VIN = 7.0 0.0 mA VCC = VCC MIN. Clock.0 mA IOL = 8.5 2.7 0. Clock PE.35 0.0 V CL = 15 pF Test Conditions FAST AND LS TTL DATA 5-163 .5 V V V V Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.8 – 100 31 32 V µA mA 2. IOH = MAX.5 0.

3 V tW trec 1.0 V DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs.3 V tPLH 1. other Recovery Time MR to CP Min 25 20 20 25 3 0 15 Typ Max Unit ns ns ns ns ns ns ns Test Conditions VCC = 5. data Hold Time. CET or DATA Parameter Clock Pulse Width Low MR or SR Pulse Width Setup Time. and Master Reset Recovery Time FAST AND LS TTL DATA 5-164 .3 V tW(L) 1.3 V OTHER CONDITIONS: PE = L P0 = P1 = P2 = P3 = H CP Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 tPHL 1.3 V Figure 1.SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tWCP tW ts ts th th trec *CEP. Master Reset Pulse Width. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs.3 V tPHL Q 1. Master Reset to Output Delay. Clock to Output Delays. and Clock Pulse Width Figure 2. AC WAVEFORMS tW(H) CP 1. other* Setup Time PE or SR Hold Time.3 V OTHER CONDITIONS: PE = MR (SR) = H CEP = CET = H MR 1. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. Count Frequency.

3 V ts(H) CP ts(L) SR or PE 1.3 V tPHL 1. MR = H SETUP TIME (ts) AND HOLD TIME (th) FOR COUNT ENABLE (CEP) AND (CET) AND PARALLEL ENABLE (PE) INPUTS The shaded areas indicate when the input is permitted to change for predictable output performance.SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A AC WAVEFORMS (continued) COUNT ENABLE TRICKLE INPUT TO TERMINAL COUNT OUTPUT DELAYS The positive TC pulse occurs when the outputs are in the (Q0 • Q1 • Q2 • Q3) state for the LS160 and LS162 and the (Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163.3 V TC 1.3 V th(L) = 0 1. 7) CEP ts(H) CET 1.3 V th(L) = 0 1.3 V Figure 4 OTHER CONDITIONS: PE = CEP = CET = MR = H CP 1.3 V th(L) = 0 1.3 V COUNT MODE (See Fig.3 V HOLD Figure 6 Figure 7 FAST AND LS TTL DATA 5-165 .3 V th(H) = 0 1. CET 1.3 V Figure 3 OTHER CONDITIONS: CP = PE = CEP = MR = H CLOCK TO TERMINAL COUNT DELAYS CP The positive TC pulse is coincident with the output state (Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163 and (Q0 • Q1 • Q2 • Q3) for the LS161 and LS163.3 V SETUP TIME (ts) AND HOLD TIME (th) FOR PARALLEL DATA INPUTS The shaded areas indicate when the input is permitted to change for predictable output performance.3 V tPLH 1. 1. 5) Q RESPONSE TO PE RESET Q RESPONSE TO SR COUNT OR LOAD Q OTHER CONDITIONS: PE = H.3 V ts(L) 1.3 V HOLD 1.3 V 1.3 V tPHL 1.3 V th(H) = 0 1.3 V ts(L) 1. 1.3 V 1.3 V tPLH 1.3 V CP th(H) = 0 1.3 V th(H) = 0 1. MR = H ts(H) 1. P0 • P1 • P2 • P3 ts(H) Q0 • Q1 • Q2 • Q3 Figure 5 OTHER CONDITIONS: PE = L.3 V COUNT ts(L) 1.3 V th (L) = 0 1.3 V PARALLEL LOAD (See Fig.3 V TC 1.

L. B CP MR Q0 – Q7 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs (Note b) LOADING (Note a) HIGH 0.L. VCC = PIN 14 GND = PIN 7 FAST AND LS TTL DATA 5-166 .L.6 mA LOW. LOW 0. b) The Output LOW drive factor is 2.5 U.25 U.L.L.25 U.L. Ceramic Plastic SOIC LOGIC SYMBOL 1 2 8 A LS164 B 8-BIT SHIFT REGISTER CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 3 4 5 6 10 11 12 13 NOTES: a) 1 TTL Unit Load (U.5) U. for Commercial (74) Temperature Ranges.25 U. 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 A 2 B 3 Q0 4 Q1 5 Q2 6 Q3 7 GND 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD PIN NAMES A.5 U.L. 0. SERIAL-IN PARALLEL-OUT SHIFT REGISTER LOW POWER SCHOTTKY • • • • • • Typical Shift Frequency of 35 MHz Asynchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts 14 1 J SUFFIX CERAMIC CASE 632-08 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 Q7 13 Q6 12 Q5 11 Q4 10 MR 9 CP 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. for Military (54) and 5 U. 0.) = 40 µA HIGH/1.L.5 U. 10 U. The device features an asynchronous Master Reset which clears the register setting all outputs LOW independent of the clock.L.5 U.SN54/74LS164 SERIAL-IN PARALLEL-OUT SHIFT REGISTER The SN54 / 74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Register. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all Motorola TTL products. 0. 0.L. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock. 5 (2.L.

0 5.4 4.5 5.0 Unit V °C mA mA FAST AND LS TTL DATA 5-167 . Data is entered serially through one of two inputs (A or B). or both inputs connected together.0 25 25 Max 5.25 125 70 – 0. Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A•B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously.0 8. 74 54 74 Min 4. forcing all Q outputs LOW. An unused input must be tied HIGH.75 – 55 0 Typ 5.SN54/74LS164 LOGIC DIAGRAM 1 2 A D B CD CD CD CD CD CD CD CD CP MR VCC = PIN 14 GND = PIN 7 = PIN NUMBERS Q0 3 Q D Q D Q D Q D Q D Q D Q D Q 8 9 Q1 4 Q2 5 Q3 6 Q4 10 Q5 11 Q6 12 Q7 13 FUNCTIONAL DESCRIPTION The LS164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages.5 4. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. MODE SELECT — TRUTH TABLE OPERATING MODE Reset (Clear) Shift INPUTS MR L H H H H A X I I h h B X I h I h OUTPUTS Q0 L L L L H Q1–Q7 L–L q0 – q6 q0 – q6 q0 – q6 q0 – q6 L (l) = LOW Voltage Levels H (h) = HIGH Voltage Levels X = Don’t Care qn = Lower case letters indicate the state of the referenced input or output one qn = set-up time prior to the LOW to HIGH clock transition. either of these inputs can be used as an active HIGH Enable for data entry through the other input.

IIN = – 18 mA VCC = MIN.0 20 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.35 0. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. VIN = VIH or VIL per Truth Table IOL = 4. AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay MR to Output Q Propagation Delay Clock to Output Q Min 25 Typ 36 24 17 21 36 27 32 Max Unit MHz ns ns VCC = 5.4 V 2.SN54/74LS164 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. VIN = 7.5 V 0. MR Pulse Width Data Setup Time Data Hold Time MR to Clock Recovery Time Min 20 15 5.7 V VCC = MAX.8 – 1.4 –100 27 0.7 3.0 mA VCC = VCC MIN. VIN = 0.0 mA IOL = 8.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.0 Test Conditions FAST AND LS TTL DATA 5-168 . VIN = 2.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0. VIN = VIH or VIL per Truth Table VCC = MAX.0 V VCC = MAX.0 V CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts th trec Parameter CP.5 V Min 2.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.5 – 0.25 0. IOH = MAX. nor for more than 1 second.65 3.0 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.5 0.

SN54/74LS164 AC WAVEFORMS *The shaded areas indicate when the input is permitted to change for predictable output performance.3 V trec 1.3 V ts(L) 1. Data Setup and Hold Times FAST AND LS TTL DATA 5-169 .3 V tW 1.3 V th(H) 1. Master Reset to Output Delay and Master Reset to Clock Recovery Time 1/fmax tW CP 1.3 V 1. Master Reset Pulse Width.3 V 1.3 V 1.3 V MR 1.3 V th(L) 1. I/fmax 1. Clock to Output Delays and Clock Pulse Width Figure 2.3 V Figure 3.3 V ts(H) D * 1.3 V tW 1.3 V CP tPHL Q 1.3 V Q 1.3 V CONDITIONS: MR = H tPLH 1.3 V 1.3 V Figure 1.3 V CP tPHL Q 1.3 V 1.

L.25 U. CP2 DS PL P0 – P7 Q7 Q7 Clock (LOW-to-HIGH Going Edge) Inputs Serial Data Input Asynchronous Parallel Load (Active LOW) Input Parallel Data Inputs Serial Output from Last State (Note b) Complementary Output (Note b) LOADING (Note a) HIGH 0. 0.L.L. LOW 0. Parallel inputing occurs asynchronously when the Parallel Load (PL) input is LOW. 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC NOTES: a) 1 TTL Unit Load (U.5) U.L. 5 (2. 16 1 J SUFFIX CERAMIC CASE 620-09 1 PL 2 CP1 3 P4 4 P5 5 P6 6 P7 7 Q7 8 GND 16 1 N SUFFIX PLASTIC CASE 648-08 PIN NAMES CP1. TRUTH TABLE CP PL 1 L H H H H X L H 2 X Q0 P0 DS Q0 DS Q0 Q1 P1 Q0 Q1 Q0 Q1 Q2 P2 Q1 Q2 Q1 Q2 Q3 P3 Q2 Q3 Q2 Q3 Q4 P4 Q3 Q4 Q3 Q4 Q5 P5 Q4 Q5 Q4 Q5 Q6 P6 Q5 Q6 Q5 Q6 Q7 P7 Q6 Q7 Q6 Q7 Parallel Entry Right Shift No Change Right Shift No Change CONTENTS RESPONSE LOGIC SYMBOL 1 11 12 13 14 3 4 5 6 PL P0 P1 P2 P3 P4 P5 P6 P7 DS Q7 CP Q7 10 2 15 L H 9 7 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-170 .5 U.L.L.5 U. for Commercial (74) Temperature Ranges.L.L.L.25 U. With PL HIGH.L. The 2-input OR clock can be used to combine two independent clock sources.5 U. new data enters via the Serial Data (DS) input.L.5 U.25 U. 5 (2.L. or one input can act as an active LOW clock enable. 0.8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER The SN54 / 74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage.75 U. 0.L.L.5) U. 10 U. 1. serial shifting occurs on the rising edge of the clock.5 U. 0.6 mA LOW. SN54/74LS165 8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 CP2 15 P3 14 P2 13 P1 12 P0 11 DS 10 Q7 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L. 0. 10 U.) = 40 µA HIGH/1. b) The Output LOW drive factor is 2. for Military (54) and 5 U.

25 125 70 – 0.5 4.4 4. however.5 5. PL must be HIGH. The parallel data can change while PL is LOW.75 – 55 0 Typ 5. with respect to the rising edge of the clock.0 5.SN54/74LS165 LOGIC DIAGRAM 11 12 13 14 3 4 5 6 P0 P1 P2 P3 P4 P5 P6 P7 10 DS 2 CP1 15 CP2 1 PL PRESET S Q0 CP R C Q0 L PRESET S Q1 CP R C Q1 L PRESET S Q2 CP R C Q2 L PRESET S Q3 CP R C Q3 L PRESET S Q4 CP R C Q4 L PRESET S Q5 CP R C Q5 L PRESET S Q6 CP R C Q6 L PRESET S Q7 CP R C Q7 L 9 7 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FUNCTIONAL DESCRIPTION The SN54/74LS165 contains eight clocked master/slave RS flip-flops connected as a shift register. one can be used as a clock inhibit by applying a HIGH signal. To avoid double clocking. The flip-flops are edge-triggered for serial operations.0 8. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. The serial input data can change at any time. provided only that the recommended setup and hold times are observed. 74 54 74 Min 4.0 Unit V °C mA mA FAST AND LS TTL DATA 5-171 . with auxiliary gating to provide overriding asynchronous parallel entry. Otherwise. The two clock inputs perform identically. For clock operation. Parallel data enters when the PL signal is LOW. the inhibit signal should only go HIGH while the clock is HIGH. provided that the recommended setup and hold times are observed.0 25 25 Max 5. the rising inhibit signal will cause the same response as a rising clock edge.

VIN = 0.25 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. VIN = VIL or VIH per Truth Table VCC = MAX.SN54/74LS165 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.0 mA VCC = VCC MIN. 74 VOL Output LOW Voltage 74 Input HIGH Current Other Inputs PL Input Other Inputs PL Input IIL IOS ICC Input LOW Current Other Inputs PL Input Short Circuit Current (Note 1) Power Supply Current – 20 0.0 mA IOL = 8.4 – 1.0 V mA mA mA VCC = MAX.0 V CL = 15 pF F Test Conditions FAST AND LS TTL DATA 5-172 .7 V IIH mA VCC = MAX.1 0.5 V V Min 2. VIN = 7.8 – 1.5 – 0. IOH = MAX.7 3. AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Maximum Input Clock Frequency Propagation Delay PL to Output Propagation Delay Clock to Output Propagation Delay P7 to Q7 Propagation Delay P7 to Q7 Min 25 Typ 35 22 22 27 28 14 21 21 16 35 35 40 40 25 30 30 25 Max Unit MHz ns ns ns ns VCC = 5.2 – 100 36 V µA 2.65 3. VIN = 2.5 20 60 0. nor for more than 1 second. VIN = VIH or VIL per Truth Table IOL = 4.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.5 0.0 0. IIN = – 18 mA VCC = MIN.5 0.3 – 0.4 V V 2.35 0.

SN54/74LS165
AC SETUP REQUIREMENTS (TA = 25°C)
Limits Symbol tW tW ts ts ts th trec Parameter CP Clock Pulse Width PL Pulse Width Parallel Data Setup Time Serial Data Setup Time CP1 to CP2 Setup Time1 Hold Time Recovery Time, PL to CP Min 25 15 10 20 30 0 45 Typ Max Unit ns ns ns ns ns ns ns VCC = 5.0 V Test Conditions

1 The role of CP , and CP in an application may be interchanged. 1 2

DEFINITION OF TERMS: SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued

recognition. A negative hold time indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the PL pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer loaded Data to the Q outputs.

AC WAVEFORMS

CP1 tW ts CP2 1.3 V tPHL 1.3 V 1/fmax tW tPLH 1.3 V 1.3 V Q7 OR Q7 PL 1.3 V tPLH 1.3 V 1.3 V 1.3 V tPHL 1.3 V

Q7 OR Q7

Figure 1

Figure 2

Pn ts(H) PL OR CP

1.3 V th(H) ts(L) 1.3 V

1.3 V th(L) 1.3 V

PL

1.3 V tW

1.3 V trec 1.3 V

CP

Figure 3

Figure 4

FAST AND LS TTL DATA 5-173

SN54/74LS166 8-BIT SHIFT REGISTERS
The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54 / 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified. The LS166 is a parallel-in or serial-in, serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or serial-in mode. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.

8-BIT SHIFT REGISTERS
LOW POWER SCHOTTKY

J SUFFIX CERAMIC CASE 620-09
16 1

• Synchronous Load • Direct Overriding Clear • Parallel to Serial Conversion
PARALLEL PARALLEL INPUTS F 11 F E 10 E CLEAR 9

16 1

N SUFFIX PLASTIC CASE 648-08

SHIFT/ INPUT OUTPUT H QH G VCC LOAD 16 15 14 13 12 SHIFT/ LOAD H QH G

16 1

D SUFFIX SOIC CASE 751B-03

SERIAL INPUT A 1 SERIAL INPUT 2 A B 3 B C 4 C D 5 D

CLEAR CLOCK INHIBIT CK 8 6 7 CLOCK CLOCK GND INHIBIT

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

PARALLEL INPUTS

FUNCTION TABLE
INPUTS CLEAR L H H H H H SHIFT/ LOAD X X L H H X CLOCK INHIBIT X L L L L H PARALLEL CLOCK X L ↑ ↑ ↑ ↑ SERIAL A...H X X X H L X X X a...h X X X QA L QA0 a H L QA0 QB L QB0 b QAn QAn QB0 L QH0 h QGn QGn QH0 INTERNAL OUTPUTS OUTPUT QH

FAST AND LS TTL DATA 5-174

SN54/74LS166
Typical Clear, Shift, Load, Inhibit, and Shift Sequences
CLOCK CLOCK INIHIBIT CLEAR SERIAL INPUT SHIFT/LOAD A B C PARALLEL INPUTS D E F G H OUTPUT QH SERIAL SHIFT CLEAR (9) CLEAR (1) SERIAL INPUT (15) SHIFT/LOAD (2) A
R CK S

H L H L H L H H INHIBIT LOAD H H L H L H L SERIAL SHIFT H

QA B (3)
R S

CK

QB C (4)
R S

CK

QC D (5)
R S

CK

E

(10)
R

QD

CK

S

F

(11)
R

QE

CK

S

QF (12) G
R CK S

QG H CLOCK CLOCK INHIBIT (14) (7) (6)
R S

CK

(13) Q H

FAST AND LS TTL DATA 5-175

SN54/74LS166
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.4 – 100 38 0.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA 5-176

SN54/74LS166
TEST TABLE FOR SYNCHRONOUS INPUTS
DATA INPUT FOR TEST H Serial Input SHIFT/LOAD 0V 4.5 V OUTPUT TESTED QH at tn+1 QH at tn+8

AC WAVEFORMS
tw(clear) CLEAR INPUT Vref Vref 0V tn CLOCK INPUT Vref tw(clock) DATA INPUT (SEE TEST TABLE) Vref Vref tsu tn + 1 (SEE NOTE 1) tn tn + 1 3V Vref th Vref tsu Vref th Vref 0V tPHL (clear-Q) Vref tPHL (CLK-Q) VOH Vref Vref VOL
NOTE 1. tn = bit time before clocking transition NOTE 1. tn+1 = bit time after one clocking transition NOTE 1. tn+8 = bit time after eight clocking transition NOTE 1. LS166 Vref = 1.3 V.

3V

0V 3V

tPLH (CLK-Q)

OUTPUT Q

AC CHARACTERISTICS (TA = 25°C)
Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Clock Frequency Clear to Output Clock to Output Min 25 Typ 35 19 23 24 30 35 35 Max Unit MHz ns ns VCC = 5.0 V CL = 15 pF F Test Conditions

AC SETUP REQUIREMENTS (TA = 25°C)
Limits Symbol tW ts ts th Parameter Clock Clear Pulse Width Mode Control Setup Time Data Setup Time Hold Time, Any Input Min 30 30 20 15 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.0 Test Conditions

FAST AND LS TTL DATA 5-177

BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS
The SN54 / 74LS168 and SN54 / 74LS169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U / D input to control the direction of counting. The SN54 / 74LS168 counts in a BCD decade (8, 4, 2, 1) sequence, while the SN54 / 74LS169 operates in a Modulo 16 binary sequence. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock.

SN54/74LS168 SN54/74LS169

BCD DECADE / MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS
LOW POWER SCHOTTKY

• • • • • • •

Low Power Dissipation 100 mW Typical High-Speed Count Frequency 30 MHz Typical Fully Synchronous Operation Full Carry Lookahead for Easy Cascading Single Up / Down Control Input Positive Edge-Trigger Operation Input Clamp Diodes Limit High-Speed Termination Effects

J SUFFIX CERAMIC CASE 620-09
16 1

CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1

N SUFFIX PLASTIC CASE 648-08

16 1

D SUFFIX SOIC CASE 751B-03

1 U/D

2 CP

3 P0

4 P1

5 P2

6 P3

8 7 CEP GND

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

PIN NAMES

LOADING (Note a) HIGH LOW 0.25 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L.

CEP CET CP PE U/D P0–P3 Q0–Q3 TC

Count Enable Parallel (Active LOW) Input Count Enable Trickle (Active LOW) Input Clock Pulse (Active positive going edge) Input Parallel Enable (Active LOW) Input Up-Down Count Control Input Parallel Data Inputs Flip-Flop Outputs Terminal Count (Active LOW) Output

0.5 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L.

LOGIC SYMBOL
9 3 4 5 6

NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges.

1 7 10 2

PE P0 P1 P2 P3 U/D CEP TC CET CP Q0 Q1 Q2 Q3

15

14 13 12 11 VCC = PIN 16 GND = PIN 8

FAST AND LS TTL DATA 5-178

SN54/74LS168 • SN54/74LS169
STATE DIAGRAMS SN54/ 74LS168 UP / DOWN DECADE COUNTER
0 1 2 3 4 0

SN54 / 74LS169

1

2

3

4

15

5 Count Up Count Down

15

5

14

6

14

6

13

7

13

7

12

11

10

9

8

12

11

10

9

8

SN54 / 74LS168 UP: TC = Q0 ⋅ Q3 ⋅ (U / D) DOWN: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U / D)

SN54 / 74LS169 UP: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U / D) DOWN: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U / D)

LOGIC DIAGRAMS SN54 / 74LS168
P0 PE P1 P2 P3

CEP CET U/D

TC

CP CP D

Q0

Q1

Q2

Q3

FAST AND LS TTL DATA 5-179

SN54/74LS168 • SN54/74LS169
LOGIC DIAGRAMS (continued) SN54 / 74LS169
P0 PE P1 P2 P3

CEP CET U/D

TC

CP CP D

Q0

Q1

Q2

Q3

GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

FAST AND LS TTL DATA 5-180

SN54/74LS168 • SN54/74LS169

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current Other Inputs CET Input Other Input CET Input IIL IOS ICC Input LOW Current Other Input CET Input Short Circuit Current (Note 1) Power Supply Current – 20 0.35 0.5 20 40 0.1 0.2 – 0.4 – 0.8 – 100 34 V µA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V

IIH

mA

VCC = MAX, VIN = 7.0 V

mA mA mA

VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at one time, nor for more than 1 second.

FUNCTIONAL DESCRIPTION The SN54/74LS168 and SN54/74LS169 use edgetriggered D-type flip-flops that have no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a set-up time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0 – P3 inputs enters the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH. The U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the COUNT DOWN mode or reaches 15 (9 for the SN54/74LS168) in the COUNT UP mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. The TC output of the SN54/74LS168 decade counter can also be LOW in the illegal states 11, 13 and 15, which can occur when power is turned on or via parallel loading. If illegal state occurs, the SN54/74LS168 will return to the legitimate sequence within two counts. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended.

MODE SELECT TABLE
PE L H H H H CEP X L L H X CET X L L X H U/D X H L X X Action on Rising Clock Edge Load (Pn → Qn) Count Up (increment) Count Down (decrement) No Change (Hold) No Change (Hold)

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

FAST AND LS TTL DATA 5-181

SN54/74LS168 • SN54/74LS169
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay, Clock to TC Propagation Delay, Clock to any Q Propagation Delay, CET to TC Propagation Delay, U / D to TC Min 25 Typ 32 23 23 13 15 15 15 17 19 35 35 20 23 20 20 25 29 Max Unit MHz ns ns ns ns VCC = 5.0 V CL = 15 pF F Test Conditions

AC SETUP REQUIREMENTS (TA = 25°C)
Limits Symbol tW ts ts ts th Parameter Clock Pulse Width Setup Time, Data or Enable Setup Time PE Setup Time U/D Hold Time Any Input Min 25 20 25 30 0 Typ Max Unit ns ns ns ns ns Test Conditions

VCC = 5.0 V

FAST AND LS TTL DATA 5-182

SN54/74LS168 • SN54/74LS169
AC WAVEFORMS
1/fmax CP 1.3 V tPHL 1.3 V 1.3 V tW tPLH 1.3 V 1.3 V CET

1.3 V tPLH

1.3 V tPHL 1.3 V

TC

1.3 V

Q OR TC

Figure 1. Clock to Output Delays, Count Frequency, and Clock Pulse Width

Figure 2. Count Enable Trickle Input To Terminal Count Output Delays

CP ts(H) CP 1.3 V tPLH TC 1.3 V 1.3 V 1.3 V tPHL 1.3 V Q0 • Q1 • Q2 • Q3 P0 • P1 • P2 • P3 1.3 V

1.3 V th(H) = 0 1.3 V ts(L) 1.3 V

1.3 V th(L) = 0 1.3 V

Figure 3. Clock to Terminal Delays

Figure 4. Setup Time (ts) and Hold (th) for Parallel Data Inputs

CP ts(L) SR OR PE 1.3 V

1.3 V th(L) = 0 1.3 V ts(H) 1.3 V

1.3 V th(H) = 0 1.3 V U/D tPLH 1.3 V 1.3 V tPHL 1.3 V 1.3 V

CP ts(H) CEP 1.3 V ts(H) CET 1.3 V

1.3 V th(H) = 0 1.3 V th(H) = 0 1.3 V ts(L) 1.3 V

1.3 V th(L) = 0 1.3 V ts(L) 1.3 V

1.3 V

TC

Figure 6. Up-Down Input to Terminal Count Output Delays
th(L) = 0 1.3 V

The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 5. Setup Time and Hold Time for Count Enable and Parallel Enable Inputs, and Up-Down Control Inputs

FAST AND LS TTL DATA 5-183

SN54/74LS170 4 x 4 REGISTER FILE OPEN-COLLECTOR
The TTL / MSI SN54 / 74LS170 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation. Open-collector outputs make it possible to connect up to 128 outputs in a wired-AND configuration to increase the word capacity up to 512 words. Any number of these devices can be operated in parallel to generate an n-bit length. The SN54 / 74LS670 provides a similar function to this device but it features 3-state outputs.

4 x 4 REGISTER FILE OPEN-COLLECTOR
LOW POWER SCHOTTKY

• • • • •

Simultaneous Read / Write Operation Expandable to 512 Words of n-Bits Typical Access Time of 20 ns Low Leakage Open-Collector Outputs for Expansion Typical Power Dissipation of 125 mW

J SUFFIX CERAMIC CASE 620-09
16 1

CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 D1 15 WA 14 WB 13 EW 12 ER 11 Q1 10 Q2 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1

N SUFFIX PLASTIC CASE 648-08

16 1

D SUFFIX SOIC CASE 751B-03

1 D2

2 D3

3 D4

4 RB

5 RA

6 Q4

7 Q3

8 GND

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

PIN NAMES

LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 0.5 U.L. 5 (2.5) U.L.

LOGIC SYMBOL
12 14 13 5 4 WA EW WB RA RB ER 11 15 1 2 3 D1 D2 D3 D4 Q1 Q2 Q3 Q4 10 9 7 6

D1 – D 4 WA, WB EW RA, RB ER Q1 – Q4

Data Inputs Write Address Inputs Write Enable (Active LOW) Input Read Address Inputs Read Enable (Active LOW) Input Outputs (Note b)

0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 1.0 U.L. Open-Collector

NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. The Output HIGH drive must be supplied by an external resistor to VCC.

VCC = PIN 16 GND = PIN 8

FAST AND LS TTL DATA 5-184

SN54/74LS170
LOGIC DIAGRAM

D4
12 3

D3
2

D2
1

D1
15

EW
13

WB WA
14

G Q

D

G Q

D

G Q

D

G Q

D

WORD 0

G Q

D

G Q

D

G Q

D

G Q

D

WORD 1

G Q

D

G Q

D

G Q

D

G Q

D

WORD 2

G Q RB
4

D

G Q

D

G Q

D

G Q

D

WORD 3

11

ER RA
5

6

7

9

10

VCC = PIN 16 GND = PIN 8 = PIN NUMBERS

Q4

Q3

Q2

Q1

FAST AND LS TTL DATA 5-185

SN54/74LS170
WRITE FUNCTION TABLE (SEE NOTES A, B, AND C)
WRITE INPUTS WB L L H H X WA L H L H X EW L L L L H 0 Q=D Q0 Q0 Q0 Q0 1 Q0 Q=D Q0 Q0 Q0 WORD 2 Q0 Q0 Q=D Q0 Q0 3 Q0 Q0 Q0 Q=D Q0

READ FUNCTION TABLE (SEE NOTES A AND D)
READ INPUTS RB L L H H X RA L H L H X ER L L L L H Q1 W0B1 W1B1 W2B1 W3B1 H OUTPUTS Q2 W0B2 W1B2 W2B2 W3B2 H Q3 W0B3 W1B3 W2B3 W3B3 H Q4 W0B4 W1B4 W2B4 W3B4 H

NOTES: A. H = HIGH Level. L = LOW Level, X = Irrelevant. NOTES: B. (Q = D) = The four selected internal flip-flop outputs will assume the states applied to the four external data inputs. NOTES: C. Q0 = the level of Q before the indicated input conditions were established. NOTES: D. W0B1 = The first bit of word 0, etc.

GUARANTEED OPERATING RANGES
Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 5.5 4.0 8.0 Unit V °C V mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Current Output LOW Voltage 74 Input HIGH Current Any D, R, W ER, EW Any D, R, W ER, EW IIL ICC Input LOW Current Any D, R, W ER, EW Power Supply Current 0.35 0.5 20 40 0.1 0.2 – 0.4 – 0.8 40 V µA 54, 74 54, 74 0.25 – 0.65 0.8 – 1.5 100 0.4 V µA V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, VOH = MAX IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.4 V

IIH

mA

VCC = MAX, VIN = 7.0 V

mA mA

VCC = MAX, VIN = 0.4 V VCC = MAX

FAST AND LS TTL DATA 5-186

D2. Q2.0 kΩ Test Conditions VOLTAGE WAVEFORMS WRITE-SELECT INPUT WA or WB DATA INPUT D1.0 25 Typ Max Unit ns ns ns ns ns ns VCC = 5. WA. EW Setup Time. Q3 or Q4 Vref READ-SELECT INPUT RA or RB READ-ENABLE INPUT ER OUTPUT Q1. WB to EW Hold Time.0 kΩ AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts ts th th tLATCH Parameter Pulse Width. WA. Data to EW Hold Time. D3 or D4 WRITE-ENABLE INPUT EW Vref tsu(W) Vref tw Vref tlatch Vref th(W) Vref th(D) tsu(D) Vref 3V 0V 3V 0V 3V 0V 3V Vref tW Vref tPHL Vref Vref tPLH Vref tPLH 0V 3V 0V VOH VOL DATA INPUT D1. Q2. ER.0 V CL = 15 pF F RL = 2. D3 or D4 WRITE-ENABLE INPUT EW OUTPUT Q1. Q2. D2. Q3 or Q4 Vref DATA INPUT D1. NegativeGoing ER to Q Outputs Propagation Delay. RA or RB to Q Outputs Propagation Delay. D2. NegativeGoing EW to Q Outputs Propagation Delay. Data Inputs to Q Outputs Min Typ 20 20 25 24 30 26 30 22 Max 30 30 40 40 45 40 45 35 Unit ns ns ns ns Figure 1 Figure 2 Figure 1 Figure 1 Test Conditions VCC = 5. Q3 or Q4 tPHL Vref Figure 1 Figure 2 FAST AND LS TTL DATA 5-187 . Data to EW Setup Time.0 V RL = 2. WB to EW Latch Time Min 25 10 15 15 5.SN54/74LS170 AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay. D3 or D4 WRITE-ENABLE INPUT EW 3V Vref 0V 3V Vref tPLH tPHL Vref VOL 3V Vref 0V 3V Vref tPHL tPLH Vref 0V 0V 3V 0V VOH OUTPUT Q1.

25 U.) = 40 µA HIGH/1. 15 3 4 5 6 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-188 .25 U.5 U. for Commercial (74) b. IE2).L.L. • Fully Edge-Triggered • 3-State Outputs • Gated Input and Output Enables • Input Clamp Diodes Limit High-Speed Termination Effects 16 1 4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 MR 15 D0 14 D1 13 D2 12 D3 11 IE2 10 IE1 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L. 1 TTL Unit Load (U. 0.5 U. LOGIC SYMBOL 9 10 1 2 IE CP 1 2 OE MR Q0 Q1 Q2 Q3 D0 D1 D2 D3 14 13 12 11 7 1 2 NOTES: a.L.25 U.6 mA LOW. b.25 U. 0. OE2) brings the output to a high impedance state without affecting the actual register contents. Temperature Ranges. A HIGH on the Master Reset (MR) input resets the Register regardless of the state of the Clock (CP).L. 0.L. D0 – D 3 IE1 – IE2 OE1 – OE2 CP MR Q0 – Q3 Data Inputs Input Enable (Active LOW) Output Enable (Active LOW) Inputs Clock Pulse (Active HIGH Going Edge) Input Master Reset Input (Active HIGH) Outputs (Note b) 0.5 U. IE2) lines. 0.L. 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 OE1 2 OE2 3 Q0 4 Q1 5 Q2 6 Q3 7 CP 8 GND 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC PIN NAMES LOADING (Note a) HIGH LOW 0.5) U.L.L.L.25 U.5 U. 0. 0. 15 (7. 65 (25) U. 0. the Output Enable (OE1. The Output LOW drive factor is 2.SN54/74LS173A 4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS173A is a high-speed 4-Bit Register featuring 3-state outputs for use in bus-organized systems. for Military (54) and 5 U. The clock is fully edge-triggered allowing either a load from the D inputs or a hold (retain register contents) depending on the state of the Input Enable Lines (IE1. 0.L. OE2) or the Input Enable (IE1.L. A HIGH on either Output Enable line (OE1.5 U.L.L.L.5 U.

SN54/74LS173A LOGIC DIAGRAM D0 14 D1 13 D2 12 D3 11 IE1 IE2 9 10 CP 7 CP D Q MR 15 D D D Q OE1 OE2 1 2 3 4 5 6 Q0 Q1 Q2 Q3 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS TRUTH TABLE MR H L L L L L CP x L IE1 x x H x L L IE2 x x x H L L Dn x x x x L H Qn L Qn Qn Qn L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial When either OE1. the output is in the off state (High Impedance).75 – 55 0 Typ 5.0 25 25 Max 5. or OE2 are HIGH. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54 74 54 74 Min 4.25 125 70 – 1.0 – 2. however this does not affect the contents or sequential operation of the register.6 12 24 Unit V °C mA mA FAST AND LS TTL DATA 5-189 .5 4.0 5.5 5.

4 V VCC = MAX.0 V F. IOH = MAX.4 3. 74 VOL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0. VIN = 0.25 0.35 0.65 3. RL = 667 Ω VCC = 5.SN54/74LS173A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.1 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 30 – 0. Any Input Recovery Time Min 20 35 17 0 10 Typ Max Unit ns ns ns ns ns VCC = 5.0 pF.4 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPLH tPHL tPHL tPZH tPZL tPLZ tPHZ Parameter Maximum Input Clock Frequency Propagation Delay. nor for more than 1 second.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. VO = 0.4 – 0. MR to Output Output Enable Time Output Disable Time Min 30 Typ 50 17 22 26 15 18 11 11 25 30 35 23 27 17 17 Max Unit MHz ns ns ns ns CL = 5.4 V V 2. VO = 2. VIN = 2. CL = 45 pF RL = 667 Ω Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts ts th trec Parameter Clock or MR Pulse Width Data Enable Setup Time Data Setup Time Hold Time.5 V V Min 2.7 V VCC = MAX. Clock to Output Propagation Delay. VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN.0 0.5 20 – 20 20 V µA µA µA mA mA mA mA 2.0 V VCC = MAX.8 – 1. VIN = 7.7 V VCC = MAX. VIN = VIL or VIH per Truth Table VCC = MAX. IIN = – 18 mA VCC = MIN.4 – 130 30 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 V Test Conditions FAST AND LS TTL DATA 5-190 .

3 V tPZH tPHZ 1.3 V ≥ VOH ≈ 1.3 V tPLZ 1.3 V Figure 3 Figure 4 AC LOAD CIRCUIT VCC RL SYMBOL SW1 TO OUTPUT UNDER TEST tPZH tPZL tPLZ tPHZ 5 kΩ CL* SWITCH POSITIONS SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed SW2 * Includes Jig and Probe Capacitance.3 V 0.3 V tPHL 1.3 V 0.3 V tPZL 1.3 V MR tW CP tPHL 1.3 V ts(H) D or E 1.5 V VOUT VOUT 1.SN54/74LS173A AC WAVEFORMS 1 / fmax tW 1.3 V Q Q tPLH 1.5 V VOL VE 1.3 V th(L) 1.3 V CP Figure 1 Figure 2 VE 1.3 V trec 1.3 V th(H) ts(L) 1. Figure 5 FAST AND LS TTL DATA 5-191 .

L.L. 5 (2. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition.L.L. for Commercial (74) b. 10 U. The Output LOW drive factor is 2.25 U. 0.5 U. Temperature Ranges.L. The device has a Master Reset to simultaneously clear all flip-flops. 1 TTL Unit Load (U. The device is used primarily as a 6-bit edge-triggered storage register.5) U.L.5 U. 0. for Military (54) and 5 U.L.25 U. HEX D FLIP-FLOP LOW POWER SCHOTTKY • • • • Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Asynchronous Common Reset Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q5 15 D5 14 D4 13 Q4 12 D3 11 Q3 10 CP 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 0. 16 16 1 J SUFFIX CERAMIC CASE 620-09 N SUFFIX PLASTIC CASE 648-08 1 1 MR 2 Q0 3 D0 4 D1 5 Q1 6 D2 7 Q2 8 GND PIN NAMES LOADING (Note a) 16 HIGH D0 – D 5 CP MR Q0 – Q5 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs (Note b) 0.L. The LS174 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.6 mA LOW.L. LOW 0. 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC NOTES: a.L. 0.5 U.25 U.5 U.SN54/74LS174 HEX D FLIP-FLOP The LSTTL / MSI SN54 / 74LS174 is a high speed Hex D Flip-Flop. LOGIC SYMBOL LOGIC DIAGRAM 3 4 6 11 13 14 MR CP D5 1 9 14 D4 13 D3 11 D2 6 D1 4 D0 3 9 1 D Q CP CD 15 D Q CP CD 12 D Q CP CD 10 D Q CP CD 7 D Q CP CD 5 D Q CP CD D0 D1 D2 D3 D4 D5 CP MR Q0 Q1 Q2 Q3 Q4 Q5 2 5 7 10 12 15 2 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Q5 Q4 Q3 Q2 Q1 Q0 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-192 . b.L.) = 40 µA HIGH/1.

25 0.5 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. VIN = 7. Each D input’s state is transferred to the corresponding flipflop’s output following the LOW to HIGH Clock (CP) transition. IIN = – 18 mA VCC = MIN. Outputs (t = n+1) Note 1 Q H L GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.0 25 25 Max 5. The Clock (CP) and Master Reset (MR) are common to all flip-flops.4 4.0 0. VIN = VIH or VIL per Truth Table IOL = 4.0 8.65 3.5 5.5 V V Min 2. IOH = MAX. VIN = VIL or VIH per Truth Table VCC = MAX.0 V VCC = MAX. FAST AND LS TTL DATA 5-193 .5 4.4 – 100 26 0. The LS174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.0 mA VCC = VCC MIN.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0. MR = H) D H L Note 1: t = n + 1 indicates conditions after next clock.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.5 0. 74 54 74 Min 4.35 0.7 3.0 5.7 V VCC = MAX.SN54/74LS174 FUNCTIONAL DESCRIPTION The LS174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs.25 125 70 – 0.75 – 55 0 Typ 5. TRUTH TABLE Inputs (t = n.8 – 1.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.5 – 0. VIN = 0. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.4 V V 2. VIN = 2. nor for more than 1 second.0 mA IOL = 8.

3 V 1. Clock to Output Delays. Clock Pulse Width. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs.0 V CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts th trec Parameter Clock or MR Pulse Width Data Setup Time Data Hold Time Recovery Time Min 20 20 5. Master Reset to Output Delay. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized.3 V tPLH 1.SN54/74LS174 AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Input Clock Frequency Propagation Delay. MR to Output Propagation Delay. FAST AND LS TTL DATA 5-194 .3 V 1.3 V Q *The shaded areas indicate when the input is permitted to *change for predictable output performance. Frequency. Master Reset Pulse Width.3 V t th(H)s(L) 1. Setup and Hold Times Data to Clock Figure 2.3 V CP Q tPHL 1. Figure 1.3 V trec 1.3 V ts(H) D * 1.0 Test Conditions AC WAVEFORMS 1/fmax tw CP 1.0 25 Typ Max Unit ns ns ns ns VCC = 5 0 V 5. Clock to Output Min 30 Typ 40 23 20 21 35 30 30 Max Unit MHz ns ns VCC = 5.3 V tW 1. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition.3 V tPHL 1.3 V MR 1. and Master Reset Recovery Time DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs.3 V th(L) 1.

16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 1 MR 2 Q0 3 Q0 4 D0 5 D1 6 Q1 7 Q1 8 GND LOADING (Note a) HIGH LOW 0. for Military (54) and 5 U. 0.L. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC NOTES: a. for Commercial (74) b. The LS175 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.L.25 U. Temperature Ranges. The device is useful for general flip-flop requirements where clock and clear inputs are common. 10 U. 5 (2.L.QUAD D FLIP-FLOP The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. LOGIC SYMBOL 4 5 12 13 LOGIC DIAGRAM MR CP D3 1 9 13 D2 12 D1 5 D0 4 9 CP D0 D1 D2 D3 D Q CP Q CD 14 15 D Q CP Q CD 11 10 D Q CP Q CD 6 7 D Q CP Q CD 3 2 1 MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 3 2 6 7 11 10 14 15 VCC = PIN 16 Q3 Q3 GND = PIN 8 = PIN NUMBERS Q2 Q2 Q1Q1 Q0 Q0 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-195 .L. The Output LOW drive factor is 2.L.L.25 U.5 U. Both true and complemented outputs of each flip-flop are provided. 0. b.25 U. The information on the D inputs is stored during the LOW to HIGH clock transition.5 U. 5 (2. SN54/74LS175 QUAD D FLIP-FLOP LOW POWER SCHOTTKY • • • • • • Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Clock to Output Delays of 30 ns Asynchronous Common Reset True and Complement Output Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L. 1 TTL Unit Load (U.L. 16 1 PIN NAMES D SUFFIX SOIC CASE 751B-03 D0 – D 3 CP MR Q0 – Q3 Q0 – Q3 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input True Outputs (Note b) Complemented Outputs (Note b) 0. independent of the Clock or D inputs.L.L. 0.6 mA LOW.5 U. when LOW. A Master Reset input resets all flip-flops.L.5) U.5) U. 0.5 U. 10 U.) = 40 µA HIGH/1.L.L.

VIN = 2.5 – 0.35 0.5 4. IIN = – 18 mA VCC = MIN. 74 54 74 Min 4.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2. The LS175 is useful for general logic applications where a common Master Reset and Clock are acceptable. VIN = VIL or VIH per Truth Table VCC = MAX.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.5 5.25 0.SN54/74LS175 FUNCTIONAL DESCRIPTION The LS175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. TRUTH TABLE Inputs (t = n. nor for more than 1 second.0 0.0 25 25 Max 5.65 3.5 0.7 V VCC = MAX.25 125 70 – 0. VIN = 7.4 V V 2.75 – 55 0 Typ 5.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. causing individual Q and Q outputs to follow.4 – 100 18 0.0 V VCC = MAX. The four flip-flops will store the state of their individual D inputs on the LOW to HIGH Clock (CP) transition.0 mA VCC = VCC MIN.0 5.5 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0. VIN = VIH or VIL per Truth Table IOL = 4. IOH = MAX. FAST AND LS TTL DATA 5-196 .0 8.0 mA IOL = 8. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. MR = H) D L H Outputs (t = n+1) Note 1 Q L H Q H L Note 1: t = n + 1 indicates conditions after next clock.8 – 1.7 3.5 V V Min 2. The Clock and Master Reset are common. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.4 4. VIN = 0.

0 V CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts th trec Parameter Clock or MR Pulse Width Data Setup Time Data Hold Time Recovery Time Min 20 20 5.SN54/74LS175 AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPLH tPHL tPLH tPHL Parameter Maximum Input Clock Frequency Propagation Delay.3 V tPLH 1. Setup and Hold Times Data to Clock Figure 2. Master Reset Pulse Width.3 V tPLH Q Q 1.3 V th(L) 1.3 V trec 1. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. Master Reset to Output Delay. Frequency.3 V ts(H) D * 1.0 25 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.3 V MR 1.3 V *The shaded areas indicate when the input is permitted to *change for predictable output performance.3 V tw 1.3 V Q CP Q tPLH 1.3 V 1. and Master Reset Recovery Time DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs.3 V tPHL 1. Clock to Output Min 30 Typ 40 20 20 13 16 30 30 25 25 Max Unit MHz ns ns VCC = 5. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs.3 V tPHL 1. Clock to Output Delays. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. FAST AND LS TTL DATA 5-197 .3 V t th(H) s(L) 1. MR to Output Propagation Delay.0 Test Conditions AC WAVEFORMS 1/fmax CP 1.3 V tPHL 1.3 V tW 1.3 V 1. Figure 1. Clock Pulse Width.

LOW 0.) = 40 µA HIGH/1. NOR.5 U. LOGIC SYMBOL PIN NAMES LOADING (Note a) HIGH A0 – A3.L. 1. 2.5 U.L. FAST AND LS TTL DATA 5-198 . 0.L. B0 – B3 S0 – S3 M Cn F0 – F3 A=B G P Cn+4 Operand (Active LOW) Inputs Function — Select Inputs Mode Control Input Carry Input Function (Active LOW) Outputs Comparator Output Carry Generator (Active LOW) Output Carry Propagate (Active LOW) Output Carry Output 1.L. b.5) U. NAND.5) U.L. operations on two variables and a variety of arithmetic operations.0 U. Subtract.L.SN54/74LS181 4-BIT ARITHMETIC LOGIC UNIT The SN54 / 74LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible 16 logic.5 U.75 U. 7 8 6 5 4 3 Cn M 2 1 23 22 21 20 19 18 A0 B0 A1 B1 A2 B2 A3 B3 Cn+4 A=B G P F1 10 F2 11 F3 13 16 14 17 15 S0 S1 S2 S3 F0 9 VCC = PIN 24 GND = PIN 12 NOTES: a.L. The Output LOW drive factor is 2. Plus Ten other Logic Operations Plus Twelve Other Arithmetic Operations 4-BIT ARITHMETIC LOGIC UNIT LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) VCC A1 24 23 B1 22 A2 21 B2 20 A3 19 B3 18 G Cn+4 17 16 P 15 A=B 14 F3 13 24 1 J SUFFIX CERAMIC CASE 623-05 N SUFFIX PLASTIC CASE 649-03 24 1 1 B0 2 A0 3 S3 4 S2 5 S1 6 S0 7 Cn 8 M 9 F0 10 F1 11 12 F2 GND ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN Ceramic Plastic NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L. 5 (2. OR. • Provides all 16 Logic Operations of Two Variables Exclusive — OR. 5 (2. 5 (2.6 mA LOW. Open Collector 10 U.L.5) U. 5 U.0 U.L. for Military (54) and 5 U.L.5 U.L. 10 U. Double. 1 TTL Unit Load (U. • Provides 16 Arithmetic Operations Add. for Commercial (74) b. 10 U. Temperature Ranges.L. 1. 2.L.L. AND.L. • Full Lookahead for High Speed Arithmetic Operation on Long Words • Input Clamp Diodes Compare.L.L. 10 U.25 U.L. 10 U. Compare.25 U.L. 0.

Controlled by the four Function Select Inputs (S0 . When the Mode Control Input (M) is HIGH. The Function Table lists the arithmetic operations that are performed without a carry in. a carry out means borrow. the carries are enabled and the device performs arithmetic operations on the two 4-bit words. One carry lookahead package is required for each group of the four LS181 devices. FAST AND LS TTL DATA 5-199 . When the Mode Control Input is LOW. P and G are not affected by carry in. The A = B output is open collector and can be wired-AND with other A = B outputs to give a comparison for more then four bits. As indicated.SN54/74LS181 LOGIC DIAGRAM 7 8 2 1 23 22 21 20 19 18 Cn M A0 B0 A1 B1 A2 B2 A3 B3 S0 6 5 S1 S2 4 S3 3 VCC = PIN 24 GND = PIN 12 = PIN NUMBERS F0 9 10 F1 A=B 14 11 F2 13 F3 15 P 16 Cn+4 17 G FUNCTIONAL DESCRIPTION The SN54 / 74LS181 is a 4-bit high speed parallel Arithmetic Logic Unit (ALU). Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths. When speed requirements are not stringent. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn+4 output. the LS181 can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. S3) and the Mode Control Input (M). For high speed operation the LS181 is used in conjunction with the 9342 or 93S42 carry lookahead circuit. The Function Table lists these operations. . thus a carry is generated when there is no underflow and no carry is generated when there is underflow. Because subtraction is actually performed by complementary addition (1s complement). select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. The A = B signal can also be used with the Cn+4 signal to indicate A>B and A<B. The A = B output from the LS181 goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the subtract mode. or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). it can perform all the 16 possible logic operations or 16 different arithmetic operations on active HIGH or active LOW operands. . Thus. For either case the table lists the operations that are performed to the operands labeled inside the logic symbol. all internal carries are inhibited and the device performs logic operations on the individual bits as listed. An incoming carry adds a one to each operation. the LS181 can be used in a simple ripple carry mode by connecting the Carry Output (Cn+4) signal to the Carry Input (Cn) of the next unit.

5 4.0 8. 74 Min 4.25 125 70 – 0.0 5.SN54/74LS181 FUNCTION TABLE MODE SELECT INPUTS S3 L L L L L L L L H H H H H H H H S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H ACTIVE LOW INPUTS & OUTPUTS LOGIC (M = H) ARITHMETIC** (M = L) (Cn = L) ACTIVE HIGH INPUTS & OUTPUTS LOGIC (M = H) ARITHMETIC** (M = L) (Cn = H) A A minus 1 AB AB minus 1 A+B AB minus 1 Logical 1 minus 1 A+B A plus (A + B) B AB plus (A + B) A⊕B A minus B minus 1 A+B A+B AB A plus (A + B) A⊕B A plus B B AB plus (A + B) A+B A+B Logical 0 A plus A* AB AB plus A AB AB plus A A A A A A+B A+B AB A+B Logical 0 minus 1 AB A plus AB B (A + B) plus AB A⊕B A minus B minus 1 AB AB minus 1 A+B A plus AB A⊕B A plus B B (A + B) plus AB AB AB minus 1 Logical 1 A plus A* A+B (A + B) plus A A+B (A + B) Plus A A A minus 1 L = LOW Voltage Level H = HIGH Voltage Level **Each bit is shifted to the next more significant position **Arithmetic operations expressed in 2s complement notation LOGIC SYMBOLS ACTIVE LOW OPERANDS 2 1 23 22 21 20 19 18 A0 B0 A1 B1 A2 B2 A3 B3 Cn+4 A=B LS181 G 4 BIT ARITHMETIC LOGIC UNIT P F1 10 F2 11 F3 13 ACTIVE HIGH OPERANDS 2 1 23 22 21 20 19 18 A0 B0 A1 B1 A2 B2 A3 B3 Cn+4 A=B LS181 G 4 BIT ARITHMETIC LOGIC UNIT P F1 10 F2 11 F3 13 7 8 6 5 4 3 Cn M 16 14 17 15 7 8 6 5 4 3 Cn M 16 14 17 15 S0 S1 S2 S3 F0 9 S0 S1 S2 S3 F0 9 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL VOH Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Output Voltage — High (A = B only) Parameter 54 74 54 74 54.5 Unit V °C mA mA V FAST AND LS TTL DATA 5-200 .75 – 55 0 Typ 5. 74 54 74 54.4 4.0 25 25 Max 5.0 5.5 5.

7 V 0. S0 through S3 and M are at 4. all other inputs are grounded.5 V V V V V V V µA 54.65 2.5 0.0 mA VCC = MIN.1 0.5 100 – 1. VIN = 7.2 – 1. With outputs open.35 0.4 0. ICC is measured for the following conditions: A. VIN = 0. VCC = VCC MIN. Note 2: Not more than one output should be shorted at a time.SN54/74LS181 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 Output LOW Voltage g Except G and P VOL Output G Output P IOH Output HIGH Current Input HIGH Current Mode Input Any A or B Input Any S Input Cn Input Mode Input Any A or B Input Any S Input Cn Input Input LOW Current Mode Input Any A or B Input Any S Input Cn Input Short Circuit Current (Note 2) Power Supply Current y See Note 1A ICC See Note 1B 74 Note 1. VIN = 2. S0 through S3. nor for more than 1 second. VIN = VIH or VIL per Truth Table IOL = 4.7 V mA VCC = MAX.0 – 20 54 74 54 – 100 32 34 µA VCC = MAX. and A inputs are at 4. VIN = VIH or VIL per Truth Table .3 0.6 0.4 0. IOH = MAX.0 mA IOL = 16 mA IOL = 8.6 – 2. IIN = – 18 mA VCC = MIN.0 Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.4 – 1.5 V. M.5 0. Min 2. B.8 – 0.25 0. all other inputs are grounded.5 2.0 V IIL mA VCC = MAX.7 0. 74 74 54. VIN = VIL or VIH per Truth Table 0. 74 IIH 20 60 80 100 0.0 mA IOL = 8.4 V IOS mA VCC = MAX mA 35 37 VCC = MAX FAST AND LS TTL DATA 5-201 . 74 54 74 54. IOH = MAX.5 3.5 – 0.5 V.7 3.

S0 = S3 = 4. S0 = S3 = 4.3 V 1. S1 = S2 = 4. 5 and Table II M = 4.3 V Figure 5 Figure 6 FAST AND LS TTL DATA 5-202 . 4 and Tables I and II M = 0 V.5 V (Sum Mode) See Fig.SN54/74LS181 AC CHARACTERISTICS (TA = 25°C.3 V tPHL 1. S0 = S3 = 4.5 V (Diff Mode) M = S0 = S3 = 0 V. 4 and Table I M = S0 = S3 = 0 V.3 V Figure 4 A INPUT B INPUT 1. 4 and Table I M = S1 = S2 = 0 V. CL = 15 pF) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay.5 V (Sum Mode) See Fig. (Sum Mode) See Fig.3 V tPHL 1.3 V 1. VCC = 5. S0 = S3 = 4.3 V tPHL 1. (Sum or Diff Mode) See Fig.5 V RL = 2.5 V (Logic Mode) See Fig. 5 and Table II M = S1 = S2 = 0 V.3 V OUTPUT 1.5 V. 5 and Table II (A or B Inputs to A = B Output) ns AC WAVEFORMS INPUT 1. 5 and Table II M = S1 = S2 = 0 V. 4 and Table I M = S0 = S3 = 0 V. S1 = S2 = 4. S0 = S3 = 0 V.5 V (Diff Mode) See Fig. S1 = S2 = 4.3 V tPLH 1.3 V tPLH OUTPUT 1.5 V (Sum Mode) See Fig.3 V INPUT 1.5 V (Diff Mode) See Fig.3 V tPLH 1.5 V (Diff Mode) See Fig. (Cn to Cn+4) (Cn to F Outputs) (A or B Inputs to G Output) (A or B Inputs to G Output) (A or B Inputs to P Output) (A or B Inputs to P Output) (AX or BX Inputs to FX Output) (AX or BX Inputs to FX Output) (AX or BX Inputs to FXH Outputs) (AX or BX Inputs to FXH Outputs) (A or B Inputs to F Outputs) (A or B Inputs to Cn+4 Output) (A or B Inputs to Cn+4 Output) 22 26 25 25 27 27 33 41 Min Typ 18 13 17 13 19 15 21 21 20 20 20 22 21 13 21 21 Max 27 20 26 20 29 23 32 32 30 30 30 33 32 20 32 32 38 26 38 38 33 38 38 38 41 41 50 62 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions M = 0 V. S0 = S3 = 4. 4 and Table I M = S0 = S3 = 0 V. 4 and Table I M = S0 = S3 = 0 V. 5 and Table II M = S1 = S2 = 0 V. S1 = S2 = 4.5 V (Diff Mode) See Fig. S1 = S2 = 4.5 V (Sum Mode) See Fig. S1 = S2 = 0 V (Sum Mode) See Fig.3 V 1. S1 = S2 = 4.0 V.3 V OUTPUT 1. Pin 12 = GND. 6 and Table I M = 0 V. 4 and Table III M = 0 V.0 kΩ (Diff Mode) See Fig.

Cn Remaining A. Cn Remaining A.5 V.5 V Bl Al Bl Al B A None None None None None Apply GND None None None None None None B A B A None FUNCTION INPUTS: S0 = S3 = 4. Cn Remaining A and B. S1 = S2 = M = 0 V Other Data Inputs Apply 4. Cn Remaining A. Cn All B Output Under Test Fl Fl Fl+1 Fl+1 P P G G Cn+4 Cn+4 Any F or Cn+4 Parameter tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Input Under Test Al Bl Al Bl A B A B A B Cn FAST AND LS TTL DATA 5-203 .SN54/74LS181 SUM MODE TEST TABLE I Other Input Same Bit Apply 4. Cn Remaining A.5 V Remaining A and B Remaining A and B Cn Cn None None Remaining B Remaining B Remaining B Remaining B All A Apply GND Cn Cn Remaining A and B Remaining A and B Remaining A and B.

5 V None None Apply GND B A Other Data Inputs Apply 4.5 V None None Apply GND Remaining A and B.5 V None A None Al None A B None None A B None None Apply GND B None Bl None B None None A B None None A None FUNCTION INPUTS: S1 = S2 = 4. Cn Remaining A and Bl. Cn Remaining B.5 V S0 = S3 = 0 V S1 = S2 = M = 4.5 V Remaining A Remaining A Remaining B. S0 = S3 = M = 0 V Other Data Inputs Apply 4. Cn Parameter tPLH tPHL tPLH tPHL Input Under Test A B Output Under Test Any F Any F Function Inputs S1 = S2 = M = 4.5 V. Cn None Output Under Test Fl Fl Fl+1 Fl+1 P P G G A=B A=B cn+4 Cn+4 Cn+4 Parameter tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Input Under Test A B Al Bl A B A B A B A B Cn LOGIC MODE TEST TABLE III Other Input Same Bit Apply 4. Cn Remaining B. Cn Remaining A and B. Cn None None None None Remaining A Remaining A None None All A and B Apply GND Remaining B. Cn Remaining B. Cn Remaining B.5 V S0 = S3 = 0 V FAST AND LS TTL DATA 5-204 . Cn Remaining A and B. Cn Remaining A and B. Cn Remaining A and B. Cn Remaining A and B. Cn Remaining A Remaining A Remaining A and B.SN54/74LS181 DIFF MODE TEST TABLE II Other Input Same Bit Apply 4.

.L.25 U. b.25 U. which makes it possible to use the circuits as programmable counters.L.L. 10 U. 0.PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade (8421) Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16 Binary Counter.5) U.L.L. VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-205 .5 U. 0. 0. 5 (2.L.) = 40 µA HIGH/1. 5 (2.5 U. 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC 1 P1 2 Q1 3 Q0 4 CE 5 U/D 6 Q2 7 Q3 8 GND LOGIC SYMBOL 11 15 LOADING (Note a) HIGH LOW 0.L. NOTES: a. The Output LOW drive factor is 2. for Military (54) and 5 U. 10 U.25 U. State changes of the counters are synchronous with the LOW-to-HIGH transition of the Clock Pulse input. 0.L.L.L. Temperature Ranges.L. 0.5) U.L. for Commercial (74) b.L.6 mA LOW.L. . SN54/74LS190 SN54/74LS191 PRESETTABLE BCD / DECADE UP/ DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/ DOWN COUNTERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 • • • • • • • • Low Power .5 U. 90 mW Typical Dissipation High Speed .5 U. 1 TTL Unit Load (U. 0. 0.7 U. .25 U.L. 25 MHz Typical Count Frequency Synchronous Counting Asynchronous Parallel Load Individual Preset Inputs Count Enable and Up / Down Control Inputs Cascadable Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 P0 15 CP 14 RC 13 TC 12 PL 11 P2 10 P3 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. An asynchronous Parallel Load (PL) input overrides counting and loads the data present on the Pn inputs into the flip-flops.5 U.5) U. 5 4 14 U/D CE CP Q0 Q1 Q2 Q3 3 2 6 7 TC 12 PL P0 P1 P2 P3 RC 13 1 10 9 PIN NAMES CE CP U/D PL Pn Qn RC TC Count Enable (Active LOW) Input Clock Pulse (Active HIGH going edge) Input Up/Down Count Control Input Parallel Load Control (Active LOW) Input Parallel Data Inputs Flip-Flop Outputs (Note b) Ripple Clock Output (Note b) Terminal Count Output (Note b) 1.L.L. A Terminal Count (TC) output and a Ripple Clock (RC) output provide overflow/underflow indication and make possible a variety of methods for generating carry / borrow signals in multistage counter applications. A Count Enable (CE) input serves as the carry / borrow input in multi-stage counters.L. .5 U. An Up / Down Count Control (U/D) input determines whether a circuit counts up or down. 0. 5 (2.L. 10 U.

SN54/74LS190 • SN54/74LS191 STATE DIAGRAMS 0 1 2 3 4 0 1 2 3 4 LS190 15 5 UP: TC = Q0 ⋅ Q3 ⋅ (U/D) DOWN: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U/D) 15 5 14 6 LS191 UP: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U/D) DOWN: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U/D) COUNT UP COUNT DOWN 14 6 13 7 13 7 12 11 10 9 8 12 11 10 9 8 LS190 LS191 LOGIC DIAGRAMS CP U/D 14 5 P0 15 CE 4 P1 1 P2 10 P3 9 PL 11 J CLOCK K PRESET CLEAR Q Q 13 12 3 2 J CLOCK K PRESET CLEAR Q Q J CLOCK K PRESET CLEAR Q Q 6 J CLOCK K PRESET CLEAR Q Q 7 RC VCC = PIN 16 GND = PIN 8 = PIN NUMBERS TC Q0 Q1 Q2 Q3 DECADE COUNTER LS190 FAST AND LS TTL DATA 5-206 .

SN54/74LS190 • SN54/74LS191 LOGIC DIAGRAMS (continued) CP U/D 14 5 P0 15 CE 4 P1 1 P2 10 P3 9 PL 11 J CLOCK K PRESET CLEAR Q Q 13 12 3 2 J CLOCK K PRESET CLEAR Q Q J CLOCK K PRESET CLEAR Q Q 6 J CLOCK K PRESET CLEAR Q Q 7 RC VCC = PIN 16 GND = PIN 8 = PIN NUMBERS TC Q0 Q1 Q2 Q3 BINARY COUNTER LS191 FAST AND LS TTL DATA 5-207 .

The RC output is normally HIGH. Note that in order to inhibit counting an enable signal must be included in each carry gate. MODE SELECT TABLE INPUTS MODE PL H H L H CE L L X H U/D L H X X CP Count Up Count Down Preset (Asyn. The TC signal is also used internally to enable the Ripple Clock (RC) output. information present on the Parallel Data inputs (P0 – P3) is loaded into the counter and appears on the Q outputs. When the Parallel Load (PL) input is LOW. Two types of outputs are provided as overflow/underflow indicators. Similarly. as indicated in the RC Truth Table. the LOW-to-HIGH CE transition must occur only while the clock is HIGH. This configuration is particularly advantageous when the clock source has a limited drive capability. 15 for the LS191) in the count-up mode. This represents the cumulative delay of the clock as it ripples through the preceding stages. To prevent counting in all stages it is only necessary to inhibit the first stage. as indicated in Figures a and b. The operating modes of the LS190 decade counter and the LS191 binary counter are identical. with internal gating and steering logic to provide individual preset. The direction of counting is determined by the U/D input signal. is the timing skew between state changes in the first and last stages. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. since a HIGH signal on CE inhibits the RC output pulse. as indicated in the Mode Select Table. All clock inputs are driven in parallel and the RC outputs propagate the carry / borrow signals in ripple fashion. The TC output should not be used as a clock signal because it is subject to decoding spikes. In Figure a. The TC output will then remain HIGH until a state change occurs. The CE input signal for a given stage is formed by combining the TC signals from all the preceding stages. When CE is LOW. because the TC output of a given stage is not affected by its own CE. the CE signal can be made LOW when the clock is in either state. A disadvantage of this configuration. This feature simplifies the design of multi-stage counters. the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. A method of causing state changes to occur simultaneously in all stages is shown in Figure b. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches maximum (9 for the LS190. as indicated in the Mode Select Table. count-up and count-down operations. each RC output is used as the clock input for the next higher stage. internal state change are initiated synchronously by the LOW-to-HIGH transition of the clock input.) No Change (Hold) CE L H X RC TRUTH TABLE INPUTS TC* H X L CP X X RC OUTPUT X X H H * TC is generated internally L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care = LOW-to-HIGH Clock Transition = LOW Pulse FAST AND LS TTL DATA 5-208 . A HIGH signal on the CE input inhibits counting. There is no such restriction on the HIGH state duration of the clock. since the RC output of any package goes HIGH shortly after its CP input goes HIGH. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry / borrow signal to ripple through to the last stop before the clock goes HIGH. The simple inhibit scheme of Figures a and b doesn’t apply. when counting is to be inhibited. whether by counting or presetting or until U / D is changed. with the only difference being the count sequences as noted in the state diagrams.SN54/74LS190 • SN54/74LS191 FUNCTIONAL DESCRIPTION The LS190 is a synchronous Up / Down BCD Decade Counter and the LS191 is a synchronous Up / Down 4-Bit Binary Counter. When counting is to be enabled. since it drives only the first stage. The configuration shown in Figure c avoids ripple delays and their associated restrictions. This operation overrides the counting functions. in some applications. When CE is LOW and TC is HIGH. Each circuit contains four master / slave flip-flops. the U / D signal should only be changed when either CE or the clock is HIGH. However.

2 – 100 35 V µA 2.0 8.5 V V Min 2.25 0.5 0. VIN = 0.4 4.5 4. 74 VOL Output LOW Voltage 74 Input HIGH Current Other Inputs CE Other Inputs CE IIL IOS ICC Input LOW Current Other Inputs CE Short Circuit Current (Note 1) Power Supply Current – 20 0.25 125 70 – 0. VIN = VIH or VIL per Truth Table IOL = 4. 74 54 74 Min 4. IIN = – 18 mA VCC = MIN. VIN = 7.4 – 1.0 25 25 Max 5.8 – 1.5 20 60 0.5 5.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.7 3.0 5.65 3.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.3 – 0. FAST AND LS TTL DATA 5-209 .1 0.5 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = VIL or VIH per Truth Table VCC = MAX. nor for more than 1 second. IOH = MAX.0 mA VCC = VCC MIN.SN54/74LS190 • SN54/74LS191 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.7 V IIH mA VCC = MAX.5 – 0.0 mA IOL = 8.4 V V 2.35 0.0 V mA mA mA VCC = MAX. VIN = 2.75 – 55 0 Typ 5.0 0.

HOLD TIME (th) is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition.0 V Test Conditions DEFINITIONS OF TERMS SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. PL to Output Q Data to Output Q Clock to RC Clock to Output Q Clock to TC U / D to RC U / D to TC CE to RC Min 20 Typ 25 22 33 20 27 13 16 16 24 28 37 30 30 21 22 21 22 33 50 32 40 20 24 24 36 42 52 45 45 33 33 33 33 Max Unit MHz ns ns ns ns ns ns ns ns VCC = 5. FAST AND LS TTL DATA 5-210 . A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOWto-HIGH and still be recognized.0 40 Typ Max Unit ns ns ns ns ns VCC = 5.SN54/74LS190 • SN54/74LS191 AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay. RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs.0 V CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW tW ts th trec Parameter CP Pulse Width PL Pulse Width Data Setup Time Data Hold Time Recovery Time Min 25 35 20 5.

n-Stage Counter Using Ripple Clock DIRECTION CONTROL U/D CE CP RC U/D CE CP RC U/D CE CP RC ENABLE CLOCK Figure b.SN54/74LS190 • SN54/74LS191 DIRECTION CONTROL ENABLE CLOCK U/D CE CP RC U/D CE CP RC U/D CE CP RC Figure a. Synchronous n-Stage Counter Using Ripple Carry / Borrow DIRECTION CONTROL ENABLE U/D CE CP CLOCK TC U/D CE CP TC U/D CE CP TC Figure c. Synchronous n-Stage Counter with Parallel Gated Carry / Borrow FAST AND LS TTL DATA 5-211 .

3 V tPLH 1.3 V 1.3 V trec ts(H) PL 1.3 V tPLH Pn tW PL 1.3 V Q=P * The shaded areas indicate when the input is permitted * to change for predictable output performance Figure 5 Figure 6 U/D tPLH TC tPHL RC 1.3 V tPLH 1.3 V tPHL 1.3 V ts(L) (H-L) only th(L) 1.3 V tPHL Q OR TC 1.3 V NOTE: PL = LOW Qn Figure 3 Figure 4 Pn PL tW CP 1.3 V tPHL 1.3 V 1.3 V Figure 1 Figure 2 Pn tPHL Qn 1.3 V 1.SN54/74LS190 • SN54/74LS191 AC WAVEFORMS 1/f MAX CP tW 1.3 V 1.3 V 1.3 V Figure 7 Figure 8 FAST AND LS TTL DATA 5-212 .3 V tPLH tPHL 1.3 V th(L) 1.3 V 1.3 V Qn Q Q=P 1.3 V CE CE MAY CHANGE CP 1.3 V th(H) ts(L) 1.3 V th(H) ts(H) CE MAY CHANGE 1.3 V tPLH 1.3 V 1.3 V CP OR CE RC 1.

5 (2. 95 mW Typical Dissipation High Speed . 0.L. 0. 5 (2.L. 0.L.5 U. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks.L. 0.6 mA LOW.L.5) U. 40 MHz Typical Count Frequency Synchronous Counting Asynchronous Master Reset and Parallel Load Individual Preset Inputs Cascading Circuitry Internally Provided Input Clamp Diodes Limit High Speed Termination Effects 16 1 N SUFFIX PLASTIC CASE 648-08 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 P0 15 MR 14 TCD 13 TCU 12 PL 11 P2 10 P3 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.25 U. VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-213 .L.5) U. .L.L.25 U.) = 40 µA HIGH/1. 10 U. 5 (2.L. for Commercial (74) b.L. 10 U. Temperature Ranges. thus simplifying multistage counter designs.L. b. for Military (54) and 5 U. 1 TTL Unit Load (U. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. 5 4 CPU CPD PL P0 P1 P2 P3 TCU TCD CPU CPD MR PL Pn Qn TCD TCU Count Up Clock Pulse Input Count Down Clock Pulse Input Asynchronous Master Reset (Clear) Input Asynchronous Parallel Load (Active LOW) Input Parallel Data Inputs Flip-Flop Outputs (Note b) Terminal Count Down (Borrow) Output (Note b) Terminal Count Up (Carry) Output (Note b) 0.5 U.L. 0. Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic. 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC 1 P1 2 Q1 3 Q0 4 CPD 5 CPU 6 Q2 7 Q3 8 GND LOGIC SYMBOL 11 15 1 10 9 PIN NAMES LOADING (Note a) HIGH LOW 0. 10 U. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously.L.L.5 U. 0. 0.25 U.5 U.L.5 U. . Individual preset inputs allow the circuits to be used as programmable counters.L. 12 13 MR Q0 Q1 Q2 Q3 14 3 2 6 7 NOTES: a.5 U.25 U.5) U.PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. The Output LOW drive factor is 2.25 U. . 0. .L. SN54/74LS192 SN54/74LS193 PRESETTABLE BCD / DECADE UP/ DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/ DOWN COUNTER LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 • • • • • • • Low Power .L.L.

SN54/74LS192 • SN54/74LS193 STATE DIAGRAMS LS192 LOGIC EQUATIONS FOR TERMINAL COUNT TCU = Q0 ⋅ Q3 ⋅ CPU TCD = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ CPD 0 1 2 3 4 0 1 2 3 4 15 5 15 5 14 6 14 6 LS193 LOGIC EQUATIONS FOR TERMINAL COUNT 13 7 TCU = Q0 ⋅ Q1⋅ Q2⋅ Q3 ⋅ CPU TCD = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ CPD COUNT UP COUNT DOWN 13 7 12 11 10 9 8 12 11 10 9 8 LS192 LS193 LOGIC DIAGRAMS P0 PL (LOAD) CPU (UP COUNT) 11 5 12 15 1 P1 10 P2 9 P3 TCU (CARRY OUTPUT) SD T Q T SD Q T SD Q T SD Q CD Q CD Q CD Q CD Q 13 CPD (DOWN COUNT) MR (CLEAR) 4 14 3 2 6 7 TCD (BORROW OUTPUT) Q0 Q1 Q2 Q3 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS LS192 FAST AND LS TTL DATA 5-214 .

SN54/74LS192 • SN54/74LS193 LOGIC DIAGRAMS (continued) P0 PL (LOAD) CPU (UP COUNT) 11 5 12 15 1 P1 10 P2 9 P3 TCU (CARRY OUTPUT) SD T Q T SD Q T SD Q T SD Q CD Q CD Q CD Q CD Q 13 CPD (DOWN COUNT) MR (CLEAR) 4 14 3 2 6 7 TCD (BORROW OUTPUT) Q0 Q1 Q2 Q3 LS193 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FAST AND LS TTL DATA 5-215 .

15 for the LS193). If one of the Clock inputs is LOW during and after a reset or load operation. MODE SELECT TABLE MR H L L L L PL X L H H H CPU X X H H CPD X X H H MODE Reset (Asyn. A HIGH signal on the Master Reset input will disable the preset gates. information present on the Parallel Data inputs (P0. the next LOW-to-HIGH transition of that Clock will be interpreted as a legitimate signal and will be counted. the next HIGH-to-LOW transition of the Count Up Clock will cause TCU to go LOW. the circuit will either count by twos or not at all. they can be used as the clock input signals to the next higher order circuit in a multistage counter. thereby causing all state changes to be initiated simultaneously. is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line. Since the TC outputs repeat the clock waveforms. The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally HIGH. When a circuit has reached the maximum count state (9 for the LS192.) Preset (Asyn. the other should be held HIGH. Each flip-flop contains JK feedback from slave to master such that a LOW-to-HIGH transition on its T input causes the slave.SN54/74LS192 • SN54/74LS193 FUNCTIONAL DESCRIPTION The LS192 and LS193 are Asynchronously Presettable Decade and 4-Bit Binary Synchronous UP / DOWN (Reversable) Counters. with the only difference being the count sequences as noted in the State Diagrams. which cannot toggle as long as either Clock input is LOW. override both Clock inputs. Each circuit contains four master/slave flip-flops. individual preset. count up and count down operations.) No Change Count Up Count Down L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care = LOW-to-HIGH Clock Transition FAST AND LS TTL DATA 5-216 . Similarly. A LOW-to-HIGH transition on the Count Up input will advance the count by one. but delayed by two gate delays. Each circuit has an asynchronous parallel load capability permitting the counter to be preset. The operating modes of the LS192 decade counter and the LS193 binary counter are identical. While counting with one clock input. with internal gating and steering logic to provide master reset. thus effectively repeating the Count Up Clock. and latch each Q output in the LOW state. Otherwise. the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. and thus the Q output to change state. When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW. TCU will stay LOW until CPU goes HIGH again. as opposed to ripple counting. depending on the state of the first flip-flop. a similar transition on the Count Down input will decrease the count by one. Synchronous switching. P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs.

SN54/74LS192 • SN54/74LS193
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.4 – 100 34 0.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)
Limits Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency CPU Input to TCU Output CPD Input to TCD Output Clock to Q PL to Q MR Input to Any Output Min 25 Typ 32 17 18 16 15 27 30 24 25 23 26 24 24 24 38 47 40 40 35 Max Unit MHz ns ns ns ns ns VCC = 5.0 V CL = 15 pF Test Conditions

FAST AND LS TTL DATA 5-217

SN54/74LS192 • SN54/74LS193
AC SETUP REQUIREMENTS (TA = 25°C)
Limits Symbol tW ts th trec Parameter Any Pulse Width Data Setup Time Data Hold Time Recovery Time Min 20 20 5.0 40 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.0 Test Conditions

DEFINITIONS OF TERMS SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the PL transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) is defined as the minimum time following the PL transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the PL transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs.

FAST AND LS TTL DATA 5-218

SN54/74LS192 • SN54/74LS193
AC WAVEFORMS

CPU or CPD

1.3 V tPHL

tW tPLH

1.3 V

Q

1.3 V

1.3 V

Figure 1

CPU or CPD tPHL TCU or TCD

1.3 V tPLH 1.3 V

Pn

1.3 V tPHL tPLH

Qn

1.3 V

NOTE: PL = LOW

Figure 2

Figure 3

Pn tw PL 1.3 V tPLH Qn

1.3 V PL tW tPHL 1.3 V Q CPU or CPD tPHL 1.3 V 1.3 V 1.3 V trec

Figure 4

Figure 5

Pn ts(H) PL

1.3 V th(H) ts(L) 1.3 V

1.3 V th(L) MR tW Q=P CPU or CPD tPHL Q 1.3 V 1.3 V trec 1.3 V

Qn

Q=P

* The shaded areas indicate when the input is permitted * to change for predictable output performance

Figure 6

Figure 7

FAST AND LS TTL DATA 5-219

SN54/74LS194A 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
The SN54 / 74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The LS194A is similar in operation to the LS195A Universal Shift Register, with added features of shift left without external connections and hold (do nothing) modes of operation. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all Motorola TTL families.

4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
LOW POWER SCHOTTKY

• • • • •

Typical Shift Frequency of 36 MHz Asynchronous Master Reset Hold (Do Nothing) Mode Fully Synchronous Serial or Parallel Data Transfers Input Clamp Diodes Limit High Speed Termination Effects

J SUFFIX CERAMIC CASE 620-09
16 1

CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 Q0 15 Q1 14 Q2 13 Q3 12 CP 11 S1 10 S0 9
16 1

N SUFFIX PLASTIC CASE 648-08

16 1

D SUFFIX SOIC CASE 751B-03

1 MR

2 DSR

3 P0

4 P1

5 P2

6 P3

7

8

DSL GND

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

PIN NAMES

LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L.

S0, S1 P0 – P3 DSR DSL CP MR Q0 – Q3

Mode Control Inputs Parallel Data Inputs Serial (Shift Right) Data Input Serial (Shift Left) Data Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs (Note b)

0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L.

NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges.

FAST AND LS TTL DATA 5-220

SN54/74LS194A
LOGIC DIAGRAM
10

P0
3

P1
4

P2

5

P3
6

S1
9

S0
2

DSR

7

DSL

VCC = PIN 16 GND = PIN 8 = PIN NUMBERS

S CP

Q0

S CP

Q1

S CP

Q2

S CP

Q3

R CLEAR

R CLEAR

R CLEAR

R CLEAR

CP MR

11 1 15 14 13 12

Q0

Q1

Q2

Q3

FUNCTIONAL DESCRIPTION The Logic Diagram and Truth Table indicate the functional characteristics of the LS194A 4-Bit Bidirectional Shift Register. The LS194A is similar in operation to the Motorola LS195A Universal Shift Register when used in serial or parallel data register transfers. Some of the common features of the two devices are described below: All data and mode control inputs are edge-triggered, responding only to the LOW to HIGH transition of the Clock (CP). The only timing restriction, therefore, is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. The register is fully synchronous, with all operations taking place in less than 15 ns (typical) making the device especially useful for implementing very high speed CPUs, or the memory buffer registers. The four parallel data inputs (P0, P1, P2, P3) are D-type inputs. When both S0 and S1 are HIGH, the data appearing on P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, and
INPUTS MR L H H H H H H S1 X I h h I I h S0 X I I I h h h DSR X X X X I h X DSL X X I h X X X Pn X X X X X X Pn Q0 L q0 q1 q1 L H P0 Q1 L q1 q2 q2 q0 q0 P1

Q3 outputs respectively following the next LOW to HIGH transition of the clock. The asynchronous Master Reset (MR), when LOW, overrides all other input conditions and forces the Q outputs LOW. Special logic features of the LS194A design which increase the range of application are described below: Two mode control inputs (S0, S1) determine the synchronous operation of the device. As shown in the Mode Selection Table, data can be entered and shifted from left to right (shift right, Q0 → Q1, etc.) or right to left (shift left, Q3 → Q2, etc.), or parallel data can be entered loading all four bits of the register simultaneously. When both S0 and S1,are LOW, the existing data is retained in a “do nothing” mode without restricting the HIGH to LOW clock transition. D-type serial data inputs (DSR, DSL) are provided on both the first and last stages to allow multistage shift right or shift left data transfers without interfering with parallel load operation.

MODE SELECT — TRUTH TABLE
OPERATING MODE Reset Hold Shift Left Shift Right Parallel Load OUTPUTS Q2 L q2 q3 q3 q1 q1 P2 Q3 L q3 L H q2 q2 P3

L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.

FAST AND LS TTL DATA 5-221

SN54/74LS194A
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.4 – 100 23 0.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)
Limits Symbol fMAX tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay, Clock to Output Propagation Delay, MR to Output Min 25 Typ 36 14 17 19 22 26 30 Max Unit MHz ns ns VCC = 5.0 V CL = 15 pF F Test Conditions

FAST AND LS TTL DATA 5-222

SN54/74LS194A
AC SETUP REQUIREMENTS (TA = 25°C)
Limits Symbol tW ts ts th trec Parameter Clock or MR Pulse Width Mode Control Setup Time Data Setup Time Hold time, Any Input Recovery Time Min 20 30 20 0 25 Typ Max Unit ns ns ns ns ns VCC = 5.0 V Test Conditions

DEFINITIONS OF TERMS SETUP TIME(ts) —is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs.

AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fmax 1.3 V CLOCK tPHL OUTPUT 1.3 V tW tPLH 1.3 V DSR DSL ts(L) th(L) = 0 P0 P1 P2 P3 ts(L) th(L) = 0 CLOCK OUTPUT* MR 1.3 V ts(H) th(H) = 0 1.3 V 1.3 V ts(H) th(H) = 0 1.3 V S1 S0

(––– IS SHIFT LEFT)

OTHER CONDITIONS: S1 = L, MR = H, S0 = H

Figure 1. Clock to Output Delays Clock Pulse Width and fmax

1.3 V tW trec 1.3 V

OTHER CONDITIONS: MR = H OTHER CONDITIONS: *DSR SET-UP TIME AFFECTS Q0 ONLY OTHER CONDITIONS: DSL SET-UP TIME AFFECTS Q3 ONLY

CLOCK tPHL OUTPUT 1.3 V

Figure 3. Setup (ts) and Hold (th) Time for Serial Data (DSR, DSL) and Parallel Data (P0, P1, P2, P3)

(STABLE TIME) S0 S1 ts th = 0 CLOCK 1.3 V OTHER CONDITIONS: MR = H ts th = 0 1.3 V 1.3 V

OTHER CONDITIONS: S0, S1 = H OTHER CONDITIONS: PO = P1 = P2 = P3 = H

Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time

Figure 4. Setup (ts) and Hold (th) Time for S Input

FAST AND LS TTL DATA 5-223

SN54/74LS195A UNIVERSAL 4-BIT SHIFT REGISTER
The SN54 / 74LS195A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all Motorola TTL products.

UNIVERSAL 4-BIT SHIFT REGISTER
LOW POWER SCHOTTKY

• • • • •

Typical Shift Right Frequency of 39 MHz Asynchronous Master Reset J, K Inputs to First Stage Fully Synchronous Serial or Parallel Data Transfers Input Clamp Diodes Limit High Speed Termination Effects

CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 Q0 15 Q1 14 Q2 13 Q3 12 Q3 11 CP 10 PE 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

J SUFFIX CERAMIC CASE 620-09
16 1

16 1

N SUFFIX PLASTIC CASE 648-08

1 MR

2 J

3 K

4 P0

5 P1

6 P2

7 P3

8 GND
16

PIN NAMES

LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L.

1

D SUFFIX SOIC CASE 751B-03

PE P0 – P3 J K CP MR Q 0 – Q3 Q3

Parallel Enable (Active LOW) Input Parallel Data Inputs First Stage J (Active HIGH) Input First Stage K (Active LOW) Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs (Note b) Complementary Last Stage Output (Note b)

0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L.

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

LOGIC SYMBOL
9 4 5 6 7

NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges.

2 10 3

J CP K

PE P0 P1 P2 P3 Q3 11

MR Q0 Q1 Q2 Q3 1 15 14 13 12 VCC = PIN 16 GND = PIN 8

FAST AND LS TTL DATA 5-224

SN54/74LS195A
LOGIC DIAGRAM
PE J
9 2 3

K
4

P0
5

P1
6

P2
7

P3
1

MR
10

CP

R CD Q0 CP S VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Q0
15

R CD CP S Q0
14

R CD CP S Q2
13

R CD Q3 CP S Q3
12 11

Q0

Q1

Q2

Q3 Q3

FUNCTIONAL DESCRIPTION The Logic Diagram and Truth Table indicate the functional characteristics of the LS195A 4-Bit Shift Register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The LS195A has two primary modes of operation, shift right (Q0 → Q1) and parallel load which are controlled by the state of the Parallel Enable (PE) input. When the PE input is HIGH, serial data enters the first flip-flop Q0 via the J and K inputs and is shifted one bit in the direction Q0 → Q1 → Q2 → Q3 following each LOW to HIGH clock transition. The JK inputs provide the flexibility of the JK type input for special applications, and the simple D type input for general applications by tying the two pins together. When the PE input is LOW, the LS195A appears as four common clocked D flip-flops. The data on the parallel inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1, Q2, Q3 outputs following the LOW to HIGH clock transition. Shift left operations (Q3 → Q2) can be achieved by tying the Qn Outputs to the Pn–1 inputs and holding the PE input LOW. All serial and parallel data transfers are synchronous, occurring after each LOW to HIGH clock transition. Since the LS195A utilizes edge-triggering, there is no restriction on the activity of the J, K, Pn and PE inputs for logic operation — except for the set-up and release time requirements. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW, independent of any other input condition.

MODE SELECT — TRUTH TABLE
OPERATING MODES Asynchronous Reset Shift, Set First Stage Shift, Reset First Shift, Toggle First Stage Shift, Retain First Stage Parallel Load INPUTS MR L H H H H H PE X h h h h I J X h I h I X K X h I I h X Pn X X X X X pn Q0 L H L q0 q0 p0 Q1 L q0 q0 q0 q0 p1 OUTPUTS Q2 L q1 q1 q1 q1 p2 Q3 L q2 q2 q2 q2 p3 Q3 H q2 q2 q2 q2 p3

L = LOW voltage levels H = HIGH voltage levels X = Don’t Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition. h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition. pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.

FAST AND LS TTL DATA 5-225

SN54/74LS195A
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.4 – 100 21 0.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)
Limits Symbol fMAX tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay, Clock to Output Propagation Delay, MR to Output Min 30 Typ 39 14 17 19 22 26 30 Max Unit MHz ns ns VCC = 5.0 V CL = 15 pF F Test Conditions

AC SETUP REQUIREMENTS (TA = 25°C)
Limits Symbol tW tW ts ts trec trel th Parameter CP Clock Pulse Width MR Pulse Width PE Setup Time Data Setup Time Recovery Time PE Release Time Data Hold Time 0 Min 16 12 25 15 25 10 Typ Max Unit ns ns ns ns ns ns ns VCC = 5.0 V Test Conditions

FAST AND LS TTL DATA 5-226

SN54/74LS195A
DEFINITIONS OF TERMS SETUP TIME(ts) —is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs.

AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.

tW 1.3 V CLOCK tPHL OUTPUT 1.3 V CONDITIONS: J = PE = MR = H K=L 1.3 V tPLH 1.3 V

PE 1.3 V ts(L) th(L) = 0 P0 P1 P2 P3 ts(L) th(L) = 0 CLOCK OUTPUT* ts(H) th(H) = 0 1.3 V 1.3 V ts(H) th(H) = 0

J&K

Figure 1. Clock to Output Delays and Clock Pulse Width

CONDITIONS: MR = H *J AND K SET–UP TIME AFFECTS Q0 ONLY

MR

tW 1.3 V 1.3 V trec

Figure 3. Setup (ts) and Hold (th) Time for Serial Data (J & K) and Parallel Data (P0, P1, P2, P3)

CLOCK tPHL OUTPUT 1.3 V

1.3 V LOAD PARALLEL DATA 1.3 V 1.3 V ts(L) trel 1.3 V ts(H) trel 1.3 V LOAD SERIAL DATA SHIFT RIGHT

PE

CONDITIONS: PE = L PO = P1 = P2 = P3 = H

CLOCK

Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time

OUTPUT

Qn = Pn

Qn* = Qn–1

CONDITIONS: MR = H *Q0 STATE WILL BE DETERMINED BY J AND K INPUTS .

Figure 4. Setup (ts) and Hold (th) Time for PE Input

FAST AND LS TTL DATA 5-227

4-STAGE PRESETTABLE RIPPLE COUNTERS
The SN54/74LS196 decade counter is partitioned into divide-by-two and divide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1) sequence or in a bi-quinary mode producing a 50% duty cycle output. The SN54/74LS197 contains divide-by-two and divide-by-eight sections which can be combined to form a modulo-16 binary counter. Low Power Schottky technology is used to achieve typical count rates of 70 MHz and power dissipation of only 80 mW. Both circuit types have a Master Reset (MR) input which overrides all other inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL) overrides clocked operations and asynchronously loads the data on the Parallel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits usable as programmable counters. The circuits can also be used as 4-bit latches, loading data from the Parallel Data inputs when PL is LOW and storing the data when PL is HIGH.

SN54/74LS196 SN54/74LS197

4-STAGE PRESETTABLE RIPPLE COUNTERS
LOW POWER SCHOTTKY

J SUFFIX CERAMIC CASE 632-08
14 1

• • • • • • •

Low Power Consumption — Typically 80 mW High Counting Rates — Typically 70 MHz Choice of Counting Modes — BCD, Bi-Quinary, Binary Asynchronous Presettable Asynchronous Master Reset Easy Multistage Cascading Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 14 MR 13 Q3 12 P3 11 P1 10 Q1 9 CP0 8
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

14 1

N SUFFIX PLASTIC CASE 646-06

14 1

D SUFFIX SOIC CASE 751A-02

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

1 PL

2 Q2

3 P2

4 P0

5 Q0

6 CP1

7 GND LOADING (Note a) HIGH LOW 1.5 U.L. 1.75 U.L. 0.8 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 8 6

PIN NAMES

LOGIC SYMBOL
1 PL 4 10 3 11 P0 P1 P2 P3

CP0 CP1 (LS196) CP1 (LS197) MR PL P0–P3 Q0–Q3

Clock (Active LOW Going Edge) Input to Divide-by-Two Section Clock (Active LOW Going Edge) Input to Divide-by-Five Section Clock (Active LOW Going Edge) Input to Divide-by-Eight Section Master Reset (Active LOW) Input Parallel Load (Active LOW) Input Data Inputs Outputs (Notes b, c)

1.0 U.L. 2.0 U.L. 1.0 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 10 U.L.

CP0

CP1 MR 13

Q0 Q1 Q2 Q3 5 9 2 12

VCC = PIN 14 GND = PIN 7

NOTES: a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. c. In addition to loading shown, Q0 can also drive CP1.

FAST AND LS TTL DATA 5-228

SN54/74LS196 • SN54/74LS197
LOGIC DIAGRAM

P0
13 4

P1
10

P2
3

P3
11

MR PL
1

8

J SD Q

J SD Q

J SD Q

J SD Q

CP0
K CD Q
6

K CD Q

K CD Q

K CD Q

CP1 Q0

5

9

2

12

Q1

Q2

Q3

LS196

P0
13 4

P1
10

P2
3

P3
11

MR PL
1

8

J SD Q

J SD Q

J SD Q

J SD Q

CP0
K CD Q
6

K CD Q

K CD Q

K CD Q

CP1 Q0

5

9

2

12

Q1

Q2

Q3

LS197

VCC = PIN 14 GND = PIN 7 = PIN NUMBERS

FAST AND LS TTL DATA 5-229

SN54/74LS196 • SN54/74LS197
FUNCTIONAL DESCRIPTION The LS196 and LS197 are asynchronously presettable decade and binary ripple counters. The LS196 Decade Counter is partitioned into divide-by-two and divide-by-five sections while the LS197 is partitioned into divide-by-two and divideby-eight sections, with all sections having a separate Clock input. In the counting modes, state changes are initiated by the HIGH to LOW transition of the clock signals. State changes of the Q outputs, however, do not occur simultaneously because of the internal ripple delays. When using external logic to decode the Q outputs, designers should bear in mind that the unequal delays can lead to decoding spikes and thus a decoded signal should not be used as a clock or strobe. The CP0 input serves the Q0 flip-flop in both circuit types while the CP1 input serves the divide-by-five or divide-by-eight section. The Q0 output is designed and specified to drive the rated fan-out plus the CP1 input. With the input frequency connected to CP0 and Q0 driving CP1, the LS197 forms a straightforward module-16 counter, with Q0 the least significant output and Q3 the most significant output. The LS196 Decade Counter can be connected up to operate in two different count sequences, as indicated in the tables of Figure 2. With the input frequency connected to CP0 and with Q0 driving CP1, the circuit counts in the BCD (8, 4, 2, 1) sequence. With the input frequency connected to CP1 and Q3 driving CP0, Q0 becomes the low frequency output and has a 50% duty cycle waveform. Note that the maximum counting rate is reduced in the latter (bi-quinary) configuration because of the interstage gating delay within the divide-by-five section. The LS196 and LS197 have an asynchronous active LOW Master Reset input (MR) which overrides all other inputs and forces all outputs LOW. The counters are also asynchronously presettable. A LOW on the Parallel Load input (PL) overrides the clock inputs and loads the data from Parallel Data (P0 – P3) inputs into the flip-flops. While PL is LOW, the counters act as transparent latches and any change in the Pn inputs will be reflected in the outputs.

Figure 2. LS196 COUNT SEQUENCES
DECADE (NOTE 1) COUNT 0 1 2 3 4 5 6 7 8 9 Q3 L L L L L L L L H H Q2 L L L L H H H H L L Q1 L L H H L L H H L L Q0 L H L H L H L H L H COUNT 0 1 2 3 4 5 6 7 8 9 Q0 L L L L L H H H H H BI-QUINARY (NOTE 2) Q3 L L L L H L L L L H Q2 L L H H L L L H H L Q1 L H L H L L H L H L

NOTES: 1. Signal applied to CP0, Q0 connected to CP1. 2. Signal applied to CP1, Q3 connected to CP0.

MODE SELECT TABLE
INPUTS RESPONSE MR L H H PL X L H CP X X Reset (Clear) Parallel Load Count

H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care = HIGH to Low Clock Transition

FAST AND LS TTL DATA 5-230

VIN = VIL or VIH per Truth Table µA VCC = MAX. 74 54 74 Min 4. PL MR. nor for more than 1 second.7 V IIH mA VCC = MAX.SN54/74LS196 • SN54/74LS197 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. VIN = 0.8 – 1.1 0.5 4. IIN = – 18 mA VCC = MIN.25 0.0 8.4 – 2.0 mA IOL = 8.4 – 0. 74 VOL Output LOW Voltage 74 Input HIGH Current Data.0 5. FAST AND LS TTL DATA 5-231 . PL MR CP0 CP1 (LS196) CP1 (LS197) Short Circuit Current (Note 1) Power Supply Current – 20 0. IOH = MAX. CP0 (LS196) MR.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.0 25 25 Max 5.4 V V 2. VIN = 2. CP0. VIN = 7.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.4 V IOS ICC mA mA VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. CP0.2 0.65 3.75 – 55 0 Typ 5. PL MR.4 4. CP1 (LS197) CP1 (LS196) Input LOW Current Data.35 0.4 – 0. VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN.5 V V Min 2.5 0.2 0.3 – 100 27 V 2.0 0.25 125 70 – 0.5 – 0.5 0.8 – 2.5 5.0 V IIL mA VCC = MAX.8 – 1. CP0 (LS196) MR.5 20 40 40 80 0.7 3. CP1 (LS197) CP1 (LS196) Data.

SN54/74LS196 • SN54/74LS197 AC CHARACTERISTICS (TA = 25°C) Limits LS196 Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency CP0 Input to Q0 Output CP1 Input to Q1 Output CP1 Input to Q2 Output CP1 Input to Q3 Output Data to Output PL Input to Any Output MR Input to Any Output Min 30 Typ 40 8.0 V CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits LS196 Symbol tW tW tW tW ts ts th th trec Parameter CP0 Pulse Width CP1 Pulse Width PL Pulse Width MR Pulse Width Data Input Setup Time — HIGH Data Input Setup Time — LOW Data Hold Time — HIGH Data Hold Time — LOW Recovery Time Min 20 30 20 15 10 15 10 10 30 Typ Max Min 20 30 20 15 10 15 10 10 30 LS197 Typ Max Unit ns ns ns ns ns ns ns ns ns VCC = 5.0 14 12 23 34 42 55 63 18 29 26 30 34 15 21 19 35 51 63 78 95 27 44 39 45 51 Max Unit MHz ns ns ns ns ns ns ns VCC = 5. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH to LOW in order to recognize and transfer LOW Data to the Q outputs. FAST AND LS TTL DATA 5-232 .0 V Test Conditions DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from HIGH to LOW in order to be recognized and transferred to the outputs. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from HIGH to LOW and still be recognized. HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH to LOW that the logic level must be maintained at the input in order to ensure continued recognition.0 13 16 22 38 41 12 30 20 29 27 30 34 15 20 24 33 57 62 18 45 30 44 41 45 51 Max Min 30 LS197 Typ 40 8.

3 V tPHL 1.3 V Qn* Q=P 1.3 V 1.3 V th(L) 1.3 V Figure 2 Figure 3 Pn* PL OR MR tW CP tPHL Q 1.3 V 1.3 V tPLH Pn tW PL 1.3 V Q 1.3 V tW(H) tPLH 1.3 V th(H) ts(L) 1.3 V Figure 1 Pn tPHL Qn 1.SN54/74LS196 • SN54/74LS197 AC WAVEFORMS CP 1.3 V Q=P * The shaded areas indicate when the input is permitted * to change for predictable output performance Figure 4 Figure 5 FAST AND LS TTL DATA 5-233 .3 V NOTE: PL = LOW Qn 1.3 V trec PL ts(H) 1.3 V 1.3 V tPLH tPHL 1.

pulse stability will only be limited by the accuracy of external timing components. A high immunity to VCC noise is also provided by internal latching circuitry. The range of jitter-free pulse widths is extended if VCC is 5. where tW is in ns if Cext is in pF and Rext is in kΩ . and 2.0 kΩ and Cext = 0. Output rise and fall times are independent of pulse length. SN54/74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 • SN54LS221 and SN74LS221 is a Dual Highly Stable One-Shot • Overriding Clear Terminates Output Pulse • Pin Out is Identical to SN54 / 74LS123 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC (TOP VIEW) VCC 16 1 Rext/ 1 Cext Cext 15 14 Q Q CLR 1Q 13 2Q 12 2 CLR 11 2B 10 2A 9 VCC CLR Q Q 4 1Q 5 2Q 6 2 Cext 8 7 2 Rext/ GND Cext Cext Rext + R/C L X X H H *° FUNCTION TABLE (EACH MONOSTABLE) INPUTS CLEAR A X H X L ± L B X X L ° H H MAXIMUM OUTPUT PULSE LENGTH 49 s 70 s OUTPUTS Q L L L Q H H H 1 1A 2 1B 3 1 CLR *See operational notes — Pulse Trigger Modes TYPE SN54LS221 SN74LS221 positive logic: Low input to clear resets Q low and positive logic: Q high regardless of dc levels at A positive logic: or B inputs. The output pulses can be terminated by the overriding clear. Output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. If pulse cutoff is not critical.4 kΩ may be used.7 Cext Rext. Once triggered. Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. capacitance up to 1000 µF and resistance as low as 1. Pulse width is defined by the relationship: tw(out) = CextRext ln 2. and greater than one decade of timing resistance (2.0 V and 25°C temperature. In most applications.0 to 70 kΩ for the SN54LS221. TYPICAL POWER DISSIPATION 23 mW 23 mW FAST AND LS TTL DATA 5-234 . Input pulse width may be of any duration relative to the output pulse width. Jitter-free operation is maintained over the full temperature and VCC ranges for greater than six decades of timing capacitance (10 pF to 10 µF).0 ≈ 0. providing the circuit with excellent noise immunity. Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse.DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS Each multivibrator of the LS221 features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. the outputs are independent of further transitions of the inputs and are a function of the timing components. Schmitt-trigger input circuitry for B input allows jitter-free triggering for inputs as slow as 1 volt / second. With Rext = 2.0 to 100 kΩ for the SN74LS221). a typical output pulse of 30 nanoseconds is achieved.

Output pulse widths varies typically no more than ±0. rises above 50%.5 V) is achieved by internal latching circuitry. this causes the output pulse width to vary in length. If the Clear pin is routinely being used to trigger the output pulse. the A input must be set high OR the B input must be set low to allow Clear to be used as a trigger. irregardless of the previous output state and other input states. once the Q output goes low. However. Pulse triggering occurs at a voltage level and is. it cannot be retriggered by other inputs. non-retriggerable. Once triggered. Rext and Cext. independent of the input slew rate. the A or B inputs must be toggled as described above before and between each Clear trigger event. Although the LS221 is pin-for-pin compatible with the LS123. High immunity to VCC noise (typically 1. or jitter.5% from device to device. defined as being 100 • tW where T is the T input period of the input pulse. This pulse width is essentially independent of VCC and temperature variations. The SN54LS/74LS221 is a dual. To reduce jitter to a minimum. Inhibit Mode: If either the A input is high or the B input is low. Although all three inputs have this Schmitt-trigger effect. Clear Mode: If the clear input is held low. jitter is not appreciable until the duty cycle approaches 90%. monolithic. standard VCC bypassing is strongly recommended. as long as the output remains high. Q will go low for a corresponding length of time. as long as Rext and Cext are within their minimum and maximum valves and the duty cycle is less than 50%. high-stability one shot. The LS123 is retriggerable so that the output is dependent upon the input transitions once it is high. all input transitions (except overriding Clear) are ignored. but special logic preconditioning on the A or B inputs must be done as follows: Following any output triggering action using the A or B inputs. only the B input should be used for very long transition triggers (≥1. the Q output is low. the output pulse width is determined by tW = RextCextIn2.SN54/74LS221 OPERATIONAL NOTES Once in the pulse trigger mode. Inputs should then be set up per the truth table (without triggering the output) to allow Clear to be used a trigger for the output pulse. tW can be varied over 9 decades of timing by proper selection of the external timing components. With Rext = 100K. it should be remembered that they are not functionally identical. the output pulse width will become shorter. Overriding Clear Mode: If the Q output is high. this cannot be done on the LS221. Pulse Trigger Mode: A transition of the A or B inputs as indicated in the functional truth table will trigger the Q output to go high for a duration determined by the tW equation described above. The Clear input may also be used to trigger an output pulse. therefore. If the duty cycle. The LS221 has four basic modes of operation. The output pulse width.0 µV/s). (Jitter is independent of Cext). it may be forced low by bringing the clear input low. However. Also note that it is recommended to externally ground the LS123 Cext pin. This is not the case for the LS221. If the duty cycle varies between low and high valves. FAST AND LS TTL DATA 5-235 . Rext should be as large as possible.

7 0.5 V V VCC = MIN. IIN = – 18 mA VCC = MIN VCC = MIN VCC = MIN Test Conditions VCC = MIN VCC = MAX. FAST AND LS TTL DATA 5-236 . 74 54 74 Min 4.7 0. IOH = MAX MIN IOL = 4.0 mA 54 74 0.0 25 25 Max 5.7 3.4 V V 2.9 0.1 Input LOW Current Input A Input B Clear Short Circuit Current (Note 1) Power Supply Current Quiescent Triggered – 20 4.8 – 1.0 0.8 – 100 11 27 0.0 0. VIN = 2.0 8.75 – 55 0 Typ 5.0 5.8 – 0. nor for more than 1 second.0 mA IOL = 8.0 0.7 V VCC = MAX.5 3.4 V IOS ICC mA VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VT+ VT T– VT+ VT T– VIH VIL VIK VOH Parameter Positive-Going Threshold Voltage at C Input Negative-Going Threshold g g Voltage at C Input Positive-Going Threshold Voltage at B Input Negative-Going Threshold g g Voltage at B Input Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Voltage 54 Output HIGH Voltage 74 54 VOL Output LOW Voltage 74 Input HIGH Current 0.8 2. VIN = 7.4 4.5 5.25 0.5 4.SN54/74LS221 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 20 IIH V µA mA 2. VIN = 0.4 – 0.4 0.0 Unit V V V V V V V VCC = MIN Guaranteed Input HIGH Voltage for A Input Guaranteed Input LOW Voltage for g A Input VCC = MIN.4 0.7 19 – 0.7 Min Typ 1.25 125 70 – 0.8 1.35 0.0 Max 2.9 2.8 0.7 V 54 74 0.0 V IIL mA VCC = MAX.

0 kΩ RT = MAX Rext 50 90 % 1.0 V. B Logic Input. Rext = 10 kΩ Cext = 80 pF Rext = 2.4 70 kΩ ns ns 1. t t 20 Unit Test Conditions AC SETUP REQUIREMENTS (VCC = 5. TA = 25°C) Symbol tPLH From (Input) A B A tPHL tPHL tPLH B Clear Clear To (Output) Q Q Q Q Q Q 70 20 tW(out) W( t) A or B Q or Q 600 6. Rext = 10 kΩ Cext = 1.0 V.0 670 6. Rext = 2.4 0 100 1000 µF A or B.SN54/74LS221 AC CHARACTERISTICS (VCC = 5. tW (clear) 40 40 15 1.0 µF.0 Ω Cext = 0.0 V/s V/µs Min Typ Max Unit FAST AND LS TTL DATA 5-237 .0 1.0 Ω pF. tW(in) Clear. See Figure 1 Cext = 80 pF.9 750 7. TA = 25°C) Limits Symbol Parameter Rate of Rise or Fall of Input Pulse dv/dt Schmitt.0 kΩ Cext = 100 pF. Rext = 2. A Input Pulse Width tW ts Rext t Cext Clear-Inactive-State Setup Time 54 External Timing Resistance 74 External Timing Capacitance Output Duty Cycle RT = 2.5 ms Limits Min Typ 45 35 50 40 35 44 120 47 Max 70 ns 55 80 ns 65 55 65 150 70 ns ns ns CL = 15 pF.

THEN CLEAR — CONDITION 2 0V 1. TRIGGER FROM B.3 V 0V 3V tPHL 0V VOH VOL VOH VOL tPLH 3V B INPUT ≥ 60 ns CLEAR Q OUTPUT A INPUT IS LOW. THEN CLEAR — CONDITION 1 3V 1. THEN TRIGGER FROM B B INPUT ≥ 50 ns CLEAR ≥ 50 ns 1. TRIGGER FROM B.SN54/74LS221 AC WAVEFORMS tW(in) B INPUT ≥60 ns CLEAR tPLH Q OUTPUT tPHL Q OUTPUT A INPUT IS LOW.3 V 3V 0V 3V 0V Q OUTPUT A INPUT IS LOW. TRIGGERING FROM POSITIVE TRANSITION OF CLEAR VOH VOL Figure 1 FAST AND LS TTL DATA 5-238 .3 V 3V 0V VOH VOL B INPUT ≥ 50 ns CLEAR TRIGGERED Q OUTPUT NOT TRIGGERED A INPUT IS LOW. tW(out) ≥0 ts 3V 0V 3V 0V VOH VOL CLEAR OVERRIDING B.

241 and 244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers.OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS The SN54 / 74LS240. clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. SN54/74LS240 SN54/74LS241 SN54/74LS244 OCTAL BUFFER / LINE DRIVER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY • Hysteresis at Inputs to Improve Noise Margins • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Input Clamp Diodes Limit High-Speed Termination Effects LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) SN54 / 74LS240 VCC 2G 20 19 1Y1 18 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 17 16 15 14 13 12 11 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 1 1G 2 1A1 3 4 5 2Y4 1A2 2Y3 6 8 9 10 7 1A3 2Y2 1A4 2Y1 GND 20 1 SN54 / 74LS241 VCC 2G 20 19 1Y1 18 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 17 16 15 14 13 12 11 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC 1 1G 2 1A1 3 4 5 2Y4 1A2 2Y3 6 8 9 10 7 1A3 2Y2 1A4 2Y1 GND SN54 / 74LS244 VCC 2G 20 19 1Y1 18 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 17 16 15 14 13 12 11 1 1G 2 1A1 3 4 5 2Y4 1A2 2Y3 8 9 10 6 7 1A3 2Y2 1A4 2Y1 GND FAST AND LS TTL DATA 5-239 .

0 5. 2G L L H D L H X H L (Z) 1G. 74 54 74 IOL Output Current — Low 54 74 Min 4.5 5.75 – 55 0 Typ 5.0 – 12 – 15 12 24 Unit V °C mA mA mA FAST AND LS TTL DATA 5-240 .25 125 70 – 3.0 25 25 Max 5. 2G L L H D L H X L H (Z) SN54 / 74LS244 INPUTS OUTPUT SN54 / 74LS241 INPUTS 1G L L H D L H X OUTPUT 2G L H (Z) H H L D L H X L H (Z) INPUTS OUTPUT H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance GUARANTEED OPERATING RANGES Symbol VCC TA IOH Supply Voltage Operating Ambient Temperature Range Output Current — High Parameter 54 74 54 74 54.SN54/74LS240 • SN54/74LS241 • SN54/74LS244 TRUTH TABLES SN54 / 74LS240 INPUTS OUTPUT 1G.5 4.

2 0.0 0. VIN = 7.4 0.0 12 12 12 15 20 15 10 Max 14 18 18 18 23 30 25 18 Unit ns ns ns ns ns ns CL = 5.4 V VCC = MAX Note 1: Not more than one output should be shorted at a time.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPLZ tPHZ Parameter Propagation Delay. Data to Output LS240 Propagation Delay.4 – 1.4 V VCC = MAX. 74 Output HIGH Voltage 54.25 0. VCC = 5. 74 VOL IOZH IOZL IIH IIL IOS Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0. Data to Output LS241 / 244 Output Enable Time to HIGH Level Output Enable Time to LOW Level Output Disable Time from LOW Level Output Disable Time from HIGH Level Min Typ 9.4 – 0.7 V VCC = MAX. Output HIGH Total.0 V VCC = MAX.8 V V V Min 2.5 20 – 20 20 V µA µA µA mA mA mA 2. VIN = 0. AC CHARACTERISTICS (TA = 25°C.2 – 225 27 44 46 50 54 mA A VCC = MAX 0. VIN = 2. 74 54. VOUT = 2.65 3.35 0.5 0.0 mA VCC = MIN. nor for more than 1 second.1 Input LOW Current Output Short Circuit Current (Note 1) Power Supply Current Total.SN54/74LS240 • SN54/74LS241 • SN54/74LS244 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VT+–VT– VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Hysteresis Input Clamp Diode Voltage 54.0 pF. IIN = – 18 mA VCC = MIN. IOH = – 3. IOH = MAX IOL = 12 mA IOL = 24 mA VCC = VCC MIN.7 V VCC = MAX. VIN = VIL or VIH per Truth Table VCC = MAX.0 0.4 V V 2. RL = 667 Ω Test Conditions FAST AND LS TTL DATA 5-241 . RL = 667 Ω CL = 45 pF.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN VCC = MIN. VOUT = 0. Output LOW ICC Total at HIGH Z LS240 LS241/244 LS240 LS241/244 – 40 – 0.

3 V 1.3 V tPZL 1.3 V VOL 0.3 V 1.3 V VE VOUT tPZH 1.3 V tPHL 1.5 V SYMBOL tPZH tPZL tPLZ tPHZ SWITCH POSITIONS SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed Figure 3 Figure 5 VE 1.3 V CL* 5 kΩ SW2 Figure 2 VE VE VOUT 1.3 V tPLH 1.3 V 1.SN54/74LS240 • SN54/74LS241 • SN54/74LS244 AC WAVEFORMS VIN 1.3 V Figure 1 TO OUTPUT UNDER TEST VIN 1.3 V tPHL VOUT 1.3 V 0.3 V tPHZ ≥VOH ≈ 1.5 V Figure 4 FAST AND LS TTL DATA 5-242 .3 V tPLZ ≈ 1.3 V VCC RL SW1 VOUT 1.3 V tPLH 1.

SN54/74LS242 SN54/74LS243 • Hysteresis at Inputs to Improve Noise Immunity • 2-Way Asynchronous Data Bus Communication • Input Clamp Diodes Limit High-Speed Termination Effects LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) SN54 / 74LS242 VCC 14 GBA 13 NC 12 1B 11 2B 10 3B 9 4B 8 QUAD BUS TRANSCEIVER LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 14 1 1 GBA 2 NC 3 1A 4 2A 5 3A 6 4A 7 GND 14 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 N SUFFIX PLASTIC CASE 646-06 SN54 / 74LS243 VCC 14 GBA 13 NC 12 1B 11 2B 10 3B 9 4B 8 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION 1 GBA 2 NC 3 1A 4 2A 5 3A 6 4A 7 GND SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC TRUTH TABLES SN54 / 74LS242 INPUTS OUTPUT GAB L L H D L H X H L (Z) GAB L H H D X L H (Z) H L INPUTS OUTPUT GAB L L H D L H X L H (Z) INPUTS OUTPUT GAB L H H D X L H (Z) H L SN54/74LS243 INPUTS OUTPUT H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance FAST AND LS TTL DATA 5-243 .QUAD BUS TRANSCEIVER The SN54 / 74LS242 and SN54 / 74LS243 are Quad Bus Transmitters / Receivers designed for 4-line asynchronous 2-way data communications between data buses.

4 – 1. 74 VOL IOZH IOZL Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW D.2 0. VIN = 2.7 V VCC = MAX.35 0.1 – 0.4 2. VOUT = 2.5 4.7 V 0. 74 54. E2 D Input IIL IOS Input LOW Current Output Short Circuit Current (Note 1) Power Supply Current Total. E1.4 – 0.75 – 55 0 Typ 5.1 0.0 0.8 0.0 5. VIN = 5. Output HIGH ICC Total.5 5.5 V V V V V V µA µA µA mA mA mA mA VCC = MAX. VIN = VIL or VIH per Truth Table 0.4 0.4 V VCC = MAX. 74 Output HIGH Voltage 54. VIN = 0.4 V VCC = MAX VCC = MAX FAST AND LS TTL DATA 5-244 .25 0. IOH = MAX IOL = 12 mA IOL = 24 mA VCC = VCC MIN.65 2. IIN = – 18 mA VCC = MIN.0 V VCC = MAX.0 25 25 Max 5.0 Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN VCC = MIN. Output LOW LS242 Total at HIGH Z LS243 54 Note 1: Not more than one output should be shorted at a time. E2 IIH Input HIGH Current E1.7 V VCC = MAX. VOUT = 0.25 125 70 – 3. nor for more than 1 second.2 – 40 – 225 38 50 50 mA 3.5 V VCC = MAX. Min 2.SN54/74LS242 • SN54/74LS243 GUARANTEED OPERATING RANGES Symbol VCC TA IOH Supply Voltage Operating Ambient Temperature Range Output Current — High Parameter 54 74 54 74 54. IOH = – 3.5 40 – 200 20 0.0 – 12 – 15 12 24 Unit V °C mA mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VT+–VT– VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Hysteresis Input Clamp Diode Voltage 54. VIN = 7.0 mA VCC = MIN. 74 54 74 IOL Output Current — Low 54 74 Min 4.

3 V SW1 VCC RL VOUT 1.3 V Figure 1 TO OUTPUT UNDER TEST VIN 1.3 V tPLZ ≈ 1.3 V VOL SYMBOL tPZH tPZL tPLZ tPHZ SWITCH POSITIONS SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed 0.3 V tPHZ ≥VOH ≈ 1.5 V Figure 5 Figure 4 FAST AND LS TTL DATA 5-245 .0 pF.3 V 1.0 V) Limits LS242 Symbol tPLH tPHL tPZH tPZL tPLZ tPHZ Parameter Propagation Delay. RL = 667 Ω CL = 45 pF.3 V tPLH 1.3 V tPHL VOUT 1. VCC = 5.3 V tPZL 1. Data to Output Output Enable Time to HIGH Level Output Enable Time to LOW Level Output Disable Time from LOW Level Output Disable Time from HIGH Level Min Typ 9.3 V VE VOUT tPZH 1.3 V 0. RL = 667 Ω Test Conditions AC WAVEFORMS VIN 1.3 V 1. F.SN54/74LS242 • SN54/74LS243 AC CHARACTERISTICS (TA = 25°C.3 V 1.5 V Figure 3 VE 1.3 V tPHL 1.0 12 15 20 15 10 Max 14 18 23 30 25 18 Min LS243 Typ 12 12 15 20 15 10 Max 18 18 23 30 25 18 Unit ns ns ns ns ns CL = 5.3 V tPLH 1.3 V 5 kΩ CL* SW2 Figure 2 VE VE VOUT 1.

25 125 70 – 3.5 4.0 5.5 5.75 – 55 0 Typ 5. OCTAL BUS TRANSCEIVER LOW POWER SCHOTTKY • • • • Hysteresis Inputs to Improve Noise Immunity 2-Way Asynchronous Data Bus Communication Input Diodes Limit High-Speed Termination Effects ESD > 3500 Volts LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) VCC 20 E 19 B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 12 B8 11 20 1 J SUFFIX CERAMIC CASE 732-03 1 DIR 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 10 GND 20 1 N SUFFIX PLASTIC CASE 738-03 TRUTH TABLE INPUTS OUTPUT E L L H DIR L H X Bus B Data to Bus A Bus A Data to Bus B Isolation 20 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial GUARANTEED OPERATING RANGES Symbol VCC TA IOH Supply Voltage Operating Ambient Temperature Range Output Current — High Parameter 54 74 54 74 54.SN54/74LS245 OCTAL BUS TRANSCEIVER The SN54 / 74LS245 is an Octal Bus Transmitter/Receiver designed for 8-line asynchronous 2-way data communication between data buses. Direction Input (DR) controls transmission of Data from bus A to bus B or bus B to bus A depending upon its logic level.0 – 12 – 15 12 24 Unit V °C mA mA mA FAST AND LS TTL DATA 5-246 .0 25 25 Max 5. The Enable input (E) can be used to isolate the buses. 74 54 74 IOL Output Current — Low 54 74 Min 4.

7 V VCC = MAX. nor for more than 1 second.0 25 27 15 15 Max 12 12 40 40 25 25 Unit ns ns ns ns ns CL = 5.7 V VCC = MAX. Output HIGH ICC Total.0 pF. VIN = 7.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN VCC = MIN. 74 VOL IOZH IOZL Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW A or B.5 20 – 200 20 0.1 0. VIN = 0. Output LOW Total at HIGH Z – 40 0. 74 54.2 0. F. VIN = VIL or VIH per Truth Table VCC = MAX.4 V VCC = MAX. IIN = – 18 mA VCC = MIN.1 – 0. AC CHARACTERISTICS (TA = 25°C.4 – 0.0 0. VIN = 5.0 8.0 mA VCC = MIN.5 V VCC = MAX.4 V V 2.4 – 1.65 3.4 V VCC = MAX Note 1: Not more than one output should be shorted at a time.SN54/74LS245 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VT+–VT– VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Hysteresis Input Clamp Diode Voltage 54.35 0.25 0.0 V VCC = MAX. RL = 667 Ω CL = 45 pF.0 V. TRISE / TFALL ≤ 6.2 – 225 70 90 95 A mA VCC = MAX V µA µA µA mA mA mA mA 2. IOH = MAX IOL = 12 mA IOL = 24 mA VCC = VCC MIN. Data to Output Output Enable Time to HIGH Level Output Enable Time to LOW Level Output Disable Time from LOW Level Output Disable Time from HIGH Level Min Typ 8.0 ns) Limits Symbol tPLH tPHL tPZH tPZL tPLZ tPHZ Parameter Propagation Delay.8 V V V Min 2.5 0.0 0. RL = 667 Ω Test Conditions FAST AND LS TTL DATA 5-247 .4 0. VCC = 5. VIN = 2. DR or E IIH Input HIGH Current DR or E A or B IIL IOS Input LOW Current Output Short Circuit Current (Note 1) Power Supply Current Total. VOUT = 2. VOUT = 0. 74 Output HIGH Voltage 54. IOH = – 3.

except the 6 and 9 are identical between the LS247. The LS249 is a 16-pin version of the 14-pin LS49 and includes full functional capability for lamp test and ripple blanking which was not available in the LS49. The LS247 has active-low outputs for direct drive of indicators. Segment identification and resultant displays are shown below. 248. Display pattern for BCD input counts above 9 are unique symbols to authenticate input conditions. LS247 SN54/74LS247 SN54/74LS248 SN54/74LS249 BCD-TO-SEVEN-SEGMENT DECODERS/ DRIVERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 • Open-Collector Outputs Drive Indicators Directly • Lamp-Test Provision • Leading / Trailing Zero Suppression LS248 • Internal Pull-Ups Eliminate Need for External Resistors • Lamp-Test Provision • Leading / Trailing Zero Suppression LS249 • Open-Collector Outputs • Lamp-Test Provision • Leading / Trailing Zero Suppression 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS a f e d g b c SEGMENT IDENTIFICATION FAST AND LS TTL DATA 5-248 . The LS47 thru 49 compose the and without tails. The LS247 and LS248 are functionally and electrically identical to the LS47 and LS48 with the same pinout configuration.BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS The SN54/74LS247 thru SN54/74LS249 are BCD-to-Seven-Segment Decoder/Drivers. 249 and the LS47. The composition of all characters. the LS247 thru 249 compose the and with the tails. The LS248 and 249 have active-high outputs for driving lamp buffers. All types feature a lamp test input and have full ripple-blanking input/output controls. On all types an automatic leading and/or trailing-edge zero-blanking control (RBI and RBO) is incorporated and an overriding blanking input (BI) is contained which may be used to control the lamp intensity by pulsing or to inhibit the output’s lamp test may be performed at any time when the BI/RBO node is at high level. 48 and 49.

SN54/74LS247 • SN54/74LS248 • SN54/74LS249 SN54 / 74LS248 SN54 / 74LS259 (TOP VIEW) OUTPUTS c 11 d 10 e 9 VCC 16 f 15 g 14 f g a 13 b 12 c 11 d 10 e 9 SN54 / 74LS247 (TOP VIEW) OUTPUTS VCC 16 f 15 g 14 f g a 13 b 12 a b c d e a b c d e BI/ B C LT RBORBI D A BI/ B C LT RBORBI D A 1 B 2 C INPUTS 3 4 LAMP RB TEST OUT PUT 5 RB IN PUT 6 D 7 A 8 GND 1 B 2 C INPUTS INPUTS 3 4 LAMP RB TEST OUT PUT 5 RB IN PUT 6 D 7 A 8 GND INPUTS ALL CIRCUIT TYPES FEATURE LAMP INTENSITY MODULATION CAPABILITY DRIVER OUTPUTS TYPE SN54LS247 SN54LS248 SN54LS249 SN74LS247 SN74LS248 SN74LS249 ACTIVE LEVEL low high high low high high OUTPUT CONFIGURATION open-collector 2.5 V 5.5 V 15 V 5.5 V TYPICAL POWER DISSIPATION 35 mW 125 mW 40 mW 35 mW 125 mW 40 mW LOGIC DIAGRAM LS247 (13) INPUT (7) A INPUT (1) B INPUT (2) C INPUT (6) D BI/RBO BLANKING (4) INPUT OR RIPPLE-BLANKING OUTPUT (3) (14) (12) OUTPUT a INPUT (7) A OUTPUT b OUTPUT c OUTPUT d OUTPUT e OUTPUT f OUTPUT g LAMP TEST INPUT (3) (14) INPUT (1) B INPUT (2) C INPUT (6) D BLANKING (4) INPUT OR RIPPLE-BLANKING OUTPUT (12) LS248.0 mA 8.0 kΩ pull-up open-collector open-collector 2.0 mA 4.5 V 5. LS249 (13) OUTPUT a OUTPUT b OUTPUT c OUTPUT d OUTPUT e OUTPUT f OUTPUT g (11) (11) (10) (10) (9) (9) (15) (15) LAMP TEST INPUT RBI (5) RIPPLE-BLANKING INPUT RIPPLE-BLANKING (5) INPUT FAST AND LS TTL DATA 5-249 .0 kΩ pull-up open-collector SINK CURRENT 12 mA 2.0 mA 24 mA 6.0 mA MAX VOLTAGE 15 V 5.

all segment outputs go off and the NOTES: 1. The ripple-blanking input (RBI) must NOTES: 1. L = LOW Level. X = Irrelevant NOTES: 1. 3. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. When the blanking input/ripple blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input. FAST AND LS TTL DATA 5-250 . ripple-blanking output (RBO) goes to a low level (response condition). When a low logic level is applied directly to the blanking input (BI). all segment outputs are on. LS249 FUNCTION TABLE DECIMAL OR FUNCTION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT INPUTS BI/RBO LT H H H H H H H H H H H H H H H H X H L RBI H X X X X X X X X X X X X X X X X L X D L L L L L L L L H H H H H H H H X L X C L L L L H H H H L L L L H H H H X L X B L L H H L L H H L L H H L L H H X L X A L H L H L H L H L H L H L H L H X L X H H H H H H H H H H H H H H H H L L H a H L H H L H H H H H L L L H L L L L H b H H H H H L L H H H L L H L L L L L H c H H L H H H H H H H L H L L L L L L H d H L H H L H H L H H H H L H H L L L H e H L H L L L H L H L H L L L H L L L H f H L L L H H H L H H L L H H H L L L H g L L H H H H H L H H H H H H H L L L H 2 3 4 1 1 OUTPUTS NOTE 1 H = HIGH Level. When ripple-blanking input (RBI) and inputs A. 4. 2. all segment outputs are off regardless of the level of any other input. B.SN54/74LS247 • SN54/74LS248 • SN54/74LS249 LS247 FUNCTION TABLE DECIMAL OR FUNCTION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT INPUTS BI/RBO LT H H H H H H H H H H H H H H H H X H L RBI H X X X X X X X X X X X X X X X X L X D L L L L L L L L H H H H H H H H X L X C L L L L H H H H L L L L H H H H X L X B L L H H L L H H L L H H L L H H X L X A L H L H L H L H L H L H L H L H X L X H H H H H H H H H H H H H H H H L L H a ON OFF ON ON OFF ON ON ON ON ON OFF OFF OFF ON OFF OFF OFF OFF ON b ON ON ON ON ON OFF OFF ON ON ON OFF OFF ON OFF OFF OFF OFF OFF ON c ON ON OFF ON ON ON ON ON ON ON OFF ON OFF OFF OFF OFF OFF OFF ON d ON OFF ON ON OFF ON ON OFF ON ON ON ON OFF ON ON OFF OFF OFF ON e ON OFF ON OFF OFF OFF ON OFF ON OFF ON OFF OFF OFF ON OFF OFF OFF ON f ON OFF OFF OFF ON ON ON OFF ON ON OFF OFF ON ON ON OFF OFF OFF ON g OFF OFF ON ON ON ON ON OFF ON ON ON ON ON ON ON OFF OFF OFF ON 2 3 4 OUTPUTS NOTE 1 LS248. C. be open or high if blanking of a decimal zero is not desired. and D are at a low level with the lamp test input high. BI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO).

5 20 IIH 0.5 V V V V V µA V V µA mA Min 2.5 5.0 V.2 4.25 125 70 – 50 1. VIN = VIL or VIH per Truth Table VOL IO(off) VO( ) O(on) VCC = MAX.4 – 0. VIN = 0.65 4.4 – 1. VIN = 2.0 V.2 15 12 24 Unit V °C µA mA V mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Voltage g BI / RBO Output LOW Voltage g BI / RBO Off-State Output Current a–g On-State Output Voltage g a–g Input HIGH Current 0.4 V IIL mA Note 1: Not more than one output should be shorted at a time.8 – 1.75 – 55 0 Typ 5.35 0. VIL per Truth Table VCC = MAX. VIN = 7. VIH = 2.6 3.7 V VCC = MAX.6 mA IOL = 3. VIN = VIH or VIL per Truth Table IOL = 1.SN54/74LS247 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL VO(off) IO(on) Supply Voltage Operating Ambient Temperature Range Output Current — High BI / RBO Output Current — Low BI / RBO Off-State Output Voltage a – g On-State Output Current a – g On-State Output Current a – g Parameter 54 74 54 74 54. VO(off) = 15 V.0 5. 74 74 54.2 – 2.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. IIN = – 18 mA VCC = MIN.35 2.0 V.3 7.0 25 25 Max 5. IOH = MAX. RL = 665 Ω Test Conditions FAST AND LS TTL DATA 5-251 . 74 54 74 Min 4. except BI / RBO BI / RBO IOS ICC Short Circuit Current BI / RBO (Note 1) Power Supply Current – 0.4 0.5 4.1 Input LOW Current Any Input. TA = 25°C) Limits Symbol tPLH tPHL tPHL tPLH Parameter Turn-Off Time from A Input Turn-On Time from A Input Turn-Off Time from RBI Input Turn-On Time from RBI Input Min Typ Max 100 100 100 100 Unit ns ns CL = 15 pF. 74 74 0.0 V VCC = MAX.0 – 0.0 13 mA mA VCC = MAX VCC = MAX 54 74 54.4 0. nor for more than 1 second. AC CHARACTERISTICS (VCC = 5.4 2.2 mA VCC = VCC MIN.5 250 0. 74 54 74 54. VIL = MAX IO(on) = 12 mA IO(on) = 24 mA VCC = MIN.2 0. VIH = 2.25 0.25 0.0 0. 74 54.

75 – 55 0 Typ 5. High-to-Low-Level Output from RBI Input Propagation Delay Time. VIN = 2.85 V. AC CHARACTERISTICS (VCC = 5. Input Conditions as for VOH IOL = 2.8 – 1.5 4.0 0. VIN = 7. nor for more than 1 second.2 – 2.0 mA Unit V °C µA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH IOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Voltage g a – g and BI / RBO Output Current a–g Output LOW Voltage a–g VOL BI / RBO 54 74 54.3 – 0. IOH = MAX. 74 54.4 – 1. Low-to-High-Level Output from A Input Propagation Delay Time. 74 74 54.35 0.0 5. VO = 0.5 0.0 V.5 V V V mA Min 2.6 mA IOL = 3. VIL = per Truth Table er 54.25 125 70 – 50 – 100 1.0 6. Low-to-High-Level Output from RBI Input Min Typ Max 100 100 100 100 Unit ns ns Test Conditions CL = 15 pF RL = 4.25 0. 74 2.0 kΩ CL = 15 pF RL = 6. TA = 25°C) Limits Symbol tPLH tPHL tPHL tPLH Parameter Propagation Delay Time.7 V VCC = MAX.3 25 0. 74 0.1 – 0.2 mA VCC = MAX.5 5.4 – 1.0 V.65 4.4 V IIL mA Note 1: Not more than one output should be shorted at a time.2 2.6 3.4 V VCC = MIN.0 mA V 74 IIH Input HIGH Current Any Input. High-to-Low-Level Output from A Input Propagation Delay Time. except BI / RBO Input LOW Current Any Input.0 25 25 Max 5.4 0.4 2.0 38 mA mA VCC = MAX VCC = MAX µA mA IOL = 1.0 0.0 kΩ FAST AND LS TTL DATA 5-252 .SN54/74LS248 GUARANTEED OPERATING RANGES Symbol VCC TA IOH Supply Voltage Operating Ambient Temperature Range Output Current — High BI / RBO Output Current — High a – g IOL Output Current — Low BI / RBO Output Current — Low BI / RBO Output Current — Low a – g Output Current — Low a – g Parameter 54 74 54 74 54.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.2 – 2.0 V VCC = MAX.2 4. 74 54 74 54 74 Min 4. IIN = – 18 mA VCC = MIN.25 0. VIN = 0. VIN = VIH or VIL per Truth Table VCC = MIN.5 20 0.35 0. VIH = 2.0 mA IOL = 6. except BI / RBO BI / RBO IOS ICC Short Circuit Current BI / RBO (Note 1) Power Supply Current – 0.

0 8.4 – 1.7 V VCC = MAX.35 0.1 – 0.0 0.0 0.5 20 0.0 5.4 0.0 15 mA mA VCC = MAX VCC = MAX µA mA IOL = 4.5 4.0 V.8 – 1. VIN = VIH or VIL per Truth Table VCC = MIN. High-to-Low-Level Output from RBI Input Propagation Delay Time. RL = 6. VIH = 2.4 V IIL mA Note 1: Not more than one output should be shorted at a time.2 4. except BI / RBO Input LOW Current Any Input.25 0.0 V.4 V VCC = MIN. TA = 25°C) Limits Symbol tPHL tPLH tPHL tPLH Parameter Propagation Delay Time.0 25 25 Max 5.6 3. Low-to-High-Level Output from RBI Input Min Typ Max 100 100 100 100 Unit ns ns Test Conditions CL = 15 pF. VIL = per Truth Table er 54.2 – 2. Low-to-High-Level Output from A Input Propagation Delay Time. High-to-Low-Level Output from A Input Propagation Delay Time.2 5.75 – 55 0 Typ 5.5 5. VIH = 2. AC CHARACTERISTICS (VCC = 5. 74 2.35 0.0 mA IOL = 8.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.6 mA IOL = 3.5 V. RL = 2.4 – 0.3 8. 74 74 54.0 V VCC = MAX. 74 54 74 54. except BI / RBO BI / RBO IOS ICC Short Circuit Current BI / RBO (Note 1) Power Supply Current – 0.5 4. VIL = MAX IOL = 1. 74 0. VOH = 5.0 Ω FAST AND LS TTL DATA 5-253 .2 mA V 74 IIH Input HIGH Current Any Input.2 250 0.4 2. IOH = MAX.0 V. nor for more than 1 second. VIN = 2. VIN = 7.65 4. IIN = – 18 mA VCC = MIN.5 0.25 125 70 – 50 1. 74 54 74 Min 4.5 V V V µA Min 2.0 Unit V °C µA mA V mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH IOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Voltage g BI / RBO Output HIGH Current a–g Output LOW Voltage BI / RBO VOL a–g 54 74 54.0 mA VCC = MAX.SN54/74LS249 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL VOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High BI / RBO Output Current — Low BI / RBO Output Current — Low BI / RBO Output Voltage — High a – g Output Current — Low a – g Output Current — Low a – g Parameter 54 74 54 74 54.25 0.0 Ω CL = 15 pF. VIN = 0.

L. It provides.L.L. Both assertion and negation outputs are provided.5 U.5 U.L.25 U. 0. ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC NOTES: a. 16 1 D SUFFIX SOIC CASE 751B-03 Select Inputs Output Enable (Active LOW) Inputs Multiplexer Inputs Multiplexer Output Complementary Multiplexer Output 0. 0. 65 U. LOGIC DIAGRAM S2 S1 S0 E1 9 10 11 7 I0 4 I1 3 I2 2 I3 1 I4 15 I5 14 I6 13 I7 12 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Z 5 6 Z FAST AND LS TTL DATA 5-254 . 15 U. 1 TTL Unit Load (U.) = 40 µA HIGH/1.L.6 mA LOW. 0. 8-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY • • • • • Schottky Process for High Speed Multifunction Capability On-Chip Select Logic Decoding Inverting and Non-Inverting 3-State Outputs Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 I4 15 I5 14 I6 13 I7 12 S0 11 S1 10 S2 9 16 J SUFFIX CERAMIC CASE 620-09 1 16 1 N SUFFIX PLASTIC CASE 648-08 1 I3 PIN NAMES S0–S2 E0 I0–I7 Z Z 2 I2 3 I1 4 I0 5 Z 6 Z 7 E0 8 GND LOADING (Note a) HIGH LOW 0.5 U.L. in one package.25 U.25 U.L.L. 0. 15 U. The LS251 can be used as a universal function generator to generate any logic function of four variables. 65 U.L.SN54/74LS251 8-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The TTL/MSI SN74LS251 is a high speed 8-Input Digital Multiplexer.L. the ability to select one bit of data from up to eight sources.L.

TRUTH TABLE E0 H L L L L L L L L L L L L L L L L S2 X L L L L L L L L H H H H H H H H S1 X L L L L H H H H L L L L H H H H S0 X L L H H L L H H L L H H L L H H I0 X L H X X X X X X X X X X X X X X I1 X X X L H X X X X X X X X X X X X I2 X X X X X L H X X X X X X X X X X I3 X X X X X X X L H X X X X X X X X I4 X X X X X X X X X L H X X X X X X I5 X X X X X X X X X X X L H X X X X I6 X X X X X X X X X X X X X L H X X I7 X X X X X X X X X X X X X X X L H Z (Z) H L H L H L H L H L H L H L H L Z (Z) L H L H L H L H L H L H L H L H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care (Z) = High impedance (Off) GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter Min 4. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. both outputs are in the high impedance (high Z) state. When the Output Enable is HIGH.75 0 Typ 5. 8-position switch with the switch position controlled by the state of three Select inputs.6 24 Unit V °C mA mA FAST AND LS TTL DATA 5-255 . Both assertion and negation outputs are provided. The Output Enable input (EO) is active LOW. S0. When it is activated.25 70 – 2.SN54/74LS251 FUNCTIONAL DESCRIPTION The LS251 is a logical implementation of a single pole. S1. The Output Enable signals should be designed to ensure there is no overlap in the active LOW portion of the enable voltage. the logic function provided at the output is: Z = EO ⋅ (I0 ⋅ S0 ⋅ S1 ⋅ S2 + I1 ⋅ S0 ⋅ S1 ⋅ S2 + I2 ⋅ S0 ⋅ S1 ⋅ Z = EO ⋅ S2 + I3 ⋅ S0 ⋅ S1⋅ S2 + I4 ⋅ S0 ⋅ S1 ⋅ S2 + I5 ⋅ S0 ⋅ Z = EO ⋅ S1 ⋅ S2 + I6 ⋅ S0 ⋅ S1 ⋅ S2 + I7 ⋅ S0 ⋅ S1 ⋅ S2). all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. When the outputs of the 3-state devices are tied together.0 25 Max 5. S2.

1 0. VIN = 0. Select to Z Output Propagation Delay. VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN. RL = 667 kΩ CL = 15 pF. VE = 0 V VCC = MAX.4 V VCC = MAX. IIN = – 18 mA VCC = MIN. AC CHARACTERISTICS (TA = 25°C.4 – 0.SN54/74LS251 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.0 17 18 17 24 30 26 37 15 30 15 Max 33 33 45 45 15 15 28 28 27 40 45 40 55 25 45 25 Unit ns ns ns ns ns ns ns ns Figure 1 Figure 2 Figure 1 Figures 2 Figures 4. VIN = 2. Data to Z Output Propagation Delay.0 0.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.0 V VCC = MAX.25 VOL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 0. 5 Figures 3. VOUT = 2. Select to Z Output Propagation Delay.0 kΩ Test Conditions FAST AND LS TTL DATA 5-256 .8 – 1. RL = 2. VE = 4.0 pF.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current 12 mA – 30 – 0.4 V VCC = MAX VCC = MAX.7 V VCC = MAX.5 V Note 1: Not more than one output should be shorted at a time. VIN = VIL or VIH per Truth Table VCC = MAX. Data to Z Output Output Enable Time to Z Output Output Enable Time to Z Output Output Disable Time to Z Output Output Disable Time to Z Output Min Typ 20 21 29 28 10 9. 5 Figures 3. IOH = MAX.4 Min 2. VIN = 7.65 3. nor for more than 1 second. 5 CL = 5. VOUT = 0. VCC = 5.4 – 130 10 0.7 V VCC = MAX. 5 Figures 4.35 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.5 20 – 20 20 V µA µA µA mA mA mA mA 0.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ Parameter Propagation Delay.

3 V tPHL 1.3 V 0.3 V ≥ VOH ≈ 1.5 V ≈ 1.3 V Figure 1 Figure 2 VE tPZL VOUT 1.3 V VOUT 1.3 V tPHL 1. Figure 5 FAST AND LS TTL DATA 5-257 .3 V VOL VE tPZH VOUT 1.5 V Figure 4 AC LOAD CIRCUIT VCC SWITCH POSITIONS RL SW1 SYMBOL tPZH tPZL tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed TO OUTPUT UNDER TEST 5 kΩ CL* SW2 * Includes Jig and Probe Capacitance.3 V VOUT 1.3 V tPHZ 1.3 V tPLH 1.5 V Figure 3 0.3 V tPLH 1.3 V 1.3 V tPLZ 1.3 V 0.SN54/74LS251 3-STATE AC WAVEFORMS VIN 1.3 V 1.3 V VIN 1.

25 U.L.5 U. E I I I I I I I I E S0 0a 0a 1a 2a 3a 0b 1b 2b 3b 0b S1 Za Zb 7 VCC = PIN 16 GND = PIN 8 9 FAST AND LS TTL DATA 5-258 .L.L.5 U.5) U.L. 0. for Military (54) and 15 U.L.25 U.L.L. 0. 65 (25) U. for Military (54) and 65 U. DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY • • • • Schottky Process for High Speed Multifunction Capability Non-Inverting 3-State Outputs Input Clamp Diodes Limit High Speed Termination Effects 16 J SUFFIX CERAMIC CASE 620-09 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 E0b 15 S0 14 I3b 13 I2b 12 I1b 11 I0b 10 Zb 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 15 (7.6 mA LOW.5 U.5 U. S1 Multiplexer A E0a I0a – I3a Za Multiplexer B E0b I0b – I3b Zb Common Select Inputs Output Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output (Note b) Output Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output (Note b) 0. It can select two bits of data from four sources using common select inputs.) = 40 µA HIGH/1.5) U.25 U. 0.L. The Output HIGH drive factor is 25 U. for Commercial (74) Temperature Ranges.25 U. 15 (7.5 U.L.L. 0.L. LOGIC SYMBOL 0.L.L.L. 0. allowing the outputs to interface directly with bus oriented systems. 14 2 1 6 5 4 3 10 11 12 13 15 NOTES: a) 1 TTL Unit Load (U.25 U.L. 16 1 N SUFFIX PLASTIC CASE 648-08 1 E0a 2 S1 3 I3a 4 I2a 5 I1a 6 I0a 7 Za 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 PIN NAMES LOADING (Note a) HIGH LOW 0. for Commercial (74) Temperature Ranges. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC S0.SN54/74LS253 DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The LSTTL / MSI SN54 / 74LS253 is a Dual 4-Input Multiplexer with 3-state outputs.L.L.L. b) The Output LOW drive factor is 7.5 U.L. It is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. 65 (25) U. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (E0) inputs. 0. 0.

They select two bits from four sources selected by common select inputs (S0. forces the outputs to a high impedance (high Z) state. 4-position switch. H = HIGH Level L = LOW Level X = Irrelevant (Z) = High Impedance (off) Address inputs S0 and S1 are common to both sections. FAST AND LS TTL DATA 5-259 . The LS253 is the logic implementation of a 2-pole. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so that there is no overlap. all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. E0b) inputs which when HIGH. where the position of the switch is determined by the logic levels supplied to the two select inputs. S1). The 4-input multiplexers have individual Output Enable (E0a. The logic equations for the outputs are shown below: Za = E0a ⋅ (I0a ⋅ S1 ⋅ S0 + I1a ⋅ S1 ⋅ S0 ⋅ I2a ⋅ S1 ⋅ S0 + I3a ⋅ S1 ⋅ S0) Zb = E0b ⋅ (I0b ⋅ S1 ⋅ S0 + I1b ⋅ S1 ⋅ S0 ⋅ I2b ⋅ S1 ⋅ S0 + I3b ⋅ S1 ⋅ S0) TRUTH TABLE SELECT INPUTS S0 X L L H H L L H H S1 X L L L L H H H H I0 X L H X X X X X X DATA INPUTS I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H OUTPUT ENABLE E0 H L L L L L L L L OUTPUT Z (Z) L H L H L H L H If the outputs of 3-state devices are tied together.SN54/74LS253 LOGIC DIAGRAM E0b 15 I3b 13 I2b 12 I1b 11 I0b 10 S0 14 S1 2 I3a 3 I2a 4 I1a 5 I0a 6 E0a 1 Zb 9 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Za 7 FUNCTIONAL DESCRIPTION The LS253 contains two identical 4-Input Multiplexers with 3-state outputs.

1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current 14 mA – 30 – 0.0 0.5 V Note 1: Not more than one output should be shorted at a time.4 0.4 V VCC = MAX VCC = MAX.SN54/74LS253 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54 74 54 74 Min 4.65 3.0 V VCC = MAX.4 V VCC = MAX.0 5. Data to Output Propagation Delay. 74 VOL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.25 125 70 – 1. VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN. AC CHARACTERISTICS (TA = 25°C.8 – 1.75 – 55 0 Typ 5. VCC = 5. IOH = MAX. VIN = 0. VIN = VIL or VIH per Truth Table VCC = MAX.7 V VCC = MAX. IIN = – 18 mA VCC = MIN.4 3.1 0. VIN = 2. VE = 0 V VCC = MAX.0 pF.7 V VCC = MAX. Select to Output Output Enable Time Output Disable Time Min Typ 17 13 30 21 15 15 27 18 Max 25 20 45 32 28 23 41 27 Unit ns ns ns ns Figure 1 Figure 1 Figures 4.25 0. VOUT = 0. nor for more than 1 second.0 25 25 Max 5.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.5 5. 5 Figures 3.4 V V 2.5 4. RL = 667 Ω Test Conditions FAST AND LS TTL DATA 5-260 . VIN = 7.4 – 130 12 0. RL = 667 Ω CL = 45 pF.0 V) See SN54LS251 for Waveforms Limits Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay. 5 CL = 5. VOUT = 2.35 0.5 V V Min 2.5 20 – 20 20 V µA µA µA mA mA mA mA 2.0 – 2.6 12 24 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.4 – 0. VE = 4.

L. 0. DUAL 4-BIT ADDRESSABLE LATCH LOW POWER SCHOTTKY • • • • • • Serial-to-Parallel Capability Output From Each Storage Bit Available Random (Addressable) Data Entry Easily Expandable Active Low Common Clear Input Clamp Diodes Limit High Speed Termination Effects J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 CL 15 E 14 Db 13 Q3b 12 Q2b 11 Q1b 10 Q0b 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L.0 U. Each latch has a Data input (D) and four outputs (Q0 – Q3). 5 (2.5 U.25 U. an active LOW Enable input (E) and an active LOW Clear input (CL). 0. When the Enable (E) is HIGH and the Clear input (CL) is LOW.5 U.5 U.L.L. changing more than one bit of the Address (A0. for Commercial (74) Temperature Ranges. the selected output (Q0 – Q3).5 U. determined by the Address inputs.L. 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC 1 A0 2 A1 3 Da 4 Q0a 5 Q1a 6 Q2a 7 Q3a 8 GND PIN NAMES LOADING (Note a) HIGH LOW 0. b) The Output LOW drive factor is 2. Therefore.SN54/74LS256 DUAL 4-BIT ADDRESSABLE LATCH The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control inputs.L. 3 LOGIC SYMBOL 2 1 15 14 13 A0. 0. follows D.5 U. the contents of the latch are stored.L. A0 A1 CL A0 A1 CL E Db Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b 4 5 6 7 VCC = PIN 16 GND = PIN 8 9 10 11 12 FAST AND LS TTL DATA 5-261 .5) U.L. these include two Address inputs (A0. Db E CL Q0a – Q3a. CL = HIGH). When the E goes HIGH. for Military (54) and 5 U. Dual 4-channel demultiplexing occurs when the (CL) and E are both LOW.L. 10 U. this should be done only while in the memory mode (E = CL = HIGH).) = 40 µA HIGH/1. Da E NOTES: a) 1 TTL Unit Load (U.25 U. 0. Q0b – Q3b Address Inputs Data Inputs Enable Input (Active LOW) Clear Input (Active LOW) Parallel Latch Outputs (Note b) 0. A1).L. all outputs (Q0 – Q3) are LOW.L. A1) could impose a transient wrong address.6 mA LOW. 0.L. When CL is HIGH and E is LOW.25 U. When operating in the addressable latch mode (E = LOW. A1 Da. 1.L.

SN54/74LS256 LOGIC DIAGRAM E 14 3 Da 1 A0 2 A1 15 CL 13 Db 4 5 6 7 9 10 11 12 Q0a VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Q1a Q2a Q3a Q0b Q1b Q2b Q3b TRUTH TABLE CL L L L L L L L L L H H H H H H H H H E H L L L L L L L L H L L L L L L L L D X L H L H L H L H X L H L H L H L H A0 X L L H H L L H H X L L H H L L H H A1 X L L L L H H H H X L L L L H H H H Q0 L L H L L L L L L QN–1 L H QN–1 QN–1 QN–1 QN–1 QN–1 QN–1 Q1 L L L L H L L L L QN–1 QN–1 QN–1 L H QN–1 QN–1 QN–1 QN–1 Q2 L L L L L L H L L QN–1 QN–1 QN–1 QN–1 QN–1 L H QN–1 QN–1 Q3 L L L L L L L L H QN–1 QN–1 QN–1 QN–1 QN–1 QN–1 QN–1 L H MODE Clear Demultiplex Memory Addressable Latch H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial MODE SELECTION E L H L H CL H H L L MODE Addressable Latch Memory Dual 4-Channel Demultiplexer Clear FAST AND LS TTL DATA 5-262 .

5 4.5 V V V Min 2.8 – 1.0 V. Address to Output Turn-On Delay.8 – 100 30 V µA 2.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Voltage 54. CL = 15 pF F FAST AND LS TTL DATA 5-263 .2 – 0. VIN = VIL or VIH per Truth Table VCC = MAX. IOH = MAX.0 8.35 0.1 0. 74 54 74 Min 4. VIN = 0.4 4.7 V IIH mA VCC = MAX.SN54/74LS256 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. Address to Output Turn-On Delay.5 20 40 0. nor for more than 1 second.0 V mA mA mA VCC = MAX. Enable to Output Turn-On Delay.0 mA VCC = VCC MIN.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. IIN = – 18 mA VCC = MIN. 74 54. 74 VOL Output LOW Voltage 74 Input HIGH Current Others E Input Others E Input IIL IOS ICC Input LOW Current Others E Input Short Circuit Current (Note 1) Power Supply Current – 20 0.0 mA IOL = 8.25 0.0 25 25 Max 5.4 0.75 – 55 0 Typ 5. Clear to Output Min Typ 20 16 20 13 20 14 12 Max 27 24 30 20 30 24 23 Unit ns ns ns ns ns ns ns Figure 1 Figure 2 Figure 3 Figure 5 Test Conditions VCC = 5. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Turn-Off Delay.4 – 0. Enable to Output Turn-Off Delay. VIN = 2.0 0. Data to Output Turn-On Delay.4 – 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. VIN = VIH or VIL per Truth Table IOL = 4. VIN = 7.0 5.65 3.5 0.5 5.25 125 70 – 0. Data to Output Turn-Off Delay.

CL = L. Enable To Output and Enable Pulse Width A1 1. Turn-on and Turn-off Delays. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. Address to Enable (See Notes 1 and 2) NOTES: 1. Clear to Output Figure 6.3 V A1 Q1 1. A = STABLE tpw 1. Turn-on and Turn-off Delays.3 V E Q Q=D Q=D OTHER CONDITIONS: C = H.3 V A ts E 1.3 V tPLH 1. Turn-on and Turn-off Delays.3 V 1.3 V OTHER CONDITIONS: E = L. 2. A = STABLE Figure 3.3 V Figure 2.3 V STABLE ADDRESS th 1. Data to Enable C 1.SN54/74LS256 AC SET-UP REQUIREMENTS (TA = 25°C) Limits Symbol ts ts th th tW Parameter Data Setup Time Address Setup Time Data Hold Time Address Hold Time Enable Pulse Width Min 20 0 0 15 15 Typ Max Unit ns Figures 4 & 6 ns ns ns ns Figure 4 Figure 6 Figure 1 VCC = 5. Data to Output Figure 1. Setup and Hold Time.3 V 1. Setup Time. CL = H. The shaded areas indicate when the inputs are permitted to change for predictable output performance.3 V tPHL 1.3 V tPHL 1.0 V Test Conditions AC WAVEFORMS D D tpw E tPHL Q OTHER CONDITIONS: CL = H. D = H 1.3 V tPLH 1.3 V D ts(H) th(H) ts(L) th(L) 1. FAST AND LS TTL DATA 5-264 .3 V tPHL 1.3 V Q 1.3 V Q OTHER CONDITIONS: E = H OTHER CONDITIONS: CL = H Figure 5. A = STABLE tPLH 1.3 V OTHER CONDITIONS: E = L. Address to Output Figure 4. Turn-on Delay.

QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The LSTTL / MSI SN54 / 74LS257B and the SN54 / 74LS258B are Quad 2-Input Multiplexers with 3-state outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the selected data in true (non-inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (EO) Input. allowing the outputs to interface directly with bus oriented systems. It is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC SN54/74LS258B 1 S 2 I0a 3 I1a 4 Za 5 I0b 6 I1b 7 Zb 8 GND FAST AND LS TTL DATA 5-265 . SN54/74LS257B SN54/74LS258B QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY • • • • • • Schottky Process For High Speed Multiplexer Expansion By Tying Outputs Together Non-Inverting 3-State Outputs Input Clamp Diodes Limit High Speed Termination Effects Special Circuitry Ensures Glitch Free Multiplexing ESD > 3500 Volts CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 E0 15 I0c 14 I1c 13 Zc 12 I0d 11 I1d 10 Zd 9 J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 SN54/74LS257B VCC = PIN 16 GND = PIN 8 16 1 D SUFFIX SOIC CASE 751B-03 1 S VCC 16 2 I0a E0 15 3 I1a I0c 14 4 Za I1c 13 5 I0b Zc 12 6 I1b I0d 11 7 Zb I1d 10 8 GND Zd 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

SN54/74LS257B D SN54/74LS258B LOGIC DIAGRAMS SN54 / 74LS257B E0 15 I0a 2 I1a 3 I0b 5 I1b 6 I0c 14 I1c 13 I0d 11 I1d 10 S 1 4 7 12 9 Za Zb Zc Zd SN54 / 74LS258B E0 15 I0a 2 I1a 3 I0b 5 I1b 6 I0c 14 I1c 13 I0d 11 I1d 10 S 1 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 4 7 12 9 Za Zb Zc Zd FAST AND LS TTL DATA 5-266 .

When the Select Input is LOW. all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. They select four bits of data from two sources each under control of a Common Data Select Input. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so there is no overlap. the I0 inputs are selected and when Select is HIGH. 2-position switch where the position of the switch is determined by the logic levels supplied to the Select Input. The logic equations for the outputs are shown below: LS257B Za = E0 • Zc = E0 • When the Output Enable Input (E0) is HIGH.25 125 70 – 1.5 4.5 5.75 – 55 0 Typ 5.0 5. the outputs are forced to a high impedance “off” state. The data on the selected inputs appears at the outputs in true (noninverted) form for the LS257B and in the inverted form for the LS258B.0 25 25 Max 5.0 – 2.SN54/74LS257B D SN54/74LS258B FUNCTIONAL DESCRIPTION The LS257B and LS258B are Quad 2-Input Multiplexers with 3-state outputs. The LS257B and LS258B are the logic implementation of a 4-pole. (I1a • S + I0a • S) Zb = E0 • (I1b • S + I0b • S) (I1c • S + I0c • S) Zd = E0 • (I1d • S + I0d • S) LS258B Za = E0 • (I1a • S + I0a • S) Zb = E0 • (I1b • S + I0b • S) Zc = E0 • (I1c • S + I0c • S) Zd = E0 • (I1d • S + I0d • S) TRUTH TABLE OUTPUT ENABLE EO H L L L L SELECT INPUT S X H H L L DATA INPUTS I0 X X X L H I1 X L H X X OUTPUTS LS257B Z (Z) L H L H OUTPUTS LS258B Z (Z) H L H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care (Z) = High Impedance (off) GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54 74 54 74 Min 4.6 12 24 Unit V °C mA mA FAST AND LS TTL DATA 5-267 . If the outputs are tied together. the I1 inputs are selected.

IOH = MAX.0 V) See SN54LS251 for Waveforms Limits Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPLZ tPHZ Parameter Propagation Delay.4 0. IIN = – 18 mA VCC = MIN. 74 VOL IOZH IOZL Output LOW Voltage 74 Output Off Current — HIGH Output Off Current — LOW Input HIGH Current Other Inputs S Inputs Other Inputs S Inputs IIL IOS Input LOW Current All Inputs Short Circuit Current (Note 1) Power Supply Current Total.4 3. VOUT = 2. VIN = 0.7 V VCC = MAX. Output 3-State LS257B LS258B LS257B LS258B LS257B LS258B 10 9.4 V VCC = MAX. nor for more than 1 second.2 – 0. Output LOW Total.4 – 0.7 V IIH mA mA mA VCC = MAX.35 0. VCC = 5. VIN = VIL or VIH per Truth Table VCC = MAX.8 – 1.0 pF RL = 667 Ω FAST AND LS TTL DATA 5-268 . Output HIGH ICC Total. VOUT = 0. Select to Output Output Enable Time to HIGH Level Output Enable Time to LOW Level Output Disable Time to LOW Level Output Disable Time from HIGH Level Min Typ 10 12 14 14 20 20 16 18 Max 13 15 21 21 25 25 25 25 Unit ns ns ns ns ns ns Test Conditions Figures 1 & 2 CL = 45 pF Figures 1 & 2 Figures 4 & 5 Figures 3 & 5 Figures 3 & 5 Figures 4 & 5 CL = 45 pF RL = 667 Ω CL = 5.1 0.0 16 14 19 16 mA VCC = MAX – 30 0.4 V VCC = MAX mA mA Note 1: Not more than one output should be shorted at a time.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.SN54/74LS257B D SN54/74LS258B DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.0 0. VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN.0 V VCC = MAX. VIN = 2. Data to Output Propagation Delay. AC CHARACTERISTICS (TA = 25°C.25 0.4 – 130 V µA µA µA 2.5 V V Min 2. VIN = 7.4 V V 2.65 3.5 20 – 20 20 40 0.1 0.

5 U.0 5. and also a 1-of-8 decoder and demultiplexer with active HIGH outputs.L.L.0 U.L. for Military (54) and 5 U. 0. 5 (2.) = 40 µA HIGH/1. 16 1 D SUFFIX SOIC CASE 751B-03 A0. 0.5 4.L. for Commercial (74) Temperature Ranges. A1. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.L.0 25 25 Max 5. 8-BIT ADDRESSABLE LATCH LOW POWER SCHOTTKY • • • • • • Serial-to-Parallel Conversion Eight Bits of Storage With Output of Each Bit Available Random (Addressable) Data Entry Active High Demultiplexing or Decoding Capability Easily Expandable Common Clear CONNECTION DIAGRAM DIP (TOP VIEW) 16 J SUFFIX CERAMIC CASE 620-09 1 VCC 16 C 15 E 14 D 13 Q7 12 Q6 11 Q5 10 Q4 9 16 1 N SUFFIX PLASTIC CASE 648-08 1 Ao PIN NAMES 2 A1 3 A2 4 Q0 5 Q1 6 Q2 8 7 Q3 GND LOADING (Note a) HIGH LOW 0. 0. The device also incorporates an active LOW common Clear for resetting all latches.25 U.25 125 70 – 0.L.L. as well as.L. 1.25 U.L.0 Unit V °C mA mA FAST AND LS TTL DATA 5-269 .L. 10 U.L. 0. 74 54 74 Min 4.5 U.4 4. 0.L. It is a multifunctional device capable of storing single line data in eight addressable latches. an active LOW Enable. A2 D E C Q0 to Q7 Address lnputs Data Input Enable (Active LOW) Input Clear (Active LOW) input Parallel Latch Outputs (Note b) 0.5 U.5 5.75 – 55 0 Typ 5.5 U.SN54/74LS259 8-BIT ADDRESSABLE LATCH The SN54 / 74LS259 is a high-speed 8-Bit Addressable Latch designed for general purpose storage applications in digital systems.5 U.6 mA LOW.5) U. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC NOTES: a) 1 TTL Unit Load (U.0 8.L. b) The Output LOW drive factor is 2.25 U.

SN54/74LS259 LOGIC DIAGRAM E 14 D 13 1 A0 2 A1 A2 3 15 C VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 4 5 6 7 9 10 11 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FUNCTIONAL DESCRIPTION The SN54 / 74LS259 has four modes of operation as shown in the mode selection table. all latches remain in their previous state and are unaffected by the Data or Address inputs. The truth table below summarizes the operations. In the one-of-eight decoding or demultiplexing mode. When operating the SN54 / 74LS259 as an addressable latch. Therefore. the MODE SELECTION E L H L H C H H L L MODE Addressable Latch Memory Active HIGH Eight-Channel Demultiplexer Clear C E D A0 L H X X L L L L L L H L L L L H L L H H • • • • • • • • • • • • • • • L L H H H H X H H H H • • • • • H H I L L L • • • • • L L I H L H • • • • • L H X L L H H A1 X L L L L • • • • • H X L L L L • • • • • H H A2 X L L L L Q0 L L H L L addressed output will follow the state of the D input with all other inputs in the LOW state. In the addressable latch mode.The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. changing more then one bit of the address could impose a transient wrong address. this should only be done while in the memory mode. In the memory mode. In the clear mode all outputs are LOW and unaffected by the address and data inputs. data on the Data line (D) is written into the addressed latch. TRUTH TABLE PRESENT OUTPUT STATES Q1 L L L L H Q2 L L L L L Q3 L L L L L • • • • • L Q4 L L L L L Q5 L L L L L Q6 L L L L L Q7 L L L L L MODE Clear Demultiplex H X L L L L L QN–1 L H QN–1 QN–1 L L L L L H Memory QN–1 QN–1 L H QN–1 QN–1 QN–1 QN–1 QN–1 Addressable Latch X = Don’t Care Condition L = LOW Voltage Level H = HIGH Voltage Level QN–1 = Previous Output State • • • • • QN–1 QN–1 L H H H H H QN–1 QN–1 FAST AND LS TTL DATA 5-270 .

IIN = – 18 mA VCC = MIN. nor for more than 1 second.5 0. VIN = 0. IOH = MAX. Enable to Output Turn-On Delay.0 mA IOL = 8. Address Parameter Min 20 15 5. VIN = 7. Data Hold Time.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. Clear or Enable Hold Time. Data to Output Turn-On Delay.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.SN54/74LS259 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.4 V V 2.35 0.8 – 1.7 3.7 V VCC = MAX.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current –20 – 0.0 20 Typ Max Unit ns ns ns ns FAST AND LS TTL DATA 5-271 .5 0.25 0.4 – 100 36 0.65 3. AC CHARACTERISTICS (TA = 25°C. VIN = VIH or VIL per Truth Table IOL = 4.0 V VCC = MAX. VIN = 2.0 mA VCC = VCC MIN.5 V V Min 2.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Turn-Off Delay.5 – 0. Clear to Output Min Typ 22 15 20 13 24 18 17 Max 35 24 32 21 38 29 27 Unit ns ns ns ns ns ns ns Test Conditions CL = 15 pF AC SET-UP REQUIREMENTS (TA = 25°C. Enable to Output Turn-Off Delay. VCC = 5.0 V) Limits Symbol ts tW th th Input Setup Time Pulse Width. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. Address to Output Turn-On Delay. Address to Output Turn-On Delay. VCC = 5. Data to Output Turn-Off Delay. VIN = VIL or VIH per Truth Table VCC = MAX.

Enable To Output and Enable Pulse Width A1 1. Data to Output Figure 1. Setup and Hold Time.3 V tPHL 1. Address to Output Figure 4. A = STABLE tPLH 1. 2. Turn-on and Turn-off Delays. Data to Enable C 1. FAST AND LS TTL DATA 5-272 . C = H. Setup Time. A = STABLE Figure 3.3 V tPLH 1. Clear to Output OTHER CONDITIONS: C = H Figure 6.3 V 1. Address to Enable (See Notes 1 and 2) NOTES: 1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. D = H OTHER CONDITIONS: C = H.3 V 1.3 V tPHL 1.3 V 1.3 V tPHL 1.3 V D ts(H) th(H) ts(L) th(L) 1. A = STABLE tw 1.3 V E Q Q=D Q=D OTHER CONDITIONS: E = L.3 V tPLH 1.SN54/74LS259 AC WAVEFORMS D D tw E tPHL Q OTHER CONDITIONS: C = H.3 V OTHER CONDITIONS: E = L. C = L. Turn-on Delay. The shaded areas indicate when the inputs are permitted to change for predictable output performance.3 V Figure 2.3 V A1 Q1 1. Turn-on and Turn-off Delays.3 V A ts E STABLE ADDRESS Q OTHER CONDITIONS: E = H Figure 5. Turn-on and Turn-off Delays.3 V Q 1.

25 125 70 – 0.75 – 55 0 Typ 5.5 4.0 25 25 Max 5.SN54/74LS260 DUAL 5-INPUT NOR GATE VCC 14 DUAL 5-INPUT NOR GATE 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 5.4 4.0 8.0 Unit V °C mA mA FAST AND LS TTL DATA 5-273 .0 5. 74 54 74 Min 4.

0 mA VCC = VCC MIN.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 6. VIN = 7.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.4 V V 2. Input to Output Min Typ 5.0 V CL = 15 pF FAST AND LS TTL DATA 5-274 .0 mA IOL = 8.65 3.5 20 IIH IIL IOS ICC V µA mA mA mA 2.35 0. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. IOH = MAX.25 0.5 – 0. VIN = 0.5 V V Min 2.5 0. VIN = VIL or VIH per Truth Table VCC = MAX.4 – 100 4.0 Max 15 15 Unit ns ns Test Conditions VCC = 5.0 0.SN54/74LS260 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.5 0. Input to Output Turn-On Delay. Output LOW –20 – 0.7 3.7 V VCC = MAX.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total. VIN = VIH or VIL per Truth Table IOL = 4. Output HIGH Total.0 5.0 V VCC = MAX. VIN = 2. nor for more than 1 second. IIN = – 18 mA VCC = MIN.5 0.8 – 1.

0 Unit V °C V mA FAST AND LS TTL DATA 5-275 .25 125 70 5. 74 54 74 Min 4.5 4.0 25 25 Max 5.75 – 55 0 Typ 5.5 5.5 4.0 8.SN54/74LS266 QUAD 2-INPUT EXCLUSIVE NOR GATE QUAD 2-INPUT EXCLUSIVE NOR GATE LOW POWER SCHOTTKY VCC 14 13 12 * 11 10 * 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 * 1 2 3 4 * 5 6 7 GND * OPEN COLLECTOR OUTPUTS 14 1 N SUFFIX PLASTIC CASE 646-06 TRUTH TABLE IN A L L H H B L H L H OUT Z H L L H 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage — High Output Current — Low Parameter 54 74 54 74 54.0 5.

65 0.0 mA VCC = VCC MIN.25 – 0. VOH = MAX IOL = 4.35 0. VIN = 2.0 0. VIN = VIL or VIH per Truth Table VCC = MAX.4 V VCC = MAX AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay.8 – 1. Other Input LOW Propagation Delay.0 V CL = 15 pF.5 40 IIH IIL ICC V µA mA mA mA 54. VIN = 7.0 mA IOL = 8. Other Input HIGH Min Typ 18 18 18 18 Max 30 30 30 30 Unit ns ns VCC = 5.4 V µA V Min 2.5 100 0. VIN = 0.2 Input LOW Current Power Supply Current –0.8 13 0. IIN = – 18 mA VCC = MIN.7 V VCC = MAX. RL = 2. 74 54.0 V VCC = MAX.SN54/74LS266 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage 74 Input HIGH Current 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. 74 0.0 kΩ Test Conditions FAST AND LS TTL DATA 5-276 .

L.5 U.5 U.L. 10 U. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. 0.OCTAL D FLIP-FLOP WITH CLEAR The SN54 / 74LS273 is a high-speed 8-Bit Register.5 U.L.L.L.L.L. 0. 20 1 DW SUFFIX SOIC CASE 751D-03 NOTES: a) 1 TTL Unit Load (U.L.L.25 U. for Military (54) and 5 U. for Commercial (74) Temperature Ranges. 5 (2. ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC TRUTH TABLE MR L H H CP X Dx X H L Qx L H L H = HIGH Logic Level L = LOW Logic Level X = Immaterial LOGIC DIAGRAM 11 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 CP CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q 1 MR VCC = PIN 20 GND = PIN 10 = PIN NUMBERS Q0 2 Q1 5 Q2 6 Q3 9 Q4 12 Q5 15 Q6 16 Q7 19 FAST AND LS TTL DATA 5-277 . 0.25 U.6 mA LOW.L. This device is supplied in a 20-pin package featuring 0.5 U.) = 40 µA HIGH/1. SN54/74LS273 • • • • 8-Bit High Speed Register Parallel Register Common Clock and Master Reset Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q7 20 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 13 Q4 12 CP 11 OCTAL D FLIP-FLOP WITH CLEAR LOW POWER SCHOTTKY 20 1 J SUFFIX CERAMIC CASE 732-03 1 MR PIN NAMES 2 Q0 3 D0 4 D1 5 Q1 6 Q2 7 D2 8 D3 9 Q3 10 GND 20 1 N SUFFIX PLASTIC CASE 738-03 LOADING (Note a) HIGH LOW 0.5) U.L. CP D0 – D 7 MR Q0 – Q7 Clock (Active HIGH Going Edge) Input Data Inputs Master Reset (Active LOW) Input Register Outputs (Note b) 0. b) The Output LOW drive factor is 2.3 inch lead spacing.25 U. 0.

8 – 1.5 5. VIN = 2.0 V VCC = MAX.0 8.5 0. VIN = 7. VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8. MR to Q Output Propagation Delay.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.0 25 25 Max 5.25 125 70 – 0. When the MR input is LOW.75 – 55 0 Typ 5.SN54/74LS273 FUNCTIONAL DESCRIPTION The SN54 / 74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset. the Q outputs are LOW.7 3. Clock to Output Min 30 Typ 40 18 17 18 27 27 27 Max Unit MHz ns ns Test Conditions Figure 1 Figure 2 Figure 1 FAST AND LS TTL DATA 5-278 .0 mA VCC = VCC MIN. AC CHARACTERISTICS (TA = 25°C.0 V) Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Input Clock Frequency Propagation Delay.0 5. VIN = VIL or VIH per Truth Table VCC = MAX. VIN = 0. IIN = – 18 mA VCC = MIN.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. IOH = MAX.0 0.65 3.5 0.5 V V Min 2.35 0.5 4. VCC = 5. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 – 0. 74 54 74 Min 4.7 V VCC = MAX.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2. Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH transition of the clock input. independent of the other inputs.4 V V 2.25 0.4 4.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. nor for more than 1 second.4 – 100 27 0.

A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized.3 V 1. Clock to Output Delays.3 V tPHL *The shaded areas indicate when the input is permitted to *change for predictable output performance. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition.0 V) Limits Symbol tw ts th trec Parameter Pulse Width.3 V th(H) 1. MR 1.3 V 1. and Master Reset Recovery Time DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs.3 V tPHL 1.0 25 Typ Max Unit ns ns ns ns Test Conditions Figure 1 Figure 1 Figure 1 Figure 2 AC WAVEFORMS 1/f max tW CP 1.3 V tPLH Qn CP Qn tPLH tW 1. FAST AND LS TTL DATA 5-279 .3 V 1.3 V ts(H) D * 1.3 V tPHL 1. Master Reset to Output Delay.3 V trec 1.3 V th(L) 1.3 V 1. Frequency.3 V 1. Clock or Clear Data Setup Time Hold Time Recovery Time Min 20 20 5. Clock Pulse Width. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs. Setup and Hold Times Data to Clock Figure 2. VCC = 5.SN54/74LS273 AC SETUP REQUIREMENTS (TA = 25°C. Master Reset Pulse Width.3 V tPLH Qn 1.3 V ts(L) Figure 1.

otherwise. If all inputs go h = HIGH simultaneously. 74 54 74 Min 4. h = it follows the Truth Table 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 4.0 Unit V °C mA mA FAST AND LS TTL DATA 5-280 .75 – 55 0 Typ 5.0 25 25 Max 5. the output h = state is indeterminate.SN54/74LS279 QUAD SET-RESET LATCH VCC 16 S1 15 R 14 Q 13 S1 12 S2 11 R 10 Q 9 QUAD SET-RESET LATCH LOW POWER SCHOTTKY 1 R 2 S1 3 S2 4 Q 5 R 6 S1 7 Q 8 GND 16 1 J SUFFIX CERAMIC CASE 620-09 TRUTH TABLE INPUT S1 L L X H H S2 L X L H H R L H H L H OUTPUT (Q) h H H L No Change 16 1 N SUFFIX PLASTIC CASE 648-08 L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care h = The output is HIGH as long as h = S1 or S2 is LOW.25 125 70 – 0.5 5.0 8.0 5.4 4.

5 0.4 – 100 7. nor for more than 1 second. R to Output Min Typ Max 22 *21* 27 Unit ns ns Test Conditions VCC = 5.SN54/74LS279 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.5 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = VIL or VIH per Truth Table VCC = MAX.0 V CL = 15 pF F * Add 0.7 3.0 ns input rise time less than 15 ns. FAST AND LS TTL DATA 5-281 . VIN = 0.0 0.0 mA VCC = VCC MIN.8 – 1.35 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.6 ns to spec limit for each 1. VIN = 2. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.65 3.0 V VCC = MAX.0 mA IOL = 8. IOH = MAX.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.25 0.0 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPHL Parameter Propagation Delay.4 V V 2.5 – 0. VIN = VIH or VIL per Truth Table IOL = 4. S to Output Propagation Delay.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2. IIN = – 18 mA VCC = MIN.5 V V Min 2.7 V VCC = MAX. VIN = 7.

0 Unit V °C mA mA FAST AND LS TTL DATA 5-282 . the word length is easily expanded.SN54/74LS280 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS The SN54 / 74LS280 is a Universal 9-Bit Parity Generator / Checker. 5. 9 H = HIGH Level.75 – 55 0 Typ 5.5 5. 6. This design permits the LS280 to be substituted for the LS180 which results in improved performance.25 125 70 – 0.0 5. but the corresponding function is provided by an input at Pin 4 and the absence of any connection at Pin 3.4 4. It features odd / even outputs to facilitate either odd or even parity. 9-BIT ODD / EVEN PARITY GENERATORS/ CHECKERS LOW POWER SCHOTTKY • • • • • Generates Either Odd or Even Parity for Nine Data Lines Typical Data-to-Output Delay of only 33 ns Cascadable for n-Bits Can Be Used To Upgrade Systems Using MSI Parity Circuits Typical Power Dissipation = 80 mW INPUTS VCC 14 F 13 F G H 1 G 2 H 3 NC I E 12 E D 11 D C 10 C B 9 B A A 8 J SUFFIX CERAMIC CASE 632-08 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 ∑ ∑ EVEN ODD 4 5 6 7 ∑ GND I ∑ INPUT EVEN ODD OUTPUTS 14 1 D SUFFIX SOIC CASE 751A-02 INPUTS ORDERING INFORMATION FUNCTION TABLE NUMBER OF INPUTS A THRU 1 THAT ARE HIGH 0. 2.0 8. 8 1. The LS280 is designed without the expander input implementation. The LS280 has buffered inputs to lower the drive requirements to one LS unit load.0 25 25 Max 5. 7. By cascading. L = LOW Level OUTPUTS ∑EVEN H L ∑ODD L H SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 4. 74 54 74 Min 4. 3. 4.

IOH = MAX. nor for more than 1 second. IIN = – 18 mA VCC = MIN.7 3.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.65 3.5 0. VIN = 7.0 V) Limits Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay.5 – 0.7 V VCC = MAX.0 V VCC = MAX.0 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = VIH or VIL per Truth Table IOL = 4.4 V V 2.4 – 100 27 0.25 0.5 V V Min 2. VIN = VIL or VIH per Truth Table VCC = MAX. AC CHARACTERISTICS (TA = 25°C.8 – 1.SN54/74LS280 FUNCTIONAL BLOCK DIAGRAM A (8) B (9) (5) ∑ EVEN C (10) D E F (11) (12) (13) (6) ∑ ODD G H (1) (2) I (4) DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. Data to Output ΣODD Min Typ 33 29 23 31 Max 50 45 35 50 Unit ns CL = 15 pF ns Test Conditions FAST AND LS TTL DATA 5-283 . VIN = 2.5 0.0 mA IOL = 8.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2. Data to Output ΣEVEN Propagation Delay. VCC = 5.0 mA VCC = VCC MIN. VIN = 0.

L. The LS283 operates with either active HIGH or active LOW operands (positive or negative logic).5 U.L.L. B1 – B4) and a Carry Input (C0). 5 (2.25 U.5) U. for Military (54) and 5 U.) = 40 µA HIGH/1. It generates the binary Sum outputs (∑1 – ∑4) and the Carry Output (C4) from the most significant bit.L.L.L.L.0 U.L. 1.SN54/74LS283 4-BIT BINARY FULL ADDER WITH FAST CARRY The SN54 / 74LS283 is a high-speed 4-Bit Binary Full Adder with internal carry lookahead. LOGIC SYMBOL 5 3 14 12 6 2 15 11 A1 A2 A3 A4 B1 B2 B3 B4 7 C0 ∑1 ∑2 ∑3 ∑4 4 1 13 10 C4 9 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-284 . 0.L. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC NOTES: a) 1 TTL Unit Load (U. 0. 16 1 J SUFFIX CERAMIC CASE 620-09 1 Σ2 2 B2 3 A2 4 Σ1 5 A1 6 B1 7 C0 8 GND 16 1 N SUFFIX PLASTIC CASE 648-08 PIN NAMES LOADING (Note a) HIGH LOW 0.L. 10 U.L.5 U.L. 16 1 D SUFFIX SOIC CASE 751B-03 A1 – A4 B1–B4 C0 ∑1 – ∑4 C4 Operand A Inputs Operand B Inputs Carry Input Sum Outputs (Note b) Carry Output (Note b) 1.6 mA LOW. 0. It accepts two 4-bit binary words (A1 – A4. 5 (2. for Commercial (74) Temperature Ranges.L. 10 U.5 U.5) U. b) The Output LOW drive factor is 2.5 U.0 U. 4-BIT BINARY FULL ADDER WITH FAST CARRY LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 B3 15 A3 14 Σ3 13 A4 12 B4 11 Σ4 10 C4 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

FAST AND LS TTL DATA 5-285 . C0 + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = ∑1 + 2 ∑2 + 4 ∑3 + 8 ∑4 + 16C4 Where: (+) = plus Example: C0 logic levels Active HIGH Active LOW L 0 1 A1 L 0 1 A2 H 1 0 A3 L 0 1 A4 H 1 0 B1 H 1 0 B2 L 0 1 Due to the symmetry of the binary add function the LS283 can be used with either all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). can be arbitrarily assigned to pins 7. but must be held LOW when no carry in is intended. 5 or 3. A1.SN54/74LS283 LOGIC DIAGRAM C0 7 A1 5 B1 6 A2 3 B2 2 A3 14 B3 15 A4 12 B4 11 C1 C2 C3 4 ∑1 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS ∑2 1 ∑3 13 ∑4 10 9 C4 FUNCTIONAL DESCRIPTION The LS283 adds two 4-bit binary words (A plus B) plus the incoming carry. Carry Input can not be left open. thus C0. B1. The binary sum appears on the sum outputs (∑1 – ∑4) and outgoing carry (C4) outputs. B3 L 0 1 B4 H 1 0 ∑1 H 1 0 ∑2 H 1 0 ∑3 L 0 1 ∑4 L 0 1 C4 H 1 0 (10+9=19) (carry+5+6=12) Interchanging inputs of equal weight does not affect the operation. Note that with active HIGH inputs.

0 25 25 Max 5.5 4.4 VCC = MAX VCC = MAX VCC = MAX.4 – 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. 74 54 74 Min 4.75 – 55 0 Typ 5.2 – 0. IOH = MAX.7 mA Note 1: Not more than one output should be shorted at a time.0 0. VIN = 2 7 V MAX 2.1 0.5 5.5 20 40 V µA µA mA mA mA mA mA VCC = MAX.8 – 1.0 5. VIN = VIL or VIH per Truth Table VCC = MAX.25 0.0 2.SN54/74LS283 FUNCTIONAL TRUTH TABLE C (n – 1) L L L L H H H H An L L H H L L H H Bn L H L H L H L H ∑n L H H L H L L H Cn L L L H L H H H C1 – C3 are generated internally C0 is an external input C4 is an output generated internally GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. Output HIGH Total. nor for more than 1 second. VIN = 0 4 V MAX 0.65 3.5 V V Min 2.0 mA VCC = VCC MIN.8 – 100 34 39 0. VIN = VIH or VIL per Truth Table IOL = 4.5 0. IIN = – 18 mA VCC = MIN.0 mA IOL = 8. Output LOW – 20 0.4 4.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. VIN = 7 0 V MAX 7. 74 VOL Output LOW Voltage 74 C0 Any A or B IIH Input HIGH Current C0 Any A or B IIL IOS ICC Input LOW Current C0 Any A or B Short Circuit Current (Note 1) Power Supply Current Total.7 3.5 – 0.0 8.5 0.4 V V 2. FAST AND LS TTL DATA 5-286 .35 0.25 125 70 – 0.

3 V VOUT tPHL VIN VOUT 1.3 V tPLH 1. VCC = 5.3 V tPHL 1.SN54/74LS283 AC CHARACTERISTICS (TA = 25°C. C0 Input to C4 Output Propagation Delay.3 V tPLH VIN Figure 1 Figure 2 FAST AND LS TTL DATA 5-287 . C0 Input to Any Σ Output Propagation Delay.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay. Any A or B Input to C4 Output Min Typ 16 15 15 15 11 11 11 12 Max 24 24 24 24 17 22 17 17 Unit ns ns CL = 15 pF Figures 1 & 2 ns ns Test Conditions AC WAVEFORMS 1. Any A or B Input to Σ Outputs Propagation Delay.

25 U.L. c) The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 Input of the device.L. LS290) Inputs Output from ÷ 2 Section (Notes b & c) Outputs from ÷ 5 & ÷ 8 Sections (Note b) CP0 CP1 CP1 MR1. 0.05 U. Clock (Active LOW going edge) Input to ÷ 8 Section (LS293).L. 0.05 U. . 0. MS2 Q0 Q1.L. Q2. FAST AND LS TTL DATA 5-288 .05 U. b) The Output LOW drive factor is 2. Each section can be used separately or tied together (Q to CP)to form BCD.5 U. J SUFFIX CERAMIC CASE 632-08 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 LS290 14 1 MS VCC 14 2 NC MR 13 3 MS MR 12 4 Q2 CP1 11 5 Q1 CP0 10 6 NC Q0 9 7 GND Q3 8 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LS293 1 NC 2 NC 3 NC 4 Q2 5 Q1 6 NC 7 GND LOADING (Note a) HIGH LOW 1. PIN NAMES Clock (Active LOW going edge) Input to ÷ 2 Section.0 U.L.L.DECADE COUNTER. Each counter has a divide-by-two section and either a divide-by-five (LS290) or divide-by-eight (LS293) section which are triggered by a HIGH-to-LOW transition on the clock inputs.5 U. Q3 0.L. 4-BIT BINARY COUNTER LOW POWER SCHOTTKY • • • • • Corner Power Pin Versions of the LS90 and LS93 Low Power Consumption .L. . 10 U.L.L.5) U.L. for Commercial (74) Temperature Ranges.) = 40 µA HIGH/1.L.5 U. 0. MR2 MS1. .5) U. Clock (Active LOW going edge) Input to ÷ 5 Section (LS290).L. Typically 42 MHz Choice of Counting Modes . NOTES: a) 1 TTL Unit Load (U. 2.25 U. or Modulo-16 counters. SN54/74LS290 SN54/74LS293 DECADE COUNTER. .L.6 mA LOW. and the LS290 also has a 2-input gated Master Set (Preset 9). BCD. 5 (2.L. Bi-Quinary. Typically 45 mW High Count Rates .L.0 U. 10 U. 1. Binary Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 MR 13 MR 12 CP1 11 CP0 10 Q0 9 Q3 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. Both of the counters have a 2-input gated Master Reset (Clear). Master Reset (Clear) Inputs Master Set (Preset-9. 5 (2. . 0. for Military (54) and 5 U.L. Bi-quinary. 4-BIT BINARY COUNTER The SN54 / 74LS290 and SN54 / 74LS293 are high-speed 4-bit ripple type counters partitioned into two sections. 0. .5 U.

3. 2.SN54/74LS290 D SN54/74LS293 LOGIC SYMBOL LS290 1 3 1 2 MS CP0 CP1 MR 1 2 12 13 9 5 4 8 Q0 Q1 Q2 Q3 LS293 10 11 10 11 CP0 CP1 MR 1 2 12 13 9 5 4 8 Q0 Q1 Q2 Q3 VCC = PIN 14 GND = PIN 7 NC = PINS 2. 6 LOGIC DIAGRAMS MS1 MS2 1 LS290 3 10 J SD Q CD Q J Q J Q R SD Q CP0 CP CP KC Q D CP KC Q D CP SC Q D 11 CP1 MR1 MR2 12 9 13 5 4 8 VCC = PIN 14 GND = PIN 7 = PIN NUMBERS Q3 Q0 Q1 Q2 LS293 10 J Q J Q J Q J Q CP0 CP K Q CD 11 CP K Q CD CP K Q CD CP K Q CD VCC = PIN 14 GND = PIN 7 = PIN NUMBERS Q3 CP1 MR1 MR2 12 9 13 5 4 8 Q0 Q1 Q2 FAST AND LS TTL DATA 5-289 . 6 VCC = PIN 14 GND = PIN 7 NC = PINS 1.

A gated AND asynchronous Master Set (MS1 ⋅ MS2) is provided on the LS290 which overrides the clocks and the MR inputs and sets the outputs to nine (HLLH). and 4-Bit Binary counters respectively. and 16 are performed at the Q0. B. and 8 are available at the Q1. 4. FAST AND LS TTL DATA 5-290 . The input count pulses are applied to input CP0. Each device consists of four master / slave flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five (LS290) or divide-by-eight (LS293) section. Each section has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW clock transition. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter. B. Q2. The Q0 output of each device is designed and specified to drive the rated fan-out plus the CP1 input of the device. BCD Decade (8421) Counter — the CP1 input must be LS290 MODE SELECTION RESET/SET INPUTS MR1 H H X L X L X MR2 H H X X L X L MS1 L X H L X X L MS2 X L H X L L X Q0 L L H OUTPUTS Q1 L L L Q2 Q3 L L H MR1 H L H L externally connected to the Q0 output. and Q3 outputs as shown in the truth table. 4. Divide-By-Two and Divide-By-Five Counter — No external interconnections are required. Since the output from the divide-by-two section is not internally connected to the succeeding stages. and Q3 outputs. The first flip-flop is used as a binary element for the divide-by-two function (CP0 as the input and Q0 as the output). The CP0 input receives the incoming count and a BCD count sequence is produced. Q2.SN54/74LS290 D SN54/74LS293 FUNCTIONAL DESCRIPTION The LS290 and LS293 are 4-bit ripple type Decade. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Note: Output Q0 connected to input CP1. LS293 MODE SELECTION RESET INPUTS MR2 H H L L Q0 L OUTPUTS Q1 L Q2 Q3 L L L L Count Count Count Count L Count Count Count TRUTH TABLE OUTPUT COUNT Q0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 L H L H L H L H L H L H L H L H Q1 L L H H L L H H L L H H L L H H Q2 L L L L H H H H L L L L H H H H Q3 L L L L L L L L H H H H H H H H LS290 BCD COUNT SEQUENCE COUNT 0 1 2 3 4 5 6 7 8 9 OUTPUT Q0 L H L H L H L H L H Q1 L L H H L L H H L L Q2 L L L L H H H H L L Q3 L L L L L L L L H H NOTE: Output Q0 is connected to Input CP1 for BCD count. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. The input count is then applied to the CP1 input and a divide-by-ten square wave is obtained at output Q0. Simultaneous division of 2. LS293 A. 3-Bit Ripple Counter — The input count pulses are applied to input CP1. 8. Q1. the devices may be operated in various counting modes: LS290 A. A gated AND asynchronous Master Reset (MR1 ⋅ MR2) is provided on both counters which overrides the clocks and resets (clears) all the flip-flops. Simultaneous frequency divisions of 2. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3 output must be externally connected to the CP0 input. Therefore. 4-Bit Ripple Counter — The output Q0 must be externally connected to input CP1. C. decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. The CP1 input is used to obtain binary divide-by-five operation at the Q3 output.

0 mA IOL = 8. IIN = – 18 mA VCC = MIN. VIN = 7.1 Input LOW Current MS.75 – 55 0 Typ 5.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.7 3. nor for more than 1 second.4 –2. FAST AND LS TTL DATA 5-291 .6 – 100 15 0.5 0. MR CP0 CP1 (LS290) CP1 (LS293) Short Circuit Current (Note 1) Power Supply Current –20 –0.SN54/74LS290 • SN54/74LS293 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.65 3. VIN = 2.5 – 0.4 –3.5 4.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 0.25 125 70 – 0. IOH = MAX.5 20 IIH V µA mA 2.5 5.2 –1.4 4.0 25 25 Max 5.5 V V Min 2.25 0. 74 54 74 Min 4.0 V IIL mA VCC = MAX.8 – 1.4 V V 2. VIN = VIL or VIH per Truth Table VCC = MAX.5 0.7 V VCC = MAX.4 V IOS ICC mA mA VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.35 0. VIN = 0.0 mA VCC = VCC MIN. VIN = VIH or VIL per Truth Table IOL = 4.0 8.0 5.

CP0 Input to Q0 Output CP0 Input to Q3 Output CP1 Input to Q1 Output CP1 Input to Q2 Output CP1 Input to Q3 Output MS Input to Q0 and Q3 Outputs MS Input to Q1 and Q2 Outputs MR Input to Any Output Min 32 16 10 12 32 34 10 14 21 23 21 23 20 26 26 16 18 48 50 16 21 32 35 32 35 30 40 40 26 40 Typ Max Min 32 16 10 12 46 46 10 14 21 23 34 34 16 18 70 70 16 21 32 35 51 51 LS293 Typ Max Unit MHz MHz ns ns ns ns ns ns ns ns AC SETUP REQUIREMENTS (TA = 25°C. VCC = 5.3 V Figure 1 *The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.SN54/74LS290 D SN54/74LS293 AC CHARACTERISTICS (TA = 25°C.0 V.3 V CP Q0 ⋅ Q3 (LS290) tPLH 1.3 V CP tPHL Q 1. CL = 15 pF) Limits LS290 Symbol fMAX fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL tPHL Parameter CP0 Input Clock Frequency CP1 Input Clock Frequency Propagation Delay.3 V tPLH 1.3 V tW 1. VCC = 5.3 V Figure 2 Figure 3 FAST AND LS TTL DATA 5-292 .3 V trec 1. MR & MS 1. AC WAVEFORMS *CP 1.3 V tW 1.3 V trec 1.3 V 1.3 V tW tPHL Q 1.0 V) Limits LS290 Symbol tW tW tW tW trec CP0 Pulse Width CP1 Pulse Width MS Pulse Width MR Pulse Width Recovery Time MR to CP Parameter Min 15 30 15 15 25 15 25 Max LS293 Min 15 30 Max Unit ns ns ns ns ns RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition form HIGH-to-LOW in order to recognize and transfer HIGH data to the Q outputs.3 V MS 1.

10 U. 5 (2.5 U. The LS298 is fabricated with the Schottky barrier process for high speed and is completely compatible with all Motorola TTL families.6 mA LOW.) The selected data is transferred to the output register synchronous with the HIGH to LOW transition of the Clock input.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.25 U.L.25 U.L. 0.L.L.5 U. LOW 0.25 U.25 U.5 U. SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 3 2 4 1 9 5 7 6 NOTES: a) 1 TTL Unit Load (U. 1 N SUFFIX PLASTIC CASE 648-08 16 1 I1b 2 I1a 3 I0a 4 I0b 5 I1c 6 I1d 7 I0d 8 GND 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION PIN NAMES LOADING (Note a) HIGH S CP I0a – I0d I1a – I1d Qa – Qd Common Select Input Clock (Active LOW Going Edge) Input Data Inputs From Source 0 Data Inputs From Source 1 Register Outputs (Note b) 0. 0. 0.5 U. 0.L.L.L.L. 0. A Common Select input selects between two 4-bit input ports (data sources. 0. QUAD 2-INPUT MULTIPLEXER WITH STORAGE LOW POWER SCHOTTKY • • • • Select From Two Data Sources Fully Edge-Triggered Operation Typical Power Dissipation of 65 mW Input Clamp Diodes Limit High Speed Termination Effects 16 1 J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Qa 15 Qb 14 Qc 13 Qd 12 CP 11 S 10 I0c 9 16 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L.) = 40 µA HIGH/1.5) U.SN54/74LS298 QUAD 2-INPUT MULTIPLEXER WITH STORAGE The SN54 / 74LS298 is a Quad 2-Port Register. b) The Output LOW drive factor is 2. It is the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. 10 11 I0a I1a I0b I1b I0c I1c I0d I1d S CP Qa Qb Qc Qd 15 14 13 12 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-293 .L.5 U.L.

5 5.5 4.4 4.75 – 55 0 Typ 5. It selects four bits of data from two sources (ports)under the control of a Common Select Input (S). The selected data is transferred to the 4-bit output register synchronous with the HIGH to LOW transition of the Clock input (CP).0 25 25 Max 5. The Data inputs (I) and Select input (S) must be stable only one setup time prior to the HIGH to LOW transition of the clock for predictable operation. The 4-bit output register is fully edge-triggered. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.0 5.SN54/74LS298 LOGIC OR BLOCK DIAGRAM I1a 2 I0a 3 I1b 1 I0b 4 I1c 5 I0c 9 I1d 6 I0d 7 S 10 CP 11 R CP S Qa 15 R CP S Qb 14 R CP S Qc 13 R CP S Qd 12 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Qa Qb Qc Qd FUNCTIONAL DESCRIPTION The LS298 is a high speed Quad 2-Port Register. 74 54 74 Min 4.0 Unit V °C mA mA FAST AND LS TTL DATA 5-294 . h = HIGH Voltage Level one setup time prior to the HIGH to LOW clock transition.0 8.25 125 70 – 0. TRUTH TABLE INPUTS S I I h h I0 I h X X I1 X X I h OUTPUT Q L H L H L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care I = LOW Voltage Level one setup time prior to the HIGH to LOW clock transition.

VIN = VIL or VIH per Truth Table VCC = MAX.4 – 100 21 0.0 V) Limits Symbol tW ts ts th th Parameter Clock Pulse Width Data Setup Time Select Setup Time Data Hold Time Select Hold Time Min 20 15 25 5. VIN = 0.5 0. nor for more than 1 second.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.0 0 Typ Max Unit ns ns ns ns VCC = 5.8 – 1. FAST AND LS TTL DATA 5-295 . VIN = 2. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. CL = 15 pF AC SET-UP REQUIREMENTS (TA = 25°C.0 mA VCC = VCC MIN. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition.5 V V Min 2.4 V V 2. AC CHARACTERISTICS (TA = 25°C.5 – 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 V.0 mA IOL = 8.25 0.65 3.35 0. g y Clock to Output Min Typ 18 21 Max 27 32 Unit ns ns Test Conditions VCC = 5.7 V VCC = MAX.SN54/74LS298 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54.0 V Test Conditions DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. VIN = VIH or VIL per Truth Table IOL = 4. IOH = MAX. VIN = 7. VCC = 5.0 V VCC = MAX.0 0. IIN = – 18 mA VCC = MIN.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.5 0.7 3.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.0 V) Limits Symbol tPLH tPHL Parameter Propagation Delay. VCC = 5.

3 V Q 1.3 V 1.3 V tPHL S* ts(L) CP 1.3 V th(H) = 0 ts(H) 1.3 V Q Q = I0 Q = I1 *The shaded areas indicate when the input is permitted to *change for predictable output performance.3 V th(L) = 0 1.3 V th(L) tW(L) tW(H) tPLH 1.3 V 1.3 V 1. Figure 1 Figure 2 FAST AND LS TTL DATA 5-296 .3 V th(H) ts(H) 1.SN54/74LS298 AC WAVEFORMS I0 I1* ts(L) CP 1.

SN54/74LS299 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS299 is an 8-Bit Universal Shift / Storage Register with 3-state outputs.5 U. 0. 1 U.L.L.L. Four modes of operation are possible: hold (store). 65 (25) U. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins.L.L.5 U.25 U. 0. 0.25 U.) = 40 µA HIGH/1. A separate active LOW Master Reset is used to reset the register. for Military (54) and 65 U.L. for Commercial (74) Temperature Ranges.L.25 U.5) U. 0. The Output HIGH drive factor is 25 U.5 U.L. shift right and load data. 0.25 U. 0.L for Military (54) and 15 U. 5 (2.L. OE2 Q0. FAST AND LS TTL DATA 5-297 .5 U. 15 (7.5 U.L. 10 U.L.5 U. 0.L.L. 0.25 U.5 U. 0. Shift Right. shift left. S1 Clock Pulse (active positive-going edge) Input Serial Data Input for Right Shift Serial Data Input for Left Shift Parallel Data Input or Parallel Output (3-State) (Note c) 3-State Output Enable (active LOW) Inputs Serial Outputs (Note b) Asynchronous Master Reset (active LOW) Input Mode Select Inputs LOADING (Note a) LOW 0. b) The Output LOW drive factor is 2. NOTES: a) 1 TTL Unit Load (U. 0. 0. 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY • Common I/O for Reduced Pin Count • Four Operation Modes: Shift Left. for Commercial (74). Q7 MR S0. for Commercial (74) Temperature Ranges.L.L.L.25 U.L.5 U.L for Military (54) and 5 U.5) U. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading.L. 0.L.6 mA LOW. Load and Store • Separate Shift Right Serial Input and Shift Left Serial Input for Easy Cascading • 3-State Outputs for Bus Oriented Applications • Input Clamp Diodes Limit High-Speed Termination Effects • ESD > 3500 Volts 20 1 J SUFFIX CERAMIC CASE 732-03 20 N SUFFIX PLASTIC CASE 738-03 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC S1 20 19 Ds7 18 Q7 17 I/O7 I/O5 I/O3 I/O1 CP 16 15 14 13 12 DS0 11 20 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L. 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC 1 S0 2 3 4 5 6 8 7 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 9 10 MR GND PIN NAMES HIGH CP DS0 DS7 I/On OE1. c) The Output LOW drive factor is 7.L.5 U.L.L.

D→Q0. Q0 = Q7 = LOW Reset I/O Voltage Undetermined Asynchronous Reset.SN54/74LS299 LOGIC DIAGRAM S1 19 S0 1 18 DS7 DS0 11 12 CLOCK Q0 MR OE1 OE2 8 9 2 3 D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q 17 Q7 VCC = PIN 20 GND = PIN 10 = PIN NUMBERS 7 13 6 14 5 15 4 16 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 FUNCTION TABLE INPUTS MR L L L L L H H H H H H H H S1 X X H L X L L H H H L L L S0 X X H X L H H L L H L L L OE1 H X X L L X L X L X H X L OE2 X H X L L X L X L X X H L X X X CP X X X X X DS0 X X X X X D D X X X X X X DS7 X X X X X X X D D X X X X Asynchronous Reset. D→Q7. D→Q0 & I/O0.0 5. Q7 I/O0 – I/O7 I/O0 – I/O7 I/O0 – I/O7 I/O0 – I/O7 Parameter 54 74 54 74 54. Q7→Q6. Shift Left. etc.4 4.0 8. etc. Shift Left.0 – 1.0 25 25 Max 5. Q0 = Q7 = LOW I/O Voltage LOW Shift Right. D→Q7 & I/O7.25 125 70 – 0. Q7→Q6 & I/O6. Shift Right.5 5.6 12 24 Unit V °C mA mA mA mA FAST AND LS TTL DATA 5-298 . Q0→O1 & I/O1. Q0→Q1. Parallel Load. Q7 Q0.75 – 55 0 Typ 5. etc. Q7 Q0. I/On→Qn Hold: I/O Voltage undetermined Hold: I/On = Qn RESPONSE H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Output Current — High Output Current — Low Q0. 74 54 74 54 74 54 74 Min 4.5 4.0 – 2. etc.

4 0.2 0.4 2. 74 74 54. VIN = 2.35 0.5 V VCC = MAX. IOH = MAX MIN IOL = 12 mA IOL = 24 mA IOL = 4. VIN = 0 4 V MAX 0. VIN = VIL or VIH per Truth Table VCC = VCC MIN.SN54/74LS299 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Voltage g I/O0 – I/O7 Output HIGH Voltage g Q0.4 0. nor for more than 1 second.1 – 0. VOUT = 2. VOUT = 0. I/O0 – I/O7 IIH Input HIGH C I t Current t Others S0. VIN = 5.7 V VCC = MAX. 74 74 2.5 0.1 3.5 40 – 400 20 40 0.0 mA IOL = 8.2 3.7 – 0.4 2.4 0. IIN = – 18 mA VOH VOL VOL IOZH IOZL VCC = MAX. S1 I/O0 – I/O7 Others IIL IOS Input LOW Current S0.4 0.0 mA VCC = VCC MIN.0 0.1 0. S1.4 V ICC Note 1: Not more than one output should be shorted at a time.65 3. Q7 I/O0 – I/O7 – 20 – 30 – 0. VIN = VIL or VIH per Truth Table VCC = MIN. Q7 Output LOW Voltage g I/O0 – I/O7 Output LOW Voltage g I/O0 – I/O7 Output Off Current HIGH I/O0 – I/O7 Output Off Current LOW I/O0 – I/O7 Others S0.25 0.4 3. IOH = MAX MIN Min 2. FAST AND LS TTL DATA 5-299 .0 VCC = MAX.5 V V V V V V V V V µA µA µA µA mA mA mA mA VCC = MAX.4 VCC = MAX VCC = MAX VCC = MAX VCC = MAX. S1 Short Circuit Current (Note 1) Power Supply Current Q0.8 –100 –130 53 mA mA mA mA 54 74 54 74 54.8 – 1.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.5 2. VIN = 7 0 V MAX 7.7 V VCC = MIN.

Clock to I/O0 – I/O7 Propagation Delay. Clear to Q0 or Q7 Propagation Delay.0 Test Conditions FAST AND LS TTL DATA 5-300 .0 V) Limits Symbol tW tW tW ts ts th th trec Parameter Clock Pulse Width HIGH Clock Pulse Width LOW Clear Pulse Width LOW Data Setup Time Select Setup Time Data Hold Time Select Hold Time Recovery Time Min 25 13 20 20 35 0 10 20 Typ Max Unit ns ns ns ns ns ns ns ns VCC = 5 0 V 5.SN54/74LS299 AC CHARACTERISTICS (TA = 25°C. Clear to I/O0 – I/O7 Output Enable Time Output Disable Time Min 25 Typ 35 26 22 27 26 17 26 13 19 10 10 39 33 40 39 25 40 21 30 15 15 Max Unit MHz ns ns ns ns ns ns CL = 5. VCC = 5. RL = 667 Ω CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C. VCC = 5.0 V) Limits Symbol fMAX tPHL tPLH tPHL tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay.0 pF CL = 45 pF. Clock to Q0 or Q7 Propagation Delay.

3 V tPLH 1. Figure 5 FAST AND LS TTL DATA 5-301 .5 V ≥ VOH ≈ 1.5 V VOUT tPHZ 1.5 V Figure 3 Figure 4 AC LOAD CIRCUIT VCC RL SW1 tPZH tPZL TO OUTPUT UNDER TEST tPLZ tPHZ SWITCH POSITIONS SYMBOL SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed 5 kΩ CL* SW2 * Includes Jig and Probe Capacitance.3 V VIN 1.SN54/74LS299 3-STATE WAVEFORMS VIN 1.3 V VOUT 1.5 V tPLZ ≈ 1.3 V tPHL 1.5 V VOL VE 1.3 V tPHL 1.5 V VE tPZH 1.5 V VE VOUT tPZL 1.5 V 1.5 V 0.3 V tPLH 1.3 V Figure 1 Figure 2 VE 1.5 V 0.3 V VOUT 1.

6 12 24 Unit V °C mA mA mA mA FAST AND LS TTL DATA 5-302 .0 5. 74 54 74 54 74 54 74 Min 4.4 4. The data extend function repeats the sign in the QA flip-flop during shifting.5 4. The output enable does not affect synchronous operation of the register.75 – 55 0 Typ 5. An overriding clear input clears the internal registers when taken low whether the outputs are enabled or off. Data is entered on the low-to-high clock transition. A serial output is also provided. This places the three-state input / output ports in the data input mode.SN54/74LS322A 8-BIT SHIFT REGISTERS WITH SIGN EXTEND These 8-bit shift registers have multiplexed input/output data ports to accomplish full 8-bit data handling in a single 20-pin package.0 25 25 Max 5. Serial data may enter the shift-right register through either D0 or D1 inputs as selected by the data select pin.0 8.5 5. 8-BIT SHIFT REGISTERS WITH SIGN EXTEND LOW POWER SCHOTTKY • • • • Multiplexed Inputs / Outputs Provide Improved Bit Density Sign Extend Function Direct Overriding Clear 3-State Outputs Drive Bus Lines Directly (TOP VIEW) DATA SIGN VCC SELECT EXTEND D1 B/QB D/QD F/QF H/QH Q/H CLOCK 20 1 J SUFFIX CERAMIC CASE 732-03 20 19 DS G S/P 18 SE 17 D1 16 B/QB 15 D/QD 14 F/QF 13 12 11 20 1 N SUFFIX PLASTIC CASE 738-03 H/GH Q/H CK D0 A/QA C/QC E/QE G/QG OE CLR 20 1 DW SUFFIX SOIC CASE 751D-03 1 2 3 D0 4 5 6 7 8 9 10 REGISTER S/P ENABLE A/QA C/QC E/QE G/QG OUTPUT CLEAR GND ENABLE ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Output Current — High Output Current — Low Q H′ Q H′ Q H′ QA– QH QA– QH QA– QH QA– QH Parameter 54 74 54 74 54.25 125 70 – 0.0 – 2.0 – 1. Synchronous parallel loading is achieved by taking the register enable and the S / P inputs low.

before the most recent ↑ transition of the clock D0. the register is cleared while the eight input/output terminals are disabled to the high-impedance state. including transitions) ↑ = Transition from LOW to HIGH level QA0…QH0 = the level of QA through QH. the eight input/output terminals are disabled to the high-impedance state. D1 = the level of steady-state inputs at inputs D0 and D1 respectively a…h = the level of steady-state inputs at inputs A through H respectively FAST AND LS TTL DATA 5-303 .SN54/74LS322A BLOCK DIAGRAM REGISTER ENABLE G S/P SIGN EXTEND SE (1) (2) (18) (17) DATA D1 (19) SELECT DS (3) D0 Q CK D Q CLR CLOCK CLEAR OUTPUT ENABLE OE (11) (9) (8) Q CK D Q CLR FOUR IDENTICAL CHANNELS NOT SHOWN Q CK D Q CLR Q CK D Q CLR (12) QH (4) A/QA (16) B/QB (7) G/QG (13) H/QH FUNCTION TABLE INPUTS OPERATION CLEAR Clear Hold Shift Right Sign Extend Load L L H H H H H REGISTER ENABLE H X H L L L L S/P X H X H H H L SIGN EXTEND X X X H H L X DATA SELECT X X X L H X X OUTPUT ENABLE L L L L L L X CLOCK X X X ↑ ↑ ↑ ↑ INPUTS/OUTPUTS A/QA L L QA0 D0 D1 QAn a B/QB L L QB0 QAn QAn QAn b C/QC … H/QH L L QC0 QBn QBn QBn c L L QH0 QGn QGn QGn h OUTPUT Q H′ L L QH0 QGn QGn QGn h When the output enable is high. respectively. before the indicated steady-state conditions were established QAn…QHn = the level of QA through QH. If both the register enable input and the S/P input are low while the clear input is low. sequential operation or clearing of the register is not affected. respectively. H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant (any input. however.

4 2.0 mA VCC = VCC MIN. nor for more than 1 second.3 0. VIN = 5. VIN = 2.2 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. Data Select Sign Extend IIH Input HIGH C I t Current t Other Data Select Sign Extend A–H Other IIL Input LOW Current Data Select Sign Extend IOS ICC Short Circuit Current (Note 1) Power Supply Current Q H′ QA– QH – 20 – 30 54 74 54 74 54. 74 74 54. VIN = VIL or VIH per Truth Table VCC = MIN. VIN = VIL or VIH per Truth Table VCC = VCC MIN.7 V VCC = MAX.0 mA IOL = 8. VOUT = 0.4 V VCC = MAX.5 V V V V V V V V V µA µA µA µA µA mA mA mA mA mA mA mA mA mA mA VCC = MAX VCC = MAX VCC = MAX VCC = MAX. VIN = 0.7 V VCC = MIN.5 2. FAST AND LS TTL DATA 5-304 .4 3. IOH = MAX MIN Min 2. 74 74 2.4 0.2 3.5 40 – 400 20 40 60 0.25 0.1 0.4 2.35 0.4 – 0.0 V VCC = MAX.65 3. VIN = 7.1 – 0.5 V VCC = MAX. IOH = MAX MIN IOL = 12 mA IOL = 24 mA IOL = 4.7 – 0.5 0. VOUT = 2. IIN = – 18 mA VOH VOL VOL IOZH IOZL VCC = MAX.2 –100 –130 60 0.8 – 1.SN54/74LS322A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Voltage g QA– QH Output HIGH Voltage g Q H′ Output LOW Voltage g QA– QH Output LOW Voltage g Q H′ Output Off Current HIGH QA– QH Output Off Current LOW QA– QH Other A – H.2 3.4 0.8 – 1.0 0.4 V Note 1: Not more than one output should be shorted at a time.4 0.

VCC = 5.0 pF CL = 45 pF.SN54/74LS322A AC CHARACTERISTICS (TA = 25°C. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RL = 667 Ω CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C. Clear to QA– QH Output Enable Time Output Disable Time Min 25 Typ 35 26 22 27 22 16 22 15 15 15 15 35 33 35 33 25 35 35 35 25 25 Max Unit MHz ns ns ns ns ns ns CL = 5. Clock to QA– QH Propagation Delay.0 Test Conditions DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. FAST AND LS TTL DATA 5-305 .0 V) Limits Symbol fMAX tPHL tPLH tPHL tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay. VCC = 5. Clock to QH′ Propagation Delay.0 V) Limits Symbol tW tW tW ts ts th th trec Parameter Clock Pulse Width HIGH Clock Pulse Width LOW Clear Pulse Width LOW Data Setup Time Select Setup Time Data Hold Time Select Hold Time Recovery Time Min 25 15 20 20 15 0 10 20 Typ Max Unit ns ns ns ns ns ns ns ns VCC = 5 0 V 5. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH Data to the Q outputs. Clear to QH′ Propagation Delay.

5 U.L.5) U. S1 SR Clock Pulse (active positive going edge) Input Serial Data Input for Right Shift Serial Data Input for Left Shift Parallel Data Input or Parallel Output (3-State) (Note c) 3-State Output Enable (active LOW) Inputs Serial Outputs (Note b) Mode Select Inputs Synchronous Reset (active LOW) Input LOADING (Note a) LOW 0.L. Shift Right. 0.0 U.5 U. c) The output LOW drive factor is 7.L.5 U. 5 (2. 0.L. 15 (7. 1 U. and parallel load. All modes are activated on the LOW-to-HIGH transition of the Clock.L.L. Its function is similar to the SN54 / 74LS299 with the exception of Synchronous Reset. for Commercial Temperature Ranges.25 U.5 U. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count.L. for Commercial Temperature Ranges.L.L. 10 U. 0.L.L. Four operation modes are possible: hold (store).L. 0.SN54/74LS323 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS323 is an 8-Bit Universal Shift / Storage Register with 3-state outputs. shift right. OE2 Q0. Parallel Load and Store • Separate Continuous Inputs and Outputs from Q0 and Q7 Allow Easy • • • • Cascading Fully Synchronous Reset 3-State Outputs for Bus Oriented Applications Input Clamp Diodes Limit High-Speed Termination Effects ESD > 3500 Volts 20 1 J SUFFIX CERAMIC CASE 732-03 20 N SUFFIX PLASTIC CASE 738-03 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC S1 20 19 DS7 Q7 18 17 I/O7 I/O5 I/O3 I/O1 CP 16 15 14 13 12 DS0 11 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.5 U. 0. 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY • Common I/O for Reduced Pin Count • Four Operation Modes: Shift Left.25 U. 20 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC 1 S0 2 3 4 5 6 8 7 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 9 10 SR GND PIN NAMES HIGH CP DS0 DS7 I/On OE1.25 U. FAST AND LS TTL DATA 5-306 . NOTES: a) 1 TTL LOAD = 40 µA HIGH/1. The output HIGH drive factor is 25 U. for Commercial Temperature Ranges.L for Military (54) and 15 U. 0. 0.5 U.L. 0.5 U.L for Military (54) and 5 U. 0.25 U.25 U.L. Q7 S0.5 U. shift left.L.L.L.L. 65 (25) U. b) The output LOW drive factor is 2. for Military (54) and 65 U.L.L. 0. 1.6 mA LOW.L.5) U. Separate inputs and outputs are provided for flip-flops Q0 and Q7 to allow easy cascading.

I/O Voltage Undetermined Hold. This device is similar in operation to the SN54/74LS299 except for synchronous reset. etc. D→Q0 & I/O0. and the outputs of Q0–Q7 are in the high impedance state regardless of the state of OE1 or OE2. Q0 = Q7 = LOW I/O voltage LOW Shift Right. Q0→Q1 & I/O1. is that the mode control (S0. 2. TRUTH TABLE INPUTS SR L L L L L H H H H H H H H S1 X X H L X L L H H H L L L S0 X X H X L H H L L H L L L OE1 H X X L L X L X L X H X L OE2 X H X L L X L X L X X H L X X X CP DS0 X X X X X D D X X X X X X DS7 X X X X X X X D D X X X X Synchronous Reset. D→Q7. Shift Left. DS7. Parallel Load I/On→Qn Hold Hold. They use eight D-type edge-triggered flip-flops that respond only to the LOW-to-HIGH transition of the Clock (CP). S1) and data inputs (DS0. A partial list of the common features are described below: 1. etc. When S0 = S1 = 1. I/O0–I/O7 are parallel inputs to flip-flops Q0–Q7 respectively. D→Q0. The only timing restriction. therefore. I/On = Qn RESPONSE H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial FAST AND LS TTL DATA 5-307 . etc. Q0 = Q7 = LOW Reset I/O voltage undetermined Synchronous Reset. Shift Left. Q7→Q6. Q0→Q1. Q7→Q6 & I/O6. An important unique feature of the SN54/74LS323 is a fully Synchronous Reset that requires only to be stable at least one setup time prior to the positive transition of the Clock Pulse. Shift Right. etc. D→Q7 & I/O7. I/O0–I/O7) may be stable at least a setup time prior to the positive transition of the Clock Pulse.SN54/74LS323 S1 19 S0 1 LOGIC DIAGRAM 18 DS7 DS0 SR 12 11 9 CP Q0 8 D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q 17 Q7 OE1 OE2 2 3 7 13 6 14 5 15 4 16 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 FUNCTIONAL DESCRIPTION The logic diagram and truth table indicate the functional characteristics of the SN54/74LS323 Universal Shift/Storage Register.

65 3.2 3.4 VCC = MAX VCC = MAX VCC = MAX VCC = MAX.2 0.4 4. Q7 I/O0 – I/O7 – 20 – 30 54 74 54 74 54.5 0.75 – 55 0 Typ 5. VIN = 5. 74 74 54.0 – 1. Q7 Output LOW Voltage g I/O0 – I/O7 Output LOW Voltage g Q0 – Q7 Output Off Current HIGH I/O0 – I/O7 Output Off Current LOW I/O0 – I/O7 Others S0.35 0. 74 74 2. 74 54 74 54 74 54 74 Min 4. VIN = 2.5 5.25 125 70 – 0.0 25 25 Max 5.4 V ICC Note 1: Not more than one output should be shorted at a time. IIN = – 18 mA VOH VOL VOL IOZH IOZL VCC = MAX.1 3.8 –100 –130 53 0. VOUT = 2.1 0.5 40 – 400 20 40 0.7 – 0.25 0. VIN = 7 0 V MAX 7.4 2.SN54/74LS323 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Output Current — High Output Current — Low Q0.0 8.4 2. IOH = MAX MIN IOL = 12 mA IOL = 24 mA IOL = 4.0 mA VCC = VCC MIN.0 mA IOL = 8. FAST AND LS TTL DATA 5-308 .4 3.6 12 24 Unit V °C mA mA mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Voltage g I/O0 – I/O7 Output HIGH Voltage g Q0. Q7 I/O0 – I/O7 I/O0 – I/O7 I/O0 – I/O7 I/O0 – I/O7 Parameter 54 74 54 74 54. IOH = MAX MIN Min 2.0 VCC = MAX. I/O0 – I/O7 IIH I t t Input HIGH C Current Others S0.4 0. Q7 Q0. VIN = VIL or VIH per Truth Table VCC = MIN. Q7 Q0.5 4.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. VIN = VIL or VIH per Truth Table VCC = VCC MIN.4 0. S1 Qo.0 – 2.0 0.5 2.4 – 0.8 – 1.4 0.7 V VCC = MIN.0 5. S1 I/O0 – I/O7 Input LOW Current IIL IOS Short Circuit Current (Note 1) Power Supply Current Others S0.5 V VCC = MAX. nor for more than 1 second.7 V VCC = MAX. S1.1 – 0. VIN = 0 4 V MAX 0.5 V V V V V V V V V µA µA µA µA mA mA mA mA mA mA mA mA VCC = MAX. VOUT = 0.

0 pF AC SETUP REQUIREMENTS (TA = 25°C.SN54/74LS323 AC CHARACTERISTICS (TA = 25°C.0 Test Conditions FAST AND LS TTL DATA 5-309 .0 V) Limits Symbol tW tW tW ts ts th th trec Parameter Clock Pulse Width HIGH Clock Pulse Width LOW Clear Pulse Width LOW Data Setup Time Select Setup Time Data Hold Time Select Hold Time Recovery Time Min 25 15 20 20 35 0 10 20 Typ Max Unit ns ns ns ns ns ns ns ns VCC = 5 0 V 5. VCC = 5. VCC = 5. Clock to Q0 or Q7 Propagation Delay. Clock to I/O0 – I/O7 Output Enable Time Output Disable Time Min 25 Typ 35 26 22 25 17 14 20 10 10 39 33 39 25 21 30 15 15 Max Unit MHz ns ns ns ns CL = 45 pF. RL = 667 Ω CL = 15 pF Test Conditions CL = 5.0 V) Limits Symbol fMAX tPHL tPLH tPHL tPLH tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay.

5 V 0.3 V tPLH 1.SN54/74LS323 3-STATE WAVEFORMS VIN tPHL 1.5 V VOL VE 1.3 V VIN 1.5 V VE VOUT tPZL 1.3 V VOUT 1.3 V tPHL 1.5 V 1.3 V VOUT 1.5 V 0.5 V VOUT tPHZ 1.3 V tPLH 1.3 V Figure 1 Figure 2 VE 1.5 V VE tPZH 1.3 V 1.5 V Figure 3 Figure 4 AC LOAD CIRCUIT VCC RL SW1 SWITCH POSITIONS SYMBOL tPZH SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed TO OUTPUT UNDER TEST tPZL tPLZ tPHZ 5 kΩ CL* SW2 * Includes Jig and Probe Capacitance.5 V ≥ VOH ≈ 1.5 V tPLZ ≈ 1. Figure 5 FAST AND LS TTL DATA 5-310 .

A1 and A2 are three-state outputs. The outputs (A0 – A2) and inputs (0 – 7) are active low. Both of these occurrences happen when the EI input goes from a logical one to a logical zero and all data inputs (0 – 7) are held at logical ones. and A2 and forces output GS to the high state and output EO to the low state. 2 and 4 were low. It serves to indicate when any of the inputs are active. A1 and A2 outputs to become momentarily enabled. Use of the EI input in conjunction with the EO output provides for the capability of having priority encoding of n input signals. OUTPUTS VCC 16 EO 15 EO 4 5 6 7 EI A2 GS 14 GS 3 13 3 INPUTS 2 12 2 1 11 1 0 10 0 A0 A1 OUTPUT A0 9 SN54/74LS348 SN54/74LS848 8-INPUT PRIORITY ENCODERS WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD 8 GND Ceramic Plastic SOIC 1 4 2 5 3 6 INPUTS 4 7 5 EI 6 A2 7 A1 OUTPUTS FUNCTION TABLE INPUTS EI H L L L L L L L L L 0 X H X X X X X X X L 1 X H X X X X X X L H 2 X H X X X X X L H H 3 X H X X X X L H H H 4 X H X X X L H H H H 5 X H X X L H H H H H 6 X H X L H H H H H H 7 X H L H H H H H H H A2 Z Z L L L L H H H H OUTPUTS A1 Z Z L L H H L L H H A0 Z Z L H L H L H L H GS H H L L L L L L L L EO H L H H H H H H H H H = HIGH Logic Level L = LOW Logic Level X = Irrelevant Z = High Impedance State FAST AND LS TTL DATA 5-311 . A1 ared A2 to the disabled state and outputs GS and EO to the high state.8-INPUT PRIORITY ENCODERS WITH 3-STATE OUTPUTS The SN54 / 74LS348 and the SN54 / 74LS848 are eight input priority encoders which provide the 8-line to 3-line function. The internal glitch reduction circuitry does add an additional fan-in of one on all data inputs (compared to that of the LS348). This allows for up to 64 line expansion without the need for special external circuitry. A1. A high on all data inputs (0 – 7) together with a low on the EI input disables outputs A0. A0. The GS (Group Signal) output is active low when any of the inputs are low. The active low input which has the highest priority (input 7 has the highest) is represented on the outputs (output A0 is the lowest bit). An example would be if inputs 1. The LS848 has special internal circuitry providing for a greatly reduced negative going glitch on the GS (Group Signal) output and on a reduced tendency for the A0. then a binary 4 would be represented on the outputs. A logical one on the Enable Input (EI) forces A0.

4 – 1.0 5.5 4. GS A0.0 – 2. A1.SN54/74LS348 • SN54/74LS848 BLOCK DIAGRAMS (5) EI (10) 0 (15) EO (14)GS G1″ G13 G29 1 (11) G2′ G31 G14 (12) (9) A0 (13) 3 (1) (2) (3) (4) 6 (6) A2 7 (4) G8′ (3) G7′ G12′ G24 G25 G26 G27 G28 (6) A2 (7) A1 4 (1) 2 (12) G3′ G9′ (13) G4′ G15 G16 G17 G10′ G19 G20 5 6 7 (2) G6′ G11′ G21 G22 G23 (7) A1 G18 (9) A0 G30 (15) EO (14) GS (5) EI (10) 0 1 2 3 4 5 (11) G5′ SN54 / 74LS348 SN54 / 74LS848 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOH IOL IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — High Output Current — Low Output Current — Low EO. A2 EO.0 8.25 125 70 – 0. A1. 74 54 74 54 74 54 74 Min 4.0 12 24 Unit V °C mA mA mA mA FAST AND LS TTL DATA 5-312 .5 5.0 25 25 Max 5.75 – 55 0 Typ 5. A2 A0. A1. A2 Parameter 54 74 54 74 54.6 4. A2 A0. GS A0. A1.

VOUT = 2.0 mA IOL = 8.0 V VCC = MAX.1 0.4 2.3 – 0. EI = GND All Others Open 0. VIN = VIH or VIL per Truth Table VOL IOZH IOZL VCC = MAX. GS EO. IOH = MAX.4 V IOS VCC = MAX Note 1: Not more than one output should be shorted at a time. GS VOL Output LOW Voltage g EO.SN54/74LS348 • SN54/74LS848 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Voltage A0. A1. EI — LS348 Input 0 — LS848 Other — LS348 Other — LS848 Input LOW Current Input 0.7 V VCC = MAX.5 2.8 – 1.4 V VCC = MAX. VIN = 2. A1. A2 VOH EO.8 – 1.5 3.5 V V V V V V V V µA µA µA µA µA µA mA mA mA mA mA mA mA mA mA mA VCC = MAX All Inputs and Outputs Open VCC = MAX.7 – 0. Inputs 7.35 0. VOUT = 0.8 – 0. nor for more than 1 second. 74 74 2. EI — LS348 IIL Input 0 — LS848 Other — LS348 Other — LS848 Short Circuit Current (Note 1) EO. A2 Power Supply Current Total. VIN = VIL or VIH per Truth Table VCC = VCC MIN.5 20 –20 20 40 40 60 0. FAST AND LS TTL DATA 5-313 .25 0.7 V IOL = 4. GS A0.2 – 120 – 130 23 mA VCC = MAX.1 3. GS Output LOW Voltage g A0. 74 54 74 54. VIN = VIL or VIH per Truth Table Min 2. Output LOW 13 25 – 20 – 30 12 54. VIN = 7.25 0. 74 74 54.4 – 0. EI — LS348 Input 0 — LS848 Other — LS348 Other — LS848 IIH Input HIGH Current Input 0.4 0.0 mA IOL = 12 mA IOL = 24 mA VCC = VCC MIN.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN. A1. Output HIGH ICC Total.4 0.5 0.2 0. IIN = – 18 mA VCC = MIN. A2 Output Off Current HIGH Output Off Current LOW Input HIGH Current Input 0.5 0.35 0.2 0. VIN = 0.0 0.65 3.

0 11 21 17 ns 26 38 40 55 26 38 40 55 ns CL = 15 pF RL = 2. A0 A1 or A2 output Out-of-Phase 1 thru 7 A0. TA = 25°C) From (Input) 1 thru 7 To (Output) A0. A0 A1 or A2 24 Out-of-Phase 0 thru 7 E0 output In-Phase 0 thru 7 GS output In-Phase EI GS output In-Phase EI EO output EI A0.SN54/74LS348 • SN54/74LS848 AC CHARACTERISTICS (VCC = 5.0 11 21 17 9.0 pF RL = 667 Ω 14 17 36 21 14 17 36 21 ns 9.0 V. A0 A1 or A2 23 35 23 35 25 18 40 27 30 18 45 27 ns CL = 5. A0 A1 or A2 output EI A0.0 Ω 11 41 18 24 11 41 18 ns 23 25 35 39 23 25 35 39 ns 20 23 30 35 20 23 30 35 ns CL = 45 pF RL = 667 Ω LS348 Limits Waveform In-Phase Min Typ 11 Max 17 Min LS848 Limits Typ 12 Max 18 ns Unit Test Conditions Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHZ tPLZ FAST AND LS TTL DATA 5-314 .

for Commercial (74) Temperature Ranges.L. The SN54 / 74LS352 is the functional equivalent of the SN54 / 74LS153 except with inverted outputs.L.DUAL 4-INPUT MULTIPLEXER The SN54 / 74LS352 is a very high-speed Dual 4-input Multiplexer with Common Select inputs and individual Enable inputs for each section. SN54/74LS352 • Inverted Version of the SN54 / 74LS153 • Separate Enables for Each Multiplexer • Input Clamp Diode Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Eb 15 S0 14 I3b 13 I2b 12 I1b 11 I0b 10 Zb 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L. The two buffered outputs present data in the inverted (complementary) form.L.L.) = 40 µA HIGH/1.5 U. 10 U.L.25 U. for Military (54) and 5 U. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC DIAGRAM Ea I0a 1 6 5 I1a 4 I2a 3 I3a 2 S1 14 S0 10 I0b 11 I1b 12 I2b 13 I3b Eb 15 LOGIC SYMBOL 1 6 5 4 3 10 11 12 13 15 I0b I1b I2b I3b Eb 14 2 Ea I0a I1a I2a I3a S0 S1 Za Zb 7 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS VCC = PIN 16 GND = PIN 8 9 9 7 Za Zb FAST AND LS TTL DATA 5-315 . DUAL 4-INPUT MULTIPLEXER LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 1 Ea 2 S1 3 I3a 4 I2a 5 I1a 6 I0a 7 Za 8 GND 16 1 N SUFFIX PLASTIC CASE 648-08 PIN NAMES LOADING (Note a) HIGH LOW 0.L. 5 (2.L. 0.5 U.25 U.6 mA LOW. D SUFFIX SOIC CASE 751B-03 NOTES: a) 1 TTL Unit Load (U. 0.L. It can select two bits of data from four sources. b) The Output LOW drive factor is 2.5 U.5) U. 0. 0.5 U.L. S1 E I0 – I1 Z Common Select Inputs Enable (Active LOW) Input Multiplexer Inputs Multiplexer Outputs (note b) 0.25 U.L. 16 1 S0.

The SN54 / 74LS352 can generate two functions of three variables.0 5.0 8.0 Unit V °C mA mA FAST AND LS TTL DATA 5-316 .0 25 25 Max 5. The logic equations for the outputs are shown below.75 – 55 0 Typ 5.4 4. 74 54 74 Min 4. When the Enables (Ea. TRUTH TABLE SELECT INPUTS S0 X L L H H L L H H S1 X L L L L H H H H E H L L L L L L L L I0 X L H X X X X X X INPUTS (a or b) I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H OUTPUT Z H H L H L H L H L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 5.5 4. Eb) which can be used to strobe the outputs independently.25 125 70 – 0. Za = Ea • (I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 • S0 + I3a • S1 • S0) Zb = Eb • (I0b • S1 • S0 + I1b • S1 • S0 + I2b • S1 • S0 + I3b • S1 • S0) The SN54 / 74LS352 can be used to move data from a group of registers to a common output bus. A less obvious application is a function generator. The two 4-input multiplexer circuits have individual active LOW Enables (Ea. S1). The particular register from which the data came would be determined by the state of the Select Inputs. Zb) are forced HIGH.SN54/74LS352 FUNCTIONAL DESCRIPTION The SN54 / 74LS352 is a Dual 4-Input Multiplexer. It selects two bits of data from up to four sources under the control of the common Select Inputs (S0. the corresponding outputs (Za. Eb) are HIGH. This is useful for implementing highly irregular random logic.

3 V tPLH 1. AC CHARACTERISTICS (TA = 25°C. CL = 15 pF AC WAVEFORMS VIN 1.7 3.0 V.5 0.4 – 100 10 0.8 – 1.5 – 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2. VIN = VIH or VIL per Truth Table IOL = 4.5 V V Min 2. VIN = 7.3 V 1. Enable to Output Propagation Delay.25 0.7 V VCC = MAX. VIN = 2. 74 VOL Output LOW Voltage 74 Input HIGH Current 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 mA VCC = VCC MIN. nor for more than 1 second. Select to Output Propagation Delay.3 V Figure 1 Figure 2 FAST AND LS TTL DATA 5-317 .4 V V 2. VCC = 5. VIN = 0.3 V tPHL VOUT 1.0 V VCC = MAX.0 mA IOL = 8.5 0.0 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.3 V 1.3 V VOUT VIN 1.65 3.SN54/74LS352 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. Data to Output Min Typ 19 25 16 21 13 17 Max 29 38 24 32 20 26 Unit ns ns ns Test Conditions Figure 1 or 2 Figure 2 Figure 1 VCC = 5. IOH = MAX.3 V tPHL 1. IIN = – 18 mA VCC = MIN.35 0.3 V tPLH 1.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current –20 –0.

The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (E0) inputs.L.L. S1 Multiplexer A E0a I0A – I3a Za Multiplexer B E0b I0b – I3b Zb Common Select Inputs 0.) = 40 µA HIGH/1. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC S0.L.L.L. 65 (25) U. for Commercial Temperature Ranges. 0. 0. for Military and 65 U.L.L. 0. 14 2 E0a I0a I1a I2a I3a S0 S1 Za Zb 7 VCC = PIN 16 GND = PIN 8 9 FAST AND LS TTL DATA 5-318 .L. 1 6 5 4 3 10 11 12 13 15 I0b I1b I2b I3b E0b NOTES: a) 1 TTL Unit Load (U.25 U.L.L.5 U.5) U. 15 (7.25 U.L. The Output HIGH drive factor is 25 U. It is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all TTL families. allowing the outputs to interface directly with bus oriented systems.L.L.L.L.L. LOGIC SYMBOL Output Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output (Note b) 0. 0.5 U.25 U.5) U. 0. b) The Output LOW drive factor is 7.25 U. It can select two bits of data from four sources using common select inputs.25 U. DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY • • • • Inverted Version of the SN54 / 74LS253 Schottky Process for High Speed Multifunction Capability Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 E0b 15 S0 14 I3b 13 I2b 12 I1b 11 I0b 10 Zb 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 65 (25) U.L.5 U.5 U.5 U. Output Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output (Note b) 0.L. for Commercial (74) Temperature Ranges.5 U. for Military (54) and 15 U.L.SN54/74LS353 DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The LSTTL / MSI SN54 / 74LS353 is a Dual 4-Input Multiplexer with 3-state outputs. 15 (7. 0. 16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 1 E0a 2 S1 3 I3a 4 I2a 5 I1a 6 I0a 7 Za 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 PIN NAMES LOADING (Note a) HIGH LOW 0.6 mA LOW.

all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. FAST AND LS TTL DATA 5-319 . The 4-input multiplexers have individual Output Enable (E0a. The logic equations for the outputs are shown below: Za = E0a • (I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 • S0 + I3a • S1 • S0) Zb = E0b • (I0b • S1 • S0 + I1b • S1 • S0 + I2b • S1 • S0 + I3b • S1 • S0) If the outputs of 3-state devices are tied together. S1). Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so that there is no overlap. E0b) inputs which when HIGH.SN54/74LS353 LOGIC DIAGRAM E0b 15 I3b 13 I2b 12 I1b 11 I0b 10 S0 14 S1 2 I3a 3 I2a 4 I1a 5 I0a 6 E0a 1 9 Zb VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 7 Za FUNCTIONAL DESCRIPTION The SN54 / 74LS353 contains two identical 4-input Multiplexers with 3-state outputs. TRUTH TABLE SELECT INPUTS S0 X L L H H L L H H S1 X L L L L H H H H I0 X L H X X X X X X DATA INPUTS I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H OUTPUT ENABLE E0 H L L L L L L L L OUTPUT Z (Z) H L H L H L H L H = HIGH Level L = LOW Level X = Immaterial (Z) = High Impedance (off) Address inputs S0 and S1 are common to both sections. forces the outputs to a high impedance (high Z) state. They select two bits from four sources selected by common select inputs (S0.

IOH = MAX. VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN.7 V VCC = MAX. IIN = – 18 mA VCC = MIN.8 – 1. VIN = 0. 5 Figures 3.0 Figures 4. VIN = VIL or VIH per Truth Table VOL IOZH IOZL VCC = MAX.6 12 24 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 Output LOW Voltage g QA – QH Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time. 74 74 2.4 V VCC = MAX. VIN = 2. 5 CL = 5 0 pF 5.25 0.1 0.4 – 0.5 V V Min 2. AC CHARACTERISTICS (TA = 25°C.4 0.0 25 25 Max 5.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.4 3. 5 Figures 3.75 –55 0 Typ 5.35 0.4 0. Select to Output Output Enable Time to HIGH Level Output Enable Time to LOW Level Output Disable Time to LOW Level Output Disable Time to HIGH Level Min Typ 11 13 20 21 11 15 12 27 Max 25 20 45 32 23 23 27 41 Unit ns ns ns ns ns ns Figure 1 Figure 1 or 2 CL = 15 pF Figures 4. nor for more than 1 second. VCC = 5. 5 Test Conditions FAST AND LS TTL DATA 5-320 . VIN = 7. Data to Output Propagation Delay.0 5.4 – 130 14 12 54. VOUT = 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.0 0.7 V VCC = MAX.SN54/74LS353 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54 74 54 74 Min 4.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPLZ tPHZ Parameter Propagation Delay.0 V VCC = MAX.5 20 – 20 20 IIH IIL IOS ICC V V V µA µA µA mA mA mA 2.5 5.0 –2.5 4.25 125 70 – 1. Output 3-State Total. VOUT = 2. Output LOW – 20 – 0.65 3.

5 V VE VOUT tPZL 1.5 V 0.3 V VOUT 1.5 V 0.0 kΩ CL* SW2 * Includes Jig and Probe Capacitance.3 V VOUT 1.SN54/74LS353 3-STATE WAVEFORMS VIN 1.5 V VE tPZH 1.5 V Figure 3 Figure 4 AC LOAD CIRCUIT VCC SWITCH POSITIONS RL SW1 SYMBOL tPZH tPZL TO OUTPUT UNDER TEST tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed 5.3 V Figure 1 Figure 2 VE 1.5 V tPLZ ≈ 1.3 V tPHL 1.3 V tPLH 1.3 V tPLH 1.3 V tPHL 1.5 V VOUT tPHZ 1. Figure 5 FAST AND LS TTL DATA 5-321 .5 V 1.5 V VOL VE 1.3 V VIN 1.5 V ≥ VOH ≈ 1.

The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power Schottky loads when the Enable (E) is LOW. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so there is no overlap.6 12 24 Unit V °C mA mA FAST AND LS TTL DATA 5-322 .0 – 2. They are organized as single 6-bit or 2-bit / 4-bit.0 25 25 Max 5.5 4. with inverting or non-inverting data (D) paths. When the Output Enable (E) is HIGH.5 5.3-STATE HEX BUFFERS These devices are high speed hex buffers with 3-state outputs. the outputs are forced to a high impedance “off” state.25 125 70 – 1.75 – 55 0 Typ 5. all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. If the outputs of the 3-state devices are tied together. SN54/74LS365A SN54/74LS366A SN54/74LS367A SN54/74LS368A 3-STATE HEX BUFFERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54 74 54 74 Min 4.0 5.

SN54/74LS365A • SN54/74LS366A SN54/74LS367A • SN54/74LS368A SN54 / 74LS365A HEX 3-STATE BUFFER WITH COMMON 2-INPUT NOR ENABLE VCC 16 E2 15 14 13 12 11 10 9 SN54 / 74LS366A HEX 3-STATE INVERTER BUFFER WITH COMMON 2-INPUT NOR ENABLE VCC 16 E2 15 14 13 12 11 10 9 1 E1 2 3 4 5 6 7 8 GND 1 E1 2 3 4 5 6 7 8 GND TRUTH TABLE INPUTS E1 L L H X E2 L L X H D L H X X L H (Z) (Z) OUTPUT L L H X TRUTH TABLE INPUTS E1 E2 L L X H D L H X X H L (Z) (Z) OUTPUT SN54 / 74LS367A HEX 3-STATE BUFFER SEPARATE 2-BIT AND 4-BIT SECTIONS VCC 16 E 15 14 13 12 11 10 9 SN54 / 74LS368A HEX 3-STATE INVERTER BUFFER SEPARATE 2-BIT AND 4-BIT SECTIONS VCC 16 E 15 14 13 12 11 10 9 1 E 2 3 4 5 6 7 8 GND 1 E 2 3 4 5 6 7 8 GND TRUTH TABLE INPUTS E L L H D L H X L H (Z) OUTPUT TRUTH TABLE INPUTS E L L H D L H X H L (Z) OUTPUT FAST AND LS TTL DATA 5-323 .

7 V VCC = MAX.1 0.0 0.4 3.4 V VCC = MAX.4 V VCC = MAX.1 Input LOW Current E Inputs IIL D Inputs – 0.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.4 IOS ICC Short Circuit Current (Note 1) Power Supply Current LS365A.0 19 24 Max 16 22 35 40 30 35 LS366A / LS368A Min Typ 7.7 V VCC = MAX.4 – 0.4 V V 2.35 0. 74 VOL IOZH IOZL IIH Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.0 V) Limits LS365A / LS367A Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Output Enable Time Output Disable Time Min Typ 10 9.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.25 0.4 0.4 – 20 – 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 V VCC = MAX. AC CHARACTERISTICS (TA = 25°C. VCC = 5.5 V V Min 2.0 pF FAST AND LS TTL DATA 5-324 .0 12 18 28 Max 15 18 35 45 32 35 Unit ns ns ns CL = 45 pF. VIN = 2.5 20 – 20 20 V µA µA µA mA mA µA mA mA 2. VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN. IOH = MAX.65 3. RL = 667 Ω Test Conditions CL = 5.0 V VCC = MAX. 367A LS366A. VIN = 7.SN54/74LS365A • SN54/74LS366A SN54/74LS367A • SN54/74LS368A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. nor for more than 1 second. 368A – 40 – 225 24 21 0. VOUT = 0. VIN = 0. VIN = 0. IIN = – 18 mA VCC = MIN.8 – 1. VIN = 0. VOUT = 2.4 V Both E Inputs at 0.5 V Either E Input at 2.

for Commercial (74) Temperature Ranges. 65 (25) U.25 U. The SN54 / 74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all Motorola TTL families. 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND FAST AND LS TTL DATA 5-325 . 0. 0. OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT LOW POWER SCHOTTKY 20 1 J SUFFIX CERAMIC CASE 732-03 • • • • • • • Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Hysteresis on Latch Enable Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Hysteresis on Clock Input to Improve Noise Margin Input Clamp Diodes Limit High Speed Termination Effects LOADING (Note a) 20 1 N SUFFIX PLASTIC CASE 738-03 PIN NAMES 20 HIGH D0 – D 7 LE CP OE O0 – O7 Data Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH going edge) Input Output Enable (Active LOW) Input Outputs (Note b) 0.L. Data appears on the bus when the Output Enable (OE) is LOW.L. 0.L. b) The Output LOW drive factor is 7. for Military (54) and 25 U.) = 40 µA HIGH/1.5 U.L. The Output HIGH drive factor is 25 U.L.25 U.5 U. OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH.6 mA LOW.L.L. When OE is HIGH the bus output is in the high impedance state. The SN54 / 74LS374 is a high-speed. SN54/74LS373 SN54/74LS374 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS.5 U.L.OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS. for Military (54) and 65 U.L.25 U.L.L. 0.L. 15 (7. for Commercial (74) Temperature Ranges.L.5 U. 0. the data that meets the setup times is latched. CONNECTION DIAGRAM DIP (TOP VIEW) SN54 / 74LS373 VCC O7 20 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 LE 11 VCC O7 20 19 D7 18 SN54 / 74LS374 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 CP 11 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.L. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. When LE is LOW. 0. DW SUFFIX SOIC CASE 751D-03 1 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC NOTES: a) 1 TTL Units Load (U.25 U. LOW 0.5 U.5) U.L.

LOGIC DIAGRAMS SN54LS / 74LS373 3 4 7 8 13 14 17 18 D0 D LATCH ENABLE LE 11 OE Q G D1 D Q G D2 D Q G D3 D Q G D4 D Q G D5 D Q G D6 D Q G D7 D Q G VCC = PIN 20 GND = PIN 10 = PIN NUMBERS 1 O0 2 5 O1 6 O2 9 O3 12 O4 15 O5 16 O6 19 O7 SN54LS / 74LS374 3 11 4 7 8 13 14 17 18 D0 CP D Q Q CP D Q Q D1 CP D Q Q D2 CP D Q Q D3 CP D Q Q D4 CP D Q Q D5 CP D Q Q D6 CP D Q Q D7 CP OE 1 2 O0 5 O1 6 O2 9 O3 12 O4 15 O5 16 O6 19 O7 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54 74 54 74 Min 4.0 5.25 125 70 – 1.5 4.SN54/74LS373 • SN54/74LS374 TRUTH TABLE LS373 Dn H L X X LE H H L X OE L L L H On H L Q0 Z* Dn H L X X LS374 LE OE L L H On H L Z* H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance * Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).0 – 2.0 25 25 Max 5.75 – 55 0 Typ 5.5 5.6 12 24 Unit V °C mA mA FAST AND LS TTL DATA 5-326 .

SN54/74LS373 • SN54/74LS374
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54 74 54, 74 VOL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 30 0.35 0.5 20 – 20 20 0.1 – 0.4 – 130 40 V µA µA µA mA mA mA mA 2.4 2.4 54 74 – 0.65 3.4 3.1 0.25 0.4 Min 2.0 0.7 0.8 – 1.5 Typ Max Unit V V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VOUT = 2.7 V VCC = MAX, VOUT = 0.4 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits LS373 Symbol fMAX tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay, Data to Output Clock or Enable to Output Output Enable Time Output Disable Time 12 12 20 18 15 25 12 15 18 18 30 30 28 36 20 25 15 19 20 21 12 15 28 28 28 28 20 25 Min Typ Max Min 35 LS374 Typ 50 Max Unit MHz ns ns ns ns CL = 5.0 pF CL = 45 pF pF, RL = 667 Ω Test Conditions

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits LS373 Symbol tW ts th Clock Pulse Width Setup Time Hold Time Parameter Min 15 5.0 20 Max Min 15 20 0 LS374 Max Unit ns ns ns

DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to LE transition from HIGH-to-LOW in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the LE transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition.

FAST AND LS TTL DATA 5-327

SN54/74LS373

AC WAVEFORMS
tW LE 1.3 V ts Dn tPLH OUTPUT tPHL th tW

Figure 1
OE tPZL VOUT 1.3 V 0.5 V 1.3 V 1.3 V tPLZ 1.3 V VOL OE tPZH VOUT 1.3 V 1.3 V tPHZ 1.3 V VOH 1.3 V 0.5 V

Figure 2

Figure 3

AC LOAD CIRCUIT
VCC

SWITCH POSITIONS
RL SW1 SYMBOL tPZH tPZL TO OUTPUT UNDER TEST tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed

5.0 kΩ CL* SW2

* Includes Jig and Probe Capacitance.

Figure 4

FAST AND LS TTL DATA 5-328

SN54/74LS374

AC WAVEFORMS
tWH CP 1.3 V ts Dn tPLH OUTPUT 1.3 V 1.3 V tPHL 1.3 V tWL 1.3 V OE tPZL VOUT 1.3 V 0.5 V

1.3 V th

1.3 V

1.3 V tPLZ ≈ 1.3 V VOL

Figure 6

Figure 5

OE tPZH VOUT

1.3 V tPHZ 1.3 V

1.3 V ≥ VOH ≈ 1.3 V 0.5 V

Figure 7

AC LOAD CIRCUIT
VCC

SWITCH POSITIONS
RL SW1 SYMBOL tPZH tPZL TO OUTPUT UNDER TEST tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed

5.0 kΩ CL* SW2

* Includes Jig and Probe Capacitance.

Figure 8

FAST AND LS TTL DATA 5-329

SN54/74LS375 4-BIT D LATCH
The SN54 / 74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input /output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follow the input. When E goes LOW, the information present at the D input prior to its setup time will be retained at the Q outputs.

4-BIT D LATCH
LOW POWER SCHOTTKY

CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 D3 15 Q3 14 Q3 13 E2,3 12 Q2 11 Q2 10 D2 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

J SUFFIX CERAMIC CASE 620-09
16 1

1 D0

2 Q0

3 Q0

4 E0,1

5 Q1

6 Q1

7 D1

8 GND
16

N SUFFIX PLASTIC CASE 648-08
1

TRUTH TABLE (Each latch)
tn D H L PIN NAMES tn+1 Q H L

NOTES: tn = bit time before enable negative-going transition. tn+1 = bit time after enable negative-going transition.

16 1

D SUFFIX SOIC CASE 751B-03

LOADING (Note a) HIGH LOW 0.25 U.L. 1.0 U.L. 1.0 U.L. 5 (2.5) U.L. 5 (2.5) U.L.

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

D1 – D 4 E0 – 1 E2 – 3 Q1 – Q4 Q1 – Q4

Data Inputs Enable Input Latches 0, 1 Enable Input Latches 2, 3 Latch Outputs (Note b) Complimentary Latch Outputs (Note b)

0.5 U.L. 2.0 U.L. 2.0 U.L. 10 U.L. 10 U.L.

NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 25 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.

LOGIC SYMBOL
1 D0 7 D1 9 D2 15 D3

LOGIC DIAGRAM
DATA ENABLE TO OTHER LATCH Q Q

4 12

E0,1

E2,3 Q0 2 3

Q1 6 5

Q2 10 11

Q3 14 13

VCC = PIN 16 GND = PIN 8

FAST AND LS TTL DATA 5-330

SN54/74LS375
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 D Input E Input IIH Input HIGH Current D Input E Input Input LOW Current D Input E Input – 20 0.1 0.4 – 0.4 – 1.6 – 100 12 mA mA mA mA VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX 0.35 0.5 20 80 V µA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V

IIL IOS ICC

Short Circuit Current (Note 1) Power Supply Current

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay, Data to Q Propagation Delay, Data to Q Propagation Delay, Enable to Q Propagation Delay, Enable to Q Min Typ 15 9.0 12 7.0 15 14 16 7.0 Max 27 17 20 15 27 25 30 15 Unit ns ns ns ns VCC = 5.0 V CL = 15 pF Test Conditions

FAST AND LS TTL DATA 5-331

SN54/74LS375
LOGIC DIAGRAM

DATA ENABLE TO OTHER LATCH

Q (SN54LS/74LS375 ONLY) Q

GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits Symbol tW ts th Parameter Enable Pulse Width Setup Time Hold Time Min 20 20 0 Typ Max Unit ns ns ns VCC = 5.0 V Test Conditions

AC WAVEFORMS

D

1.3 V ts

1.3 V th 1.3 V 1.3 V

E

1.3 V tPLH

Q

tPLH

1.3 V

tPHL tPHL

1.3 V

Q

tPHL tPHL

1.3 V

tPLH tPLH

1.3 V

DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized.

FAST AND LS TTL DATA 5-332

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE
The SN54 / 74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54 / 74LS378 is a 6-Bit Register with a buffered common enable. This device is similar to the SN54 / 74LS174, but with common Enable rather than common Master Reset. The SN54 / 74LS379 is a 4-Bit Register with buffered common Enable. This device is similar to the SN54 / 74LS175 but features the common Enable rather then common Master Reset.

SN54/74LS377 SN54/74LS378 SN54/74LS379
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE
LOW POWER SCHOTTKY

• • • • •

8-Bit High Speed Parallel Registers Positive Edge-Triggered D-Type Flip Flops Fully Buffered Common Clock and Enable Inputs True and Complement Outputs Input Clamp Diodes Limit High Speed Termination Effects

20 1

J SUFFIX CERAMIC CASE 732-03

PIN NAMES

LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L.

20 1

N SUFFIX PLASTIC CASE 738-03

E D0 – D 3 CP Q0 – Q3 Q0 – Q3

Enable (Active LOW) Input Data Inputs Clock (Active HIGH Going Edge) Input True Outputs (Note b) Complemented Outputs (Note b)

0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L.

20 1

DW SUFFIX SOIC CASE 751D-03

NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. 16 1

J SUFFIX CERAMIC CASE 620-09

16 1

N SUFFIX PLASTIC CASE 648-08

16 1

D SUFFIX SOIC CASE 751B-03

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXDW SN74LSXXXD Ceramic Plastic SOIC SOIC

FAST AND LS TTL DATA 5-333

SN54/74LS377 • SN54/74LS378 • SN54/74LS379
CONNECTION DIAGRAM DIPS (TOP VIEW) SN54 / 74LS377
VCC Q7 20 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 13 Q4 12 CP 11
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

1 E

2 Q0

3 D0

4 D1

5 Q1

6 Q2

7 D2

8 D3

9 Q3

10 GND

SN54 / 74LS378
VCC 16 Q5 15 D5 14 D4 13 Q4 12 D3 11 Q3 10 CP 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

1 E

2 Q0

3 D0

4 D1

5 Q1

6 D2

7 Q2

8 GND

SN54 / 74LS379
VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

1 E

2 Q0

3 Q0

4 D0

5 D1

6 Q1

7 Q1

8 GND

FAST AND LS TTL DATA 5-334

SN54/74LS377 • SN54/74LS378 • SN54/74LS379
LOGIC DIAGRAMS SN54 / 74LS377
3 4 7 8 13 14 17 18

D0 E ENABLE
1

D1

D2

D3

D4

D5

D6

D7

CP CLOCK
11

CP D Q

CP D Q

CP D Q

CP D Q

CP D Q

CP D Q

CP D Q

CP D Q

Q0
2

Q1
5

Q2
6

Q3
9

Q4
12

Q5
15

Q6
16

Q7
19

SN54 / 74LS378
3 4 6 11 13 14

D0 CP
9

D1

D2

D3

D4

D5

CP D E Q
1

CP D E Q

CP D E Q

CP D E Q

CP D E Q

CP D E Q

E Q0
2

Q1
5

Q2
7

Q3
10

Q4
12

Q5
15

SN54 / 74LS379

4

5

12

13

D0 CP
9

D1

D2

D3

CP E Q
1

D E Q

CP Q

D E Q

CP Q

D E Q

CP Q

D Q

E Q0
3

Q0
2

Q1
6

Q1
7

Q2
11

Q2
10

Q3
14

Q3
15

FAST AND LS TTL DATA 5-335

SN54/74LS377 • SN54/74LS378 • SN54/74LS379
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current LS377 LS378 LS379 – 20 0.35 0.5 20 0.1 – 0.4 – 100 28 22 15 V µA mA mA mA mA 2.5 2.7 54 74 – 0.65 3.5 3.5 0.25 0.4 Min 2.0 0.7 0.8 – 1.5 Typ Max Unit V V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH , , or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

IIH IIL IOS ICC

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX, NOTE 1

NOTE: With all inputs open and GND applied to all data and enable inputs, ICC is measured after a momentary GND, then 4.5 V is applied to clock. Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay, Clock to Output Min 30 Typ 40 17 18 27 27 Max Unit MHz ns Test Conditions VCC = 5 0 V 5.0 CL = 15 pF

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits Symbol tW ts ts th Parameter Any Pulse Width Data Setup Time Enable Setup Time Any Hold Time Inactive — State Active — State Min 20 20 10 25 5.0 Typ Max Unit ns ns ns ns ns VCC = 5.0 V Test Conditions

DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following

the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized.

FAST AND LS TTL DATA 5-336

SN54/74LS377 • SN54/74LS378 • SN54/74LS379
TRUTH TABLE
E H L L
L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial

CP

Dn X H L

Qn No Change H L

Qn No Change L H

AC WAVEFORMS

SN54 / 74LS377
1/fmax CP 1.3 V ts(H) D OR E * 1.3 V tPLH Q 1.3 V ts(L) th(H) tW 1.3 V th(L) 1.3 V tPHL 1.3 V Q E, D * CP 1.3 V ts(H)

SN54 / 74LS378
1/fmax tW 1.3 V th(H) 1.3 V tPHL 1.3 V ts(L) th(L) 1.3 V tPLH 1.3 V

Figure 1. Clock to Output Delays Clock Pulse Width, Frequency, Setup and Hold Times Data or Enable to Clock

Figure 2. Clock to Output Delays Clock Pulse Width, Frequency, Setup and Hold Times Data or Enable to Clock

SN54 / 74LS379
1/fmax CP 1.3 V ts(H) E, D * 1.3 V tPLH Q 1.3 V ts(L) th(H) tW 1.3 V th(L) 1.3 V tPHL 1.3 V

*The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 3. Clock to Output Delays Clock Pulse Width, Frequency, Setup and Hold Times Data, Enable to Clock

FAST AND LS TTL DATA 5-337

SN54/74LS386 QUAD 2-INPUT EXCLUSIVE-OR GATE
QUAD 2-INPUT EXCLUSIVE-OR GATE
LOW POWER SCHOTTKY
VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08
14 1

1

2

3

4

5

6

7 GND N SUFFIX PLASTIC CASE 646-06
1

14

14 1

D SUFFIX SOIC CASE 751A-02

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

FAST AND LS TTL DATA 5-338

SN54/74LS386
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.2 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.8 – 100 10 0.35 0.5 40 IIH IIL IOS ICC V µA mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)
Limits Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay, Other Input LOW Propagation Delay, Other Input HIGH Min Typ 12 10 20 13 Max 23 17 30 22 Unit ns ns VCC = 5.0 V CL = 15 pF Test Conditions

FAST AND LS TTL DATA 5-339

DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER
The SN54 / 74LS390 and SN54 / 74LS393 each contain a pair of high-speed 4-stage ripple counters. Each half of the LS390 is partitioned into a divide-by-two section and a divide-by five section, with a separate clock input for each section. The two sections can be connected to count in the 8.4.2.1 BCD code or they can count in a biquinary sequence to provide a square wave (50% duty cycle) at the final output. Each half of the LS393 operates as a Modulo-16 binary divider, with the last three stages triggered in a ripple fashion. In both the LS390 and the LS393, the flip-flops are triggered by a HIGH-to-LOW transition of their CP inputs. Each half of each circuit type has a Master Reset input which responds to a HIGH signal by forcing all four outputs to the LOW state.

SN54/74LS390 SN54/74LS393

DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER
LOW POWER SCHOTTKY

• • • • •

Dual Versions of LS290 and LS293 LS390 has Separate Clocks Allowing ÷ 2, ÷ 2.5, ÷ 5 Individual Asynchronous Clear for Each Counter Typical Max Count Frequency of 50 MHz Input Clamp Diodes Minimize High Speed Termination Effects

J SUFFIX CERAMIC CASE 620-09
16 1

16 1

N SUFFIX PLASTIC CASE 648-08

CONNECTION DIAGRAM DIP (TOP VIEW) SN54 / 74LS390
VCC 16 CP0 15 MR 14 Q0 13 CP1 12 Q1 11 Q2 10 Q3 9 J SUFFIX CERAMIC CASE 632-08
14 1 16 1

D SUFFIX SOIC CASE 751B-03

1 CP0

2 MR

3 Q0

4 CP1

5 Q1

6 Q2

7 Q3

8 GND
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 14 1

N SUFFIX PLASTIC CASE 646-06

SN54 / 74LS393
VCC 14 CP 13 MR 12 Q0 11 Q1 10 Q2 9 Q3 8

14 1

D SUFFIX SOIC CASE 751A-02

ORDERING INFORMATION
1 CP 2 MR 3 Q0 4 Q1 5 Q2 6 Q3 7 GND SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

FAST AND LS TTL DATA 5-340

a decade divider operating in the 8. 1.L.L.2.1 BCD code is obtained. Each half of the LS390 contains a ÷ 5 section that is independent except for the common MR function.5 U. for Military (54) and 5 U. The first flip-flop is triggered by HIGH-to-LOW transitions of the CP input signal. 5 (2.0 U. as shown in the BCD Truth Table. LOW 1. Thus state changes of the Q outputs do not occur simultaneously.L.L.4.SN54/74LS390 • SN54/74LS393 PIN NAMES CP CP0 CP1 MR Q0 – Q3 Clock (Active LOW going edge) Input to +16 (LS393) Clock (Active LOW going edge) Input to ÷ 2 (LS390) Clock (Active LOW going edge) Input to ÷ 5 (LS390) Master Reset (Active HIGH) Input Flip-Flop outputs (Note b) LOADING (Note a) HIGH 0. 0.L. as indicated in the ÷ 16 Truth Table.5 U.L.L. with the third stage output exhibiting a 20% duty cycle when the input frequency is constant.5) U. To obtain a ÷10 function having a 50% duty cycle output.L.6 mA LOW. connect the input signal to CP1 and connect the Q3 output to the CP0 input. 10 U.5 U. 1. therefore. 0. Since the flip-flops change state asynchronously. for Commercial (74) b) Temperature Ranges.L. A HIGH signal on MR forces all outputs to the LOW state and prevents counting.L. SN54 / 74LS390 LOGIC DIAGRAM (one half shown) CP1 CP0 K CP CD MR J Q CD K CP J Q CD K CP J Q CD K CP J Q Q0 Q1 Q2 Q3 SN54 / 74LS393 LOGIC DIAGRAM (one half shown) CP K CP CD MR J Q CD K CP J Q CD K CP J Q CD K CP J Q Q0 Q1 Q2 Q3 FAST AND LS TTL DATA 5-341 .1 binary sequence.5 U. This means that logic signals derived from combinations of these outputs will be subject to decoding spikes and. 0.2. The ÷ 5 section operates in 4.5 U.L.L. FUNCTIONAL DESCRIPTION Each half of the SN54 / 74LS393 operates in the Modulo 16 binary sequence. 0.L.5 U. A HIGH signal on MR forces all outputs LOW and prevents counting. the Q0 output provides the desired 50% duty cycle output. Each of the other flip-flops is triggered by a HIGH-to-LOW transition of the Q output of the preceding flip-flop. should not be used as clocks for other counters.25 U. registers or flip-flops. If the input frequency is connected to CP0 and the Q0 output is connected to CP1. NOTES: a) 1 TTL Unit Load (U. as shown in the ÷ 5 Truth Table.) = 40 µA HIGH/1. b) The Output LOW drive factor is 2.0 U. logic signals derived from combinations of LS390 outputs are also subject to decoding spikes.

74 54 74 Min 4.5 4.SN54/74LS390 • SN54/74LS393 SN54 / 74LS390 BCD TRUTH TABLE (Input on CP0.25 125 70 – 0.5 5. Q0 CP1) OUTPUTS COUNT 0 1 2 3 4 5 6 7 8 9 Q3 L L L L L L L L H H Q2 Q1 L L L L H H H H L L L L H H L L H H L L Q0 L H L H L H L H L H COUNT 0 1 2 3 4 SN54/ 74LS390 ÷ 5 TRUTH TABLE (Input on CP1) OUTPUTS Q3 L L L L H Q2 Q1 L L H H L L H L H L SN54 / 74LS393 TRUTH TABLE OUTPUTS COUNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q3 L L L L L L L L H H H H H H H H Q2 Q1 L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H Q0 L H L H L H L H L H L H L H L H SN54 / 74LS390 ÷ 10 (50% @ Q0) TRUTH TABLE (Input on CP1.0 5. Q3 to CP0) OUTPUTS COUNT 0 1 2 3 4 5 6 7 8 9 Q3 L L L L H L L L L H Q2 Q1 L L H H L L L H H L L H L H L L H L H L Q0 L L L L L H H H H H H = HIGH Voltage Level L = LOW Voltage Level GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.4 4.0 Unit V °C mA mA FAST AND LS TTL DATA 5-342 .0 8.0 25 25 Max 5.75 – 55 0 Typ 5.

5 – 0.4 – 100 26 0. CP to Q0 CP0 to Q0 CP to Q3 CP0 to Q2 CP1 to Q1 CP1 to Q2 CP1 to Q3 MR to Any Output LS393 LS390 LS393 LS390 LS390 LS390 LS390 LS390/393 Min 25 20 12 13 12 13 40 40 37 39 13 14 24 26 13 14 24 20 20 20 20 60 60 60 60 21 21 39 39 21 21 39 Typ 35 Max Unit MHz MHz ns ns ns CL = 15 pF ns ns ns ns ns Test Conditions FAST AND LS TTL DATA 5-343 . VIN = 2. CP0 CP1 IOS ICC Short Circuit Current (Note 1) Power Supply Current – 20 – 0. VIN = 7. IOH = MAX.1 MR IIL Input LOW Current CP.7 V VCC = MAX. VIN = 0.65 3.0 V) Limits Symbol fMAX fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency CP0 to Q0 Maximum Clock Frequency CP1 to Q1 Propagation Delay.7 3. VIN = VIH or VIL per Truth Table IOL = 4.0 0.0 V Note 1: Not more than one output should be shorted at a time.4 V 2.4 – 1. IIN = – 18 mA VCC = MIN.4 V V 2.5 0.5 0.25 0.5 V V Min 2. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.8 – 1. AC CHARACTERISTICS (TA = 25°C. nor for more than 1 second.6 – 2.SN54/74LS390 • SN54/74LS393 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54. VIN = VIL or VIH per Truth Table VCC = MAX.0 mA IOL = 8.35 0. VCC = 5.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN.0 mA VCC = VCC MIN.5 20 IIH V µA mA mA mA mA mA mA VCC = MAX VCC = MAX VCC = MAX.

3 V 1.3 V Q 1. VCC = 5.0 V Test Conditions AC WAVEFORMS *CP 1. FAST AND LS TTL DATA 5-344 .3 V tPLH 1.3 V tW tPHL 1.SN54/74LS390 • SN54/74LS393 AC SETUP REQUIREMENTS (TA = 25°C.0 V) Limits Symbol tW tW tW tW trec Parameter Clock Pulse Width CP0 Pulse Width CP1 Pulse Width MR Pulse Width Recovery Time LS393 LS390 LS390 LS390/393 LS390/393 Min 20 20 40 20 25 Typ Max Unit ns ns ns ns ns VCC = 5.3 V tW CP 1.3 V tPHL Q 1.3 V trec Figure 2 *The number of Clock Pulses required between tPHL and tPLH measurements can be determined from the appropriate Truth Table.3 V Figure 1 MR & MS 1.

L. P0 – P3 DS S CP MR OE O0 – O3 Q3 Parallel Inputs Serial Data Input Mode Select Input Clock (Active LOW) Input Master Reset (Active LOW) Input Output Enable (Active HIGH) Input 3-State Register Outputs Register Output 0. 10 U.L.L.L. 65 U. The fourth stage also has a conventional output for linking purposes in multi-stage serial operations. An active HIGH Output Enable (OE) input controls the 3-state output buffers. 0.25 U.25 U.L.5 U.L. 0. 0. 0.L. 0. 15 U.SN74LS395 4-BIT SHIFT REGISTER WITH 3-STATE OUTPUTS The SN74LS395 is a 4-Bit Register with 3-state outputs and can operate in either a synchronous parallel load or a serial shift-right mode. S P0 P1 P2 P3 2 10 9 DS CP OE MR O0 O1 O2 O3 Q3 11 1 15 14 13 12 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-345 .L. 0.) = 40 µA HIGH/1.L. 4-BIT SHIFT REGISTER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY • Shift Left or Parallel 4-Bit Register • 3-State Outputs • Input Clamp Diodes Limit High-Speed Termination Effects J SUFFIX CERAMIC CASE 620-09 16 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 O0 15 O1 14 O2 13 O3 12 Q3 11 CP 10 OE 9 16 1 N SUFFIX PLASTIC CASE 648-08 1 MR 2 DS 3 P0 4 P1 5 P2 6 P3 7 S 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 PIN NAMES LOADING (Note a) HIGH LOW 0. 0.5 U.L. as determined by the Select input.5 U.L. 0. 5 U.L.L.25 U. 0.L.6 mA LOW. 0.25 U.5 U. but does not interfere with the other operations.L.25 U.L.5 U. ORDERING INFORMATION SN74LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 7 3 4 5 6 NOTES: a) 1 TTL Unit Load (U.5 U. An asynchronous active LOW Master Reset (MR) input overrides the synchronous operations and clears the register.L.25 U.

the Pn inputs are enabled. however. O2 to P1 and O1 to P0. A left-shift is accomplished by connecting the outputs back to the Pn inputs.0 25 Max 5. When the Select input is HIGH. RESET First Stage Parallel Load H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial tn.. MODE SELECT — TRUTH TABLE Inputs @ tn Operating Mode Asynchronous Reset Shift.e.0 Unit V °C mA mA FAST AND LS TTL DATA 5-346 . parallel loading or resetting operations can still be accomplished.25 70 – 0. a CP HIGH-LOW transition transfers data in Q0 to Q1. i. Outputs @ tn+1 Ds X H L X Pn X X X Pn O0 L H L P0 O1 L O0n O0n P1 O2 L O1n O1n P2 O3 L O2n O2n P3 MR L H H H CP X S X L L H GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter Min 4. O3 to P2. State changes are initiated by HIGH-to-LOW transitions on the Clock Pulse (CP) input. Ds and S inputs can change when the Clock is in either state.SN74LS395 LOGIC DIAGRAM S Ds P0 P1 P2 P3 CP CP CD MR D Q CP CD D Q CP CD D Q CP CD D Q OE O0 O1 O2 O3 Q3 FUNCTION DESCRIPTION The SN74LS395 contains four D-type edge-triggered flip-flops and auxiliary gating to select a D input either from a Parallel (Pn) input or from the preceding stage. A LOW signal on the S input enables the serial inputs for shift-right operations. Q1 to Q2. this does not affect other operations or the Q3 output. and Q2 to Q3. The shifting. outputs O0 – O3 are in the high impedance state. n + 1 = time before and after CP HIGH-to-LOW transition NOTE: When OE is HIGH.75 0 Typ 5.4 8. When the S input is LOW. the output buffers are disabled and the Q0 – Q3 outputs are in a high impedance condition. however. but offset one place to the left. SET First Stage Shift. with P3 acting as the linking input from another package. as indicated in the Truth Table. Signals on the Pn. When the OE input is HIGH. provided that the recommended set-up and hold times are observed.

5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. VIN = 2. nor for more than 1 second.35 Output Off Current HIGH Output Off Current LOW Input HIGH Current – 0.4 – 100 31 0.5 V.0 Test Conditions FAST AND LS TTL DATA 5-347 . VO = 0.25 VOL IOZH IOZL IIH IIL IOS Output LOW Voltage 0.4 V VCC = MAX. OE = GND. Output LOW 34 mA – 20 – 0. VIN = VIL or VIH per Truth Table VCC = MAX. VO = 2. Mode Select Setup Time.0 0.0 mA IOL = 8.5 20 – 20 20 V µA µA µA mA mA mA mA 0. OE = 4.0 V CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts ts th Parameter Clock Pulse Width Setup Time. Low to High Propagation Delay. Clear to Output Propagation Delay.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.4 V VCC = MAX VCC = MAX.0 V VCC = MAX. AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPHL tPLH tPHL tPZH tPZL tPLZ tPHZ Parameter Maximum Input Clock Frequency Propagation Delay.0 pF VCC = 5. Output HIGH ICC Total.8 – 1.0 V then GND Note 1: Not more than one output should be shorted at a time. High to Low Output Enable Time Output Disable Time Min 30 Typ 45 22 15 25 15 17 12 11 35 30 30 25 25 20 17 Max Unit MHz ns ns ns ns CL = 5. All Others Data Hold Time Min 16 40 20 10 Typ Max Unit ns ns ns ns VCC = 5 0 V 5. VIN = VIH or VIL per Truth Table IOL = 4. CP = GND VCC = MAX.SN74LS395 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. VIN = 7.5 0.65 3.4 V VCC = MAX.7 – 0.0 mA VCC = VCC MIN. VIN = 0.7 V VCC = MAX.4 Min 2. IOH = MAX. IIN = – 18 mA VCC = MIN. CP momentary 3.

5 V VE 1.3 V th(L) ts(H) 1.3 V ts(L) th(L) ts(H) 1.3 V th(H) S LOAD SERIAL DATA SHIFT RIGHT 1.3 V tPLZ ≈ 1.3 V VOUT 1.3 V tPZL 1.3V ≥ VOH ≈ 1. Figure 5 FAST AND LS TTL DATA 5-348 .5 V VOUT 1. Figure 1 Figure 2 VE 1.3 V VOL 0.3 V 1/fmax tW tPLH CP 1.3 V tPHL 1.3 V th(H) 1.3 V tPZH tPHZ 1. D * ts(L) CP OR MR Q 1.3 V 0.SN74LS395 AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance.3 V LOAD PARALLEL DATA 1.3 V *The Data Input is DS for S = LOW and Pn for S = HIGH.3 V Figure 3 Figure 4 AC LOAD CIRCUIT VCC RL SYMBOL SW1 tPZH tPZL TO OUTPUT UNDER TEST tPLZ tPHZ 5 kΩ CL* SW2 SWITCH POSITIONS SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed * Includes Jig and Probe Capacitance.

10 U.L. 0.5 U.L. FAST AND LS TTL DATA 5-349 . They are the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register.5 U. while the SN54 / 74LS399 has only Q outputs.L. 5 (2. 0. The SN54/ 74LS398 features both Q and Q inputs.5) U. 0.L. 10 U.L.25 U. 20 1 N SUFFIX PLASTIC CASE 738-03 20 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXDW SN74LSXXXD Ceramic Plastic SOIC SOIC NOTES: a) 1 TTL Unit Load (U.L.5 U.L. The selected data is transferred to the output register on the LOW-to-HIGH transition of the Clock input. b) The Output LOW drive factor is 2.5) U.QUAD 2-PORT REGISTER The SN54 / 74LS398 and SN54 / 74LS399 are Quad 2-Port Registers.L.6 mA LOW.L. LOW 0.L.25 U. for Military (54) and 5 U.L.25 U.L. 0.25 U. for Commercial (74) Temperature Ranges. A Common Select input selects between two 4-bit input ports (data sources). 0.5 U.5 U. 5 (2.L.) = 40 µA HIGH/1.L. 0. SN54/74LS398 SN54/74LS399 QUAD 2-PORT REGISTER LOW POWER SCHOTTKY • • • • Select From Two Data Sources Fully Positive Edge-Triggered Operation Both True and Complemented Outputs on SN54 / 74LS398 Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC Qd 20 19 Qd 18 Iod 17 I1d 16 I1c 15 I0c 14 Qc 13 Qc 12 CP 11 16 J SUFFIX CERAMIC CASE 620-09 1 SN54 / 74LS398 N SUFFIX PLASTIC CASE 648-08 1 1 S 2 Qa 3 Qa 4 I0a 5 I1a 6 I1b 7 I0b 8 Qb 9 Qb 10 GND 16 VCC = PIN 20 GND = PIN 10 VCC 16 Qd 15 I0d 14 I1d 13 I1c 12 I0c 11 Qc 10 CP 9 16 1 D SUFFIX SOIC CASE 751B-03 SN54 / 74LS399 20 J SUFFIX CERAMIC CASE 732-03 1 1 S 2 Qa 3 I0a 4 I1a 5 I1b 6 I0b 7 Qb 8 GND VCC = PIN 16 GND = PIN 8 PIN NAMES LOADING (Note a) HIGH S CP I0a – I0d I1a – I0d Qa – Qd Qa – Qd Common Select Input Clock (Active HIGH Going Edge) Input Data Inputs From Source 0 Data Inputs From Source 1 Register True Outputs (Note b) Register Complementary Outputs (Note b) 0.L.

The SN54 / 74LS398 has both Q and Q Outputs available. The Data inputs (I) and Select inputs (S) must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation. The 4-Bit RS type output register is fully edge-triggered. FUNCTION TABLE INPUTS S I I h h I0 I h X X I1 X X I h Q L H L H OUTPUTS Q* H L H L *SN54 / 74LS398 only I = LOW Voltage Level one setup time pior to the LOW-to-HIGH clock transition h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial FAST AND LS TTL DATA 5-350 . They select four bits of data from two sources (Ports) under the control of a common Select Input (S).SN54/74LS398 • SN54/74LS399 FUNCTIONAL BLOCK DIAGRAM IOA S IIA R IOB S IIB R IOC S IIC R IOD S IID R * SN54 / 74LS398 only * Q D QD * QC * Q B QC * Q A QB S QA FUNCTIONAL DESCRIPTION The SN54 / 74LS398 and SN54 / 74LS399 are high-speed Quad 2-Port Registers. The selected data is transferred to a 4-Bit Output Register synchronous with the LOW-to-HIGH transition of the Clock in- put (CP).

0 0.5 0.5 5.0 mA VCC = VCC MIN. IOH = MAX.75 – 55 0 Typ 5.7 3.0 5.0 mA IOL = 8.5 – 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0. nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.4 V V 2.0 V VCC = MAX.35 0.8 – 1.5 4.25 0. VIN = VIH or VIL per Truth Table IOL = 4. VIN = 2. VIN = VIL or VIH per Truth Table VCC = MAX.0 25 25 Max 5.0 V CL = 15 pF FAST AND LS TTL DATA 5-351 .4 4. VCC = 5.25 125 70 – 0. IIN = – 18 mA VCC = MIN. Clock to Output Q Min Typ 18 21 Max 27 32 Unit ns Test Conditions VCC = 5. 74 VOL Output LOW Voltage 74 Input HIGH Current 0.0 V) Limits Symbol tPLH tPHL Parameter Propagation Delay.0 8. VIN = 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.65 3.SN54/74LS398 • SN54/74LS399 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54.5 V V Min 2.7 V Typ Max Unit V Test Conditions Guaranteed Input H