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A Practical Guide to High-Speed Printed-Circuit-Board Layout

A Practical Guide to High-Speed Printed-Circuit-Board Layout

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Aaa|oe 0|a|oeae 30-00, Septemher (2005) 1

A Pract|ca| 0a|de to ß|eh-Speed
Pr|ated-0|rca|t-8oard la)oat
Bv 1chn ^rdlzzcnl |jchn.ardlzzcnl©analce.ocm]
Despiìe iìs criìical naìure in high-speed circuiìry, prinìed-circuiì-
board (PCB) layouì is ofìen one of ìhe lasì sìeps in ìhe design
process. There are many aspecìs ìo high-speed PCB layouì;
volumes have been wriììen on ìhe subiecì. This arìicle addresses
high-speed layouì from a pracìical perspecìive. A maior aim is ìo
help sensiìize newcomers ìo ìhe many and various consideraìions
ìhey need ìo address when designing board layouìs for high-speed
circuiìry. Buì iì is also inìended as a refresher ìo benehì ìhose
who have been away from board layouì for a while. Noì every
ìopic can be covered in deìail in ìhe space available here, buì we
address ley areas ìhaì can have ìhe greaìesì payoff in improving
circuiì performance, reducing design ìime, and minimizing ìime-
consuming revisions.
Alìhough ìhe focus is on circuiìs involving high-speed op amps,
ìhe ìopics and ìechniques discussed here are generally applicable
ìo layouì of mosì oìher high-speed analog circuiìs. When op amps
operaìe aì high RI frequencies, circuiì performance is heavily
dependenì on ìhe board layouì. A high-performance circuiì design
ìhaì lools good "on paper¨ can render mediocre performance
when hampered by a careless or sloppy layouì. Thinling ahead and
paying aììenìion ìo salienì deìails ìhroughouì ìhe layouì process
will help ensure ìhaì ìhe circuiì performs as expecìed.
Ihe Schemat|c
Alìhough ìhere is no guaranìee, a good layouì sìarìs wiìh a good
schemaìic. Be ìhoughìful and generous when drawing a schemaìic,
and ìhinl abouì signal ßow ìhrough ìhe circuiì. A schemaìic ìhaì
has a naìural and sìeady ßow from lefì ìo righì will ìend ìo have a
good ßow on ìhe board as well. Puì as much useful informaìion
on ìhe schemaìic as possible. The designers, ìechnicians, and
engineers who will worl on ìhis iob will be mosì appreciaìive,
including us; aì ìimes we are asled by cusìomers ìo help wiìh a
circuiì because ìhe designer is no longer ìhere.
Whaì lind of informaìion belongs on a schemaìic besides ìhe
usual reference designaìors, power dissipaìions, and ìolerances?
Here are a few suggesìions ìhaì can ìurn an ordinary schemaìic
inìo a superschemaìic! Add waveforms, mechanical informaìion
abouì ìhe housing or enclosure, ìrace lengìhs, leep-ouì areas;
designaìe which componenìs need ìo be on ìop of ìhe board;
include ìuning informaìion, componenì value ranges, ìhermal
informaìion, conìrolled impedance lines, noìes, brief circuiì
operaìing descripìions . (and ìhe lisì goes on).
Irast No 0ae
If you`re noì doing your own layouì, be sure ìo seì aside ample
ìime ìo go ìhrough ìhe design wiìh ìhe layouì person. An ounce of
prevenìion aì ìhis poinì is worìh more ìhan a pound of cure! Don`ì
expecì ìhe layouì person ìo be able ìo read your mind. Your inpuìs
and guidance are mosì criìical aì ìhe beginning of ìhe layouì process.
The more informaìion you can provide, and ìhe more involved you
are ìhroughouì ìhe layouì process, ìhe beììer ìhe board will ìurn
ouì. Cive ìhe designer inìerim compleìion poinìs÷aì which you
wanì ìo be noìihed of ìhe layouì progress for a quicl review. This
"loop closure¨ prevenìs a layouì from going ìoo far asìray and will
minimize reworling ìhe board layouì.
Your insìrucìions for ìhe designer should include: a brief descripìion
of ìhe circuiì`s funcìions; a sleìch of ìhe board ìhaì shows ìhe inpuì
and ouìpuì locaìions; ìhe board stac/ up (i.e., how ìhicl ìhe board
will be, how many layers, deìails of signal layers and planes÷power,
http:,,www.aaa|oe.com,aaa|oed|a|oeae
ground, analog, digiìal, and RI); which signals need ìo be on each
layer; where ìhe criìical componenìs need ìo be locaìed; ìhe exacì
locaìion of bypassing componenìs; which ìraces are criìical; which
lines need ìo be conìrolled-impedance lines; which lines need ìo
have maìched lengìhs; componenì sizes; which ìraces need ìo lepì
away from (or near) each oìher; which ctrcutts need ìo be lepì away
from (or near) each oìher; which ccmpcnents need ìo be close ìo (or
away from) each oìher; which componenìs go on ìhe ìop and ìhe
boììom of ìhe board. You`ll never geì a complainì for giving someone
ìoo much informaìion÷ìoo /ttt/e, yes; ìoo much, no.
¬ /earntng expertence. Abouì 1u years ago I designed a
mulìilayer surface-mounìed board÷wiìh componenìs on
boìh sides of ìhe board. The board was screwed inìo a gold-
plaìed aluminum housing wiìh many screws (because of a
sìringenì vibraìion spec). Bias feed-ìhrough pins poled up
ìhrough ìhe board. The pins were wire-bonded ìo ìhe PCB.
Iì was a complicaìed assembly. Some of ìhe componenìs on
ìhe board were ìo be S¬T (seì aì ìesì). Buì I hadn`ì specihed
where ìhese componenìs should be. Can you guess where
some of ìhem were placed? Righì! On ìhe boììom of ìhe
board. The producìion engineers and ìechnicians were noì
very happy when ìhey had ìo ìear ìhe assembly aparì, seì
ìhe values, and ìhen reassemble everyìhing. I didn`ì male
ìhaì misìale again.
locat|oa, locat|oa, locat|oa
As in real esìaìe, locaìion is everyìhing. Where a circuiì is placed
on a board, where ìhe individual circuiì componenìs are locaìed,
and whaì oìher circuiìs are in ìhe neighborhood are all criìical.
Typically, inpuì-, ouìpuì-, and power locaìions are dehned, buì
whaì goes on beìween ìhem is "up for grabs.¨ This is where paying
aììenìion ìo ìhe layouì deìails will yield signihcanì reìurns. Sìarì
wiìh criìical componenì placemenì, in ìerms of boìh individual
circuiìs and ìhe enìire board. Specifying ìhe criìical componenì
locaìions and signal rouìing paìhs from ìhe beginning helps ensure
ìhaì ìhe design will worl ìhe way iì`s inìended ìo. Ceììing iì righì
ìhe hrsì ìime lowers così and sìress÷and reduces cycle ìime.
Power-Sapp|) 8)pass|ae
Bypassing ìhe power supply aì ìhe ampliher`s supply ìerminals ìo
minimize noise is a criìical aspecì of ìhe PCB design process÷boìh
for high-speed op amps and any oìher high-speed circuiìry. There
are ìwo commonly used conhguraìions for bypassing high-speed
op amps.
Rat/s tc grcund. This ìechnique, which worls besì in mosì cases,
uses mulìiple parallel capaciìors connecìed from ìhe op amp`s
power-supply pins direcìly ìo ground. Typically, ìwo parallel
capaciìors are sufhcienì÷buì some circuiìs may benehì from
addiìional capaciìors in parallel.
Paralleling differenì capaciìor values helps ensure ìhaì ìhe
power supply pins see a low ac impedance across a wide band of
frequencies. This is especially imporìanì aì frequencies where ìhe
op-amp pcver-supp/y reiecttcn (PSR) is rolling off. The capaciìors
help compensaìe for ìhe ampliher`s decreasing PSR. Mainìaining
a low impedance paìh ìo ground for many decades of frequency
will help ensure ìhaì unwanìed noise doesn`ì hnd iìs way inìo ìhe
op amp. Iigure 1 shows ìhe benehìs of mulìiple parallel capaciìors.
Aì lower frequencies ìhe larger capaciìors offer a low impedance
paìh ìo ground. Once ìhose capaciìors reach self resonance, ìhe
capaciìive qualiìy diminishes and ìhe capaciìors become inducìive.
Thaì is why iì is imporìanì ìo use mulìiple capaciìors: when one
capaciìor`s frequency response is rolling off, anoìher is becoming
signihcanì, ìhereby mainìaining a low ac impedance over many
decades of frequency.
2 Aaa|oe 0|a|oeae 30-00, Septemher (2005)
1M
100k
10k
1k
100
10
1
0.1
0.01
0.001
0.001 10k 1k 100 10 1 0.1 0.01
FREQUENCY (MHz)
I
M
P
E
D
A
N
C
E

(
6
)
100pF
1000pF
0.01MF
0.1MF
2.2MF
Fleure 1. Capaoltcr lmpedanoe vs. frequenov.
Sìarìing direcìly aì ìhe op amp`s power-supply pins; ìhe capaciìor
wiìh ìhe lowesì value and smallesì physical size should be placed
on ìhe same side of ìhe board as ìhe op amp÷and as close ìo ìhe
ampliher as possible. The ground side of ìhe capaciìor should
be connecìed inìo ìhe ground plane wiìh minimal lead- or ìrace
lengìh. This ground connecìion should be as close as possible ìo
ìhe ampliher`s load ìo minimize disìurbances beìween ìhe rails
and ground. Iigure 2 illusìraìes ìhis ìechnique.
-V
S
+V
S
+
+
BYPASS
CAPACITORS
BYPASS
CAPACITORS
LOAD
Fleure 2. laralleloapaoltcr rallstcercund bvpasslne.
This process should be repeaìed for ìhe nexì-higher-value
capaciìor. A good place ìo sìarì is wiìh u.u1 MI for ìhe smallesì
value, and a 2.2-MI÷or larger÷elecìrolyìic wiìh low ESR for ìhe
nexì capaciìor. The u.u1 MI in ìhe u5uS case size offers low series
inducìance and excellenì high-frequency performance.
Rat/ tc rat/. An alìernaìe conhguraìion uses one or more bypass
capaciìors ìied beìween ìhe posiìive- and negaìive supply
rails of ìhe op amp. This meìhod is ìypically used when iì is
difhculì ìo geì all four capaciìors in ìhe circuiì. A drawbacl ìo
ìhis approach is ìhaì ìhe capaciìor case size can become larger,
because ìhe volìage across ìhe capaciìor is double ìhaì of ìhe
single-supply bypassing meìhod. The higher volìage requires a
higher brealdown raìing, which ìranslaìes inìo a larger case size.
This opìion can, however, offer improvemenìs ìo boìh PSR and
disìorìion performance.
Since each circuiì and layouì is differenì; ìhe conhguraìion,
number, and values of ìhe capaciìors are deìermined by ìhe acìual
circuiì requiremenìs.
Paras|t|cs
Parasiìics are ìhose nasìy liììle gremlins ìhaì creep inìo your PCB
(quiìe liìerally) and wreal havoc wiìhin your circuiì. They are ìhe
hidden sìray capaciìors and inducìors ìhaì inhlìraìe high-speed
circuiìs. They include inducìors formed by paclage leads and
excess ìrace lengìhs; pad-ìo-ground, pad-ìo-power-plane, and
pad-ìo-ìrace capaciìors; inìeracìions wiìh vias, and many more
possibiliìies. Iigure 3(a) is a ìypical schemaìic of a noninverìing
op amp. If parasiìic elemenìs were ìo be ìalen inìo accounì,
however, ìhe same circuiì would lool lile Iigure 3(b).
In high-speed circuiìs, iì doesn`ì ìale much ìo inßuence circuiì
performance. Someìimes iusì a few ìenìhs of a picofarad is
enough. Case in poinì: if only 1 pI of addiìional sìray parasiìic
capaciìance is presenì aì ìhe inverìing inpuì, iì can cause almosì
2 dB of pealing in ìhe frequency domain (Iigure 4). If enough
capaciìance is presenì, iì can cause insìabiliìy and oscillaìions.
R
G
V
I
A
V
= R
F
/R
G
+ 1
-V
+V R
F
R
L
(a)
TRACE
PAD
-V
+V
PAD
VIA
PAD
TRACE
PAD
TRACE
PAD
PAD
PAD PAD
V
O R
G
R
F
R
L
VIA
V
I
PAD
PAD
PAD
PAD
(b)
Fleure 3. Tvploal cp amp olroult. as deslened (a) and wlth parasltlos (b).
Aaa|oe 0|a|oeae 30-00, Septemher (2005) 3
10
8
6
4
2
0
1 300 100 30 10 3
FREQUENCY (MHz)
G
A
I
N

(
d
B
)
0pF
1pF
Fleure 4. ^ddltlcnal peaklne oaused bv parasltlo oapaoltanoe.
A few basic formulas for calculaìing ìhe size of ìhose gremlins
can come in handy when seeling ìhe sources of ìhe problemaìic
parasiìics. Equaìion 1 is ìhe formula for a parallel-plaìe capaciìor
(see Iigure 5).

C

d

11 3 .
pI

(1)
C is ìhe capaciìance, ¬ is ìhe area of ìhe plaìe in cm
2
, / is ìhe
relaìive dielecìric consìanì of board maìerial, and d is ìhe disìance
beìween ìhe plaìes in cenìimeìers.
A
d
Fleure 5. Capaoltanoe between twc plates.
Sìrip inducìance is anoìher parasiìic ìo be considered, resulìing
from excessive ìrace lengìh and lacl of ground plane. Equaìion 2
shows ìhe formula for ìrace inducìance. See Iigure 6.

Inducìance H
+ ( )
+
+ |
(
'
`
J
J
+

]
]
]
]
u uuu2
2
u 2235 u 5 . ln . . L
L
1 H
1 H
L
µ

(2)
1 is ìhe ìrace widìh, L is ìhe ìrace lengìh, and H is ìhe ìhiclness
of ìhe ìrace. All dimensions are in millimeìers.
H
L
W
Fleure 6. lnduotanoe cf a traoe leneth.
The oscillaìion in Iigure 7 shows ìhe effecì of a 2.54-cm ìrace
lengìh aì ìhe noninverìing inpuì of a high-speed op amp. The
equivalenì sìray inducìance is 29 nH (nanohenry), enough ìo
cause a susìained low-level oscillaìion ìhaì persisìs ìhroughouì ìhe
period of ìhe ìransienì response. The picìure also shows how using
a ground plane miìigaìes ìhe effecìs of sìray inducìance.
2.88
2.00
1.00
0.57
211.9 220.0 230.0 240.0 250.0
TIME (ns)
V
O
L
T
A
G
E

(
V
)
Fleure 7. lulse respcnse wlth÷and wlthcut÷ercund plane.
Vtas are anoìher source of parasiìics; ìhey can inìroduce boìh
inducìance and capaciìance. Equaìion 3 is ìhe formula for parasiìic
inducìance (see Iigure S).

L T
T
d
+

]
]
]
2
4
1 ln nH

(3)
T is ìhe ìhiclness of ìhe board and d is ìhe diameìer of ìhe via
in cenìimeìers.
d
D
1
D
2
GROUND PLANE
d
D
1
D
2
T
Fleure 8. vla dlmenslcns.
Equaìion 4 shows how ìo calculaìe ìhe parasiìic capaciìance of
a via (see Iigure S).

C
TD
D D
r

÷
u 55
1
2 1
. r
pI

(4)
d
r
is ìhe relaìive permeabiliìy of ìhe board maìerial. T is ìhe
ìhiclness of ìhe board. D
1
is ìhe diameìer of ìhe pad surrounding
ìhe via. D
2
is ìhe diameìer of ìhe clearance hole in ìhe ground plane.
All dimensions are in cenìimeìers. A single via in a u.157-cm-ìhicl
board can add 1.2 nH of inducìance and u.5 pI of capaciìance;
ìhis is why, when laying ouì boards, a consìanì vigil musì be lepì
ìo minimize ìhe inhlìraìion of parasiìes!
4 Aaa|oe 0|a|oeae 30-00, Septemher (2005)
0roaad P|aae
There is much more ìo discuss ìhan can be covered here, buì we`ll
highlighì some of ìhe ley feaìures and encourage ìhe reader ìo
pursue ìhe subiecì in greaìer deìail. A lisì of references appears aì
ìhe end of ìhis arìicle.
A ground plane acìs as a common reference volìage, provides
shielding, enables heaì dissipaìion, and reduces sìray inducìance
(buì iì also increases parasiìic capaciìance). While ìhere are many
advanìages ìo using a ground plane, care musì be ìalen when
implemenìing iì, because ìhere are limiìaìions ìo whaì iì can and
cannoì do.
Ideally, one layer of ìhe PCB should be dedicaìed ìo serve as ìhe
ground plane. Besì resulìs will occur when ìhe enìire plane is
unbrolen. Resisì ìhe ìempìaìion ìo remove areas of ìhe ground
plane for rouìing oìher signals on ìhis dedicaìed layer. The ground
plane reduces ìrace inducìance by magneìic-held cancellaìion
beìween ìhe conducìor and ìhe ground plane. When areas of ìhe
ground plane are removed, unexpecìed parasiìic inducìance can
be inìroduced inìo ìhe ìraces above or below ìhe ground plane.
Because ground planes ìypically have large surface and cross-
secìional areas, ìhe resisìance in ìhe ground plane is lepì ìo a
minimum. Aì low frequencies, currenì will ìale ìhe paìh of leasì
resisìance, buì aì high frequencies currenì follows ìhe paìh of
leasì tmpedance.
Neverìheless, ìhere are excepìions, and someìimes less ground
plane is beììer. High-speed cp amps will perform beììer if ìhe
ground plane is removed from under ìhe inpuì and ouìpuì pads.
The sìray capaciìance inìroduced by ìhe ground plane aì ìhe inpuì,
added ìo ìhe op amp`s inpuì capaciìance, lowers ìhe phase margin
and can cause insìabiliìy. As seen in ìhe parasiìics discussion, 1 pI
of capaciìance aì an op amp`s inpuì can cause signihcanì pealing.
Capaciìive loading aì ìhe ouìpuì÷including sìrays÷creaìes a pole
in ìhe feedbacl loop. This can reduce phase margin and could
cause ìhe circuiì ìo become unsìable.
Analog and digiìal circuiìry, including grounds and ground planes,
should be lepì separaìe when possible. Iasì-rising edges creaìe
currenì spiles ßowing in ìhe ground plane. These fasì currenì
spiles creaìe noise ìhaì can corrupì analog performance. Analog
and digiìal grounds (and supplies) should be ìied aì one common
ground poinì ìo minimize circulaìing digiìal and analog ground
currenìs and noise.
Aì high frequencies, a phenomenon called s/tn effect musì be
considered. Slin effecì causes currenìs ìo ßow in ìhe ouìer surfaces
of a conducìor÷in effecì maling ìhe conducìor narrower, ìhus
increasing ìhe resisìance from iìs dc value. While slin effecì is
beyond ìhe scope of ìhis arìicle, a good approximaìion for ìhe slin
depìh in copper, in cenìimeìers, is
Slin Depìh
Hz

( )
6 61 .
f

(5)
Less-suscepìible plaìing meìals can be helpful in reducing
slin effecì.
Packae|ae
Op amps are ìypically offered in a varieìy of paclages. The paclage
chosen can affecì an ampliher`s high-frequency performance.
The main inßuences are parasiìics (menìioned earlier) and stgna/
rcuttng. Here we will focus on rouìing inpuìs, ouìpuìs, and power
ìo ìhe ampliher.
Iigure 9 illusìraìes ìhe layouì differences beìween an op amp in
an SOIC paclage (a) and one in an SOT-23 paclage (b). Each
paclage ìype presenìs iìs own seì of challenges. Iocusing on
(a), close examinaìion of ìhe feedbacl paìh suggesìs ìhaì ìhere
are mulìiple opìions for rouìing ìhe feedbacl. Keeping ìrace
lengìhs shorì is paramounì. Parasiìic inducìance in ìhe feedbacl
can cause ringing and overshooì. In Iigures 9(a) and 9(b), ìhe
feedbacl paìh is rouìed around ìhe ampliher. Iigure 9(c) shows an
alìernaìive approach÷rouìing ìhe feedbacl paìh under ìhe SOIC
paclage÷which minimizes ìhe feedbacl paìh lengìh. Each opìion
has subìle differences. The hrsì opìion can lead ìo excess ìrace
lengìh, wiìh increased series inducìance. The second opìion uses
vias, which can inìroduce parasiìic capaciìance and inducìance.
The inßuence and implicaìions of ìhese parasiìics musì be ìalen
inìo consideraìion when laying ouì ìhe board. The SOT-23 layouì
is almosì ideal: minimal feedbacl ìrace lengìh and use of vias;
ìhe load and bypass capaciìors are reìurned wiìh shorì paìhs ìo
ìhe same ground connecìion; and ìhe posiìive rail capaciìors, noì
shown in Iigure 9(b), are locaìed direcìly under ìhe negaìive rail
capaciìors on ìhe boììom of ìhe board.
R
F
-V
S
CERAMIC
BYPASS
ELECTROLYTIC
BYPASS
+
CERAMIC
BYPASS
OPTIONAL
CAPACITOR
V
IN
DISABLE
R
G
V
OUT
CERAMIC
BYPASS
ELECTROLYTIC
BYPASS
+
+V
S
(a)
E
L
E
C
T
R
O
L
Y
T
I
C
B
Y
P
A
S
S
+
C
E
R
A
M
I
C
B
Y
P
A
S
S
R
L
R
F
R
G
V
OUT
-V
S
V
OUT
V
IN
+V
S
BYPASS CAPS ARE
ON BOTTOM OF BOARD
WITH GROUND RETURNS
IMMEDIATELY UNDER R
L
+V
+IN -IN
(b)
(c)
CERAMIC
BYPASS
ELECTROLYTIC
BYPASS
+
+V
S
R
F
-V
S
V
IN
DISABLE
R
G
V
OUT
CERAMIC
BYPASS
ELECTROLYTIC
BYPASS
+
CERAMIC
BYPASS
OPTIONAL
CAPACITOR
Fleure 9. Lavcut dlfferenoes fcr an cpamp olroult. (a) S0lC
paokaee. (b) S0T23. and (o) S0lC wlth R
F
underneath bcard.
Aaa|oe 0|a|oeae 30-00, Septemher (2005) 5
Lcv-dtstcrttcn amp/tfer ptncut. A new low-disìorìion pinouì,
available in some Analog Devices op amps (ìhe ADSu45,
1
for
example), helps eliminaìe boìh of ìhe previously menìioned
problems; and iì improves performance in ìwo oìher imporìanì
areas as well. The LICSP`s low-disìorìion pinouì, as shown in
Iigure 1u, ìales ìhe ìradiìional op amp pinouì, roìaìes iì counìer-
cloclwise by one pin and adds a second ouìpuì pin ìhaì serves as
a dedicaìed feedbacl pin.
AD8099 DISABLE 1
FEEDBACK 2
–IN 3
+IN 4
+V
S
V
OUT
C
C
–V
S
8
7
6
5
Fleure 10. 0p amp wlth lcwdlstcrtlcn plncut.
The low-disìorìion pinouì permiìs a close connecìion beìween
ìhe ouìpuì (ìhe dedicaìed feedbacl pin) and ìhe inverìing inpuì,
as shown in Iigure 11. This greaìly simplihes and sìreamlines
ìhe layouì.
R
F
V
O
V
IN
-V
S
DISABLE
R
L
R
G
CERAMIC
BYPASS
ELECTROLYTIC
BYPASS
+
+V
S
CERAMIC
BYPASS
ELECTROLYTIC
BYPASS
+
Fleure 11. lCB lavcut fcr ^D8045 lcwdlstcrtlcn cp amp.
Anoìher benehì is decreased second harmonic disìorìion. One
cause of second-harmonic disìorìion in convenìional op-amp pin
conhguraìions is ìhe coupling beìween ìhe noninverìing inpuì and
ìhe negaìive supply pin. The low-disìorìion pinouì for ìhe LICSP
paclage eliminaìes ìhis coupling and greaìly reduces second-
harmonic disìorìion; in some cases ìhe reducìion can be as much
as 14 dB. Iigure 12 shows ìhe difference in disìorìion performance
beìween ìhe ADSu99
2
SOIC and ìhe LICSP paclage.
This paclage has yeì anoìher advanìage÷in power dissipaìion.
The LICSP provides an exposed paddle, which lowers ìhe ìhermal
resisìance of ìhe paclage and can improve U
]A
by approximaìely
4u%. Wiìh iìs lower ìhermal resisìance, ìhe device runs cooler,
which ìranslaìes inìo higher reliabiliìy.
-50
-60
-70
-80
-90
-100
-110
-120
0.1 10 1
FREQUENCY (MHz)
H
A
R
M
O
N
I
C

D
I
S
T
O
R
T
I
O
N

(
d
B
c
)
G = +5
V
OUT
= 2V p-p
V
S
= 5V
R
L
= 1006
SOIC
CSP
SOLID LINES¬SECOND HARMONIC
DOTTED LINES¬THIRD HARMONIC
Fleure 12. ^D8099 dlstcrtlcn ocmparlscn÷the same
cp amp ln S0lC and LFCSl paokaees.
Aì presenì, ìhree Analog Devices high-speed op amps are
available wiìh ìhe new low-disìorìion pinouì: ADSu45, ADSu99,
and ADSuuu.
3
koat|ae aad Sh|e|d|ae
A wide varieìy of analog and digiìal signals, wiìh high- and low
volìages and currenìs, ranging from dc ìo CHz, exisìs on circuiì
boards. Keeping signals from inìerfering wiìh one anoìher can
be difhculì.
Recalling ìhe advice ìo "Trusì No One,¨ iì is criìical ìo ìhinl ahead
and come up wiìh a plan for how ìhe signals will be processed on
ìhe board. Iì is imporìanì ìo noìe which signals are sensiìive and
ìo deìermine whaì sìeps musì be ìalen ìo mainìain ìheir inìegriìy.
Cround planes provide a common reference poinì for elecìrical
signals, and ìhey can also be used for shielding. When signal
isolaìion is required, ìhe hrsì sìep should be ìo provide physical
disìance beìween ìhe signal ìraces. Here are some good pracìices
ìo observe:
· Minimizing long parallel runs and close proximiìy of signal
ìraces on ìhe same board will reduce inducìive coupling.
· Minimizing long ìraces on adiacenì layers will prevenì
capaciìive coupling.
· Signal ìraces requiring high isolaìion should be rouìed on
separaìe layers and÷if ìhey cannoì be ìoìally disìanced÷
should run orìhogonally ìo one anoìher wiìh ground plane
in beìween. Orìhogonal rouìing will minimize capaciìive
coupling, and ìhe ground will form an elecìrical shield.
This ìechnique is exploiìed in ìhe formaìion of ccntrc//ed-
tmpedance lines.
High-frequency (RI) signals are ìypically run on conìrolled-
impedance lines. Thaì is, ìhe ìrace mainìains a characìerisìic
impedance, such as 5u ohms (ìypical in RI applicaìions).
Two common ìypes of conìrolled-impedance lines, mtcrcstrtp
4

and strtp/tne
5
can boìh yield similar resulìs, buì wiìh differenì
implemenìaìions.
0 Aaa|oe 0|a|oeae 30-00, Septemher (2005)
A microsìrip conìrolled-impedance line, shown in Iigure 13,
can be run on eiìher side of a board; iì uses ìhe ground plane
immediaìely beneaìh iì as a reference plane.
GROUND PLANE
DIELECTRIC H
TRACE
W
T
Fleure 13. ^ MICROSTRIP transmlsslcn llne.
Equaìion 6 can be used ìo calculaìe ìhe characìerisìic impedance
for an IR4 board.

Z
r
u
S7
1 41
5 9S
u S

+ ( )

]
]
]
] r .
ln
.
.
H
1 +T

(6)
H is ìhe disìance in from ìhe ground plane ìo ìhe signal ìrace,
1 is ìhe ìrace widìh, T is ìhe ìrace ìhiclness; all dimensions
are in mils (inches 1u
÷3
). d
r
is ìhe dielecìric consìanì of ìhe
PCB maìerial.
Sìripline conìrolled-impedance lines (see Iigure 14) use ìwo layers
of ground plane, wiìh signal ìrace sandwiched beìween ìhem. This
approach uses more ìraces, requires more board layers, is sensiìive
ìo dielecìric ìhiclness variaìions, and cosìs more÷so iì is ìypically
used only in demanding applicaìions.
EMBEDDED
TRACE
DIELECTRIC
GROUND,
POWER
PLANES
W
T
H
H
B
Fleure 14. Strlpllne ocntrclledlmpedanoe llne.
The characìerisìic-impedance design equaìion for sìripline is
shown in equaìion 7.

Z
r
u
6u 1
u S
O
( )

( )
( )

]
]
]
] r
ln
.
.9
+
E
1 T

(7)
Cuard ri ngs, or "guardi ng,¨ is anoìher common ìype of
shieldi ng used wiìh op amps; iì is used ìo prevenì sìray
currenìs f rom enìeri ng sensiìive nodes. The pri nciple is
sìraighìforward÷compleìely surround ìhe sensiìive node wiìh a
guard conducìor ìhaì is lepì aì, or driven ìo (aì low impedance)
ìhe same poìenìial as ìhe sensiìive node, and ìhus sinls sìray
currenìs away from ìhe sensiìive node. Iigure 15(a) shows ìhe
guard ring schemaìics for inverìing and noninverìing op-amp
conhguraìions. Iigure 15(b) shows a ìypical implemenìaìion
of boìh guard rings for a SOT-23-5 paclage.
INVERTING
GUARD
RING
NONINVERTING
GUARD
RING
(a)
INVERTING
AD8067
V
OUT
–V
+IN
+V
–IN
NONINVERTING
AD8067
V
OUT
–V
+IN
+V
–IN
(b)
Fleure 15. Cuard rlnes. (a) lnvertlne and ncnlnvertlne
cperatlcn. (b) S0T235 paokaee.
There are many oìher opìions for shielding and rouìing. The reader
is encouraged ìo review ìhe references below for more informaìion
on ìhis and oìher ìopics menìioned above.
00N0luSI0N
Inìelligenì circuiì-board layouì is imporìanì ìo successful op-amp
circuiì design, especially for high-speed circuiìs. A good schemaìic
is ìhe foundaìion for a good layouì; and close coordinaìion beìween
ìhe circuiì designer and ìhe layouì designer is essenìial, especially
in regard ìo ìhe locaìion of parìs and wiring. Topics ìo consider
include power-supply bypassing, minimizing parasiìics, use of
ground planes, ìhe effecìs of op-amp paclaging, and meìhods of
rouìing and shielding.
I0k IukIߣk k£A0IN0
Ardizzoni, ]ohn, "Keep High-Speed Circuiì-Board Layouì on
Tracl,¨ II Ttmes, May 23, 2uu5.
Brolaw, Paul, "An IC Amplifier Lser`s Cuide ìo Decoupling,
Crounding, and Maling Things Co Righì for a Change,¨
Analog Devices Applicaìion Noìe AN-2u2.
Brolaw, Paul and ]eff Barrow, "Crounding for Low- and High-
Irequency Circuiìs,¨ Analog Devices Applicaìion Noìe AN-345.
Buxìon, ]oe, "Careful Design Tames High-Speed Op Amps,¨
Analog Devices Applicaìion Noìe AN-257.
DiSanìo, Creg, "Proper PC-Board Layouì Improves Dynamic
Range,¨ IDN, November 11, 2uu4.
Cranì, Doug and Scoìì Wurcer, "Avoiding Passive-Componenì
Piìfalls,¨ Analog Devices Applicaìion Noìe AN-34S.
]ohnson, Howard W. and Marìin Craham, Htgh-Speed Dtgtta/
Destgn, a Handbcc/ cf E/ac/ Magtc, Prenìice Hall, 1993.
]ung, Walì, ed., Op ¬mp ¬pp/tcattcns Handbcc/, Elsevier-Newnes, 2uu5.
k£I£k£N0£S-VAlI0 AS 0I S£PI£N8£k 2005
1
ADI websiìe: www.analog.com (Search) ADSu45 (Co)
2
ADI websiìe: www.analog.com (Search) ADSu99 (Co)
3
ADI websiìe: www.analog.com (Search) ADSuuu (Co)
4
hììp://www.microwaves1u1.com/encyclopedia/microsìrip.cfm
5
hììp://www.microwaves1u1.com/encyclopedia/sìripline.cfm

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