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JK RS T Flip-Flop Design

JK RS T Flip-Flop Design

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JK, RS, T Flip-Flop Design

Design Practice - MyCAD

Table of Contents • • Preface NAND2 Design – NAND2 schematic and symbol – NAND2 simulation – NAND2 layout and results of verification NAND3 Design – NAND3 schematic and symbol – NAND3 simulation – NAND3 layout and results of verification JK Flip-Flop Design – JK Flip-Flop schematic and symbol – JK Flip-Flop simulation – JK Flip-Flop layout and results of verification RS Flip-Flop Design – RS Flip-Flop schematic and symbol – RS Flip-Flop simulation – RS Flip-Flop layout and results of verification T Flip-Flop Design – T Flip-Flop schematic and symbol – T Flip-Flop simulation – T Flip-Flop layout and results of verification • • • • JK. RS. T Flip-Flop Design Practice .MyCAD 2 .

T FlipFlop schematic and layout. RS. RS. SELOCO Incorporated. JK. T Flip-Flop Design Practice . – MyCAD Tutorial : Learn how to use schematic and layout editor. – MySpice Tutorial : Learn about simulating a circuit.MyCAD 3 . RS. JK. please refer to the related documents as below. If you want to get more information. Copyright © 1992 – 2006.Preface • • • This document provides the information on how to design JK. – MyChip Pro Verification Reference Manual : Look up specific verification commands. T Flip-Flop is designed based on MOSIS SCMOS layout rules.

MyCAD 4 . T Flip-Flop Design Practice . RS.NAND2 schematic and symbol Logic Symbol IN0 0 0 1 1 IN1 0 1 0 1 OUT 1 1 1 0 Truth Table Schematic JK.

MyCAD 5 . T Flip-Flop Design Practice .NAND2 Simulation IN0 OUT IN1 JK. RS.

NAND2 layout and results of verification DRC result Layout JK.MyCAD LVS result 6 . RS. T Flip-Flop Design Practice .

RS.NAND3 schematic and symbol Logic Symbol Input A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Output OUT 1 1 1 1 1 1 1 0 Truth Table Schematic Design Practice . T Flip-Flop .MyCAD 7 JK.

T Flip-Flop Design Practice . RS.NAND3 Simulation IN0 IN1 IN2 JK.MyCAD OUT 8 .

RS.NAND3 layout and results of verification DRC result Layout JK. T Flip-Flop Design Practice .MyCAD LVS result 9 .

RS.JK FF schematic and symbol Logic Symbol Input J 0 0 1 1 K 0 1 0 1 Qn+1 Qn 0 1 Qn' Output 동작 불변 리셋 세트 반전 Truth Table Schematic JK. T Flip-Flop Design Practice .MyCAD 10 .

MyCAD 11 . T Flip-Flop Design Practice .JK FF Simulation J Q K Q_bar CLK JK. RS.

MyCAD LVS result 12 . RS. T Flip-Flop Design Practice .JK FF layout and results of verification DRC result Layout JK.

RS FF schematic and symbol Logic Symbol Input S 0 0 1 1 R 0 1 0 1 Q Output 동작 전 상태유지 0 1 리셋 세트 사용불가 Truth Table Schematic JK.MyCAD 13 . T Flip-Flop Design Practice . RS.

T Flip-Flop Design Practice .MyCAD 14 .RS FF Simulation S Q R Q_bar CLK JK. RS.

T Flip-Flop Design Practice .MyCAD LVS result 15 . RS.RS FF layout and results of verification DRC result Layout JK.

T Flip-Flop Design Practice .T FF schematic and symbol Logic Symbol Input T 0 1 Output Q Q0 Q0' Truth Table Schematic JK. RS.MyCAD 16 .

T Flip-Flop Design Practice . RS.MyCAD 17 .T FF Simulation T Q CLK Q_bar JK.

T Flip-Flop Design Practice .MyCAD LVS result 18 . RS.T FF layout and results of verification DRC result Layout JK.

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