1.3.

OVERLOADED OPERATORS
Description bitwise-and bitwise-or bitwise-xor bitwise-not Left u/l,uv,lv u/l,uv,lv u/l,uv,lv Operator and or xor not Right u/l,uv,lv u/l,uv,lv u/l,uv,lv u/l,uv,lv

2.4. CONVERSION FUNCTIONS
From un,lv sg,lv un,sg un,sg na in To sg un lv in un sg Function SIGNED(from) UNSIGNED(from) STD_LOGIC_VECTOR(from) TO_INTEGER(from) TO_UNSIGNED(from) TO_SIGNED(from)

1164 PACKAGES QUICK REFERENCE CARD
REVISION 1.0
() {} bold b u/l bv uv lv un sg na in sm
c

1.4. CONVERSION FUNCTIONS
From u/l uv,lv b bv,ul bv,lv To b bv u/l lv uv Function TO_BIT(from, [xmap]) TO_BITVECTOR(from, [xmap]) TO_STDULOGIC(from) TO_STDLOGICVECTOR(from) TO_STDULOGICVECTOR(from)

3. IEEE’S NUMERIC_BIT
3.1. PREDEFINED TYPES
UNSIGNED(na to | downto na) Array of BIT SIGNED(na to | downto na) Array of BIT

Grouping Repeated As is ::= ::= ::= ::= ::= ::= ::= ::= ::= ::= ::=

[] | CAPS

Optional Alternative User Identifier

BIT STD_ULOGIC/STD_LOGIC BIT_VECTOR STD_ULOGIC_VECTOR STD_LOGIC_VECTOR UNSIGNED SIGNED NATURAL INTEGER SMALL_INT (subtype INTEGER range 0 to 1) commutative

3.2. OVERLOADED OPERATORS
Left Op Right Return abs sg sg sg sg +,-,*,/,rem,mod un un +,-,*,/,rem,mod sg sg +,-,*,/,rem,mod c na un +,-,*,/,rem,mod c in sg <,>,<=,>=,=,/= un bool <,>,<=,>=,=,/= sg bool <,>,<=,>=,=,/= c na bool <,>,<=,>=,=,/= c in bool

1.5. PREDICATES
RISING_EDGE(SIGID) Rise edge on signal ? FALLING_EDGE(SIGID) Fall edge on signal ? IS_X(OBJID) Object contains ‘X’ ? un sg un sg un sg un sg

2. IEEE’S NUMERIC_STD
2.1. PREDEFINED TYPES
UNSIGNED(na to | downto na) SIGNED(na to | downto na) Arrays of STD_LOGIC

1. IEEE’S STD_LOGIC_1164
1.1. LOGIC VALUES
‘U’ ‘X’/’W’ ‘0’/’L’ ‘1’/’H’ ‘Z’ ‘-’ Uninitialized Strong/Weak unknown Strong/Weak 0 Strong/Weak 1 High Impedance Don’t care

3.3. PREDEFINED FUNCTIONS
SHIFT_LEFT(un, na) SHIFT_RIGHT(un, na) SHIFT_LEFT(sg, na) SHIFT_RIGHT(sg, na) ROTATE_LEFT(un, na) ROTATE_RIGHT(un, na) ROTATE_LEFT(sg, na) ROTATE_RIGHT(sg, na) RESIZE(sg, na) RESIZE(un, na) un un sg sg un un sg sg sg un

2.2. OVERLOADED OPERATORS
Left Op Right Return abs sg sg sg sg +,-,*,/,rem,mod un un +,-,*,/,rem,mod sg sg +,-,*,/,rem,mod c na un +,-,*,/,rem,mod c in sg <,>,<=,>=,=,/= un bool <,>,<=,>=,=,/= sg bool <,>,<=,>=,=,/= c na bool <,>,<=,>=,=,/= c in bool

1.2. PREDEFINED TYPES
STD_ULOGIC Subtypes: STD_LOGIC X01 X01Z UX01 UX01Z Base type Resolved STD_ULOGIC Resolved X, 0 & 1 Resolved X, 0, 1 & Z Resolved U, X, 0 & 1 Resolved U, X, 0, 1 & Z

un sg un sg un sg un sg

3.4. CONVERSION FUNCTIONS
From un,bv sg,bv un,sg un,sg na in To sg un bv in un sg Function SIGNED(from) UNSIGNED(from) BIT_VECTOR(from) TO_INTEGER(from) TO_UNSIGNED(from) TO_SIGNED(from)

2.3. PREDEFINED FUNCTIONS
SHIFT_LEFT(un, na) SHIFT_RIGHT(un, na) SHIFT_LEFT(sg, na) SHIFT_RIGHT(sg, na) ROTATE_LEFT(un, na) ROTATE_RIGHT(un, na) ROTATE_LEFT(sg, na) ROTATE_RIGHT(sg, na) RESIZE(sg, na) RESIZE(un, na) un un sg sg un un sg sg sg un

STD_ULOGIC_VECTOR(na to | downto na) Array of STD_ULOGIC STD_LOGIC_VECTOR(na to | downto na) Array of STD_LOGIC

© 1995 Qualis Design Corporation. Permission to reproduce and distribute strictly verbatim copies of this document in whole is hereby granted. See reverse side for additional information.

© 1995 Qualis Design Corporation

© 1995 Qualis Design Corporation

OVERLOADED OPERATORS Left Op Right Return + uv uv + lv lv +.sg sg.=. [justify]. [width]). [justify]. uv. 0 or 1 6. in) un un sg sg lv lv lv lv lv lv lv 7.<=.-. uv) COND(bool. SYNOPSYS’ STD_LOGIC_SIGNED 7. un) SHR(sg.1. CONVERSION FUNCTIONS From To Function un.u lv CONV_STD_LOGIC_VECTOR(from.*.un. OVERLOADED OPERATORS Left Op Right Return abs sg sg.*. HWRITE(line.sg. [width]).<=. [justify]. lv.*.u sg CONV_SIGNED(from. [width]).-c in uv <.>=.*. SYNOPSYS’ STD_LOGIC_UNSIGNED 6.>=. na) SH_RIGHT(lv./ c un sg.=.. u/l./= c Right Return lv lv lv lv lv lv in lv u/l lv lv bool in bool 9. size) in./= lv bool <.*. Read/write octal values OREAD(line./= c in bool 6.lv +.-./ sg sg.-c in lv +.-. lv.>.lv +. uv.u un CONV_UNSIGNED(from. size) uv TO_STDULOGICVECTOR(from.>=..-. lv.1.=. [good]).<=. lv) COND_OP(bool.c u/l lv <. [justify].<=. u/l) Shift operations: SH_LEFT(lv.1.<=./= c in bool <.2.=.-. Read/write hexadecimal values HREAD(line.-c +. na) lv uv u/l lv uv lv uv lv uv lv uv 4.lv +./ u/l u/l +.c u/l sg.uv. [good]). un) SHL(sg.3.un lv STD_LOGIC_VECTOR(from) un. OWRITE(line. na) ALIGN_SIZE(uv. 9. HREAD(line..sg in CONV_INTEGER(from) in. HWRITE(line. WRITE(line./= c in bool <. PREDEFINED TYPES UNSIGNED(na to | downto na) SIGNED(na to | downto na) Arrays of STD_LOGIC SMALL_INT Integer. OR USA Phone: +1-503-531-0377 FAX: +1-503-629-5525 E-mail: info@qualis. size) 5.sg. uv.3. [good]).c <.2. [width]).-.lv +.=.=.un.>=. WRITE(line.4./= un bool <.<=.* uv uv +.>=. SYNOPSYS’ STD_LOGIC_ARITH 4.>. size) in./= c in bool 9. CONVERSION FUNCTIONS zero-extend sign-exten From lv To in Function CONV_INTEGER(from) 4. size) 8.<=. OWRITE(line.* +.>.>.<=.lv +. Permission to reproduce and distribute strictly verbatim copies of this document in whole is hereby granted.=. CONVERSION FUNCTIONS From lv. Qualis Design Corporation Beaverton.>.un. lv. na) ALIGN_SIZE(u/l.2. na) SH_RIGHT(uv.*.. u/l.>=.lv + un un. READ(line./ lv lv +.=.4. SYNOPSYS’ STD_LOGIC_MISC 5.* lv lv +..>=. na) Resize functions: ALIGN_SIZE(lv. uv. PREDEFINED FUNCTIONS C-like ?: replacements: COND_OP(bool.=.lv +. [good]).-.lv un UNSIGNED(from) sg.>. un) SHR(un.lv +.lv +.+.-./= sg bool <.com Also available: VHDL Quick Reference Card Verilog HDL Quick Reference Card © 1995 Qualis Design Corporation © 1995 Qualis Design Corporation .. un) EXT(lv.2.<=. na) SH_LEFT(uv.>.sg.-c in lv +. uv. lv. [justify]. [good]). u/l. OVERLOADED OPERATORS Left lv lv lv lv lv Op Right Return + lv lv +.lv <.=. PREDEFINED FUNCTIONS SHL(un.lv sg SIGNED(from) sg. READ(line.1.-.-.c u/l un./ un un.>. SYNOPSYS’ STD_LOGIC_TEXTIO Read/write binary values READ(line.>. CONVERSION FUNCTIONS From lv To in Function CONV_INTEGER(from) un sg sg un sg un sg un sg un sg u/l lv lv lv uv uv uv lv uv 7. [justify]. na) ALIGN_SIZE(u/l. lv. [good]). [good]). WRITE(line.1. OREAD(line.c in sg.c in un. [width]).>=./= c in bool 4.>=. in) SEXT(lv. [justify].*c u/l uv +./= <. PREDEFINED FUNCTIONS AND_REDUCE(lv | uv) OR_REDUCE(lv | uv) XOR_REDUCE(lv | uv) u/l u/l u/l © 1995 Qualis Design Corporation. [width]). [width]).<=.u/l in in To Function in TO_INTEGER(from) lv TO_STDLOGICVECTOR(from. CADENCE’S STD_LOGIC_ARITH 9. OVERLOADED OPERATORS Left Op abs +.>./c u/l lv +.>=. uv. lv. uv.

Sign up to vote on this title
UsefulNot useful