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D D
CPU1
01-CPU1.Sch

CPU2
02-CPU2.Sch

CPU3
03-CPU3.Sch

SDRAM
04-MEM.sch

C C
UART_USB_ETC
05-UART_USB_POWER.sch

Audio
mini2440原理图
06-Audio.sch

DM9000
07-DM9000.sch

Interface
08-INTERFACE.sch

B B

A A

Title

Size
友善之臂计算机科技有限公司
Number Revision
B
Date: 19-Jul-2009 Sheet of
File: D:\mini2440\原理图\mini2440 原理图.ddb Drawn By:
1 2 3 4 5 6
1 2 3 4 5 6

D D
VDD33V
R64
4.7K S2
NORBOOT
1

BUS

BUS
J1
OM0
1
OM0
2 从NOR FLASH启动系统, 一般为BIOS模式
2 CON3 3
3 4 从NAND FLASH启动系统,一般为正常运行模式

nXDACK0

nXDREQ0

D3 nLAN_CS
NANDBOOT 5

nLED_3

nLED_4

K2 nLED_1
L5 nLED_2
F6 nGCS0
B2 nGCS1
C3 nGCS2
C4 nGCS3

C2 nGCS5

E4 nWAIT
E6 LnWE
C5 LnOE
CON5
R35 4.7K C5 XTIpll

R13
T15
K7
K6
K5
15p

L3
X2
U1A 12M
C6

nGCS0
nXDREQ0/GPB10

nGCS1/GPA12
nGCS2/GPA13
nGCS3/GPA14
nGCS4/GPA15
nGCS5/GPA16

nWAIT

OM0
OM1
nXDREQ1/GPB8

nXBREQ/GPB6
nXDACK0/GPB9
nXDACK1/GPB7

nXBACK/GPB5

nOE

nWE
XTOpll
15p
D12 LDATA0
DATA0
C12 LDATA1
DATA1
E11 LDATA2
DATA2
A13 LDATA3
DATA3
LADDR0 F7 F10 LDATA4
ADDR/GPA0 DATA4
LADDR1 E7 F11 LDATA5
C ADDR1 DATA5 C
LADDR2 B7 DMA Chip Select C13 LDATA6
ADDR2 DATA6
LADDR3 F8 A14 LDATA7
ADDR3 DATA7
LADDR4 C7 D13 LDATA8
ADDR4 DATA8
LADDR5 D8 B15 LDATA9
ADDR5 DATA9
LADDR6 E8 A17 LDATA10
ADDR6 DATA10
LADDR7 D7 C14 LDATA11
ADDR7 DATA11
LADDR8 G8 D15 LDATA12
ADDR8 DATA12
LADDR9 B8 C15 LDATA13
ADDR9 DATA13
LADDR10 A8 D14 LDATA14
ADDR10 DATA14
LADDR11 C8 B17 LDATA15
ADDR11 DATA15
LADDR12 B9 S3C2440 C16 LDATA16
ADDR12 DATA16
LADDR13 H8 Address E15 LDATA17
ADDR13 DATA17
LADDR14 E9 Data E14 LDATA18
ADDR14 DATA18
LADDR15 C9 E13 LDATA19 22p
ADDR15 DATA19
LADDR16 D9 E12 LDATA20 XTIrtc
ADDR16 DATA20
LADDR17 G9 E16 LDATA21
ADDR17 DATA21
LADDR18 F9 F15 LDATA22 C1
ADDR18 DATA22 X1
LADDR19 H9 G13 LDATA23
ADDR19 DATA23 32.768kHz
LADDR20 D10 E17 LDATA24
ADDR20 DATA24
LADDR21 C10 G12 LDATA25
ADDR21 DATA25
LADDR22 H10 F14 LDATA26 XTOrtc

TCLK1/EINT19/GPG11
ADDR22 DATA26
LADDR23 E10 ADC Clock Timer F12 LDATA27
ADDR23 DATA27
LADDR24 C11 G11 LDATA28 C2
CLKOUT1/GPH10
ADDR24 DATA28
CLKOUT0/GPH9

B LADDR25 G10 G16 LDATA29 22p B


ADDR25 DATA29
LDATA30

TOUT0/GPB0
TOUT1/GPB1
TOUT2/GPB2
TOUT3/GPB3
TCLK0/GPB4
D11 H13
AIN4/TSYM

AIN6/TSXM

ADDR26 DATA30
AIN5/TSYP

AIN7/TSXP

F13 LDATA31
MPLLCAP
UPLLCAP

DATA31
EXYCLK

XTOpll

XTOrtc
XTIpll

XTIrtc
AIN0
AIN1
AIN2
AIN3

OM2
OM3
Aref

S3C2440X
U17

U16

H12
R9

N14

G14
G15

U12
J6
J5
J7
R14

R15
P15

R16
P16

P10

P17
P13

M14

K3
K4
T16
T17

T13

L12
CLKOUT0
CLKOUT1
MPLLCAP

L3CLOCK
UPLLCAP

L3MODE
TSYM

TSXM

L3DATA
TSYP

TSXP
AIN0
AIN1
AIN2
AIN3

EINT19
XTOpll

XTOrtc
XTIpll

XTIrtc

GPB0
GPB1

VDD33V

VDD33V
R68
4.7K MPLLCAP UPLLCAP
C40 C41
2n7 680p

A A

Title

Size
友善之臂计算机科技有限公司
Number Revision
B
Date: 19-Jul-2009 Sheet of
File: D:\mini2440\原理图\mini2440 原理图.ddb Drawn By:
1 2 3 4 5 6
1 2 3 4 5 6

VDD33V

NR1

NR2

NR3

NR4
10K

10K

10K

10K
NCON
GPG13
D GPG14 D
GPG15 128M-1G Nand Flash版mini2440需要去掉NR4, NR5

GPIO_IO
GPIO_IO

GPIO_IO
GPIO_IO
GPIO_IO
GPIO_IO
GPIO_IO
GPIO_IO
GPIO_IO
GPIO_IO
原理见S3C2440数据手册

1K

1K
NR5

NR8
I2SLRCK
I2SSCLK

SPIMISO

SPIMOSI

nSS_SPI
I2CSDA

I2SSDO

SPICLK
I2CSCL
RA7

EINT13

EINT14

EINT15

EINT11

EINT20
CDCLK

GPG13
GPG14
GPG15
I2SSDI

PDN0
PDP0
LSCLK1 1 8 LLSCLK1

DN0
DP0
LnSRAS 2 7 LLnSRAS
LnSCAS 3 6 LLnSCAS

M10
K10

N11
N12
U14

U13
LSCKE LLSCKE

R11

R10
L10

T11
L11
P12
4 5

M9

J10
U8

U6

K9
R7
T7
L8

L9
P7

P9
VDD33V
U1B
22
R17 R22

SPIMISO1/EINT13/GPG5

SPIMOSI1/EINT14/GPG6
I2SSDO/I2SSDI/GPE4

nSS0/EINT10/GPG2
nSS1/EINT11/GPG3
SPICLK0/GPE13
IICSCL/GPE14

EINT20/GPG12
EINT21/GPG13
EINT22/GPG14
EINT23/GPG15
DP0
SPICLK1/EINT15/GPG7
I2SLRCK/GPE0
I2SSCLK/GPE1
CDCLK/GPE2
I2SSDI/nSS0/GPE3

SPIMISO0/GPE11

SPIMOSI0/GPE12
IICSDA/GPE15

DN1/PDN0
DP1/PDP0
DN0
R55 22 10K 10K
LLSCLK0 LSCLK0

LLnSCS0
R63 22 LnSCS0 LnWBE0 D4
nBE0:nWBE0:DQM0
LnWBE1 B5 N2 VD0
nBE1:nWBE1:DQM1 VD0/GPC8
LnWBE2 D5 L6 VD1 EINT19
nBE2:nWBE2:DQM2 VD1/GPC9
LnWBE3 E5 USS N4 VD2 EINT15
C nBE3:nWBE3:DQM3 VD2/GPC10 C
LLnSCS0 D2 R1 VD3 EINT14
nGCS6:nSCS0 VD3/GPC11
E3 IIC N3 VD4 EINT13
nGCS7:nSCS1 VD4/GPC12
LLnSCAS D6 IIS P2 VD5 EINT11
nSCAS VD5/GPC13
LLnSRAS C6 M6 VD6 EINT8
nSRAS VD6/GPC14
LLSCKE VD7

2
A2 SDRAM SPI P3
SCKE VD7/GPC15
LLSCLK0 B4 R2 VD8 K1 K2 K3 K4 K5 K6
SCLK0 VD8/GPD0
LLSCLK1 B3 M5 VD9
SCLK1 VD9/GPD1
TSP N5 VD10
VD10/GPD2
ALE D1 R3 VD11
ALE/GPA18 VD11/GPD3
CLE F5 P4 VD12
CLE/GPA17 VD12/GPD4
RnB G6 R4 VD13

1
FRnB VD13/GPD5/USBTXDN1
NCON R12 NAND CTRL P5 VD14
NCON VD14/GPD6/USBTXDP1
nFCE F4 N6 VD15
nFCEGPA22 VD15/GPD7/USBOEN1 CON12
nFRE E1 M7 VD16
nFRE/GPA20 VD16/GPD8/SPIMISO1 GND
nFWE F3 LCD DATA T4 VD17 8
nFWE/GPA19 VD17/GPD9/SPIMOSI1 VDD33V
R5 VD18 7
VD18/GPD10/LPICLK1 EINT19 GPG11
SDCLK N8 T5 VD19 6
SDCLK/GPE5 VD19/GPD11/USBRXDP1 EINT15 GPG7
SDCMD K8 LCD CTRL P6 VD20 5
SDCMD/GPE6 VD20/GPD12/USBRXDN1 EINT14 GPG6
SDDATA0 R8 SDIO R6 VD21 4

LCD_PWREN/EINT12/GPG4
SDDATA0/GPE7 VD21/GPD13/USBRXD1 EINT13 GPG5
SDDATA1 M8 N7 VD22 3
SDDATA1/GPE8 VD22/nSS1/GPD14 EINT11 GPG3

VFRAME:VSYNC/GPC3
SDDATA2 P8 UART U5 VD23 2
EINT8 GPG0

LCD_LPCREVB/GPC7
SDDATA2/GPE9 VD23/nSS0/GPD15

VLINE:HSYNC/GPC2
SDDATA3 J9 1

LCD_LPCREV/GPC6
SDDATA3/GPE10
nCTS1/RXD2/GPH7
nRTS1/TXD2/GPH6

LCD_LPCOE/GPC5
CON8

VM:VDEN/GPC4
B B
JTAG
nCTS0/GPH0
nRTS0/GPH1

UCLK/GPH8

VCLK/GPC1
LEND/GPC0
RXD0/GPH3

RXD1/GPH5
TXD0/GPH2

TXD1/GPH4

nTRST

TDO
TMS
TCK
TDI
S3C2440X
K11

K13
K14
K16
K17
J11
J15
K15

H15
J13
H17
J16
J14

M1

M4
M3
M2
L1
L4

L7

P11
L17

P1
VDD33V

nLED_1 LED1 R401K

LCD_PWR
VFRAME

USB_EN
LCDVF1
LCDVF2
GREEN
WP_SD

nTRST
nCTS0
nRTS0

VLINE
VCLK
RXD0

RXD1

RXD2

LEND
TXD0

TXD1

TXD2

R411K
TMS
TCK

TDO

nLED_2 LED2
TDI

VM
GREEN
nLED_3 LED3 R421K

GREEN
nLED_4 LED4 R431K

GREEN

A A

Title

Size
友善之臂计算机科技有限公司
Number Revision
B
Date: 19-Jul-2009 Sheet of
File: D:\mini2440\原理图\mini2440 原理图.ddb Drawn By:
1 2 3 4 5 6
1 2 3 4 5 6

VDD33V

D7
1N4148 TP1
D D8 CON1 D
R12 VDDRTC

1
10K
BAT1 1N4148
BATTERY
VDD33V
VDD33V

VDDRTC
PWREN
R10
15K VDD1.25V VDD1.25V

M13
H14

N15

A16

A10

N16

U11
B11
P14

F16
J12

J17
G4

A6
A1

U2
U1
T8
T6

L2
F1

J2
U1C

VDD_adc(3.3V)

VDDA_MPLL(1.2V)
VDD_RTC(3.3V)

VDDalive(1.2V)
VDDalive(1.2V)

VDDiarm(1.2V)
VDDiarm(1.2V)
VDDiarm(1.2V)
VDDiarm(1.2V)
VDDiarm(1.2V)
VDDiarm(1.2V)
VDDiarm(1.2V)
VDDi(1.2V)
VDDi(1.2V)
VDDi(1.2V)
VDDi(1.2V)
VDDi(1.2V)
VDDi(1.2V)
VDDi(1.2V)

VDDA_UPLL(1.2V)
nBATT_FLT
PWREN
nRESET H16
nRESET
N13
nRSTOUT/GPA21
C EINT0 N17 VDD33V C
EINT0/GPF0
EINT1 M16 B6
EINT1/GPF1 VDDMOP(SCLK,100MHz:3.3V)
EINT2 L13 A9
EINT2/GPF2 VDDMOP(SCLK,100MHz:3.3V)
EINT3 M15 B12
EINT3/GPF3 VDDMOP(SCLK,100MHz:3.3V)
EINT4 M17 B14
EINT4/GPF4 VDDMOP(SCLK,100MHz:3.3V)
EINT5 L14 B16
EINT5/GPF5 VDDMOP(SCLK,100MHz:3.3V)
EINT6 L15 EXT INT F17
EINT6/GPF6 VDDMOP(SCLK,100MHz:3.3V)
IRQ_LAN L16 C1
EINT7/GPF7 VDDMOP(SCLK,100MHz:3.3V)
EINT8 N9
EINT8/GPG0
EINT9 T9
EINT9/GPG1
nCD_SD T10 K12
EINT16/GPG8 VDDOP()3.3V)
EINT17 M11 T12
EINT17/GPG9/nRST1 VDDOP()3.3V)
EINT18 N10 T3
EINT18/GPG10/nCTS1 VDDOP()3.3V)
J1
VDDOP()3.3V)
CAM_PCLK G5
CAMPCLK/GPJ8
CAM_VSYNC G7
CAMVSYNC/GPJ9
CAM_HREF G2 T14
CAMHREF/GPJ10 VSSA_ADC
CAMCLK J3 F2
CAMCLKOUT/GPJ11 VSSi
CAMRST J4 A3
CAMRESET/GPJ12 VSSi
CAMDATA0 H6 CAMERA IF A4
CAMDATA0/GPJ0 VSSi
CAMDATA1 G3 B10
CAMDATA1/GPJ1 VSSi
CAMDATA2 H5 A12
CAMDATA2/GPJ2 VSSi
CAMDATA3 H4 C17
CAMDATA3/GPJ3 VSSi
CAMDATA4 H3 G17
CAMDATA4/GPJ4 VSSi
B CAMDATA5 H7 B
CAMDATA5/GPJ5
CAMDATA6 J8 R17
CAMDATA6/GPJ6 VSSA_mPLL
CAMDATA7 H2 M12
CAMDATA7/GPJ7 VSSA_UPLL
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSiarm

VSSiarm
VSSiarm
VSSiarm
VSSiarm
VSSiarm
vssiarm

S3C2440X
U10

B1

D17
D16
A15

A11

U15

H11
H1
K1
T1
T2
U4
U7

E2

A7
A5
N1
U3
U9

G1
B13

VDD33V

C14 C15 C16 C17 C18 C19 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 CA10 CA11 CA12 CA13
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF

A A
VDD1.25V
Title

C20 C21 C22 C23 C24 C25 CA14 CA15 CA16 CA17 CA18 CA20 CA21 CA22 CA23
Size
友善之臂计算机科技有限公司
Number Revision
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
B
Date: 19-Jul-2009 Sheet of
File: D:\mini2440\原理图\mini2440 原理图.ddb Drawn By:
1 2 3 4 5 6
1 2 3 4 5 6

LADDR2 23 2 LDATA0 LADDR2 23 2 LDATA16


A0 DQ0 A0 DQ0
LADDR3 24 U6 4 LDATA1 LADDR3 24 U7 4 LDATA17
A1 DQ1 A1 DQ1
LADDR4 25 5 LDATA2 LADDR4 25 5 LDATA18
A2 DQ2 A2 DQ2
LADDR5 26 7 LDATA3 LADDR5 26 7 LDATA19
A3 DQ3 A3 DQ3
LADDR6 29 8 LDATA4 LADDR6 29 8 LDATA20
A4 DQ4 A4 DQ4
D LADDR7 30 10 LDATA5 LADDR7 30 10 LDATA21 VDD33V VDD33V D
A5 DQ5 A5 DQ5
LADDR8 31 11 LDATA6 LADDR8 31 11 LDATA22
A6 DQ6 A6 DQ6
LADDR9 32 13 LDATA7 LADDR9 32 13 LDATA23
A7 DQ7 A7 DQ7
LADDR10 33 42 LDATA8 LADDR10 33 42 LDATA24
A8 DQ8 A8 DQ8

4
3
2
1

4
3
2
1
LADDR11 34 44 LDATA9 LADDR11 34 44 LDATA25
A9 DQ9 A9 DQ9
LADDR12 22 45 LDATA10 LADDR12 22 45 LDATA26
A10 DQ10 A10 DQ10 RA8 RA9
LADDR13 35 47 LDATA11 LADDR13 35 47 LDATA27
A11 DQ11 A11 DQ11
LADDR14 36 48 LDATA12 LADDR14 36 48 LDATA28
A12 DQ12 A12 DQ12
50 LDATA13 50 LDATA29
DQ13 DQ13
LADDR24 20 51 LDATA14 LADDR24 20 51 LDATA30
BA0 DQ14 BA0 DQ14
LADDR25 21 53 LDATA15 LADDR25 21 53 LDATA31

5
6
7
8

5
6
7
8
BA1 DQ15 BA1 DQ15
LnWBE0 15 19 LnSCS0 LnWBE2 15 19 LnSCS0 VDD33V
LDQM nSCS LDQM nSCS
LnWBE1 39 18 LnSRAS LnWBE3 39 18 LnSRAS
UDQM nSRAS UDQM nSRAS
17 LnSCAS 17 LnSCAS
nSCAS nSCAS
LSCKE 37 16 LnWE LSCKE 37 16 LnWE
SCKE nWE SCKE nWE
LSCLK0 38 VDD33V LSCLK1 38 VDD33V CON7 SD/MMC CARD
SCLK SCLK
1 1
VDD0 VDD0
28 14 28 14 nCD_SD 11
VSS0 VDD1 VSS0 VDD1 nCD
41 27 41 27 WP_SD 10
VSS1 VDD2 VSS1 VDD2 WP
54 54
VSS2 VSS2
3 3 SDDATA1 8
VDDQ0 VDDQ0 DAT1
6 9 6 9 SDDATA0 7 15
VSSQ0 VDDQ1 VSSQ0 VDDQ1 DAT0 PAD4
12 43 12 43 6
C VSSQ1 VDDQ2 VSSQ1 VDDQ2 GND C
46 49 46 49 SDCLK 5 14
VSSQ2 VDDQ3 VSSQ2 VDDQ3 CLK PAD3
52 52 4
VSSQ3 VSSQ3 VDD
3 13
GND PAD2
SDCMD 2
CMD
HY57V561620(32MB)/或其他兼容型号 VDD33V SDDATA3 1 12
CD/DAT3 PAD1
HY57V561620 (32MB)/或其他兼容型号
SDDATA2 9
C27 C28 C29 DAT2
100nF 100nF 100nF
VDD33V

C30 C31 C32 C33


100nF 100nF 100nF 100nF
NOR FLASH
U10

LADDR1 25 29 LDATA0
A0 D0
LADDR2 24 31 LDATA1
A1 D1
LADDR3 23 33 LDATA2
A2 D2
LADDR4 22 35 LDATA3

NAND FLASH
A3 D3
LADDR5 21 38 LDATA4
A4 D4
LADDR6 20 40 LDATA5
A5 D5
VDD33V LADDR7 19 42 LDATA6
A6 D6
B U2 K9F1208 LADDR8 18 44 LDATA7
B
A7 D7
44 LDATA7 LADDR9 8 30 LDATA8
R6 I/O7 A8 D8
43 LDATA6 LADDR10 7 32 LDATA9
10K I/O6 A9 D9
42 LDATA5 LADDR11 6 34 LDATA10
I/O5 A10 D10
RnB 7 41 LDATA4 LADDR12 5 36 LDATA11
R/B I/O4 A11 D11
nFCE 9 32 LDATA3 LADDR13 4 39 LDATA12
CE I/O3 A12 D12
CLE 16 31 LDATA2 LADDR14 3 41 LDATA13
CLE I/O2 A13 D13
ALE 17 30 LDATA1 LADDR15 2 43 LDATA14
ALE I/O1 A14 D14
nFWE 18 29 LDATA0 LADDR16 1 45 LDATA15
WE I/O0 A15 D15
nFRE 8 LADDR17 48
RE A16
VDD33V LADDR18 17
A17
6 19 LADDR19 16 VDD33V
SE WP A18
13 12 LADDR20 9 37
VSS VCC A19 VDD
36 37 LADDR21 10
VSS VCC A20/NC
LADDR22 13
A21/NC
C10 28 LnOE
OE
0.1uF 11 LnWE VDD33V
WE
26 nGCS0
CE
VDD33V 15
NC R7
47
NC
NandFlash可兼容三星或现代64M/128M-1G各型号 /RST/NC
12 nRESET 10K
27 14
VSS /WP
46
VSS R69
A 10K 不焊 A
AM29LV160DB/SST39VF1601
Title

NOR Flash最大可兼容8M
Size
友善之臂计算机科技有限公司
Number Revision
B
Date: 19-Jul-2009 Sheet of
File: D:\mini2440\原理图\mini2440 原理图.ddb Drawn By:
1 2 3 4 5 6
1 2 3 4 5 6 7 8

R5
不焊
NETLINK2
D 0 D
R8
不焊
NETLINK3 NETLINK
0
R13
VDD33V 0

NETLINK1
NETACT
R82
4.7K

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD33V
U18

NC
NC

EEDO

SPEED#

MDIO
EECS
DVDD
DVDD

DGND

DGND

DVDD

TXD3
TXD2
TXD1
EECK

TX_EN
GPIO3
GPIO2
GPIO1
GPIO0

LINK_ACT#

CLK20MO
EEDI

MDC
DUP#
VDD33V
R16 1K
VDD33V 76 50 RD1
77
DGND TXD0
49 50 RD5 R39 1K
C NC TX_CLK 50 C
78 48 LAN
LINK_O TEST5
79 47 TX- 1
WACKUP RX_CLK TD+
nRESET 80 46 TX+ 2
PW_RST# RX_ER TD-
81 45 3
DGND RX_DV
C81 C79 LDATA15 82 44 4
SD15 COL GND
10uF 10uF C74 C36 LDATA14 83 43 RX- 5
SD14 CRS GND
0.1uF 0.1uF LDATA13 84 42 RX+ 6
SD13 DGND
LDATA12 85 41 7
SD12 RXD3 RD+
LDATA11 86 40 8
SD11 RXD2 RD-
LDATA10 87 39 9
SD10 RXD1 GLEDA
LDATA9 NETACT

1
88 DM9000 38 10
SD9 RXD0 GLEDk
GND VDD33V LDATA8 89 37 VDD33V C8 C35 11
SD8 LINK_I YLEDA
90 36 NETLINK 12
DVDD DVDD RD6 YLEDK
91 35 A
IO16 AVDD 0.1uF 0.1uF A
LADDR2 92 34 TX- 50 RD3 B

2
CMD TXO- 50 B
93 33 TX+ C
SA4 TXO+ C
94 32 CD1 D
SA5 AGND D
95 31
SA6 AGND
96 30 RX- HR911103A
SA7 RXI-
VDD33V 97 29 RX+ 0.1u
SA8 RXI+
98 28
SA9 AVDD
99 27
DGND AVDD
IRQ_LAN 100 26
INT BGRES
IOWAIT

X2_25M
X1_25M
TEST1
TEST2
TEST3
TEST4
DVDD

DGND

DVDD

DGND

AGND
IOW#
IOR#

AEN

RST
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7

SD
GND R83
6.8K %1
B B
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9

VDD33V

X6
LDATA0
LDATA1
LDATA2
LDATA3
LDATA4
LDATA5
LDATA6
LDATA7
nWAIT
LnWE
LnOE

25M
C77 C78
22p 22p
nLAN_CS

VDD33V
1 R76 2
4.7K

A A

Title

友善之臂计算机科技有限公司
Size Number Revision
A3
Date: 19-Jul-2009 Sheet of
File: D:\mini2440\原理图\mini2440 原理图.ddb Drawn By:
1 2 3 4 5 6 7 8
1 2 3 4 5 6

VDD5V

VDD33V C54 R27 15K USB-HOST


1 2
D R23 22 1 D

16
VBUS
0.1uF DN0 2 1 USB_D- 2
D-
U17 DP0 2 1 USB_D+ 3
D+
TXD0 11 14 RSTXD0 4

VDD
T1IN T1OUT GND
RXD0 12 13 RSRXD0 R24 22 R28 15K
ROUT1 RIN1 COM0
1 2
nRTS0 10 7 RSRTS0 BOXCONN_DB9 USB Port A type
T2IN T2OUT
nCTS0 9 8 RSCTS0
ROUT2 RIN2 1 USB(HOST)SOCKET
6
1 4
C1+ C2+ 2 RSTXD0
C55
7 RSCTS0
C58
3 RSRXD0
104 3 5 104
C1- C2- 8 RSRTS0 USB使能引脚,使用GPC5
4 USB_5V
9 R291.5K
USB_EN1 2
5
USB-DEVICE
VSS

2 6 1 R30470K 2
V+ V-
1
(male) R2522 VBUS
C56 MAX3232SOP C59 PDN0 1 2 2
R2622 D-
104 104 PDP0 1 2 3
15

D+
4
GND

C USB Port A type C


CON1 CON2 CON3
TXD0 TXD1 TXD2
1 1 1
RXD0
VDD5V
GND
2
3
RXD1
VDD5V
GND
2
3
RXD2
VDD5V
GND
2
3
串口电路
4 4 4
USB端口电路
CON4 CON4 CON4

1.8V电源产生电路(实测可能有偏差) 1.25V电源产生电路(实测可能有偏差)
U5
S1
VDD5V U14 VDD18V VDD33V MAX8860EUA18 VDD1.25V
CON5
1 3 2 1
Vin Vout IN OUT
4
1
2
3
4
5

GND

C11 OUT C13 C43


4
C37 C64 NC C65 10uF/10V 10uF/10V 104
CN1
104 10uF LM1117-1.8V 10uF C38
R31
复位电路
VDD5V 104
2

10
1
B VDDIN 8 B
2 /FAULT
3
开发板为5V供电输入 3.3V电源产生电路(实测可能有偏差) 7
VDD33V U9
DC_JACK /SHDN 4 1
4 1
VDD5V U4 VDD33V
CON8 1 3 C34
Vin Vout 6 5 R2

GND
VDDIN CC SET 104 3 2 nRESET
GND

1 3 2
GND 4 470
2 C9 NC C12 C39
GND C3 MAX811
3 10uF 10uF
VDD5V 100nF LM1117-33 C7 33nF/6.3V
4 R33 RST

3
100nF R32
2

100K
CON4
0 SW-PB
H1 H5
1 1 Power
VDD33V
CON1 CON1 R1
H2
H6 330
1 RED
1
CON1
H3 CON1
1
A A
CON1
H4
Title
1
CON1
固定孔
Size
友善之臂计算机科技有限公司
Number Revision
B
Date: 19-Jul-2009 Sheet of
1 2 3 4 5 File: D:\mini2440\原理图\mini2440 原理图.ddb Drawn By:6
1 2 3 4 5 6

J2
3 VDD5V
2
1 VDD33V
CON3
general int resist pulled up
D D
LCD CEMERA 10K 10K
CON5 RA1 VDD33V RA2 VDD33V
VDDLCD 1 I2CSDA
2 VDDLCD VDD5V GND 1 EINT0 1 8 EINT5 1 8
VD0 3 1 2 I2CSCL CON4
4 VD1 EINT17 EINT18 2 EINT1 2 7 EINT6 2 7
VD2 5 3 4 EINT20 VDD5V VDD33V
6 VD3 EINT3 EINT9 3 1 2 EINT2 3 6 CLKOUT0 3 6
VD4 7 5 6 CAMRST GND nRESET
8 VD5 nGCS1 nGCS2 4 3 4 EINT4 4 5 CLKOUT1 4 5
VD6 9 7 8 CAMCLK AIN0 AIN1
10 VD7 nGCS3 nGCS5 5 5 6
GND 11 9 10 CAM_HREF AIN2 AIN3
12 VD8 LnOE LnWE 6 7 8
VD9 13 11 12 CAM_VSYNC EINT0 EINT1
14 VD10 nWAIT nRESET 7 9 10
VD11 15 13 14 CAM_PCLK EINT2 EINT3 KBD resist pulled up spi resist pulled up
16 VD12 nXDACK0 nXDREQ0 8 11 12
VD13 17 15 16 CAMDATA7 EINT4 EINT5
18 VD14 LADDR0 LADDR1 9 13 14 RA3 10K VDD33V RA4 10K VDD33V
VD15 19 17 18 CAMDATA6 EINT6 EINT8
20 GND LADDR2 LADDR3 10 15 16 EINT11 1 8 SPICLK 1 8
VD16 21 19 20 CAMDATA5 EINT9 EINT11
22 VD17 LADDR4 LADDR5 11 17 18 EINT13 2 7 SPIMISO 2 7
VD18 23 21 22 CAMDATA4 EINT13 EINT14
24 VD19 LADDR6 LADDR24 12 19 20 EINT14 3 6 SPIMOSI 3 6
VD20 25 23 24 CAMDATA3 EINT15 EINT17
26 VD21 LDATA0 LDATA1 13 21 22 EINT15 4 5 nSS_SPI 4 5
VD22 27 25 26 CAMDATA2 EINT18 EINT19
28 VD23 LDATA2 LDATA3 14 23 24
GND 29 27 28 CAMDATA1 SPIMISO SPIMOSI
30 LCD_PWR LDATA4 LDATA5 15 25 26
GPB1 31 29 30 VDD33V CAMDATA0 SPICLK nSS_SPI RA5 10K VDD33V RA6 10K VDD33V
32 nRESET LDATA6 LDATA7 16 27 28
VM 33 31 32 D1 VDD33V I2CSCL I2CSDA 1 8 EINT3 1 8
34 VFRAME LDATA8 LDATA9 17 29 30
VLINE 35 33 34 VDD_CAM GPB0 GPB1 2 7 EINT9 2 7
36 VCLK LDATA10 LDATA11 18 31 32
TSXM 37 35 36 VDD18V CLKOUT0 CLKOUT1 I2CSCL 3 6 EINT17 3 6
38 TSXP LDATA12 LDATA13 19 33 34
TSYM 39 37 38 1N4148 GND I2CSDA 4 5 EINT18 4 5
40 TSYP LDATA14 LDATA15 20
GND 41 39 40 HEADER 18X2
CON20
HEADER 20X2
C LCD41P C
i2c resist pulled up system busl int resist pulled up

LCD接口 系统总线接口 CMOS摄像头接口 GPIO

JTAG 蜂鸣器 I2C总线:AT24C08 AD输入

VDD33V
B VDD5V B
R58

R59

R60

R61

VDD33V

2
SPEAKER

VDD33V W1

B
C
10K
JTAG
10K

10K

10K

10K

SPEAKER U8 AIN0 3
TAP
1 2 1K Q1 1 8
nTRST nRESET R57 A0 VDD

A
3 4 GPB0 R34 B 9014 2 7
TDI TDO A1 WP
5 6 1.5K 3 6 I2CSCL
TMS A2 SCL
7 8 4 5 I2CSDA

1
TCK GND SDA
9 10
24C08
E

HEADER 4X2

A A

Title

Size
友善之臂计算机科技有限公司
Number Revision
B
Date: 19-Jul-2009 Sheet of
File: D:\mini2440\原理图\mini2440 原理图.ddb Drawn By:
1 2 3 4 5 6
1 2 3 4 5 6

D D

音频输入与输出电路

C45 10uF/16V CON14


LINEOUT_L EARJACK
VDD33V VDD33V U12 UDA1341TS
10 26

ROUT1
ROUT2
LOUT1
LOUT2
DVDD VOUTL
AU_AVDD33V 24 LINEOUT_R

GND
VOUTR

1
3 10uF/16V
AVDD(ADC)
L4 C71 7 2 C46
+ Vpref(ADC) VINL1
10mH 25 4 VINR
C AVDD(DAC) VINR1 C

5
4

3
2

1
10uF/16V VINL 6 28 R4 R9
VINL2 Vref(ADC&DAC)
8 10K 10K LINEOUT_L

2
VINR2
23 LINEOUT_R
QMUTE
22 9
AGCSTAT OVERFL
OUTR
CDCLK 12 OUTL

麦克风
SYSCLK
I2SSCLK 16 21
BCK TEST2
I2SLRCK 17 20
WS TEST1
I2SSDI 18
C26 DATAO C47
MIC2 I2SSDO 19 1 CON10
DATAI AVSS(ADC)
MIC2_IN 5 R77 R78 R79 R80 MIC_IN MIC_IN
Vnref(ADC) 1
L3MODE 13 11 10K 10K 10K 10K GND
L3MODE DVSS 2
10uF/16V L3CLOCK 14 27 10uF/16V MIC_IN
MICROPHONE1 L3CLOCK AVSS(DAC) 3
R14 L3DATA 15 R3
L3DATA
4.7K 4.7K CON3

VDD33V VDD33V
R15 R11
100 C4 C44 100
10uF/16V 0.1uF
C48
C42
B B
10uF/16V 10uF/16V

A A

Title

Size
友善之臂计算机科技有限公司
Number Revision
B
Date: 19-Jul-2009 Sheet of
1 2 3 4 5 File: D:\mini2440\原理图\mini2440 原理图.ddb Drawn By:6