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AN920-D

AN920-D

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AN920/D Theory and Applications of the MC34063 and mA78S40 Switching Regulator Control Circuits

http://onsemi.com Prepared by: Jade Alberkrack ON Semiconductor

APPLICATION NOTE

This paper describes in detail the principle of operation of the MC34063 and μA78S40 switching regulator subsystems. Several converter design examples and numerous applications circuits with test data are included. INTRODUCTION The MC34063 and μA78S40 are monolithic switching regulator subsystems intended for use as dc to dc converters. These devices represent a significant advancement in the ease of implementing highly efficient and yet simple switching power supplies. The use of switching regulators is becoming more pronounced over that of linear regulators because the size reductions in new equipment designs require greater conversion efficiency. Another major advantage of the switching regulator is that it has increased application flexibility of output voltage. The output can be less than, greater than, or of opposite polarity to that of the input voltage. PRINCIPLE OF OPERATION In order to understand the difference in operation between linear and switching regulators we must compare the block diagrams of the two step−down regulators shown in Figure 1. The linear regulator consists of a stable reference, a high gain error amplifier, and a variable resistance series−pass element. The error amplifier monitors the output voltage level, compares it to the reference and generates a linear control signal that varies between two extremes, saturation and cutoff. This signal is used to vary the resistance of the series−pass element in a corrective fashion in order to maintain a constant output voltage under varying input voltage and output load conditions. The switching regulator consists of a stable reference and a high gain error amplifier identical to that of the linear regulator. This system differs in that a free running oscillator and a gated latch have been added. The error amplifier again monitors the output voltage, compares it to the reference level and generates a control signal. If the output voltage is below nominal, the control signal will go to a high state and turn on the gate, thus allowing the oscillator clock pulses to drive the series−pass element alternately from cutoff to saturation. This will continue until the output voltage is pumped up slightly above its nominal value. At this time, the control signal will go low and turn off the gate, terminating any further switching of the series−pass element. The output voltage will eventually decrease to below nominal due to the presence of an external load, and will initiate the switching process again. The increase in conversion efficiency is primarily due to the operation of the series−pass element only in the saturated or cutoff state. The voltage drop across the element, when saturated, is small as is the dissipation. When in cutoff, the current through the element and likewise the power dissipation are also small. There are other variations of switching control. The most common are the fixed frequency pulse width modulator and the fixed on−time variable off−time types, where the on−off switching is uninterrupted and regulation is achieved by duty cycle control. Generally speaking, the example given in Figure 1b does apply to MC34063 and μA78S40.
Vin Linear Control Signal Error Amp a. Linear Regulator Vin Error Amp + Vout + − Ref Voltage Vout

Gated Latch

Ref Voltage

− Digital Control Signal

OSC b. Switching Regulator

Figure 1. Step−Down Regulators

© Semiconductor Components Industries, LLC, 2006

1

May, 2006 − Rev. 5

Publication Order Number: AN920/D

AN920/D
GENERAL DESCRIPTION The MC34063 series is a monolithic control circuit containing all the active functions required for dc to dc converters. This device contains an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active peak current limit circuit, driver, and a high current output switch. This series was specifically designed to be incorporated in step−up, step−down and voltage−inverting converter applications. These functions are contained in an 8−pin dual in−line package shown in Figure 2a. The μA78S40 is identical to the MC34063 with the addition of an on−board power catch diode, and an uncommitted operational amplifier. This device is in a 16−pin dual in−line package which allows the reference and the noninverting input of the comparator to be pinned out. These additional features greatly enhance the flexibility of this part and allow the implementation of more sophisticated applications. These may include series−pass regulation of the main output or of a derived second output voltage, a tracking regulator configuration or even a second switching regulator. FUNCTIONAL DESCRIPTION The oscillator is composed of a current source and sink which charges and discharges the external timing capacitor CT between an upper and lower preset threshold. The typical charge and discharge currents are 35 μA and 200 μA respectively, yielding about a one to six ratio. Thus the ramp−up period is six times longer than that of the ramp−down as shown in Figure 3. The upper threshold is equal to the internal reference voltage of 1.25 V and the lower is approximately equal to 0.75 V. The oscillator runs continuously at a rate controlled by the selected value of CT. During the ramp−up portion of the cycle, a Logic “1” is present at the “A” input of the AND gate. If the output voltage of the switching regulator is below nominal, a Logic “1” will also be present at the “B” input. This condition will set the latch and cause the “Q” output to go to a Logic “1”, enabling the driver and output switch to conduct. When the oscillator reaches its upper threshold, CT will start to discharge and Logic “0” will be present at the “A” input of the AND gate. This logic level is also connected to an inverter whose output presents a Logic “1” to the reset input of the latch. This condition will cause “Q” to go low, disabling the driver and output switch. A logic truth table of these functional blocks is shown in Figure 4. The output of the comparator can set the latch only during the ramp−up of CT and can initiate a partial or full on−cycle of output switch conduction. Once the comparator has set the latch, it cannot reset it. The latch will remain set until CT begins ramping down. Thus the comparator can initiate output switch conduction, but cannot terminate it and the latch is always reset when CT begins ramping down. The comparator’s output will be at a Logic “0” when the output voltage of the switching regulator is above nominal. Under these conditions, the comparator’s output can inhibit a portion of the output switch on−cycle, a complete cycle, a complete cycle plus a portion of one cycle, multiple cycles, or multiple cycles plus a portion of one cycle.
Drive 8 Collector Switch Collector

B A

Latch S R 170 Q Q2 Q1

1

Ipk 7 Sense Ipk OSC VCC 6 + − Comparator Inverting 5 Input Comp CT

2

Switch Emitter

3 1.25 V Reference Regulator

Timing Capacitor

4 Ground a. MC34063

Noninverting Input

Timing Capacitor

Ipk Sense

Driver Collector 15 170 2 Diode Anode

9

10

11 GND CT OSC Comp Ipk

12

13

14

A B

Latch S R Q

8 Ref Output

7 Inverting Input

6 Noninverting Input

b. mA78S40

Figure 2. Functional Block Diagrams
V Upper Threshold 1.25 V Typical

Lower Threshold 0.75 V Typical t 6t Charge t Discharge

Figure 3. CT Voltage Waveform

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2

Diode Cathode

VCC Op Amp

Output

Switch Emitter

+

1.25 V Ref

Op Amp

D1 5 4 3 1

Switch Collector 16

Inverting Input

GND

VCC

− +

AN920/D
Active Condition of Timing Capacitor, CT Begins Ramp−Up Begins Ramp−Down Ramping Down 0 AND Gate Inputs A B 0 0 Latch Inputs S 0 0 0 1 R Output Switch 0 0 0

Comments on State of Output Switch Switching regulator’s output is ≥ nominal (‘B’ = 0). No change since ‘B’ was 0 before CT Ramp− Down. No change even though switching regulator’s output < nominal. Output switch cannot be initiated during RT Ramp−Down. No change since output switch conduction was terminated when ‘A’ went to 0. Switching regulator’s output went < nominal during CT Ramp−Up (‘B’ → 1). Partial on− cycle for output switch.

Ramping Down Ramping Up

0 1

0

1 0

0

Ramping Up

1

0

1

Switching regulator’s output went ≥ nominal (‘B’ → 0) during CT Ramp−Up. No change since ‘B’ cannot reset latch. Complete on−cycle since ‘B’ was 1 before CT started Ramp−Up. Output switch conduction is always terminated whenever CT is Ramping Down.

Begins Ramp−Up Begins Ramp−Down

1 1

Figure 4. Logic Truth Table of Functional Blocks

Current limiting is accomplished by monitoring the voltage drop across an external sense resistor placed in series with VCC and the output switch. The voltage drop developed across this resistor is monitored by the Ipk Sense pin. When this voltage becomes greater than 330 mV, the current limit circuitry provides an additional current path to charge the timing capacitor CT. This causes it to rapidly reach the upper oscillator threshold, thereby shortening the time of output switch conduction and thus reducing the amount of energy stored in the inductor. This can be observed as an increase in the slope of the charging portion of the CT voltage
1 Comparator Output 0

waveform as shown in Figure 5. Operation of the switching regulator in an overload or shorted condition will cause a very short but finite time of output conduction followed by either a normal or extended off−time internal provided by the oscillator ramp−down time of CT. The extended interval is the result of charging CT beyond the upper oscillator threshold by overdriving the current limit sense input. This can be caused by operating the switching regulator with a severely overloaded or shorted output or having the input voltage grossly above the nominal design value.

Timing Capacitor, CT

On Output Switch Off

Nominal Output Voltage Level Output Voltage Startup Quiescent Operation

Figure 5. Typical Operating Waveforms

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AN920/D
30 TA = 25°C Ichg, Charging Current (mA) 10 3.0 1.0 a. Step−Down Vout 3 Vin 0.3 L 0.1 0.03 0 Ichg = Idischg +Vin D1 0.2 0.4 0.6 0.8 VCLS, Current−Limit Sense Voltage (V) 1.0 MC34063 μA78S40 Q1
+

+Vin VCC = 40 V VCC = 5 V MC34063 μA78S40

Q1

L +Vout D1
+

Co

RL

+Vout

Co

RL

Figure 6. Timing Capacitor Charge Current versus Current−Limit Sense Voltage

b. Step−Up Vout . Vin +Vin Q1 D1 μA78S40 L
+

Under extreme conditions, the voltage across CT will approach VCC and can cause a relatively long off−time. This action may be considered a feature since it will reduce the power dissipation of the output switch considerably. This feature may be disabled on the μA78S40 only, by connecting a small signal PNP transistor as a clamp. The emitter is connected to CT, the base to the reference output, and the collector to ground. This will limit the maximum charge voltage across CT to less than 2.0 V. With the use of current limiting, saturation of the storage inductor may be prevented as well as achieving a soft startup. In practice the current limit circuit will somewhat modify the charging slope and peak amplitude of CT each time the output switch is required to conduct. This is because the threshold voltage of the current limit sense circuit exhibits a “soft” voltage turn−on characteristic and has a turn−off time delay that causes some overshoot. The 330 mV threshold is defined where the charge and discharge currents are of equal value with VCC = 5.0 V, as shown in Figure 6. The current limit sense circuit can be disabled by connecting the Ipk Sense pin to VCC. To aid in system design flexibility, the driver collector, output switch collector and emitter are pinned out separately. This allows the designer the option of driving the output switch transistor into saturation with a selected forced gain or driving it near saturation when connected as a Darlington. The output switch has a typical current gain of 70 at 1.0 A and is designed to switch a maximum of 40 V collector−to−emitter, with up to 1.5 A peak collector current. The μA78S40 has the additional features of an on−chip uncommitted operational amplifier and catch diode. The op amp is a high gain single supply type with an input common−mode voltage range that includes ground. The output is capable of sourcing up to 150 mA and sinking 35 mA. A separate VCC pin is provided in order to reduce the integrated circuit standby current and is useful in low power applications if the operational amplifier is not incorporated into the main switching system. The catch diode is constructed from a lateral PNP transistor and is capable of blocking up to 40 V and will conduct current up to 1.5 A. There is, however, a “catch” when using it.

−Vout

Co

RL

c. Voltage−Inverting |Vout| 3 . Vin

Figure 7. Basic Switching Regulator Configurations

Because the integrated circuit substrate is common with the internal and external circuitry ground, the cathode of the diode cannot be operated much below ground or forward biasing of the substrate will result. This totally eliminates the diode from being used in the basic voltage inverting configuration as in Figure 15, since the substrate, pin 11, is common to ground. The diode can be considered for use only in low power converter applications where the total system component count must be held to a minimum. The substrate current will be about 10 percent of the catch diode current in the step−up configuration and about 20 percent in the step−down and voltage−inverting in which pin 11 is common to the negative output. System efficiency will suffer when using this diode and the package dissipation limits must be observed. STEP−DOWN SWITCHING REGULATOR OPERATION Shown in Figure 7a is the basic step−down switching regulator. Transistor Q1 interrupts the input voltage and provides a variable duty cycle squarewave to a simple LC filter. The filter averages the squarewaves producing a dc output voltage that can be set to any level less than the input by controlling the percent conduction time of Q1 to that of the total switching cycle time. Thus,
ton Vout + Vin % ton or Vout + Vin ton ) toff

The MC34063/μA78S40 achieves regulation by varying the on−time and the total switching cycle time. An explanation of the step−down converter operation is as follows: Assume that the transistor Q1 is off, the inductor current IL is zero, and the output voltage Vout is at its nominal

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4

The on−time. The known quantities are the voltage across the inductor and the required peak current for the selected switch conduction time. the calculated value will need to be increased due to the internal equivalent series resistance ESR of the capacitor. Q+ = Q−. The ripple voltage can be calculated from the known values of on−time.5 mV and the minimum achievable ripple at the output will be the feedback divider ratio multiplied by 1. and the current at any instant is: IL + IL(pk) * Vout ) VF t L A minimum value of inductance can now be calculated for L. maximum output current. and the peak current will decay at a rate of ΔI/ΔT = V/L as energy is supplied to Co and RL. This voltage difference to completely change the latch states is about 1. peak inductor current. The additional ripple voltage will be equal to Ipk(ESR). and a minimum charge−current oscillator. The cycle time of the LC network is equal to ton(max) + toff and the minimum operating frequency is: fmin + 1 ton(max) ) toff At the end of the on−time. The off−time is not related to the ramp−down time of CT. Increasing the value of the filter capacitor will reduce the output ripple voltage. Co in parallel with RL. ton. The voltage across the inductor is equal to Vin − Vsat − Vout and the peak current at any instant is: IL + Vin * Vsat * Vout t L The off−time. is the maximum possible switch conduction time. Vripple(p−p) + 1 Co t1 i t dt ) 0 1 I t 2 pk 1 Co t2 i t dt t1 where i t + 1 I t 2 pk ton 2 and i t + toff 2 Note that the volt−time product of ton must be equal to that of toff and the inductance value is not of concern when determining their ratio. must be zero. The required value for CT can be determined by using the minimum oscillator charging current and the typical value for the oscillator voltage swing both taken from the data sheet electrical characteristics table.0 10− 6 ton 0. off−time. Q1 is turned off. This voltage deficiency is monitored by the switching control circuit and causes it to drive Q1 into saturation. CT + Ichg(min) Dt DV + 20 + 4. and output capacitor value. toff. The output voltage across capacitor Co will eventually decay below nominal because it is the only component supply current into the external load RL.com 5 .5 A graphical derivation of the peak−to−peak ripple voltage can be obtained from the capacitor current and voltage waveforms in Figure 8. The inductor current will start to flow from Vin through Q1 and. a point of diminishing return will be reached because the comparator requires a finite voltage difference across its inputs to control the latch. The voltage across the inductor during this period is equal to Vout + VF of D1.5 mV or: V Vripple(p−p)min + out (1. the average current into the inductor must be equal to the output current for a complete cycle.5 Vref 10− 3) 10− 5 ton http://onsemi. is the time that diode D1 is in conduction and it is determined by the time required for the inductor current to return to zero.AN920/D value. If the output voltage is to remain constant. Then IL(peak) attained during ton must decay to zero during toff and a ratio of ton to toff can be determined. and rise at a rate of ΔI/ΔT = V/L. Vin * Vsat * Vout V ) VF ton + out toff L L Vout ) VF t N on + Vin * Vsat * Vout toff This minimum value of inductance was calculated by assuming the onset of continuous conduction operation with a fixed input voltage. However. it generates a reverse voltage that forward biases D1. In practice. As the magnetic field in the inductor starts to collapse. It is equal to the time required for CT to ramp up from its lower to upper threshold. V * Vsat * Vout Lmin + in ton Ipk(switch) Assume that during quiescent operation the average output voltage is constant and that the system is operating in the discontinuous mode. The peak inductor current with respect to output current is: IL(pk) IL(pk) ton ) toff + (Iout ton) ) (Iout toff) 2 2 IL(pk)(ton ) toff) + Iout (ton ) toff) 2 NIL(pk) + 2 Iout Ipk t2 t1 Ipk t2 t2 + 1 ) 1 ton 2 0 Co Co toff 2 t1 ton and toff And t1 + t2 * t1 + 2 2 Substituting for t1 and t2 − t1 yields: + 1 Co + Ipk (ton 2)2 ) 1 ton 2 Co Ipk (toff 2)2 2 toff Ipk (ton ) toff) 8 Co The peak inductor current is also equal to the peak switch current Ipk(switch) since the two are in series. The net charge per cycle delivered to the output filter capacitor Co. The calculations shown account for the ripple voltage contributed by the ripple current into an ideal capacitor. if the output voltage is to remain constant.

8 * 5. By using substitution and some algebraic gymnastics.com 6 .5% Vout or 25 mVp−p ÌÌÌ ÌÌÏ Ì Ï ÌÌÌÌÌÌÌÌ ÏÏ ÌÌÌÌ Q+ 1/2 Ipk/2 ton/2 Vripple(p−p) t0 t1 t2 +Ipk/2 1.0 ) 0. The cycle time of the LC network is equal to ton(max) + toff. the MC34063 with an external catch diode can also be used. ton(max) ) toff + 1 fmin + 1 50 103 + 20 ms per cycle 3.0 toff/2 Q− + 0. however. There will be a further discussion of this and other design considerations later. Determine the ratio of switch conduction ton versus diode conduction toff time. Next calculate ton and toff from the ratio of ton/toff in #1 and the sum of ton + toff in #2.6 V Vripple(p−p) = 0. http://onsemi. Figures 12 and 13 show two different ripple reduction techniques. an equation can be written for toff in terms of ton/toff and ton + toff.0 V Iout = 50 mA fmin = 50 kHz Vin(min) = 24 V − 10% or 21. Vout ) VF ton + Vin(min) * Vsat * Vout toff + 5. The μA78S40 was chosen in order to implement a minimum component system. The second technique uses a Zener diode to level shift the output down to the reference voltage. The first uses the μA78S40 operational amplifier to drive the comparator in the feedback loop.8 21.AN920/D Voltage Across Switch Q1 VCE Vin + VF Vin Vsat 0 Vin Vin − Vsat 0 VF Ipk Iin = IC(AVG) 0 Diode D1 Current Ipk ID(AVG) 0 Inductor Current Ipk Iout = Ipk/2 = IC(AVG) + ID(AVG) 0 Capacitor Co Current Voltage Across Diode D1 VKA Switch Q1 Current 0 −Ipk/2 Capacitor Co Ripple Voltage Vout + Vpk Vout Vout − Vpk Figure 8. The frequency chosen is a compromise between switching losses and inductor size.6 * 0. Step−Down Switching Regulator Waveforms This problem becomes more apparent in a step−up converter with a high output voltage.37 2. Step−Down Switching Regulator Design Example A schematic of the basic step−down regulator is shown in Figure 9. Given are the following: Vout = 5.

Iout = 50 mA Vin = 24 V. CT + 4.857. External Diode* Vin = 18 to 30 V.6 V.3% 72. RL = 0. ton(max). Iout = 50 mA Vin = 24 V.6 ms + 5. Iout = 25 to 50 mA Vin = 21.com 7 . The maximum on−time.25 V Ref + * L Co 27 + Vout 5 V/50 mA Conditions Results Δ = 16 mV or ± 0. is set by selecting a value for CT.6 ms Since ton(max) ) toff + 20 ms ton(max) + 20 ms * 14.AN920/D The equation is: toff + + ton(max) ) toff ton toff )1 20 10− 6 0.37 ) 1 Note that the ratio of ton/(ton + toff) does not exceed the maximum of 6/7 or 0.4 ms Vin = 24 V + 216 pF Use a standard 220 pF capacitor. This maximum is defined by the 6:1 ratio of charge−to−discharge current of timing capacitor CT (refer to Figure 3).0 + 4.4 10− 6) + 14. Step−Down Design Example − + 1. 4.0 10− 5 ton 10− 5 (5. Iout = 50 mA Figure 9.16% Δ = 28 mV or ± 0.7 8 7 6 Test Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency. Internal Diode Efficiency.1 Ω Vin = 24 V.28% 24 mVp−p 105 mA 45. Iout = 50 mA Vin = 24 V.6% http://onsemi. + 47 R2 36 k R1 12 k CT 220 pF 9 10 11 GND CT OSC Comp Op Amp − Ipk S R 170 D1 5 4 3 2 1N5819 853 μH 1 Q 12 13 VCC 14 15 16 Rsc 2.

R2 resistor divider.8 * 5. even a solid tantalum capacitor of this value will have a typical ESR (equivalent series resistance) of 0. In satisfying the example shown.3 Ω which will contribute 30 mV of ripple. An explanation of the step−up converter’s operation is as follows. A minimum value for an ideal output filter capacitor can now be obtained. At this time.33 pk(switch) 0. Initially. This configuration allows the output voltage to be set to any value greater than that of the input by the following relationship: t t Vout + Vin on ) Vin or Vout + Vin on ) 1 toff toff 115 + 2.33 10− 3 Using the above derivation. Energy is stored in the inductor during the time that transistor Q1 is in the “on” state.4 100 10− 3 + 853 mH 10− 6 The divider current can go as low as 100 μA without affecting system performance. The ripple components are not in phase. driving Q1 into saturation. The ripple voltage should be kept to a low value since it will directly affect the system line and load regulation. In selecting a minimum current divider R1 is equal to: R1 + 100 1.e. I pk(switch) + Vin * Vsat * Vout ton(max) Lmin 10− 6 If a standard 5% tolerance 12 k resistor is chosen for R1.1 Ω was selected. The inductor current will decay at a rate of ΔI/ΔT = V/L and the voltage across it is equal to Vout + VF − Vin. 24 V. but can be assumed to be for a conservative design. The output voltage is: Vout + 1. the current limit will activate slightly above the rated Iout of 50 mA. A value for the current limit resistor. The current at any instant is: http://onsemi.5 A when using the internal switch transistor.AN920/D 5.8 * 5.7 W This value may have to be adjusted downward to compensate for conversion losses and any increase in Ipk(switch) current if Vin varies upward. a 27 μF tantalum with an ESR of 0. a minimum value of inductance can be calculated.86 W. Co + + Ipk(switch) (ton ) toff) 8 Vripple(p−p) 0. Current will start to flow from Vin through the inductor and Q1 and rise at a rate of ΔI/ΔT = V/L. the design is optimized to meet the assumed conditions.0 5. The nominal output voltage is programmed by the R1. 500 W Rearranging the above equation so that R2 can be solved yields: R2 + R1 Vout *1 1. the inductor current is zero. Q1 will turn off and the magnetic field in the inductor will start to collapse generating a reverse voltage that forward biases D1.25 + 24 * 0. This deficiency will be sensed by the control circuit and it will initiate an on−cycle. STEP−UP SWITCHING REGULATOR OPERATION The basic step−up switching regulator is shown in Figure 7b and the waveform is in Figure 10. 8. With knowledge of the peak switch current and maximum on time. the energy is transferred in series with Vin to the output filter capacitor and load. Rsc. R2 will also be a standard value.25 R2 ) 1 R1 6.0 * 1 1. Vin(min) * Vsat * Vout Lmin + ton(max) Ipk(switch) + 21.25 10− 6 + 12. can be determined by using the current level of Ipk(switch) when Vin = 24 V. however. use 2. load current is being supplied only by Co and it will eventually fall below nominal. Upon turn−off. At Vin(nom) i.4 853 10− 6 + 115 mA Rsc + I + 0. supplying energy to Co and RL. Do not set Rsc to exceed the maximum Ipk(switch) limit of 1. The peak switch current is: Ipk(switch) + 2 Iout + 2 (50 + 100 mA 10− 3) 9.1 (20 8 (25 10− 6) 10− 3) + 10 mF Ideally this would satisfy the design goal.6 * 0.25 7. and the output voltage is at its nominal value. At Vin(min). The voltage across the inductor is equal to Vin − Vsat and the peak current is: IL + Vin * Vsat t L When the on−time is completed.com 8 . R2 + 12 + 36 k 103 5. operation is at the onset of continuous mode and the output current capability will be greater than 50 mA.0 5.. assume that transistor Q1 is off.

AN920/D Voltage Across Switch Q1 VCE Vout + VF Vin Vsat 0 Vout − Vsat Diode D1 Voltage VKA 0 VF Switch Q1 Current Ipk 0 Diode D1 Current Ipk Iout 0 Inductor Current Ipk Iin = IL(AVG) 0 Capacitor Co Current 1/2(Ipk − Iout) 0 −Iout Capacitor Co Ripple Voltage Vout + Vpk Vout Vout − Vpk Figure 10. a minimum inductance value can be determined. If the output voltage is to remain constant.com 9 Ñ ÌÌÌÌÏÏÏÏÏÑ ÌÌ ÑÑ ÌÌ ÌÌ Q+ Q− toff t1 ton Vripple(p−p) Ipk − Iout Figure 10 shows the step−up switching regulator waveforms. since the two are in series. that the volt−time product of ton must be equal to that of toff and the inductance value does not affect this relationship. Vin * Vsat V ) VF * Vin ton + out toff L L V ) VF * Vin t N on + out Vin * Vsat toff Note again. peak inductor current. With knowledge of the voltage across the inductor during ton and the required peak current for the selected switch conduction time. output current and output capacitor value. By observing the capacitor current and making some substitutions in the above statement. Ichg toff + Idischg ton http://onsemi. Step−Up Switching Regulator Waveforms IL + IL(pk) * Vout ) VF * Vin t L Assuming that the system is operating in the discontinuous mode. IL(pk) toff + Iout (ton ) toff) 2 t IL(pk) + 2 Iout on ) 1 toff The peak inductor current is also equal to the peak switch current. Lmin + Vin * Vsat t Ipk(switch) on(max) The ripple voltage can be calculated from the known values of on−time. Referring to the . the net charge per cycle delivered to the output filter capacitor must be zero. The inductor current charges the output filter capacitor through diode D1 only during toff. a formula for peak inductor current can be obtained. Then IL(pk) attained during ton must decay to zero during toff and a ratio of ton to toff can be written. off−time. the current through the inductor will reach zero after the toff period is completed. Q+ = Q−.

5 ms Substituting for t1 yields: (Ipk * Iout) (Ipk * Iout) + 1 toff 2 Ipk Co (Ipk * Iout)2 toff + 2 Ipk Co Note that the ratio of ton/(ton + toff) does not exceed the maximum of 0.3 15.5 442 10− 3 10− 6 + 226 mH http://onsemi. Solving for t1 in known terms yields: Ipk * Iout Ipk + t1 toff Ipk * Iout Nt1 + toff Ipk Vout ) VF * Vin(min) ton + Vin(min) * Vsat toff + 28 ) 0.5 ms + 15.5 ms ton + 20 ms * 4. ton(max) ) toff + 1 fmin + 1 50 103 And the current during t1 can be written: Ipk * Iout I+ t t1 The ripple voltage is: Vripple(p−p) + 1 Co t1 0 Ipk * Iout t dt t1 + 20 ms per cycle 3.AN920/D capacitor current waveforms in Figure 10. The cycle time of the LC network is equal to ton(max) + toff. The μA78S40 again was chosen in order to implement a minimum component system.75 V Vripple(p−p) = 0. is set by selecting a value for CT.42 ) 1 Ipk * Iout t2 t1 + 1 2 0 t1 Co (Ipk * Iout) + 1 t1 2 Co + 4. ton(max). Lmin + + Vin(min) * Vsat ton Ipk(switch) 6.0 + 4. The peak switch current is: Ipk(switch) + 2 Iout + 2 (50 + 442 mA ton )1 toff 10− 3) (3. A minimum value of inductance can be calculated since the maximum on−time and peak switch current are known. Next calculate ton and toff from the ratio of ton/toff in #1 and the sum of ton + toff in #2.42 2.75 6.5% Vout or 140 mVp−p 1. t1 is defined as the capacitor charging interval. 6. The area neglected is equal to: I A + (toff * t1) out 2 Step−Up Switching Regulator Design Example The basic step−up regulator schematic is shown in Figure 11.3 + 3.8 * 6.857. The maximum on−time. CT + 4.0 V − 25% or 6.75 * 0. 4.0 10− 5 ton 10− 5 (15. The following conditions are given: Vout = 28 V Iout = 50 mA fmin = 50 kHz Vin(min) = 9. Determine the ratio of switch conduction ton versus diode conduction toff time. toff + 20 10− 6 3.42 ) 1) This neglects a small portion of the total Q− area.5 10− 6) A simplified formula that will give an error of less than 5% for a voltage step−up greater than 3 with an ideal capacitor is shown: Vripple(p−p) [ Iout t Co on + 620 pF 5.com 10 .75 * 0.

2 mV due to ESR.5 10− 3 10− 6 50 140 [ 5. or Rsc may be destroyed since they form a direct path from Vin to Vout. Rsc.33 Rsc + I pk(switch) + 0.0 V.3 15.AN920/D 7. can now be determined by using the current level of Ipk(switch) when Vin = 9.com 11 .7 mV and 44.0 * 0. V * Vsat I pk(switch) + in ton(max) Lmin + 9. 8.5 226 10− 6 10− 6 Co [ V [ Iout ton ripple(p−p) 10− 3 15.5 Vref + 107 mV I 10− 3 ) out ton ) Ipk ESR Co + 33.10 Ω was again chosen.2 mV http://onsemi.5 mF + 597 mA 0. This yields a total ripple voltage of: V Eripple(p−p) + out 1.7 mV ) 44. Protection may be achieved by current limiting Vin or replacing the inductor with 1:1 turns ratio transformer.6 mV ) 28. The ripple voltage due to the capacitance value is 28. D1. If the output is severely overloaded or shorted.33 597 10− 3 The ripple contribution due to the gain of the comparator: V Vripple(p−p) + out 1.55 W.25 + 33.5 Vref + 28 1. A value for the current limit resistor.5 W Note that current limiting in this basic step−up configuration will only protect the switch transistor from overcurrent due to inductor saturation. L. use 0.6 mV 10− 3 10− 3 + 0.5 1. An approximate value for an ideal output filter capacitor is: A 27 μF tantalum capacitor with an ESR of 0.

5 240 226 μH 15 16 8 7 6 Test Line Regulation Load Regulation Output Ripple Efficiency.AN920/D Vin = 9 V + 47 R2 47 k R1 2. External Diode* Vin = 6. Iout = 50 mA Vin = 9.21% Δ = 50 mV or ± 0.09% 90 mVp−p 62.0 V.2 k CT 620 pF 9 10 11 GND CT OSC Comp Op Amp − Ipk S R Q 12 13 VCC 14 Rsc 0.75 V.com 12 − + 5 1.25 V Ref + 170 D1 4 3 2 1N5819 1 * Co 27 + Vout 5 V/50 mA Conditions Results Δ = 120 mV or ± 0. Iout = 25 to 50 mA Vin = 6.0 V.2% .0 to 12 V. Iout = 50 mA Vin = 9. Iout = 50 mA Vin = 9. Step−Up Design Example http://onsemi. Internal Diode Efficiency.2% 74.0 V. Iout = 50 mA Figure 11.

1 mA .2 k resistor was selected for R1 so that the divider current is about 500 μA. Vout + 1. The nominal output voltage is programmed by the R1. use 47 k 10.25 V Reference Regulator CT Q Q2 Q1 1 2 D1 3 CT 4 Vout R1 VZ = Vout − 1.25 1 ) R2 R1 A standard 5% tolerance. 2. The required base drive is: IB + + Ipk(switch) Bf 442 10− 3 20 The current required to drive the internal 170 Ω base−emitter resistor is: + 22.com 13 − + 1.25 + 2200 + 47. 080 W.25 V + Co Figure 13.2 k Then R2 + R1 Vout *1 1. R2 divider. MC34063 Ripple Reduction Technique http://onsemi.25 10− 6 + 2500 W. the output switch transistor is driven into saturation with a forced gain of 20 at an input voltage of 7.25 28 * 1 1. use 2. R1 + 500 1.25 V Ref + R2 Vout R1 + Co 9. In this design example.AN920/D Vin L Rsc CT 9 10 11 GND CT OSC Comp Op Amp − Ipk S R 170 D1 5 4 3 2 1 Q 12 13 VCC 14 15 16 8 7 6 Figure 12.0 V. mA78S40 Ripple Reduction Technique L 8 S R 7 Rsc Vin 6 Ipk OSC VCC + − Comp 5 GND 1.

1) 10− 3 Energy is stored in the inductor during the conduction time of Q1. Voltage Across Switch Q1 VCE Vin Vsat 0 Vin − (−Vout + VF) (Vin − Vsat) + Vout Diode D1 Voltage VKA 0 VF Switch Q1 Current Ipk Iin = IC(AVG) 0 Diode D1 Current Ipk Iout 0 Inductor Current Ipk 0 Capacitor Co Current Ipk − Iout 1/2(Ipk − Iout) 0 −Iout Capacitor Co Ripple Voltage −Vout + Vpk Vout −Vout − Vpk Figure 14. equal to. a ratio of ton to toff can be determined. or greater than that of the input and is set by the following relationship: t Vout + Vin on toff The voltage−inverting converter operates almost identically to that of the step−up previously discussed.2 V for the drop across Rsc (0. Voltage−Inverting Switching Regulator Waveforms http://onsemi.7 170 + 4. the energy is transferred to the output filter capacitor and load. Upon turn−off.1 mA The driver collector current is equal to sum of 22.2 mA. (Vin * Vsat) ton + (|Vout| ) VF) toff |Vout| ) VF t N on + toff Vin * Vsat + 248 W. use 240 W VOLTAGE−INVERTING SWITCHING REGULATOR OPERATION The basic voltage−inverting switching regulator is shown in Figure 7c and the operating waveforms are in Figure 14. Lmin. Then the driver collector resistor is equal to: Rdriver + + Vin * Vsat(driver) * VRSC IB ) I170 W 7.3 V for driver saturation and 0.1 mA + 4. Allow 0.0 * 0. This allows the magnitude of the output to be set to any value. It may be less than.1 mA = 26.1 ) 4.3 * 0.com 14 ÌÌÌÌ Ï ÌÌÌÌÌÌÏÏÑ Ì Ï Ï ÌÌÌÏÏÏÑÑ ÌÌÌ ÑÑÑ Q+ Q− toff t1 ton Vripple(p−p) . Remember that the volt−time product of ton must be equal to that of toff.AN920/D I170 W + VBE(switch) 170 + 0. The voltage across the inductor during ton is Vin − Vsat but during toff the voltage is equal to the negative magnitude of Vout + VF. Notice that in this configuration the output voltage is derived only from the inductor. and Co are the same as that of the step−up converter.5 × 442 mA Ipk). The derivations and the formulas for Ipk(switch).2 (22.

5 A Results Δ = 3.5 A Vin = 15 V.24 ) 1 + 8.1 Ω Vin = 15 V. toff + 20 10− 6 1.09% 35 mVp−p 2.5 μH Co 470 Co 470 Vout −15 V/0.5 V Vripple(p−p) = 0. The following operating conditions are given: Vout = −15 V Iout = 500 mA fmin = 50 kHz Vin(min) = 15 V − 10% or 13.01% Δ = 27 mV or ± 0.8 + 1.0 mV or ± 0.9 ms ton + 20 ms * 8. The μA78S40 was selected for this design since it has the reference and both comparator inputs pinned out. |Vout| ) VF ton + Vin * Vsat toff + 15 ) 0.6% Figure 15. Determine the ratio of switch conduction ton versus diode conductions toff time.5 * 0. Calculate ton and toff from the ratio of ton/toff in #1 and the sum of ton + toff in #2. Voltage−Inverting Design Example http://onsemi.5 V.5 A .9 ms + 11. RL = 0. ton(max) ) toff + 1 fmin + 50 1 10− 3 + 20 ms 3.5 A 80.5 A Vin = 13. Iout = 0.4% Vout or 60 mVp−p 1. Iout = 0.AN920/D Voltage−Inverting Switching Regulator Design Example A circuit diagram of the basic voltage−inverting regulator is shown in Figure 15.25 V Ref + D1 1N5822 4 3 2 1 L 66.857.0 k 15 8 7 6 * Heatsink.12 CT 430 pF 9 10 11 GND CT OSC Comp Op Amp − Ipk S R 170 Q 12 13 VCC 14 RBE 160 Q2 MPS U51A * RB 160 16 R1 3. Iout = 0. Iout = 0.24 Vin = 15 V 2.1 ms Note again that the ratio of ton/(ton + toff) does not exceed the maximum of 0.com 15 + + − + 5 1. + R2 36 k 100 Rsc 0. IERC PSC2−3CB Test Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Conditions Vin = 12 to 16 V.8 13.5 A Vin = 15 V.1 to 0. The cycle time of the LC network is equal to ton(max) + toff.

3 mV I 10− 3 ) out ton ) Ipk ESR Co + 444 pF.8 11. The nominal output voltage is programmed by the R1.24 A 10− 3) (1.020 Ω each was chosen.5 * 0. I pk(switch) + + Vin * Vsat ton Lmin 16.5 1.24 + 156. The current−limit resistor value was selected by determining the level of Ipk(switch) for Vin = 16. use 3.25 + 18 mV 10− 3 10− 3 10 (35) 2. Therefore two 470 μF http://onsemi. This yields a total ripple voltage of: |Vout| Eripple(p−p) + 1.5 mF The ripple contribution due to the gain of the comparator is: |Vout| Vripple(p−p) + 1.25 10− 3 + 2. R2 and the noninverting input must also be at ground potential when Vout is in regulation.9 mV ) 22.4 mV 6.5 V in order to enhance the turn−off switching time. the voltage at the junction of R1.5 mH A divider current of about 400 μA was desired for this example.5 11.25 10− 6 7.0 k Then R2 + |Vout| R1 1.0 mA .25 R2 R1 + 13.1 10− 6) capacitors with an ESR of 0. The magnitude of Vout is: |Vout| + 1.com 16 + 0.4 mV due to ESR.24 + 66. CT + 4.24 ) 1) + 18 mV ) 5. the ESR of the output filter capacitor becomes the dominant factor in choosing a value for capacitance.5 * 0. Note that with a negative output voltage.8 160 + 5.5 V. An approximate value for an ideal output filter capacitor is: Iout Co [ t Vripple(p−p) on [ 60 0.24 35 + 64 mA The value for the base−emitter turn−off resistor RBE is determined by: RBE + I + 10 Bf pk(switch) [ 92.9 mV and 22.62 A 0. Therefore. The required base drive is: IB + Ipk(switch) Bf 8.5 10− 6 10− 6 + 3. Output switch transistor Q2 is driven into a soft saturation with a forced gain of 35 at an input voltage of 13.1 66. R2 divider.12 W + 15 3. R1 + 400 1.3 W.33 2. use 430 pF 5.1 10− 3 10− 6 + 2.13 W. use 160 W The additional base current required due to RBE is: IRBE + VBE (Q2) RBE For a given level of ripple.5 Vref + 15 1.33 Rsc + I pk(switch) + 0.62 + 0.8 11. The ripple voltage due to the capacitance value is 5.125 W.0 1.1 2.AN920/D 4. use 0. A value of CT must be selected in order to set ton(max).5 Vref + 46.0 10− 5 ton 10− 5 (11.0 + 4. the inverting input of the comparator is referenced to ground. The peak switch current is: t Ipk(switch) + 2 Iout on ) 1 toff + 2 (500 + 2. The minimum required inductance value is: Lmin + Vin(min) * Vsat ton Ipk(switch) 10− 6 9.25 + 36 k 10.

5 * 0. Vin Figure 16. L or D2 may be destroyed since they form a direct path from Vin to Vout. The cycle time of the LC network is equal to ton(max) + toff. Energy is stored in the inductor during the time that transistors Q1 and Q2 are in the “on” state.9 2. its terminal voltage will eventually fall below the desired output. Then the base driver resistor is equal to: RB + Vin(min) * Vsat(IC) * VRSC * VBE(Q2) IB ) I160 W +Vin Q1 L + +Vout D1 Co + 13. 3.6 ) 0.5 * 0.9 ms ton + 20 ms * 6. Determine the ratio of switch conduction ton versus diode conduction toff time. Next calculate ton and toff from the ratio of ton/toff in #1 and the sum of ton(max) + toff in #2. equal to.9 ) 1 + 6. Upon turn−off. This allows the output voltage to be set to any value.5 V Vout = 10 V fmin = 50 kHz Iout = 120 mA Vripple(p−p) = 1% Vout or 100 mVp−p The following design procedure is provided so that the user can select proper component values for his specific converter application. toff + + ton(max) ) toff ton toff )1 20 10− 6 1. However. Current limit protection cannot be employed in the basic step−up circuit.0 (64 ) 5) 10− 3 + 165. and in order to utilize the remaining battery energy the step−up circuit shown in Figure 16b will be required.5 to 14. Basic Switching Regulator Configurations +Vin Q1 L Q2 D2 + +Vout By combining circuits a and b.3 * 1. the energy is transferred to the output filter capacitor and load forward biasing diodes D1 and D2.6 7. Step−Down Vout 3 Vin +Vin L Q2 +Vout D2 + STEP UP/DOWN SWITCHING REGULATOR OPERATION When designing at the board level it sometimes becomes necessary to generate a constant output voltage that is less than that of the battery. or greater than that of the input.com 17 . This regulator was designed to operate from a standard 12 V battery pack with the following conditions: Vin = 7. Vout ) VFD1 ) VFD2 ton + Vin(min) * VsatQ1 * VsatQ2 toff + 10 ) 0. thus it may be less than.9 ms + 13. ton(max) ) toff + 1 fmin 1 50 103 + 20 ms per cycle + A complete step−up/down switching regulator design example is shown in Figure 18. The step−down circuit shown in Figure 16a will perform this function efficiently. If the output is severely overloaded or shorted.0 mA = 69 mA. The step−up/down configuration allows the control circuit to implement current limiting because Q1 is now in series with Vout. as is in the step−down circuit.8 + 1.3 V for the drop across Rsc (0. Step−Up/Down Switching Regulator Design Example D1 Co b. Allow 0. General Applications Co b.12 × 2.8 V for the IC driver saturation and 0.24 A Ipk). Step−Up/Down Vout 3 . Vin Figure 17.1 ms http://onsemi.8 * 0. as the battery discharges. a unique step−up/down configuration can be created (Figure 17) which still employs a simple inductor for the voltage transformation. Step−Up Vout . but during toff the output voltage is derived only from the inductor and is with respect to ground instead of Vin. use 160 W a. Note that during ton this circuit is identical to the basic step−up.AN920/D Then IB (Q2) is equal to the sum of 64 mA + 5. Combined Configuration 1.2 W.8 * 0.

The maximum on−time is set by selecting a value for CT.8 * 0.5 V 6 + + 14.5 to 14.8 13.25 V Reference Regulator MC34063 R2 GND 4 2 CT 3 CT 510 pF 100 5 R1 1.015% 95 mVp−p 1. RL = 0. CT + 4.0 + 4.6 V.1 696 10− 3 + 111 mH Use a standard 510 pF capacitor. 7.5 * 0. A minimum value of inductance can now be calculated since the maximum on−time and peak switch current are known. I pk(switch) + Vin * VsatQ1 * VsatQ2 ton(max) Lmin 10− 6 6.AN920/D 4.com 18 .11% Δ = 3.0 10− 5 ton(max) 10− 5 (13.8 13.5 * 0. 5.5 V.22 Vin 7.0 mV or ± 0.41 A D2 1N5818 Vout 10 V/120 mA 120 μH D1 1N5818 Co 330 + 1 Q Q2 170 Ipk OSC VCC + − Comp 1. can be determined by using the current limit level of Ipk(switch) when Vin = 14.1 10− 6) Lmin + Vin(min) * VsatQ1 * VsatQ2 ton Ipk(switch) 10− 6 + 524 pF + 7.1 Ω Vin = 7.6 V.54 A 74% Figure 18. Iout = 10 to 120 mA Vin = 12.5 to 14. Iout = 120 mA Vin = 12.8 * 0. Iout = 120 mA Vin = 12.9 ) 1) A 120 μH inductor was selected for Lmin.1 k Test Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Conditions Vin = 7. Q1 MPSU51A RBE 300 RB 150 8 S R 7 Rsc 0.3 k 9. Rsc.6 V.5 V.5 to 14. The peak switch current is: t Ipk(switch) + 2 Iout on ) 1 toff + 2 (120 + 696 mA 10− 3) (1.5 V. Step−Up/Down Switching Regulator Design Example http://onsemi.1 120 10− 6 + 1. Iout = 120 mA Results Δ = 22 mV or ± 0. A value for the current limit resistor.

8 300 + 3.25 + 7 R1 If 1. When checking the initial switcher operation with an oscilloscope. maximum output load current. however.AN920/D Rsc + I 0.5 10− 3 Ipk(switch) 9. From the above it becomes apparent that ESR is the dominant factor in the selection of an output filter capacitor. The circuit performance data shows excellent line and load regulation.5 Vref + 10 1.com 19 . However.0 mA 10 (20) 696 10− 3 + 287 W [ 15.33 pk(switch) The value for the base−emitter turn−off resistor RBE is determined by: RBE + I + 10 Bf pk(switch) + 0. thus ton will be somewhat shorter and the actual LC operating frequency will be greater than predicted. the design equations for Lmin were based upon the assumption that the switching regulator is operating on the onset of continuous conduction with a fixed input voltage. Also note that the voltage drop developed across the current−limit resistor Rsc was not accounted for in the ton/toff and Lmin design formulas. DESIGN CONSIDERATIONS As previously stated.33 1. there will be some concern of circuit instability due to the apparent random switching of the output.15 * 0. Typically the oscillator charge−current will be greater than the specific minimum of 20 microamps. but can be assumed to be for a conservative design. It is a normal operating characteristic of this type of switching regulator and is caused by the asynchronous operation of the comparator to that of the oscillator.41 + 0. There is some loss in conversion efficiency over the basic step−up or step−down circuits due to the added switch transistor and diode “on” losses. R2 + R1 + R1 Vout *1 VRef 10 * 1 1.22 Ω resistor.5 1.8 (35 ) 3) 10− 3 + 151 W + 12 mV The ripple components are not in phase. A 330 μF with an ESR of 0. The additional base current required due to RBE is: V IRBE + BEQ1 RBE + 0. and a minimum charge−current oscillator.7 mF Ideally this would satisfy the design goal. This voltage drop must be considered when designing high current converters that operate with an input voltage of less than 5. The nominal output voltage is programmed by the R1.5 * 0. The required base drive is: IB + Ipk(switch) Bf 696 10− 3 + 20 + 35 mA http://onsemi.12 Ω was selected to satisfy this design example by the following: ESR [ Vripple(p−p) * Iout Co A standard 150 Ω resistor was used.3 Ω which will contribute an additional 209 mV of ripple.8 * 0. even a solid tantalum capacitor of this value will have a typical ESR (equivalent series resistance) of 0. ton * Vout VRef 1. R2 resistor divider. this unique converter demonstrates that with a simple inductor. 10. 8. This is not a problem. The oscilloscope will be difficult to synchronize.25 10− 3 10− 3 The base drive resistor for Q1 is equal to: RB + Vin(min) * Vsat(driver) * VRSC * VBEQ1 IB ) IRBE + 7.1 k. A minimum value for an ideal output filter capacitor is: Iout Co [ t Vripple(p−p) on [ 120 100 10− 3 13. both being standard resistor values. The oscilloscope may be synchronized by varying the input voltage or load current slightly from the design nominals. Transistor Q1 is driven into saturation with a forced gain of approximately 20 at an input voltage of 7.0 V. then R2 would be 9. Also there is a ripple component due to the gain of the comparator equal to: V Vripple(p−p) + out 1.5 V.3 k is chosen for R1. a step−up/down converter with current limiting can be constructed.1 10− 3 10− 6 A standard 300 Ω resistor was selected.23 W Use a standard 0.

R2 output voltage divider should be located as close to the IC as possible to eliminate any noise pick−up into the feedback loop. When the output filter capacitor reaches its nominal voltage. The number of turns. A negative temperature coefficient timing capacitor will help reduce this sensitivity. Oscillator Timing Capacitor (nF) 100 toff 100 0 Figure 20. a ratio of ton/(ton + toff) greater than 0.857 may be required. Output Switch On−Off Time (μs) 1000 Comparator Noninverting Input = Vref Comparator Inverting Input = GND VCC = 5 V. Vin = 5 V 8 S R 7 Ipk OSC 6 + 1 ton Q toff 170 To Scope 2 100 1N270 VCC + 1. wire and core size information is not given since no attempt was made to optimize their design. Current limiting must be used on all step−up and voltage−inverting designs using the ratio extender circuit.AN920/D High frequency circuit layout techniques are imperative with switching regulators.com 20 . With the circuit.0 10 CT. The circuit diagrams were purposely drawn in a manner to depict this. Ipk(sense) = VCC TA = 25°C ton ton 10 toff Without Ratio Extender Circuit With Ratio Extender Circuit 0 1. mainly step−up and voltage−inverting. Figure 20 shows the output switch on and off time versus CT with and without the ratio extender circuit. Notice that without the circuit. The R1. This can be obtained by the addition of the ratio extender circuit shown in Figure 19. All circuits used molypermalloy power toroid cores for the magnetics where only the inductance value is given. the ratio of ton/(ton + toff) is limited to 0. To minimize EMI. The low current signal and high current switch and output grounds should return on separate paths back to the input filter capacitor. the ratio is variable depending upon the value chosen for CT since toff is now nearly a constant.0 nF. Output Switch On−Off Time Test Circuit ton−toff. Output Switch On−Off Time versus Oscillator Timing Capacitor http://onsemi.25 V Reference Regulator 4 3 CT 2N524 ton toff Ratio Extender Circuit CT 10 Comp 5 − Figure 19. the voltage feedback loop will control regulation. This will allow the inductor time to reset between cycles of overcurrent during initial power up of the switcher.857 only for values of CT greater than 2. Inductor and transformer design information may be obtained from the magnetic core and assembly companies listed on the switching regulator component source table. all high current loops should be kept as short as possible using heavy copper runs. This circuit uses germanium components and is temperature sensitive. In some circuit designs.

5 12 28/50 36/225 190/5.0 334/45 9.0/250 − − − − − − −12/50 − 11 26 27 28 29 30 31 32 Low Power with Minimum Components Medium Power Buffered Switch and Second Output Linear Pass from Main Output Buffered Switch and Buffered Linear Pass from Main Output Negative Input and Negative Output 24 36 28 33 28 −28 5/50 12/750 5.5 10/120 − − 18 Voltage−Inverting MC34063 μA78S40 μA78S40 μA78S40 μA78S40 Low Power Medium Power with Buffered Switch High Voltage. Low Power High Voltage.0/5000 24/500 15/3000 −12/500 − − 12/300 15/50 12/1000 − − − − − − − 9 21 22 23 24 25 Input V Output 1 V/mA Output 2 V/mA Output 3 V/mA Figure No.5 4.5 to 14. High Power with Buffered Switch 42 Watt Off−Line Flyback Switcher Tracking Regulator with Buffered Switch and Buffered Linear Pass from Input 5. and a performance table is included.5 2. Each of these circuits was constructed and tested.0 12 4. They are categorized into three INDEX OF CONVERTER CIRCUITS Main Output Configuration Step−Down μA78S40 MC34063 MC34063 μA78S40 μA78S40 μA78S40 Step−Up μA78S40 MC34063 MC34063 μA78S40 μA78S40 μA78S40 μA78S40 μA78S40 Low Power with Minimum Components Medium Power High Voltage. major groups based upon the main output configuration.5 4.0/4000 −12/500 − − − 12/700 12/500 − − − −12/700 − 33 15 34 35 37 http://onsemi. Step−Up/Down MC34063 Medium Power Step−Up/Down 7.5 4.0/100 See Circuit 15/1000 28/250 − − − − 6/30 − 12/500 5.com 21 .AN920/D APPLICATIONS SECTION Listed below is an index of all the converter circuits shown in this application note.0 15 28 115 Vac 15 −12/100 −15/500 −120/850 5. Medium Power Photoflash Linear Pass from Main Output Buffered Linear Pass from Main Output EE PROM Programmer Buffered Switch and Buffered Linear Pass from Main Output Dual Switcher. Step−Up and Step−Down with Buffered Switch 9.

RL = 0. Iout = 750 mA Vin = 36 V. Iout = 100 to 750 mA Vin = 36 V. Iout = 750 mA Vin = 36 V.25 V Reference Regulator GND 2 1N5819 CT 3 470 pF 190 μH 5 4 15 k 1. Figure 21.AN920/D 8 S R 7 0.6 A 89.1 Ω Vin = 36 V. Iout = 750 mA Results Δ = 15 mV or ± 0.0 watts is possible from an 8−pin dual−in−line package with Vin = 36 V and Vout = 12 V.063% Δ = 40 mV or ± 0.5% A maximum power transfer of 9. Step−Down http://onsemi.17% 60 mVp−p 1.2 Vin 36 V 47 6 + 1 Q 170 Ipk OSC VCC + − Comp 1.74 k 270 + Vout 12 V/750 mA Test Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Conditions Vin = 20 to 40 V.com 22 .

com 23 .0 A.0 A.25 V Reference Regulator GND 330 pF 5 4 3.0 to 5.1 Ω Vin = 20 to 30 V. Iout2 = 100 to 300 mA.0 A Vin = 28 V.09% Δ = 20 mV or ± 0. The second output power should not exceed 25% of the main output.0 A. Iout2 = 300 mA Vout2 12 V/300 m A Results Δ = 9.036 100 Ipk OSC Vin 28 V 2200 6 + 1 Q T 1. Figure 22. Iout1 = 5.0 A. Iout2 = 300 mA Vin = 28 V. RL = 0.AN920/D D45VH4 (1) MBR2540 (2) 22 51 8 S R 0. IERC HP3−T0127−CB (2) Heatsink. Iout1 = 5.000 3 1N5819 VCC + − Comp 1.0 mV or ± 0.3% Δ = 12 mV or ± 0. The 100 Ω potentiometer is used to divide down the voltage across the 0.1 μH + 7 CT 22. Iout1 = 5. Iout2 = 300 mA Vin = 28 V. Step−Down with Buffered Switch and Second Output http://onsemi. RL = 0.4T 170 2 23.2% 60 mVp−p 11.036 Ω resistor and thus fine tune the current limit. Iout1 = 1. Iout2 = 300 mA Vin = 28 V. Iout2 = 300 mA Vin = 28 V.05% 25 mVp−p 11.0 A. IERC UP−000−CB Test Line Regulation Load Regulation Output Ripple Short Circuit Current Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Vout1 Vout1 Vout1 Vout1 Vout2 Vout2 Vout2 Vout2 Conditions Vin = 20 to 30 V.25 A 80% A second output can be easily derived by winding a secondary on the main output inductor and phasing it so that energy is delivered to Vout2 during toff.1 Ω Vin = 28 V. Iout2 = 300 mA Vin = 20 V. Iout1 = 5.2 k + 470 Vout1 5 V/5 A (1) Heatsink.0 A.6 k 1.4 A Δ = 72 mV or ± 0. Iout1 = 5. Iout1 = 5.

Iout1 = 100 to 500 mA.22 750 pF 9 10 11 GND CT OSC Comp Op Amp − Ipk S R 170 D1 5 4 3 2 1 Vout2 15 V/50 mA 22 k 130 μH 0.AN920/D Vin = 33 V + 33 18.2% http://onsemi.2 k 1. Iout1 = 500 mA. Iout1 = 500 mA.15% 80 mVp−p 2. Iout1 = 500 mA.0 k 0. Iout2 = 50 mA Vin = 33 V. Step−Down with Linear Pass from Main Output − + 1.com 24 .63% Δ = 70 mV or ± 0. Iout2 = 50 mA Vin = 33 V. Iout2 = 50 mA Vin = 33 V.1 Vout1 24 V/500 mA Q 12 13 VCC 14 15 16 8 7 6 1.5 A Δ = 20 mV or ± 0. Iout2 = 0 to 50 mA.2% 70 mVp−p 90 mA 88. Iout2 = 50 mA Figure 23. Iout2 = 50 mA Vin = 33 V.1 Ω Vin = 33 V. RL = 0. Iout2 = 50 mA Vin = 33 V.067% Δ = 60 mV or ± 0. Iout1 = 500 mA.1 Ω Vin = 30 to 36 V.25 V Ref + 1N5819 2. Iout1 = 500 mA. RL = 0.0 k 100 + Conditions Results Δ = 30 mV or ± 0. Iout1 = 500 mA Vin = 33 V.8 k Test Line Regulation Load Regulation Output Ripple Short Circuit Current Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Vout1 Vout1 Vout1 Vout1 Vout2 Vout2 Vout2 Vout2 Vin = 30 to 36 V.

Iout2 = 1. Iout1 = 3.0 mV or ± 0. Iout1 = 3.0 A.0 A.1 Ω Vin = 28 to 36 V.0 A Results Δ = 13 mV or ± 0. Iout1 = 3. Iout1 = 1. IERC HP3−T0127−4CB Conditions Vin = 28 to 36 V. RL = 0. Iout2 = 0 to 1.043% Δ = 21 mV or ± 0. Iout2 = 1.0 mA.0 A Vin = 36 V. Iout1 = 3.0 A Vin = 36 V.25 V Ref + * Vout2 12 V/1.022 + D45VH10 35 μH Vout1 15 V/3. Step−Down with Buffered Switch and Buffered Linear Pass from Main Output − + 1. Iout2 = 1. Iout2 = 1. RL = 0.0 mA MBR1540 * 2200 + * 100 470 22 k 2.6 A Δ = 2.6 A 78.0 to 4.com 25 .1 Test Line Regulation Load Regulation Output Ripple Short Circuit Current Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Vout1 Vout1 Vout1 Vout1 Vout2 Vout2 Vout2 Vout2 Figure 24.AN920/D Vin = 28 to 36 V 0.0 mA 8.0 A Vin = 36 V. Iout1 = 3. extra #10 hole required for MBR2540.0 A.5% http://onsemi.0 A Vin = 36 V.0 mV or ± 0.07% 120 mVp−p 12.0 A Vin = 36 V.5 A Vin = 36 V. Iout2 = 1.1 Ω Vin = 36 V.0 A. Iout2 = 1.0 k 51 910 pF 9 10 11 GND CT OSC Comp Op Amp − Ipk S R 170 D1 5 4 3 2 1 Q 12 13 VCC 14 15 16 8 7 6 820 TIP31 0.08% 25 mVp−p 3.008% Δ = 2.2 k 963 *All devices mounted on one heatsink.0 A.

causing the internal 1.5 V with respect to ground is generated by the Op Amp. the output switch must be connected in series with the negative input. Note that the 10 k and 20 k resistors must be matched pairs for good line regulation and that no provision is made for output short−circuit protection.5 V Test Line Regulation Load Regulation Output Ripple Efficiency In this step−down circuit. Figure 25.25 V Ref + Conditions Vin = −22 to −28 V.8 k 3.com 26 . Step−Down with Negative Input and Negative Output − + 1. Iout = 500 mA Vin = −28 V.104% Δ = 10 mV or ± 0.25 V reference to be with respect to −Vin. Iout = 500 mA Results Δ = 25 mV or ± 0. A second reference of −2. Iout = 100 to 500 mA Vin = −28 V.5% http://onsemi.AN920/D Vin = −28 V 11.09 k + 100 275 μH Vout −12 V/500 mA 1N5819 16 + 470 820 pF 9 10 11 GND CT OSC Comp Op Amp − Ipk S R 170 D1 5 20 k 4 3 2 1 Q 12 13 VCC 14 15 470 8 10 k 7 6 470 20 k 10 k −2.042% 130 mVp−p 85. Iout = 500 mA Vin = −28 V.

25 V 1N5819 8 S R 7 0. The high efficiency is partially due to the use of the tapped inductor. Step−Up http://onsemi.75T T 1.042% 100 mVp−p 90.028% Δ = 30 mV or ± 0.1 watts is possible with Vin = 12 V and Vout = 36 V.4% A maximum power transfer of 8.22 Vin 12 V 470 Comp 5 GND 4 6 Ipk OSC VCC + − 1.AN920/D 180 μH 7.7 k Test Line Regulation Load Regulation Output Ripple Efficiency Conditions Vin = 11 to 15 V. Iout = 225 mA Vin = 12 V. The tap point is set for a voltage differential of 1. Figure 26. Iout = 225 mA Results Δ = 20 mV or ± 0.25 V Reference Regulator CT 3 910 pF 170 2 Q 1 + Vout 36 V/225 mA 100 75 k 2. The range of Vin is somewhat limited when using this method.com 27 .25 V. Iout = 225 mA Vin = 12 V. Iout = 50 to 225 mA Vin = 12 V.

0 mA Vin = 5. The 24 V level is the maximum step−up allowed by the oscillator ratio of ton/(ton + toff).5 V and a 24 V output rated at 45 mA.37% 250 mVp−p 113 mA 68% This circuit was designed to power the ON Semiconductor Solid Ceramic Displays from a Vin of 4.0 V.0 mA Results Δ = 2.0 to 6.7 M 27 k 10 k T1: Primary = 25 Turns #28 AWG Secondary = 260 Turns #40 AWG Core = Ferroxcube 1408P−L00−3CB Bobbin = Ferroxcube 1408PCB1 Gap = 0.com 28 . Test Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Conditions Vin = 4.0 mA To SCD 504 Display 8 S R 7 0.5 to 12 V.0 V.61% Δ = 1.0 Vout 190 V/5.4 V or ± 0. Low Power Step−Up for Solid Ceramic Display http://onsemi. RL = 0.24 Vin 4. High−Voltage. Iout = 5. Iout = 5. The design calculations are based on a step−up converter with an input of 4.25 V Reference Regulator 2 CT 3 680 pF 4 4.0 mA Vin = 5.0 V. Iout = 5. The 45 mA current level was chosen so that the transformer primary power level is about 10% greater than that required by the load.1 Ω Vin = 5. Iout = 1.5 to12 V 100 Comp 5 GND 6 + 1 Q 170 Ipk OSC VCC + − 1.0 mA Vin = 5.5 to 12 V. Figure 27. The maximum Vin of 12 V is determined by the sum of the flyback and leakage inductance voltages present at the collector of the output switch during turn−off must not exceed 40 V.0 V.3 V or ± 0.003″ Spacer for a primary inductance of 140 μH.AN920/D T1 Lp = 140 μH 1N4936 + 1.

this step−up converter will charge capacitor C1 from 0 to 334 V in 4.1 1600 pF MR817 9 10 11 GND CT OSC Comp Op Amp − Ipk S R 170 D1 5 4 3 2 1 Q 10 0.0 V 0.5 to 6. Figure 28. IERC PB1−36CB http://onsemi.0 seconds.5 μH.8 M 120 4.7 seconds.022 + D45VH10 * T1 27 Lp = 16. The switching operation will cease until C1 bleeds down to 323 V. 18 k With Vin of 6.com 29 .AN920/D Vin = 4.018″ Spacer for a Primary Inductance of 16. The charging time between flashes is 4.0 V. High−Voltage Step−Up with Buffered Switch for Photoflash Applications − + 1. FT−118 Shutter TRAID PL−10 12 13 VCC 14 15 16 22 M C1 500 + 8 7 6 18 k 1.033 G.E.25 V Ref + * Heatsink. The output current at 334 V is 45 mA.7 M Charging Indicator LED T1: Primary = 10 Turns #17 AWG Secondary = 130 Turns #30 AWG Core = Ferroxcube 2616P−L00−3C8 Bobbin = Ferroxcube 2616PCB1 Gap = 0.5 μH 2200 5.

0 V. Iout2 = 30 mA Vin = 2.0 V/30 mA 38.1 10 k Conditions Results Δ = 20 mV or ± 0.0 mV or ± 0. Iout1 = 100 mA. Iout2 = 30 mA Vin = 2. Iout1 = 100 mA. Iout2 = 30 mA Figure 29.5 V. Iout2 = 30 mA Vin = 2. Iout1 = 25 to 100 mA. Iout2 = 30 mA Vin = 2.5 V + 470 62 k 10 k 0.5 to 3.0 mVp−p 150 mA 68.5 V. Step−Up with Linear Pass from Main Output − + 5 1. Iout2 = 30 mA Vin = 2.3 k 0.com 30 .5 to 3.0083% 5.5 V. Iout1 = 100 mA. RL = 0.2 k Test Line Regulation Load Regulation Output Ripple Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Vout1 Vout1 Vout1 Vout2 Vout2 Vout2 Vout2 Vin = 2.1 Ω Vin = 3.5 V.AN920/D Vin = 2.25 V Ref + 170 D1 4 3 2 1 Vout2 6. Iout1 = 100 mA Vin = 2. Iout2 = 0 to 50 mA.22 40 μH 1N5819 Vout1 9.0083% Δ = 1.0 V/100 mA + 910 pF 9 10 11 GND CT OSC Comp Op Amp − Ipk S R Q 12 13 VCC 14 15 27 16 330 8 7 6 8.5 V. Iout1 = 100 mA.5 V.11% Δ = 20 mV or ± 0.5 V.11% 60 mVp−p Δ = 1.3% http://onsemi.0 mV or ± 0. Iout1 = 100 mA.

5 V ‘A’ 16.95 5. Co.25 < 1. A step−up converter provides a selectable regulated voltage at Pins 1 and 5. This voltage is used to generate a second reference at point ‘X’ and to power the linear regulator consisting of the internal op amp and a TIP29 transistor.22 294 k ‘B’ 13.5 k 0.5 to 5.com 31 − + 1.245 V.AN920/D Vin = 4.2 k Voltage @ Pins 1 & 5 23.5 > 2.5 > 2. the μA78S40 can generate the required VPP voltage of 21 V or 25 V needed to program and erase EEPROMs from a single 5.058 WRITE TTL Input 47 k 3.07 28.28 6. The linear regulator amplifies the voltage at ‘X’ by four.4 k Switch Position A A B B NOTE: WRITE < 1.0 V supply. When the WRITE input is less than 1. When the WRITE input is greater than 2.25 1. Vref = 1.25 All values are in volts.6 k 4.5 V. the 2N5089 turns ON clamping point ‘X’ to the internal reference level of 1.52 28.01 5.1 V or 4. The μA78AS40 reference can only source current. The VPP output is short−circuit protected and can supply a current of 100 mA at 21 V or 75 mA at 25 V over an input range of 4.0 + 470 ‘X’ 16. generating the required VPP output voltage for the byte−erase write cycle. .07 X 5. Used in conjunction with two transistors.52 23. the 2N5089 transistor is OFF.0 (1.28 VPP 20. The VPP output will not be at approximately 5.12 25.5 V. Figure 30.7 k TIP29 470 VPP Output 10.25 V Ref + 1. therefore a reference pre bias of 470 Ω is used.5 k + 47 0.24 1.7 k 70 μH 68 820 pF 9 10 11 GND CT OSC Comp Op Amp − Ipk S R 170 D1 5 4 3 2 1 Q 12 13 VCC 14 15 16 8 7 6 2N5089 1.12 Contributed by Steve Hageman of Calex Mfg.0 k + 57.245 V. Step−Up with Buffered Linear Pass from Main Output for Programming EEPROMs http://onsemi. allowing the voltage at ‘X’ to rise exponentially with an approximate time constant of 600 μs as required by some EEPROMs.5 to 5.245 + Vsat 2N5089).25 V. Inc.

0 mV or ± 0.0 V.0 k 0.083% 75 mVp−p Δ = 3.5 to 5.0 V Vin = 4.25 V Ref + 47 4 3 2 1 1N5818 MC79L12 ACP 47 0. Iout1 = 0.5 V Conditions Vin = 5.0 V Vin = 5.5 to 5. Iout3 = 0 to 50 mA Vin = 5.5 to 5.5 V Vin = 5.0 V.0 V All outputs are at nominal load current unless otherwise noted.0 mV or ± 0. IERC LAT0127B5CB (2) Heatsink. IERC PB1−36CB 953 Test Line Regulation Load Regulation Output Ripple Line Regulation Load Regulation Output Ripple Short Circuit Current Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency NOTE: Vout1 Vout1 Vout1 Vout2 Vout2 Vout2 Vout2 Vout3 Vout3 Vout3 Vout3 Vin = 4.0 V Vin = 5.5 V + 6800 22 k 2. Step−Up with Buffered Switch and Buffered Linear Pass from Main Output http://onsemi.12% 15 mVp−p 130 mA 71.8% .25 to 1.1 Vout3 −12 V/50 mA 1N5818 47 + Results Δ = 18 mV or ± 0.06% Δ = 25 mV or ± 0.022 8.0 V.021% 20 mVp−p 2. Iout2 = 100 to 500 mA Vin = 5.1 1200 pF 9 10 11 GND CT OSC Comp Op Amp − Ipk S R 170 D1 Q 12 13 VCC 14 15 16 2N5824 2200 + Vout1 15 V/1.2 k (1) Heatsink.8 μH 5.1 Ω Vin = 5. RL = 0.0 V. RL = 0.013% Δ = 5.0 V. Figure 31.0 mV or ± 0.0 A Vin = 5.com 32 + − + 5 1.7 A Δ = 2.0 mA + 8 7 820 6 27 D44 VH1 (1) TIP29 (2) 0.1 Ω Vin = 4.008% Δ = 29 mV or ± 0.5 V Vin = 5.5 to 5.AN920/D Vin = 4.1 Vout2 −12 V/50 mA 8.

Iout2 = 250 mA Results Δ = 30 mV or ± 0. Iout1 = 250 mA.25 V Ref + MPSU51A 4.0 kHz.0 V/250 mA Conditions Vin = 9.18% 70 mVp−p 81. Iout2 = 250 mA Vin = 12 V. Iout2 = 100 to 300 mA.04% Δ = 18 mV or ± 0. Iout1 = 100 to 300 mA. Output 1 uses the typical step−up circuit configuration while Output 2 makes the use of the op amp connected with positive feedback to create a free running step−down converter. Dual Switcher.4 mH + 2200 Vout2 5. RL = 0. Iout1 = 250 mA.com 33 .1 1.054% Δ = 20 mV or ± 0. The op amp slew rate limits the maximum switching frequency at rated load to less than 2. Iout1 = 250 mA.7 A Δ = 4.0 to 15 V.AN920/D Vin = 12 V + 47 47 k 0. Iout2 = 250 mA Vin = 12 V.1 Ω Vin = 9. Iout1 = 250 mA.2 k 470 pF 9 10 11 GND CT OSC Comp Op Amp − Ipk S R 170 D1 5 4 3 2 1 10 k Q 12 13 VCC 14 15 180 16 1N5819 470 + 108 μH Vout1 28 V/250 mA 8 7 6 100 0. Iout2 = 250 mA Vin = 12 V.8% http://onsemi.24 2.0 mV or ± 0.036% 35 mVp−p 1.0 to 15 V. Iout2 = 250 mA Vin = 12 V. Step−Up and Step−Down with Buffered Switch − + 1. Iout1 = 250 A Vin = 12 V.0 M 470 1N5819 3. Iout2 = 250 mA Vin = 12 V. Iout1 = 250 mA.2 k Test Line Regulation Load Regulation Output Ripple Short Circuit Current Line Regulation Load Regulation Output Ripple Efficiency Vout1 Vout1 Vout1 Vout1 Vout2 Vout2 Vout2 This circuit shows a method of using the μA78S40 to construct two independent converters.6 k 1. Figure 32.

RL = 0. thus allowing the internally connected comparator and reference to function properly for output voltage control.0 mV or ± 0. Iout = 100 mA Vin = 5.0 V 100 6 + 1 Q 170 Ipk OSC VCC + − Comp 1.008% Δ = 10 mV or ± 0. A 12% improvement can be realized with the addition of an external PNP saturated switch when connected in a similar manner to that shown in Figure 15.5 to 5. Iout = 10 to 100 mA Vin = 5.0 V.24 Vin 4. With this configuration.AN920/D 8 S R 7 0. the sum of Vin + Vout + VF must not exceed 40 V.5 to 6.0 V.com 34 .4 A 60% The above circuit shows a method of using the MC34063 to construct a low power voltage−inverting converter. Note that the integrated circuit ground.25 1 ) R2 R1 1000 + Vout −12 V/100 mA Test Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Conditions Vin = 4.0 V. Iout = 100 mA Vin = 5. pin 4. The conversion efficiency is modest since the output switch is connected as a Darlington and its on−voltage is a large portion of the minimum operating input voltage. Figure 33.042% 35 mVp−p 1.1 Ω Vin = 5.25 V Reference Regulator GND 2 88 μH CT 3 + 1300 pF 4 1N5819 5 R2 8. Low Power Voltage−Inverting http://onsemi. is connected directly to the negative output.0 V.0 V. Iout = 100 mA Results Δ = 2.2 k R1 953 |Vout| + 1.

If an http://onsemi.042% Δ = 70 mV or ± 0. In this circuit the μA78S40 is connected to operate as a fixed frequency pulse width modulator. The 1000 pF capacitor is used to filter the spikes generated by the high switching current flowing through the wiring and Rsc inductance. The oscillator sawtooth waveform is connected to the noninverting input of the comparator and a preset voltage of 685 mV. Figure 34. As the output loading is increased.1 Ω Vin = 28 V. This in turn will cause the optoreceiver transistor to turn on. the MPS6515 will activate the Ipk(sense) pin and shorten ton on a cycle−by−cycle basis. The preset voltage reduces the maximum percent on−time of the output switch from a nominal of 85. Iout = 850 mA Vin = 28 V. All calculations are done for the typical voltage−inverting converter with an input of 28 V and an output of −120 V. the maximum rating of this device is 120 V. The peak drain current at 42 W output is 2. The inductor value will be 50 μH or 200 μH center tapped for the value of CT used. raising the voltage at Pin 10 which will cause a reduction in percent on−time of the output switch. the TL431 will start to conduct current through the LED in the 4N35. Without the tap. Iout = 850 mA Vin = 28 V. High Power Voltage−Inverting with Buffered Switch An economical 42 watt off−line flyback switcher is shown in Figure 35.AN920/D Vin = 28 V Rsc 0. the output switch transistor would need a VCE breakdown greater than 148 V at the start of toff.25 V Ref + 200 μH Center Tapped *Heatsink IERC Nested Pair HP1−T03−CB HP3−T03−CB Conditions Vin = 24 to 28 V. The maximum must be less than 50% when an equal turns ratio of primary to clamp winding is − + 1.0 A. and a 4N35 optocoupler.022 + 2N6438 * 4700 100 k 100 10 51 1050 1200 pF 9 10 11 GND CT OSC Comp Op Amp − Ipk S R 170 MR822 D1 5 4 3 2 1 560 Vout −120 V/850 mA + 1000 pF 13 VCC 14 15 16 12 Q 8 7 6 Test Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency This high power voltage−inverting circuit makes use of a center tapped inductor to step−up the magnitude of the output. Iout = 100 to 850 mA Vin = 28 V. RL = 0. Iout = 850 mA Results Δ = 100 mV or ± 0.8% used.0 V output reaches its nominal level. As the 5. Output regulation and isolation is achieved by the use of the TL431 as an output reference and comparator.029% 450 mVp−p 6.7% to about 45%.4 A 81. derived from the reference is connected to the inverting input.com 35 .

0 k 0.9 k 0.1 + + 15 k 2.0 k MUR110 8 + 0.030″ Spacer in each leg for a primary inductance of 550 μH. Primary to primary leakage inductance must be less than 30 μH.0 A http://onsemi.5 mH.0 V: 6 Turns (two strands) #18 AWG Bifilar Wound Secondary 12 V: 14 Turns #23 AWG Bifilar Wound Figure 35. The μA78S40 may be used in any of the previously shown circuit designs as a fixed frequency pulse width modulator. A complete printed circuit board with component layout is shown in Figure 36. L2.0047 UL/CSA MPS6515 1000 pF *Heatsink Thermalloy 6072B−MT T1 − Core and Bobbin: Coilcraft PT3995 Gap: 0.8 A 1000 10 + S Q R 170 D1 5 4 3 2 1 MTP 4N50 4 5 9 9 + 1000 10 + ±12 V Return 8 7 6 470 pF 5 6 560 4 680 1.24 3. Bifilar Wound Secondary 5.0 V/4. L1 − Coilcraft Z7156: Remove one layer for final inductance of 4.8 k MPSA55 1N4937 T1 − Primary: Pins 4 and 6 = 72 Turns #24 AWG.8 A * 1.AN920/D output is shorted.25 V Ref 7 L3 Vout3 −12 V/0. L3 − Coilcraft Z7157: 25 μH at 1. the Ipk(sense) circuit will cause CT to charge beyond the upper oscillator trip point and the oscillator frequency will decrease.1 115 VAC ±20% 9 10 11 GND CT Ipk OSC Comp − + Op Amp 12 L2 13 VCC 14 15 16 Vout2 12 V/0. This action will result in a lower average power dissipation for the output switching transistor. Each output has a series inductor and a second shunt filter capacitor forming a Pi filter.5 A T1 6 1N4303 Fusible Resistor 12 6 680 + 100 1 1/2 4N35 3. however consideration must be given to the proper selection of the feedback loop elements in order to insure circuit stability. Bifilar Wound Pins 5 and 6 = 72 Turns #26 AWG. Care must be taken with the layout of grounds in the Pi filter network.0 k 2200 20 Ω 470 20 A 22 + 2 0. Each input and output filter capacitor must have separate ground returns to the transformer as shown on the circuit diagram. 42 Watt Off−Line Flyback Switcher with Primary Power Limiting − + 1. MBR1635 L1 Vout1 5.3 k 1.com 36 .0 W 1000 3.0 V Return 1N965A 1000 pF 1. This is used to reduce the level of high frequency ripple and spikes.3 k 10 11 11 TL431 5.

Iout2 or Iout3 = 0.8 A 75.0 mV or ± 0.1 Ω Vin = 92 to 138 Vac Vin = 115 Vac.01% Δ = 3.com 37 . RL = 0.5 A Vin = 115 Vac Vin = 115 Vac.7% All outputs are at nominal load current unless otherwise noted. Figure 35.0 mV or ± 0. RL = 0.2 A Δ = 10 mV or ± 0. Iout1 = 1.AN920/D Test Line Regulation Load Regulation Output Ripple Short Circuit Current Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency NOTE: Vout1 Vout1 Vout1 Vout1 Vout2 or Vout3 Vout2 or Vout3 Vout2 or Vout3 Vout2 or Vout3 Vin = 92 to 138 Vac Vin = 115 Vac.03% 40 mVp−p 19.0 to 4.8 A Vin = 115 Vac Vin = 115 Vac.1 Ω Vin = 115 Vac Conditions Results Δ = 1.6% 80 mVp−p 10.04% Δ = 384 mV or ± 1.25 to 0. (continued) 42 Watt Off−Line Flyback Switcher with Primary Power Limiting http://onsemi.

AN920/D Component Layout − Bottom View Printed Circuit Board Negative − Bottom View Figure 36. 42 Watt Off−Line http://onsemi.com 38 .

15 + MPSU51A 1N5822 Vout1 −12 V/500 mA 36. Iout1 = 500 A Vin = 15 V. Iout1 = 500 mA. Iout2 = 500 mA Vin = 15 V. Tracking Regulator. Iout1 = 500 mA. The op amp is connected as a unity gain inverter when |Vout1| = |Vout2|. Iout1 = 500 mA. Voltage−Inverting with Buffered Switch and Buffered Linear Pass from Input − + 1.AN920/D Vin = 15 V 0. The ±12 V outputs are monitored by the op amp in a corrective fashion so that the voltage at the center of the divider is zero ± VIO.25 V Ref * Vout2 12 V/500 mA 12 k 200 0.021% 140 mVp−p 77. Iout1 = 500 mA. Iout2 = 100 to 500 mA.5 to 18 V.com 39 + + Results .008% 125 mVp−p Δ = 10 mV or ± 0. Iout2 = 500 mA Vin = 15 V.1 12 k Conditions Vin = 14.0 k 12 k 1.042% Δ = 2.0 mV or ± 0.5 to 18 V. Iout2 = 500 mA Vin = 14. Iout2 = 500 mA Δ = 10 mV or ± 0.1 μH 100 * 100 100 Vout2 Voltage Adj 2. Figure 37. Iout1 = 100 to 500 mA. Iout2 = 500 mA Vin = 15 V.5 k 270 180 pF 9 10 11 GND CT OSC Comp Op Amp − Ipk S R 170 D1 5 6.042% Δ = 5.2% http://onsemi.2 k 4 3 2 1 *Heatsink IERC PSC2−3 Q 12 13 VCC 14 15 16 8 7 6 MPSU01A Tracking Adj Test Line Regulation Load Regulation Output Ripple Line Regulation Load Regulation Output Ripple Efficiency Vout1 Vout1 Vout1 Vout2 Vout2 Vout2 This tracking regulator provides a ±12 V output from a single 15 V input. Iout2 = 500 mA Vin = 15 V.0 mV or ± 0. Iout1 = 500 mA. The negative output is generated by a voltage−inverting converter while the positive is a linear pass regulator taken from the input.

O. AN−P100. P. Switchmode Transformer Ferrite E−Core Packages. EDN. DS−P200. Copyright 1982 by Pulse Engineering. 2021 W. IN 46206 (317) 856−3731 United Chemi−Con 9801 W. Copyright 1982 by Fairchild Camera and Instruments Corporation. HeatSink/Dissipator Products and Thermal Management Guide. IL 60018 (312) 696−2000 Heatsinks IERC 135 W. BIBLIOGRAPHY Steve Hageman. by Ferroxcube Corporation. Voltage Regulator Handbook. by Abraham I. CA 92112 (714) 279−5900 Magnetic Cores Ferroxcube 5083 Kings Highway Saugerties.AN920/D SUMMARY The goal of this application note is to convey the theory of operation of the MC34063 and μA78S40.O. 1979. Copyright 1988 by Motorola Inc. Catalog MPP−303U. Molypermalloy Powder Cores. Valley View Lane Dallas. Copyright 1980 by International Electronic Research Corporation. IL 60013 (312) 639−2361 Pulse Engineering P. Inc. Copyright 1978 by Fairchild Camera and Instruments Corporation. PA 16512 (814) 452−5611 Mallory Capacitor Co. Linear and Interface Integrated Circuits Data Manual. Box 1284 Indianapolis. Cary. Another major objective is to show the ease and simplicity in designing switching converters and to remove any mystical “black magic” fears. P. 1983. Inc. Box 12235 San Diego.. mA78S40 Switching Voltage Regulator. Jim Lange.com 40 . Copyright 1977 by Hayden Book Company Inc. Texas 75234 (214) 243−4321 Magnetic Assemblies Coilcraft. Power Converter Design. NY 12477 (914) 246−2811 Magnetics. Copyright 1989 by Motorola Inc. Motorola Rectifiers and Zener Diodes Data Book. Motorola Power Data Book. Switching and Linear Power Supply. IL 60076 (312) 679−8200 ON Semiconductor does not endorse or warrant the suppliers referenced. January 20. Pressman. CA (213) 849−2481 Thermalloy. ON Semiconductor maintains a Linear and Discrete products applications staff that is dedicated to assisting customers with any design problems or questions. Linear Ferrite Materials and Components Sixth Edition. Box 961 Erie. SWITCHING REGULATOR COMPONENT SOURCES Capacitor Erie Technical Products P.O. Copyright 1989 by Motorola Inc. by Coilcraft Inc. Design Manual for SMPS Power Transformers. Burbank. Copyright 1981 by Magnetics Inc. ED 16. The circuits were chosen to explore a variety of cost effective and practical solutions in designing switching converters. Linear/Switchmode Voltage Regulator Hanbook Theory and Practice.O. and to show the derivation of the basic first order design equations. August 2. http://onsemi. Inc. Box 391 Butler. Suite 300 Skokie. Tapped Inductor Improves Efficiency for Switching Regulator. Structured Design of Switching Power Magnetics. DC/dc Converter Powers EEPROMs. PA 16001 (412) 282−8282 TDK Corporation of America 4709 Golf Rd. by Coilcraft Inc. Copyright 1988 by Motorola Inc. Higgins Road Rosemont. Application Note 370. Magnolia Blvd. 1102 Silver Lake Rd.

or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.com N. SCILLC reserves the right to make changes without further notice to any products herein. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application. SCILLC makes no warranty. costs. affiliates. please contact your local Sales Representative http://onsemi.O. employees. damages. any claim of personal injury or death associated with such unintended or unauthorized use. SCILLC products are not designed. representation or guarantee regarding the suitability of its products for any particular purpose. All operating parameters. or other applications intended to support or sustain life. subsidiaries. Box 5163.onsemi. Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe. consequential or incidental damages. intended. and expenses. directly or indirectly.AN920/D ON Semiconductor and are registered trademarks of Semiconductor Components Industries. SCILLC does not convey any license under its patent rights nor the rights of others. and distributors harmless against all claims. This literature is subject to all applicable copyright laws and is not for resale in any manner. Buyer shall indemnify and hold SCILLC and its officers.onsemi. including “Typicals” must be validated for each customer application by customer’s technical experts. nor does SCILLC assume any liability arising out of the application or use of any product or circuit. Denver. and specifically disclaims any and all liability. Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www. SCILLC is an Equal Opportunity/Affirmative Action Employer. and reasonable attorney fees arising out of.com Order Literature: http://www.com/orderlit For additional information.com 41 AN920/D . or authorized for use as components in systems intended for surgical implant into the body. LLC (SCILLC). PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P. even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. including without limitation special. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->