# Sheet 1 of 10

Cascode Current Mirror The main property/feature of a current source/sink is that the current though the device is independent of the voltage across it. Figure 1 shows the most basic of current sink. The current Iout is set by the voltage applied across the gate-source of the device, the greater the voltage the larger the current flow through the device. However as you can see from Figure 1 as the current increases then the slope in the saturation increases – for an ideal current sink/source we want this region to be flat ie very high resistance. These saturation slopes extrapolate to a point on the –x axis known as the Channel length modulation parameter λ, which is equal 1/-x, typical values are 0.01-0.05. The smaller this value then the smaller the slope in saturation and the better the current source/sink will be. The output resistance rout is given by:-

rout =

1 λ .I D
IOUT

Saturation Region

IOUT

Vout
M2

VGS

VSAT VGS

VOUT

VGG-VTO
Figure 1 Simple current sink As the slope in saturation region is determined by the output resistance rout then increasing this will greatly improve the performance of the current source/sink. In addition we would like to reduce Vsat to allow larger voltage swings across the device.

rds1.rds2). we can replace the resistor by an active resistor formed by a CMOS Fet and this forms the basis of the cascode current source/sink. . In reality this method is not to practical because of the voltage drop across the resistor however.rds1 Figure 3 Adding an active load to increase the rout of the current source/sink to improve performance.Sheet 2 of 10 One way of increasing the output resistance is to add a resistor between the source and ground as shown in Figure 2.rds2)r.rds2). IOUT Vout M2 VSAT VGS r Rout = (gm2.rds2). Figure 3 Shows the addition of an active load to M2 can increase the output resistance from rds2 to (gms2.r Figure 2 Method for increasing performance of current source/sink by adding a source resistor to increase rout by (gm2. IOUT VGS1 M2 Vout 2VSAT VGS2 M1 Rout = (gm2.

The circuits for the n-type and p-type diode (active resistors) are shown in Figure 4. ID = β (VGS − VT )2 2 Where β = K' W 2L As in the diode configurat ion the gate is connected to the source then VGS = VDS and ID = β (VDS − VT )2 2 2I D + VT β rearrange to get VDS VDS = In most applications these diodes can be used to generate a fixed bias voltages as shown in Figure 5. As used as an active load the resistance of the ‘diode’ is 1/gm. .Sheet 3 of 10 MOS Diode When the gate and drain terminals are connected together on a CMOS FET the operation is similar to a p-n junction diode. I Vout VSAT + VON M1 M1 VDD Vout VSAT + VON N –Type Diode P – Type Diode I Figure 4 Active resistor/diode configurations. and the sources are connected to supplies. The gates are connected to the drains.

which is fairly independent of current IREF. IREF can be set using a resistor or band-gap/resistor network.Sheet 4 of 10 VDD M2 Vout2 2VSAT + 2VON I M1 Vout1 VSAT + VON N –Type Diodes Figure 5 Two N-type CMOS diodes giving two fixed bias voltages of VSAT+VON and 2VAT+2VON We can use these CMOS diodes to provide bias to the current mirror shown in Figure 3 to form the most popular current source/sink circuits known as the cascode current mirror M1 & M2 are effectively two diodes in series with a total voltage drop of 2VSAT+2VT. .

(1) The bias to M2 (Vgs2) is 2VSAT + 2 VT Sub into (1) VD ≥ (2VSAT + 2VT ) .VT RIN = 1 1 + gm1 gm3 gm 2 2 = gm.go 4 R OUT = .VT . but lower output swing due to the extra device. M1 and M3 are wired as diodes and each have a voltage drop of VSAT+VT across the drain-source junction.Sheet 5 of 10 VDD IREF IOUT VIN M1 M2 Vout 2VSAT + VT 2 * VDSAT + 2 * VT M3 M4 VSAT + VT VSS VDSAT + VT Figure 6 Cascode current source. showing that the minimum voltage output is 2VSAT+VT above the rail VSS (in this case 0V).rds go 2 .VT = 2VSAT . VD ≥ VG . This circuit has higher output impedance than the simple current mirror.

ID 1 = 2.3V R OUT = R O4 + R O2 (1 + gm4.5MΩ 0.Sheet 6 of 10 Example Using the circuit of Figure 6. All FETs are the same (W/L =1).5E 6 1 + 80E -6 .2.5 ) + 1 = .ID VGS − VT = 2 * 20E -6 1. Vgs = VT + IREF Kp = 1+ 20E -6 80E -6 = 1.5 .5V VSAT = VGS . Kp = 80E-6. with VDD = +5V and VSS = -5V. ( ) .5 Vout = VSS .R O4 ) gm = 2.1 = 0. λ = 0.02 * 20E -6 ∴ R OUT = 2.2(0. for this setup the circuit was analysed and the annotate DC solution selected to add all the node voltage and currents to the circuit. Vout and Rout. The simulation setup is shown in Figure 7.5E 6 = 505MΩ The above circuit with the data given was simulated in ADS using a DC simulation to verify the calculated results. 5 − 1 = = 80E -6 A/V R O4 = R O2 = 1 λ. Calculate Vgs.(2VSAT + VT ) = 5 .02.VT = 1.5E 6 + 2. Assuming the following parameters VT = 1V.

61 V vgs3 0A -20 uA -40. The simulation has given slightly different results from the simplified hand calculations as you would expect.0 uA vd4 20.0 uA vd1 MOSFET_NMO MOSFET4 Model=MOSFETM Length=L um -5 V Width=W um MOSFET_NMO MOSFET2 Model=MOSFETM Length=L um Width=W um 20 uA -3.41 V 20.30 V vgs2 0A -20 uA -5 V -5 V MOSFET_NMO MOSFET1 Model=MOSFETM Length=L um Width=W um -5 V 0A -1. NOTE that the bulk connections have been connected to the lowest circuit potential ie –VDD or –5V.0 uA -2.63 pA -20.98 V 20. The resistor load has been calculated assuming a current of 20uA and a Vout minimum of –3V.0 uA V_DC SRC2 Vdc=VDD R R1 R=400000 MOSFET_NMO MOSFET3 Model=MOSFETM Length=L um Width=W um -20.Sheet 7 of 10 Var Eqn DC DC DC1 SweepVar= Start=0 Stop=5 Step=.71 pA -5 V 0A -3.11 pA LEVEL1_Mode MOSFETM NMOS=yes Vto=1 Kp=80e-6 Lambda=LAMBD -5 V -1.0 uA -3.0 uA V_DC SRC3 Vdc=-VDD Figure 7 ADS DC simulation of the cascode current source example.02 20 uA I_DC SRC1 Idc=20 uA 20 uA -1.0 -5 -5 V uA V -20. .0 uA I_Probe I1 -5.01 VAR VAR2 W=1 VDD=5 L=1 LAMBDA=0.60 pA -5 V 40.

25 then VON = 2.Id.L K' W And VON = If we set the W/L ratio of M1 to 0.Id.VT g Id = is also = VSAT K' W (VGS . because we are using two stages the current mirror will reduce the rail voltage available by VOUT= 2VSAT+VT. However.Sheet 8 of 10 Decreasing VOUT A cascode current sink can be used in the ‘tail’ in a long-tail pair/differential amplifier to improve the common mode rejection. One such circuit is shown in Figure 8. Vgs1 is VT + 2VON VD ≥ VG – VT (1) Sub into (1) To bias to M2 (Vgs1) is 2VSAT + VT VD ≥ (2VSAT + VT) – VT = 2VSAT . VGS = VON +VT So rearrangin VON = VGS . Other cascode circuits have been modified to reduce VOUT as much as possible.4W = K'L 4 = 2.VT )2 we can sub in to get Id = K' W (VON )2 2L 2L 2.VON Therefore. which could be typically ~ 2V less than the supply rail.

25).Sheet 9 of 10 VDD VDD IREF1 IREF2 W/L = 1/4 IOUT M1 M2 Vout 2VSAT 2VSAT+VT M3 M4 VSAT VSAT+VT VSS Figure 8 Method for decreasing the voltage drop across the two output devices to give a greater available voltage swing. M3 supplied 2VSAT+VT to the top pair FETS M4 and M5. Although this circuit has a low output voltage drop (2VON) it suffers in that M1 connected to M2 are not matched devices (M1 has a W/L ratio of 0. Each pair of FETS in the cascode are fed with the same bias. . To eliminate this problem the circuit shown in Figure 9 is used. As a result IOUT will not track IREF over temperature.

62 V vgs4 0A -1.73V giving voltage across the two output FETs of 1.0 uA -4.0 uA V 5 V_DC SRC2 5V Vdc=VDD 20 uA 5V R R1 R=437 kOhm I_DC SRC4 Idc=20 uA MOSFET_NMOS MOSFET5 Model=MOSFETM Length=L um 20 uA Width=W um -20. .635V).02 -692 fA 0A -5 V -5 V -5 V MOSFET_NMOS MOSFET6 Model=MOSFETM Length=L um Width=W um -5 V60.0 uA MOSFET_NMOS MOSFET4 Model=MOSFETM Length=L um Width=W um -5 V MOSFET_NMOS MOSFET2 Model=MOSFETM Length=L um Width=W um LEVEL1_Mode MOSFETM1 NMOS=yes Vto=1 Kp=80e-6 Lambda=LAMBD Var -20 uA -20 uAVAR Eqn VAR2 -5 V -4. The Vout in this case is –3.32 V W=1 Rload=1 20 uA -5 V VDD=5 L=1 -5 V LAMBDA=0.Sheet 10 of 10 DC DC DC1 5V 20 uA I_DC SRC1 Idc=20 uA 20 uA MOSFET_NMOS MOSFET3 Model=MOSFETM Length=4*L um -2.0 uA I_Probe I1 0A -2.73 V 20.0 V vd1 -3.30 V vgs2 0A -5 V -681 fA -5 V -5 V -20.40 pA 0A -2.27V (giving a VON for each device of 0.0 uA vd4 20.0 uA -3.33uA 20.39 pA Width=W um -60.0 uA -5 V -5 V -5 V -20 uA V_DC SRC3 Vdc=-VDD Figure 9 ADS Transient simulation of the improved high-voltage swing version of the cascode current source.96 pA -20.