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Introduction to
Electronics
An Online Text
Bob Zulinski
Associate Professor
of Electrical Engineering
Michigan Technological University
Version 2.0
Introduction to Electronics ii
Dedication
Human beings are a delightful and complex amalgam of
the spiritual, the emotional, the intellectual, and the physical.
This is dedicated to all of them; especially to those
who honor and nurture me with their friendship and love.
Introduction to Electronics iii
Table of Contents
Preface xvi
Philosophy of an Online Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi
Notes for Printing This Document . . . . . . . . . . . . . . . . . . . . . . . . xviii
Copyright Notice and Information . . . . . . . . . . . . . . . . . . . . . . . . xviii
Review of Linear Circuit Techniques 1
Resistors in Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Resistors in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Over Sum 1
Inverse of Inverses 1
Ideal Voltage Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ideal Current Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Real Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Voltage Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Current Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Superposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
A quick exercise 4
What’s missing from this review??? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
You’ll still need Ohm’s and Kirchoff’s Laws 5
Basic Amplifier Concepts 6
Signal Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ground Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
To work with (analyze and design) amplifiers . . . . . . . . . . . . . . . . . . . . . 7
Voltage Amplifier Model 8
Signal Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Amplifier Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Amplifier Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Open-Circuit Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Introduction to Electronics iv
Power Supplies, Power Conservation, and Efficiency 11
DC Input Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Conservation of Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Amplifier Cascades 13
Decibel Notation 14
Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Cascaded Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Current Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Using Decibels to Indicate Specific Magnitudes . . . . . . . . . . . . . . . . . . . 15
Voltage levels: 15
Power levels 16
Other Amplifier Models 17
Current Amplifier Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Transconductance Amplifier Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transresistance Amplifier Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Amplifier Resistances and Ideal Amplifiers 20
Ideal Voltage Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Ideal Current Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ideal Transconductance Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Ideal Transresistance Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Uniqueness of Ideal Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Frequency Response of Amplifiers 24
Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Magnitude Response 24
Phase Response 24
Frequency Response 24
Amplifier Gain 24
The Magnitude Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Causes of Reduced Gain at Higher Frequencies . . . . . . . . . . . . . . . . . . 26
Causes of Reduced Gain at Lower Frequencies . . . . . . . . . . . . . . . . . . 26
Introduction to Electronics v
Differential Amplifiers 27
Example: 27
Modeling Differential and Common-Mode Signals . . . . . . . . . . . . . . . . . 27
Amplifying Differential and Common-Mode Signals . . . . . . . . . . . . . . . . 28
Common-Mode Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ideal Operational Amplifiers 29
Ideal Operational Amplifier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Op Amp Operation with Negative Feedback . . . . . . . . . . . . . . . . . . . . . 30
Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Op Amp Circuits - The Inverting Amplifier 31
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Op Amp Circuits - The Noninverting Amplifier 33
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Input and Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Op Amp Circuits - The Voltage Follower 34
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Input and Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Op Amp Circuits - The Inverting Summer 35
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Op Amp Circuits - Another Inverting Amplifier 36
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Op Amp Circuits - Differential Amplifier 38
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Op Amp Circuits - Integrators and Differentiators 40
The Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
The Differentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Introduction to Electronics vi
Op Amp Circuits - Designing with Real Op Amps 42
Resistor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Source Resistance and Resistor Tolerances . . . . . . . . . . . . . . . . . . . . . 42
Graphical Solution of Simultaneous Equations 43
Diodes 46
Graphical Analysis of Diode Circuits 48
Examples of Load-Line Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Diode Models 50
The Shockley Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Forward Bias Approximation 51
Reverse Bias Approximation 51
At High Currents 51
The Ideal Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
An Ideal Diode Example 53
Piecewise-Linear Diode Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A Piecewise-Linear Diode Example 57
Other Piecewise-Linear Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Diode Applications - The Zener Diode Voltage Regulator 59
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Load-Line Analysis of Zener Regulators . . . . . . . . . . . . . . . . . . . . . . . . 59
Numerical Analysis of Zener Regulators . . . . . . . . . . . . . . . . . . . . . . . . 61
Circuit Analysis 62
Zener Regulators with Attached Load . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Example - Graphical Analysis of Loaded Regulator 64
Diode Applications - The Half-Wave Rectifier 66
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
A Typical Battery Charging Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
The Filtered Half-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Relating Capacitance to Ripple Voltage 70
Introduction to Electronics vii
Diode Applications - The Full-Wave Rectifier 72
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
1
st
(Positive) Half-Cycle 72
2
nd
(Negative) Half-Cycle 72
Diode Peak Inverse Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Diode Applications - The Bridge Rectifier 74
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
1
st
(Positive) Half-Cycle 74
2
nd
(Negative) Half-Cycle 74
Peak Inverse Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Diode Applications - Full-Wave/Bridge Rectifier Features 75
Bridge Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Full-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Filtered Full-Wave and Bridge Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . 75
Bipolar Junction Transistors (BJTs) 76
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Qualitative Description of BJT Active-Region Operation . . . . . . . . . . . . 77
Quantitative Description of BJT Active-Region Operation . . . . . . . . . . . 78
BJT Common-Emitter Characteristics 80
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Input Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Active Region 81
Cutoff 82
Saturation 82
The pnp BJT 83
BJT Characteristics - Secondary Effects 85
Introduction to Electronics viii
The n-Channel Junction FET (JFET) 86
Description of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Equations Governing n-Channel JFET Operation . . . . . . . . . . . . . . . . . 89
Cutoff Region 89
Triode Region 89
Pinch-Off Region 89
The Triode - Pinch-Off Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
The Transfer Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Metal-Oxide-Semiconductor FETs (MOSFETs) 92
The n-Channel Depletion MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
The n-Channel Enhancement MOSFET . . . . . . . . . . . . . . . . . . . . . . . . 93
Comparison of n-Channel FETs 94
p-Channel JFETs and MOSFETs 96
Cutoff Region 98
Triode Region 98
Pinch-Off Region 98
Other FET Considerations 99
FET Gate Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
The Body Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Basic BJT Amplifier Structure 100
Circuit Diagram and Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Load-Line Analysis - Input Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Load-Line Analysis - Output Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
A Numerical Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Basic FET Amplifier Structure 107
Amplifier Distortion 110
Biasing and Bias Stability 112
Introduction to Electronics ix
Biasing BJTs - The Fixed Bias Circuit 113
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
For b = 100 113
For b = 300 113
Biasing BJTs - The Constant Base Bias Circuit 114
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
For b = 100 114
For b = 300 114
Biasing BJTs - The Four-Resistor Bias Circuit 115
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Bias Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
To maximize bias stability 117
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
For b = 100 (and V
BE
= 0.7 V) 118
For b = 300 118
Biasing FETs - The Fixed Bias Circuit 119
Biasing FETs - The Self Bias Circuit 120
Biasing FETs - The Fixed + Self Bias Circuit 121
Design of Discrete BJT Bias Circuits 123
Concepts of Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Design of the Four-Resistor BJT Bias Circuit . . . . . . . . . . . . . . . . . . . . 124
Design Procedure 124
Design of the Dual-Supply BJT Bias Circuit . . . . . . . . . . . . . . . . . . . . . 125
Design Procedure 125
Design of the Grounded-Emitter BJT Bias Circuit . . . . . . . . . . . . . . . . 126
Design Procedure 126
Analysis of the Grounded-Emitter BJT Bias Circuit . . . . . . . . . . . . . . . 127
Introduction to Electronics x
Bipolar IC Bias Circuits 129
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
The Diode-Biased Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Current Ratio 130
Reference Current 131
Output Resistance 131
Compliance Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Using a Mirror to Bias an Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Wilson Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Current Ratio 133
Reference Current 134
Output Resistance 134
Widlar Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Current Relationship 135
Multiple Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
FET Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Linear Small-Signal Equivalent Circuits 138
Diode Small-Signal Equivalent Circuit 139
The Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
The Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Diode Small-Signal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Notation 142
BJT Small-Signal Equivalent Circuit 143
The Common-Emitter Amplifier 145
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Constructing the Small-Signal Equivalent Circuit . . . . . . . . . . . . . . . . . 146
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Introduction to Electronics xi
The Emitter Follower (Common Collector Amplifier) 149
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Review of Small Signal Analysis 153
FET Small-Signal Equivalent Circuit 154
The Small-Signal Equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
FET Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
The Common Source Amplifier 157
The Small-Signal Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
The Source Follower 159
Small-Signal Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Review of Bode Plots 164
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
The Bode Magnitude Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
The Bode Phase Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Single-Pole Low-Pass RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Gain Magnitude in dB 167
Bode Magnitude Plot 168
Bode Phase Plot 169
Single-Pole High-Pass RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Bode Magnitude Plot 170
Bode Phase Plot 171
Introduction to Electronics xii
Coupling Capacitors 172
Effect on Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Constructing the Bode Magnitude Plot for an Amplifier . . . . . . . . . . . . 174
Design Considerations for RC-Coupled Amplifiers 175
Low- & Mid-Frequency Performance of CE Amplifier 176
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Midband Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
The Effect of the Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . 179
The Effect of the Emitter Bypass Capacitor C
E
. . . . . . . . . . . . . . . . . . 180
The Miller Effect 183
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Deriving the Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
The Hybrid-p BJT Model 185
The Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Effect of C
p
and C
m
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
High-Frequency Performance of CE Amplifier 189
The Small-Signal Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
High-Frequency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
The CE Amplifier Magnitude Response . . . . . . . . . . . . . . . . . . . . . . . . 192
Nonideal Operational Amplifiers 193
Linear Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Input and Output Impedance 193
Gain and Bandwidth 193
Nonlinear Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Output Voltage Swing 194
Output Current Limits 194
Slew-Rate Limiting 194
Full-Power Bandwidth 195
Introduction to Electronics xiii
DC Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Input Offset Voltage, V
IO
195
Input Currents 195
Modeling the DC Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Using the DC Error Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
DC Output Error Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Finding Worst-Case DC Output Error 201
Canceling the Effect of the Bias Currents . . . . . . . . . . . . . . . . . . . . . . 203
Instrumentation Amplifier 204
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Simplified Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Noise 206
Johnson Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Johnson Noise Model 207
Shot Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
1/f Noise (Flicker Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Other mechanisms producing 1/f noise 209
Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Amplifier Noise Performance 211
Terms, Definitions, Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Amplifier Noise Voltage 211
Amplifier Noise Current 212
Signal-to-Noise Ratio 212
Noise Figure 213
Noise Temperature 213
Converting NF to/from T
n
214
Adding and Subtracting Uncorrelated Quantities . . . . . . . . . . . . . . . . . 214
Amplifier Noise Calculations 215
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Calculating Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Typical Manufacturer’s Noise Data 217
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Example #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Example #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Introduction to Electronics xiv
Noise - References and Credits 220
Introduction to Logic Gates 221
The Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
The Ideal Case 221
The Actual Case 221
Manufacturer’s Voltage Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 222
Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Manufacturer’s Current Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 223
Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Static Power Consumption 224
Dynamic Power Consumption 224
Rise Time, Fall Time, and Propagation Delay . . . . . . . . . . . . . . . . . . . 226
Speed-Power Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
TTL Logic Families & Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 228
CMOS Logic Families & Characteristics . . . . . . . . . . . . . . . . . . . . . . . 229
MOSFET Logic Inverters 230
NMOS Inverter with Resistive Pull-Up . . . . . . . . . . . . . . . . . . . . . . . . . 230
Circuit Operation 230
Drawbacks 231
CMOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Circuit Operation 232
Differential Amplifier 239
Modeling Differential and Common-Mode Signals . . . . . . . . . . . . . . . . 239
Basic Differential Amplifier Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Case #1 - Common-Mode Input 240
Case #2A - Differential Input 241
Case #2B - Differential Input 241
Large-Signal Analysis of Differential Amplifier 242
Introduction to Electronics xv
Small-Signal Analysis of Differential Amplifier 246
Differential Input Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Analysis of Differential Half-Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Differential Input Resistance 250
Differential Output Resistance 250
Common-Mode Input Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Analysis of Common-Mode Half-Circuit . . . . . . . . . . . . . . . . . . . . . . . . 253
Common-mode input resistance 253
Common-mode output resistance 253
Common-Mode Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Introduction to Electronics xvi
1
I use the word “supposedly” because, in my view, the official rewards for textbook
authoring fall far short of what is appropriate and what is achievable through an equivalent
research effort, despite all the administrative lip service to the contrary. These arguments,
though, are more appropriately left to a different soapbox.
Preface
Philosophy of an Online Text
I think of myself as an educator rather than an engineer. And it has
long seemed to me that, as educators, we should endeavor to bring
to the student not only as much information as possible, but we
should strive to make that information as accessible as possible,
and as inexpensive as possible.
The technology of the Internet and the World Wide Web now allows
us to virtually give away knowledge! Yet, we don’t, choosing
instead to write another conventional text book, and print, sell, and
use it in the conventional manner. The “whys” are undoubtedly
intricate and many; I offer only a few observations:
G Any change is difficult and resisted. This is true in the habits
we form, the tasks we perform, the relationships we engage.
It is simply easier not to change than it is to change. Though
change is inevitable, it is not well-suited to the behavior of any
organism.
G The proper reward structure is not in place. Faculty are
supposedly rewarded for writing textbooks, thereby bringing
fame and immortality to the institution of their employ.
1
The
recognition and reward structure are simply not there for a text
that is simply “posted on the web.”
G No economic incentive exists to create and maintain a
Introduction to Electronics xvii
structure that allows all authors to publish in this manner; that
allows students easy access to all such material, and that
rigorously ensures the material will exceed a minimum
acceptable quality.
If I were to do this the way I think it ought to be done, I would have
prepared the course material in two formats. The first would be a
text, identical to the textbooks with which you are familiar, but
available online, and intended to be used in printed form. The
second would be a slide presentation, à la Corel
®
Presentations¹
or Microsoft
®
PowerPoint
®
, intended for use in the classroom or in
an independent study.
But, alas, I am still on that journey, so what I offer you is a hybrid of
these two concepts: an online text somewhat less verbose than a
conventional text, but one that can also serve as classroom
overhead transparencies.
Other compromises have been made. It would be advantageous to
produce two online versions - one intended for use in printed form,
and a second optimized for viewing on a computer screen. The two
would carry identical information, but would be formatted with
different page and font sizes. Also, to minimize file size, and
therefore download times, font selection and variations are
somewhat limited when compared to those normally encountered
in a conventional textbook.
You may also note that exercise problems are not included with this
text. By their very nature problems quickly can become “worn out.”
I believe it is best to include problems in a separate document.
Until all of these enhancements exist, I hope you will find this a
suitable and worthwhile compromise.
Enough of this; let’s get on with it...
Introduction to Electronics xviii
Notes for Printing This Document
This document can be printed directly from the Acrobat
®
Reader -
see the Acrobat
®
Reader help files for details.
If you wish to print the entire document, do so in two sections, as
most printer drivers will only spool a maximum of 255 pages at one
time.
Copyright Notice and Information
This entire document is ©1999 by Bob Zulinski. All rights reserved.
I copyrighted this online text because it required a lot of work, and
because I hold a faint hope that I may use it to acquire
immeasurable wealth, thereby supporting the insatiable, salacious
lifestyle that I’ve always dreamed of.
Thus, you will need my permission to print it. You may obtain that
permission simply by asking: tell me who you are and what you
want it for. Route your requests via email to rzulinsk@mtu.edu, or
by USPS mail to Bob Zulinski, Dept. of Electrical Engineering,
Michigan Technological University, Houghton MI 49931-1295.
Generous monetary donations included with your request will be
looked upon with great favor.
Introduction to Electronics 1 Review of Linear Circuit Techniques
R
1
R
2
Fig. 1.
R’s in series.
R
1
R
2
Fig. 2.
R’s in parallel.
R R R R
total
+ + +
1 2 3
(1)
R
R R
R R
total

+
1 2
1 2
(2)
R
R R R
total

+ + +
1
1 1 1
1 2 3

(3)
Review of Linear Circuit Techniques
Resistors in Series
This is the simple one!!!
Resistors must carry the same current!!!
L’s is series and C’s in parallel have same form.
Resistors in Parallel
Resistors must have the same voltage!!!
Equation takes either of two forms:
Product Over Sum:
Only valid for two resistors. Not calculator-efficient!!!
Inverse of Inverses:
Always valid for multiple resistors. Very calculator-efficient!!!
L’s in parallel and C’s in series have same forms.
Introduction to Electronics 2 Review of Linear Circuit Techniques
+
-
+
-
3 V 5 V
Fig. 3. Ideal voltage
sources in parallel???
Fig. 4. Ideal current
sources in series???
v
i
V
OC
I
SC
1/R
TH
Fig. 5. Typical linear i - v
characteristic of a real source.
v V i R i I
v
R
OC TH SC
TH
− − or
(4)
Ideal Voltage Sources
Cannot be connected in parallel!!!
Real voltage sources include a series
resistance (“Thevenin equivalent”), and can
be paralleled.
Ideal Current Sources
Cannot be connected in series!!!
Real current sources include a parallel
resistance (“Norton equivalent”), and can be
connected in series.
Real Sources
All sources we observe in nature exhibit a
decreasing voltage as they supply increasing
current.
We presume that i-v relationship to be linear,
so we can write the equations:
Introduction to Electronics 3 Review of Linear Circuit Techniques
+
-
V
OC
=

V
TH
R
TH
+
-
v
i
Fig. 6. Thevenin
equivalent circuit.
I
SC
R
TH
+
-
v
i
Fig. 7. Norton equivalent
circuit.
+
-
+
+
+
-
-
-
V
X
V
A
V
B
V
C
R
A
R
B
R
C
Fig. 8. Example of a
voltage divider.
R
V
I
TH
OC
SC
(5)
V
R
R R R
V
B
B
A B C
X

+ +
(6)
The linear equations help us visualize what might be inside of a real
source:
Note that:
We can generalize this any linear resistive circuit can be ⇒
represented as in Figs. 6 and 7.
Voltage Dividers
Example - finding the voltage across R
B
:
Resistors must be in series, i.e., they must
carry the same current!!!
(Sometimes we cheat a little, and use the divider equation if the
currents through the resistors are almost the same - we’ll note this
in class if that is the case)
Introduction to Electronics 4 Review of Linear Circuit Techniques
R
A
R
B
R
C
I
X
I
B
Fig. 9. Example of a current divider.
+
-
I
Fig. 10. The total
response current I . . .
I
A
Fig. 11. . . . is the sum of
the response I
A
. . .
+
-
I
B
Fig. 12. . . . and the
response I
B
. . .
I
R
R R R
I
B
B
A B C
X

+ +
1
1 1 1
(7)
10 kΩ 30 kΩ
4 V 12 V
V
X
Fig. 13. A quick exercise . . .
Current Dividers
Resistors must be in parallel, i.e.,
have the same voltage!!!
Superposition
Superposition applies to any linear circuit - in fact, this is the
definition of a linear circuit!!!
An example of finding a response using superposition:
A quick exercise:
Use superposition and voltage division to show that V
X
= 6 V:
Introduction to Electronics 5 Review of Linear Circuit Techniques
What’s missing from this review???
Node voltages / mesh currents . . .
For the kinds of problems you’ll encounter in this course, I think you
should forget about these analysis methods!!!
If there is any other way to solve a circuit problem, do it that other
way . . . you’ll arrive at the answer more efficiently, and with more
insight.
You’ll still need Ohm’s and Kirchoff’s Laws:
KVL: Sum of voltages around a closed loop is zero.
We’ll more often use a different form:
Sum of voltages from point A to point B is the same
regardless of the path taken.
KCL: Sum of currents into a node (or area) is zero.
I won’t insult you by repeating Ohm’s Law here . . .
Introduction to Electronics 6 Basic Amplifier Concepts
Signal
Source
Amplifier Load v
i
(t) v
o
(t)
+ +
- -
Ground
Fig. 14. Block diagram of basic amplifier.
v
i
t
Fig. 15. Generic input
signal voltage.
v
o
t
Fig. 16. Output voltage
of noninverting
amplifier.
v
o
t
Fig. 17. Output voltage
of inverting amplifier.
Basic Amplifier Concepts
Signal Source
A signal source is anything that provides the signal, e.g., . . .
. . . the carbon microphone in a telephone handset . . .
. . . the fuel-level sensor in an automobile gas tank . . .
Amplifier
An amplifier is a system that provides gain . . .
. . . sometimes voltage gain (illustrated below), sometimes current
gain, always power gain.
Introduction to Electronics 7 Basic Amplifier Concepts
Signal
Source
Amplifier Load v
i
(t) v
o
(t)
+ +
- -
Ground
Fig. 18. Block diagram of basic amplifier (Fig. 14 repeated).
Load
The load is anything we deliver the amplified signal to, e.g., . . .
. . . loudspeaker . . .
. . . the leg of lamb in a microwave oven . . .
Ground Terminal
Usually there is a ground connection . . .
. . . usually common to input and output . . .
. . . maybe connected to a metal chassis . . .
. . . maybe connected to power-line ground . . .
. . . maybe connected to both . . .
. . . maybe connected to neither . . . use caution!!!
To work with (analyze and design) amplifiers
we need to visualize what might be inside all three blocks of Fig. 18,
i.e., we need models!!!
Introduction to Electronics 8 Voltage Amplifier Model
+
+
-
-
v
s
v
i
A
voc
v
i
v
o
+ +
- -
R
S
R
L
R
i
R
o
i
i
i
o
Source Amplifier Load
Fig. 19. Modeling the source, amplifier, and load with the emphasis on
voltage.
Voltage Amplifier Model
This is usually the one we have the most intuition about . . .
Signal Source
Our emphasis is voltage . . . source voltage decreases as source
current increases, as with any real source . . .
. . . so we use a Thevenin equivalent.
Amplifier Input
When the source is connected to the amplifier, current flows . . .
. . . the amplifier must have an input resistance, R
i
.
Amplifier Output
Output voltage decreases as load current increases . . .
. . . again we use a Thevenin equivalent.
Load
Load current flows . . . the load appears as a resistance, R
L
.
Introduction to Electronics 9 Voltage Amplifier Model
+
+
-
-
v
s
v
i
A
voc
v
i
v
o
+ +
- -
R
S
R
L
R
i
R
o
i
i
i
o
Source Amplifier Load
Fig. 20. Voltage amplifier model (Fig. 19 repeated).
+
-
v
i
A
voc
v
i
v
o
+ +
- -
R
L
R
i
R
o
i
i
i
o
Amplifier Load
+
-
v
i
Fig. 21. A
v
= v
o
/v
i
illustrated.
A
v
v
voc
o
i
R
L


(8)
A
v
v
v
R
R R
A v A A
R
R R
V
o
i
o
L
o L
voc i v voc
L
o L

+

+
(9)
Open-Circuit Voltage Gain
If we remove R
L
(i.e., with R
L
= ) the voltage of the Thevenin ∞
source in the amplifier output is the open-circuit output voltage of
the amplifier. Thus, A
voc
is called the open-circuit voltage gain:
Voltage Gain
With a load in place our concept of voltage gain changes slightly:
We can think of this as the amplifier voltage gain if the source were
ideal:
Introduction to Electronics 10 Voltage Amplifier Model
+
+
-
-
v
s
v
i
A
voc
v
i
v
o
+ +
- -
R
S
R
L
R
i
R
o
i
i
i
o
Source Amplifier Load
Fig. 22. Voltage amplifier model (Fig. 19 repeated).
A
v
v
v
R
R R
v A A
R
R R
R
R R
vs
o
s
i
i
S i
s vs voc
i
S i
L
o L

+

+ +
(10)
A
i
i
v
R
v
R
v
v
R
R
A
R
R
i
o
i
o
L
i
i
o
i
i
L
v
i
L
(11)
G
P
P
V I
VI
A A A
R
R
A
R
R
o
i
o o
i i
v i v
i
L
i
L
i

2 2
(12)
With our “real” source model we define another useful voltage gain:
Notice that A
v
and A
vs
are both less than A
voc
, due to loading effects.
Current Gain
We can also define the amplifier current gain:
Power Gain
Because the amplifier input and load are resistances, we have
P
o
= V
o
I
o
, and P
i
= V
i
I
i
(rms values). Thus:
Introduction to Electronics 11 Power Supplies, Power Conservation, and Efficiency
+
+
-
-
v
s
v
i
A
voc
v
i
v
o
+ +
- -
R
S
R
L
R
i
R
o
i
i
i
o
Source Amplifier Load
V
AA
-V
BB
I
A
I
B
V
AA
V
BB
+
+
-
-
Fig. 23. Our voltage amplifier model showing power supply and ground connections.
P V I V I
S AA A BB B
+ (13)
P P P P
S i o D
+ + (14)
Power Supplies, Power Conservation, and Efficiency
The signal power delivered to the load is converted from the dc
power provided by the power supplies.
DC Input Power
This is sometimes noted as P
IN
. Use care not to confuse this with
the signal input power P
i
.
Conservation of Power
Signal power is delivered to the load P
o

Power is dissipated within the amplifier as heat P
D

The total input power must equal the total output power:
Virtually always P
i
<< P
S
and is neglected.
Introduction to Electronics 12 Power Supplies, Power Conservation, and Efficiency
+
+
-
-
v
s
v
i
A
voc
v
i
v
o
+ +
- -
R
S
R
L
R
i
R
o
i
i
i
o
Source Amplifier Load
V
AA
-V
BB
I
A
I
B
V
AA
V
BB
+
+
-
-
Fig. 24. Our voltage amplifier model showing power supply and ground connections
(Fig. 23 repeated).
η ×
P
P
o
S
100% (15)
Efficiency
Efficiency is a figure of merit describing amplifier performance:
Introduction to Electronics 13 Amplifier Cascades
+
-
v
i1
A
voc1
v
i1
+
-
R
i1
R
o1
i
i1
+
-
v
o1
=

v
i2
A
voc2
v
i2
+
-
R
i2
R
o2
i
i2
i
o2
v
o2
+
-
Amplifier 1 Amplifier 2
Fig. 25. A two-amplifier cascade.
A
v
v
v
o
i
1
1
1
(16)
+
-
v
i1
A
voc
v
i1
+
-
R
i1
R
o2
i
i1
i
o2
v
o2
+
-
Fig. 26. Model of cascade.
A
v
v
v
v
v
o
i
o
o
2
2
2
2
1
(17)
A
v
v
v
v
A A
voc
o
i
o
o
v v

1
1
2
1
1 2
(18)
Amplifier Cascades
Amplifier stages may be connected together (cascaded) :
Notice that stage 1 is loaded by the input resistance of stage 2.
Gain of stage 1:
Gain of stage 2:
Gain of cascade:
We can replace the two models by a single model (remember, the
model is just a visualization of what might be inside):
Introduction to Electronics 14 Decibel Notation
10 10
10 10 10
20 10 10
2
2
log log
log log log
log log log
G A
R
R
A R R
A R R
v
i
L
v i L
v i L

+ −
+ −
(21)
G G
dB
10log (19)
G GG G G G G
total dB dB dB , , ,
log log log + + 10 10 10
1 2 1 2 1 2
(20)
Decibel Notation
Amplifier gains are often not expressed as simple ratios . . . rather
they are mapped into a logarithmic scale.
The fundamental definition begins with a power ratio.
Power Gain
Recall that G = P
o
/P
i
, and define:
G
dB
is expressed in units of decibels, abbreviated dB.
Cascaded Amplifiers
We know that G
total
= G
1
G
2
. Thus:
Thus, the product of gains becomes the sum of gains in decibels.
Voltage Gain
To derive the expression for voltage gain in decibels, we begin by
recalling from eq. (12) that G = A
v
2
(R
i
/R
L
). Thus:
Introduction to Electronics 15 Decibel Notation
A A
v dB v
20log (22)
A A
i dB i
20log (23)
316 20
316
1
10 . log
.
V =
V
V
dBV
(24)
Even though R
i
may not equal R
L
in most cases, we define:
Only when R
i
does equal R
L
, will the numerical values of G
dB
and
A
v dB
be the same. In all other cases they will differ.
From eq. (22) we can see that in an amplifier cascade the product
of voltage gains becomes the sum of voltage gains in decibels.
Current Gain
In a manner similar to the preceding voltage-gain derivation, we can
arrive at a similar definition for current gain:
Using Decibels to Indicate Specific Magnitudes
Decibels are defined in terms of ratios, but are often used to
indicate a specific magnitude of voltage or power.
This is done by defining a reference and referring to it in the units
notation:
Voltage levels:
dBV, decibels with respect to 1 V . . . for example,
Introduction to Electronics 16 Decibel Notation
5 10
5
699 mW=
mW
1 mW
dBm log .
(25)
5 230 mW=10log
5 mW
1 W
dbW − .
(26)
Power levels:
dBm, decibels with respect to 1 mW . . . for example
dBW, decibels with respect to 1 W . . . for example
There is a 30 dB difference between the two previous examples
because 1 mW = - 30 dBW and 1 W = +30 dBm.
Introduction to Electronics 17 Other Amplifier Models
+
+
-
-
v
s
v
i
A
voc
v
i
v
o
+ +
- -
R
S
R
L
R
i
R
o
i
i
i
o
Source Amplifier Load
Fig. 27. Modeling the source, amplifier, and load with the emphasis on
voltage (Fig. 19 repeated).
i
s
R
S
R
L
R
o
i
i
i
o
Source Current Amplifier Load
v
i
+
-
R
i
v
o
+
- A
isc
i
i
Fig. 28. Modeling the source, amplifier, and load with the emphasis on
current.
A
i
i
isc
o
i
R
L

0
(27)
Other Amplifier Models
Recall, our voltage amplifier model arose from our visualization of
what might be inside a real amplifier:
Current Amplifier Model
Suppose we choose to emphasize current. In this case we use
Norton equivalents for the signal source and the amplifier:
The short-circuit current gain is given by:
Introduction to Electronics 18 Other Amplifier Models
R
L
R
o
i
i
i
o
Source Transconductance Amplifier Load
v
i
+
-
R
i
v
o
+
- G
msc
v
i
+
-
v
s
R
S
Fig. 29. The transconductance amplifier model.
+
-
v
i
R
moc
i
i
v
o
+ +
- -
R
L
R
i
R
o
i
i
i
o
Source Transresistance Amplifier Load
i
s
R
S
Fig. 30. The transresistance amplifier model.
G
i
v
msc
o
i
R
L

0
(siemens, S) (28)
R
v
i
moc
o
i
R
L


(ohms, ) Ω (29)
Transconductance Amplifier Model
Or, we could emphasize input voltage and output current:
The short-circuit transconductance gain is given by:
Transresistance Amplifier Model
Our last choice emphasizes input current and output voltage:
The open-circuit transresistance gain is given by:
Introduction to Electronics 19 Other Amplifier Models
Any of these four models can be used to represent what might be
inside of a real amplifier.
Any of the four can be used to model the same amplifier!!!
G Models obviously will be different inside the amplifier.
G If the model parameters are chosen properly, they will
behave identically at the amplifier terminals!!!
We can change from any kind of model to any other kind:
G Change Norton equivalent to Thevenin equivalent (if
necessary).
G Change the dependent source’s variable of dependency
with Ohm’s Law v
i
= i
i
R
i
(if necessary). ⇒
Try it!!! Pick some values and practice!!!
Introduction to Electronics 20 Amplifier Resistances and Ideal Amplifiers
+
+
-
-
v
s
v
i
A
voc
v
i
v
o
+
+
- -
R
S
R
L
R
i
R
o
i
i
i
o
Source Voltage Amplifier Load
Fig. 31. Voltage amplifier model.
Amplifier Resistances and Ideal Amplifiers
Ideal Voltage Amplifier
Let’s re-visit our voltage amplifier model:
We’re thinking voltage, and we’re thinking amplifier . . . so how can
we maximize the voltage that gets delivered to the load ?
G We can get the most voltage out of the signal source if
R
i
>> R
S
, i.e., if the amplifier can “measure” the signal voltage
with a high input resistance, like a voltmeter does.
In fact, if , we won’t have to worry about the value of R
i
⇒∞
R
S
at all!!!
G We can get the most voltage out of the amplifier if R
o
<< R
L
,
i.e., if the amplifier can look as much like a voltage source as
possible.
In fact, if , we won’t have to worry about the value of R
L
R
o
⇒0
at all!!!
So, in an ideal world, we could have an ideal amplifier!!!
Introduction to Electronics 21 Amplifier Resistances and Ideal Amplifiers
+
-
A
voc
v
i
v
i
+
-
Fig. 32. Ideal voltage amplifier. Signal
source and load are omitted for clarity.
i
s
R
S
R
L
R
o
i
i
i
o
Source Current Amplifier Load
v
i
+
-
R
i
v
o
+
- A
isc
i
i
Fig. 33. Current amplifier model (Fig. 28 repeated).
An ideal amplifier is only a concept; we cannot build one.
But an amplifier may approach the ideal, and we may use the
model, if only for its simplicity.
Ideal Current Amplifier
Now let’s revisit our current amplifier model:
How can we maximize the current that gets delivered to the load ?
G We can get the most current out of the signal source if
R
i
<< R
S
, i.e., if the amplifier can “measure” the signal current
with a low input resistance, like an ammeter does.
In fact, if , we won’t have to worry about the value of R
S
R
i
⇒0
at all!!!
Introduction to Electronics 22 Amplifier Resistances and Ideal Amplifiers
A
isc
i
i
i
i
Fig. 34. Ideal current amplifier.
G
msc
v
i
v
i
+
-
Fig. 35. Ideal transconductance amplifier.
G We can get the most current out of the amplifier if R
o
>> R
L
,
i.e., if the amplifier can look as much like a current source as
possible.
In fact, if , we won’t have to worry about the value of R
o
⇒∞
R
L
at all!!!
This leads us to our conceptual ideal current amplifier:
Ideal Transconductance Amplifier
With a mixture of the previous concepts we can conceptualize an
ideal transconductance amplifier.
This amplifier ideally measures the input voltage and produces an
output current:
Introduction to Electronics 23 Amplifier Resistances and Ideal Amplifiers
R
moc
i
i
i
i
+
-
Fig. 36. Ideal transresistance amplifier.
Ideal Transresistance Amplifier
Our final ideal amplifier concept measures input current and
produces an output voltage:
Uniqueness of Ideal Amplifiers
Unlike our models of “real” amplifiers, ideal amplifier models cannot
be converted from one type to another (try it . . .).
Introduction to Electronics 24 Frequency Response of Amplifiers
A
V
V
V V
V V
A A
v
o
i
o o
i i
v v



∠ (30)
A A
v v
dB
20log (31)
Frequency Response of Amplifiers
Terms and Definitions
In real amplifiers, gain changes with frequency . . .
“Frequency” implies sinusoidal excitation which, in turn, implies
phasors . . . using voltage gain to illustrate the general case:
Both |A
v
| and A
v
are functions of frequency and can be plotted. ∠
Magnitude Response:
A plot of |A
v
| vs. f is called the magnitude response of the amplifier.
Phase Response:
A plot of A
v
vs. f is called the phase response of the amplifier. ∠
Frequency Response:
Taken together the two responses are called the frequency
response . . . though often in common usage the term frequency
response is used to mean only the magnitude response.
Amplifier Gain:
The gain of an amplifier usually refers only to the magnitudes:
Introduction to Electronics 25 Frequency Response of Amplifiers
f

(log scale)
|A
v
|
dB
|A
v mid
|
dB
3 dB
f
H
Bandwidth, B
midband region
Fig. 37. Magnitude response of a dc-coupled, or direct-coupled amplifier.
f

(log scale)
|A
v
|
dB
|A
v mid
|
dB
3 dB
f
L
f
H
Bandwidth, B
midband region
Fig. 38. Magnitude response of an ac-coupled, or RC-coupled amplifier.
The Magnitude Response
Much terminology and measures of amplifier performance are
derived from the magnitude response . . .
|A
v mid
|
dB
is called the midband gain . . .
f
L
and f
H
are the 3-dB frequencies, the corner frequencies, or the
half-power frequencies (why this last one?) . . .
B is the 3-dB bandwidth, the half-power bandwidth, or simply the
bandwidth (of the midband region) . . .
Introduction to Electronics 26 Frequency Response of Amplifiers
+
-
+
-
Fig. 39. Two-stage amplifier model including stray
wiring inductance and stray capacitance between
stages. These effects are also found within each
amplifier stage.
+
-
+
-
Fig. 40. Two-stage amplifier model showing
capacitive coupling between stages.
Causes of Reduced Gain at Higher Frequencies
Stray wiring inductances . . .
Stray capacitances . . .
Capacitances in the amplifying devices (not yet included in our
amplifier models) . . .
The figure immediately below provides an example:
Causes of Reduced Gain at Lower Frequencies
This decrease is due to capacitors placed between amplifier stages
(in RC-coupled or capacitively-coupled amplifiers) . . .
This prevents dc voltages in one stage from affecting the next.
Signal source and load are often coupled in this manner also.
Introduction to Electronics 27 Differential Amplifiers
+
-
+
-
+
-
+
-
v
I1
v
I2
v
ICM
v
ID
/2
v
ID
/2
1
1
2
2
+ -
Fig. 41. Representing two sources by their differential and
common-mode components.
v v
v
v v
v
I ICM
ID
I ICM
ID
1 2
2 2
+ − and
(32)
Differential Amplifiers
Many desired signals are weak, differential signals in the presence
of much stronger, common-mode signals.
Example:
Telephone lines, which carry the desired voice signal between the
green and red (called tip and ring) wires.
The lines often run parallel to power lines for miles along highway
right-of-ways . . . resulting in an induced 60 Hz voltage (as much as
30 V or so) from each wire to ground.
We must extract and amplify the voltage difference between the
wires, while ignoring the large voltage common to the wires.
Modeling Differential and Common-Mode Signals
As shown above, any two signals can be modeled by a differential
component, v
ID
, and a common-mode component, v
ICM
, if:
Introduction to Electronics 28 Differential Amplifiers
+
-
+
-
v
o
=

A
d
v
id
+

A
cm
v
icm
v
id
/2
v
id
/2
+ -
Amplifier
+
-
v
icm
Fig. 42. Amplifier with differential and common-mode input signals.
CMRR
A
A
dB
d
cm
20log (34)
v v v v
v v
ID I I ICM
I I

+
1 2
1 2
2
and
(33)
Solving these simultaneous equations for v
ID
and v
ICM
:
Note that the differential voltage v
ID
is the difference between the
signals v
I1
and v
I2
, while the common-mode voltage v
ICM
is the
average of the two (a measure of how they are similar).
Amplifying Differential and Common-Mode Signals
We can use superposition to describe the performance of an
amplifier with these signals as inputs:
A differential amplifier is designed so that A
d
is very large and A
cm
is very small, preferably zero.
Differential amplifier circuits are quite clever - they are the basic
building block of all operational amplifiers
Common-Mode Rejection Ratio
A figure of merit for “diff amps,” CMRR is expressed in decibels:
Introduction to Electronics 29 Ideal Operational Amplifiers
+
-
v
+
v
-
v
O
v
O
=

A
0
(v
+
-v
-
)
Fig. 43. The ideal operational amplifier:
schematic symbol, input and output voltages,
and input-output relationship.
Ideal Operational Amplifiers
The ideal operational amplifier is an
ideal differential amplifier:
A
0
= A
d
= A
cm
= 0 ∞
R
i
= R
o
= 0 ∞
B = ∞
The input marked “+” is called the noninverting input . . .
The input marked “-” is called the inverting input . . .
The model, just a voltage-dependent voltage source with the gain
A
0
(v
+
- v
-
), is so simple that you should get used to analyzing
circuits with just the schematic symbol.
Ideal Operational Amplifier Operation
With A
0
= , we can conceive of three rules of operation: ∞
1. If v
+
> v
-
then v
o
increases . . .
2. If v
+
< v
-
then v
o
decreases . . .
3. If v
+
= v
-
then v
o
does not change . . .
In a real op amp v
o
cannot exceed the dc power supply voltages,
which are not shown in Fig. 43.
In normal use as an amplifier, an operational amplifier circuit
employs negative feedback - a fraction of the output voltage is
applied to the inverting input.
Introduction to Electronics 30 Ideal Operational Amplifiers
Op Amp Operation with Negative Feedback
Consider the effect of negative feedback:
G If v
+
> v
-
then v
o
increases . . .
Because a fraction of v
o
is applied to the inverting input,
v
-
increases . . .
The “gap” between v
+
and v
-
is reduced and will eventually
become zero . . .
Thus, v
o
takes on the value that causes v
+
- v
-
= 0!!!
G If v
+
< v
-
then v
o
decreases . . .
Because a fraction of v
o
is applied to the inverting input,
v
-
decreases . . .
The “gap” between v
+
and v
-
is reduced and will eventually
become zero . . .
Thus, v
o
takes on the value that causes v
+
- v
-
= 0!!!
In either case, the output voltage takes on whatever value that
causes v
+
- v
-
= 0!!!
In analyzing circuits, then, we need only determine the value of v
o
which will cause v
+
- v
-
= 0.
Slew Rate
So far we have said nothing about the rate at which v
o
increases or
decreases . . . this is called the slew rate.
In our ideal op amp, we’ll presume the slew rate is as fast as we
need it to be (i.e., infinitely fast).
Introduction to Electronics 31 Op Amp Circuits - The Inverting Amplifier
+
-
+
v
O
v
i
R
1
R
2
i
1
i
2
0
Fig. 44. Inverting amplifier circuit.
v
v R v R
R R
i o


+
+
2 1
1 2
(35)
v R v R v
R
R
v A
R
R
i o o i v 2 1
2
1
2
1
0 + ⇒ − ⇒ −
(36)
Op Amp Circuits - The Inverting Amplifier
Let’s put our ideal op amp concepts to work in this basic circuit:
Voltage Gain
Because the ideal op amp has R
i
= , the current into the inputs ∞
will be zero.
This means i
1
= i
2
, i.e., resistors R
1
and R
2
form a voltage dividerIII
Therefore, we can use superposition to find the voltage v
-
.
(Remember the quick exercise on p. 4

??? This is the identical
problem!!!):
Now, because there is negative feedback, v
o
takes on whatever
value that causes v
+
- v
-
= 0

, and v
+
= 0 !!!
Thus, setting eq. (35) to zero, we can solve for v
o
:
Introduction to Electronics 32 Op Amp Circuits - The Inverting Amplifier
+
-
+
v
O
v
i
R
1
R
2
i
1
i
2
0
Fig. 45. Inverting amplifier circuit
(Fig. 44 repeated).
i
v
R
R
v
i
v
R
i
in
i i
v
R
i
1
1 1
1
1

(37)
R
O
0 (38)
Input Resistance
This means resistance “seen” by the signal source v
i
, not the input
resistance of the op amp, which is infinite.
Because v
-
= 0, the voltage across R
1
is v
i
. Thus:
Output Resistance
This is the Thevenin resistance which would be “seen” by a load
looking back into the circuit (Fig. 45 does not show a load attached).
Our op amp is ideal; its Thevenin output resistance is zero:
Introduction to Electronics 33 Op Amp Circuits - The Noninverting Amplifier
+
-
+
v
O
v
i
R
1
R
2
i
1
i
2
0
Fig. 46. Noninverting amplifier circuit.
v v v
R
R R
v
i o

+
+ −
1
1 2
(39)
v
R R
R
v
R
R
v A
R
R
o i i v

+
+
|
(
'
`
J
J
⇒ +
1 2
1
2
1
2
1
1 1 (40)
R R
in i
∞ (41)
R
O
0 (42)
Op Amp Circuits - The Noninverting Amplifier
If we switch the v
i
and ground connections on the inverting
amplifier, we obtain the noninverting amplifier:
Voltage Gain
This time our rules of operation and a voltage divider equation lead
to:
from which:
Input and Output Resistance
The source is connected directly to the ideal op amp, so:
A load “sees” the same ideal Thevenin resistance as in the inverting
case:
Introduction to Electronics 34 Op Amp Circuits - The Voltage Follower
+
-
+
v
o
v
i
Fig. 47. The voltage follower.
v v v v A
i o v

+ −
1 (43)
R R
in O
∞ and 0 (44)
Op Amp Circuits - The Voltage Follower
Voltage Gain
This one is easy:
i.e., the output voltage follows the input voltage.
Input and Output Resistance
By inspection, we should see that these values are the same as for
the noninverting amplifier . . .
In fact, the follower is just a special case of the noninverting
amplifier, with R
1
= and R
2
= 0!!! ∞
Introduction to Electronics 35 Op Amp Circuits - The Inverting Summer
+
-
+
v
O
v
B
R
B
R
F
i
A
i
F
+
v
A
R
A
i
B
+ -
Fig. 48. The inverting summer.
i
v
R
i
v
R
A
A
A
B
B
B
and
(45)
( ) i i i v R i i R
v
R
v
R
F A B R F A B F
A
A
B
B
F
+ + +
|
(
'
`
J
J and
(46)
v
R
R
v
R
R
v
O
F
A
A
F
B
B
− +
|
(
'
`
J
J
(47)
Op Amp Circuits - The Inverting Summer
This is a variation of the inverting amplifier:
Voltage Gain
We could use the superposition approach as we did for the
standard inverter, but with three sources the equations become
unnecessarily complicated . . . so let’s try this instead . . .
Recall . . . v
O
takes on the value that causes v
-
= v
+
= 0 . . .
So the voltage across R
A
is v
A
and the voltage across R
B
is v
B
:
Because the current into the op amp is zero:
Finally, the voltage rise to v
O
equals the drop across R
F
:
Introduction to Electronics 36 Op Amp Circuits - Another Inverting Amplifier
+
-
+
v
O
v
i
R
1
R
2
i
1 R
4
R
3
i
2
Fig. 49. An inverting amplifier with a resistive T-network
for the feedback element.
v
O
R
4
R
3
v
TH
R
TH
+ +
Fig. 50. Replacing part of the original circuit with a
Thevenin equivalent
Op Amp Circuits - Another Inverting Amplifier
If we want very large gains with the standard inverting amplifier of
Fig. 44, one of the resistors will be unacceptably large or
unacceptably small . . .
We solve this problem with the following circuit:
Voltage Gain
One common approach to a solution begins with a KCL equation at
the R
2
- R
3
- R
4
junction . . .
. . . we’ll use the superposition & voltage divider approach, after we
apply some network reduction techniques.
Notice that R
3
, R
4
and the op amp output voltage source can be
replaced with a Thevenin equivalent:
Introduction to Electronics 37 Op Amp Circuits - Another Inverting Amplifier
v
-
=

0
v
TH
R
EQ
= R
2
+

R
TH
R
1
v
i
Fig. 51. Equivalent circuit to original amplifier.
v
R
R R
v R R R
TH O TH

+

3
3 4
3 4
and || (48)
v
R
R
v
TH
EQ
i

1
(49)
( ) R
R R
v
R R R
R
v
R
R
R R
R
v
O i i
3
3 4
2 3 4
1
2
1
3 4
1
+

+
− +
|
(
'
`
J
J
||
||
(50)
A
v
v
R
R
R
R
R R
R
v
O
i
− +
|
(
'
`
J
J
+
|
(
'
`
J
J
1
4
3
2
1
3 4
1
||
(51)
The values of the Thevenin elements in Fig. 50 are:
With the substitution of Fig. 50 we can simplify the original circuit:
Again, v
O
, and therefore v
TH
, takes on the value necessary to make
v
+
- v
-
= 0 . . .
We’ve now solved this problem twice before (the “quick exercise” on
p. 4, and the standard inverting amplifier analysis of p. 31):
Substituting for v
TH
and R
EQ
, and solving for v
O
and A
v
:
Introduction to Electronics 38 Op Amp Circuits - The Differential Amplifier
+
-
+
v
O
v
1
R
1
R
2
i
1
i
2
+
R
1
R
2
v
2
+ -
Fig. 52. The differential amplifier.
v
R
R R
v v
+ −

+

2
1 2
2
(52)
( )
i
v v
R
v
R
R
R R R
v i
1
1
1
1
1
2
1 1 2
2 2



+


(53)
( )
v i R
R
R
v
R R
R R R
v
R
2
2 2
2
1
1
2 2
1 1 2
2

+
(54)
( )
v v v
R
R R
v
R
R
v
R R
R R R
v
O R

+
− +
+
+
2
2
1 2
2
2
1
1
2 2
1 1 2
2
(55)
Op Amp Circuits - Differential Amplifier
The op amp is a differential amplifier to begin with, so of course we
can build one of these!!!
Voltage Gain
Again, v
O
takes on the value
required to make v
+
= v
-
.
Thus:
We can now find the current
i
1
, which must equal the
current i
2
:
Knowing i
2
, we can calculate the voltage across R
2
. . .
Then we sum voltage rises to the output terminal:
Introduction to Electronics 39 Op Amp Circuits - The Differential Amplifier
( ) ( ) ( )
R
R R
v
R R
R R R
v
R R
R R R
v
R R
R R R
v
2
1 2
2
2 2
1 1 2
2
1 2
1 1 2
2
2 2
1 1 2
2
+
+
+

+
+
+
(56)
( )
( )
( )

+
+

+
+

R R R R
R R R
v
R R R
R R R
v
R
R
v
1 2 2 2
1 1 2
2
2 1 2
1 1 2
2
2
1
2
(57)
( )
v
R
R
v
R
R
v
R
R
v v
O
− + −
2
1
1
2
1
2
2
1
2 1
(58)
Working with just the v
2
terms from eq. (55) . . .
And, finally, returning the resulting term to eq. (55):
So, under the conditions that we can have identical resistors (and
an ideal op amp) we truly have a differential amplifier!!!
Introduction to Electronics 40 Op Amp Circuits - Integrators and Differentiators
+
-
v
O
v
i
R C
i
R
i
C
+
+ -
Fig. 53. Op amp integrator.
i
v
R
i
R
i
C

(59)
( ) v
C
i dt
C
i dt v
C C
t
C C
t
+
−∞
∫ ∫
1 1
0
0
(60)
( ) ( )
v
C
v
R
dt v
RC
v dt v
O
i
t
C i C
t
− + − +
∫ ∫
1
0
1
0
0 0
(61)
Op Amp Circuits - Integrators and Differentiators
Op amp circuits are not limited to resistive elements!!!
The Integrator
From our rules and previous
experience we know that v
-
= 0
and i
R
= i
C
, so . . .
From the i-v relationship of a
capacitor:
Combining the two previous equations, and recognizing that
v
O
= - v
C
:
Normally v
C
(0) = 0 (but not always). Thus the output is the integral
of v
i
, inverted, and scaled by 1/RC.
Introduction to Electronics 41 Op Amp Circuits - Integrators and Differentiators
+
-
v
O
v
i
R C
i
R
i
C
+
+
-
Fig. 54. The op amp differentiator.
i C
dv
dt
C
dv
dt
i
C
C i
R

(62)
v v i R RC
dv
dt
O R R
i
− − − (63)
The Differentiator
This analysis proceeds in the
same fashion as the previous
analysis.
From our rules and previous
experience we know that v
-
= 0
and i
C
= i
R
. . .
From the i-v relationship of a capacitor:
Recognizing that v
O
= -v
R
:
Introduction to Electronics 42 Op Amp Circuits - Designing with Real Op Amps
+
-
+
v
O
v
i
R
1
R
L
i
L
i
F
+
-
R
2
Fig. 55. Noninverting amplifier with load.
+
-
+
v
O
v
i
R
1
R
2
i
1
i
2
R
S
Fig. 56. Inverting amplifier including source resistance.
Op Amp Circuits - Designing with Real Op Amps
Resistor Values
Our ideal op amp can supply unlimited current; real ones can’t . . .
To limit i
F
+ i
L
to a reasonable
value, we adopt the “rule of
thumb” that resistances should
be greater than approx. 100 Ω.
Of course this is highly
dependent of the type of op amp
to be used in a design.
Larger resistances render circuits more susceptible to noise and
more susceptible to environmental factors.
To limit these problems we adopt the “rule of thumb” that
resistances should be less than approximately 1 MΩ.
Source Resistance and Resistor Tolerances
In some designs R
S
will
affect desired gain.
Resistor tolerances will
also affect gain.
If we wish to ignore source resistance effects, resistances must be
much larger than R
S
(if possible).
Resistor tolerances must also be selected carefully.
Introduction to Electronics 43 Graphical Solution of Simultaneous Equations
y x y and 4 (64)
Fig. 57. Simple example of obtaining the solution to simultaneous
equations using a graphical method.
Graphical Solution of Simultaneous Equations
Let’s re-visit some 7
th
-grade algebra . . .we can find the solution of
two simultaneous equations by plotting them on the same set of
axes.
Here’s a trivial example:
We plot both equations:
Obviously, the solution is where the two plots intersect, at x = 4,
y = 4 . . .
Introduction to Electronics 44 Graphical Solution of Simultaneous Equations
y
x
x

<

|
¦
|
0 0
0
, for
0.4x , for
2
(65)
Fig. 58. Another example of graphically finding the solution to
simultaneous equations.
y
x
− 8
4
5
(66)
Let’s try another one:
and
Here we see that the solution is approximately at x = 3.6, y = 5.2.
Note that we lose some accuracy with a graphical method, but, we
gain the insight that comes with the “picture.”
Introduction to Electronics 45 Graphical Solution of Simultaneous Equations
Fig. 59. Graphically finding multiple solutions.
y x x 0 4
2
. , for all
(67)
y
x
− 8
4
5
(68)
If we change the previous example slightly, we’ll see that we can’t
arbitrarily neglect the other quadrants:
and
Now we have two solutions - the first one we found before, at
x = 3.6, y = 5.2 . . . the second solution is at x = -5.5, y = 12.5.
In the pages and weeks to come, we will often use a graphical
method to find current and voltage in a circuit.
This technique is especially well-suited to circuits with nonlinear
elements.
Introduction to Electronics 46 Diodes
Anode Cathode
p-type n-type
+ -
i
D
v
D
+
+
+
+
+
+
+
-
-
-
-
-
-
-
free
electrons
free
”holes”
Fig. 60. Simplified physical construction and schematic symbol of
a diode.
Diodes
When we “place” p-type semiconductor adjacent to n-type
semiconductor, the result is an element that easily allows current to
flow in one direction, but restricts current flow in the opposite
direction . . . this is our first nonlinear element:
The free holes “wish” to combine with the free electrons . . .
When we apply an external voltage that facilitates this combination
(a forward voltage, v
D
> 0), current flows easily.
When we apply an external voltage that opposes this combination,
(a reverse voltage, v
D
< 0), current flow is essentially zero.
Of course, we can apply a large enough reverse voltage to force
current to flow . . .this is not necessarily destructive.
Introduction to Electronics 47 Diodes
Fig. 61. PSpice-generated i-v characteristic for a 1N750 diode showing the various regions of
operation.
Thus, the typical diode i-v characteristic:
V
F
is called the forward knee voltage, or simply, the forward voltage.
G It is typically approximately 0.7 V, and has a temperature
coefficient of approximately -2 mV/K
V
B
is called the breakdown voltage.
G It ranges from 3.3 V to kV, and is usually given as a positive
value.
Diodes intended for use in the breakdown region are called zener
diodes (or, less often, avalanche diodes).
In the reverse bias region, |i
D
| 1 nA for low-power (“signal”) ≈
diodes.
Introduction to Electronics 48 Graphical Analysis of Diode Circuits
i
D
+
-
v
D
+
-
R
V
S
Fig. 62. Example circuit to illustrate
graphical diode circuit analysis.
v
+
-
(=R)
V
OC
i
+
-
(=V
S
)
R
TH
Fig. 63. Thevenin eq. of
Fig. 62 identified.
V
OC
I
SC
1/R
TH
v=v
D
i=i
D
Fig. 64. Graphical solution.
v V iR i I
v
R
OC TH SC
TH
− − or
(69)
Graphical Analysis of Diode Circuits
We can analyze simple diode circuits using the graphical method
described previously:
We need two equations to find the
two unknowns i
D
and v
D
.
The first equation is “provided” by
the diode i-v characteristic.
The second equation comes from
the circuit to which the diode is
connected.
This is just a standard Thevenin
equivalent circuit . . .
. . . and we already know its i-v
characteristic . . . from Fig. 5 and eq.
(4) on p. 2:
. . . where V
OC
and I
SC
are the open-
circuit voltage and the short-circuit
current, respectively.
A plot of this line is called the load
line, and the graphical procedure is
called load-line analysis.
Introduction to Electronics 49 Graphical Analysis of Diode Circuits
i
D
+
-
v
D
+
-
R
V
S
Fig. 65. Example circuit
(Fig. 62 repeated).
Case 3: V
OC
= V
S
= 10 V
I
SC
= 10 V / 1 kΩ = 10 mA
V
OC
not on scale, use slope:
1
1
1 2 5
2 5 k
mA
V
mA
V Ω

.
.
The solution is at:
v
D
0.68 V, i
D
9.3 mA ≈ ≈
Fig. 66. Example solutions.
Examples of Load-Line Analysis
Case 1: V
S
= 2.5 V and R = 125 Ω
Case 2: V
S
= 1 V and R = 25 Ω
Case 3: V
S
= 10 V and R = 1 kΩ
Case 1: V
OC
= V
S
= 2.5 V and I
SC
= 2.5 V / 125 Ω = 20 mA.
We locate the intercepts, and draw the line.
The solution is at v
D
0.71 V, i
D
14.3 mA ≈ ≈
Case 2: V
OC
= V
S
= 1 V and I
SC
= 1 V / 25 Ω = 40 mA
I
SC
is not on scale, so we use the slope:
1
25
40 20
0 5 Ω

mA
V
mA
V .
The solution is at v
D
0.70 V, i
D
12.0 mA ≈ ≈
Introduction to Electronics 50 Diode Models
i I
v
nV
D S
D
T

|
(
'
`
J
J

]
]
]
exp 1 (70)
v nV
i
I
D T
D
S
+
|
(
'
`
J
J
ln 1 (71)
V
kT
q
T
(72)
Diode Models
Graphical solutions provide insight, but neither convenience nor
accuracy . . . for accuracy, we need an equation.
The Shockley Equation
or conversely
where,
I
S
is the saturation current, 10 fA for signal diodes ≈
I
S
approx. doubles for every 5 K increase in temp.
n is the emission coefficient, 1 n 2 ≤ ≤
n = 1 is usually accurate for signal diodes (i
D
< 10 mA)
V
T
is the thermal voltage,
k, Boltzmann’s constant, k = 1.38 (10
-23
) J/K
T. temperature in kelvins
q, charge of an electron, q = 1.6 (10
-19
) C
Note: at T = 300 K, V
T
= 25.9 mV
we’ll use V
T
= 25 mV as a matter of convenience.
Introduction to Electronics 51 Diode Models
i I
v
nV
D S
D
T

|
(
'
`
J
J
exp (75)
i I
D S
≈ − (76)
v nV
i
I
i R
D T
D
S
D S
+
|
(
'
`
J
J
+ ln 1 (77)
i I
v
nV
D S
D
T

|
(
'
`
J
J

]
]
]
exp 1 (73)
v nV
i
I
D T
D
S
+
|
(
'
`
J
J
ln 1 (74)
Repeating the two forms of the Shockley equation:
Forward Bias Approximation:
For v
D
greater than a few tenths of a volt, exp(v
D
/nV
T
) >> 1, and:
Reverse Bias Approximation:
For v
D
less than a few tenths (negative), exp(v
D
/nV
T
) << 1, and:
At High Currents:
where R
S
is the resistance of the bulk semiconductor material,
usually between 10 Ω and 100 Ω.
Introduction to Electronics 52 Diode Models
+
-
i
D
v
D
fwd bias (ON)
rev bias (OFF)
Fig. 67. Ideal diode i-v characteristic.
Let’s stop and review . . .
G Graphical solutions provide insight, not accuracy.
G The Shockley equation provides accuracy, not convenience.
But we can approximate the diode i-v characteristic to provide
convenience, and reasonable accuracy in many cases . . .
The Ideal Diode
This is the diode we’d like to have.
We normally ignore the breakdown
region (although we could model this,
too).
Both segments are linear . . . if we
knew the correct segment we could
use linear analysis!!!
In general we don’t know which line segment is correct . . .so we
must guess , and then determine if our guess is correct.
If we guess “ON,” we know that v
D
= 0, and that i
D
must turn out to
be positive if our guess is correct.
If we guess “OFF,” we know that i
D
= 0, and that v
D
must turn out to
be negative if our guess is correct.
Introduction to Electronics 53 Diode Models
10 V 10 V
+
+ +
-
- -
4 kΩ
6 kΩ 3 kΩ
7 kΩ v
D
i
D
Fig. 68.Circuit for an ideal diode example.
10 V 10 V
+
+ +
- -
4 kΩ
6 kΩ 3 kΩ
7 kΩ
v
D
-
Fig. 69.Equivalent circuit if the diode is OFF.
10 V 10 V
+
+ +
- -
4 kΩ
6 kΩ 3 kΩ
7 kΩ
v
D
-
6 V 3 V
+ +
- -
Fig. 70.Calculating v
D
for the OFF diode.
10 V 10 V
+ +
- -
4 kΩ
6 kΩ 3 kΩ
7 kΩ i
D
Fig. 71.Equivalent circuit if the diode is ON.
6 V 3 V
+ +
- -
2.4 kΩ 2.1 kΩ i
D
667 µA
Fig. 72.Calculating i
D
for the ON diode.
An Ideal Diode Example:
We need first to
assume a diode state,
i.e., ON or OFF.
We’ll arbitrarily choose
OFF.
If OFF, i
D
= 0, i.e., the
diode is an open circuit.
We can easily find v
D
using voltage division
and KVL v
D
= 3 V. ⇒
v
D
is not negative, so
diode must be ON.
If ON, v
D
= 0, i.e., the
diode is a short circuit.
We can easily find i
D

using Thevenin eqs.
i
D
= 667 µA. ⇒
No contradictions !!!
Introduction to Electronics 54 Diode Models
+
-
i
D
v
D
fwd bias (ON)
rev bias (OFF)
Fig. 73. Ideal diode i-v characteristic.
(Fig. 67 repeated)
Let’s review the techniques, or rules, used in analyzing ideal diode
circuits. These rules apply even to circuits with multiple diodes:
1. Make assumptions about diode states.
2. Calculate v
D
for all OFF diodes, and i
D
for all ON diodes.
3. If all OFF diodes have v
D
< 0, and all ON diodes have i
D
> 0,
the initial assumption was correct. If not make new
assumption and repeat.
Introduction to Electronics 55 Diode Models
V
X
-V
X
/R
X
1/R
X
i
v
Fig. 74. A piecewise-linear segment.
+
+
-
-
V
X
R
X
v
i
Fig. 75. Circuit producing eq. (?).
v V iR
X X
+ (78)
Piecewise-Linear Diode Models
This is a generalization of the ideal diode concept.
Piecewise-linear modeling uses straight line segments to
approximate various parts of a nonlinear i-v characteristic.
The line segment at left has the
equation:
The same equation is provided
by the following circuit:
Thus, we can use the line segments of Fig. 74 to approximate
portions of an element’s nonlinear i-v characteristic . . .
. . . and use the equivalent circuits of Fig. 75 to represent the
element with the approximated characteristic!!!
Introduction to Electronics 56 Diode Models
i
D
v
D
V
F
1/R
F
V
Z
1/R
Z
Fig. 76. A diode i-v characteristic (red) and
its piecewise-linear equivalent (blue).
A “complete” piecewise-linear diode model looks like this:
G In the forward bias region . . .
. . . the approximating segment is characterized by the forward
voltage, V
F
, and the forward resistance, R
F
.
G In the reverse bias region . . .
. . . the approximating segment is characterized by i
D
= 0, i.e.,
an open circuit.
G In the breakdown region . . .
. . . the approximating segment is characterized by the zener
voltage, V
Z
, (or breakdown voltage, V
B
) and the zener
resistance, R
Z
.
Introduction to Electronics 57 Diode Models
5 V
500 Ω
+ +
-
-
v
D
i
D
Fig. 77. Circuit for piecewise-
linear example.
5 V
500 Ω
+
+
-
-
v
D
+
-
0.5 V
10 Ω
Fig. 78. Equivalent circuit in forward
bias region.
i
D


+

5 05
500 10
882
V V
mA
.
.
Ω Ω
(79)
( )( )
v
D
+

05 882 10
0588
. .
.
V mA
V

(80)
A Piecewise-Linear Diode Example:
We have modeled a diode using piecewise-linear segments with:
V
F
= 0.5 V, R
F
= 10 , and V
Z
= 7.5 V, R
Z
= 2.5 Ω Ω
Let us find i
D
and v
D
in the following circuit:
We need to “guess” a line segment.
Because the 5 V source would tend to
force current to flow in a clockwise
direction, and that is the direction of
forward diode current, let us choose the
forward bias region first.
Our equivalent circuit for the forward bias
region is shown at left. We have
and
This solution does not contradict our forward bias assumption, so
it must be the correct one for our model.
Introduction to Electronics 58 Diode Models
+
-
i
D
v
D
fwd bias (ON)
rev bias (OFF)
Fig. 79. Ideal diode i-v characteristic.
(Fig. 67 repeated)
+
-
i
D
v
D
V
F
fwd bias (ON)
rev bias (OFF)
Fig. 80. I-v characteristic of constant voltage
drop diode model.
Other Piecewise-Linear Models
Our ideal diode model is a
special case . . .
. . . it has V
F
= 0, R
F
= 0 in the
forward bias region . . .
. . . it doesn’t have a
breakdown region.
The constant voltage drop
diode model is also a special
case . . .
. . . it has R
F
= 0 in the forward
bias region . . .
. . . V
F
usually 0.6 to 0.7 V . . .
. . . it doesn’t have a
breakdown region
Introduction to Electronics 59 The Zener Diode Voltage Regulator
+
+
+
-
-
-
V
TH
R
TH
=

500 Ω
v
D v
OUT
i
D
7.5 V to 10 V
Fig. 81. Thevenin equivalent source with
unpredictable voltage and zener diode.
Diode Applications - The Zener Diode Voltage Regulator
Introduction
This application uses diodes in the breakdown region . . .
For V
Z
< 6 V the physical breakdown phenomenon is called zener
breakdown (high electric field). It has a negative temperature
coefficient.
For V
Z
> 6 V the mechanism is called avalanche breakdown (high
kinetic energy). It has a positive temperature coefficient.
For V
Z
6 V the breakdown voltage has nearly zero temperature ≈
coefficient, and a nearly vertical i-v char. in breakdown region, i.e.,
a very small R
Z
.
These circuits can produce nearly constant voltages when used
with voltage supplies that have variable or unpredictable output
voltages. Hence, they are called voltage regulators.
Load-Line Analysis of Zener Regulators
Note: when intended for use
as a zener diode, the
schematic symbol changes
slightly . . .
With V
TH
positive, zener
current can flow only if the
zener is in the breakdown
region . . .
We can use load line analysis with the zener diode i-v characteristic
to examine the behavior of this circuit.
Introduction to Electronics 60 The Zener Diode Voltage Regulator
+
+
+
-
-
-
V
TH
R
TH
=

500 Ω
v
D v
OUT
i
D
7.5 V to 10 V
Fig. 82. Thevenin equivalent source with
unpredictable voltage and zener diode.
(Fig. 81 repeated)
Fig. 83. 1N750 zener (V
Z
= 4.7 V) i-v
characteristic in breakdown region, with load
lines from source voltage extremes.
Note that v
OUT
= -v
D
. Fig. 83
below shows the graphical
construction.
Because the zener is upside-down
the Thevenin equivalent load line
is in the 3
rd
quadrant of the diode
characteristic.
As V
TH
varies from 7.5 V to 10 V, the load line moves from its blue
position, to its green position.
As long as the zener remains in breakdown, v
OUT
remains nearly
constant, at 4.7 V. ≈
As long as the minimum V
TH
is somewhat greater than V
Z
(in this
case V
Z
= 4.7 V) the zener remains in the breakdown region.
If we’re willing to give up some output voltage magnitude, in return
we get a very constant output voltage.
This is an example of a zener diode voltage regulator providing line
voltage regulation . . . V
TH
is called the line voltage.
Introduction to Electronics 61 The Zener Diode Voltage Regulator
Fig. 84. Zener i-v characteristic of Fig. 83 with
piecewise-linear segment.
+
-
V
TH
R
TH
=

500 Ω
v
OUT
7.5 V to 10 V
8 Ω
4.6 V
+
-
+
-
Fig. 85. Regulator circuit of Fig. 81 with piecewise-
linear model replacing the diode.
Numerical Analysis of Zener Regulators
To describe line voltage regulation numerically we use linear circuit
analysis with a piecewise-linear model for the diode.
To obtain the model we draw a tangent to the curve in the vicinity
of the operating point:
From the intercept and slope of the piecewise-linear segment we
obtain V
Z
= 4.6 V and R
Z
= 8 Ω. Our circuit model then becomes:
Introduction to Electronics 62 The Zener Diode Voltage Regulator
+
-
V
TH
R
TH
=

500 Ω
v
OUT
7.5 V to 10 V
8 Ω
4.6 V
+
-
+
-
Fig. 86. Regulator with diode model
(Fig. 85 repeated).
( )
V
8
8
500 8
75 46 4567


Ω Ω

+
− . . . V V mV
(81)
V
O
+ 46 4567 464567 . . . V mV V (82)
( )
V
8
8
500 8
10 46 8504


Ω Ω

+
− V V V . .
(83)
V
O
+ 46 8504 468504 . . . V mV V (84)
Important: The model above is valid only if zener is in
breakdown region !!!
Circuit Analysis:
The 500 Ω and 8 Ω resistors are in series, forming a voltage divider.
For V
TH
= 7.5 V:
For V
TH
= 10 V:
Thus, for a 2.5 V change in the line voltage, the output voltage
change is only 39.4 mV !!!
Introduction to Electronics 63 The Zener Diode Voltage Regulator
+
+
-
-
v
D
v
OUT
i
D
+
-
V
SS
R
S
R
L
Fig. 87. Zener regulator with load.
+
+
-
-
v
D v
OUT
i
D
+
-
V
SS
R
S
R
L
Fig. 88. Regulator drawn with zener and
load in reversed positions.
+
+
-
-
v
D v
OUT
i
D
+
-
V
TH
R
TH
Fig. 89. Regulator of Fig. 87 with V
SS
, R
S
,
and R
L
replaced by Thevenin eq.
Zener Regulators with Attached Load
Now let’s add a load to our regulator circuit . . .
Only the zener is nonlinear, so we approach this problem by finding
the Thevenin equivalent seen by the diode:

The resulting circuit is topologically identical to the circuit we just
analyzed!!!
Different loads will result in different values for V
TH
and R
TH
, but the
analysis procedure remains the same!!!
Introduction to Electronics 64 The Zener Diode Voltage Regulator
+
+
-
-
v
D
v
OUT
i
D
+
-
R
S
= 500 Ω
R
L
10 V V
SS
Fig. 90. Example of loaded zener regulator for
graphical analysis.
V V
OC TH

+

10
500
10 952
k
10 k
V V

Ω Ω
.
(85)
I
V
R
SC
SS
S

10
20
V
500
mA

(86)
V V
OC TH

1
10
k
1k + 500
V = 6.67 V

Ω Ω
(87)
I
V
R
SC
SS
S

10
20
V
500
mA

(88)
Example - Graphical Analysis of Loaded Regulator
Let’s examine graphically the behavior of a loaded zener regulator.
Let V
SS
= 10 V, R
S
= 500 Ω and,
(a) R
L
= 10 kΩ (b) R
L
= 1 kΩ (c) R
L
= 100 Ω
We find the load lines in each case by calculating the open-circuit
(Thevenin) voltage and the short-circuit current:
(a)
(b)
Introduction to Electronics 65 The Zener Diode Voltage Regulator
V V
OC TH

+

100
100 500
10 167

Ω Ω
V V .
(89)
Fig. 91. Load line analysis for the loaded zener regulator.
I
V
R
SC
SS
S

10
20
V
500
mA

(90)
(c)
The three load lines are plotted on the zener characteristic below:
As long as R
L
(and therefore V
TH
) is large enough so that the zener
remains in breakdown, the output voltage is nearly constant !!!
This is an example of a zener diode voltage regulator providing load
voltage regulation (or simply, load regulation).
Introduction to Electronics 66 The Half-Wave Rectifier
v
O
v
D
V
m
sin ωt v
S
+ +
+
- -
-
R
L
Fig. 92. The half-wave rectifier circuit.
t
v
S
T
V
m
-V
m
Fig. 93. Waveform of voltage source.
t
v
O
T
V
m
Fig. 94. Output voltage waveform.
t
v
D
T
-V
m
Fig. 95. Diode voltage waveform.
Diode Applications - The Half-Wave Rectifier
Introduction
This diode application changes
ac into dc. The voltage source is
most often a sinusoid (but can be
anything).
We’ll assume the diode is ideal
for our analysis.
During positive half-cycle . . .
. . . diode conducts (“ON”)
. . . v
D
= 0
. . . v
O
= v
S
During negative half-cycle . . .
. . . diode “OFF”
. . . i
D
= 0, v
O
= 0
. . . v
D
= v
S
Peak Inverse Voltage, PIV:
Another term for breakdown
voltage rating . . .
. . . in this circuit, the diode
PIV rating must be > V
m
.
Introduction to Electronics 67 The Half-Wave Rectifier
R
total
D
V
BATTERY
+
-
A
110 V
rms
V
m
sin ωt
+
-
Fig. 96. A circuit typical of most battery chargers.
t
V
m
-V
m
T
V
BATT
Charging
current
v
S
Fig. 97. Battery charger waveforms.
Here v
S
represents the transformer secondary voltage, and V
BATT
represents the battery voltage.
A Typical Battery Charging Circuit
In the figure above . . .
. . . V
BATTERY
represents the battery to be charged . . .
. . . R
total
includes all resistance (wiring, diode, battery, etc.) reflected
to the transformer secondary winding.
Charging current flows only when V
m
sin ωt > V
BATTERY
. . .
. . . inertia of meter movement allows indication of average current.
Introduction to Electronics 68 The Half-Wave Rectifier
v
S
(t)
C R
L
v
L
(t)
i
D
(t) i
L
(t)
+
+
-
-
Fig. 98. Filtered half-wave rectifier.
t
v
L
(t)
V
m
Ripple voltage, V
r
on diode off
T T
on on diode off
Fig. 99. Load voltage waveform in the filtered half-wave rectifier.
The Filtered Half-Wave Rectifier
Also called a peak rectifier, a half-wave rectifier with a smoothing
capacitor, or a half-wave rectifier with a capacitor-input filter.
We create it by placing a capacitor in parallel with the rectifier load
(creating a low-pass filter):
Analysis of this circuit
with a nonlinear element
is very difficult . . .
. . . so we will use the
ideal diode model.
A lot happens in this circuit!!! Let’s look at the load voltage:
Introduction to Electronics 69 The Half-Wave Rectifier
t
v
L
(t)
V
m
Ripple voltage, V
r
on diode off
T T
on on diode off
Fig. 100. Load voltage waveform (Fig. 99 repeated).
We let v
S
(t) = V
m
sin ωt . . . and assume steady-state . . .
1. When v
S
> v
L
(shown in blue), the diode is on, and the voltage
source charges the capacitor.
(Because the diode and source are ideal, v
S
can only be
infinitesimally greater than v
L
)
2. When v
S
< v
L
(shown in red), the diode is off, and C discharges
exponentially through R
L
.
3. We define peak-to-peak ripple voltage, V
r
, as the total change
in v
L
over one cycle.
4. In practice, V
r
is much smaller than shown here, typically being
1% to 0.01% of V
m
(e.g., a few mV). This means that:
(a) the load voltage is essentially “pure” dc
(b) the diode is off for almost the entire period, T !!!
Introduction to Electronics 70 The Half-Wave Rectifier
t
v
L
(t)
V
m
Ripple voltage, V
r
on diode off
T T
on on diode off
Fig. 101. Load voltage waveform (Fig. 99 repeated).
Q I T
V
R
T
V
fR
L
m
L
m
L
≈ ≈
(91)
Q V C
r
(92)
V C
V
fR
C
V
V fR
r
m
L
m
r L

(93)
Relating Capacitance to Ripple Voltage
Because the diode is off for nearly the entire period, T, the capacitor
must supply the “dc” load current during this interval.
The charge taken from the capacitor in this interval is:
The capacitor voltage decreases by V
r
in this interval, which
requires a decrease in the charge stored in the capacitor:
Equating these equations and solving for C gives us a design
equation that is valid only for small V
r
:
Introduction to Electronics 71 The Half-Wave Rectifier
t
v
L
(t)
V
m
Ripple voltage, V
r
on diode off
T T
on on diode off
Fig. 102. Load voltage waveform (Fig. 99 repeated).
t
i(t)
T T
i
D
(t)
i
L
(t)
i
D PEAK
on on on diode off diode off
Fig. 103. Current waveforms in filtered half-wave rectifier.
Because all of the charge supplied to the load must come from the
source only when the diode is ON, i
D PEAK
can be very large, as
illustrated below..
Introduction to Electronics 72 The Full-Wave Rectifier
v
S
(t)
v
L
(t)
i
L
(t)
+
-
v
S
(t)
v
in
(t)
+
+
-
-
v
A
(t)
v
B
(t)
D
A
D
B
R
L
Fig. 104. The full-wave rectifier.
t
v
S
V
m
-V
m
Fig. 105. Voltage across each half of the
transformer secondary.
t
v
L
V
m
Fig. 106. Full-wave load voltage.
Diode Applications - The Full-Wave Rectifier
The full-wave rectifier makes use of a center-tapped transformer to
effectively create two equal input sources:
Operation
Note that the upper half of the transformer secondary voltage has
its negative reference at ground, while the lower half of the
secondary voltage has its positive reference at ground.
1
st
(Positive) Half-Cycle:
Current flows from upper source, through D
A
and R
L
, returning to
upper source via ground. Any current through D
B
would be in
reverse direction, thus D
B
is off.
2
nd
(Negative) Half-Cycle:
Current flows from lower source, through D
B
and R
L
, returning to
lower source via ground. Any current through D
A
would be in
reverse direction, thus D
A
is off.
Introduction to Electronics 73 The Full-Wave Rectifier
v
S
(t)
v
L
(t)
i
L
(t)
+
-
v
S
(t)
v
in
(t)
+
+
-
-
v
A
(t)
v
B
(t)
D
A
D
B
R
L
Fig. 107. The full-wave rectifier (Fig. 104 repeated).
t
v
A
-2V
m
Fig. 108. Voltage across diode D
A
.
t
v
B
-2V
m
Fig. 109. Voltage across diode D
B
.
Diode Peak Inverse Voltage
When D
A
is on, D
B
is off . . . a KVL path around the “outside” loop of
the transformer secondary shows that D
B
must withstand a voltage
of 2v
S
.
When D
B
is on, D
A
is off . . . now a KVL path shows that D
B
must
withstand 2v
S
.
Thus the diode PIV rating must be 2V
m
. Diode voltage waveforms
are shown below . . .
Introduction to Electronics 74 The Bridge Rectifier
v
L
(t)
i
L
(t)
+
-
v
in
(t) v
S
(t)
D
1
+
-
D
2
D
3
D
4
Fig. 110. The bridge rectifier.
t
v
S
V
m
-V
m
Fig. 111. Input voltage to diode bridge.
t
v
L
V
m
Fig. 112. Full-wave load voltage.
t
v
1
, v
3
-V
m
Fig. 113. Diode voltage for D
1
and D
3
.
t
v
2
, v
4
-V
m
Fig. 114. Diode voltage for D
2
and D
4
.
Diode Applications - The Bridge Rectifier
The bridge rectifier is also a full-wave rectifier, but uses a diode
bridge rather than a center-tapped transformer:
Operation
1
st
(Positive) Half-Cycle:
Current flows from top end of v
S
,
through D
1
and R
L
, then via
ground through D
3
, and back to
v
S
.
2
nd
(Negative) Half-Cycle:
Current flows from bottom end
of v
S
, through D
2
and R
L
, then
via ground through D
4
, and back
to v
S
.
Peak Inverse Voltage:
In each half-cycle the OFF
diodes are directly across v
S
,
thus the diode PIV is V
m
.
Introduction to Electronics 75 Full-Wave/Bridge Rectifier Features
V C
V
fR
C
V
V fR
r
m
L
m
r L

2 2
(94)
Diode Applications - Full-Wave/Bridge Rectifier Features
Bridge Rectifier
Much cheaper transformer more than offsets the negligible cost of
two more diodes.
Full-Wave Rectifier
Archaic since vacuum tube rectifiers have largely been replaced by
semiconductor rectifiers.
Preferable only at low voltages (one less diode forward-voltage
drop), if at all.
Filtered Full-Wave and Bridge Rectifiers
Because the rectifier output voltage is “full-wave,” C discharges for
approximately only half as long as in the half-wave case.
Thus, for a given ripple voltage, only half the capacitance is
required (all other parameters being equal).
That is, a factor of 2 appears in denominator of eq. (93):
Remember though, the design equation is valid only for small V
r
.
Introduction to Electronics 76 Bipolar Junction Transistors (BJTs)
collector
n-type
n-type
emitter
p-type base
C
B
E
v
CE
v
BE
+
+
-
-
i
C
i
E
i
B
C
B
E
Fig. 115. The npn BJT representative physical
structure (left), and circuit symbol (right).
Bipolar Junction Transistors (BJTs)
Introduction
The BJT is a nonlinear, 3-terminal device based on the junction
diode. A representative structure sandwiches one semiconductor
type between layers of the opposite type. We first examine the npn
BJT:
Two junctions: collector-
base junction (CBJ);
emitter-base junction
(EBJ).
Current in one p-n
junction affects the
current in the other p-n
junction.
There are four regions of
operation:
Operating Region EBJ CBJ Feature
cutoff rev. rev. i
C
= i
E
= i
B
= 0
active fwd. rev. amplifier
saturation fwd. fwd. v
CE
nearly zero
inverse rev. fwd. limited use
We’re most interested in the active region, but will have to deal with
cutoff and saturation, as well.
Discussion of inverse region operation is left for another time.
Introduction to Electronics 77 Bipolar Junction Transistors (BJTs)
C
B
E
n
p
n
Fig. 116. Active-region
BJT currents.
Qualitative Description of BJT Active-Region Operation
G Emitter region is heavily doped . . .lots of electrons available
to conduct current.
G Base region very lightly doped and very narrow . . .very few
holes available to conduct current.
G Rev-biased CBJ collector positive w.r.t base. ⇒
G Fwd-biased EBJ base positive w.r.t emitter. ⇒
G Emitter current, i
E
, consists mostly of electrons being injected
into base region; because the base is lightly doped, i
B
is small.
Some of the injected electrons combine with holes in base
region.
Most of the electrons travel across the narrow base and are
attracted to the positive collector voltage, creating a collector
current!!!
G The relative current magnitudes are
indicated by the arrow thicknesses in the
figure.
G Because i
B
is so small, a small change in
base current can cause a large change in
collector current - this is how we get this
device to amplify!!!
Introduction to Electronics 78 Bipolar Junction Transistors (BJTs)
v
CE
v
BE
+
+
-
-
i
C
i
E
i
B
C
B
E
Fig. 117. Npn BJT
schematic symbol.
i I
v
V
E ES
BE
T

|
(
'
`
J
J

]
]
]
exp 1 (95)
i i i
E B C
+ (96)
α
i
i
C
E
(97)
Quantitative Description of BJT Active-Region Operation
The emitter-base junction (EBJ) is a diode and
is governed by the Shockley eqn.:
where, I
ES
ranges from pA to fA
and n is usually 1 ≈
Also, from KCL:
In the active region (only!!!) i
C
is a fixed % of i
E
, which is dependent
on the manufacturing process.
We assign the symbol α to that ratio, thus:
Ideally, we would like α = 1. Usually, α falls between 0.9 and 1.0,
with 0.99 being typical.
Remember!!! Eqs. (95) and (96) apply always.
Eq. (97) applies only in the active region.
Introduction to Electronics 79 Bipolar Junction Transistors (BJTs)
i i I
v
V
C E ES
BE
T

|
(
'
`
J
J

]
]
]
α α exp 1 (98)
i I
v
V
C S
BE
T

|
(
'
`
J
J
exp (99)
( )
i i i i i i i i
E C B E E B B E
+ ⇒ + ⇒ − α α 1 (100)
( )
i
i
i
i
C
B
E
E





α
α
α
α
β
1 1
(101)
α
β
β

+1
(102)
i i
C B
β (103)
From eqs. (95) and (97) we have:
and for a forward-biased EBJ, we may approximate:
where the scale current, I
S
= αI
ES
.
Also, from eqs. (96) and (97) we have:
thus
Solving the right-hand half of eq. (101) for α:
For α = 0.99, we have β = 100. Rearranging eq. (101) gives:
Thus, small changes in i
B
produce large changes in i
C
, so again we
see that the BJT can act as an amplifier!!!
Introduction to Electronics 80 BJT Common-Emitter Characteristics
v
BE
+
-
v
CE
+
-
i
B
i
C
+
+
-
-
Fig. 118.Circuit for measuring
BJT characteristics.
Fig. 119. Typical input characteristic of an npn BJT.
BJT Common-Emitter Characteristics
Introduction
We use the term common-emitter
characteristics because the emitter is
common to both voltage sources.
The figure at left represents only how we
might envision measuring these
characteristics. In practice we would
never connect sources to any device
without current-limiting resistors in
series!!!
Input Characteristic
First, we measure the i
B
- v
BE
relationship (with v
CE
fixed). Not
surprisingly, we see a typical diode curve:
This is called the input characteristic because the base-emitter will
become the input terminals of our amplifier.
Introduction to Electronics 81 BJT Common-Emitter Characteristics
v
BE
+
-
v
CE
+
-
i
B
i
C
+
+
-
-
Fig. 120. Circuit for
measuring BJT characteristics
(Fig. 118 repeated).
Fig. 121. Typical output characteristics of an npn BJT.
Output Characteristics
Next, we measure a family of i
C
- v
CE
curves for various values of
base current:
Active Region:
Recall that the active region requires that the EBJ be forward-
biased, and that the CBJ be reverse-biased.
A forward-biased EBJ means that v
BE
0.7 V. Thus, the CBJ will ≈
be reverse-biased as long as v
CE
> 0.7 V.
Note that i
C
and i
B
are related by the ratio β, as long as the BJT is
in the active region.
We can also identify the cutoff and saturation regions . . .
Introduction to Electronics 82 BJT Common-Emitter Characteristics
Fig. 122. BJT output characteristics with cutoff and saturation
regions identified.
Cutoff:
The EBJ is not forward-biased (sufficiently) if i
B
= 0. Thus the cutoff
region is the particular curve for i
B
= 0 (i.e., the horizontal axis).
Saturation:
When the EBJ is forward-biased, v
BE
0.7 V. Then, the CBJ is ≈
reverse-biased for any v
CE
> 0.7 V. Thus, the saturation region lies
to the left of v
CE
= 0.7 V.
Note that the CBJ must become forward-biased by 0.4 V to 0.5 V
before the i
C
= βi
B
relationship disappears, just as a diode must be
forward-biased by 0.4 V to 0.5 V before appreciable forwardcurrent
flows.
Introduction to Electronics 83 The pnp BJT
collector
p-type
p-type
emitter
n-type base
C
B
E
v
EC
v
EB
+
+
-
-
i
C
i
E
i
B
C
B
E
Fig. 123. A pnp BJT and its schematic symbol. Note
that the current and voltage references have been
reversed.
i i i i I
v
V
E B C E ES
EB
T
+
|
(
'
`
J
J −

]
]
]
and exp 1
(104)
i i i i i I
v
V
C E C B C S
EB
T

|
(
'
`
J
J
α β , exp and (105)
The pnp BJT
We get the same behavior with an n-type base sandwiched
between a p-type collector and a p-type emitter:
Now current in a fwd.
biased EBJ flows in the
opposite direction . . .
. . . i
C
and i
E
resulting
from acti ve regi on
operation also flow in the
opposite direction.
Note that the voltage and
current references are
reversed.
But the equations have
the same appearance:
In general,
And for the active region in particular,
where, the latter equation is the approximation for a forward-biased
EBJ.
Introduction to Electronics 84 The pnp BJT
Fig. 124. Input characteristic of a pnp BJT.
Fig. 125. Output characteristics of a pnp BJT.
Because the voltage and current references are reversed, the input
and output characteristics appear the same also:
Introduction to Electronics 85 BJT Characteristics - Secondary Effects
Fig. 126. BJT output characteristics illustrating Early voltage.
BJT Characteristics - Secondary Effects
The characteristics of real BJTs are somewhat more complicated
than what has been presented here (of course!!!).
One secondary effect you need to be aware of . . .
G Output characteristics are not horizontal in the active region,
but have an upward slope . . .
G This is due to the Early effect, a change in base width as v
CE
changes (also called base width modulation) . . .
G Extensions of the actual output characteristics intersect at the
Early voltage, V
A
. . .
G Typical value of V
A
is 50 V to 100 V.
Other secondary effects will be described as needed.
Introduction to Electronics 86 The n-Channel Junction FET
n-type
Drain
Gate
Source
p v
DS
v
GS
+
+
-
-
i
D
i
D
i
G
=

0
D
G
S
channel
p
Fig. 127. The n-channel JFET
representative physical structure (left) and schematic
symbol (right).
n
Drain
Gate
Source
p p
Fig. 128. Depletion region
depicted for v
GS
= 0, v
DS
= 0.
The n-Channel Junction FET (JFET)
The field-effect transistor, or FET, is also a 3-terminal device, but
it is constructed, and functions, somewhat differently than the BJT.
There are several types. We begin with the junction FET (JFET),
specifically, the n-channel JFET.
Description of Operation
The p-n junction is a
typical diode . . .
Holes move from p-type
into n-type . . .
Electrons move from n-
type into p-type . . .
Region near the p-n
junction is left without
any available carriers -
depletion region
The depletion region is shown at left
for zero applied voltage (called zero
bias). . .
Carriers are still present in the n-type
channel . . .
Current could flow between drain and
source (if v
DS
0) . . . ≠
Channel has relatively low resistance.
Introduction to Electronics 87 The n-Channel Junction FET
n
Drain
Gate
Source
p p
v
GS
<

0
+
-
Fig. 129.
Depletion region for negative
v
GS
(reverse bias).
n
Drain
Gate
Source
p p
v
GS
=

V
P
+
-
Fig. 130. Depletion region at
pinch-off (v
GS
= V
P
).
Fig. 131. FET i-v curves for small
v
DS
.
As the reverse bias increases across
the p-n junction, the depletion region
width increases,
Because negative voltage at the Gate
pulls holes away from junction,
And positive voltage at the Source
pulls electrons away from junction.
Thus, the channel becomes narrower,
and the channel resistance increases.
With sufficient reverse bias the
depletion region pinches-off the entire
channel:
v
GS
= V
P
, pinch-off voltage
The channel resistance becomes
infinite; current flow impossible for
any v
DS
(less than breakdown).
Typical values: -5 < V
P
< -2
Thus, the FET looks like a voltage-
controlled resistance at small values
of v
DS
.
This region of FET operation is called
the voltage-controlled resistance, or
triode, region.
Introduction to Electronics 88 The n-Channel Junction FET
n
Drain
Gate
Source
p p
0

<

v
DS
<

|V
P
|
+
-
Fig. 132. Asymmetrical depletion
region as v
DS
increases.
n
Drain
Gate
Source
p p
v
DS
|V
P
|
+
-
Fig. 133.Pinch-off at drain end for
v
DS
= V
P
.
Fig. 134. N-channel JFET output
characteristics (2N3819).
Now, as v
DS
increases, the depletion region becomes asymmetrical:
Reverse bias is greater at the drain
end, so the depletion region is greater
at the drain end.
Thus the channel becomes more
restricted and, for fixed v
GS
, i-v curves
become flatter (i.e., more horizontal).
For v
DS
= |V
P
| channel becomes
pinched-off only at drain end.
Carriers drift across pinched-off region
under influence of the E field.
The rate of drift, and therefore the
drain current flow, is dependent on
width of entire channel (i.e., on v
GS
),
but independent of v
DS
!!!
As v
GS
changes, the curves
become horizontal at different
values of drain current.
Thus, we have a device with
the output characteristics at
left.
Note that they are very similar
to BJT curves, though the
physical operation is very
different.
Introduction to Electronics 89 The n-Channel Junction FET
i
D
0 (106)
( )
[ ]
i K v V v v
D GS P DS DS
− − 2
2
(107)
( )
i K v V v v
D GS P DS DS
− 2 , for small (108)
( )
R
v
i K v V
channel
DS
D GS P
≈ ≈

1
2
(109)
( )
i K v V
D GS P

2
(110)
Equations Governing n-Channel JFET Operation
Cutoff Region:
The FET is in cutoff for v
GS
V
P
, and for any v
DS
: ≤
Triode Region:
The FET is in the triode region for 0 > v
GS
> V
P
, and v
GD
> V
P
:
where K has units of amperes per square volt, A/V
2
For very small values of v
DS
, the v
DS
2
term in the above eguation is
negligible:
and the channel resistance is approximately given by:
Pinch-Off Region:
The FET is in the pinch-off region for 0 > v
GS
> V
P
, and v
GD
< V
P
:
The pinch-off region (also called the saturation region) is most
useful for amplification.
Note that v
GS
is never allowed to forward bias the p-n junction !!!
Introduction to Electronics 90 The n-Channel Junction FET
v V v v V v V v
GD P GS DS P GS P DS
⇒ − ⇒ − (111)
Fig. 135. 2N3819 n-channel JFET output
characteristics showing the triode - pinch-off
boundary.
v V
i
K
GS P
D

(112)
v
i
K
i Kv
DS
D
D DS

2
(113)
The Triode - Pinch-Off Boundary
We know pinch-off just occurs at the drain end when:
But from eq. (110)
Combining eqs. (111) and (112) gives the boundary:
The output characteristics exhibit a breakdown voltage for
sufficient magnitude of v
DS
.
“Real” output characteristics also have an upward slope and
can be characterized with an “Early” voltage, V
A
.
Introduction to Electronics 91 The n-Channel Junction FET
Fig. 136. 2N3819 n-channel JFET transfer
characteristic.
( )
i K v V
D GS P

2
(114)
K
I
V
DSS
P

2
(115)
The Transfer Characteristic
Because the gate-channel p-n junction is reversed biased always,
the input i-v characteristic of a FET is trivial.
However, the pinch-off region equation (110), repeated below,
gives rise to a transfer characteristic:
I
DSS
is the zero-gate-voltage drain current. Substituting i
D
= I
DSS
and
v
GS
= 0 into eq. (114) gives a relationship between K and I
DSS
:
Introduction to Electronics 92 Metal-Oxide-Semiconductor FETs (MOSFETs)
p-type substrate (body)
n n
metal
SiO
2
channel
S D G
B
S
D
G B
Fig. 137. The n-channel depletion MOSFET representative
physical structure (left) and schematic symbol (right).
Metal-Oxide-Semiconductor FETs (MOSFETs)
MOSFETs are constructed quite differently than JFETs, but their
electrical behavior is extremely similar . . .
The n-Channel Depletion MOSFET
The depletion MOSFET is built horizontally on a p-type substrate:
G n-type wells, used for the source and drain, are connected by
a very thin n-type channel . . .
G The gate is a metallized layer insulated from the channel by a
thin oxide layer . . .
G Negative gate voltages repel electrons from the channel,
causing the channel to narrow . . .
When v
GS
is sufficiently negative (v
GS
= V
P
), the channel is
pinched-off . . .
G Positive gate voltages attract electrons from the substrate,
causing the channel to widen . . .
Introduction to Electronics 93 Metal-Oxide-Semiconductor FETs (MOSFETs)
p-type substrate (body)
n n
metal
SiO
2
S D G
B
S
D
G B
Fig. 138. The n-channel enhancement MOSFET physical
structure (left) and schematic symbol (right).
The n-Channel Enhancement MOSFET
The MOSFET is built horizontally on a p-type substrate. . .
G n-type wells, used for the source and drain, are not connected
by a channel at all . . .
G The gate is a metallized layer insulated from the channel by a
thin oxide layer . . .
G Positive gate voltages attract electrons from the substrate . . .
When v
GS
is sufficiently positive, i.e., greater than the threshold
voltage, V
TH
, an n-type channel is formed (i.e., a channel is
enhanced) . . .
V
TH
functions exactly like a “positive-valued V
P

Introduction to Electronics 94 Comparison of n-Channel FETs
i
D
v
GS
V
P
I
DSS
Fig. 139. Transfer char.,
n-channel JFET.
i
D
v
GS
V
P
I
DSS
Fig. 140. Transfer char., n-
channel depletion MOSFET.
i
D
v
GS
V
TH
Fig. 141. Transfer char., n-
channel enhancement MOSFET.
( )
i K v V
D GS P

2
(116)
( )
i K v V
D GS P

2
(117)
( )
i K v V
D GS TH

2
(118)
Comparison of n-Channel FETs
G The n-channel JFET can only have
negative gate voltages . . .
p-n junction must remain reversed
biased . . .
Actual device can operate with v
GS
slightly positive, approx. 0.5 V max.
G The n-channel depletion MOSFET
can have either negative or positive
gate voltages . . .
Gate current prevented by oxide
insulating layer in either case.
G The n-channel enhancement
MOSFET can have only positive
gate voltages . . .
Gate current prevented by oxide
insulating layer . . .
Only the notation changes in the
equation:
Introduction to Electronics 95 Comparison of n-Channel FETs
Fig. 142. Typical output characteristics,
n-channel JFET.
Fig. 143. Typical output characteristics,
n-channel depletion MOSFET.
Fig. 144. Typical output characteristics,
n-channel enhancement MOSFET.
n-channel FET output characteristics differ only in v
GS
values:
Introduction to Electronics 96 p-Channel JFETs and MOSFETs
v
DS
v
GS
+
+
-
-
i
D
i
D
i
G
=

0
D
G
S
S
D
G B
i
D
i
G
=

0
v
GS
+
-
S
D
G B
i
D
i
G
=

0
v
GS
+
-
Fig. 145.Schematic symbols for p-channel FETs.
From left to right: JFET, depletion MOSFET, enhancement MOSFET.
p-Channel JFETs and MOSFETs
By switching n-type semiconductor for p-type, and vice versa, we
create p-channel FETs . . .
The physical principles of operation are directly analogous . . .
Actual current directions and voltage polarities are reversed from
the corresponding n-channel devices . . .
Schematic symbols simply have the arrows reversed (because
arrow indicates direction of forward current in the corresponding p-n
junction):
Note the same reference directions and polarities for p-channel
devices as we used for n-channel devices . . .
i-v curves for p-channel FETs are identical to n-channel curves,
except algebraic signs are reversed.
Introduction to Electronics 97 p-Channel JFETs and MOSFETs
V
TH
V
P
n-ch. JFET
n-ch. depl. MOSFET
n-ch. enh. MOSFET
V
P
V
TH
p-ch. JFET
p-ch. depl. MOSFET
p-ch. enh. MOSFET
Fig. 146. Comparison of p-channel and n-channel transfer
characteristics.
Fig. 147. Typical p-channel transfer
characteristic.
Fig. 148. Typical p-channel transfer
characteristic.
For comparing transfer characteristics on p-channel and n-channel
devices, the following approach is helpful:
But more often you’ll see negative signs used to labels axes, or
values along the axes, such as these examples:
Introduction to Electronics 98 p-Channel JFETs and MOSFETs
Fig. 149. Typical p-channel output
characteristic.
Fig. 150. Typical p-channel output
characteristic.
i
D
0 (119)
( )
[ ]
i K v V v v
D GS P DS DS
− − 2
2
(120)
( )
i K v V
D GS P

2
(121)
Output characteristics for p-channel devices are handled in much
the same way:
Equations governing p-channel operation are exactly the same as
those for n-channel operation. Replacing V
P
with V
TH
as necessary,
they are:
Cutoff Region:
(in cutoff for v
GS
V
P
, and for any v
DS
) ≥
Triode Region:
(for v
GS
< V
P
, and v
GD
< V
P
)
where K is negative, and has units of -A/V
2
Pinch-Off Region:
(for v
GS
< V
P
, and v
GD
> V
P
)
Introduction to Electronics 99 Other FET Considerations
D
G B
S
Fig. 151. Zener-diode gate
protection of a MOSFET.
D
G
S
Fig. 152. Normal
MOSFET body-
source connection.
Other FET Considerations
FET Gate Protection
The gate-to-channel impedance (especially in MOSFETs) can
exceed 1 GΩ !!!
To protect the thin gate oxide layer, zeners are often used:
Zeners can be used externally, but are
usually incorporated right inside the FET
case.
Many FET device types available with or
without zener protection.
Zener protection adds capacitance, which
reduces FET performance at high
frequencies.
The Body Terminal
In some (rare) applications the body terminal
of MOSFETs is used to influence the drain
current.
Usually the body is connected to the source
terminal or a more negative voltage (to
prevent inadvertently forward-biasing the
channel-body parasitic diode).
Introduction to Electronics 100 Basic BJT Amplifier Structure
++
+
+
-
-
R
B
R
C
V
CC
V
BB
v
in
+
-
+
-
+
-
v
CE
v
BE
i
C
i
B
Fig. 153. Basic BJT amplifier structure.
V v i R v
BB in B B BE
+ +
(122)
i
B
v
BE
V
BB
V
BB
/R
B
V
BB
+v
in max
V
BB
-v
in max
i
B max
I
BQ
i
B min
Q
Fig. 154. Load-line analysis around base-emitter loop.
V i R v
CC C C CE
+ (123)
Basic BJT Amplifier Structure
Circuit Diagram and Equations
The basic BJT amplifier takes the form
shown:
KVL equation around B-E loop:
KVL equation around C-E loop:
Load-Line Analysis - Input Side
Remember that the base-emitter is a diode.
The Thevenin resistance is constant, voltage varies with time, but
the Thevenin. Thus, the load line has constant slope (-1/R
B
), and
moves with time.
Introduction to Electronics 101 Basic BJT Amplifier Structure
i
B
v
BE
V
BB
V
BB
/R
B
V
BB
+v
in max
V
BB
-v
in max
i
B max
I
BQ
i
B min
Q
Fig. 155. Load-line analysis around base-emitter loop
(Fig. 154 repeated).
G The load line shown in red for v
in
= 0.
When v
in
= 0, only dc remains in the circuit.
This i
B
, v
BE
operating pt. is called the quiescent pt.
The Q-point is given special notation: I
BQ
, V
BEQ
G Maximum excursion of load line with v
in
is shown in blue.
G Minimum excursion of load line with v
in
is shown in green.
G Thus, as v
in
varies through its cycle, base current varies from
i
B max
to i
B min
.
The base-emitter voltage varies also, from v
BE max
to v
BE min
,
though we are less interested in v
BE
at the moment.
Introduction to Electronics 102 Basic BJT Amplifier Structure
+ +
+
+
-
-
R
B
R
C
V
CC
V
BB
v
in
+
-
+
-
+
-
v
CE
v
BE
i
C
i
B
Fig. 156. Basic BJT amplifier structure
(Fig. 153 repeated).
Fig. 157. Amplifier load line on BJT output characteristics.
Load-Line Analysis - Output Side
Returning to the circuit, observe
that V
CC
and R
C
form a Thevenin
equivalent, with output variables
i
C
and v
CE
.
Thus we can plot this load line on
t h e t r a n s i s t o r o u t p u t
characteristics!!!
Because neither V
CC
nor R
C
are
time-varying, this load line is
fixed!!!
Introduction to Electronics 103 Basic BJT Amplifier Structure
Fig. 158. Amplifier load line on BJT output characteristics
(Fig. 157 repeated).
G The collector-emitter operating point is given by the
intersection of the load line and the appropriate base current
curve . . .
when v
in
= 0, i
B
= I
BQ
, and the quiescent pt. is I
CQ
, V
CEQ
at v
in max
, i
B
= i
B max
, and the operating pt. is i
C max
, v
CE min
at v
in min
, i
B
= i
B min
, and the operating pt. is i
C min
, v
CE max
G If the total change in v
CE
is greater than total change in v
in
, we
have an amplifier !!!
Introduction to Electronics 104 Basic BJT Amplifier Structure
++
+
+
-
-
R
B
=

10 kΩ
V
CC
=

10 V
V
BB
=

1 V
v
in
=

0.1 sin ωt V
+
-
+
-
+
-
v
CE
v
BE
i
C
i
B
R
C
=

1 kΩ
Q
1
2N2222
Fig. 159. Example circuit illustrating basic amplifier
structure.
Fig. 160. PSpice-simulated 2N2222 input characteristic.
A Numerical Example
Let’s look at a PSpice simulation of realistic circuit:
First we generate the input characteristic and draw the appropriate
base-emitter circuit load lines:
Introduction to Electronics 105 Basic BJT Amplifier Structure
Fig. 161. 2N2222 output characteristics, with curves for base currents of (from
bottom to top) 4 µA, 13 µA, 22 µA, 31 µA, 40 µA, and 49 µA.
A
v
v
!!!
v
CE
in



2.95V - 6.11V
V 0 2
158
.
. (124)
Using the cursor tool in the PSpice software plotting package, we
determine:
i
B min
= 22 µA I
BQ
= 31 µA i
B max
= 40 µA
Next we generate the output characteristics and superimpose the
collector-emitter circuit load line:
The resulting collector-emitter voltages are:
v
CE min
= 2.95 V V
CEQ
= 4.50 V v
CE max
= 6.11 V
Finally, using peak-to-peak values we have a voltage gain of:
Introduction to Electronics 106 Basic BJT Amplifier Structure
Fig. 162. Input waveform for the circuit of Fig. 159.
Fig. 163. Output (collector) waveform for the circuit of Fig. 159.
Of course, PSpice can give us the waveforms directly (and can
even give us gain, if we desire):
Introduction to Electronics 107 Basic FET Amplifier Structure
+
+
-
V
DD
=

15 V
V
BB
=

-1 V
v
in
=

0.5 sin ωt V
+
-
+
-
+
-
v
DS
v
GS
i
D
R
D
=

1 kΩ
J
1
2N3819
Fig. 164. Basic FET amplifier structure.
V v v
GG in GS
+ (125)
V i R v
DD D D DS
+ (126)
Basic FET Amplifier Structure
The basic FET amplifier takes the same form as the BJT amplifier.
Let’s go right to a PSpice simulation example using a 2N3819 n-
channel JFET:
Now, KVL around the gate-source loop gives:
while KVL around the drain-source loop gives the familiar result:
Because i
G
= 0, the FET has no input characteristic, but we can plot
the transfer characteristic, and use eq. (125) to add the appropriate
load lines.
In this case, the load line locating the Q point, i.e., the line for
v
in
= 0, is called the bias line:
Introduction to Electronics 108 Basic FET Amplifier Structure
Fig. 165. PSpice-generated 2N3819 transfer characteristic showing the bias line,
and lines for v
GS min
and v
GS max
.
v i
GS D
min min
. . − ⇒ 15 300 V mA (127)
V I
GSQ DQ
− ⇒ 10 530 . . V mA (128)
v i
GS D
max max
. . − ⇒ 05 8 22 V mA (129)
From the transfer characteristic, the indicated gate-source voltages
correspond to the following drain current values:
Note, however, that we could have gone directly to the output
characteristics, as the parameter for the family of output curves is
v
GS
:
Introduction to Electronics 109 Basic FET Amplifier Structure
Fig. 166. 2N3819 output characteristics, with curves for gate-source voltages of
(from bottom to top) -3 V, -2.5 V, -2 V, -1.5 V, -1 V, -0.5 V, and 0 V.
v v
GS DS
min max
. . − ⇒ 15 120 V V (130)
V V
GSQ DSQ
− ⇒ 10 970 . . V V (131)
v v
GS DS
max min
. . − ⇒ 05 678 V V (132)
A
v
v
!!!
v
DS
GS



6.78V - 12.0V
1V
5 22 . (133)
From the output characteristics and the drain-source load line, the
indicated gate-source voltages correspond to the following drain-source
voltage values:
Thus, using peak-to-peak values, we have a voltage gain of:
Introduction to Electronics 110 Amplifier Distortion
Fig. 167. Output (drain) waveform for the FET amplifier example.
Amplifier Distortion
Let’s look at the output waveform (v
DS
) of the previous example:
Can you discern that the output sinusoid is distorted ?
The positive half-cycle has an amplitude of
12.0 V - 9.70 V = 2.30 V
while the negative half cycle has an amplitude of
9.70 V - 6.78 V = 2.92 V
This distortion results from the nonlinear (2
nd
-order) transfer
characteristic, the effects of which also can be seen in the
nonuniform spacing of the family of output characteristics . . .
BJT’s are also nonlinear, though less prominently so . . .
Introduction to Electronics 111 Amplifier Distortion
+
+
-
V
DD
=

15 V
V
BB
=

-1.5 V
v
in
=

1.5 sin ωt V
+
-
+
-
+
-
v
DS
v
GS
i
D
R
D
=

1.3 kΩ
J
1
2N3819
Fig. 168. Slight changes to the FET amplifier example to
illustrate nonlinear distortion.
Fig. 169. Severely distorted output waveform resulting from operation in the
cutoff region (top) and the triode region (bottom).
Distortion also results if the instantaneous operating point along the
output-side load line ventures too close to the saturation or cutoff
regions for the BJT (the triode or cutoff regions for the FET), as the
following example illustrates:
Introduction to Electronics 112 Biasing and Bias Stability
Biasing and Bias Stability
Notice from the previous load line examples:
G The instantaneous operating point moves with instantaneous
signal voltage.
Linearity is best when operating point stays within the active
(BJTs) or pinch-off (FETs) regions.
G The quiescent point is the dc (zero signal) operating point.
It lies near the “middle” of the range of instantaneous
operating points.
This dc operating point is required if linear amplification is to
be achieved !!!
G The dc operating point (the quiescent point, the Q point, the
bias point) obviously requires that dc sources be in the circuit.
G The process of establishing an appropriate bias point is called
biasing the transistor.
G Given a specific type of transistor, biasing should result in the
same or nearly the same bias point in every transistor of that
type . . . this is called bias stability.
Bias stability can also mean stability with temperature, with
aging, etc.
We study BJT and FET bias circuits in the following pages . . .
Introduction to Electronics 113 Biasing BJTs - The Fixed Bias Circuit
R
B
R
C
V
CC
i
C
+
-
v
CE
Fig. 170. BJT fixed bias circuit.
I
V V
R
B
CC BE
B



15
200
715
V - 0.7V
k
A

. µ (134)
I I V V I R
C B CE CC C C
⇒ − β 715 785 . . mA V (135)
I
V V
R
B
CC BE
B



15
200
715
V - 0.7V
k
A

. µ (136)
I I V V I R
C B CE CC C C
⇒ − − β 215 6 45 . . mA V (137)
Biasing BJTs - The Fixed Bias Circuit
Example
We let V
CC
= 15 V,
R
B
= 200 kΩ, and R
C
= 1 kΩ
β varies from 100 to 300
To perform the analysis, we
assume that operation is in the
active region, and that V
BE
= 0.7 V.
For β = 100:
Q. Active region??? A. V
CE
> 0.7 V and I
B
> 0 Yes!!! ⇒
For β = 300:
Q. Active region? A. V
CE
< 0.7 V No!!! Saturation!!! ⇒
Thus our calculations for β = 300 are incorrect, but more importantly
we conclude that fixed bias provides extremely poor bias stability!!!
Introduction to Electronics 114 Biasing BJTs - The Constant Base Bias Circuit
R
E
R
C
V
CC
i
C
+
-
v
CE
+
V
BB
-
Fig. 171. BJT constant base bias
circuit.
I
V V
R
I I
E
BB BE
E
C E



+
215
1
213 . . mA mA
β
β
(138)
V V I R I R
CE CC C C E E
− − 6 44 . V (139)
I
V V
R
I I
E
BB BE
E
C E



+
215
1
214 . . mA mA
β
β
(140)
V V I R I R
CE CC C C E E
− − 6 41 . V (141)
Biasing BJTs - The Constant Base Bias Circuit
Example
Now we let V
CC
= 15 V and V
BB
= 5 V
R
C
= 2 kΩ and R
E
= 2 kΩ
β varies from 100 to 300
And we assume operation in active
region and V
BE
= 0.7 V, as before.
Though not explicitly shown here, the
active-region assumption must always
be verified.
For β = 100:
For β = 300:
Thus we conclude that constant base bias provides excellent bias
stability!!! Unfortunately, we can’t easily couple a signal into this
circuit, so it is not as useful as it may first appear.
Introduction to Electronics 115 Biasing BJTs - The Four-Resistor Bias Circuit
R
1
R
2
R
C
R
E
V
CC
Fig. 172. The four-resistor bias
circuit.
R
1
R
2
R
C
R
E
V
CC
V
CC
+ +
- -
Fig. 173. Equivalent after “trick” with supply voltage.
R
B
R
C
R
E
V
CC
V
BB
+
+
-
-
Fig. 174. Final equivalent after using Thevenin’s
Theorem on base divider.
Biasing BJTs - The Four-Resistor Bias Circuit
Introduction
This combines features of fixed bias and constant base bias, but it
takes a circuit-analysis “trick” to see that:
Introduction to Electronics 116 Biasing BJTs - The Four-Resistor Bias Circuit
R
B
R
C
R
E
V
CC
V
BB
+
+
-
-
Fig. 175. Four-resistor bias circuit equivalent
(Fig. 174 repeated).
V I R V I R
BB B B BE E E
+ + (142)
( )
V I R V I R
BB B B BE B E
+ + + β 1 (143)
( )
I
V V
R R
B
BB BE
B E


+ + β 1
(144)
( )
( )
β
β
β
I I
V V
R R
B C
BB BE
B E


+ +1
(145)
V V I R I R
CE CC C C E E
− − (146)
Circuit Analysis
Analysis begins with KVL around b-e loop:
But in the active region I
E
= (β + 1)I
B
:
Now we solve for I
B
:
And multiply both sides by β :
We complete the analysis with KVL around c-e loop:
Introduction to Electronics 117 Biasing BJTs - The Four-Resistor Bias Circuit
( )
( )
β
β
β
I I
V V
R R
B C
BB BE
B E


+ +1
(147)
Bias Stability
Bias stability can be illustrated with eq. (145), repeated below:
Notice that if R
E
= 0 we have fixed bias, while if R
B
= 0 we have
constant base bias.
To maximize bias stability:
G We minimize variations in I
C
with changes in β . . .
By letting (β + 1)R
E
>> R
B
,
Because then β and (β + 1) nearly cancel in eq. (147).
Rule of Thumb: let (β + 1)R
E
10 R
B


|
|
|
|
|
β 100
Equivalent Rule: let I I
R B
2
10 ≈
max
G We also minimize variations in I
C
with changes in V
BE
. . .
By letting V
BB
>> V
BE
.
Rule of Thumb: let V V V V
R CE R CC
C E
≈ ≈ ≈
1
3
Because if V
BE
and I
B
are small. V V
R BB
E

Introduction to Electronics 118 Biasing BJTs - The Four-Resistor Bias Circuit
R
C
R
2
5 kΩ
15 V
1 kΩ
R
1
R
E
10 kΩ 1 kΩ
Fig. 176. Example circuit.
R
B
= 3.3 kΩ
R
C
R
E
+
+
-
-
1 kΩ
1 kΩ
5 V
15 V
Fig. 177. Equivalent circuit.
( )
I
V V
R R
I I
B
BB BE
B E
C B


+ +

β
µ β
1
412 412 . . A mA
(148)
⇒ ⇒ − − I
I
V V I R I R
E
C
CE CC C C E E
α
416 672 . . mA V
(149)
( )
I
V V
R R
I I
B
BB BE
B E
C B


+ +

β
µ β
1
141 4 24 . . A mA
(150)
⇒ ⇒ − − I
I
V V I R I R
E
C
CE CC C C E E
α
4 25 650 . . mA V
(151)
Example
For β = 100 (and V
BE
= 0.7 V):
For β = 300:
Thus we have achieved a reasonable degree of bias stability.
Introduction to Electronics 119 Biasing FETs - The Fixed Bias Circuit
V
DD
V
GG
R
D
R
G
i
D
v
DS
v
GS
+
+
-
-
+
-
Fig. 178. FET fixed bias circuit.
.i
D
v
GS
V
GSQ
I
DQ
I
DQ
High-current device
Low-current device
Fig. 179. Graphical illustration of fixed bias using an
n-channel JFET.
Biasing FETs - The Fixed Bias Circuit
Just as the BJT parameters b and
V
BE
vary from device to device, so
do the FET parameters K and V
P
(or
V
TH
).
Thus, bias circuits must provide bias
stability, i.e., a reasonably constant
I
DQ
.
We look first at the fixed bias circuit
shown at left, and note that
V
GG
= v
GSQ
.
For an n-channel JFET, note
that V
GG
must be < 0, which
requires a second power
supply.
For an n-ch. depl. MOSFET,
V
GG
can be either positive or
negative.
For an n-ch. enh. MOSFET,
V
GG
must be > 0
Finally, note the complete lack of bias stability. Fixed bias is not
practical!!!
Introduction to Electronics 120 Biasing FETs - The Self Bias Circuit
V
DD
R
D
R
G
v
DS
v
GS
+
+
-
-
R
S
i
D
R
S
i
D
+
-
Fig. 180. FET self-bias circuit.
i
D
v
GS
I
DQ
I
DQ
High-current device
Low-current device
Bias line
v
GS
= -R
S
i
D
Fig. 181. Graphical solution to self-bias circuit,
showing improved stability.
v i R
GS D S
− (152)
( )
i K v V
D GS P

2
(153)
Biasing FETs - The Self Bias Circuit
From a KVL equation around the
gate-source loop we obtain the bias
line:
And, assuming operation in the
pinch-off region:
Solving simultaneously provides the
Q point. A graphical solution is
shown, below left.
Note the improvement in bias
stability over a fixed bias approach.
Note also that V
GSQ
can only be
negative. Thus, self-bias is not
sui t abl e f or enhancement
MOSFETs!
An analytical solution requires the quadratic formula (though a good
guess often works) - the higher current solution is invalid (why?).
Introduction to Electronics 121 Biasing FETs - The Fixed + Self Bias Circuit
V
DD
R
2
R
S
R
D
R
1
Fig. 182. Fixed + self-bias
circuit for FETs.
V
DD
R
D
R
G
v
DS
+
-
R
S
i
D
V
G
+
-
Fig. 183. Equivalent circuit after using
Thevenin’s Theorem on gate divider.
v V i R
GS G D S
− (154)
( )
i K v V
D GS P

2
(155)
Biasing FETs - The Fixed + Self Bias Circuit
This is just the four-resistor bias circuit with a different name!!!
A KVL equation around gate-source loop provides the bias line:
And, as usual, assuming operation in the pinch-off region:
Simultaneous solution provides Q-point - see next page.
Introduction to Electronics 122 Biasing FETs - The Fixed + Self Bias Circuit
i
D
v
GS
V
G
I
DQ
I
DQ
High-current device
Low-current device
Bias line
v
GS
= V
G
- R
S
i
D
Intercept at
V
G
/ R
S
Fig. 184. Graphical solution to fixed + self bias circuit.
G Note that bias stability can be much improved over that
obtained with self-bias.
The degree of stability increases as V
G
or R
S
increases.
Rule of thumb: let V V V V
R DS R DD
D S

1
3
G Other considerations:
Because I
G
= 0, R
1
and R
2
can be very large (e.g., MΩ).
Because V
G
can be > 0, this circuit can be used with any FET,
including enhancement MOSFETs.
Introduction to Electronics 123 Design of Discrete BJT Bias Circuits
i
C
v
CE
V
CC
R
C
+

R
E
V
CC
P
MAX
=

i
C
v
CE
Q-point area
Fig. 185. Typical BJT output characteristics.
Design of Discrete BJT Bias Circuits
In the next few sections we shall look at biasing circuits in
somewhat greater detail.
Concepts of Biasing
We want bias stability because we generally desire to keep the Q-
point within some region:
In addition to voltage gain, we must consider and compromise
among the following:
G Signal Swing: If V
CEQ
is too small the device will saturate. If
I
CQ
is too small the device will cut off.
G Power Dissipation: V
CEQ
and I
CQ
must be below certain limits.
G Input Impedance: We can increase Z
in
with high R values.
G Output Impedance: We can decrease Z
out
with low R values.
G Bias Stability: We can increase stability with low R values.
G Frequency Response: A higher V
CEQ
lowers junction C and
improves response. A specific I
CQ
maximizes f
t
.
Introduction to Electronics 124 Design of Discrete BJT Bias Circuits
R
E
R
C
V
CC
R
1
R
2
i
B
i
2
i
1
i
C
i
E
-
v
E
+
-
v
B
+
Fig. 186. Four-resistor bias
circuit, revisited.
( )
( )
I
V V
R R
CQ
BB BEQ
B E


+ +
β
β 1
(156)
R
V
I
R
V
I
V
I
C
R
CQ
E
E
EQ
E
CQ
C
≈ and (157)
( )
R
V V
I
R
V V V
I I
E BEQ
CC E BEQ
BQ
2
2
1
2

+

− +
+
and
(158)
Design of the Four-Resistor BJT Bias Circuit
We begin where we are most familiar, by
revisiting the four-resistor bias circuit.
Assume that I
CQ
, V
BEQ
, V
CC
, β
min
and β
max
are known. This amounts to little more
than having chosen the device and the
Q-point.
Now, recall this result from a KVL
equation around the base-emitter loop:
Design Procedure
G First, we decide how V
CC
divides among , V
CE
, V
E
. For V
R
C
temperature stability we want V
E
>> temperature variation in
V
BE
. Recall the “one-third” rule of thumb. Then:
G Then we choose I
2
(larger I
2
lower R
B
better bias ⇒ ⇒
stability lower Z
in
). ⇒
Recall the rule of thumb: I
2
= 10 I
BQ max
. Then:
Introduction to Electronics 125 Design of Discrete BJT Bias Circuits
R
E
R
C
+V
CC
R
B
i
B
i
C
i
E
-
v
B
+
-V
EE
Fig. 187. Dual-supply bias ckt.
( )
( )
I
V V
R R
CQ
EE BEQ
B E


+ +
β
β 1
(159)
R
V
I
V
I
R
V V V
I
B
B
BQ
B
CQ
E
EE B BEQ
CQ

− −
;
β
and (160)
( )
[ ]
R
V V V V
I
V V V V
I
C
CC CEQ B BEQ
CQ
CC CEQ B BEQ
CQ

− − − +

− + +
(161)
Design of the Dual-Supply BJT Bias Circuit
This is essentially the same as the four-
resistor bias circuit. Only the reference
point (ground) has changed.
We begin with the same assumptions as
for the previous circuit.
Because its important that you
understand the principles used to obtain
these equations, verify that the following
results from a KVL equation around the
base-emitter loop:
Design Procedure
G Allocate a fraction of V
EE
for V
B
. For bias stability we would
like the voltage across R
E
to be << |V
B
| (i.e., R
B
<< βR
E
).
A starting point, i.e., a rule of thumb is |V
B
| = V
EE
/ 20. Then:
G Choose V
CEQ
. Here a rule of thumb is: V
CEQ
V
CC
/2. Then: ≈
Note: Smaller V
CEQ
larger R
C
larger A
v
larger Z
out
⇒ ⇒ ⇒
Introduction to Electronics 126 Design of Discrete BJT Bias Circuits
R
C
+V
CC
R
2
i
B
i
C
i
2
-V
EE
R
1
i
1
Fig. 188. Grounded-emitter
bias circuit.
( )
I
V
R
R
V V
R R
CQ
CC EE BEQ
C

− +

]
]
]
+
β
β
1
2
1
(162)
R
V V
I
R
V V
I I
R
V V
I I
EE BEQ CEQ BEQ
BQ
C
CC VEQ
CQ
2
2
1
2 1

+


+


+
(165)
/ 2
CEQ CC
V V ≈ (163)
2 max
10
BQ
I I ≈ (164)
Design of the Grounded-Emitter BJT Bias Circuit
Grounding the emitter directly lowers
inductance in the emitter lead, which
increases high-frequency gain.
Bias stability is obtained by connecting
base to collector through R
1
.
Verifying this approximate equation is
difficult; a derivation is provided on the
following pages:
Design Procedure
G Allocate V
CC
between V
Rc
and V
CEQ
. With supply voltage split
between only two elements the rule of thumb becomes:
G Choose I
2
. To have R
1
<< βR
C
, we want I
2
>> I
B
. The rule of
thumb is:
G Then:
Introduction to Electronics 127 Design of Discrete BJT Bias Circuits
R
C
+V
CC
R
2
i
B
i
C
i
2
-V
EE
R
1
i
1
Fig. 189. Grounded-emitter
bias circuit (Fig. 188 repeated).
( )
I
V
R
R
V V
R R
CQ
CC EE BEQ
C

− +

]
]
]
+
β
β
1
2
1
(166)
I I I
B 1 2
+ (167)
( ) I I I I I
R C B
C
+ + +
1 2
1 β (168)
I
V V
R
EE BEQ
2
2

+
(169)
( ) ( )
[ ]
V V I I R I I R
CC BEQ B B C
+ + + + +
2 1 2
1 β
(170)
( ) ( ) ( ) V V
R
R
V V I R
R
R
V V I R
CC BEQ EE BEQ B
C
EE BEQ B C
+ + + + + + +
1
2
1
2
1 β (171)
Analysis of the Grounded-Emitter BJT Bias Circuit
Q. How do we obtain this equation?
A. We begin by noting that :
and
Then we find I
2
with a KVL equation around the base-emitter loop:
Now we sum voltage rises from ground to V
CC
:
Substituting (169) into (170):
Introduction to Electronics 128 Design of Discrete BJT Bias Circuits
( ) ( ) ( ) V V
R
R
V V I R
R
R
V V I R
CC BEQ EE BEQ B
C
EE BEQ B C
+ + + + + + +
1
2
1
2
1 β (172)
( ) ( ) ( )
[ ]
V V
R
R
V V
R
R
V V I R R
CC BEQ EE BEQ
C
EE BEQ B C
− − + − + + +
1
2 2
1
1 β (173)
( )
I
V
R
R
V V
R R
CQ
CC EE BEQ
C

− +

]
]
]
+
β
β
1
2
1
(174)
Repeating eq. (171) from the bottom of the previous page:
The next step is to collect terms:
Finally, if we apply the following approximations:
V
CC
- V
BEQ
V
CC
R
C
/R
2
0 β + 1 β ≈ ≈ ≈
we obtain our objective, the original approximation:
Introduction to Electronics 129 Bipolar IC Bias Circuits
Bipolar IC Bias Circuits
Introduction
Integrated circuits present special problems that must be
considered before circuit designs are undertaken.
For our purposes here, the most important consideration is real
estate. Space on an IC wafer is at a premium. Anything that takes
up too much space is a liability. Consider the following:
G Resistors are very inefficient when it comes to real estate.
The area required is directly proportional to the value of
resistance (remember R = ρL

/

A

?).
As a result, use of resistances in ICs is avoided, if possible.
And resistances greater than 100 kΩ are extremely rare.
When used, it is quite difficult to control resistance values with
accuracy unless each resistor is laser-trimmed. Tolerances
are as large as 50% are not unusual.
Because all resistors are fabricated at the same time, all
resistors are “off” by the same amount. This means that
resistors that are intended to be equal will essentially be equal.
G Capacitors are also liabilities. Capacitance values greater
than 100 pF are virtually unheard of.
G Inductors only recently became integrable. Their use is quite
limited.
G BJTs are very efficient. And while β values suffer the same
3:1 to 5:1 variation found in discrete transistors, all BJTs on an
IC wafer are essentially identical (if intended to be).
This latter point is most important, and drives all IC circuit design.
We begin to examine this on the following pages.
Introduction to Electronics 130 Bipolar IC Bias Circuits
I
REF
I
O
= I
C2
Q
1
Q
2
R
REF
V
CC
V
CC
Load
I
C1
I
B1
I
B2
Fig. 190. Diode-biased current mirror.
I I I I I
O C C C B

2 1
β (175)
( ) I I I I I I I
REF C B B B B B
+ + + +
1 1 2
2 2 β β
(176)
( )
I
I
I
I
O
REF
B
B

+

+

+
β
β
β
β
β
2 2
1
1
2 (177)
The Diode-Biased Current Mirror
Current Ratio:
This is the most simple of all IC bias
circuit techniques.
The key here is that the BJTs are
identical !!! Because V
BE1
= V
BE2
, this
means that I
B1
= I
B2
= I
B
.
Note that V
CB1
= 0, thus Q
1
is active
(at the edge of saturation).
If we assume Q
2
is also active, we
have I
C1
= I
C2
= I
C
.
From this point the analysis proceeds
straightforwardly . . .
And from a KCL equation at the collector of Q
1
:
Dividing (175) by (176):
Thus, as long as Q
2
remains active, for large β, I
O
I
REF
, i.e., I
O

reflects the current I
REF
(hence “mirror”), regardless of the load!!!
Introduction to Electronics 131 Bipolar IC Bias Circuits
I
REF
I
O
= I
C2
Q
1
Q
2
R
REF
V
CC
V
CC
Load
I
C1
I
B1
I
B2
Fig. 191. Diode-biased current mirror
(Fig. 190 repeated.
I
V V
R
V
R
REF
CC BE
REF
CC
REF



−07 . V
(178)
r
i
v
o
C
CE

]
]
]



2
2
1
(179)
Reference Current:
I
REF
is set easily, by choosing R
REF
:
Output Resistance:
Finally, the output resistance seen by
the load is just the output resistance
of Q
2
:
Introduction to Electronics 132 Bipolar IC Bias Circuits
I
C2
V
CE2
Compliance Range
r
o
= 1/slope
0.5 V BV
Fig. 193. Example of the compliance range of a
current mirror. The diode-biased mirror is
represented in this figure.
V
CC
-V
EE
Amplifier
Current
Mirror
Fig. 194. Follower
biased with a current
nirror.
V
CC
-V
EE
I
DC
Fig. 195. Representation
of the mirror circuit of
Fig. 194.
Fig. 192.
Compliance Range
This is defined as the range of
voltages over which the mirror
circuit functions as intended.
For the diode-biased mirror, this
is the range where Q
2
remains
active.
Using a Mirror to Bias an Amplifier
Changing transistor areas gives mirror ratios other than
unity, which is useful to obtain small currents without
using large R values. The schematic technique used to
show integer ratios other than unity is shown.
Introduction to Electronics 133 Bipolar IC Bias Circuits
I
REF
R
REF
Q
1 Q
3
Q
2
I
O
= I
C2
V
CC
Load
V
CC
Fig. 196. Wilson current mirror.
( )
I I I I
E C B B 2 3
2 2 + + β (180)
( )
I I I I
O C E B

+

+
+
2 2
1
2
1
β
β
β β
β
(181)
I I I
B E B 2 2
1
1
2
1

+

+
+ β
β
β
(182)
I I I I I
REF C B B B
+ +
+
+
1 2
2
1
β
β
β
(183)
Wilson Current Mirror
Current Ratio:
The addition of another transistor
creates a mirror with an output
resistance of βr
o2
(very large!!!) ≈
Because V
BE1
= V
BE3
we know that
I
B1
= I
B3
= I
B
.
Because V
CB3
= 0, Q
3
is active.
Because V
CB1
= V
BE2
, Q
1
is active.
Thus we know that I
C1
= I
C3
= βI
B
.
We assume also that Q
2
is active.
We proceed with the mathematical derivation without further
comment.
Introduction to Electronics 134 Bipolar IC Bias Circuits
( ) ( )
( )
( )
( ) ( )
I
I
I
I I
O
REF
B
B B

+
+
+
+
+

+
+
+
+
+
+
+

+
+ + +
β β
β
β
β
β
β β
β
β β
β
β
β
β β
β β β
2
1
2
1
2
1
1
1
2
1
2
1 2
(184)
I
I
O
REF

+
+ +

+
+

+

β β
β β
β β β
2
2
2 2
2
2 2
1
1
2
2
1
1
2
1
(185)
I
V V V
R
V
R
REF
CC BE BE
REF
CC
REF

− −


2 3
14 . V
(186)
Thus the Wilson mirror ratio is much closer to unity than the ratio of
the simple diode-biased mirror.
Reference Current:
The reference current can be found by summing voltages rises from
ground to V
CC
:
Output Resistance:
The output resistance of the Wilson can be shown to be βr
o2
.
However, the derivation of the output resistance is a sizable
endeavor and will not be undertaken here.
Introduction to Electronics 135 Bipolar IC Bias Circuits
V
BE1
I
O
= I
C2
Q
1
Q
2
R
1
V
CC
V
CC
Load
I
C1
R
2
V
BE2
+ +
- -
Fig. 197. Widlar mirror.
i I
v
V
v V
i
I
C S
BE
T
BE T
C
S

|
(
'
`
J
J

|
(
'
`
J
J
exp ln and (187)
V V
i
I
V V
i
I
BE T
C
S
BE T
C
S
1
1
2
2

|
(
'
`
J
J

|
(
'
`
J
J
ln ln and (188)
Widlar Current Mirror
If very small currents are required, the
resistances in the previous mirror
circuits become prohibitively large.
The Widlar mirror solves that problem
Though it uses two resistors, the total
resistance required by this circuit is
reduced substantially.
The circuit’s namesake is Bob Widlar
(wide’ lar) of Fairchild Semiconductor
and National Semiconductor.
The analysis is somewhat different than
our previous two examples.
Current Relationship:
Recall the Shockley transistor equations for forward bias:
Thus we may write:
Note that V
T
and I
S
are the same for both transistors because they
are identical (and assumed to be at the same temperature).
Introduction to Electronics 136 Bipolar IC Bias Circuits
V
BE1
I
O
= I
C2
Q
1
Q
2
R
1
V
CC
V
CC
Load
I
C1
R
2
V
BE2
+ +
- -
Fig. 198. Widlar mirror (Fig. 197
repeated).
V V R I V R I
BE BE E BE C 1 2 2 2 2 2 2
+ ≈ + (189)
V V V R I
BE BE BE C 1 2 2 2
− ≈ ∆ (190)
Analysis: Design:
V
R
I
I
I R
V
I
I
I
T C
C
C
T
C
C
C 2
1
2
2 2
2
1
2
ln ln
|
(
'
`
J
J

|
(
'
`
J
J
(192)
V
I
I
V
I
I
R I V
I
I
R I
T
C
S
T
C
S
C T
C
C
C
ln ln ln
1 2
2 2
1
2
2 2
|
(
'
`
J
J

|
(
'
`
J
J
≈ ⇒
|
(
'
`
J
J
≈ (191)
I I
V V
R
C REF
CC BE
1
1
1


(193)
Continuing with the derivation from the
previous page . . .
From a KVL equation around the base-
emitter loop:
Rearranging:
Substituting the base-emitter voltages from eq. (188) into eq. (190):
Where the last step results from a law of logarithms.
This is a transcendental equation. It must be solved iteratively, or
with a spreadsheet, etc. The form of the equation to use depends
on whether we’re interested in analysis or design:
where:
Introduction to Electronics 137 Bipolar IC Bias Circuits
I
REF
V
CC
V
CC
V
CC
-V
EE
-V
EE
-V
EE
Load 1 Load 2
Load 3 Load 4
Fig. 199. Multiple current mirrors.
Multiple Current Mirrors
In typical integrated circuits multiple current mirrors are used to
provide various bias currents. Usually, though, there is only one
reference current, so that the total resistance on the chip may be
minimized.
The figure below illustrates the technique of multiple current mirrors,
as well as mirrors constructed with pnp devices:
FET Current Mirrors
The same techniques are used in CMOS ICs (except, of course, the
devices are MOSFETs). The details of these circuits are not
discussed here.
Introduction to Electronics 138 Linear Small-Signal Equivalent Circuits
Linear Small-Signal Equivalent Circuits
G In most amplifiers (and many other circuits):
We use dc to bias a nonlinear device . . .
At an operating point (Q-point) where the nonlinear device
characteristic is relatively straight, i.e., almost linear . . .
And then inject the signal to be amplified (the small signal) into
the circuit.
G The circuit analysis is split into two parts:
DC analysis, which must consider the nonlinear device
characteristics to determine the operating point.
Alternatively, we can substitute an accurate model, such as a
piecewise-linear model, for the nonlinear device.
AC analysis, but because injected signal is small, only a small
region of the nonlinear device characteristic need be
considered.
This small region is almost linear, so we assume it is linear,
and construct a linear small-signal equivalent circuit.
G After analysis, the resulting dc and ac values may be
recombined, if necessary or desired.
Introduction to Electronics 139 Diode Small-Signal Equivalent Circuit
V
DC
v
s
+
v
D
i
D
+
-
Fig. 200. Generalized diode circuit.
i
D
v
D
I
DQ
V
DQ
Q
Fig. 201. Diode characteristic.
∆ ∆ i K v
D D
(194)
Diode Small-Signal Equivalent Circuit
The Concept
First, we allow v
s
to be zero. The circuit is now dc only, and has a
specific Q-point shown.
We can find the Q-point analytically with the Shockley equation, or
with a diode model such as the ideal, constant-voltage-drop, or
piecewise-linear model.
Now, we allow v
s
to be nonzero, but small.
The instantaneous operating point moves slightly above and below
the Q-point. If signal is small enough, we can approximate the
diode curve with a straight line.
The Equations
This straight-line approximation allows us to write a linear equation
relating the changes in diode current (around the Q-pt.) to the
changes in diode voltage:
Introduction to Electronics 140 Diode Small-Signal Equivalent Circuit
∆ ∆ i K v
D D
(195)
i
D
v
D
I
DQ
V
DQ
Q
Fig. 202. Diode curve with tangent at
Q-point.
i
r
v
d
d
d

1
(196)
Repeating the linear equation from the previous page:
The coefficient K is the slope of the straight-line approximation, and
must have units of Ω
-1
.
We can choose any straight line we want. The best choice (in a
least-squared error sense) is a line tangent at pt. Q !!!
We rewrite eq. (195) with changes in notation.
K becomes 1/r
d
, ∆i
D
becomes i
d
, and ∆v
D
becomes v
d
:
This is merely Ohm’s Law!!!
r
d
is the dynamic resistance or small-signal resistance of the diode.
i
d
and v
d
are the signal current and the signal voltage, respectively.
Introduction to Electronics 141 Diode Small-Signal Equivalent Circuit
1
r
i
v
d
D
D
Q po




int
(197)
i I
v
nV
I
v
nV
D S
D
T
S
D
T

|
(
'
`
J
J

]
]
]

|
(
'
`
J
J
exp exp 1 (198)

∂v
I
v
nV
I
nV
V
nV
D
S
D
T
Q po
S
T
DQ
T
exp exp
int
|
(
'
`
J
J

]
]
]

|
(
'
`
J
J

(199)
I I
V
nV
DQ S
DQ
T

|
(
'
`
J
J
exp (200)


i
v
I
nV
r
nV
I
D
D
Q po
DQ
T
d
T
DQ

≈ ⇒ ≈
int
(201)
Diode Small-Signal Resistance
We need only to calculate the value of r
d
, where 1/r
d
is the slope of
a line tangent at pt. Q, i.e.,
We use the diode forward-bias approximation:
Thus:
But, notice from (198):
So:
Notes:
1. The calculation of r
d
is easy, once we know I
DQ
!!!
2. I
DQ
can be estimated with simple diode models !!!
3. Diode small-signal resistance r
d
varies with Q-point.
4. The diode small-signal model is simply a resistor !!!
Introduction to Electronics 142 Notation
i
D
t
I
DQ
i
D
i
d
Fig. 203. Illustration of various currents.
Notation
The following notation is standard:
v
D
, i
D
This is the total instantaneous quantity.
(dc + ac, or bias + signal)
V
D
, I
D
This is the dc quantity.
(i.e., the average value)
v
d
, i
d
This is the ac quantity.
(This is the total instantaneous quantity with the
average removed)
V
d
, I
d
If a vector, this is a phasor quantity. If a scalar it is
an rms or effective value.
Introduction to Electronics 143 BJT Small-Signal Equivalent Circuit
V
DC
v
s
+
i
C
i
E
i
B
Fig. 204. Generalized BJT circuit.
i
B
t
I
BQ
i
B
i
b
Fig. 205. Generalized base current waveform.
i
B
v
BE
I
BQ
Q
~0.7 V
Fig. 206. BJT input characteristic.
i
i
v
v
r
v
b
B
BE
Q po
be be

]
]
]
]




π
int
1
(202)
where r
V
I
T
BQ
π

(203)
BJT Small-Signal Equivalent Circuit
First, note the total base current (bias + signal): i
B
= I
BQ
+ i
b
This produces a total base-emitter voltage: v
BE
= V
BEQ
+ v
be
Now, let the signal component be small: |i
b
| << I
BQ
With the signal sufficiently small, v
be
and i
b
will be approximately
related by the slope of the BJT input characteristic, at the Q-point.
This is identical to the diode small-signal development !!! Thus, the
equations will have the same form:
Introduction to Electronics 144 BJT Small-Signal Equivalent Circuit
i
c
i
e
i
b
B C
E
r
π
βi
b
v
be
+
-
Fig. 207. BJT small-signal equivalent circuit.
i i i i
C B c b
⇒ β β (204)
With r
π
determined, we can turn our attention to the output
(collector) side.
If the BJT is in its active region, we have a simple current
relationship:
Combining eqs. (202) through (204) we can construct the BJT
small-signal equivalent circuit:
Because the bias point is “accounted for” in the calculation of r
π
,
this model applies identically to npn and to pnp devices.
Introduction to Electronics 145 The Common-Emitter Amplifier
R
S
R
1
R
2
R
C
R
E
R
L
C
in
C
out
v
s
v
o
+
+
-
-
V
CC
Q
1
v
in
+
-
C
E
Fig. 208. Standard common emitter amplifier circuit.
The Common-Emitter Amplifier
Introduction
The typical four-resistor bias circuit is shown in black. . .capacitors
are open circuits at dc, so only signal currents can flow in the blue
branches.
Capacitors are chosen to appear as short circuits at frequencies
contained in the signal (called midband frequencies).
C
in
and C
out
couple the signal into, and out of, the amplifier. C
E
provides a short circuit around R
E
for signal currents only (dc
currents cannot flow through C
E
.
A standard dc analysis of the four-resistor bias circuit provides the
Q-point, and from that we obtain the value of r
π
.
Introduction to Electronics 146 The Common-Emitter Amplifier
R
S
R
1
R
2
R
C
R
E
R
L
C
in
C
out
v
s
v
o
+
+
-
-
V
CC
Q
1
v
in
+
-
C
E
Fig. 209. Standard common emitter. (Fig. 208 repeated)
v
s
R
S
R
2
R
1
r
π
R
L
R
C βi
b
v
o
+
+
-
-
B
E
C
i
b
v
in
+
-
Fig. 210. Small signal equivalent circuit of common emitter amplifier.
Constructing the Small-Signal Equivalent Circuit
To construct small-signal equivalent circuit for entire amplifier, we:
1. Replace the BJT by its small-signal model.
2. Replace all capacitors with short circuits.
3. Set all dc sources to zero, because they have zero signal
component!!!
The result is the small-signal equivalent circuit of the amplifier:
Introduction to Electronics 147 The Common-Emitter Amplifier
v
s
R
S
R
B
r
π R
L
’ βi
b
v
o
+
+
-
-
B
E
C
i
b
v
in
+
-
Fig. 211. Simplified small signal equivalent of common emitter amplifier.
v i R
o b L


β
(206)
v v i r
in be b

π
(205)
A
v
v
i R
i r
R
r
v
o
in
b L
b
L




β β
π π
(207)
A
v
v
R
r
vo
o
in
C

−β
π
(208)
For convenience we let R
1
|| R
2
= R
B
, and R
C
|| R
L
= R
L
’:
Voltage Gain
Our usual focus is A
v
= v
o
/v
in
, or A
vs
= v
o
/v
s
. We concentrate on the
former. Because i
b
is the only parameter common to both sides of
the circuit, we can design an approach:
1. We write an equation on the input side to relate v
in
to i
b
.
2. We write an equation on output side to relate v
o
to i
b
.
3. We combine equations to eliminate i
b
.
Thus:
And:
With R
L
removed (an open-circuit load), we define the open-circuit
voltage gain, A
vo
:
Introduction to Electronics 148 The Common-Emitter Amplifier
v
s
R
S
R
B
r
π R
L
βi
b
v
o
+
+
-
-
B
E
C
i
b
v
in
+
-
i
in
R
in
Fig. 212. Input resistance of common emitter amplifier.
R
S
R
B
r
π R
C
βi
b
B
E
C
i
b
R
o
Fig. 213. Output resistance of common emitter amplifier.
R R r
in B
||
π
(209)
R R
o C
(210)
Input Resistance
By definition, R
in
= v
in
/i
in
. We can find this simply by inspection:
Output Resistance
Recall that to find R
o
, we must remove the load, and set all
independent sources to zero, but only independent sources. We do
not set dependent sources to zero!!!
Thus:
Now, because i
b
= 0, the dependent source βi
b
= 0 also,and:
Introduction to Electronics 149 The Emitter Follower (Common Collector Amplifier)
R
S
R
1
R
2
R
E
R
L
C
in
C
out
v
s
v
o
+
+
-
-
V
CC
Q
1
v
in
+
-
Fig. 214. Standard emitter follower circuit.
v
s
R
S
R
2
R
1
r
π
R
L
R
E
βi
b
v
o
+
+
-
-
B
E
C
i
b
v
in
+
-
(β+1)i
b
R
1
|| R
2
= R
B
R
E
|| R
L
= R
L

Fig. 215. Emitter follower small-signal equivalent circuit. The
collector terminal is grounded, or common, hence the alternate name
Common Collector Amplifier.
The Emitter Follower (Common Collector Amplifier)
Introduction
We have a four-resistor bias network, with R
C
= 0.
Unlike the common-emitter amplifier, v
o
is taken from the emitter.
The small-signal equivalent is derived as before:
Introduction to Electronics 150 The Emitter Follower (Common Collector Amplifier)
v
s
R
S
R
2
R
1
r
π
R
L
R
E
βi
b
v
o
+
+
-
-
B
E
C
i
b
v
in
+
-
(β+1)i
b
R
1
|| R
2
= R
B
R
E
|| R
L
= R
L

Fig. 216. Emitter follower small-signal equivalent (Fig. 215 repeated).
( )
v i r i R
in b b L
+ +

π
β 1
(211)
( )
v i R
o b L
+

β 1
(212)
( )
( )
A
v
v
R
r R
v
o
in
L
L

+

+ +

β
β
π
1
1
(213)
Voltage Gain
Gain, A
v
= v
o
/v
in
, is found using the same approach described for
the common-emitter amplifier. We write two equations of i
b
- one on
the input side, one on the output side - and solve:
Typical values for A
v
range from 0.8 to unity. The emitter (output)
voltage follows the input voltage, hence the name emitter follower.
The feature of the follower is not voltage gain, but power gain, high
input resistance and low output resistance, as we see next . . .
Introduction to Electronics 151 The Emitter Follower (Common Collector Amplifier)
v
s
R
S
R
2
R
1
r
π
R
L
R
E
βi
b
v
o
+
+
-
-
B
E
C
i
b
v
in
+
-
(β+1)i
b
R
1
|| R
2
= R
B
R
E
|| R
L
= R
L
R
in
R
it
Fig. 217. Calculating the input resistance of the emitter follower.
R
v
i
R R R
v
i
in
in
in
B it it
in
b
|| , where
(214)
( )
R r R
it L
+ +

π
β 1
(215)
( )
[ ]
R R r R
in B L
+ +

||
π
β 1
(216)
Input Resistance
Note that :
We’ve already written the equation we need to find R
it
. It’s equation
(211), from which:
Thus
Compare this to the common emitter input resistance, which is
generally much lower, at . R R r
in B
||
π
Introduction to Electronics 152 The Emitter Follower (Common Collector Amplifier)
R
S
R
2
R
1
r
π
R
E
βi
b
v
test
+
-
B
E
C
i
y
(β+1)i
b
R
1
||R
2
||R
S
= R
S
’ i
test
i
b
R
o
R
ot
Fig. 218. Circuit for calculating follower output resistance.
( )
R
v
i
R R R
v
i
v
i
o
test
test
E ot ot
test
y
test
b

− +
|| , where
β 1
(217)
( )
v i R r R
R r
test b S ot
S


+ ∴

+
+
π
π
β 1
(218)
Output Resistance
Notice that we have set the independent source to zero, and
replaced R
L
by a test source. From the definition of output
resistance:
But
Compare this to the common emitter input resistance, which is
much higher, at R
C
.
Introduction to Electronics 153 Review of Small-Signal Analysis
Review of Small Signal Analysis
It’s presumed that a dc analysis has been completed, and r
π
is
known.
1. Draw the small-signal equivalent circuit.
A. Begin with the transistor small signal model.
B. For midband analysis, coupling and bypass
capacitors replaced by short circuits.
C. Set independent dc sources to zero.
2. Identify variables of interest.
3. Write appropriate independent circuit equations.
(This usually requires an equation on the “input” side and an
equation on the “output” side of the small-signal equivalent
circuit.)
4. Solve.
5. Check units!!!
Introduction to Electronics 154 FET Small-Signal Equivalent Circuit
V
DC
v
s
+
i
D
i
S
Fig. 219. Generalized FET circuit.
i
D
v
GS
V
P
I
DSS
I
DQ
V
GSQ
Q
Fig. 220. FET transfer characteristic.
v V v i I i
GS GSQ gs D DQ d
+ + and (219)
i
d
i
s
v
gs
+
-
G D
S
g
m
v
gs
Fig. 221. FET sm. sig. model.
i g v
d m gs
(220)
FET Small-Signal Equivalent Circuit
The Small-Signal Equivalent
We restrict operation to the pinch-off region and note that the dc
source and the circuit determine the Q-point.
For small v
s
, the instantaneous operating pt. stays very near Q, and
the transfer curve can be approximated with a line tangent at Q.
Both v
GS
and i
D
have dc and ac components:
V
GSQ
and I
DQ
are related by the second-
order FET characteristic, but if |v
s
| is
small enough, v
gs
and i
d
are related
(almost) linearly:
g
m
, is called the transconductance.
This leads immediately to the model at
left.
Introduction to Electronics 155 FET Small-Signal Equivalent Circuit
i
D
v
GS
V
P
I
DSS
I
DQ
V
GSQ
Q
Fig. 222.FET transfer characteristic.
g
i
v
m
D
GS
Q



(221)
( )
i K v V
D GS P

2
(222)
( )
[ ]
( )
g
v
K v V K V V
m
GS
GS P
Q
GSQ P
− −


2
2 (223)
V V
I
K
GSQ P
DQ

(224)
g KI
m DQ
2 (225)
g
I I
V
m
DSS DQ
P
2 (226)
Transconductance
The coefficient g
m
is the slope
of the tangent :
From the pinch-off region
equation:
We obtain:
But also from eq. (222) we have
Substituting this into eq. (223), we see that the transconductance
can also be written as:
Or, finally, because K = I
DSS
/V
P
2
we can write:
Introduction to Electronics 156 FET Small-Signal Equivalent Circuit
Fig. 223. FET output characteristics.
i
i
v
v
i
v
v g v
v
r
d
D
GS
Q
gs
D
DS
Q
ds m gs
ds
d

]
]
]
]
+

]
]
]
]
+




(227)
i
d
i
s
v
gs
+
-
G D
S
g
m
v
gs r
d
Fig. 224. FET small-signal model including
FET output resistance.


i
v r
Q
D
DS
Q
d

1
slope of output char. at (228)
FET Output Resistance
Recall that FET output
characteristics have upward
slope. This means that i
d
is
not dependent only on v
gs
,
but also on v
ds
.
We can account for both
dependencies by writing:
where
A single addition to the small-signal model accounts for r
d
:
Output resistance is more
noticeable in FETs than in
BJTs.
But it is also observed in BJTs
and can be included in the
BJT small-signal model,
where the notation r
o
is used
for output resistance.
Introduction to Electronics 157 The Common-Source Amplifier
R
sig
R
G
R
D
R
S
R
L
C
in
C
out
v
sig
v
o
+
+
-
-
V
DD
v
in
+
-
C
S
Fig. 225. Standard common source amplifier circuit.
v
sig
R
sig
r
d
R
G R
L
R
D
g
m
v
gs
v
o
+
+
- -
G
S
D
v
in
+
-
i
in
v
gs
+
-
r
d
||R
D
||R
L
= R
L

Fig. 226. Small-signal equivalent circuit for the common source amplifier.
The Common Source Amplifier
The Small-Signal Equivalent Circuit
The self-bias circuit is shown in black.
Capacitors are open circuits at dc, so only signal currents flow in the
blue branches.
A standard dc analysis provides the value of g
m
.
The small-signal equivalent is constructed in the standard manner:
Introduction to Electronics 158 The Common-Source Amplifier
v
sig
R
sig
r
d
R
G R
L
R
D
g
m
v
gs
v
o
+
+
- -
G
S
D
v
in
+
-
i
in
v
gs
+
-
r
d
||R
D
||R
L
= R
L

Fig. 227. Common source small signal equivalent (Fig. 226 repeated).
v v v g v R
in gs o m gs L


and
(229)
A
v
v
g R
v
o
in
m L


(230)
R
v
i
R
in
in
in
G

(231)
R r R
o d D
|| (232)
Voltage Gain
Thus:
Input Resistance
Because no dc current flows through R
G
it can be extremely large.
Output Resistance
Remember, we must remove R
L
, and set all independent sources
to zero. For this circuit we can determine R
o
by inspection:
Introduction to Electronics 159 The Source Follower
R
sig
R
G
R
S
R
L
C
in
C
out
v
sig
v
o
+
+
-
-
V
DD
v
in
+
-
Fig. 228. Source follower circuit.
v
sig
R
sig
r
d
R
G
R
L
R
S
g
m
v
gs
v
o
+
+
-
-
G
S
D
v
in
+
-
i
in
v
gs
+
-
r
d
||R
S
||R
L
= R
L

Fig. 229. Source follower small-signal equivalent circuit.
The Source Follower
Small-Signal Equivalent Circuit
This follower uses fixed bias: I
G
= 0 V
GSQ
= 0 I
D
= I
DSS
⇒ ⇒
Tremendously large R
in
is obtained by sacrificing bias stability,
which isn’t very important in this circuit anyway, as we shall see.
The small-signal equivalent is constructed in the usual manner:
Introduction to Electronics 160 The Source Follower
v
sig
R
sig
r
d
R
G
R
L
R
S
g
m
v
gs
v
o
+
+
-
-
G
S
D
v
in
+
-
i
in
v
gs
+
-
r
d
||R
S
||R
L
= R
L

Fig. 230. Source follower small-signal equivalent circuit (Fig. 229
repeated).
v v v v v v
in gs o gs in o
+ ⇒ − (233)
( )
v g v i R g v
v
R
R v g
R
R
o m gs in L m gs
gs
G
L gs m
G
L
+

+
|
(
'
`
J
J

+
|
(
'
`
J
J

1
(234)
( )
v v v g
R
R
o in o m
G
L
− +
|
(
'
`
J
J

1
(235)
1
1 1
+ +
|
(
'
`
J
J

]
]
]
+
|
(
'
`
J
J

g
R
R v v g
R
R
m
G
L o in m
G
L
(236)
A
v
v
g
R
R
g
R
R
v
o
in
m
G
L
m
G
L

+
|
(
'
`
J
J

+ +
|
(
'
`
J
J


1
1
1
05 . to 0.8 typically (237)
Voltage Gain
This one requires a little more algebra. Beginning with:
and
We replace v
gs
in eq. (234) with eq. (233), and solve for v
o
/v
in
:
Introduction to Electronics 161 The Source Follower
v
sig
R
sig
r
d
R
G
R
L
R
S
g
m
v
gs
v
o
+
+
-
-
G
S
D
v
in
+
-
i
in
v
gs
+
-
r
d
||R
S
||R
L
= R
L

Fig. 231. Source follower small-signal equivalent circuit (Fig. 229
repeated).
v v v v v g
R
R
in gs o gs gs m
G
L
+ + +
|
(
'
`
J
J

1
(238)
v i R i R g
R
R
in in G in G m
G
L
+ +
|
(
'
`
J
J

1
(239)
( )
R
v
i
R g R R
in
in
in
G m G L
+ +

1
(240)
Input Resistance
Replacing v
o
in eq. (233) with eq. (234):
But v
gs
= i
in
R
G
:
Solving for v
in
/i
in
:
Because I
G
= 0, R
G
can be several MΩ. With the additional
multiplying factor of R
L
’, R
in
can become extremely large!!!
Introduction to Electronics 162 The Source Follower
v
test
R
sig
r
d
R
G
R
S
g
m
v
gs
+
-
G
S
D
i
test
v
gs
+
-
Fig. 232. Determining output resistance of the source follower.
i
v
R
v
r
v
R R
g v
test
test
S
test
d
test
G sig
m gs
+ +
+

(241)
v
R
R R
v
gs
G
G sig
test

+
(242)
i v
R r R R
g R
R R
test test
S d G sig
m G
G sig
+ +
+
+
+
|
(
'
`
J
J
1 1 1
(243)
Output Resistance
This calculation is a little more involved, so we shall be more formal
in our approach.
We remove R
L
, apply a test source, v
test
, and set the independent
source to zero.
From a KCL equation at the source node:
But R
G
and R
sig
form a voltage divider:
Substituting eq. (242) into eq. (241):
Introduction to Electronics 163 The Source Follower
v
test
R
sig
r
d
R
G
R
S
g
m
v
gs
+
-
G
S
D
i
test
v
gs
+
-
Fig. 233. Determining output resistance of the source follower (Fig.
232 repeated).
R
v
i
R r R R
g R
R R
o
test
test
S d G sig
m G
G sig

+ +
+
+
+
1
1 1 1
(244)
( )
R R r R R
R R
g R
o S d G sig
G sig
m G
+
+
|
(
'
`
J
J
|| || || (245)
Thus:
Finally, we recognize this form as that of resistances in parallel:
Introduction to Electronics 164 Review of Bode Plots
A f
j
f
f
j
f
f
j
f
f
v
Z Z
P
( )
|
(
'
`
J
J
+
|
(
'
`
J
J
+
|
(
'
`
J
J
1 2
1
1
1

(246)
Review of Bode Plots
Introduction
The emphasis here is review. Please refer to an appropriate text if
you need a more detailed treatment of this subject.
Let us begin with a generalized transfer function:
We presume the function is limited to certain features:
G Numerator and denominator can be factored.
G Numerator factors have only one of the two forms shown.
G Denominator factors have only the form shown.
Remember:
G Bode plots are not the actual curves, but only asymptotes to
the actual curves.
G Bode magnitude plots are not based on the transfer function
itself, but on the logarithm of the transfer function - actually, on
20 log A
v
.
G The total Bode response for A
v
(f) consists of the magnitude
response and the phase response. Both of these consist of
the sum of the responses to each numerator and denominator
factor.
Introduction to Electronics 165 Review of Bode Plots
0 dB
f
z1
20 dB/decade
Fig. 234. Bode magnitude
response for jf/f
Z1
.
0 dB
f
z2
20 dB/decade
Fig. 235. Bode magnitude
response for 1 + jf/f
Z2
.
The Bode Magnitude Response
Now, let’s review the Bode magnitude response of each term:
The numerator term : j
f
f
Z1
The magnitude response increases 20
dB per decade for all f.
For f = f
Z1
the term has a magnitude of 1.
Thus the magnitude response has an
amplitude of 0 dB at f
Z1
.
The numerator term : 1
2
+ j
f
f
Z
For f << f
Z2
the imaginary term is
negligible; the magnitude is just 0 dB.
For f >> f
Z2
the imaginary term
dominates, thus the magnitude increases
20 db per decade.
The denominator term : 1
1
+ j
f
f
P
For f << f
P1
the imaginary term is
negligible; the magnitude is just 0 dB.
For f >> f
P1
the imaginary term
dominates, thus the magnitude
decreases 20 db per decade (because
the term is in the denominator).
0 dB
f
p
-20 dB/decade
Fig. 236. Bode magnitude
response for 1 + jf/f
P1
.
Introduction to Electronics 166 Review of Bode Plots
+90
O
Fig. 237. Bode phase response
for jf/f
Z1
.
0
O
f
z2
/10
10f
z2
+90
O
45
O
/decade
Fig. 238. Bode phase response
for 1 + jf/f
Z2
.
The Bode Phase Response
Now, let’s review the Bode phases response of each term:
The numerator term : j
f
f
Z1
The phase response is simply 90
o
for all
f.
The numerator term : 1
2
+ j
f
f
Z
For f << f
Z2
the imaginary term is
negligible; the phase is just 0
o
.
For f >> f
Z2
the imaginary term
dominates, thus the phase is 90
o
.
At f = f
Z2
, the term is 1 + j1; its phase is
45
O
.
The denominator term : 1
1
+ j
f
f
P
For f << f
Z2
the imaginary term is
negligible; the phase is just 0
o
.
For f >> f
Z2
the imaginary term
dominates, thus the phase is -90
o
.
At f = f
Z2
, the term is 1 + j1; its phase is
-45
O
.
0
O
f
p
/10
10f
p
-45
O
/decade
-90
O
Fig. 239. Bode phase response
for 1 + jf/f
P1
.
Introduction to Electronics 167 Review of Bode Plots
V
o
(s)
R
+
1/sC
V
in
(s)
+
-
Fig. 240. Single-pole low-pass RC circuit,
A
V
V
sC
R
sC
sRC
v
o
in

+

+
1
1
1
1
(247)
( )
A
j RC f
j
f
f
f
RC
v
b
b

+

+

1
1 2
1
1
1
2 π π
where
(248)
A
f
f
v
b

+
|
(
'
`
J
J
1
1
2
2
(249)
Single-Pole Low-Pass RC
The review of the details of the
Bode response of a single-pole
low-pass RC circuit begins with
the s-domain transfer function:
Note that there is a pole at s = -1/RC and zero at s = . ∞
For the sinusoidal steady state response we substitute j2πf for s:
This fits the generalized single-pole form from the previous page,
except we’re using “f
b
” instead of “f
P
.” The term f
b
is called the half-
power frequency, the corner frequency, the break frequency, or the
3-dB frequency.
Gain Magnitude in dB:
From:
Introduction to Electronics 168 Review of Bode Plots
( )
A
f
f
f
f
f
f
f
f
v
dB
b
b
b b

+
|
(
'
`
J
J
− +
|
(
'
`
J
J
− +
|
(
'
`
J
J
− +
|
(
'
`
J
J

]
]
]
]
20
1
1
20 1 20 1
20 1 10 1
2
2
2
2
2
2 2
log log log
log log
(250)
( )
A
v
dB
− 10 1 0 log dB (251)
A
f
f
f
f
v
dB
b b

|
(
'
`
J
J

|
(
'
`
J
J
10 20
2
log log
(252)
f
b
/10 f
b
10f
b
100f
b
-3 dB
-40 dB
-20 dB
A
v
, dB
f
Fig. 241. Bode magnitude plot for single-pole low-
pass, in red. The actual curve is shown in blue.
We obtain:
Bode Magnitude Plot:
From eq. (250), at low frequencies (f /f
b
<< 1):
And, at high frequencies (f /f
b
>> 1):
Note that the latter
equation decreases 20
dB for each factor of 10
increase in frequency
(i.e., -20 db per decade).
Introduction to Electronics 169 Review of Bode Plots
f/f
b
1
θ θθ θ Re
Im
Fig. 242. Trigonometric representation
of transfer function phase angle.
A
j
f
f
v
b

+
1
1
(253)
θ
A
b
v
f
f
−arctan (254)
f
b
/10 f
b
10f
b
100f
b
θ, deg
f 0
O
-45
O
-90
O
Fig. 243. Bode phase plot for single-pole low-pass,
shown in red. The actual curve is shown in blue.
Bode Phase Plot:
From the transfer function:
The transfer function phase angle
is:
The Bode phase plot shows the characteristic shape of this inverse
tangent function:
Introduction to Electronics 170 Review of Bode Plots
V
o
(s)
R
+
1/sC
V
in
(s)
+
-
Fig. 244. Single-pole high-pass RC
circuit.
A
R
sC
R
sRC
sRC
v

+

+
1
1
(255)
( )
( )
A
j RC f
j RC f
j
f
f
j
f
f
f
RC
v
b
b
b

+

+

2
1 2
1
1
2
π
π π
where (256)
A
f
f
f
f
v
dB
b b

|
(
'
`
J
J
− +
|
(
'
`
J
J
20 20 1
2
log log
(257)
Single-Pole High-Pass RC
The s-domain transfer function:
Note there is a pole at s = -1/RC,
and a zero at s = 0.
For the sinusoidal steady state response we substitute j2πf for s:
Bode Magnitude Plot:
Because this is a review, we go directly to the resulting gain
equation:
Recall from Fig. (234) that the first term is a straight line, with +20
dB/dec slope, passing through 0 dB at f
b
.
The last term is the same term from the low pass example, which
has the form of Fig. (236).
The total Bode magnitude response is merely the sum of these two
responses.
Introduction to Electronics 171 Review of Bode Plots
f
b
/10 f
b
10f
b
100f
b
-3 dB
-40 dB
-20 dB
A
v
, dB
f
Fig. 245. Bode magnitude plot for single-pole high
pass, in red. The actual curve is shown in blue.
f
b
/10 f
b
10f
b
100f
b
θ, deg
f
90
O
45
O
0
O
Fig. 246. Bode phase plot for single-pole high-pass,
in red. The actual curve is shown in blue.
θ
A
b
v
f
f
°− 90 arctan (258)
Adding the two individual responses gives:
Bode Phase Plot:
The transfer function leads to the following phase equation:
This is just the low-pass phase plot shifted upward by 90
o
:
Introduction to Electronics 172 Coupling Capacitors
R
S
R
B
R
C
R
L
C
in
C
out
v
s
v
o
+
+
-
-
V
CC
Q
1
v
in
+
-
Source Amplifier Load
Fig. 247. Representative amplifier circuit, split into sections.
R
B
r R
C βi
b
i
b
Fig. 248. Amplifier sm. sig. eq. ckt.
R
in
R
o
+
-
+
-
v
x
A
vo
v
x
Fig. 249. Model equivalent to
amplifier section.
Coupling Capacitors
Effect on Frequency Response
In our midband amplifier analysis, we assumed the capacitors were
short circuits, drew the small-signal equivalent, and analyzed it for
overall gain (or other parameters). This time, though:
(1) we can draw the sm. sig. eq.
ckt. of the amplifier section only,
(2) analyze it, determine the its
model parameters, and . . .
Introduction to Electronics 173 Coupling Capacitors
R
in
R
o
+
-
+
-
v
x
A
vo
v
x
R
L
C
out
v
o
+
-
R
S
C
in
v
s
+
-
Fig. 250. Complete circuit redrawn with amplifier section replaced by its model.
( )
f
C R R
in S in
1
1
2

+ π
(259)
( )
f
C R R
out o L
2
1
2

+ π
(260)
. . . (3) redraw the entire circuit (Fig. 247) as shown:
Note that both sides are identical topologically, and are single-pole,
high-pass circuits:
On the left: On the right:
At frequencies above f
1
and f
2
, the Bode magnitude plots from
these high-pass circuits are simply horizontal lines at 0 dB, which
add to become a single horizontal line at 0 dB. Of course, the
amplifier (and resistive dividers) will shift this horizontal line
(hopefully upward, because we probably want A
v
> 1). .
Suppose we begin somewhere above f
1
and f
2
- at midband . . . we
already know how to find the midband gain, which will become
on the Bode magnitude plot. 20logA
v
mid
Now let’s work our way lower in frequency. . . when we get to the
first of the two pole frequencies, our Bode magnitude plot begins to
drop at 20 dB/decade. . . when we get to the second pole, the plot
drops at 40 dB/decade. . . see the illustration on the next page.
Introduction to Electronics 174 Coupling Capacitors
20 log A
v mid
f
1
f
2
20 dB/dec
40 dB/dec
Fig. 251. Generalized Bode magnitude plot of an amplifier with
coupling capacitors. Here f
1
is assumed to be lower than f
2
.
Note that the presence of f
1
moves the overall half-power frequency
above f
2
.
Constructing the Bode Magnitude Plot for an Amplifier
1. Analyze the circuit with the coupling capacitors replaced by
short circuits to find the midband gain.
2. Find the break frequency due to each coupling capacitor.
3. Sketch the Bode magnitude plot by beginning in the midband
range and moving toward lower frequencies.
Introduction to Electronics 175 Design Considerations for RC-Coupled Amplifiers
Design Considerations for RC-Coupled Amplifiers
1. RC-Coupled amplifiers:
Coupling capacitors - capacitors cost $
Direct-Coupled amplifiers:
No capacitors - bias circuits interact - more difficult design, but
preferable.
2. Determine Thevenin resistance “seen” by each coupling
capacitor.
Larger resistances mean smaller and cheaper capacitors.
3. Choose f
b
for each RC circuit to meet overall -3 dB
requirement.
Judicious choice can reduce overall cost of capacitors.
4. Calculate required capacitance values.
5. Choose C values somewhat larger than calculated
(approximately 1.5 times larger).
Some C tolerances are as much as -20%, +80 %. Vales can
change with time and temperature. ±10 %
Introduction to Electronics 176 Low- & Mid-Frequency Performance of CE Amplifiers
R
S
R
1
R
2
R
C
R
EB
R
L
C
in
C
out
v
s
v
o
+
+
-
-
V
CC
Q
1
v
in
+
-
C
E
R
EF
Fig. 252. Generic single-supply common emitter ckt.
(Let R
B
= R
1
|| R
2
, R
L
’ = R
L
|| R
C
, R
E
= R
EF
+ R
EB
)
R
S
R
B
R
C
R
EB
R
L
C
in
C
out
v
s
v
o
+
+
-
-
V
CC
Q
1
v
in
+
-
C
E
R
EF
-V
EE
Fig. 253. Generic dual-supply common emitter ckt.
(Let R
L
’ = R
L
|| R
C
, R
E
= R
EF
+ R
EB
)
Low- & Mid-Frequency Performance of CE Amplifier
Introduction
We begin with two of the most common topologies of common-
emitter amplifier:
Introduction to Electronics 177 Low- & Mid-Frequency Performance of CE Amplifiers
v
s
R
S
R
B
r
R
L

βi
b
v
o
+
+
-
-
B
E
C
i
b
v
in
+
-
i
in
i
o
R
EF
R
C
R
L
R
in
Fig. 254. Generic small-signal equivalent of common emitter amplifier.
( )
A
v
v
R
r R
R
R
v
o
in
L
EF
L
EF



+ +



>>
β
β
β
π
1
1 , if
(261)
A
v
v
A
R
R R
v
o
s
v
in
S in
s

+
(262)
( )
[ ]
R
v
i
R r R
in
in
in
B EF
+ + ||
π
β 1 (263)
A
i
i
A
R
R
R
R R
R
R R
i
o
in
v
R
v
R
v
in
L
C
C L
B
B X
o
L
in
in

+ +
β (264)
Both common-emitter topologies have the same small-signal
equivalent circuit:
Midband Performance
For the equivalent circuit shown, R
o
= R
C
, but if we include the BJT
output resistance r
o
in the equivalent circuit, the calculation of R
o
becomes much more involved. We’ll leave this topic with the
assumption that R
o
R
C
. ≈
The focus has been A
v
, but we can determine A
i
also:
where R
X
= r
π
+ (β + 1)R
EF
.
Introduction to Electronics 178 Low- & Mid-Frequency Performance of CE Amplifiers
Design Considerations
G In choosing a device we should consider:
Frequency performance
Noise figure
Power Dissipation
Device choice may not be critical. . .
G Design Tradeoffs:
1. R
B
large for high R
in
and high A
i
R
B
small for bias (Q-pt.) stability
2. R
C
large for high A
v
and A
i
R
C
small for low R
o
, low signal swing, high frequency
response
3. R
EF
small (or zero) for maximum A
v
and A
i
R
EF
> 0 for larger R
in
, gain stability, improved high and
low frequency response, reduced distortion
G Gain Stability:
Note from eq. (261), as R
EF
increases, A
v
-R
L
’/R
EF
, i.e., gain ≈
becomes independent of β !!!
Introduction to Electronics 179 Low- & Mid-Frequency Performance of CE Amplifiers
v
s
R
S
R
B
r
π R
L
βi
b
v
o
+
+
-
-
B
E
C
i
b
v
in
+
-
i
in
i
o
R
EF
C
out
C
in
R
C
Fig. 255.Approximate sm. sig. equivalent of the CE amplifier at low
frequencies. The effect of C
E
is ignored by replacing it with a short circuit.
C
in
and C
out
remain so that their effect can be determined.
f
R C
b
Thevenin

1

(265)
( )
f
R R C
out
C L out

+
1

(266)
for A
v
v
f
R C
v
o
in
in
in in

1

(267)
( )
for A
v
v
f
R R C
v
o
s
in
S in in

+
1

(268)
The Effect of the Coupling Capacitors
To determine the effect of the coupling capacitors, we approximate
the small-signal equivalent as shown. C
in
and C
out
are then a part
of independent single-pole high-pass circuits, with break
frequencies of:
Thus the effect of C
out
is:
And the effect of C
in
is:
Equations for f
in
are approximate, because the effects of C
in
and C
E
interact slightly. The interaction is almost always negligible.
Introduction to Electronics 180 Low- & Mid-Frequency Performance of CE Amplifiers
v
s
R
S
R
B
r
π R
L
’ βi
b
v
o
+
+
-
-
B
E
C
i
b
v
in
+
-
i
o
R
EF
C
E
R
EB
Fig. 256. Approximate common emitter sm. sig. equivalent at low frequencies.
Only the effect of C
E
is accounted for in this circuit.
A
v
, dB
f
1
C
E
= short ckt.
C
E
= open ckt.
f
f
2
Fig. 257. Bode magnitude plot showing the effect
of C
E
only.
The Effect of the Emitter Bypass Capacitor C
E
Consider the following:
At sufficiently high frequencies, C
E
appears as a short circuit. Thus
the total emitter resistance is at its lowest, and A
v
is at its highest.
This appears like, and is, the standard single-pole high-pass effect.
At sufficiently low frequencies C
E
appears as an open circuit. The
total emitter resistance is at its highest, and A
v
is at its lowest, but
A
v
is not zero!!! Thus, there is not just a single-pole high-pass
effect. There must also be a zero at a frequency other than f = 0,
as shown below:
Introduction to Electronics 181 Low- & Mid-Frequency Performance of CE Amplifiers
R
B
r
π R
L
’ βi
b
v
o
+
-
B
E
C
i
b
v
in
+
-
i
in
i
o
R
EF
R
EB
R
thevenin
R
X
R
Y
Fig. 258. Finding Thevenin R “seen” by C
E
, assuming we are interested
in v
o
/v
in
, i.e., assuming R
S
= 0.
i
c
i
test
i
b
r βi
b
v
be
+
-
v
test
+
Fig. 259. Finding R
Y
.
( )
R R R R R R
Thevenin EB X EB EF Y
+ || || (269)
i
v
r
v
r
b
be test

π π
(270)
( )
i i
test b
− + β 1 (271)
R
v
i
r
Y
test
test

+
π
β 1
(272)
( )
R
R R r
Y
B S

+
+
||
π
β 1
(273)
To find the pole frequency f
1
we need the Thevenin resistance
“seen” by C
E
:
From inspection we should see that:
The difficulty is finding R
Y
, which is undertaken below:
If R
S
0, then R
Y
becomes: ≠
Introduction to Electronics 182 Low- & Mid-Frequency Performance of CE Amplifiers
f
C R R
r
E EB EF
1
1
2
1

+
+
|
(
'
`
J
J

]
]
]
π
β
π
||
(274)
20 log A
v mid
f
out
20 dB/dec
f
2
f
1
f
in
40 dB/dec
40 dB/dec
60 dB/dec
Fig. 260. One example of the
Bode plot of a CE amplifier.
f
C R R
r R R
E EB EF
B S
1
1
2
1

+
+
+
|
(
'
`
J
J

]
]
]
π
β
π
||
( || (275)
f
C R
E EB
2
1
2

π
(276)
Thus, for A
v
= v
o
/v
in
:
Or, for A
v
= v
o
/v
s
:
The zero f
2
is the frequency where : Z jf R
jf C
E E
E
( ) ||
2
2
1

The mathematical derivation of eq. (276) is not a focus of this
course; it is left for your own endeavor.
The Bode magnitude plot of a common
emitter amplifier is the summation of the
effects of poles f
in
, f
out
, f
1
, and the zero f
2
.
One of many possible examples is shown
at left.
Introduction to Electronics 183 The Miller Effect
Z
V
in
V
out
= A
v
V
in
+ +
- -
I
z
“Black Box”
Fig. 261. Circuit with feedback impedance Z. The
black box is usually an amplifier, but can be any
network with a common node.
V
in
V
out
= A
v
V
in
+
+
-
-
I
z
“Black Box”
Z
in, Miller
Z
out, Miller
Fig. 262. Circuit to be made equivalent to the previous
figure.
The Miller Effect
Introduction
Before we can examine the high frequency response of amplifiers,
we need some additional tools. The Miller Effect is one of them.
Consider:
It is difficult to analyze a circuit with a feedback impedance, so we
wish to find a circuit that is equivalent at the input & output ports:
If we can choose Z
in. Miller
so that I
z
is the same in both circuits, the
input port won’t “know” the difference - the circuits will be equivalent
at the input port.
Introduction to Electronics 184 The Miller Effect
( )
I
V V
Z
V A V
Z
V A
Z
Z
in o in v in
in v

− 1
(277)
I
V
Z
Z
in
in Miller

,
(278)
Z
Z
A
in Miller
v
,

− 1
(279)
Z Z
A
A
Z
A
out Miller
v
v
v
,




1
1
1
1 (280)
Deriving the Equations
From Fig. 261:
And from Fig. 262:
Setting eqs. (277) and (278) equal, and solving:
Using a similar approach, the circuits can be made equivalent at the
output ports, also, if:
Notes:
1. Though not explicitly shown in the derivation, A
v
and all
the impedances can be complex (i.e., phasors).
2. If |A
v
| is, say, 10 or larger, then Z
out, Miller
Z. ≈
3. If A
v
> 1 and real, then Z
in, Miller
is negative!!! This latter
phenomenon is used, among other things, to construct
oscillators.
Introduction to Electronics 185 The Hybrid-π BJT Model
r
π
+
-
v
π
g
m
v
π
r
o
C
µ
C
π
r
µ
r
x B C
E E
B’
Fig. 263. Hybrid-π model of BJT.
The Hybrid-π ππ π BJT Model
The Model
This is another tool we need before we examine the high frequency
response of amplifiers.
The hybrid-π BJT model includes elements that are negligible at low
frequencies and midband, but cannot be ignored at higher
frequencies of operation:
r
x
= ohmic resistance of base region, a few tens of ohms ≈
r
π
= dynamic resistance of base region, as described previously
r
o
= collector resistance of BJT, as described previously
r
µ
, C
µ
represent the characteristics of the reverse-biased collector-
base junction:
r
µ
several Megohms C
µ
1 pF to 10 pF ≈ ≈
C
π
= diffusion capacitance of b-e junction, 100 pF to 1000 pF ≈
g
m
= BJT transconductance; we can show that g
m
= β/r
π
= I
CQ
/V
T
Introduction to Electronics 186 The Hybrid-π BJT Model
r
π
+
-
v
π
g
m
v
π
r
o
C
µ
C
π
r
µ
r
x B C
E E
B’
Fig. 264. Hybrid-π model of BJT (Fig. 263 repeated).
r
π
+
-
v
π
g
m
v
π
r
o
C
π
B C
E E
B’
C
2
C
1
Fig. 265. Simplified hybrid-π BJT model using the Miller Effect and the other
assumptions described in the text..
Effect of C
π
and C
µ
Notice the small values of C
π
and C
µ
, especially when compared to
typical values of C
in
, C
out
, and C
E
.
At low and midband frequencies, C
π
and C
µ
appear as open circuits.
At high frequencies, where C
π
and C
µ
have an effect, C
in
, C
out
, and
C
E
appear as short circuits.
To focus our attention, we’ll assume r
x
0 and r
µ
, and we’ll ≈ ≈ ∞
use the Miller Effect to replace C
µ
:
Introduction to Electronics 187 The Hybrid-π BJT Model
r
π
+
-
v
π
g
m
v
π
r
o
C
π
B C
E E
B’
C
2
C
1
Fig. 266. Miller Effect applied to hybrid-π model (Fig. 265 repeated).
f
h1
f
h2
Fig. 267. Typical amplifier response in the
midband and high-frequency regions. f
h1
is
normally due to C
1
+ C
π
, and f
h2
is normally
due to C
2
.
( ) C C A A C
v v 1
1 − ≈
µ µ
(281)
C C
A
C
v
2
1
1

|
(
'
`
J
J

µ µ
(282)
f
C R
b
eq Thevenin

1

(283)
From the Miller Effect equations, (279) and (280):
Individually, all Cs in Fig. 266 have a single-pole low-pass effect.
As frequency increases they become short circuits, and v
o
approaches zero .
Thus there are two low-pass poles with the mathematical form:
Because C
1
+ C
π
>> C
2
, the pole
due to C
1
+ C
π
will dominate.
The pole due to C
2
is usually
negligible, especially when R
L
’ is
included in the circuit.
Introduction to Electronics 188 The Hybrid-π BJT Model
r
π
+
-
v
π
g
m
v
π
r
o
C
π
B C
E E
B’
C
2
C
1
Fig. 268. Miller Effect applied to hybrid-π model (Fig. 265 repeated).
( )
f f
C C R
H h
Thevenin

+
1
1
1

π
(284)
f
C R A C R
H
Thevenin v Thevenin
≈ ≈
1
2
1
2
1
π π
µ
(285)
The overall half-power frequency, then, is usually due to C
1
+ C
π
:
For typical transistors, C
1
> C
π
. For a moment, let us be very
approximate and presume that C
π
is negligibly small. Then:
i.e., f
H
is approximately inversely proportional to |A
v
| !!!
Amplifiers are sometimes rated by their Gain-Bandwidth Product,
which is approximately constant. This is especially true for high
gains where C
1
dominates.
Introduction to Electronics 189 High-Frequency Performance of the CE Amplifier
R
S
R
1
R
2
R
C
R
E
R
L
C
in
C
out
v
s
v
o
+
+
-
-
V
CC
Q
1
v
in
+
-
C
E
Fig. 269. Standard common emitter amplifier (Fig.
208 repeated).
r
π
+
-
v
π
g
m
v
π
r
o
C
µ
C
π
r
µ
r
x B C
E E
B’
v
s
R
S
+
-
v
in
+
-
R
B
= R
1
||R
2
R
L
’ = r
o
||R
L
||R
C
R
L
||R
C
Fig. 270. Amplifier small-signal equivalent circuit using hybrid-π BJT model.
High-Frequency Performance of CE Amplifier
The Small-Signal Equivalent Circuit
We now have the tools we need to analyze (actually, estimate) the
high-frequency performance of an amplifier circuit. We choose the
common-emitter amplifier to illustrate the techniques:
Now we use the hybrid-π equivalent for the BJT and construct the
small-signal equivalent circuit for the amplifier:
Introduction to Electronics 190 High-Frequency Performance of the CE Amplifier
+
-
v
π g
m
v
π
C
µ
C
π
C B’
v
s

R
S

+
-
R
L

+
-
v
o
Fig. 271. Modified small-signal equivalent, using a Thevenin
equivalent on the input side, and assuming r
µ
is infinite.
+
-
v
π
g
m
v
π
C
π
C B’
v
s

R
S

+
-
R
L

+
-
v
o
C
µ
(1+g
m
R
L
’)
Fig. 272. Final (approximate) equivalent after applying the Miller Effect.
A
v
v
g R
v
o
m L
≈ −

π
(286)
High-Frequency Performance
We can simplify the circuit further by using a Thevenin equivalent
on the input side, and by assuming the effect of r
µ
to be negligible:
Note that the Thevenin resistance R
s
’ = r
π
|| [r
x
+ (R
B
||R
S
)]
Recognizing that the dominant high-frequency pole occurs on the
input side, we endeavor only to calculate f
h1
. Thus we ignore the
effect of C
µ
on the output side, calculate the voltage gain, and apply
the Miller Effect on the input side only.
Introduction to Electronics 191 High-Frequency Performance of the CE Amplifier
+
-
v
π
g
m
v
π
C
π
C B’
v
s

R
S

+
-
R
L

+
-
v
o
C
µ
(1+g
m
R
L
’)
Fig. 273. Final (approximate) equivalent after applying the Miller Effect (Fig. 272
repeated).
f
R C
h
S total
1
1
2


π
(287)
C C C g R
total m L
+ +

|
(
'
`
J
J
π µ
1 (288)
( )
[ ]
R r r R R
S x B S

+
π
|| ||
(289)
So we have
where
and
Introduction to Electronics 192 High-Frequency Performance of the CE Amplifier
20 log A
v mid
f
out
f
2
f
h1
f
in
f
1
-20 dB/dec
20 dB/dec
40 dB/dec
40 dB/dec
60 dB/dec
Fig. 274. One example of the entire Bode magnitude response of a common
emitter amplifier.
BW f f f f
H L h
− ≈ −
1 1
(290)
The CE Amplifier Magnitude Response
Finally, we can estimate the entire Bode magnitude response of an
amplifier. . . an example:
Of this plot, the lower and upper 3-dB frequencies are the most
important, as they determine the bandwidth of the amplifier:
where the latter approximation assumes that adjacent poles are far
away.
We’ve estimated the frequency response of only one amplifier
configuration, the common-emitter. The techniques, though, can be
applied to any amplifier circuit.
Introduction to Electronics 193 Nonideal Operational Amplifiers
A
v
, dB
f, Hz
100
80
60
40
20
0
10 1 10
2
10
3
10
4
10
5
10
6
20 log A
0
f
t
= A
0
f
b
f
b
20 dB/decade
Fig. 275. Typical op amp Bode magnitude
response.
A s
A
s
f
b
( )
+
0
2
1
π
(291)
f A f A f
t b of bf

0
(292)
Nonideal Operational Amplifiers
In addition to operational voltage amplifiers, there are operational
current amplifiers and operational transconductance amplifiers
(OTAs). This discussion is limited to voltage amplifiers.
Linear Imperfections
Input and Output Impedance:
Ideally, R
in
= and R
out
= 0. ∞
Realistically, R
in
ranges from 1 MΩ in BJT op amps to 1 TΩ in ≈ ≈
FET op amps.
R
out
ranges from less than 100 Ω in general purpose op amps, to
several kΩ in low power op amps.
Gain and Bandwidth:
Ideally, A
v
= and BW = . ∞ ∞
Realistically, A
v
ranges from 80 dB (10
4
) to 140 dB (10
7
).
Many internally-compensated op amps have their BW restricted to
prevent oscillation, producing the Bode magnitude plot shown:
The transfer function, then, has a
single-pole, low-pass form:
And gain-bandwidth product is
constant:
Introduction to Electronics 194 Nonideal Operational Amplifiers
t
v
o
Expected output
Actual output
Fig. 276. Illustration of op amp slew-rate limiting.
Nonlinear Imperfections
Output Voltage Swing:
BJT op amp outputs can swing to within 2V
BE
of V
SUPPLY
. ±
FET op amp outputs an swing to within a few mV of V
SUPPLY
. ±
Output Current Limits:
Of course, currents must be limited to a “safe” value. Some op
amps have internal current limit protection.
General purpose op amps have output currents in the range of tens
of mA. For examples, the LM741 has an output current rating of
25 mA, while the LM324 can source 30 mA and sink 20 mA. ±
Slew-Rate Limiting:
This is the maximum rate at which v
O
can change, . It
dv
dt
SR
o

is caused by a current source driving the compensation capacitor.
As an example, the LM741 has a SR of 0.5 V/µs. ≈
Introduction to Electronics 195 Nonideal Operational Amplifiers
v t V t
dv
dt
SR V fV
o OM
o
OM OM
( ) sin
max
⇒ ω ω π 2 (293)
f
SR
V
FP
OM


(294)
Full-Power Bandwidth:
This is defined as the highest frequency for which an undistorted
sinusoidal output is obtainable at maximum output voltage:
Solving for f and giving it a special notation:
DC Imperfections:
Many of the concepts in this section are rightly credited to Prof. D.B.
Brumm.
Input Offset Voltage, V
IO
:
v
O
is not exactly zero when v
I
= 0. The input offset voltage V
IO
is
defined as the value of an externally-applied differential input
voltage such that v
O
= 0. It has a polarity as well as a magnitude.
Input Currents:
Currents into noninverting and inverting inputs are not exactly zero,
but consist of base bias currents (BJT input stage) or gate leakage
currents (FET input stage):
I
I
+
, current into noninverting input
I
I
-
, current into inverting input
These also have a polarity as well as a magnitude.
Introduction to Electronics 196 Nonideal Operational Amplifiers
+
- v
-
v
+
+ -
V
IO
ideal
op amp
I
B
-

I
IO
/2 I
B
+

I
IO
/2
i=0
i=0
I
I
-
I
I
+
v
O
Fig. 277. DC error model of operational amplifier.
I
I I
I I I
B
I I
IO I I

+

+ −
+ −
2
and
(295)
In general, I
I
+
I
I
-
, so we define the input bias current as the ≠
average of these, and the input offset current as the difference:
Data sheets give maximum magnitudes of these parameters.
Modeling the DC Imperfections
The definitions of
G input offset voltage, V
IO
G input bias current, I
B
G and, input offset current, I
IO
lead to the following dc error model of the operational amplifier:
Introduction to Electronics 197 Nonideal Operational Amplifiers
+
+
-
-
R
N
R
F
R
+
v
IN
Fig. 278. Noninverting op amp
configuration.
+
+
-
-
R
N
R
F
R
+
v
IN
Fig. 279. Inverting op amp
configuration.
+
-
R
N
R
F
R
+
Fig. 280. Identical circuits result when the
sources of Figs. 278 and 279 are set to
zero.
Using the DC Error Model
Recall the standard noninverting and inverting operational amplifier
configurations. Note the presence of the resistor R
+
. It is often
equal to zero, especially if dc error does not matter.
Notice that these circuits become identical when we set the
independent sources to zero:
Introduction to Electronics 198 Nonideal Operational Amplifiers
+
-
V
OE
R
F
R
+
+
-
V
IO
I
+
I
-
R
N
Fig. 282. Op amp noninverting and
inverting amplifiers, external source set to
zero, using dc error model.
+
- v
-
v
+
+ -
V
IO
ideal
op amp
I
B
-

I
IO
/2 I
B
+

I
IO
/2
i=0
i=0
I
I
-
I
I
+
v
O
Fig. 281. DC error op amp model (Fig. 277
repeated).
Now, recall the dc error op amp model:
And replace the ideal op amp of Fig. 280 with this model:
With the help of Thevenin equivalents, virtually all op amp circuits
reduce to Fig. 282 when the external sources are set to zero !!!
Introduction to Electronics 199 Nonideal Operational Amplifiers
+
-
V
OE
R
F
R
+
+
-
V
IO
I
+
I
-
R
N
Fig. 283. Op amp configurations, with external
source set to zero, using dc error model. (Fig.
282 repeated)
v V R I
IO
+ + +
− −
(296)
( ) V
R
R
V R I
OE
F
N
IO , Part A
− +
|
(
'
`
J
J +
+ +
1
(297)
Note that the source V
IO
can
be “slid” in series anywhere in
the input loop.
Also note carefully the polarity
of V
IO
.
And, finally, note that the dc
error current sources have
been omitted for clarity.
Currents resulting from these
sources are shown in red.
We can now determine the dc output error for virtually any op amp
configuration. We have already noted the dc output error as V
OE
.
Using superposition, we’ll first set I
-
to zero. The voltage at the
noninverting input is
This voltage is simply the input to a noninverting amplifier, so the dc
output error, from these two error components alone, is:
Introduction to Electronics 200 Nonideal Operational Amplifiers
+
-
V
OE
R
F
R
+
+
-
V
IO
I
+
I
-
R
N
Fig. 284. Op amp configurations, with external
source set to zero, using dc error model. (Fig.
282 repeated)
V R I
OE F , Part B


(298)
V
R R
R
R
R R
R I
R
R
R I
OE
N F
N
N
N F
F
F
N
, Part B

+
+
+
|
(
'
`
J
J
− − −
1 (299)
R
R
R R
R R R
N
N F
F F N

+
||
(300)
( ) V
R
R
V R I R I
OE
F
N
IO
− +
|
(
'
`
J
J + −
+ + − −
1
(301)
Next, we consider just I
-
, i.e.,
we let V
IO
= 0 and I
+
= 0.
Now v
+
= v
-
= 0, so there is no
current through R
N
.
The current I
-
must flow
through R
F
, creating the dc
output error component:
Now we make use of a mathematical “trick.” To permit factoring, we
write (298) as:
where
And, finally, we combine (297) and (299) to obtain the totally
general result:
Introduction to Electronics 201 Nonideal Operational Amplifiers
+
+
-
-
v
IN
v
O
10 kΩ 100 kΩ
Fig. 285. DC output error example.
[ ]
I
B
∈ 0 100 , nA (302)
[ ]
I
IO
∈ −40 40 , nA (303)
[ ]
V
IO
∈ −2 2 , mV (304)
( ) V
R
R
V R I
OE
F
N
IO
− +
|
(
'
`
J
J −
− −
1
(305)
DC Output Error Example
The maximum bias current is
100 nA, i.e.,
A positive value for I
B
means
into the chip.
The maximum offset current magnitude is 40 nA, i.e.,
Note that the polarity of I
IO
is unknown.
The maximum offset voltage magnitude is 2 mV, i.e.,
Note also that the polarity of V
IO
is unknown.
Finding Worst-Case DC Output Error:
G Setting v
IN
to 0, and comparing to Fig. 282 and eq. (301):
where (1 + R
F
/R
N
) = 11, and R
-
= 9.09 kΩ.
Note the missing term because R
+
= 0.
Introduction to Electronics 202 Nonideal Operational Amplifiers
( )( )
V
OE
− − 11 2 22 mV - 0 mV (306)
( ) ( )( )
[ ]
V
OE
− − + 11 2 120 34 mV - 9.09 k nA mV Ω (307)
G The term (V
IO
- R
-
I
-
) takes its largest positive value for
V
IO
= +2 mV and I
-
= 0 (we cannot reverse the op amp input
current so the lowest possible value is zero):
Thus, from eq. (305):
G The term (V
IO
- R
-
I
-
) takes its largest negative value for
V
IO
= -2 mV and I
-
= 100 nA + 40 nA/2 = 120 nA.
Thus from eq. (305):
G Thus we know V
OE
will lie between -22 mV and +34 mV.
Without additional knowledge, e.g., measurements on a particular
chip, we can not determine error with any higher accuracy.
Introduction to Electronics 203 Nonideal Operational Amplifiers
( ) V
R
R
V R I R I
OE
F
N
IO
− +
|
(
'
`
J
J + −
+ + − −
1
(308)
( ) ( )
V
R
R
V R I
I
R I
I
R
R
V R R I R R
I
OE
F
N
IO B
IO
B
IO
F
N
IO B
IO
− +
|
(
'
`
J
J + +
|
(
'
`
J
J − −
|
(
'
`
J
J

]
]
]
− +
|
(
'
`
J
J + − + +

]
]
]
+ −
+ − + −
1
2 2
1
2
(309)
R R R R
F N
+ −
||
(310)
Canceling the Effect of the Bias Currents:
Consider the complete dc error equation (301), repeated below:
If we knew the exact values of I
+
and I
-
we could choose the
resistances R
+
and R
-
so that these terms canceled. However, we
can’t know these values in general.
We do however know the value of input bias current, I
B
.
Rewriting (308) to show the effect of the bias currents:
Thus, we can eliminate the effect of I
B
if we select
This makes the average error due to currents be zero.
Introduction to Electronics 204 Instrumentation Amplifier
R
2
R
3
R
1
R
4
v
2
v
1
v
O
+
-
v
ID
+
-
Fig. 286. Difference amplifier.
( )
v
R
R
v v
O

2
1
1 2
(311)
R
R
R
R
v
2
v
1
v
O
+
-
R
2
R
2
R
1
R
1
+
+
-
-
+
-
v
ID
+
-
v
Y
+
-
v
ID
Fig. 287. Instrumentation amplifier.
Instrumentation Amplifier
Introduction
Recall the basic op amp
difference amplifier:
only if:
R
R
R
R
4
3
2
1

To obtain high CMRR, R
4
/R
3
and R
2
/R
1
must be very closely
matched. But this is impossible, in general, as we usually don’t
know the internal resistances of v
1
and v
2
with certainty or
predictability.
The solution is an instrumentation-quality differential amplifier!!!
Introduction to Electronics 205 Instrumentation Amplifier
R
R
R
R
v
2
v
1
v
O
+
-
R
2
R
2
R
1
R
1
+
+
-
-
+
-
v
ID
+
-
+
-
v
ID
Fig. 288. Instrumentation amplifier (Fig. 287
repeated).
i
v
R
R
ID
1
2
1

(312)
( )
v v
R
R
v v
O Y
+
|
(
'
`
J
J
− 1
2
1
1 2
(313)
Simplified Analysis
The input op amps present infinite input impedance to the
sources, thus the internal resistances of v
1
and v
2
are now
negligible.
Because the op amps are ideal v
ID
appears across the series
R
1
resistances. Current through these resistances is:
This current also flows through R
2
. The voltage v
Y
is the sum
of voltages across the R
1
and R
2
resistances, and the 2
nd
stage
is a difference amplifier with unity gain. Thus:
Instrumentation amplifiers are available in integrated form,
both with and without the R
1
resistances built-in.
Introduction to Electronics 206 Noise
p kTB
n
4 (314)
e kTRB
r
4
(315)
4 0127 kTR R .
nV
Hz
(316)
Noise
We can define “noise” in two different ways:
1. Any undesired component in the signal (e.g., radio-frequency
interference, crosstalk, etc.)
2. Random inherent mechanisms.
Johnson Noise
This is noise generated across a resistor’s terminals due to random
thermal motion of electrons.
Johnson noise is white noise, meaning it has a flat frequency
spectrum - the same noise power in each Hz of bandwidth:
where, k = Boltzmann’s constant = 1.38 x 10
-23
J/K,
T = resistor temperature in kelvins
B = measurement bandwidth in Hz.
The open-circuit rms noise voltage across a resistor R is:
From eq. (315), at T
room
= 293 K:
This means that, if we have a perfect, noiseless BPF with
BW = 10 kHz, and V
in
is the noise voltage of a 10 kΩ resistance at
T
room
, we would measure an output voltage V
OUT
of 1.27 µV with an
ideal (noiseless) true-rms voltmeter.
Introduction to Electronics 207 Noise
I qI B
r DC
2
(317)
Johnson noise is random. The instantaneous amplitude is
unpredictable and must be described probabilistically.
It follows a Gaussian distribution with a mean value of zero. This
amplitude distribution has a flat spectrum with very “sharp”
fluctuations.
Johnson Noise Model:
A voltage source e
r
in series with a resistance R.
The significance of Johnson noise is that it sets a lower bound on
the noise voltage present in any amplifier, signal source, etc.
Shot Noise
Shot noise arises because electric current flows in discrete charges,
which results in statistical fluctuations in the current.
The rms fluctuation is a dc current I
DC
is given by:
where, q = electron charge = 1.60 x 10
-19
C
B = measurement bandwidth in Hz.
Introduction to Electronics 208 Noise
Shot Noise, 10 kHz measurement bandwidth, from eq. (317)
I
DC
I
r
% fluctuation
1 A 57 nA 0.0000057%
1 µA
57 pA 0.0057% (-85 dB)
1 pA 57 fA 5.6%
Eq. (317) assumes that the charge carriers act independently.
This is true for charge carriers crossing a barrier (e.g., a junction
diode).
This is false for current in metallic conductor (e.g. a simple resistive
circuit). For this latter case, actual noise is less than that given in
eq. (317), i.e., the model gives a pessimistic estimate for design
purposes.
1/f Noise (Flicker Noise)
This is additional, or excess, noise found in real devices, caused by
various sources.
1/f noise is pink noise - it has a 1/f spectrum, which means equal
power per decade of bandwidth, rather than equal power per Hz.
Introduction to Electronics 209 Noise
As an example, let’s look at 1/f noise in resistors:
Fluctuations in resistance result in an additional noise voltage which
is proportional to the current flowing in the resistance.
The amount of additional noise depends on resistor construction.
The table below lists the excess noise for various resistor types.
The entries are given in rms voltage, per volt applied across the
resistor, and measured over one decade of bandwidth:
Carbon-composition
0.10 µV/V to 3 µV/V
Carbon-film
0.05 µV/V to 0.3 µV/V
Metal-film
0.02 µV/V to 0.2 µV/V
Wire-wound
0.01 µV/V to 0.2 µV/V
Other mechanisms producing 1/f noise:
G Base current noise in transistors.
G Cathode current noise in vacuum tubes.
G Speed of ocean currents.
G Flow of sand in an hourglass.
G Yearly flow of the Nile (measured over past 2000 years).
G Loudness of a piece of classical music vs. time.
Introduction to Electronics 210 Noise
Interference
In this case any interfering signal or unwanted “stray” pickup
constitutes a form of noise.
The frequency spectrum and amplitude characteristics depend on
type of interference:
Sharp spectrum, relatively constant amplitude:
60 Hz interference.
Radio and television stations.
Broad spectrum, probabilistic amplitude:
Automobile ignition noise.
Lightning.
Motors, switches, switching regulators, etc.
Some circuits, detectors, cables, etc., are microphonic:
Noise voltage or current is generated as a result of vibration.
Introduction to Electronics 211 Amplifier Noise Performance
Noiseless
e
n
i
n
v
sig
R
sig
+
Noisy amplifier
Fig. 289. Noise model of an amplifier.
Amplifier Noise Performance
Terms, Definitions, Conventions
Any noisy amplifier can be completely specified for noise in terms
of two noise generators, e
n
and i
n
:
Amplifier Noise Voltage:
Amplifier noise voltage is more properly called the equivalent short-
circuit input rms noise voltage.
e
n
is the noise voltage that appears to be present at an amplifier
input if the input terminals are shorted. It is equivalent to a noisy
offset voltage, and is expressed in nV / at a specific frequency. Hz
It is measured by:
G shorting the amplifier input,
G measuring the rms noise output,
G dividing by amplifier gain (and further dividing by ). B
e
n
increases at lower frequencies, so it appears as 1/f noise.
Introduction to Electronics 212 Amplifier Noise Performance
SNR
P
P
sig
n

|
(
'
`
J
J
10log dB (318)
SNR
v
e
sig
n

|
(
'
`
J
J
20log dB (319)
Amplifier Noise Current:
Amplifier noise current is more properly called the equivalent open-
circuit input rms noise current.
i
n
is the apparent noise current at an amplifier input. It is equivalent
to a noisy bias current, and is expressed in pA / at a specific Hz
frequency.
It is measured by:
G shunting the amplifier input with a resistor,
G measuring the rms noise output,
G dividing by amplifier gain (and further dividing by ), B
G “subtracting” noise due to e
n
and the resistor (we discuss
adding and subtracting noise voltages later).
i
n
increases at lower frequencies for op amps and BJTs - it
increases at higher frequencies for FETs.
Signal-to-Noise Ratio:
Expressed in decibels, the default definition is a ratio of signal
power to noise power (delivered to the same resistance, and
measured with the same bandwidth and center frequency):
It can also be expressed as the ratio of rms voltages:
Introduction to Electronics 213 Amplifier Noise Performance
A
v
V
n
R
S
(T = 0) Real (noisy)
Amplifier
Fig. 290. Noisy amplifier with ideal
input.
A
v
V
n
R
S
(T = T
n
) Noiseless
Amplifier
Fig. 291. Ideal amplifier with noisy
input.
( )
( )
NF
P P
P P
sig n
input
sig n
output

]
]
]
]
10log
/
/
dB (320)
NF SNR SNR
input output
− (321)
Noise Figure:
This is a figure of merit for comparing amplifiers. It indicates how
much noise an amplifier adds.
Defined simply:
It can be written even more simply:
Note that NF will always be greater than 0 dB for a real amplifier.
Noise Temperature:
An alternative figure of merit to noise figure, it gives the same
information about an amplifier. The definition is illustrated below:
A real amplifier (Fig. 290) that produces v
n
at its output with a
noiseless input, has the noise temperature T
n
.
An ideal, noiseless amplifier (Fig. 291) with a source resistance at
T = T
n
produces the same noise voltage at its output.
Introduction to Electronics 214 Amplifier Noise Performance
( )
T T NF
T
T
n
NF
n
− ⇔ +
|
(
'
`
J
J
10 1 10 1
10 /
log (322)
v v e
total sig n
2 2 2
+
(323)
Converting NF to/from T
n
:
where, NF is expressed in dB
T is the ambient (room) temperature, usually 290 K
For good, low-noise amplifier performance:
NF << 3 dB and/or T
n
<< 290 K
Adding and Subtracting Uncorrelated Quantities
This applies to operations such as noise noise, or noise signal. ± ±
Because noise is probabilistic, we don’t know instantaneous
amplitudes. As a result we can only add and subtract powers.
This means squared amplitudes add (rms amplitudes do not), e.g.:
Introduction to Electronics 215 Amplifier Noise Calculations
Noiseless
e
n
i
n
v
sig
R
sig
+
Noisy amplifier
Fig. 292. Noise model of an amplifier (Fig. 289 repeated).
e e e i R
t r n n sig
2 2 2 2 2
+ +
(324)
e e i R
eq n n sig
2 2 2 2
+
(325)
Amplifier Noise Calculations
Introduction
Repeating our amplifier noise model:
We presume the input resistance of the noiseless amplifier is much
larger than R
sig
, and describe the following amplifier noise sources:
e
r
, the Johnson noise of R
sig
,
e
n
,the amplifier noise source (amplifier noise referred to the input),
i
n
R
sig
, the noise voltage resulting from i
n
flowing through R
sig
The total input noise is (assuming they are uncorrelated):
For convenience, we define the last two terms of eq. (324) as the
equivalent amplifier input noise, i.e., the amplifier noise contribution
with a noise-free R
sig
:
Introduction to Electronics 216 Amplifier Noise Calculations
( )
( )
( )
( )
NF
P P
P P
P P
P P
P G e
e P G
e
e
e e i R
e
e i R
e
sig n
input
sig n
output
sig input n output
n input sig output
sig input p t
r sig input p
t
r
r n n sig
r
n n sig
r

]
]
]
]

×
×
|
(
'
'
`
J
J
J

]
]
]
]

|
(
'
`
J
J
+ +
|
(
'
'
`
J
J
J
+
+
|
(
'
'
`
J
J
J

10 10
10 10 10
10 1 10
2
2
2
2
2 2 2 2
2
2 2 2
2
log
/
/
log
log log log
log log 1
2
2
+
|
(
'
`
J
J
e
e
eq
r
(326)
Calculating Noise Figure
The noise figure of this amplifier may now be calculated. We use
the definition of NF as the ratio of powers, and let G
p
represent the
amplifier power gain:
Observe that for small R
sig
, amplifier noise voltage dominates, while
for large R
sig
, the amplifier noise current dominates.
FET amplifiers have nearly zero noise current, so they have a clear
advantage !!!
Remember, NF data must include values of R
sig
and frequency to
have significance.
Introduction to Electronics 217 Typical Manufacturer’s Noise Data
Fig. 293. 2N5210 noise voltage vs.
frequency, for various quiescent collector
currents.
Fig. 294. 2N5210 noise current vs. frequency,
for variousquiescent collector currents.
Fig. 295. 2N5210 total noise voltage at 100 Hz
vs. source resistance, for various quiescent
collector currents
Typical Manufacturer’s Noise Data
Introduction
Manufacturers present noise data in various ways. Here is some
typical data for Motorola’s 2N5210 npn BJT:
Introduction to Electronics 218 Typical Manufacturer’s Noise Data
e e e i R
t r n n sig
2 2 2 2 2
+ +
(327)
e
t
697 . nV / Hz
(328)
The e
n
, i
n
data of Figs. 293 and 294 can be used to construct
Fig. 295, a plot of total noise voltage, e
t
, for various values of R
sig
.
We simply follow eq. (324), repeated here:
Example #1
Calculate the total equivalent input noise per unit bandwidth, for a
2N5210 operating at 100 Hz with a source resistance of 1 kΩ, and
a collector bias current of 1 mA:
1. e
r
4.02 nV / from eq. (316). ≈ Hz
2. e
n
4.5 nV / (f = 100 Hz, I
C
= 1 mA) from Fig. 293. ≈ Hz
3. i
n
3.5 pA / (f = 100 Hz, I
C
= 1 mA) from Fig. 294. ≈ Hz
Evaluating eq. (327) - remembering to square the terms on the
right-hand side, and take the square root of the resulting sum -
gives :
This compares favorably (within graphical error) with a value slightly
greater than 7 nV / obtained from Fig. 295. Hz
Of course, it would take many calculations of this type to produce
the curves of Fig. 295.
Introduction to Electronics 219 Typical Manufacturer’s Noise Data
NF
e i R
e
n n sig
r
+
+
|
(
'
'
`
J
J
J
10 1
2 2 2
2
log (329)
Fig. 296. 2N5210 100-Hz noise figure vs.
source resistance, at various quiescent
collector currents.
( )
( )
( )
NF +
|
(
'
'
`
J
J
J
10 1
570
402
10 301 479
2
2
log
.
.
log . . dB (330)
Example #2
Determine the narrow bandwidth noise figure for the amplifier of
example #1 (f = 100 Hz, I
CQ
= 1 mA, R
sig
= 1 kΩ).
1. From eq. (326), repeated here
with the values of e
n
, i
n
, and e
r
from example #1, we calculate:
which compares favorably to the value of approx. 5 dB obtained
from the manufacturer’s data shown below:
Introduction to Electronics 220 Noise - References and Credits
Noise - References and Credits
References for this section on noise are:
1. Noise Specs Confusing?, Application Note 104, National
Semiconductor Corp., May 1974.
This is an excellent introduction to noise. I highly recommend
that you get a copy. It is available on National’s website at
http://www.national.com
2. The Art of Electronics, 2
nd
ed., Paul Horowitz and Winfield Hill,
Cambridge University Press, New York, 1989.
This text has a good treatment of noise, and makes a good
general electronics reference. Check it out at
http://www.artofelectronics.com
3. The 2N5210 data sheets, of which Figs. 293 - 296 are a part,
are available from Motorola, Inc., at http://www.motorola.com
Introduction to Electronics 221 Introduction to Logic Gates
V
DC
V
O
V
I
Fig. 297. Logic inverter. DC supply
connections are not normally shown.
V
O
V
I
V
DC
V
DC V
DC
/2
ideal
actual
Fig. 298. Ideal and actual inverter transfer
functions.
Introduction to Logic Gates
The Inverter
We will limit our exploration to the logic inverter, the simplest of
logic gates. A logic inverter is essentially just an inverting amplifier,
operated at its saturation levels:
The Ideal Case
V
I
is either V
DC
(logic 1) or zero (logic 0).
V
O
is either zero (logic 0) or V
DC
(logic 1).
The Actual Case
We don’t know the exact transfer function of any individual logic
inverter.
Manufacturer’s specifications give us a clue about the “range” of
permitted input and output levels.
Introduction to Electronics 222 Introduction to Logic Gates
V
O
V
I
V
DC
V
DC
V
OH
V
OL
V
IH
V
IL
tr. fn. forbidden regions
Fig. 300. Mfr’s voltage specs illustrated with
example transfer functions.
V
DC
V
OH
V
IH
V
IL
V
OL
0
Output:
Logic 1
Output: Logic 0
Input sees
Logic 1
Input sees
Logic 0
NM
H
NM
L
Fig. 299. Mfr’s voltage specs illustrated
on a number line.
NM V V NM V V
H OH IH L IL OL
− − and (331)
Manufacturer’s Voltage Specifications
G V
IH
= lowest V
I
guaranteed to be “seen” as “high” (logic 1).
G V
IL
= highest V
I
guaranteed to be “seen” as “low” (logic 0).
And with V
I
meeting the above specifications:
G V
OH
= lowest “high” (logic 1) output voltage.
G V
OL
= highest “low” (logic 0) output voltage.
Noise Margin
Noise margin is the maximum noise amplitude that can be added
to the input voltage, without causing an error in the output logic
level. It is the smaller of:
Introduction to Electronics 223 Introduction to Logic Gates
Fig. 301. Reference directions for mfr’s current
specifications.
Fig. 302. Fan-out illustrated.
FO
I
I
H
OH
IH

|
(
'
`
J
J int (332)
FO
I
I
L
OL
IL

|
(
'
`
J
J int (333)
Manufacturer’s Current Specifications
Note that the reference
direction for both input and
output currents is into the chip.
G I
OH
= highest current that output can source with V
O
V
OH
. ≥
G I
OL
= highest current that output can sink with V
O
V
OL
. ≤
G I
IH
= highest possible input current with V
I
V
IH
. ≥
G I
IL
= highest possible input current with V
I
V
IL
. ≤
Fan-Out
Fan-out is defined as the maximum number of gates that can be
driven without violating the voltage specifications. It must be an
integer, of course; it is the smaller of:
and
Introduction to Electronics 224 Introduction to Logic Gates
V
DC
V
O
R
HIGH
R
LOW
C
LOAD
S
Fig. 303. Simple model of logic
gate output.
Q C V
LOAD DC
(334)
E QV C V
DC LOAD DC

2
(335)
Power Consumption
Static Power Consumption:
The static power is the power required to run the chip when the
output isn’t changing.
It may be different when the output is high may be different than
when the output is low. Thus, we normally assume that it is merely
the average of the two.
Dynamic Power Consumption:
Because load capacitance is always present, additional power is
required when the output is changing states.
To understand this, consider the following logic gate model, and
presume the switch begins in the low position.
When the switch goes high, C
LOAD
charges from V
OL
( 0) to ≈
V
OH
( V
DC
). ≈
At the end of this charging cycle, the
charge stored in C
LOAD
is:
And the energy required of V
DC
to deliver
this charge is:
Introduction to Electronics 225 Introduction to Logic Gates
V
DC
V
O
R
HIGH
R
LOW
C
LOAD
S
Fig. 304. Logic gate model (Fig.
303 repeated).
E C V
C LOAD DC

1
2
2
(336)
C V
T
C V f
LOAD DC
LOAD DC
2
2

(337)
P C V f
dynamic LOAD DC

2
(338)
Of the energy required of V
DC
, half is
stored in the capacitor:
The remaining half of the energy required
of V
DC
has been dissipated as heat in
R
HIGH
.
Now the switch changes state, i.e., goes
low. C
LOAD
discharges toward V
OL
( 0), ≈
and the energy stored in C
LOAD
is
dissipated in R
LOW
.
Finally, suppose V
O
is continually changing states, with a frequency
f (i.e., with period T). The energy dissipated in the gate per period
is:
But energy per unit time is power, i.e., the dynamic power
dissipation:
Introduction to Electronics 226 Introduction to Logic Gates
V
OH
V
OL
100%
90%
50%
10%
0%
v
I
t
t
r
t
f
v
O
t
t
PHL
t
PLH
V
OH
V
OL
50%
Fig. 305. Generic examples of rise time, fall time, and
propagation delay.
Rise Time, Fall Time, and Propagation Delay
We use the following definitions to describe logic waveforms:
t
r
, rise time - time interval for a waveform to rise from 10% to
90% of its total change
t
f
, fall time - time interval for a waveform to fall from 90% to 10%
of its total change
t
PHL
and t
PLH
, propagation delay -
time interval from the 50% level of the input
waveform to 50% level of the output
t
PD
, average propagation delay -
simply, the average of t
PHL
and t
PLH
Introduction to Electronics 227 Introduction to Logic Gates
Speed-Power Product
The speed-power product provides a “figure of merit” of a logic
family.
It is defined as the product of propagation delay (speed) and static
power dissipation (power) per gate
Note this product has units of energy.
Currently, the speed-power product of logic families range from
approximately from 5 pJ to 50 pJ
Introduction to Electronics 228 Introduction to Logic Gates
TTL Logic Families & Characteristics
hex inverter ⇒ 7404 74S04 74LS04 74AS04 74ALS04 74F04
p
a
r
a
m
e
t
e
r
u
n
i
t
s
t
a
n
d
a
r
d
S
S
c
h
o
t
t
k
y
L
S
l
o
w
-
p
o
w
e
r

S
A
S
a
d
v
a
n
c
e
d

S
A
L
S
a
d
v
a
n
c
e
d

L
S
F
F
A
S
T
t
PD
ns 10 3 10 2 4 3
P
static
mW 10 19 2 7 1 4
I
OH
µA
-400 -1000 -400 -2000 -400 -1000
I
OL
mA 16 20 8 20 8 20
I
IH
µA
40 50 20 20 20 20
I
IL
mA -1.6 -2.0 -0.4 -0.5 -0.1 -0.6
V
OH
V 2.4 2.7 2.7 3.0 3.0 2.7
V
OL
V 0.4 0.5 0.5 0.5 0.5 0.5
V
IH
V 2.0 V for all TTL families
V
IL
V 0.8 V for all TTL families
. . . table compiled by Prof. D.B. Brumm
Introduction to Electronics 229 Introduction to Logic Gates
CMOS Logic Families & Characteristics
These are typical examples of the guaranteed values for V
DC
= 5 V,
and are specifications for driving auxiliary loads, not other gates
alone..
Output current ratings depend upon the specific gate type, esp. in
the 4000 series.
Ratings for I
OH
and I
OL
are given for the specific V
OH
and V
OL
.
p
a
r
a
m
e
t
e
r
u
n
i
t
4
0
0
0
7
4
C
7
4
H
C
7
4
H
C
T
A
C
A
C
T
t
PD
ns 80 90 9 10 5 5
P
static
< 1 µW for all versions
I
OH
mA -1.0 -0.36 -4.0 -4.0 -24 -24
I
OL
mA 2.4 0.36 4.0 4.0 24 24
I
IH
µA
1.0 1.0 1.0 1.0 1.0 1.0
I
IL
mA -1.0 -1.0 -1.0 -1.0 -1.0 -1.0
V
OH
V 2.5 2.4 3.5 3.5 3.7 3.7
V
OL
V 0.4 0.4 0.4 0.4 0.4 0.4
V
IH
V 3.5 3.5 3.5 2.0 3.5 2.0
V
IL
V 1.5 1.5 1.0 0.8 1.5 0.8
V
DC
V 3 - 15 3 - 15 2 - 6 5±0.5 2 - 6 5±0.5
. . . table compiled by Prof. D.B. Brumm
Introduction to Electronics 230 MOSFET Logic Inverters
V
DD
V
I
V
O
R
pull-up
Fig. 306. NMOS inverter with
resistive pull-up for the load.
Drain Voltage, V
DS
V
GS
= 3 V
V
GS
= 4 V
V
GS
= 5 V
V
GS
= 6 V
8 V V
GS
= 7 V 9 10 V
Fig. 307. Ideal FET output characteristics, and load line for
V
DD
= 10 V and R
pull-up
= 10 kΩ.
D
r
a
i
n

C
u
r
r
e
n
t
,

I
D
MOSFET Logic Inverters
NMOS Inverter with Resistive Pull-Up
As Fig. 306 shows, this is the most basic of inverter circuits.
Circuit Operation:
The term NMOS implies an n-channel enhancement MOSFET.
Using a graphical analysis technique, we can plot the load line on
the output characteristics, shown below.
When the FET is operating in its triode region, it pulls the output
voltage low, i.e., toward zero. When the FET is in cutoff, the drain
resistance pulls the output voltage up, i.e., toward V
CC
, which is why
it is called a pull-up resistor.
Because V
GS
= V
I
and V
DS
= V
O
, we can use Fig. 307 to plot the
transfer function of this inverter.
Introduction to Electronics 231 MOSFET Logic Inverters
Input Voltage, V
I
Fig. 308. Inverter transfer function.
Drawbacks:
1. A large R results in reduced V
O
for anything but the largest
loads, and slows output changes for capacitive loads.
2. A small R results in excessive current, and power dissipation,
when the output is low.
The solution to both of these problems is to replace the pull-up
resistor with an active pull-up.
O
u
t
p
u
t

V
o
l
t
a
g
e
,

V
O
Introduction to Electronics 232 MOSFET Logic Inverters
V
DD
V
I
V
O
D
D
S
S
G
G
v
GSN
v
SGP
+
+
+
-
-
-
v
SDP
v
DSN
+
-
Fig. 309. CMOS inverter.
Drain-Source Voltage of NMOS FET, V
DSN
V
GSN
= 3 V
V
GSN
= 4 V
V
GSN
= 5 V
V
GSN
= 6 V
V
GSN
= 7 V 8 V 10 V 9
Fig. 310. Ideal NMOS output characteristics.
D
r
a
i
n

C
u
r
r
e
n
t
,

I
D
CMOS Inverter
Circuit Operation:
The CMOS inverter uses an active pull-up,
a PMOS FET in place of the resistor.
The PMOS and NMOS devices are
complementary MOSFETs, which gives rise
to the name CMOS.
In the previous example, the resistor places
a load line on the NMOS output
characteristic.
Here, the PMOS FET places a load curve on the output
characteristic. The load curve changes as V
I
changes !!!
The NMOS output curves are the usual fare, and are shown in the
figure below:
Introduction to Electronics 233 MOSFET Logic Inverters
V
SGP
= 3 V
V
SGP
= 4 V
V
SGP
= 5 V
V
SGP
= 6 V
V
SGP
= 7 V 8 V 10 V 9
Source-Drain Voltage of PMOS FET, V
SDP
Fig. 311. Ideal PMOS output characteristics.
v V v
SGP DD GSN
− (339)
v V v
SDP DD DSN
− (340)
D
r
a
i
n

C
u
r
r
e
n
t
,

|
I
D
|
The PMOS output curves, above, are typical also, but on the input
side of the PMOS FET:
This means we can re-label the PMOS curves in terms of v
GSN
.
And, on the output side of the PMOS FET:
This means we can “rotate and shift” the curves to display them in
terms of v
DSN
. This is done on the following page.
Introduction to Electronics 234 MOSFET Logic Inverters
V
DSN
(= 10 V - V
SDP
)
V
GSN
= 7 V (V
SGP
= 3 V)
V
GSN
= 6 V (V
SGP
= 4 V)
V
GSN
= 5 V (V
SGP
= 5 V)
V
GSN
= 4 V (V
SGP
= 6 V)
V
GSN
= 3 V 2 V 0 V 1
Fig. 312. PMOS “load curves” for V
DD
= 10 V.
D
r
a
i
n

C
u
r
r
e
n
t
,

|
I
D
|
The curves above are the same PMOS output characteristics of Fig.
233, but they’ve been:
1. Re-labeled in terms of v
GSN
.
2. Rotated about the origin and shifted to the right by 10 V (i.e.,
displayed on the v
DSN
axis).
Introduction to Electronics 235 MOSFET Logic Inverters
V
GSN
= 7 V
V
GSN
= 6 V
V
GSN
= 5 V
V
GSN
= 4 V
V
GSN
= 3 V 2 V 0 V 1
V
GSN
= 3 V
V
GSN
= 4 V
V
GSN
= 5 V
V
GSN
= 6 V
V
GSN
= 7 V 8 V 10 V 9
NMOS Drain-Source Voltage, V
DSN
Fig. 313. NMOS output characteristics (in blue) and PMOS load
curves (in green) plotted on same set of axes.
D
r
a
i
n

C
u
r
r
e
n
t
,

|
I
D
|
We can now proceed with a graphical analysis to develop the
transfer characteristic. We do so in the following manner:
1. We plot the NMOS output characteristics of Fig. 310, and the
PMOS load curves of Fig. 312, on the same set of axes.
2. We choose the single correct output characteristic and the
single correct load curve for each of several values of v
I
.
3. We determine the output voltage from the intersection of the
output characteristic and the load curve, for each value of v
I
chosen in the previous step.
4. We plot the v
O
vs. v
I
transfer function using the output voltages
determined in step 3.
The figure below shows the NMOS output characteristics and the
PMOS load curves plotted on the same set of axes:
Introduction to Electronics 236 MOSFET Logic Inverters
NMOS Drain-Source Voltage, V
DSN
V
I
= V
GSN
= 3 V
Fig. 314. Appropriate NMOS and PMOS curves for v
I
= 3 V.
V
I
= V
GSN
= 4 V
NMOS Drain-Source Voltage, V
DSN
Fig. 315. Appropriate NMOS and PMOS curves for v
I
= 4 V.
D
r
a
i
n

C
u
r
r
e
n
t
,

|
I
D
|
D
r
a
i
n

C
u
r
r
e
n
t
,

|
I
D
|
Note from Fig. 313 That for V
I
= V
GSN
2 V the NMOS FET (blue ≤
curves) is in cutoff, so the intersection of the appropriate NMOS and
PMOS curves is at V
O
= V
DSN
= 10 V.
As V
I
increases above 2 V, we select the appropriate NMOS and
PMOS curve, as shown in the figures below.
Introduction to Electronics 237 MOSFET Logic Inverters
V
I
= V
GSN
= 5 V
NMOS Drain-Source Voltage, V
DSN
Fig. 316. Appropriate NMOS and PMOS curves for v
I
= 5 V.
V
I
= V
GSN
= 6 V
NMOS Drain-Source Voltage, V
DSN
Fig. 317. Appropriate NMOS and PMOS curves for v
I
= 6 V.
D
r
a
i
n

C
u
r
r
e
n
t
,

|
I
D
|
D
r
a
i
n

C
u
r
r
e
n
t
,

|
I
D
|
Because the ideal characteristics shown in these figures are
horizontal, the intersection of the two curves for V
I
= V
GSN
= 5 V
appears ambiguous, as can be seen below.
However, real MOSFETs have finite drain resistance, thus the
curves will have an upward slope. Because the NMOS and PMOS
devices are complementary, their curves are symmetrical, and the
true intersection is precisely in the middle:
Introduction to Electronics 238 MOSFET Logic Inverters
Input Voltage, V
I
Fig. 319. CMOS inverter transfer function. Note the similarity to
the ideal transfer function of Fig. 298.
NMOS Drain-Source Voltage, V
DSN
V
I
= V
GSN
= 7 V
Fig. 318. Appropriate NMOS and PMOS curves for v
I
= 7 V.
O
u
t
p
u
t

V
o
l
t
a
g
e
,

V
O
For V
I
= V
GSN
8 V, the PMOS FET (green curves) is in cutoff, so ≥
the intersection is at V
O
= V
DSN
= 0 V.
Collecting “all” the intersection points from Figs. 314-318 (and the
ones for other values of v
I
that aren’t shown here) allows us to plot
the CMOS inverter transfer function:
D
r
a
i
n

C
u
r
r
e
n
t
,

|
I
D
|
Introduction to Electronics 239 Differential Amplifier
+
-
+
-
+
-
+
-
v
I1
v
I2
v
ICM
v
ID
/2
v
ID
/2
1
1
2
2
+ -
Fig. 320. Representing two sources by their differential and
common-mode components (Fig. 41 repeated).
v v
v
v v
v
I ICM
ID
I ICM
ID
1 2
2 2
+ − and
(341)
v v v v
v v
ID I I ICM
I I

+
1 2
1 2
2
and
(342)
Differential Amplifier
We first need to remind ourselves of a fundamental way of
representing any two signal sources by their differential and
common-mode components. This material is repeated from pp. 27-
28:
Modeling Differential and Common-Mode Signals
As shown above, any two signals can be modeled by a differential
component, v
ID
, and a common-mode component, v
ICM
, if:
Solving these simultaneous equations for v
ID
and v
ICM
:
Note that the differential voltage v
ID
is the difference between the
signals v
I1
and v
I2
, while the common-mode voltage v
ICM
is the
average of the two (a measure of how they are similar).
Introduction to Electronics 240 Differential Amplifier
R
C
R
C
I
BIAS
V
CC
-V
EE
v
I1
v
I2
v
OD
v
O1
v
O2
Q
1
Q
2
i
C1
i
C2
+
+
+
-
- -
Fig. 321. Differential amplifier.
R
C
R
C
I
BIAS
V
CC
-V
EE
v
OD
v
O1
v
O2
Q
1
Q
2
i
C1
i
C2
+
+
+
-
- -
v
ICM
+
-
v
ICM
v
ICM
Fig. 322. Differential amplifier with only a
common-mode input.
v V R i
v V R i
O CC C C
O CC C C
1 1
2 2


(343)
( )
v v v
R i i
OD O O
C C C


1 2
2 1
(344)
i i
I
E E
BIAS
1 2
2

(345)
i i
I
C C
BIAS
1 2
2

α
(346)
v
OD
0 (347)
Basic Differential Amplifier Circuit
The basic diff amp circuit consists of
two emitter-coupled transistors.
We can descri be the total
instantaneous output voltages:
And the total instantaneous differential
output voltage:
Case #1 - Common-Mode Input:
We let v
I1
= v
I2
= v
ICM
, i.e., v
ID
= 0.
From circuit symmetry, we can
write:
and
Introduction to Electronics 241 Differential Amplifier
R
C
R
C
I
BIAS
V
CC
-V
EE
v
OD
v
O1
v
O2
Q
1
Q
2
i
C1
i
C2
+
+
+
-
- -
v
ID
/2

=

1

V v
ID
/2

=

1

V
+
+ -
-
+1

V -1

V
0.7

V
+
-
0.3

V
-1.3

V
+
-
Fig. 323. Differential amplifier with +2 V
differential input.
R
C
R
C
I
BIAS
V
CC
-V
EE
v
OD
v
O1
v
O2
Q
1
Q
2
i
C1
i
C2
+
+
+
-
- -
v
ID
/2

=

-1

V v
ID
/2

=

-1

V
+
+ -
-
-1

V +1

V
0.7

V
+
-
0.3

V
-1.3

V
+
-
Fig. 324. Differential amplifier with -2 V
differential input.
i
C2
0 (348)
v V
O CC 2
(349)
i i I
C E BIAS 1 1
α α (350)
v V R I
O CC C BIAS 1
−α (351)
v R I
OD C BIAS
−α (352)
i
C1
0 (353)
v V
O CC 1
(354)
i i I
C E BIAS 2 2
α α (355)
v V R I
O CC C BIAS 2
−α (356)
v R I
OD C BIAS
α (357)
Case #2A - Differential Input:
Now we let v
ID
= 2 V and v
ICM
= 0.
Note that Q
1
is active, but Q
2
is
cutoff. Thus we have:
Case #2B - Differential Input:
This is a mirror image of Case
#2A. We have v
ID
= -2 V and
v
ICM
= 0.
Now Q
2
is active and Q
1
cutoff:
These cases show that a common-mode input is ignored, and that
a differential input steers I
BIAS
from one side to the other, which
reverses the polarity of the differential output voltage!!!
We show this more formally in the following sections.
Introduction to Electronics 242 Large-Signal Analysis of Differential Amplifier
R
C
R
C
I
BIAS
V
CC
-V
EE
v
I1
v
I2
v
OD
v
O1
v
O2
Q
1
Q
2
i
C1
i
C2
+
+
+
-
- -
Fig. 325. Differential amplifier circuit
(Fig. 321 repeated).
i I
V
V
C S
BE
T
1
1

|
(
'
`
J
J
exp (358)
i I
v
V
C S
BE
T
2
2

|
(
'
`
J
J
exp (359)
i
i
v v
V
v
V
C
C
BE BE
T
ID
T
1
2
1 2

− |
(
'
`
J
J

|
(
'
`
J
J
exp exp (360)
i
i
v
V
C
C
ID
T
1
2
1 1 + +
|
(
'
`
J
J
exp (361)
i
i
i i
i
I
i
C
C
C C
C
BIAS
C
1
2
1 2
2 2
1 +
+

α
(362)
Large-Signal Analysis of Differential Amplifier
We begin by assuming identical devices
in the active region, and use the forward-
bias approximation to the Shockley
equation:
Dividing eq. (358) by eq. (359):
From eq. (360) we can write:
And we can also write:
Introduction to Electronics 243 Large-Signal Analysis of Differential Amplifier
v
ID
/

V
T
Fig. 326. Normalized collector currents vs.
normalized differential input voltage, for a differential
amplifier.
i
I
v
V
C
BIAS
ID
T
2
1

+
|
(
'
`
J
J
α
exp
(363)
i
I
v
V
C
BIAS
ID
T
1
1

+ −
|
(
'
`
J
J
α
exp
(364)
Equating (361) and (362) and solving for i
C2
:
To find a similar expression for i
C1
we would begin by dividing eqn.
(359) by (358) . . . the result is:
The current-steering effect of varying v
ID
is shown by plotting eqs.
(363) and (364):
Note that I
BIAS
is steered from one side to the other . . .as v
id
changes from approximately -4V
T
(-100 mV) to +4V
T
(+100 mV)!!!
i
C

/

α
I
B
I
A
S
Introduction to Electronics 244 Large-Signal Analysis of Differential Amplifier
i
I
v
V
v
V
v
V
I
v
V
v
V
v
V
C
BIAS
ID
T
ID
T
ID
T
BIAS
ID
T
ID
T
ID
T
2
1
2
2
2
2 2

+
|
(
'
`
J
J

]
]
]
]
]
]

|
(
'
`
J
J

|
(
'
`
J
J

]
]
]
]
]
]


|
(
'
`
J
J
|
(
'
`
J
J
+ −
|
(
'
`
J
J
α
α
exp
exp
exp
exp
exp exp
(365)
i
I
v
V
v
V
v
V
I
v
V
v
V
v
V
C
BIAS
ID
T
ID
T
ID
T
BIAS
ID
T
ID
T
ID
T
1
1
2
2
2
2 2

+ −
|
(
'
`
J
J

]
]
]
]
]
]
|
(
'
`
J
J
|
(
'
`
J
J

]
]
]
]
]
]

|
(
'
`
J
J
|
(
'
`
J
J
+ −
|
(
'
`
J
J
α
α
exp
exp
exp
exp
exp exp
(366)
v I R
v
V
v
V
v
V
v
V
OD BIAS C
ID
T
ID
T
ID
T
ID
T

|
(
'
`
J
J
− −
|
(
'
`
J
J
|
(
'
`
J
J
+ −
|
(
'
`
J
J
α
exp exp
exp exp
2 2
2 2
(367)
v I R
v
V
OD BIAS C
ID
T

|
(
'
`
J
J
α tanh
2
(368)
Using (363) and (364), and recalling that v
OD
= R
C
(

i
C2
- i
C1
):
Thus we see that differential input voltage and differential output
voltage are related by a hyperbolic tangent function!!!
Introduction to Electronics 245 Large-Signal Analysis of Differential Amplifier
v
ID
/

V
T
Fig. 327. Normalized differential output voltage vs.
normalized differential input voltage, for a differential
amplifier.
A normalized version of the hyperbolic tangent transfer function is
plotted below:
This transfer function is linear only for |v
ID
/V
T
| much less than 1,
i.e., for |v
ID
| much less than 25 mV!!!
We usually say the transfer function is acceptably linear for a |v
ID
|
of 15 mV or less.
If we can agree that, for a differential amplifier, a small input signal
is less than about 15 mV, we can perform a small-signal analysis of
this circuit !!!
V
O
D

/

α
R
C
I
B
I
A
S
Introduction to Electronics 246 Small-Signal Analysis of Differential Amplifier
R
C
R
C
I
BIAS
V
CC
-V
EE
v
I1
v
I2
v
OD
v
O1
v
O2
Q
1
Q
2
i
C1
i
C2
+
+
+
-
- -
Fig. 328. Differential amplifier (Fig. 321
repeated).
R
C
R
C
βi
b2
βi
b1
r
π
r
π
i
b2
i
b1
R
EB
(β+1)i
b2
(β+1)i
b1
v
id
/2 v
id
/2
v
od
v
o1
v
o2
+
+
+
+ +
-
-
- -
-
v
X
Fig. 329. Small-signal equivalent with a differential input. R
EB
is
the equivalent ac resistance of the bias current source.
Small-Signal Analysis of Differential Amplifier
Differential Input Only
We presume the input to the
differential amplifier is limited to a
purely differential signal.
This means that v
ICM
can be any
value.
We further presume that the
differential input signal is small as
defined in the previous section.
Thus we can construct the small-
signal equivalent circuit using
exactly the same techniques that
we studied previously:
Introduction to Electronics 247 Small-Signal Analysis of Differential Amplifier
R
C
R
C
βi
b2
βi
b1
r
π
r
π
i
b2
i
b1
R
EB
(β+1)i
b2
(β+1)i
b1
v
id
/2 v
id
/2
v
od
v
o1
v
o2
+
+
+
+ +
-
-
- -
-
v
X
Fig. 330. Diff. amp. small-signal equivalent (Fig. 329 repeated).
( )( )
v
i r i i R
id
b b b EB
2
1
1 1 2
+ + +
π
β
(369)
( )
[ ]
( )
[ ]
v
i r R i R
id
b EB b EB
2
1 1
1 2
+ + + +
π
β β
(370)
( )( ) − + + +
v
i r i i R
id
b b b EB
2
1
2 1 2 π
β
(371)
( )
[ ]
( )
[ ]
− + + + +
v
i r R i R
id
b EB b EB
2
1 1
2 1 π
β β
(372)
We begin with a KVL equation around left-hand base-emitter loop:
and collect terms:
We also write a KVL equation around right-hand base-emitter loop:
and collect terms:
Introduction to Electronics 248 Small-Signal Analysis of Differential Amplifier
R
C
R
C
βi
b2
βi
b1
r
π
r
π
i
b2
i
b1
R
EB
(β+1)i
b2
(β+1)i
b1
v
id
/2 v
id
/2
v
od
v
o1
v
o2
+
+
+
+ +
-
-
- -
-
v
X
Fig. 331. Diff. amp. small-signal equivalent (Fig. 329 repeated).
( ) ( )
[ ]
0 2 1
1 2
+ + + i i r R
b b EB π
β
(373)
( )
i i
b b 1 2
0 + (374)
Adding (370) and (372):
Because neither resistance is zero or negative, it follows that
and, because v
X
= (i
b1
+ i
b2
)R
EB
, the voltage v
X
must be zero, i.e.,
point X is at signal ground for all values of R
EB
!!!
The junction between the collector resistors is also at signal ground,
so the left half-circuit and the right half-circuit are independent of
each other, and can be analyzed separately !!!
Introduction to Electronics 249 Small-Signal Analysis of Differential Amplifier
Fig. 332. Left half-circuit of
differential amplifier with a differential
input.
v
v
v
v
R
r
o
in
o
id
C 1 1
2 2


/
β
π
(375)
A
v
v
R
r
vds
o
id
C
1
1
2

−β
π
(376)
A
v
v
R
r
vds
o
id
C
2
2
2

β
π
(377)
A
v
v
R
r
vdb
od
id
C

−β
π
(378)
Analysis of Differential Half-Circuit
The circuit at left is just the small-
signal equivalent of a common emitter
amplifier, so we may write the gain
equation directly:
For v
o1
/v
id
we must multiply the
denominator of eq. (375) by two:
In the notation A
vds
the subscripts mean:
v, voltage gain d, differential input s, single-ended output
The right half-circuit is identical to Fig. 332, but has an input of
-v
id
/2, so we may write:
Finally, because v
od
= v
o1
- v
o2
, we have the result:
where the subscript b refers to a balanced output.
Thus, we can refer to differential gain for either a single-ended
output or a differential output.
Introduction to Electronics 250 Small-Signal Analysis of Differential Amplifier
R
C
R
C
βi
b2
βi
b1
r
π
r
π
i
b2
i
b1
R
EB
(β+1)i
b2
(β+1)i
b1
v
id
/2 v
id
/2
v
od
v
o1
v
o2
+
+
+
+ +
-
-
- -
-
v
X
Fig. 333. Diff. amp. small-signal equivalent (Fig. 329 repeated).
v
i
r
v
i
R r
id
b
id
b
id
/ 2
2
1 1

π π
(379)
R R R R
os C od C
and 2 (380)
Remember our hyperbolic tangent transfer function? Eq. (378) is
just the slope of that function, evaluated at v
ID
= 0 !!!
Other parameters of interest . . .
Differential Input Resistance
This is the small-signal resistance seen by the differential source:
Differential Output Resistance
This is the small-signal resistance seen by the load, which can be
single-ended or balanced. We can determine this by inspection:
Introduction to Electronics 251 Small-Signal Analysis of Differential Amplifier
R
C
R
C
I
BIAS
V
CC
-V
EE
v
I1
v
I2
v
OD
v
O1
v
O2
Q
1
Q
2
i
C1
i
C2
+
+
+
-
- -
Fig. 334. Differential amplifier (Fig. 321
repeated).
R
C
R
C
βi
b2
βi
b1
r
π
r
π
i
b2
i
b1
2R
EB
(β+1)i
b2
(β+1)i
b1
v
icm
v
icm
v
od
v
o1
v
o2
+
+
+
+ +
-
-
- -
-
2R
EB
Fig. 335. Small-signal equivalent with a common-mode input. The
resistance of the bias current source is represented by
2R
EB
|| 2R
EB
= R
EB
.
Common-Mode Input Only
We now restrict the input to a
common-mode voltage only.
This is, we let v
ID
= 0.
We again construct the small-signal
circuit using the techniques we
studied previously.
As a bit of a trick, we represent the
equivalent ac resistance of the bias
current source as two resistors in
series:
Introduction to Electronics 252 Small-Signal Analysis of Differential Amplifier
R
C
R
C
βi
b2
βi
b1
r
π
r
π
i
b2
i
b1
2R
EB
(β+1)i
b2
(β+1)i
b1
v
icm
v
icm
v
od
v
o1
v
o2
+
+
+
+ +
-
-
- -
-
i
X
=

0
2R
EB
Fig. 336. Small-signal equivalent with a common-mode input.
Note the current i
X
.
The voltage across each 2R
EB
resistor is identical because the
resistors are connected across the same nodes.
Therefore, the current i
X
is zero and we can remove the connection
between the resistors !!!
This “decouples” the left half-circuit from the right half-circuit at the
emitters.
At the top of the circuit, the small-signal ground also decouples the
left half-circuit from the right half-circuit.
Again we need only analyze one-half of the circuit !!!
Introduction to Electronics 253 Small-Signal Analysis of Differential Amplifier
R
C
βi
b1
r
π
i
b1
v
icm
v
o1
or v
o2
+
+
-
-
2R
EB
Fig. 337. Either half-circuit of diff.
amp. with a common-mode input.
( )
v
v
v
v
R
r R
o
icm
o
icm
C
EB
1 2
1 2


+ +
β
β
π
(381)
A
vcd
0 (382)
( )
[ ]
R
v
i i
v
i
r R
icm
icm
b b
icm
b
EB

+
+ +
1 2 1
2
1
2
1 2
π
β (383)
R R R R
os C od C
and 2 (384)
Analysis of Common-Mode Half-Circuit
Again, the circuit at left is just the
small-signal equivalent of a common
emitter amplifier (this time with an
emitter resistor), so we may write the
gain equation:
Eq. (381) gives A
vcs
, the common-
mode gain for a single-ended output.
Because v
o1
= v
o2
, the output for a
balanced load will be zero:
Common-mode input resistance:
Because the same v
icm
source is connected to both bases:
Common-mode output resistance:
Because we set independent sources to zero when determining R
o
,
we obtain the same expressions as before:
Introduction to Electronics 254 Small-Signal Analysis of Differential Amplifier
( )
CMRR
A
A
r R
r
R
r
vds
vcs
EB
EB

+ +

π
π π
β
β
1 2
2
(385)
CMRR CMRR
dB
20log (386)
Common-Mode Rejection Ratio
CMRR is a measure of how well a differential amplifier can amplify
a differential input signal while rejecting a common-mode signal.
For a single-ended load:
For a differential load CMRR is theoretically infinite because A
vcd
is
theoretically zero. In a real circuit, CMRR will be much greater than
that given above.
To keep these two CMRRs in mind it may help to remember the
following:
G A
vcs
= 0 if the bias current source is ideal (for which R
EB
= ). ∞
G A
vcd
= 0 if the circuit is symmetrical (identical left- and right-
halves).
CMRR is almost always expressed in dB:

Introduction to Electronics

ii

Dedication
Human beings are a delightful and complex amalgam of the spiritual, the emotional, the intellectual, and the physical. This is dedicated to all of them; especially to those who honor and nurture me with their friendship and love.

Introduction to Electronics

iii

Table of Contents
Preface xvi
Philosophy of an Online Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi Notes for Printing This Document . . . . . . . . . . . . . . . . . . . . . . . . xviii Copyright Notice and Information . . . . . . . . . . . . . . . . . . . . . . . . xviii

Review of Linear Circuit Techniques 1
Resistors in Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Resistors in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Over Sum 1 Inverse of Inverses 1

Ideal Voltage Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ideal Current Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Superposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A quick exercise 4 You’ll still need Ohm’s and Kirchoff’s Laws 5

2 2 2 3 4 4

What’s missing from this review??? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Basic Amplifier Concepts 6
Signal Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . To work with (analyze and design) amplifiers . . . . . . . . . . . . . . . . . . . . . 6 6 7 7 7

Voltage Amplifier Model 8
Signal Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Amplifier Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Amplifier Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Open-Circuit Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Introduction to Electronics

iv

Power Supplies, Power Conservation, and Efficiency 11
DC Input Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Conservation of Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Amplifier Cascades 13 Decibel Notation 14
Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cascaded Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Decibels to Indicate Specific Magnitudes . . . . . . . . . . . . . . . . . . .
Voltage levels: 15 Power levels 16

14 14 14 15 15

Other Amplifier Models 17
Current Amplifier Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transconductance Amplifier Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Transresistance Amplifier Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Amplifier Resistances and Ideal Amplifiers 20
Ideal Voltage Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ideal Current Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ideal Transconductance Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ideal Transresistance Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Uniqueness of Ideal Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 21 22 23 23

Frequency Response of Amplifiers 24
Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Magnitude Response 24 Phase Response 24 Frequency Response 24 Amplifier Gain 24

The Magnitude Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Causes of Reduced Gain at Higher Frequencies . . . . . . . . . . . . . . . . . . 26 Causes of Reduced Gain at Lower Frequencies . . . . . . . . . . . . . . . . . . 26

Introduction to Electronics

v

Differential Amplifiers 27
Example: 27

Modeling Differential and Common-Mode Signals . . . . . . . . . . . . . . . . . 27 Amplifying Differential and Common-Mode Signals . . . . . . . . . . . . . . . . 28 Common-Mode Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Ideal Operational Amplifiers 29
Ideal Operational Amplifier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Op Amp Operation with Negative Feedback . . . . . . . . . . . . . . . . . . . . . 30 Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Op Amp Circuits - The Inverting Amplifier 31
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Op Amp Circuits - The Noninverting Amplifier 33
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Input and Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Op Amp Circuits - The Voltage Follower 34
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Input and Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Op Amp Circuits - The Inverting Summer 35
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Op Amp Circuits - Another Inverting Amplifier 36
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Op Amp Circuits - Differential Amplifier 38
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Op Amp Circuits - Integrators and Differentiators 40
The Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 The Differentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .The Half-Wave Rectifier 66 Introduction . . . 52 An Ideal Diode Example 53 Piecewise-Linear Diode Models . .Graphical Analysis of Loaded Regulator 64 Diode Applications . . . . . . 63 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 A Typical Battery Charging Circuit . . . . . . . . . . . . . . . 61 Circuit Analysis 62 Zener Regulators with Attached Load . . . . . .The Zener Diode Voltage Regulator 59 Introduction . . . . . . . . . . . . . . . . . . . . . 49 Diode Models 50 The Shockley Equation . . . . . . . . . . . . . . . . . . . 59 Numerical Analysis of Zener Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Introduction to Electronics vi Op Amp Circuits . . . . . 42 Graphical Solution of Simultaneous Equations 43 Diodes 46 Graphical Analysis of Diode Circuits 48 Examples of Load-Line Analysis . . . . . . 50 Forward Bias Approximation 51 Reverse Bias Approximation 51 At High Currents 51 The Ideal Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 The Filtered Half-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Diode Applications . . . . . . . . . . . . . . . . . . . . .Designing with Real Op Amps 42 Resistor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Source Resistance and Resistor Tolerances . . . . . . . . . . . . . . . . . . . 55 A Piecewise-Linear Diode Example 57 Other Piecewise-Linear Models . . . . . . . . . 68 Relating Capacitance to Ripple Voltage 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Load-Line Analysis of Zener Regulators . . . .

. 80 Input Characteristic . . . . . . . . 74 Diode Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .The Bridge Rectifier 74 Operation . . 75 Bipolar Junction Transistors (BJTs) 76 Introduction . . . . . . . . . . . . . . . 80 Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Qualitative Description of BJT Active-Region Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Diode Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Full-Wave/Bridge Rectifier Features 75 Bridge Rectifier . . . . . . . . . . . 81 Active Region 81 Cutoff 82 Saturation 82 The pnp BJT 83 BJT Characteristics . . . . . . . . . . . . . . .Introduction to Electronics vii Diode Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .The Full-Wave Rectifier 72 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1st (Positive) Half-Cycle 72 2nd (Negative) Half-Cycle 72 Diode Peak Inverse Voltage . . . . . . . . . . . . . . . . . . . . . . . 78 BJT Common-Emitter Characteristics 80 Introduction . . . . . . . . 74 1st (Positive) Half-Cycle 74 2nd (Negative) Half-Cycle 74 Peak Inverse Voltage . . . . . . . 75 Full-Wave Rectifier . . . . . 77 Quantitative Description of BJT Active-Region Operation . . . . 75 Filtered Full-Wave and Bridge Rectifiers . . .Secondary Effects 85 . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Pinch-Off Boundary . . . . . . . . 89 Cutoff Region 89 Triode Region 89 Pinch-Off Region 89 The Triode . . . . . . . . . . . . . . . . . . . 90 The Transfer Characteristic . Load-Line Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Comparison of n-Channel FETs 94 p-Channel JFETs and MOSFETs 96 Cutoff Region 98 Triode Region 98 Pinch-Off Region 98 Other FET Considerations 99 FET Gate Protection . . . . . . . . . . . . . . .Output Side . . . . . . . . . . . . A Numerical Example . . .Input Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Metal-Oxide-Semiconductor FETs (MOSFETs) 92 The n-Channel Depletion MOSFET . . . . . . . . . . . . . . . . 100 100 102 104 Basic FET Amplifier Structure 107 Amplifier Distortion 110 Biasing and Bias Stability 112 . . . . . 92 The n-Channel Enhancement MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . 99 The Body Terminal . . . . . . . . . . . . 86 Equations Governing n-Channel JFET Operation . . . . . . . . . . . . . Load-Line Analysis . . . . . . . . . 99 Basic BJT Amplifier Structure 100 Circuit Diagram and Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Introduction to Electronics viii The n-Channel Junction FET (JFET) 86 Description of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . 125 Design Procedure 125 Design of the Grounded-Emitter BJT Bias Circuit . . . . .The Fixed Bias Circuit 119 Biasing FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V) 118 For b = 300 118 Biasing FETs . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . . . .The Fixed Bias Circuit 113 Example . . . . . . . .The Four-Resistor Bias Circuit 115 Introduction . . . . . . . . . . . . . . . . . 114 For b = 100 114 For b = 300 114 Biasing BJTs . . . . . . . . . . . . . . . . 113 For b = 100 113 For b = 300 113 Biasing BJTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Design Procedure 124 Design of the Dual-Supply BJT Bias Circuit . . . . . . . . . . . . . . . . .Introduction to Electronics ix Biasing BJTs . . . . . . . . . . . . 116 Bias Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Design Procedure 126 Analysis of the Grounded-Emitter BJT Bias Circuit . . . . . . . . . . . . . . . . . . . . . .The Constant Base Bias Circuit 114 Example . . . . . . . .The Self Bias Circuit 120 Biasing FETs . . . . . . . . . . . 127 . . . . . . . . . . . . . . . . . . . . . . . . . . 118 For b = 100 (and VBE = 0. . . . . . . .The Fixed + Self Bias Circuit 121 Design of Discrete BJT Bias Circuits 123 Concepts of Biasing . . . . . . 123 Design of the Four-Resistor BJT Bias Circuit . . . . . . . . . . . . 117 To maximize bias stability 117 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . 141 Notation 142 BJT Small-Signal Equivalent Circuit 143 The Common-Emitter Amplifier 145 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 FET Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 The Equations . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Current Ratio 133 Reference Current 134 Output Resistance 134 Widlar Current Mirror . . . . . . . . . . . . . . . . . 135 Current Relationship 135 Multiple Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Wilson Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Resistance . . . . . . . . . . . . . . . . 137 Linear Small-Signal Equivalent Circuits 138 Diode Small-Signal Equivalent Circuit 139 The Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Diode Small-Signal Resistance . . . . . 145 146 147 148 148 . . . . . . . . . . . . . . . . . .Introduction to Electronics x Bipolar IC Bias Circuits 129 Introduction . . . . . . . . . . . Constructing the Small-Signal Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 The Diode-Biased Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Using a Mirror to Bias an Amplifier . . . . . . . . . . . . . . 130 Current Ratio 130 Reference Current 131 Output Resistance 131 Compliance Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Resistance . . . . . . . . . . . Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Resistance . . . . . . . . . . . . . . . . . Input Resistance . . . . . Single-Pole Low-Pass RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Magnitude in dB 167 Bode Magnitude Plot 168 Bode Phase Plot 169 164 165 166 167 Single-Pole High-Pass RC . . . . . . . . . . . . . . . . . 156 The Common Source Amplifier 157 The Small-Signal Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Resistance . . Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 FET Output Resistance . . . . . . . . . . . . . . . . . . . . . . . 159 160 161 162 Review of Bode Plots 164 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Bode Phase Response . . . . . . . . . . . . . . . . . . . . . Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Gain . . . . . . . . . . . . . . 154 Transconductance . . . . . 149 150 151 152 Review of Small Signal Analysis 153 FET Small-Signal Equivalent Circuit 154 The Small-Signal Equivalent . . . . . . . . . . . . . . . . . . . . . . . . 157 158 158 158 The Source Follower 159 Small-Signal Equivalent Circuit . . . . . . . . . . . . . . The Bode Magnitude Response . . . . . . . . . . . .Introduction to Electronics xi The Emitter Follower (Common Collector Amplifier) 149 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Bode Magnitude Plot 170 Bode Phase Plot 171 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . 193 Input and Output Impedance 193 Gain and Bandwidth 193 Nonlinear Imperfections . . . . . . . . . 183 Deriving the Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 High-Frequency Performance of CE Amplifier 189 The Small-Signal Equivalent Circuit . . . . . . . . . . . . . . . . . . . Design Considerations . . . . . . . . 190 The CE Amplifier Magnitude Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 177 178 179 180 The Miller Effect 183 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 High-Frequency Performance . . . . . . . . . . . 174 Design Considerations for RC-Coupled Amplifiers 175 Low. . . . . . . . . . . . . . . . . . . . . 194 Output Voltage Swing 194 Output Current Limits 194 Slew-Rate Limiting 194 Full-Power Bandwidth 195 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .& Mid-Frequency Performance of CE Amplifier 176 Introduction . . . . . . . . . . . . . . . . . . . . The Effect of the Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Constructing the Bode Magnitude Plot for an Amplifier . . . . . . 185 Effect of Cp and Cm . . . . . . . . . . .Introduction to Electronics xii Coupling Capacitors 172 Effect on Frequency Response . . Midband Performance . . . . . . . . . . . . . . . . . . . 184 The Hybrid-p BJT Model 185 The Model . . . . . . . . . . . . . . . . 192 Nonideal Operational Amplifiers 193 Linear Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Effect of the Emitter Bypass Capacitor CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 . . . . . . . . 196 Using the DC Error Model . . . . . . . . . . . . . . . . . . . . 195 Input Offset Voltage. . . . . . . . . . . . . . . . . . . . . . . 214 Amplifier Noise Calculations 215 Introduction . . . . . . . . . . . . . . . 204 Simplified Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Amplifier Noise Performance 211 Terms. . . . . . . . . . 203 Instrumentation Amplifier 204 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 DC Output Error Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Example #2 . . . . . . . . . . . . . . . . . . . . . . . . 206 Johnson Noise Model 207 Shot Noise . . . . . . . . . . . . . . . . . . . . . . . . . . 207 1/f Noise (Flicker Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . VIO 195 Input Currents 195 Modeling the DC Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Finding Worst-Case DC Output Error 201 Canceling the Effect of the Bias Currents . . . 217 Example #1 . . . . Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Calculating Noise Figure . . . . . . . . . . . . . . . . . . . 216 Typical Manufacturer’s Noise Data 217 Introduction . . . . . . . . . 208 Other mechanisms producing 1/f noise 209 Interference . . . . . . . . . . . . . . . . . . . . . . . . .Introduction to Electronics xiii DC Imperfections . . . 211 Amplifier Noise Voltage 211 Amplifier Noise Current 212 Signal-to-Noise Ratio 212 Noise Figure 213 Noise Temperature 213 Converting NF to/from Tn 214 Adding and Subtracting Uncorrelated Quantities . . . . . . 205 Noise 206 Johnson Noise . . . . . . . . . . . . .

. . . . . . . . . Power Consumption . . . . . . . . . . . . CMOS Logic Families & Characteristics . . . . . . . . . . . . . . . .Differential Input 241 Case #2B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Common-Mode Input 240 Case #2A . . . . . . . . . . . . . . . . 221 The Ideal Case 221 The Actual Case 221 Manufacturer’s Voltage Specifications . . . . . . . . . . . . . . . . . . . . . 240 Case #1 . . . . . . . . Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and Propagation Delay . . 239 Basic Differential Amplifier Circuit . . . . . . . . . . . 230 Circuit Operation 230 Drawbacks 231 CMOS Inverter . . . . Fan-Out . . . . . . . .Introduction to Electronics xiv Noise . . . . . . . . . . . . . . . . 232 Circuit Operation 232 Differential Amplifier 239 Modeling Differential and Common-Mode Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .References and Credits 220 Introduction to Logic Gates 221 The Inverter . . . . . . . . . . . . . . . . . . Speed-Power Product . . . . . . . . . . . . . . . . . Noise Margin . . . . . . . . . TTL Logic Families & Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Power Consumption 224 Dynamic Power Consumption 224 222 222 223 223 224 226 227 228 229 Rise Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manufacturer’s Current Specifications . . . . . MOSFET Logic Inverters 230 NMOS Inverter with Resistive Pull-Up . . . . . . . . . . . .Differential Input 241 Large-Signal Analysis of Differential Amplifier 242 . . . . . . . . . .

. . . . . . . . . . . . . 249 Differential Input Resistance 250 Differential Output Resistance 250 Common-Mode Input Only . . . . . . . 254 . . . . . . . . . . . . . 246 Analysis of Differential Half-Circuit . . . 253 Common-mode input resistance 253 Common-mode output resistance 253 Common-Mode Rejection Ratio . . . . . . . . . . 251 Analysis of Common-Mode Half-Circuit . . . .Introduction to Electronics xv Small-Signal Analysis of Differential Amplifier 246 Differential Input Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Though change is inevitable. the official rewards for textbook authoring fall far short of what is appropriate and what is achievable through an equivalent research effort. And it has long seemed to me that. in my view. and as inexpensive as possible. we don’t. the relationships we engage.Introduction to Electronics xvi Preface Philosophy of an Online Text I think of myself as an educator rather than an engineer. choosing instead to write another conventional text book.” No economic incentive exists to create and maintain a 1 G G I use the word “supposedly” because. though. This is true in the habits we form. These arguments. thereby bringing fame and immortality to the institution of their employ. as educators. The proper reward structure is not in place. despite all the administrative lip service to the contrary. sell. are more appropriately left to a different soapbox. Faculty are supposedly rewarded for writing textbooks. but we should strive to make that information as accessible as possible. and print.1 The recognition and reward structure are simply not there for a text that is simply “posted on the web. It is simply easier not to change than it is to change. I offer only a few observations: G Any change is difficult and resisted. it is not well-suited to the behavior of any organism. The “whys” are undoubtedly intricate and many. and use it in the conventional manner. The technology of the Internet and the World Wide Web now allows us to virtually give away knowledge! Yet. we should endeavor to bring to the student not only as much information as possible. . the tasks we perform.

I would have prepared the course material in two formats. à la Corel Presentations or Microsoft PowerPoint. identical to the textbooks with which you are familiar. But. intended for use in the classroom or in an independent study. If I were to do this the way I think it ought to be done. I am still on that journey. It would be advantageous to produce two online versions . Until all of these enhancements exist.Introduction to Electronics xvii structure that allows all authors to publish in this manner. Also. and a second optimized for viewing on a computer screen. Other compromises have been made.” I believe it is best to include problems in a separate document. but would be formatted with different page and font sizes. font selection and variations are somewhat limited when compared to those normally encountered in a conventional textbook. You may also note that exercise problems are not included with this text. The two would carry identical information. so what I offer you is a hybrid of these two concepts: an online text somewhat less verbose than a conventional text. but available online.one intended for use in printed form. Enough of this. I hope you will find this a suitable and worthwhile compromise. By their very nature problems quickly can become “worn out. The second would be a slide presentation. and that rigorously ensures the material will exceed a minimum acceptable quality... . alas. and intended to be used in printed form. The first would be a text. that allows students easy access to all such material. let’s get on with it. to minimize file size. but one that can also serve as classroom overhead transparencies. and therefore download times.

and because I hold a faint hope that I may use it to acquire immeasurable wealth. salacious lifestyle that I’ve always dreamed of. . of Electrical Engineering. thereby supporting the insatiable. Dept. If you wish to print the entire document.Introduction to Electronics xviii Notes for Printing This Document This document can be printed directly from the Acrobat Reader see the Acrobat Reader help files for details. or by USPS mail to Bob Zulinski.edu. I copyrighted this online text because it required a lot of work. Thus. as most printer drivers will only spool a maximum of 255 pages at one time. Copyright Notice and Information This entire document is 1999 by Bob Zulinski. You may obtain that permission simply by asking: tell me who you are and what you want it for. Houghton MI 49931-1295. do so in two sections. Generous monetary donations included with your request will be looked upon with great favor. you will need my permission to print it. Route your requests via email to rzulinsk@mtu. Michigan Technological University. All rights reserved.

Review of Linear Circuit Techniques Introduction to Electronics 1 Review of Linear Circuit Techniques Resistors in Series R1 R2 Fig. R’s in parallel. Resistors in Parallel R1 R2 Resistors must have the same voltage!!! Equation takes either of two forms: Fig. Product Over Sum: Rtotal = R1 R2 R1 + R2 (2) Only valid for two resistors. . Not calculator-efficient!!! Inverse of Inverses: Rtotal = 1 1 1 1 + + + R1 R2 R3 (3) Always valid for multiple resistors. This is the simple one!!! Rtotal = R1 + R2 + R3 + (1) Resistors must carry the same current!!! L’s is series and C’s in parallel have same form. Very calculator-efficient!!! L’s in parallel and C’s in series have same forms. 2. R’s in series. 1.

Fig. Ideal voltage sources in parallel??? Ideal Current Sources Cannot be connected in series!!! Real current sources include a parallel resistance (“Norton equivalent”). v = VOC − i RTH or i = ISC − v RTH (4) . and can be connected in series. 4. so we can write the equations: VOC v Fig.Review of Linear Circuit Techniques Introduction to Electronics 2 Ideal Voltage Sources + 3V + 5V Cannot be connected in parallel!!! Real voltage sources include a series resistance (“Thevenin equivalent”). Typical linear i . 5. Fig.v characteristic of a real source. 3. Ideal current sources in series??? i ISC 1/RTH Real Sources All sources we observe in nature exhibit a decreasing voltage as they supply increasing current. We presume that i-v relationship to be linear. and can be paralleled.

Example of a voltage divider.finding the voltage across RB : VB = RB VX R A + RB + RC (6) Fig.we’ll note this in class if that is the case) . i.e. 8. Resistors must be in series.. and use the divider equation if the currents through the resistors are almost the same . RA + VX RC RB + VA + VB + VC - Voltage Dividers Example . Norton equivalent circuit. 6 and 7. 6. 7.Review of Linear Circuit Techniques Introduction to Electronics 3 The linear equations help us visualize what might be inside of a real source: i + VOC = VTH RTH + v Fig. Thevenin equivalent circuit. Note that: RTH = VOC ISC (5) We can generalize this ⇒ any linear resistive circuit can be represented as in Figs. they must carry the same current!!! (Sometimes we cheat a little. i + ISC RTH v Fig.

. have the same voltage!!! Superposition Superposition applies to any linear circuit . . . 13. . . Fig. Example of a current divider. . 12. . .e. . A quick exercise: Use superposition and voltage division to show that VX = 6 V: 4V 10 kΩ 30 kΩ 12 V VX Fig. . and the response IB . . 9. . i. . 10. A quick exercise .. this is the definition of a linear circuit!!! An example of finding a response using superposition: I + - IA + - IB Fig. . is the sum of the response IA . . Fig. 11.Review of Linear Circuit Techniques Introduction to Electronics 4 IB IX RA RB RC Current Dividers 1 RB IB = I 1 1 1 X + + R A RB RC (7) Fig. The total response current I .in fact. Resistors must be in parallel.

For the kinds of problems you’ll encounter in this course. I think you should forget about these analysis methods!!! If there is any other way to solve a circuit problem. . and with more insight. you’ll arrive at the answer more efficiently. . .Review of Linear Circuit Techniques Introduction to Electronics 5 What’s missing from this review??? Node voltages / mesh currents . KCL: Sum of currents into a node (or area) is zero. I won’t insult you by repeating Ohm’s Law here . . . We’ll more often use a different form: Sum of voltages from point A to point B is the same regardless of the path taken. do it that other way . . You’ll still need Ohm’s and Kirchoff’s Laws: KVL: Sum of voltages around a closed loop is zero. .

. . . . . .. Output voltage of inverting amplifier. sometimes voltage gain (illustrated below). . Generic input signal voltage. . . . Amplifier An amplifier is a system that provides gain . . 16. 14. . . . . e. Output voltage of noninverting amplifier. the fuel-level sensor in an automobile gas tank . . vi vo vo t t t Fig. sometimes current gain. Block diagram of basic amplifier. 15. . always power gain.g.Basic Amplifier Concepts Introduction to Electronics 6 Basic Amplifier Concepts + vi (t) + Amplifier vo (t) Ground Signal Source Load Fig. 17. . Signal Source A signal source is anything that provides the signal. . Fig. the carbon microphone in a telephone handset . Fig.

. .. . . 14 repeated). maybe connected to neither . . .Basic Amplifier Concepts Introduction to Electronics 7 Signal Source + vi (t) - + Amplifier vo (t) Ground Load Fig. . maybe connected to both . 18. . . the leg of lamb in a microwave oven . Load The load is anything we deliver the amplified signal to. . . i. loudspeaker . . . . .. e.e. usually common to input and output . . . 18. maybe connected to power-line ground . . . . use caution!!! To work with (analyze and design) amplifiers we need to visualize what might be inside all three blocks of Fig. . Ground Terminal Usually there is a ground connection . . Block diagram of basic amplifier (Fig. . . . . . we need models!!! . .g. . . . . . . . . . . . maybe connected to a metal chassis . .

current flows . . RS vs + Source ii + vi Ri + Ro io + vo RL Load Avocvi Amplifier Fig. . the load appears as a resistance. . Amplifier Output Output voltage decreases as load current increases . source voltage decreases as source current increases. . again we use a Thevenin equivalent. RL . . . . . . . 19. as with any real source . Ri . . Signal Source Our emphasis is voltage . so we use a Thevenin equivalent.Voltage Amplifier Model Introduction to Electronics 8 Voltage Amplifier Model This is usually the one we have the most intuition about . Modeling the source. Load Load current flows . amplifier. . . the amplifier must have an input resistance. . . . . Amplifier Input When the source is connected to the amplifier. and load with the emphasis on voltage. . . . . .

21. Av = vo /vi illustrated. with RL = ∞ ) the voltage of the Thevenin source in the amplifier output is the open-circuit output voltage of the amplifier. 20. 19 repeated). Avoc is called the open-circuit voltage gain: Avoc = vo vi (8) RL = ∞ Voltage Gain With a load in place our concept of voltage gain changes slightly: AV = vo vi ⇒ vo = RL Avocv i Ro + RL ⇒ Av = Avoc RL Ro + RL (9) We can think of this as the amplifier voltage gain if the source were ideal: ii + vi + Ro io + vo R L - vi + - Ri Avocvi Amplifier Load Fig.e..Voltage Amplifier Model Introduction to Electronics 9 RS vs + - ii + vi R i + - Ro io + vo R L - Avocvi Source Amplifier Load Fig. Thus. Open-Circuit Voltage Gain If we remove RL (i. . Voltage amplifier model (Fig.

With our “real” source model we define another useful voltage gain: Avs = vo vs ⇒ vi = Ri vs RS + Ri ⇒ Avs = Avoc Ri RL RS + Ri Ro + RL (10) Notice that Av and Avs are both less than Avoc . 19 repeated).Voltage Amplifier Model Introduction to Electronics 10 RS vs + - ii + vi R i + - Ro io + vo R L - Avocvi Source Amplifier Load Fig. and Pi = Vi Ii (rms values). Thus: G= Po VoIo 2 Ri 2 R = = Av Ai = Av = Ai L Pi Vi Ii RL Ri (12) . due to loading effects. 22. we have Po = Vo Io . Voltage amplifier model (Fig. Current Gain We can also define the amplifier current gain: Ai = io R RL v o Ri = = = Av i vi ii v i RL RL Ri vo (11) Power Gain Because the amplifier input and load are resistances.

and Efficiency IA RS vs + Source ii + vi + V AA Ro io + vo + - V AA Ri A vocv i RL Amplifier IB -V BB Load - V BB + Fig. Use care not to confuse this with the signal input power Pi . Power Conservation. Conservation of Power Signal power is delivered to the load ⇒ Po Power is dissipated within the amplifier as heat ⇒ PD The total input power must equal the total output power: PS + Pi = Po + PD (14) Virtually always Pi << PS and is neglected. and Efficiency Introduction to Electronics 11 Power Supplies. Our voltage amplifier model showing power supply and ground connections.Power Supplies. The signal power delivered to the load is converted from the dc power provided by the power supplies. . Power Conservation. 23. DC Input Power PS = VAAI A + VBBIB (13) This is sometimes noted as PIN.

and Efficiency Introduction to Electronics 12 IA RS vs + Source ii + vi - V AA Ro + io + vo - + V AA - Ri A vocv i RL Amplifier IB -V BB Load - V BB + Fig.Power Supplies. 23 repeated). Efficiency Efficiency is a figure of merit describing amplifier performance: η= Po × 100% PS (15) . 24. Our voltage amplifier model showing power supply and ground connections (Fig. Power Conservation.

the model is just a visualization of what might be inside): ii1 + vi1 + -A v voc i1 Ro2 io2 + vo2 - Ri1 Fig.Amplifier Cascades Introduction to Electronics 13 Amplifier Cascades Amplifier stages may be connected together (cascaded) : ii1 + vi1 + -A voc1 i1 Ro1 ii2 + vo1 = vi2 + -A Ro2 io2 + vo2 - Ri1 Ri2 v voc2 i2 v Amplifier 1 Amplifier 2 Fig. Model of cascade. 25. . A two-amplifier cascade. Gain of stage 1: Av 1 = Av 2 = v o1 v i1 (16) Gain of stage 2: v o2 v o2 = v i 2 v o1 (17) Gain of cascade: Avoc = v o1 v o 2 = Av 1Av 2 v i 1 v o1 (18) We can replace the two models by a single model (remember. 26. Notice that stage 1 is loaded by the input resistance of stage 2.

rather they are mapped into a logarithmic scale. dB (20) Thus. Cascaded Amplifiers We know that Gtotal = G1 G2 . Voltage Gain To derive the expression for voltage gain in decibels. Power Gain Recall that G = Po /Pi . we begin by recalling from eq. (12) that G = Av2(Ri /RL ). abbreviated dB. . Thus: Gtotal . and define: GdB = 10logG (19) GdB is expressed in units of decibels.Decibel Notation Introduction to Electronics 14 Decibel Notation Amplifier gains are often not expressed as simple ratios . the product of gains becomes the sum of gains in decibels. Thus: 10 logG = 10 log Av 2 Ri RL (21) = 10 log Av + 10 log Ri − 10 log RL 2 = 20 log Av + 10 log Ri − 10 log RL . The fundamental definition begins with a power ratio. dB + G2. dB = 10 logG1G2 = 10 logG1 + 10 logG2 = G1. .

16 V = 10 dBV 1V (24) . but are often used to indicate a specific magnitude of voltage or power. .16 V = 20 log 3. . From eq. (22) we can see that in an amplifier cascade the product of voltage gains becomes the sum of voltage gains in decibels.Decibel Notation Introduction to Electronics 15 Even though Ri may not equal RL in most cases. This is done by defining a reference and referring to it in the units notation: Voltage levels: dBV. decibels with respect to 1 V . 3. we can arrive at a similar definition for current gain: Ai dB = 20log Ai (23) Using Decibels to Indicate Specific Magnitudes Decibels are defined in terms of ratios. In all other cases they will differ. will the numerical values of GdB and Av dB be the same. for example. we define: Av dB = 20log Av (22) Only when Ri does equal RL . Current Gain In a manner similar to the preceding voltage-gain derivation.

for example 5 mW = 10log 5 mW = −23. for example 5 mW = 10 log 5 mW = 6. . .30 dBW and 1 W = +30 dBm.Decibel Notation Introduction to Electronics 16 Power levels: dBm. . decibels with respect to 1 W .99 dBm 1 mW (25) dBW.0 dbW 1W (26) There is a 30 dB difference between the two previous examples because 1 mW = . . . decibels with respect to 1 mW .

our voltage amplifier model arose from our visualization of what might be inside a real amplifier: RS vs + Source ii + vi Ri + Ro io + vo RL Load Avocvi Amplifier Fig. Modeling the source. 27. The short-circuit current gain is given by: Aisc = io ii (27) RL = 0 . In this case we use Norton equivalents for the signal source and the amplifier: ii + vi io + vo - is RS Ri Aiscii Ro RL Source Current Amplifier Load Fig. and load with the emphasis on voltage (Fig. 19 repeated). Modeling the source. and load with the emphasis on current. 28. amplifier. Current Amplifier Model Suppose we choose to emphasize current. amplifier.Other Amplifier Models Introduction to Electronics 17 Other Amplifier Models Recall.

S) RL = 0 (28) Transresistance Amplifier Model Our last choice emphasizes input current and output voltage: ii + vi + Ro io + vo R L - is RS Ri Rmocii Source Transresistance Amplifier Load Fig. The open-circuit transresistance gain is given by: Rmoc = vo ii (ohms.Other Amplifier Models Introduction to Electronics 18 Transconductance Amplifier Model Or. The transconductance amplifier model. Ω ) RL = ∞ (29) . 29. The short-circuit transconductance gain is given by: Gmsc = io vi (siemens. we could emphasize input voltage and output current: RS vs + ii + vi io + vo - Ri Gmscvi Ro RL Source Transconductance Amplifier Load Fig. 30. The transresistance amplifier model.

Change the dependent source’s variable of dependency with Ohm’s Law ⇒ vi = ii Ri (if necessary).Other Amplifier Models Introduction to Electronics 19 Any of these four models can be used to represent what might be inside of a real amplifier. Any of the four can be used to model the same amplifier!!! G G Models obviously will be different inside the amplifier. they will behave identically at the amplifier terminals!!! We can change from any kind of model to any other kind: G G Change Norton equivalent to Thevenin equivalent (if necessary). Try it!!! Pick some values and practice!!! . If the model parameters are chosen properly.

in an ideal world.Amplifier Resistances and Ideal Amplifiers Introduction to Electronics 20 Amplifier Resistances and Ideal Amplifiers Ideal Voltage Amplifier Let’s re-visit our voltage amplifier model: RS vs + Source ii + vi + Ro io + vo R L Load Ri Avocvi Voltage Amplifier Fig. In fact. like a voltmeter does. if Ro ⇒ 0 . we could have an ideal amplifier!!! .e. .e. . Voltage amplifier model. i. if the amplifier can “measure” the signal voltage with a high input resistance. and we’re thinking amplifier .. 31. we won’t have to worry about the value of RS at all!!! G We can get the most voltage out of the amplifier if Ro << RL . We’re thinking voltage. if the amplifier can look as much like a voltage source as possible. In fact. we won’t have to worry about the value of RL at all!!! So. if Ri ⇒ ∞ .. i. so how can we maximize the voltage that gets delivered to the load ? G We can get the most voltage out of the signal source if Ri >> RS .

An ideal amplifier is only a concept.Amplifier Resistances and Ideal Amplifiers Introduction to Electronics 21 + vi - + - Avocvi Fig. i. Current amplifier model (Fig. if the amplifier can “measure” the signal current with a low input resistance. and we may use the model. How can we maximize the current that gets delivered to the load ? G We can get the most current out of the signal source if Ri << RS . 28 repeated). But an amplifier may approach the ideal. Ideal voltage amplifier. In fact. 32. 33. if Ri ⇒0 . Signal source and load are omitted for clarity. we cannot build one. if only for its simplicity. Ideal Current Amplifier Now let’s revisit our current amplifier model: ii + vi io + vo - is RS Ri Aiscii Ro RL Source Current Amplifier Load Fig. like an ammeter does. we won’t have to worry about the value of RS at all!!! ..e.

Ideal Transconductance Amplifier With a mixture of the previous concepts we can conceptualize an ideal transconductance amplifier. 34. Ideal current amplifier. we won’t have to worry about the value of RL at all!!! This leads us to our conceptual ideal current amplifier: ii Aiscii Fig. 35. if the amplifier can look as much like a current source as possible.Amplifier Resistances and Ideal Amplifiers Introduction to Electronics 22 G We can get the most current out of the amplifier if Ro >> RL . This amplifier ideally measures the input voltage and produces an output current: + vi - Gmscvi Fig.e. In fact. Ideal transconductance amplifier. .. i. if Ro ⇒ ∞ .

Ideal transresistance amplifier. 36. . ideal amplifier models cannot be converted from one type to another (try it . .). Uniqueness of Ideal Amplifiers Unlike our models of “real” amplifiers. .Amplifier Resistances and Ideal Amplifiers Introduction to Electronics 23 Ideal Transresistance Amplifier Our final ideal amplifier concept measures input current and produces an output voltage: ii + - Rmocii Fig.

Frequency Response: Taken together the two responses are called the frequency response .Frequency Response of Amplifiers Introduction to Electronics 24 Frequency Response of Amplifiers Terms and Definitions In real amplifiers. . gain changes with frequency . Amplifier Gain: The gain of an amplifier usually refers only to the magnitudes: A v dB = 20log A v (31) . Magnitude Response: A plot of |Av| vs. . implies phasors . . . “Frequency” implies sinusoidal excitation which. Phase Response: A plot of ∠ Av vs. . f is called the phase response of the amplifier. using voltage gain to illustrate the general case: Av = V ∠Vo Vo = o = A v ∠A v Vi Vi ∠Vi (30) Both |Av| and ∠ Av are functions of frequency and can be plotted. though often in common usage the term frequency response is used to mean only the magnitude response. . f is called the magnitude response of the amplifier. in turn.

. . 38.Frequency Response of Amplifiers Introduction to Electronics 25 The Magnitude Response Much terminology and measures of amplifier performance are derived from the magnitude response . . |Av|dB midband region |Av mid|dB 3 dB Bandwidth. Magnitude response of a dc-coupled. . |Av|dB midband region |Av mid|dB 3 dB Bandwidth. or the half-power frequencies (why this last one?) . fL and fH are the 3-dB frequencies. . or RC-coupled amplifier. . |Av mid|dB is called the midband gain . B f (log scale) fL fH Fig. or direct-coupled amplifier. or simply the bandwidth (of the midband region) . . B is the 3-dB bandwidth. Magnitude response of an ac-coupled. the half-power bandwidth. the corner frequencies. . . 37. B f (log scale) fH Fig.

+ - + - Fig.Frequency Response of Amplifiers Introduction to Electronics 26 Causes of Reduced Gain at Higher Frequencies Stray wiring inductances . 39. Causes of Reduced Gain at Lower Frequencies This decrease is due to capacitors placed between amplifier stages (in RC-coupled or capacitively-coupled amplifiers) . Capacitances in the amplifying devices (not yet included in our amplifier models) . . . . The figure immediately below provides an example: + - + - Fig. This prevents dc voltages in one stage from affecting the next. . . Signal source and load are often coupled in this manner also. Two-stage amplifier model showing capacitive coupling between stages. . Two-stage amplifier model including stray wiring inductance and stray capacitance between stages. . Stray capacitances . . 40. . These effects are also found within each amplifier stage.

41. vICM . resulting in an induced 60 Hz voltage (as much as 30 V or so) from each wire to ground. Example: Telephone lines. . and a common-mode component. differential signals in the presence of much stronger. Modeling Differential and Common-Mode Signals 1 1 2 vI1 + vI2 + vICM + + + vID /2 2 Fig. The lines often run parallel to power lines for miles along highway right-of-ways . any two signals can be modeled by a differential component. common-mode signals. if: v I1 = v ICM + v ID 2 and v I 2 = v ICM − v ID 2 (32) . Representing two sources by their differential and common-mode components. We must extract and amplify the voltage difference between the wires. .Differential Amplifiers Introduction to Electronics 27 Differential Amplifiers Many desired signals are weak. which carry the desired voice signal between the green and red (called tip and ring) wires. vID . vID /2 As shown above. while ignoring the large voltage common to the wires.

Differential amplifier circuits are quite clever .Differential Amplifiers Introduction to Electronics 28 Solving these simultaneous equations for vID and vICM : v ID = v I1 − v I 2 and v ICM = v I1 + v I 2 2 (33) Note that the differential voltage vID is the difference between the signals vI1 and vI2 . Amplifier with differential and common-mode input signals. Amplifying Differential and Common-Mode Signals We can use superposition to describe the performance of an amplifier with these signals as inputs: + vicm + + vid /2 Amplifier vid /2 + vo = Ad vid + Acm vicm - Fig. preferably zero.they are the basic building block of all operational amplifiers Common-Mode Rejection Ratio A figure of merit for “diff amps.” CMRR is expressed in decibels: CMRRdB = 20log Ad Acm (34) . while the common-mode voltage vICM is the average of the two (a measure of how they are similar). A differential amplifier is designed so that Ad is very large and Acm is very small. 42.

.) The ideal operational amplifier is an ideal differential amplifier: A0 = Ad = ∞ Ri = ∞ B= ∞ Acm = 0 Ro = 0 Fig.v. and input-output relationship. just a voltage-dependent voltage source with the gain A0 (v+ . Ideal Operational Amplifier Operation With A0 = ∞ .then vo increases . . . In a real op amp vo cannot exceed the dc power supply voltages. . . which are not shown in Fig. If v+ < v. 2. we can conceive of three rules of operation: 1. . .then vo does not change . 3. . input and output voltages. .then vo decreases .a fraction of the output voltage is applied to the inverting input. . The input marked “+” is called the noninverting input . The input marked “-” is called the inverting input . is so simple that you should get used to analyzing circuits with just the schematic symbol. an operational amplifier circuit employs negative feedback .Ideal Operational Amplifiers Introduction to Electronics 29 Ideal Operational Amplifiers v+ v- + vO vO = A0 (v+ -v. In normal use as an amplifier. The ideal operational amplifier: schematic symbol. If v+ > v. .). 43. 43. The model. If v+ = v.

Ideal Operational Amplifiers Introduction to Electronics 30 Op Amp Operation with Negative Feedback Consider the effect of negative feedback: G If v+ > v.then vo increases . In our ideal op amp.v. Slew Rate So far we have said nothing about the rate at which vo increases or decreases .v. . then.= 0!!! In analyzing circuits.e. Because a fraction of vo is applied to the inverting input. vo takes on the value that causes v+ . this is called the slew rate. vo takes on the value that causes v+ .is reduced and will eventually become zero .then vo decreases .increases . .v. Thus.v.. . . Thus. infinitely fast).is reduced and will eventually become zero .= 0. . . . . v. The “gap” between v+ and v. . . .= 0!!! In either case. The “gap” between v+ and v. . . . v. Because a fraction of vo is applied to the inverting input.decreases . . the output voltage takes on whatever value that causes v+ . we’ll presume the slew rate is as fast as we need it to be (i.= 0!!! G If v+ < v. we need only determine the value of vo which will cause v+ .

because there is negative feedback.. Voltage Gain Because the ideal op amp has Ri = ∞ . vo takes on whatever value that causes v+ .e. Inverting amplifier circuit.Op Amp Circuits ..The Inverting Amplifier Introduction to Electronics 31 Op Amp Circuits .v. resistors R1 and R2 form a voltage dividerIII Therefore. (Remember the quick exercise on p. (35) to zero. and v+ = 0 !!! Thus. This means i1 = i2 . 44. the current into the inputs will be zero. setting eq. we can solve for vo : v i R2 + v oR1 = 0 ⇒ vo = − R2 vi R1 ⇒ Av = − R2 R1 (36) . we can use superposition to find the voltage v.= 0 . i.The Inverting Amplifier Let’s put our ideal op amp concepts to work in this basic circuit: + vO 0 i1 + vi R1 R2 i2 Fig. 4 ??? This is the identical problem!!!): v− = v i R2 + v o R1 R1 + R2 (35) Now.

Op Amp Circuits . Inverting amplifier circuit (Fig. Thus: i1 = vi R1 ⇒ Rin = vi vi = v = R1 i1 R i 1 (37) Output Resistance This is the Thevenin resistance which would be “seen” by a load looking back into the circuit (Fig. its Thevenin output resistance is zero: RO = 0 (38) .= 0. 45 does not show a load attached). Input Resistance This means resistance “seen” by the signal source vi . Our op amp is ideal.The Inverting Amplifier Introduction to Electronics 32 + vO 0 i1 + vi R1 R2 i2 Fig. 44 repeated). not the input resistance of the op amp. the voltage across R1 is vi . Because v. which is infinite. 45.

The Noninverting Amplifier If we switch the vi and ground connections on the inverting amplifier.Op Amp Circuits . Voltage Gain This time our rules of operation and a voltage divider equation lead to: R1 vi = v+ = v− = vo (39) R1 + R2 from which: vo =  R  R1 + R2 v i = 1 + 2 v i R1 R1   ⇒ Av = 1 + R2 R1 (40) Input and Output Resistance The source is connected directly to the ideal op amp. we obtain the noninverting amplifier: + vi i1 R1 R2 0 + vO i2 Fig.The Noninverting Amplifier Introduction to Electronics 33 Op Amp Circuits . so: Rin = Ri = ∞ (41) A load “sees” the same ideal Thevenin resistance as in the inverting case: (42) RO = 0 . 46. Noninverting amplifier circuit.

47. Rin = ∞ and RO = 0 (44) In fact. we should see that these values are the same as for the noninverting amplifier .. the output voltage follows the input voltage.The Voltage Follower + vi Fig. . + vo Voltage Gain This one is easy: vi = v+ = v − = vo ⇒ Av = 1 (43) i.The Voltage Follower Introduction to Electronics 34 Op Amp Circuits .Op Amp Circuits . the follower is just a special case of the noninverting amplifier. Input and Output Resistance By inspection. .e. The voltage follower. with R1 = ∞ and R2 = 0!!! .

The Inverting Summer Introduction to Electronics 35 Op Amp Circuits . but with three sources the equations become unnecessarily complicated . 48. .The Inverting Summer This is a variation of the inverting amplifier: + iA + vA RA vB + RB iB + RF vO iF - Fig. Recall . . So the voltage across RA is vA and the voltage across RB is vB : iA = vA RA and iB = vB RB (45) Because the current into the op amp is zero: iF = i A + iB v v  and v RF = RF (i A + i B ) = RF  A + B   R A RB  (46) Finally. . . . the voltage rise to vO equals the drop across RF : R  R v O = − F v A + F v B  RB   RA (47) . Voltage Gain We could use the superposition approach as we did for the standard inverter. . so let’s try this instead .= v+ = 0 . vO takes on the value that causes v. . .Op Amp Circuits . The inverting summer.

44. Notice that R3 . after we apply some network reduction techniques.Another Inverting Amplifier If we want very large gains with the standard inverting amplifier of Fig. Replacing part of the original circuit with a Thevenin equivalent . Voltage Gain One common approach to a solution begins with a KCL equation at the R2 . 50.R4 junction . . . .Op Amp Circuits . we’ll use the superposition & voltage divider approach. 49. one of the resistors will be unacceptably large or unacceptably small . . R4 and the op amp output voltage source can be replaced with a Thevenin equivalent: R4 R3 + vO RTH + vTH Fig. An inverting amplifier with a resistive T-network for the feedback element. . . We solve this problem with the following circuit: + vO i1 vi + R1 R2 i2 R4 R3 Fig.Another Inverting Amplifier Introduction to Electronics 36 Op Amp Circuits . .R3 .

and therefore vTH.Op Amp Circuits .Another Inverting Amplifier Introduction to Electronics 37 The values of the Thevenin elements in Fig. Equivalent circuit to original amplifier. and the standard inverting amplifier analysis of p. 4. 51. takes on the value necessary to make v+ . 31): v TH = − REQ vi R1 (49) Substituting for vTH and REQ . Again. vO . and solving for vO and Av : R + (R3 || R4 ) R R3 R || R  vO = − 2 v i = − 2 + 3 4 v i R3 + R 4 R1 R1   R1  R  R vO R || R  = −1 + 4   2 + 3 4  vi R1   R3   R1 (50) Av = (51) .= 0 Fig.= 0 . We’ve now solved this problem twice before (the “quick exercise” on p.v. 50 we can simplify the original circuit: vi R1 REQ = R2 + RTH vTH v. 50 are: v TH = R3 vO R3 + R4 and RTH = R3 || R4 (48) With the substitution of Fig. . .

vO takes on the value required to make v+ = v. v R = i 2R2 = 2 R2 R2R2 v1 − v R1 R1(R1 + R2 ) 2 (54) Then we sum voltage rises to the output terminal: vO = v + − v R = 2 R2 R R2R2 v 2 − 2 v1 + v R1 + R2 R1 R1(R1 + R2 ) 2 (55) . . vO Thus: v+ = R2 v2 = v− R1 + R2 (52) Fig.Differential Amplifier The op amp is a differential amplifier to begin with. .Op Amp Circuits . so of course we can build one of these!!! R1 + v2 i1 + v1 R1 + R2 R2 + i2 - Voltage Gain Again. The differential amplifier. we can calculate the voltage across R2 . 52.The Differential Amplifier Introduction to Electronics 38 Op Amp Circuits . which must equal the current i2 : (53) i1 = v1 − v − v1 R2 = − v 2 = i2 R1 R1 R1(R1 + R2 ) Knowing i2 . We can now find the current i1 ..

. (55): vO = − R2 R R v 1 + 2 v 2 = 2 (v 2 − v 1) R1 R1 R1 (58) So.The Differential Amplifier Introduction to Electronics 39 Working with just the v2 terms from eq. under the conditions that we can have identical resistors (and an ideal op amp) we truly have a differential amplifier!!! . . finally. (55) .Op Amp Circuits . returning the resulting term to eq. R2 R 2R 2 R1R2 R2R2 v2 + v2 = v2 + v2 R1 + R2 R1(R1 + R2 ) R1(R1 + R2 ) R1(R1 + R2 ) R (R + R2 ) R1R2 + R2R2 R v2 = 2 1 v2 = 2 v2 R1(R1 + R2 ) R1(R1 + R2 ) R1 (56) = (57) And.

. From the i-v relationship of a capacitor: t 1 1 v C = ∫ iC dt = ∫ iC dt + v C (0) C −∞ C0 Combining the two previous equations. Op amp integrator. and scaled by 1/RC. so . iR = vi = iC R (59) Fig. inverted. and recognizing that vO = .vC : t (60) 1 v 1 v O = − ∫ i dt + v C (0) = − v i dt + v C (0) C0R RC ∫ 0 t t (61) Normally vC (0) = 0 (but not always). .= 0 and iR = iC .Integrators and Differentiators Introduction to Electronics 40 Op Amp Circuits . Thus the output is the integral of vi .Op Amp Circuits .Integrators and Differentiators Op amp circuits are not limited to resistive elements!!! The Integrator + vO iR + vi R + C iC From our rules and previous experience we know that v. 53. .

Integrators and Differentiators Introduction to Electronics 41 The Differentiator + vO iC vi + C + R iR - This analysis proceeds in the same fashion as the previous analysis. . From our rules and previous experience we know that v. Fig.Op Amp Circuits . 54. The op amp differentiator. From the i-v relationship of a capacitor: iC = C dv C dv = C i = iR dt dt (62) Recognizing that vO = -vR : v O = −v R = −i R R = −RC dv i dt (63) . .= 0 and iC = iR .

Resistor tolerances will also affect gain. . Fig. resistances must be much larger than RS (if possible). we adopt the “rule of thumb” that resistances should be greater than approx. Of course this is highly dependent of the type of op amp to be used in a design. Source Resistance and Resistor Tolerances + vO i1 + vi RS R1 R2 i2 In some designs RS will affect desired gain. Noninverting amplifier with load. . . + vi R1 R2 + iF RL iL + vO - To limit iF + iL to a reasonable value. If we wish to ignore source resistance effects. Resistor tolerances must also be selected carefully. 55. Inverting amplifier including source resistance.Designing with Real Op Amps Introduction to Electronics 42 Op Amp Circuits . To limit these problems we adopt the “rule of thumb” that resistances should be less than approximately 1 MΩ. 56. real ones can’t . Fig.Designing with Real Op Amps Resistor Values Our ideal op amp can supply unlimited current. Larger resistances render circuits more susceptible to noise and more susceptible to environmental factors.Op Amp Circuits . 100 Ω.

Obviously. Simple example of obtaining the solution to simultaneous equations using a graphical method.. . .we can find the solution of two simultaneous equations by plotting them on the same set of axes. y=4. Here’s a trivial example: y =x and y =4 (64) We plot both equations: Fig. 57. the solution is where the two plots intersect. .Graphical Solution of Simultaneous Equations Introduction to Electronics 43 Graphical Solution of Simultaneous Equations Let’s re-visit some 7th-grade algebra . at x = 4..

y = 5. Another example of graphically finding the solution to simultaneous equations. Here we see that the solution is approximately at x = 3.6. but.Graphical Solution of Simultaneous Equations Introduction to Electronics 44 Let’s try another one:  0.2. we gain the insight that comes with the “picture.4x . for x ≥ 0 and (65) y =8− 4x 5 (66) Fig. Note that we lose some accuracy with a graphical method.” . 58. for x < 0 y = 2 0.

. we’ll see that we can’t arbitrarily neglect the other quadrants: y = 0. for all x (67) and y =8− 4x 5 (68) Fig.Graphical Solution of Simultaneous Equations Introduction to Electronics 45 If we change the previous example slightly.5. .4 x 2. . 59. the second solution is at x = -5. Now we have two solutions . In the pages and weeks to come. This technique is especially well-suited to circuits with nonlinear elements.the first one we found before. at x = 3. y = 12.6. we will often use a graphical method to find current and voltage in a circuit. Graphically finding multiple solutions.5. y = 5.2 .

current flow is essentially zero. vD > 0).. this is our first nonlinear element: free ”holes” free electrons Anode Cathode + + + + . Simplified physical construction and schematic symbol of a diode. . Of course. .this is not necessarily destructive. When we apply an external voltage that opposes this combination. . we can apply a large enough reverse voltage to force current to flow . The free holes “wish” to combine with the free electrons .iD + vD - Fig.Diodes Introduction to Electronics 46 Diodes When we “place” p-type semiconductor adjacent to n-type semiconductor. but restricts current flow in the opposite direction . . When we apply an external voltage that facilitates this combination (a forward voltage.. vD < 0).n-type p-type + + + . . . . current flows easily. 60. the result is an element that easily allows current to flow in one direction. (a reverse voltage.

PSpice-generated i-v characteristic for a 1N750 diode showing the various regions of operation. In the reverse bias region. less often. Diodes intended for use in the breakdown region are called zener diodes (or. G It ranges from 3.7 V. the forward voltage. . VF is called the forward knee voltage. G It is typically approximately 0. or simply. and is usually given as a positive value. the typical diode i-v characteristic: Fig. 61. and has a temperature coefficient of approximately -2 mV/K VB is called the breakdown voltage.3 V to kV.Diodes Introduction to Electronics 47 Thus. |iD| ≈ 1 nA for low-power (“signal”) diodes. avalanche diodes).

. A plot of this line is called the load line. 62. 63. and the graphical procedure is called load-line analysis. from Fig. . This is just a standard Thevenin equivalent circuit . . The first equation is “provided” by the diode i-v characteristic. 2: v = VOC − iRTH or i = ISC − v RTH (69) i=iD ISC 1/R TH . 62 identified. The second equation comes from the circuit to which the diode is connected. . Thevenin eq. of Fig. . RTH(=R) i + VOC Fig. 64. . and we already know its i-v characteristic . Example circuit to illustrate graphical diode circuit analysis. Graphical solution. (4) on p. . where VOC and ISC are the opencircuit voltage and the short-circuit current.Graphical Analysis of Diode Circuits Introduction to Electronics 48 Graphical Analysis of Diode Circuits We can analyze simple diode circuits using the graphical method described previously: R + VS Fig. . + (=VS) v - . V OC v=v D Fig. iD + vD - We need two equations to find the two unknowns iD and vD . respectively. 5 and eq. .

V The solution is at: vD ≈ 0. so we use the slope: The solution is at vD ≈ 0.71 V.5 V and ISC = 2.5 V and R = 125 Ω Case 2: VS = 1 V and R = 25 Ω Case 3: VS = 10 V and R = 1 kΩ Case 1: VOC = VS = 2. 66. 62 repeated).Graphical Analysis of Diode Circuits Introduction to Electronics 49 Examples of Load-Line Analysis R + VS Fig. iD + vD - Case 1: VS = 2.70 V. iD ≈ 14.68 V. use slope: 1 1 kΩ .5 V / 125 Ω = 20 mA.3 mA Fig. . We locate the intercepts.5mA 0 V ISC is not on scale. iD ≈ 9. 65. = 1mA = 2255mA V .0 mA Case 3: VOC = VS = 10 V ISC = 10 V / 1 kΩ = 10 mA VOC not on scale.3 mA Case 2: VOC = VS = 1 V and ISC = 1 V / 25 Ω = 40 mA 1 25 Ω mA = 40V = 20. The solution is at vD ≈ 0. Example solutions. iD ≈ 12. and draw the line. Example circuit (Fig.

charge of an electron. for accuracy. we need an equation. .6 (10-19) C Note: at T = 300 K.9 mV we’ll use VT = 25 mV as a matter of convenience. temperature in kelvins q. The Shockley Equation  v   iD = IS exp D  − 1  nVT    or conversely (70) i  v D = nVT ln D + 1  IS  where. Boltzmann’s constant. VT = 25. V = kT T q (72) k. n is the emission coefficient. 1 ≤ n ≤ 2 (71) n = 1 is usually accurate for signal diodes (iD < 10 mA) VT is the thermal voltage. .38 (10-23) J/K T. but neither convenience nor accuracy . .Diode Models Introduction to Electronics 50 Diode Models Graphical solutions provide insight. ≈ 10 fA for signal diodes IS approx. k = 1. IS is the saturation current. q = 1. doubles for every 5 K increase in temp.

exp(vD /nVT ) << 1. . usually between 10 Ω and 100 Ω. and: i D ≈ −IS (76) At High Currents: i  v D = nVT ln D + 1 + i DRS  IS  (77) where RS is the resistance of the bulk semiconductor material. exp(vD /nVT ) >> 1.Diode Models Introduction to Electronics 51 Repeating the two forms of the Shockley equation:  v   iD = IS exp D  − 1  nVT    i  v D = nVT ln D + 1  IS  Forward Bias Approximation: (73) (74) For vD greater than a few tenths of a volt. and: v  iD ≈ IS exp D   nVT  Reverse Bias Approximation: (75) For vD less than a few tenths (negative).

Both segments are linear . . . . 67. if we knew the correct segment we could use linear analysis!!! In general we don’t know which line segment is correct .” we know that iD = 0. and reasonable accuracy in many cases .Diode Models Introduction to Electronics 52 Let’s stop and review . Ideal diode i-v characteristic. G G Graphical solutions provide insight. If we guess “OFF.” we know that vD = 0. . and then determine if our guess is correct. and that iD must turn out to be positive if our guess is correct. .so we must guess . too). vD rev bias (OFF) Fig. The Ideal Diode + - iD This is the diode we’d like to have. . . not convenience. We normally ignore the breakdown fwd bias (ON) region (although we could model this. . But we can approximate the diode i-v characteristic to provide convenience. not accuracy. and that vD must turn out to be negative if our guess is correct. If we guess “ON. The Shockley equation provides accuracy. .

4 kΩ + 10 V 6 kΩ 3 kΩ iD 7 kΩ + 10 V If ON. iD = 0. 69.4 kΩ + 6V iD 667 µA 2.Diode Models Introduction to Electronics 53 An Ideal Diode Example: 4 kΩ + 10 V 6 kΩ 3 kΩ iD + vD 7 kΩ + 10 V We need first to assume a diode state. vD is not negative. . i. 68. We’ll arbitrarily choose OFF.Circuit for an ideal diode example. No contradictions !!! Fig. vD = 0. 2. ⇒ iD = 667 µA.1 kΩ + 3V We can easily find iD using Thevenin eqs. Fig.. i. 72.e. Fig.. the diode is a short circuit. ON or OFF. 4 kΩ + + 10 V + 6 V 6 kΩ vD 7 kΩ 3 kΩ + 3V + 10 V - We can easily find vD using voltage division and KVL ⇒ vD = 3 V.Calculating vD for the OFF diode.Calculating iD for the ON diode. the diode is an open circuit. Fig. Fig. 71. so diode must be ON. 4 kΩ + + 10 V 6 kΩ 3 kΩ 7 kΩ + 10 V vD If OFF..Equivalent circuit if the diode is OFF.Equivalent circuit if the diode is ON.e.e. 70. i.

Ideal diode i-v characteristic. . Calculate vD for all OFF diodes. If not make new assumption and repeat. If all OFF diodes have vD < 0. Make assumptions about diode states. 3. and iD for all ON diodes. These rules apply even to circuits with multiple diodes: + - iD fwd bias (ON) vD rev bias (OFF) Fig.Diode Models Introduction to Electronics 54 Let’s review the techniques. or rules. 73. (Fig. 67 repeated) 1. and all ON diodes have iD > 0. the initial assumption was correct. used in analyzing ideal diode circuits. 2.

Piecewise-linear modeling uses straight line segments to approximate various parts of a nonlinear i-v characteristic. The line segment at left has the equation: i v = VX + iR X 1/RX (78) v VX -V X /RX The same equation is provided by the following circuit: VX . 75 to represent the element with the approximated characteristic!!! .+ Fig. 74. . .Diode Models Introduction to Electronics 55 Piecewise-Linear Diode Models This is a generalization of the ideal diode concept. and use the equivalent circuits of Fig. RX v + i - Fig. . A piecewise-linear segment. Thus. we can use the line segments of Fig. Circuit producing eq. 75. . 74 to approximate portions of an element’s nonlinear i-v characteristic . . (?).

an open circuit. VZ . G In the breakdown region . . . RF . VF . the approximating segment is characterized by iD = 0. . RZ . . . . G In the forward bias region . G In the reverse bias region . . . .e. A diode i-v characteristic (red) and its piecewise-linear equivalent (blue).Diode Models Introduction to Electronics 56 A “complete” piecewise-linear diode model looks like this: iD VZ 1/RZ VF 1/RF vD Fig. the approximating segment is characterized by the zener voltage.. . 76. and the forward resistance. (or breakdown voltage. . i. VB ) and the zener resistance. . . . the approximating segment is characterized by the forward voltage. . .

588 V (80) Fig. RF = 10 Ω .Diode Models Introduction to Electronics 57 A Piecewise-Linear Diode Example: We have modeled a diode using piecewise-linear segments with: VF = 0. let us choose the forward bias region first. Equivalent circuit in forward bias region.5 V + (8.5 V. 77.82 mA )(10 Ω) = 0. We have Fig. 500 Ω + + 5V 0. and that is the direction of forward diode current.5 V = 8.5 Ω Let us find iD and vD in the following circuit: 500 Ω iD + 5V + vD - We need to “guess” a line segment.82 mA 500 Ω + 10 Ω (79) v D = 0.5 V 10 Ω vD + iD = and 5 V − 0. Because the 5 V source would tend to force current to flow in a clockwise direction. . 78. Our equivalent circuit for the forward bias region is shown at left. This solution does not contradict our forward bias assumption.5 V. RZ = 2. Circuit for piecewiselinear example. and VZ = 7. so it must be the correct one for our model.

. . . 80. RF = 0 in the forward bias region . .Diode Models Introduction to Electronics 58 Other Piecewise-Linear Models + - iD fwd bias (ON) Our ideal diode model is a special case . . it doesn’t breakdown region. (Fig. . have a + - iD fwd bias (ON) The constant voltage drop diode model is also a special case . . . .7 V . it has VF = 0. . I-v characteristic of constant voltage drop diode model. .6 to 0. . . . . VF usually 0. . 67 repeated) . it has RF = 0 in the forward bias region . . . . . . . vD rev bias (OFF) Fig. . 79. . . it doesn’t breakdown region have a vD VF rev bias (OFF) Fig. Ideal diode i-v characteristic.

Hence. . they are called voltage regulators. . Thevenin equivalent source with unpredictable voltage and zener diode. the schematic symbol changes slightly . a very small RZ . .5 V to 10 V vD + iD + vOUT - Note: when intended for use as a zener diode. We can use load line analysis with the zener diode i-v characteristic to examine the behavior of this circuit. . . Fig. . zener current can flow only if the zener is in the breakdown region . in breakdown region. 81.The Zener Diode Voltage Regulator Introduction This application uses diodes in the breakdown region .The Zener Diode Voltage Regulator Introduction to Electronics 59 Diode Applications . . For VZ < 6 V the physical breakdown phenomenon is called zener breakdown (high electric field).. For VZ > 6 V the mechanism is called avalanche breakdown (high kinetic energy). For VZ ≈ 6 V the breakdown voltage has nearly zero temperature coefficient. Load-Line Analysis of Zener Regulators RTH = 500 Ω + VTH 7.e. It has a positive temperature coefficient. With VTH positive. and a nearly vertical i-v char. i. These circuits can produce nearly constant voltages when used with voltage supplies that have variable or unpredictable output voltages. It has a negative temperature coefficient.

81 repeated) Because the zener is upside-down the Thevenin equivalent load line is in the 3rd quadrant of the diode characteristic. VTH is called the line voltage. Fig. - Fig. (Fig. in return we get a very constant output voltage. Thevenin equivalent source with unpredictable voltage and zener diode.7 V) the zener remains in the breakdown region. This is an example of a zener diode voltage regulator providing line voltage regulation .The Zener Diode Voltage Regulator Introduction to Electronics 60 RTH = 500 Ω + vD + iD VTH 7. vOUT remains nearly constant. . If we’re willing to give up some output voltage magnitude. 82. 83 + below shows the graphical vOUT construction. the load line moves from its blue position.7 V) i-v characteristic in breakdown region. 83. .7 V. As VTH varies from 7. with load lines from source voltage extremes. to its green position. .5 V to 10 V - Note that vOUT = -vD . at ≈ 4.5 V to 10 V. Fig. 1N750 zener (VZ = 4. As long as the minimum VTH is somewhat greater than VZ (in this case VZ = 4. As long as the zener remains in breakdown.

83 with piecewise-linear segment.6 V and RZ = 8 Ω. 85. From the intercept and slope of the piecewise-linear segment we obtain VZ = 4.6 V + vOUT - Fig.The Zener Diode Voltage Regulator Introduction to Electronics 61 Numerical Analysis of Zener Regulators To describe line voltage regulation numerically we use linear circuit analysis with a piecewise-linear model for the diode. . Zener i-v characteristic of Fig.5 V to 10 V 8Ω + 4. Regulator circuit of Fig. To obtain the model we draw a tangent to the curve in the vicinity of the operating point: Fig. 84. Our circuit model then becomes: RTH = 500 Ω + VTH 7. 81 with piecewiselinear model replacing the diode.

for a 2.64567 V (82) For VTH = 10 V: V8 Ω = 8Ω (10 V − 4. the output voltage change is only 39.67 mV = 4. Regulator with diode model (Fig. forming a voltage divider. 85 repeated).67 mV 500 Ω + 8 Ω (81) VO = 4. Important: The model above is valid only if zener is in breakdown region !!! Circuit Analysis: The 500 Ω and 8 Ω resistors are in series.4 mV !!! .5 V to 10 V - Fig. 86.04 mV = 4.6 V) = 45.6 V + 45.68504 V (84) Thus.6 V) = 85.6 V + vOUT - VTH 7. For VTH = 7.5 V − 4.5 V change in the line voltage.5 V: V8 Ω = 8Ω (7.The Zener Diode Voltage Regulator Introduction to Electronics 62 RTH = 500 Ω + 8Ω + 4.04 V 500 Ω + 8 Ω (83) VO = 4.6 V + 85.

. 89. . The resulting circuit is topologically identical to the circuit we just analyzed!!! Different loads will result in different values for VTH and RTH . 88. but the analysis procedure remains the same!!! . 87. 87 with VSS . Regulator of Fig. Regulator drawn with zener and load in reversed positions. Zener regulator with load.The Zener Diode Voltage Regulator Introduction to Electronics 63 Zener Regulators with Attached Load Now let’s add a load to our regulator circuit . Fig. and RL replaced by Thevenin eq. so we approach this problem by finding the Thevenin equivalent seen by the diode: RS + VSS RL + vOUT vD + iD + VTH RTH + vOUT vD + iD Fig. + RL vOUT - Only the zener is nonlinear. RS . RS + VSS vD + iD Fig.

(a) RL = 10 kΩ (b) RL = 1 kΩ (c) RL = 100 Ω RS = 500 Ω + VSS 10 V vD + iD + RL vOUT - Fig. RS = 500 Ω and.Graphical Analysis of Loaded Regulator Let’s examine graphically the behavior of a loaded zener regulator. We find the load lines in each case by calculating the open-circuit (Thevenin) voltage and the short-circuit current: (a) VOC = VTH = ISC = 10 kΩ 10 V = 9.52 V 10 kΩ + 500 Ω VSS 10 V = = 20 mA RS 500 Ω 1 kΩ 10 V = 6. 90.67 V 1kΩ + 500 Ω (85) (86) (b) VOC = VTH = ISC = (87) VSS 10 V = = 20 mA RS 500 Ω (88) . Example of loaded zener regulator for graphical analysis. Let VSS = 10 V.The Zener Diode Voltage Regulator Introduction to Electronics 64 Example .

Load line analysis for the loaded zener regulator. As long as RL (and therefore VTH ) is large enough so that the zener remains in breakdown. the output voltage is nearly constant !!! This is an example of a zener diode voltage regulator providing load voltage regulation (or simply. 10 V = 167 V 100 Ω + 500 Ω VSS 10 V = = 20 mA RS 500 Ω (89) (90) The three load lines are plotted on the zener characteristic below: Fig. 91. load regulation). .The Zener Diode Voltage Regulator Introduction to Electronics 65 (c) VOC = VTH = ISC = 100 Ω .

.The Half-Wave Rectifier Introduction to Electronics 66 Diode Applications . . 94. v O = vS During negative half-cycle . Waveform of voltage source.The Half-Wave Rectifier + vD + Vm sin ωt + vO - Introduction This diode application changes ac into dc. . Output voltage waveform. vO = 0 . . vS RL Fig. . diode “OFF” . . . . vS Vm t T -Vm . . . PIV: T t Another term for breakdown voltage rating . 93. . vD = 0 . We’ll assume the diode is ideal for our analysis. diode conducts (“ON”) . . Fig. vD = vS Fig. . . . . -Vm Fig. vO Vm t T . . . . 95. The half-wave rectifier circuit. the diode PIV rating must be > Vm . During positive half-cycle . in this circuit. Diode voltage waveform. The voltage source is most often a sinusoid (but can be anything). . . vD Peak Inverse Voltage. iD = 0. 92. .

. Rtotal includes all resistance (wiring. 97. battery. and VBATT represents the battery voltage.) reflected to the transformer secondary winding. 96. . .The Half-Wave Rectifier Introduction to Electronics 67 A Typical Battery Charging Circuit Rtotal 110 Vrms + Vm sin ωt A Fig. Here vS represents the transformer secondary voltage. A circuit typical of most battery chargers. . . vS Charging current Vm VBATT t T -Vm Fig. . D + VBATTERY In the figure above . . diode. . VBATTERY represents the battery to be charged . . . . . . . Charging current flows only when Vm sin ωt > VBATTERY . Battery charger waveforms. inertia of meter movement allows indication of average current. etc. . .

Load voltage waveform in the filtered half-wave rectifier. so we will use the ideal diode model. a half-wave rectifier with a smoothing capacitor. A lot happens in this circuit!!! Let’s look at the load voltage: vL(t) Vm Ripple voltage. . or a half-wave rectifier with a capacitor-input filter. . 99. . Vr t on diode off on diode off on T T Fig. 98. . Filtered half-wave rectifier. . . RL Fig.The Half-Wave Rectifier Introduction to Electronics 68 The Filtered Half-Wave Rectifier Also called a peak rectifier. We create it by placing a capacitor in parallel with the rectifier load (creating a low-pass filter): iD (t) + vS (t) C iL (t) + vL (t) Analysis of this circuit with a nonlinear element is very difficult .

vS can only be infinitesimally greater than vL ) 2. 99 repeated). and the voltage source charges the capacitor. This means that: (a) the load voltage is essentially “pure” dc (b) the diode is off for almost the entire period. Vr t on diode off on diode off on T T Fig. We define peak-to-peak ripple voltage. 3. We let vS (t) = Vm sin ωt . When vS < vL (shown in red). (Because the diode and source are ideal. When vS > vL (shown in blue).The Half-Wave Rectifier Introduction to Electronics 69 vL(t) Vm Ripple voltage. as the total change in vL over one cycle. the diode is on. Vr . 100. Vr is much smaller than shown here.g. typically being 1% to 0. . . In practice. . the diode is off. and assume steady-state . . a few mV).. T !!! . Load voltage waveform (Fig. and C discharges exponentially through RL .01% of Vm (e. 4. 1.

Load voltage waveform (Fig. The charge taken from the capacitor in this interval is: Q ≈ ILT ≈ Vm V T = m RL fRL (91) The capacitor voltage decreases by Vr in this interval. Vr t on diode off on diode off on T T Fig. the capacitor must supply the “dc” load current during this interval. which requires a decrease in the charge stored in the capacitor: Q = Vr C (92) Equating these equations and solving for C gives us a design equation that is valid only for small Vr : Vr C = Vm fRL ⇒ C= Vm Vr fRL (93) . 101. 99 repeated). Relating Capacitance to Ripple Voltage Because the diode is off for nearly the entire period.The Half-Wave Rectifier Introduction to Electronics 70 vL(t) Vm Ripple voltage. T.

i(t) iD PEAK iD(t) iL(t) t on diode off on diode off on T T Fig. Vr t on diode off on diode off on T T Fig. 103. vL(t) Vm Ripple voltage. 102. Current waveforms in filtered half-wave rectifier. as illustrated below. Load voltage waveform (Fig.The Half-Wave Rectifier Introduction to Electronics 71 Because all of the charge supplied to the load must come from the source only when the diode is ON. iD PEAK can be very large.. 99 repeated). .

1st (Positive) Half-Cycle: Current flows from upper source. while the lower half of the secondary voltage has its positive reference at ground. 104. -Vm Fig. thus DA is off. Voltage across each half of the transformer secondary. .The Full-Wave Rectifier Introduction to Electronics 72 Diode Applications . returning to lower source via ground. Any current through DA would be in reverse direction. vS Vm t Vm t vL Fig. 105. iL (t) + vL (t) - Operation Note that the upper half of the transformer secondary voltage has its negative reference at ground. Full-wave load voltage. 106. The full-wave rectifier. through DA and RL.The Full-Wave Rectifier The full-wave rectifier makes use of a center-tapped transformer to effectively create two equal input sources: vA (t) vin (t) + vS (t) + vS (t) DA DB RL vB (t) Fig. Any current through DB would be in reverse direction. thus DB is off. 2nd (Negative) Half-Cycle: Current flows from lower source. through DB and RL. returning to upper source via ground.

When DB is on. Fig. 107. Voltage across diode DB . . vA t vB t -2Vm -2Vm Fig.The Full-Wave Rectifier Introduction to Electronics 73 vA (t) vin (t) + vS (t) + vS (t) DA DB RL vB (t) Fig. iL (t) + vL (t) - Diode Peak Inverse Voltage When DA is on. 104 repeated). a KVL path around the “outside” loop of the transformer secondary shows that DB must withstand a voltage of 2vS . . DA is off . . . 108. now a KVL path shows that DB must withstand 2vS . 109. DB is off . Thus the diode PIV rating must be 2Vm . . Diode voltage waveforms are shown below . . Voltage across diode DA . . The full-wave rectifier (Fig.

through D1 and RL . v 2. 2nd (Negative) Half-Cycle: t Fig. then via ground through D4 . The bridge rectifier. v 3 t -Vm Current flows from bottom end of vS . Full-wave load voltage. thus the diode PIV is Vm . vS Vm t -Vm Operation 1st (Positive) Half-Cycle: Current flows from top end of vS .The Bridge Rectifier Introduction to Electronics 74 Diode Applications . v 1. 112. vL Vm Fig. 110. . Fig. Diode voltage for D1 and D3 .The Bridge Rectifier The bridge rectifier is also a full-wave rectifier. but uses a diode bridge rather than a center-tapped transformer: D4 D1 vin (t) + vS (t) - iL (t) + vL (t) - D3 D2 Fig. v 4 t -Vm Peak Inverse Voltage: In each half-cycle the OFF diodes are directly across vS . 113. and back to vS . Fig. 111. and back to vS . Diode voltage for D2 and D4 . through D2 and RL . 114. then via ground through D3 . Input voltage to diode bridge.

Full-Wave/Bridge Rectifier Features Introduction to Electronics 75 Diode Applications . a factor of 2 appears in denominator of eq. Preferable only at low voltages (one less diode forward-voltage drop). Thus. That is. . Filtered Full-Wave and Bridge Rectifiers Because the rectifier output voltage is “full-wave. the design equation is valid only for small Vr .Full-Wave/Bridge Rectifier Features Bridge Rectifier Much cheaper transformer more than offsets the negligible cost of two more diodes. for a given ripple voltage. Full-Wave Rectifier Archaic since vacuum tube rectifiers have largely been replaced by semiconductor rectifiers. if at all. only half the capacitance is required (all other parameters being equal).” C discharges for approximately only half as long as in the half-wave case. (93): Vr C = Vm 2fRL ⇒ C= Vm 2Vr fRL (94) Remember though.

but will have to deal with cutoff and saturation. Current in one p-n junction affects the current in the other p-n junction. There are four regions of operation: CBJ rev. fwd. emitter-base junction (EBJ). Feature iC = iE = iB = 0 amplifier vCE nearly zero limited use B p-type base n-type emitter E Fig. Discussion of inverse region operation is left for another time.Bipolar Junction Transistors (BJTs) Introduction to Electronics 76 Bipolar Junction Transistors (BJTs) Introduction The BJT is a nonlinear. rev. fwd. fwd. Operating Region cutoff active saturation inverse EBJ rev. 3-terminal device based on the junction diode. The npn BJT representative physical structure (left). rev. and circuit symbol (right). A representative structure sandwiches one semiconductor type between layers of the opposite type. We first examine the npn BJT: C n-type collector C iC iB B +v BE + vCE iE E Two junctions: collectorbase junction (CBJ). . 115. fwd. We’re most interested in the active region. as well.

iB is small. consists mostly of electrons being injected into base region.this is how we get this device to amplify!!! B p G n E Fig.r. Active-region BJT currents. creating a collector current!!! C n G The relative current magnitudes are indicated by the arrow thicknesses in the figure. Fwd-biased EBJ ⇒ base positive w. . a small change in base current can cause a large change in collector current . Some of the injected electrons combine with holes in base region. . Most of the electrons travel across the narrow base and are attracted to the positive collector voltage. Because iB is so small. because the base is lightly doped. Base region very lightly doped and very narrow .t base.lots of electrons available to conduct current.very few holes available to conduct current. Emitter current. 116. . Rev-biased CBJ ⇒ collector positive w.r.t emitter. . iE .Bipolar Junction Transistors (BJTs) Introduction to Electronics 77 Qualitative Description of BJT Active-Region Operation G G G G G Emitter region is heavily doped . .

:  v   i E = IES exp BE  − 1  VT    where. Remember!!! Eqs. Npn BJT schematic symbol.9 and 1. Eq.0.Bipolar Junction Transistors (BJTs) Introduction to Electronics 78 Quantitative Description of BJT Active-Region Operation C iC iB B + vCE +v BE . (95) and (96) apply always. Usually.99 being typical. which is dependent on the manufacturing process. IES ranges from pA to fA and n is usually ≈ 1 Also. .iE E Fig. from KCL: i E = i B + iC (95) (96) In the active region (only!!!) iC is a fixed % of i E. (97) applies only in the active region. 117. α falls between 0. The emitter-base junction (EBJ) is a diode and is governed by the Shockley eqn. thus: α= iC iE (97) Ideally. we would like α = 1. We assign the symbol α to that ratio. with 0.

small changes in iB produce large changes in iC .99.Bipolar Junction Transistors (BJTs) Introduction to Electronics 79 From eqs. we may approximate: (98) v  iC ≈ IS exp BE   VT  where the scale current. Rearranging eq. (101) gives: iC = β i B (103) Thus. from eqs. (101) for α: α= β β +1 (102) For α = 0. (96) and (97) we have: i E = iC + i B ⇒ i E = αi E + i B ⇒ i B = (1 − α )i E (100) thus iC αi E α = = =β iB (1 − α )iE 1 − α (101) Solving the right-hand half of eq. (99) Also. so again we see that the BJT can act as an amplifier!!! . IS = αIES . we have β = 100. (95) and (97) we have:  v   iC = αi E = αIES exp BE  − 1  VT    and for a forward-biased EBJ.

Not surprisingly. Input Characteristic First. The figure at left represents only how we might envision measuring these characteristics. 119. This is called the input characteristic because the base-emitter will become the input terminals of our amplifier. 118.vBE relationship (with vCE fixed). we measure the iB .Circuit for measuring BJT characteristics. In practice we would never connect sources to any device without current-limiting resistors in series!!! Fig. Typical input characteristic of an npn BJT.BJT Common-Emitter Characteristics Introduction to Electronics 80 BJT Common-Emitter Characteristics Introduction iC iB + v+ BE + vCE + - We use the term common-emitter characteristics because the emitter is common to both voltage sources. . we see a typical diode curve: Fig.

We can also identify the cutoff and saturation regions . 120. Note that iC and iB are related by the ratio β. 118 repeated).7 V. the CBJ will be reverse-biased as long as vCE > 0. and that the CBJ be reverse-biased. Thus. A forward-biased EBJ means that vBE ≈ 0. as long as the BJT is in the active region. Circuit for measuring BJT characteristics (Fig. 121. Active Region: Recall that the active region requires that the EBJ be forwardbiased. we measure a family of iC .7 V. Fig. . Typical output characteristics of an npn BJT. .BJT Common-Emitter Characteristics Introduction to Electronics 81 Output Characteristics Next.vCE curves for various values of base current: iC iB + + vCE v+ BE + - Fig. .

.5 V before the iC = βiB relationship disappears.5 V before appreciable forwardcurrent flows. Cutoff: The EBJ is not forward-biased (sufficiently) if iB = 0. . vBE ≈ 0.7 V. Thus. Saturation: When the EBJ is forward-biased. the CBJ is reverse-biased for any vCE > 0.4 V to 0. just as a diode must be forward-biased by 0.e.4 V to 0.7 V. 122.7 V. Note that the CBJ must become forward-biased by 0.BJT Common-Emitter Characteristics Introduction to Electronics 82 Fig. the saturation region lies to the left of vCE = 0. BJT output characteristics with cutoff and saturation regions identified. Thus the cutoff region is the particular curve for iB = 0 (i. the horizontal axis). Then.

Note that the current and voltage references have been reversed. . . But the equations have the same appearance: C p-type collector C iC iB B vEC + vEB + iE E B n-type base p-type emitter E Fig. i E = i B + iC and  v   iE = IES exp EB  − 1  VT    (104) And for the active region in particular. In general. . . 123. Note that the voltage and current references are reversed. . i C = βi B and v  iC ≈ IS exp EB   VT  (105) where. iC and iE resulting from active region operation also flow in the opposite direction. the latter equation is the approximation for a forward-biased EBJ.The pnp BJT Introduction to Electronics 83 The pnp BJT We get the same behavior with an n-type base sandwiched between a p-type collector and a p-type emitter: Now current in a fwd. iC = α i E . biased EBJ flows in the opposite direction . A pnp BJT and its schematic symbol. .

Fig. .The pnp BJT Introduction to Electronics 84 Because the voltage and current references are reversed. Output characteristics of a pnp BJT. 125. Input characteristic of a pnp BJT. 124. the input and output characteristics appear the same also: Fig.

. . This is due to the Early effect. Typical value of VA is 50 V to 100 V.Secondary Effects Introduction to Electronics 85 BJT Characteristics . One secondary effect you need to be aware of . VA . a change in base width as vCE changes (also called base width modulation) . BJT output characteristics illustrating Early voltage. . . Extensions of the actual output characteristics intersect at the Early voltage. G G G G Output characteristics are not horizontal in the active region. Other secondary effects will be described as needed. . Fig. but have an upward slope . .BJT Characteristics . .Secondary Effects The characteristics of real BJTs are somewhat more complicated than what has been presented here (of course!!!). . 126. .

Description of Operation Drain D iD iG = 0 G + vDS +v GS iD S Source Fig. Depletion region depicted for vGS = 0. . . . Gate p n p Source Fig. . . . 128. Electrons move from ntype into p-type . Region near the p-n junction is left without any available carriers depletion region Gate p n-type p channel Drain The depletion region is shown at left for zero applied voltage (called zero bias). . . . or FET. and functions. . specifically. somewhat differently than the BJT. . but it is constructed. . We begin with the junction FET (JFET). the n-channel JFET. 127. There are several types. Carriers are still present in the n-type channel .The n-Channel Junction FET Introduction to Electronics 86 The n-Channel Junction FET (JFET) The field-effect transistor. vDS = 0. The p-n junction is a typical diode . Holes move from p-type into n-type . Current could flow between drain and source (if vDS ≠ 0) . The n-channel JFET representative physical structure (left) and schematic symbol (right). . Channel has relatively low resistance. is also a 3-terminal device.

Thus. And positive voltage at the Source pulls electrons away from junction. Because negative voltage at the Gate pulls holes away from junction. 131. Drain With sufficient reverse bias the depletion region pinches-off the entire channel: vGS = VP . region. This region of FET operation is called the voltage-controlled resistance. Typical values: -5 < VP < -2 Gate + vGS = VP - p n p Source Fig. Fig. pinch-off voltage The channel resistance becomes infinite. Depletion region at pinch-off (vGS = VP). Thus. Gate + vGS < 0 - p n p Source Fig. or triode. 129. current flow impossible for any vDS (less than breakdown). the depletion region width increases. and the channel resistance increases. Depletion region for negative vGS (reverse bias). the channel becomes narrower. the FET looks like a voltagecontrolled resistance at small values of vDS .The n-Channel Junction FET Introduction to Electronics 87 Drain As the reverse bias increases across the p-n junction. FET i-v curves for small vDS . . 130.

Source Fig. Thus the channel becomes more restricted and.. as vDS increases. Note that they are very similar to BJT curves. 133. Drain + |VP| - For vDS = |VP | channel becomes pinched-off only at drain end.. we have a device with the output characteristics at left.e. the depletion region becomes asymmetrical: Drain + 0 < vDS < |VP| - Gate p n p Reverse bias is greater at the drain end. Source Fig. The rate of drift. but independent of vDS!!! As vGS changes. though the physical operation is very different. for fixed vGS . the curves become horizontal at different values of drain current. more horizontal). so the depletion region is greater at the drain end. Asymmetrical depletion region as vDS increases. Thus. i-v curves become flatter (i. N-channel JFET output characteristics (2N3819). and therefore the drain current flow. 132.The n-Channel Junction FET Introduction to Electronics 88 Now. on vGS).Pinch-off at drain end for vDS = VP . Fig. . 134. vDS Gate p n p Carriers drift across pinched-off region under influence of the E field. is dependent on width of entire channel (i.e.

and vGD > VP : i D = K 2(v GS − VP )v DS − v DS 2 [ ] (107) where K has units of amperes per square volt. Note that vGS is never allowed to forward bias the p-n junction !!! . and for any vDS : iD = 0 (106) Triode Region: The FET is in the triode region for 0 > vGS > VP . for small v DS (108) and the channel resistance is approximately given by: Rchannel ≈ Pinch-Off Region: v DS 1 ≈ iD 2K (v GS − VP ) (109) The FET is in the pinch-off region for 0 > vGS > VP .The n-Channel Junction FET Introduction to Electronics 89 Equations Governing n-Channel JFET Operation Cutoff Region: The FET is in cutoff for vGS ≤ VP . and vGD < VP : i D = K (v GS − VP ) 2 (110) The pinch-off region (also called the saturation region) is most useful for amplification. A/V2 For very small values of vDS . the vDS2 term in the above eguation is negligible: i D = 2K (v GS − VP )v DS .

135. “Real” output characteristics also have an upward slope and can be characterized with an “Early” voltage. (110) v GS − VP = iD K (112) Combining eqs. 2N3819 n-channel JFET output characteristics showing the triode . (111) and (112) gives the boundary: v DS = iD K ⇒ i D = Kv DS 2 (113) Fig.Pinch-Off Boundary We know pinch-off just occurs at the drain end when: v GD = VP ⇒ v GS − v DS = VP ⇒ v GS − VP = v DS (111) But from eq.pinch-off boundary. The output characteristics exhibit a breakdown voltage for sufficient magnitude of vDS .The n-Channel Junction FET Introduction to Electronics 90 The Triode . VA . .

gives rise to a transfer characteristic: i D = K (v GS − VP ) 2 (114) Fig. 136. IDSS is the zero-gate-voltage drain current. However. the input i-v characteristic of a FET is trivial.The n-Channel Junction FET Introduction to Electronics 91 The Transfer Characteristic Because the gate-channel p-n junction is reversed biased always. 2N3819 n-channel JFET transfer characteristic. Substituting iD = IDSS and vGS = 0 into eq. the pinch-off region equation (110). (114) gives a relationship between K and IDSS : K= IDSS 2 VP (115) . repeated below.

. the channel is pinched-off . Negative gate voltages repel electrons from the channel. causing the channel to narrow . . The n-Channel Depletion MOSFET S G SiO 2 metal D D n channel p-type substrate (body) n G B B S Fig.Metal-Oxide-Semiconductor FETs (MOSFETs) Introduction to Electronics 92 Metal-Oxide-Semiconductor FETs (MOSFETs) MOSFETs are constructed quite differently than JFETs. The depletion MOSFET is built horizontally on a p-type substrate: G G G n-type wells. but their electrical behavior is extremely similar . . . are connected by a very thin n-type channel . . The n-channel depletion MOSFET representative physical structure (left) and schematic symbol (right). G Positive gate voltages attract electrons from the substrate. When vGS is sufficiently negative (vGS = VP ). . . . . . 137. The gate is a metallized layer insulated from the channel by a thin oxide layer . . . causing the channel to widen . used for the source and drain. .

are not connected by a channel at all . . .e. . an n-type channel is formed (i.. . When vGS is sufficiently positive. a channel is enhanced) . G G G n-type wells.e. Positive gate voltages attract electrons from the substrate . The gate is a metallized layer insulated from the channel by a thin oxide layer . greater than the threshold voltage. . .. i. . VTH . The MOSFET is built horizontally on a p-type substrate. used for the source and drain. The n-channel enhancement MOSFET physical structure (left) and schematic symbol (right). VTH functions exactly like a “positive-valued VP “ . 138. . .Metal-Oxide-Semiconductor FETs (MOSFETs) Introduction to Electronics 93 The n-Channel Enhancement MOSFET S G SiO 2 metal D D n p-type substrate (body) n G B B S Fig. .

Only the notation changes in the equation: i D = K (v GS − VTH ) 2 (118) . . p-n junction must remain reversed biased . IDSS vGS VP Actual device can operate with vGS slightly positive. Transfer char. 141. nchannel depletion MOSFET. IDSS vGS VP i D = K (v GS − VP ) 2 (117) Fig. .. . . . . 139. vGS VTH Fig. approx. Transfer char. . i D = K (v GS − VP ) G 2 (116) iD The n-channel depletion MOSFET can have either negative or positive gate voltages .. . Fig. nchannel enhancement MOSFET. n-channel JFET. Gate current prevented by oxide insulating layer . Transfer char.Comparison of n-Channel FETs Introduction to Electronics 94 Comparison of n-Channel FETs iD G The n-channel JFET can only have negative gate voltages . .5 V max. Gate current prevented by oxide insulating layer in either case. 140. . 0. iD G The n-channel enhancement MOSFET can have only positive gate voltages ..

Comparison of n-Channel FETs

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n-channel FET output characteristics differ only in vGS values:

Fig. 142. Typical output characteristics, n-channel JFET.

Fig. 143. Typical output characteristics, n-channel depletion MOSFET.

Fig. 144. Typical output characteristics, n-channel enhancement MOSFET.

p-Channel JFETs and MOSFETs

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p-Channel JFETs and MOSFETs
By switching n-type semiconductor for p-type, and vice versa, we create p-channel FETs . . . The physical principles of operation are directly analogous . . . Actual current directions and voltage polarities are reversed from the corresponding n-channel devices . . . Schematic symbols simply have the arrows reversed (because arrow indicates direction of forward current in the corresponding p-n junction):
D iD iG = 0 G + vDS +v GS iD S iG = 0 G +v GS S B G D iD iG = 0 +v GS S B D iD

Fig. 145.Schematic symbols for p-channel FETs. From left to right: JFET, depletion MOSFET, enhancement MOSFET.

Note the same reference directions and polarities for p-channel devices as we used for n-channel devices . . . i-v curves for p-channel FETs are identical to n-channel curves, except algebraic signs are reversed.

p-Channel JFETs and MOSFETs

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For comparing transfer characteristics on p-channel and n-channel devices, the following approach is helpful:

n-ch. JFET n-ch. depl. MOSFET

VP p-ch. enh. MOSFET VTH

VTH

n-ch. enh. MOSFET VP

p-ch. JFET p-ch. depl. MOSFET

Fig. 146. Comparison of p-channel and n-channel transfer characteristics.

But more often you’ll see negative signs used to labels axes, or values along the axes, such as these examples:

Fig. 147. Typical p-channel transfer characteristic.

Fig. 148. Typical p-channel transfer characteristic.

p-Channel JFETs and MOSFETs

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Output characteristics for p-channel devices are handled in much the same way:

Fig. 149. Typical p-channel output characteristic.

Fig. 150. Typical p-channel output characteristic.

Equations governing p-channel operation are exactly the same as those for n-channel operation. Replacing VP with VTH as necessary, they are: Cutoff Region: (in cutoff for vGS ≥ VP , and for any vDS )
iD = 0
(119)

Triode Region: (for vGS < VP , and vGD < VP ) i D = K 2(v GS − VP )v DS − v DS 2

[

]

(120)

where K is negative, and has units of -A/V2 Pinch-Off Region: (for vGS < VP , and vGD > VP ) i D = K (v GS − VP )
2

(121)

Other FET Considerations

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Other FET Considerations
FET Gate Protection
The gate-to-channel impedance (especially in MOSFETs) can exceed 1 GΩ !!! To protect the thin gate oxide layer, zeners are often used:

D

Zeners can be used externally, but are usually incorporated right inside the FET case.

G

B

Many FET device types available with or without zener protection. Zener protection adds capacitance, which reduces FET performance at high frequencies.

S
Fig. 151. Zener-diode gate protection of a MOSFET.

The Body Terminal

D

In some (rare) applications the body terminal of MOSFETs is used to influence the drain current. Usually the body is connected to the source terminal or a more negative voltage (to prevent inadvertently forward-biasing the channel-body parasitic diode).

G

S
Fig. 152. Normal MOSFET bodysource connection.

the load line has constant slope (-1/RB ). Load-Line Analysis . . and moves with time.Basic BJT Amplifier Structure Introduction to Electronics 100 Basic BJT Amplifier Structure Circuit Diagram and Equations The basic BJT amplifier takes the form shown: iC RB + vin + VBB iB + vBE + vCE + VCC RC KVL equation around B-E loop: VBB + v in = i BRB + v BE KVL equation around C-E loop: VCC = iC RC + v CE (122) (123) Fig. 153. but the Thevenin.Input Side Remember that the base-emitter is a diode. Basic BJT amplifier structure. Thus. The Thevenin resistance is constant. Load-line analysis around base-emitter loop. iB VBB /RB iB max IBQ iB min vBE VBB +vin max Q VBB -vin max VBB Fig. 154. voltage varies with time.

The Q-point is given special notation: IBQ . The base-emitter voltage varies also. from vBE max to vBE min . is called the quiescent pt. though we are less interested in vBE at the moment. Thus. only dc remains in the circuit. . 154 repeated). 155. base current varies from iB max to iB min . as vin varies through its cycle. Load-line analysis around base-emitter loop (Fig. VBEQ G G G Maximum excursion of load line with vin is shown in blue. This iB .Basic BJT Amplifier Structure Introduction to Electronics 101 iB VBB /R B iB max IBQ iB min Q vBE VBB -vin max VBB VBB +vin max Fig. G The load line shown in red for vin = 0. When vin = 0. vBE operating pt. Minimum excursion of load line with vin is shown in green.

Amplifier load line on BJT output characteristics. this load line is fixed!!! Fig. 157. Fig. .Output Side Returning to the circuit. 153 repeated). 156. Basic BJT amplifier structure (Fig. VCC RC iC RB + vin + VBB iB + vBE + vCE + - Thus we can plot this load line on the transistor output characteristics!!! Because neither VCC nor RC are time-varying. with output variables iC and vCE . observe that VCC and RC form a Thevenin equivalent.Basic BJT Amplifier Structure Introduction to Electronics 102 Load-Line Analysis .

. vCE max G If the total change in vCE is greater than total change in vin . when vin = 0. G The collector-emitter operating point is given by the intersection of the load line and the appropriate base current curve . is iC max . vCE min at vin min . and the operating pt. is iC min . iB = iB min . 158. 157 repeated). VCEQ at vin max . . iB = iB max . Amplifier load line on BJT output characteristics (Fig. we have an amplifier !!! . iB = IBQ .Basic BJT Amplifier Structure Introduction to Electronics 103 Fig. and the quiescent pt. and the operating pt. is ICQ .

PSpice-simulated 2N2222 input characteristic.Basic BJT Amplifier Structure Introduction to Electronics 104 A Numerical Example Let’s look at a PSpice simulation of realistic circuit: RC = 1 kΩ iC RB = 10 kΩ + + vBE iB + + vCE Q1 2N2222 + VCC = 10 V vin = 0. Example circuit illustrating basic amplifier structure. First we generate the input characteristic and draw the appropriate base-emitter circuit load lines: Fig. 159. 160.1 sin ωt V VBB = 1 V Fig. .

and 49 µA. 13 µA. 2N2222 output characteristics. 22 µA. we determine: iB min = 22 µA IBQ = 31 µA iB max = 40 µA Next we generate the output characteristics and superimpose the collector-emitter circuit load line: Fig. with curves for base currents of (from bottom to top) 4 µA. The resulting collector-emitter voltages are: vCE min = 2. 40 µA.8 ∆v in 0.11 V Finally. 161. using peak-to-peak values we have a voltage gain of: Av = ∆v CE 2.6.2 V !!! (124) .95 V VCEQ = 4.50 V vCE max = 6. 31 µA.11V = = −15.95 V .Basic BJT Amplifier Structure Introduction to Electronics 105 Using the cursor tool in the PSpice software plotting package.

163. if we desire): Fig. Input waveform for the circuit of Fig. 162. Output (collector) waveform for the circuit of Fig. 159. .Basic BJT Amplifier Structure Introduction to Electronics 106 Of course. PSpice can give us the waveforms directly (and can even give us gain. 159. Fig.

J1 2N3819 + VDD = 15 V vin = 0. the FET has no input characteristic.e. but we can plot the transfer characteristic. Let’s go right to a PSpice simulation example using a 2N3819 nchannel JFET: RD = 1 kΩ iD + + VBB = -1 V + vDS + vGS . KVL around the gate-source loop gives: VGG + v in = v GS (125) while KVL around the drain-source loop gives the familiar result: VDD = i DRD + v DS (126) Because iG = 0. is called the bias line: .. the line for vin = 0.5 sin ωt V Fig. Basic FET amplifier structure.Basic FET Amplifier Structure Introduction to Electronics 107 Basic FET Amplifier Structure The basic FET amplifier takes the same form as the BJT amplifier. Now. 164. i. and use eq. the load line locating the Q point. In this case. (125) to add the appropriate load lines.

= −15 V ⇒ iD min = 3. 165. From the transfer characteristic. that we could have gone directly to the output characteristics.Basic FET Amplifier Structure Introduction to Electronics 108 Fig.22 mA (128) max max (129) Note.5 V ⇒ IDQ = 5.30 mA ⇒ iD = 8. the indicated gate-source voltages correspond to the following drain current values: v GS min . however. and lines for vGS min and vGS max . PSpice-generated 2N3819 transfer characteristic showing the bias line. VGSQ = −10 V v GS = −0.00 mA (127) . as the parameter for the family of output curves is vGS : .

and 0 V.0 V = = −5. -1 V.0 V (130) . -1.78 V . -2 V.5 V. = −15 V ⇒ v DS max = 12.Basic FET Amplifier Structure Introduction to Electronics 109 Fig.5 V. with curves for gate-source voltages of (from bottom to top) -3 V. -0.78 V (131) max min (132) Thus. the indicated gate-source voltages correspond to the following drain-source voltage values: v GS min . 166. 2N3819 output characteristics.12. From the output characteristics and the drain-source load line. using peak-to-peak values.5 V ⇒ VDSQ = 9. we have a voltage gain of: Av = ∆v DS 6.22 ∆v GS 1V !!! (133) .5 V. VGSQ = −10 V v GS = −0. -2.70 V ⇒ v DS = 6.

70 V = 2.Amplifier Distortion Introduction to Electronics 110 Amplifier Distortion Let’s look at the output waveform (vDS ) of the previous example: Fig. . Output (drain) waveform for the FET amplifier example. Can you discern that the output sinusoid is distorted ? The positive half-cycle has an amplitude of 12. . BJT’s are also nonlinear. . . though less prominently so .9. 167. the effects of which also can be seen in the nonuniform spacing of the family of output characteristics .70 V .6.30 V while the negative half cycle has an amplitude of 9. .92 V This distortion results from the nonlinear (2nd-order) transfer characteristic.0 V .78 V = 2.

Fig. 169. .3 kΩ iD + + VBB = -1. 168.Amplifier Distortion Introduction to Electronics 111 Distortion also results if the instantaneous operating point along the output-side load line ventures too close to the saturation or cutoff regions for the BJT (the triode or cutoff regions for the FET). as the following example illustrates: RD = 1.5 sin ωt V Fig.J1 2N3819 + VDD = 15 V vin = 1. Severely distorted output waveform resulting from operation in the cutoff region (top) and the triode region (bottom). Slight changes to the FET amplifier example to illustrate nonlinear distortion.5 V + vDS + vGS .

the Q point. Linearity is best when operating point stays within the active (BJTs) or pinch-off (FETs) regions. The process of establishing an appropriate bias point is called biasing the transistor. We study BJT and FET bias circuits in the following pages . . . this is called bias stability. with aging. This dc operating point is required if linear amplification is to be achieved !!! G G G The dc operating point (the quiescent point. Bias stability can also mean stability with temperature. It lies near the “middle” of the range of instantaneous operating points. Given a specific type of transistor. . G The quiescent point is the dc (zero signal) operating point.Biasing and Bias Stability Introduction to Electronics 112 Biasing and Bias Stability Notice from the previous load line examples: G The instantaneous operating point moves with instantaneous signal voltage. the bias point) obviously requires that dc sources be in the circuit. etc. . biasing should result in the same or nearly the same bias point in every transistor of that type . .

RB 200 kΩ ⇒ VCE = VCC − IC RC = 7. Active region? A. 170. Active region??? For β = 300: A. Example We let VCC = 15 V.The Fixed Bias Circuit VCC RB RC iC + vCE Fig.0. and RC = 1 kΩ β varies from 100 to 300 To perform the analysis.Biasing BJTs . we assume that operation is in the active region. VCE < 0. BJT fixed bias circuit. and that VBE = 0.The Fixed Bias Circuit Introduction to Electronics 113 Biasing BJTs .7 V = = 715 µA . IC = βIB = 215 mA (137) Q.85 V (134) IC = βIB = 7. VCE > 0.7 V ⇒ No!!! Saturation!!! Thus our calculations for β = 300 are incorrect. but more importantly we conclude that fixed bias provides extremely poor bias stability!!! .7 V and IB > 0 ⇒ Yes!!! IB = VCC − VBE 15 V .0.15 mA (135) Q. Ω RB 200 k ⇒ VCE = VCC − IC RC = −6.7 V.45 V (136) .7 V = = 715 µA . For β = 100: IB = VCC − VBE 15 V . RB = 200 kΩ.

so it is not as useful as it may first appear. BJT constant base bias circuit. the active-region assumption must always be verified. as before.41 V (141) Thus we conclude that constant base bias provides excellent bias stability!!! Unfortunately. 171. Though not explicitly shown here. RE ⇒ IC = β IE = 214 mA . .The Constant Base Bias Circuit V CC RC iC + v CE RE Example Now we let VCC = 15 V and VBB = 5 V RC = 2 kΩ and RE = 2 kΩ β varies from 100 to 300 And we assume operation in active region and VBE = 0. we can’t easily couple a signal into this circuit.44 V (139) For β = 300: IE = VBB − VBE = 215 mA . For β = 100: IE = VBB − VBE = 215 mA . RE ⇒ IC = β IE = 213 mA . V BB + - Fig. β +1 (140) VCE = VCC − IC RC − IE RE = 6.The Constant Base Bias Circuit Introduction to Electronics 114 Biasing BJTs .7 V.Biasing BJTs . β +1 (138) VCE = VCC − IC RC − IE RE = 6.

RC RB VBB + RE + VCC Fig. Final equivalent after using Thevenin’s Theorem on base divider. but it takes a circuit-analysis “trick” to see that: VCC R1 RC + VCC R2 RE R1 RC + VCC R2 RE Fig. 173. The four-resistor bias circuit.Biasing BJTs . Fig. . 174.The Four-Resistor Bias Circuit Introduction This combines features of fixed bias and constant base bias. 172. Equivalent after “trick” with supply voltage.The Four-Resistor Bias Circuit Introduction to Electronics 115 Biasing BJTs .

The Four-Resistor Bias Circuit Introduction to Electronics 116 Circuit Analysis RC RB VBB + RE + VCC Fig. 175. Four-resistor bias circuit equivalent (Fig. Analysis begins with KVL around b-e loop: VBB = IBRB + VBE + IE RE (142) But in the active region IE = (β + 1)IB : VBB = IBRB + VBE + (β + 1)IBRE (143) Now we solve for IB : IB = VBB − VBE RB + (β + 1)RE (144) And multiply both sides by β : βIB = IC = β (VBB − VBE ) RB + (β +1)RE (145) We complete the analysis with KVL around c-e loop: VCE = VCC − IC RC − IE RE (146) .Biasing BJTs . 174 repeated).

Rule of Thumb: 1 let VRC ≈ VCE ≈ VRE ≈ VCC 3 Because VR ≈ VBB if VBE and IB are small. E . Rule of Thumb: Equivalent Rule: let (β + 1)RE ≈ 10 RB let IR ≈ 10IB 2 max    β = 100   G We also minimize variations in IC with changes in VBE . . By letting VBB >> VBE . Because then β and (β + 1) nearly cancel in eq. By letting (β + 1)RE >> RB .Biasing BJTs . . (147). .The Four-Resistor Bias Circuit Introduction to Electronics 117 Bias Stability Bias stability can be illustrated with eq. repeated below: βIB = IC = β (VBB − VBE ) RB + (β +1)RE (147) Notice that if RE = 0 we have fixed bias. . while if RB = 0 we have constant base bias. To maximize bias stability: G We minimize variations in IC with changes in β . (145).

Equivalent circuit. α ⇒ IC = βIB = 412 mA . .72 V (149) For β = 300: IB = VBB − VBE = 141 µA . 177.The Four-Resistor Bias Circuit Introduction to Electronics 118 Example 15 V R1 10 kΩ RC 1 kΩ RC R B = 3. Example circuit.50 V (151) Thus we have achieved a reasonable degree of bias stability.7 V): IB = VBB − VBE = 412 µA . For β = 100 (and VBE = 0. RB + (β + 1)RE IC = 4. 176.25 mA α ⇒ IC = βIB = 4.Biasing BJTs . Fig. (148) ⇒ IE = ⇒ VCE = VCC − IC RC − IE RE = 6.24 mA (150) ⇒ IE = ⇒ VCE = VCC − IC RC − IE RE = 6.3 kΩ + 1 kΩ 15 V 1 kΩ + - R2 5 kΩ RE 1 kΩ 5 V - RE Fig. RB + (β + 1)RE IC = 416 mA .

The Fixed Bias Circuit Introduction to Electronics 119 Biasing FETs . Fixed bias is not practical!!! . i. IDQ vGS Finally. depl.iD High-current device For an n-channel JFET. Graphical illustration of fixed bias using an n-channel JFET. Thus. VGG can be either positive or negative. We look first at the fixed bias circuit shown at left.Biasing FETs . which requires a second power supply. bias circuits must provide bias stability. so do the FET parameters K and VP (or VTH). and note that VGG = vGSQ .The Fixed Bias Circuit VDD RD + vGS iD + vDS Just as the BJT parameters b and VBE vary from device to device.e. For an n-ch. RG VGG + - Fig. FET fixed bias circuit. 178. . MOSFET. VGG must be > 0 IDQ Low-current device VGSQ Fig. note the complete lack of bias stability.. note that VGG must be < 0. MOSFET. a reasonably constant IDQ . 179. enh. For an n-ch.

the higher current solution is invalid (why?). An analytical solution requires the quadratic formula (though a good guess often works) . A graphical solution is shown. FET self-bias circuit. iD High-current device Note the improvement in bias stability over a fixed bias approach. 181. 180.Biasing FETs .The Self Bias Circuit VDD RD + vGS RG iD vDS + R S iD + From a KVL equation around the gate-source loop we obtain the bias line: (152) v GS = −i DRS And. assuming operation in the pinch-off region: i D = K (v GS − VP ) 2 - RS (153) Fig. Graphical solution to self-bias circuit. below left. Note also that VGSQ can only be negative. Solving simultaneously provides the Q point. . self-bias is not suitable for enhancement MOSFETs! IDQ IDQ vGS Bias line vGS = -RS iD Low-current device Fig.The Self Bias Circuit Introduction to Electronics 120 Biasing FETs . Thus. showing improved stability.

as usual. A KVL equation around gate-source loop provides the bias line: v GS = VG − i DRS (154) And. 182. 183. Fig. Equivalent circuit after using Thevenin’s Theorem on gate divider.see next page. . assuming operation in the pinch-off region: i D = K (v GS − VP ) 2 (155) Simultaneous solution provides Q-point .The Fixed + Self Bias Circuit Introduction to Electronics 121 Biasing FETs .The Fixed + Self Bias Circuit This is just the four-resistor bias circuit with a different name!!! V DD R1 RD V DD RD RG + RS iD + v DS - R2 RS VG Fig. Fixed + self-bias circuit for FETs.Biasing FETs .

g.The Fixed + Self Bias Circuit Introduction to Electronics 122 iD High-current device Bias line vGS = VG . VG G Note that bias stability can be much improved over that obtained with self-bias. R1 and R2 can be very large (e. Because VG can be > 0.Biasing FETs . Graphical solution to fixed + self bias circuit. . 184. Rule of thumb: 1 let VRD = VDS = VRS = VDD 3 G Other considerations: Because IG = 0.RS iD Low-current device IDQ IDQ vGS Intercept at V G / RS Fig.. The degree of stability increases as VG or RS increases. this circuit can be used with any FET. including enhancement MOSFETs. MΩ).

185. Output Impedance: We can decrease Zout with low R values.Design of Discrete BJT Bias Circuits Introduction to Electronics 123 Design of Discrete BJT Bias Circuits In the next few sections we shall look at biasing circuits in somewhat greater detail. . Concepts of Biasing We want bias stability because we generally desire to keep the Qpoint within some region: iC VCC RC + RE PMAX = iC vCE Q-point area VCC vCE Fig. Power Dissipation: VCEQ and ICQ must be below certain limits. In addition to voltage gain. we must consider and compromise among the following: G G G G G G Signal Swing: If VCEQ is too small the device will saturate. Frequency Response: A higher VCEQ lowers junction C and improves response. A specific ICQ maximizes ft . If ICQ is too small the device will cut off. Input Impedance: We can increase Zin with high R values. Bias Stability: We can increase stability with low R values. Typical BJT output characteristics.

VE . Assume that ICQ . β (VBB − VBEQ ) = RB + (β + 1)RE (156) Design Procedure G First. 186. VBEQ . Four-resistor bias circuit. VCC . Recall the rule of thumb: I2 = 10 IBQ max . Now. recall this result from a KVL equation around the base-emitter loop: ICQ Fig. Recall the “one-third” rule of thumb. Then: R2 = VE + VBEQ I2 and R1 = VCC − (VE + VBEQ ) I2 + IBQ (158) . revisited. This amounts to little more than having chosen the device and the Q-point. Then: C RC = G VR C ICQ and RE = VE VE ≈ IEQ ICQ (157) Then we choose I2 (larger I2 ⇒ lower RB ⇒ better bias stability ⇒ lower Zin). VCE .Design of Discrete BJT Bias Circuits Introduction to Electronics 124 Design of the Four-Resistor BJT Bias Circuit i1 R1 iB + R2 i2 vB iE + vE R E VCC RC iC We begin where we are most familiar. we decide how VCC divides among VR . βmin and βmax are known. by revisiting the four-resistor bias circuit. For temperature stability we want VE >> temperature variation in VBE .

ICQ = Design Procedure G β (VEE − VBEQ ) RB + (β + 1)RE (159) Allocate a fraction of VEE for VB . Then: RB = G V. 187. i.. Here a rule of thumb is: VCEQ ≈ VCC /2.e. RB << βRE). A starting point. Because its important that you understand the principles used to obtain these equations.B βVB = IBQ ICQ and RE ≈ VEE − VB − VBEQ ICQ (160) Choose VCEQ . verify that the following results from a KVL equation around the base-emitter loop: -VEE Fig.. a rule of thumb is |VB| = VEE / 20.Design of Discrete BJT Bias Circuits Introduction to Electronics 125 Design of the Dual-Supply BJT Bias Circuit +VCC RC iC iB iE RB vB + RE This is essentially the same as the fourresistor bias circuit. Only the reference point (ground) has changed. We begin with the same assumptions as for the previous circuit. For bias stability we would like the voltage across RE to be << |VB| (i. Dual-supply bias ckt.e. Then: RC = VCC − VCEQ − −(VB + VBEQ ) ICQ [ ]=V CC − VCEQ + VB + VBEQ ICQ (161) Note: Smaller VCEQ ⇒ larger RC ⇒ larger Av ⇒ larger Zout .

To have R1 << βRC . ICQ   R β VCC − 1 (VEE + VBEQ ) R2  ≈  R1 + βRC (162) Design Procedure G Allocate VCC between VRc and VCEQ . With supply voltage split between only two elements the rule of thumb becomes: VCEQ ≈ VCC / 2 G (163) Choose I2 . Grounded-emitter bias circuit. we want I2 >> IB .Design of Discrete BJT Bias Circuits Introduction to Electronics 126 Design of the Grounded-Emitter BJT Bias Circuit +VCC RC iC Grounding the emitter directly lowers inductance in the emitter lead. The rule of thumb is: G I2 ≈ 10IBQ max Then: (164) R2 = VEE + VBEQ I2 R1 = VCEQ − VBEQ I2 + IBQ RC = VCC − VVEQ ICQ + I1 (165) . Verifying this approximate equation is difficult. a derivation is provided on the following pages: i1 R1 iB R2 i2 -VEE Fig. Bias stability is obtained by connecting base to collector through R1 . 188. which increases high-frequency gain.

Grounded-emitter bias circuit (Fig. We begin by noting that : I1 = I2 + IB (167) and -VEE Fig. How do we obtain this equation? i1 R1 iB R2 i2 ICQ   R β VCC − 1 (VEE + VBEQ ) R2  ≈  R1 + βRC (166) A. 189. 188 repeated).Design of Discrete BJT Bias Circuits Introduction to Electronics 127 Analysis of the Grounded-Emitter BJT Bias Circuit +VCC RC iC Q. IRC = I1 + IC = I2 + (β + 1)IB (168) Then we find I2 with a KVL equation around the base-emitter loop: I2 = VEE + VBEQ R2 (169) Now we sum voltage rises from ground to VCC : VCC = VBEQ + (I2 + IB )R1 + I2 + (β + 1)IB RC Substituting (169) into (170): [ ] (170) VCC = VBEQ + R1 (VEE + VBEQ ) + IBR1 + RC (VEE + VBEQ ) + (β + 1)IBRC R2 R2 (171) .

VBEQ ≈ VCC RC /R2 ≈ 0 β + 1≈ β we obtain our objective. if we apply the following approximations: VCC .Design of Discrete BJT Bias Circuits Introduction to Electronics 128 Repeating eq. the original approximation: ICQ   R β VCC − 1 (VEE + VBEQ ) R2  =  R1 + βRC (174) . (171) from the bottom of the previous page: VCC = VBEQ + R1 (VEE + VBEQ ) + IBR1 + RC (VEE + VBEQ ) + (β + 1)IBRC R2 R2 (172) The next step is to collect terms: VCC − VBEQ − R1 (VEE + VBEQ ) − RC (VEE + VBEQ ) = IB R1 + (β + 1)RC R2 R2 [ ] (173) Finally.

And resistances greater than 100 kΩ are extremely rare. When used. use of resistances in ICs is avoided. BJTs are very efficient. Anything that takes up too much space is a liability. it is quite difficult to control resistance values with accuracy unless each resistor is laser-trimmed. Space on an IC wafer is at a premium. Capacitance values greater than 100 pF are virtually unheard of. G G G Capacitors are also liabilities. all resistors are “off” by the same amount. if possible. Tolerances are as large as 50% are not unusual. For our purposes here. This means that resistors that are intended to be equal will essentially be equal.Bipolar IC Bias Circuits Introduction to Electronics 129 Bipolar IC Bias Circuits Introduction Integrated circuits present special problems that must be considered before circuit designs are undertaken. the most important consideration is real estate. We begin to examine this on the following pages. This latter point is most important. . Their use is quite limited. and drives all IC circuit design. Inductors only recently became integrable. all BJTs on an IC wafer are essentially identical (if intended to be). Consider the following: G Resistors are very inefficient when it comes to real estate. Because all resistors are fabricated at the same time. And while β values suffer the same 3:1 to 5:1 variation found in discrete transistors. The area required is directly proportional to the value of resistance (remember R = ρL / A ?). As a result.

IO = IC 2 = IC1 = IC = βIB And from a KCL equation at the collector of Q1 : IREF = IC1 + IB1 + IB 2 = βIB + 2IB = (β + 2)IB Dividing (175) by (176): (176) IO IREF = β IB β 1 = = (β + 2)IB β + 2 1 + 2 β (177) Thus.Bipolar IC Bias Circuits Introduction to Electronics 130 The Diode-Biased Current Mirror Current Ratio: VCC IREF VCC Load This is the most simple of all IC bias circuit techniques. . Note that VCB1 = 0. From this point the analysis proceeds straightforwardly . we have IC1 = IC2 = IC . . i. as long as Q2 remains active. for large β.. The key here is that the BJTs are identical !!! Because VBE1 = VBE2 . RREF IC1 Q1 IB1 IB2 IO = IC2 Q2 If we assume Q2 is also active. IO reflects the current IREF (hence “mirror”). regardless of the load!!! . (175) Fig. thus Q1 is active (at the edge of saturation).e. this means that IB1 = IB2 = IB . Diode-biased current mirror. IO ≈ IREF . 190.

190 repeated. 191. the output resistance seen by the load is just the output resistance of Q2 : Fig.Bipolar IC Bias Circuits Introduction to Electronics 131 VCC IREF VCC Load Reference Current: IREF is set easily.7 V ≈ RREF RREF (178) Q2 Output Resistance: Finally. by choosing RREF : RREF IC1 Q1 IB1 IB2 IO = IC2 IREF = VCC − VBE VCC − 0.  ∂i  ro =  C 2  ∂v CE 2  −1 (179) . Diode-biased current mirror (Fig.

Using a Mirror to Bias an Amplifier VCC Amplifier VCC IDC Current Mirror -VEE Fig. 194. . this is the range where Q2 remains active. 193. Fig. VCE2 0. The schematic technique used to show integer ratios other than unity is shown. -VEE Fig. Fig.Bipolar IC Bias Circuits Introduction to Electronics 132 IC2 ro = 1/slope Compliance Range This is defined as the range of voltages over which the mirror circuit functions as intended. The diode-biased mirror is represented in this figure. Follower biased with a current nirror. 192.5 V BV Compliance Range For the diode-biased mirror. Changing transistor areas gives mirror ratios other than unity. Representation of the mirror circuit of Fig. 194. 195. Example of the compliance range of a current mirror. which is useful to obtain small currents without using large R values.

196. Wilson current mirror. IE 2 = IC 3 + 2IB = (β + 2)IB (180) IO = IC 2 = β (β + 2) β IE 2 = IB β +1 β +1 (181) IB 2 = β +2 1 IE 2 = IB β +1 β +1 β +2 IB β +1 (182) IREF = IC1 + IB 2 = βIB + (183) .Bipolar IC Bias Circuits Introduction to Electronics 133 Wilson Current Mirror V CC IREF R REF V CC Load IO = IC2 Current Ratio: The addition of another transistor creates a mirror with an output resistance of ≈ βro2 (very large!!!) Because VBE1 = VBE3 we know that IB1 = IB3 = IB . Thus we know that IC1 = IC3 = βIB . Q2 Q1 Q3 Fig. Q1 is active. Because VCB3 = 0. Because VCB1 = VBE2 . We proceed with the mathematical derivation without further comment. We assume also that Q2 is active. Q3 is active.

However. Reference Current: The reference current can be found by summing voltages rises from ground to VCC : IREF = VCC − VBE 2 − VBE 3 VCC − 14 V .Bipolar IC Bias Circuits Introduction to Electronics 134 IO IREF β (β + 2) β (β + 2) IB β (β + 2) β +1 β +1 = = = β +2 β (β + 1) β + 2 β (β + 1) + (β + 2) β IB + IB + β +1 β +1 β +1 (184) IO IREF β 2 + 2β 1 1 = 2 ≈ ≈1 = 2 2 β + 2β + 2 1 + 1+ 2 2 β + 2β β (185) Thus the Wilson mirror ratio is much closer to unity than the ratio of the simple diode-biased mirror. ≈ RREF RREF (186) Output Resistance: The output resistance of the Wilson can be shown to be βro2 . . the derivation of the output resistance is a sizable endeavor and will not be undertaken here.

IO = IC2 Current Relationship: Recall the Shockley transistor equations for forward bias: v  iC = IS exp BE   VT  Thus we may write: i  and v BE = VT ln C   IS  i  and VBE 2 = VT ln C 2   IS  (187) i  VBE 1 = VT ln C1   IS  (188) Note that VT and IS are the same for both transistors because they are identical (and assumed to be at the same temperature). The circuit’s namesake is Bob Widlar (wide’ lar) of Fairchild Semiconductor and National Semiconductor. The analysis is somewhat different than our previous two examples. . the total resistance required by this circuit is reduced substantially. 197. If very small currents are required. Widlar mirror. The Widlar mirror solves that problem Though it uses two resistors.Bipolar IC Bias Circuits Introduction to Electronics 135 Widlar Current Mirror VCC VCC Load R1 IC1 Q1 V+ BE1 V+ BE2 Q2 R2 Fig. the resistances in the previous mirror circuits become prohibitively large.

. . Widlar mirror (Fig. This is a transcendental equation.Bipolar IC Bias Circuits Introduction to Electronics 136 VCC VCC Load Continuing with the derivation from the previous page . 197 repeated). It must be solved iteratively. 198. or with a spreadsheet. etc. From a KVL equation around the baseemitter loop: R1 IC1 Q1 V+ BE1 IO = IC2 Q2 V+ BE2 R2 VBE 1 = VBE 2 + R2IE 2 ≈ VBE 2 + R2IC 2 (189) Rearranging: VBE 1 − VBE 2 = ∆VBE ≈ R2IC 2 (190) Fig. The form of the equation to use depends on whether we’re interested in analysis or design: Analysis: where: VT  IC1  ln  = IC 2 R2  IC 2  Design: R2 = VT  IC1  ln  IC 2  IC 2  (192) IC1 ≈ IREF = VCC − VBE 1 R1 (193) . Substituting the base-emitter voltages from eq. (188) into eq. (190): I  I  VT ln C1  − VT ln C 2  ≈ R2IC 2  IS   IS  I  ⇒ VT ln C1  ≈ R2IC 2  IC 2  (191) Where the last step results from a law of logarithms.

so that the total resistance on the chip may be minimized. . 199. FET Current Mirrors The same techniques are used in CMOS ICs (except. the devices are MOSFETs). of course. as well as mirrors constructed with pnp devices: VCC Load 1 Load 2 -VEE IREF VCC Load 3 -VEE VCC Load 4 -VEE Fig. though. Multiple current mirrors.Bipolar IC Bias Circuits Introduction to Electronics 137 Multiple Current Mirrors In typical integrated circuits multiple current mirrors are used to provide various bias currents. Usually. The figure below illustrates the technique of multiple current mirrors. there is only one reference current. The details of these circuits are not discussed here.

such as a piecewise-linear model. . which must consider the nonlinear device characteristics to determine the operating point. so we assume it is linear. . the resulting dc and ac values may be recombined. G After analysis. Alternatively. . i. we can substitute an accurate model. if necessary or desired.Linear Small-Signal Equivalent Circuits Introduction to Electronics 138 Linear Small-Signal Equivalent Circuits G In most amplifiers (and many other circuits): We use dc to bias a nonlinear device . but because injected signal is small. At an operating point (Q-point) where the nonlinear device characteristic is relatively straight. for the nonlinear device. AC analysis.e.. . This small region is almost linear. G The circuit analysis is split into two parts: DC analysis. And then inject the signal to be amplified (the small signal) into the circuit. only a small region of the nonlinear device characteristic need be considered. almost linear . and construct a linear small-signal equivalent circuit. .

The instantaneous operating point moves slightly above and below the Q-point.Diode Small-Signal Equivalent Circuit Introduction to Electronics 139 Diode Small-Signal Equivalent Circuit vs VDC + iD + vD IDQ iD Q vD Fig. Diode characteristic. or with a diode model such as the ideal.) to the changes in diode voltage: ∆i D = K ∆v D (194) . we allow vs to be nonzero. The Concept First. VDQ Fig. we allow vs to be zero. and has a specific Q-point shown. If signal is small enough. We can find the Q-point analytically with the Shockley equation. Now. we can approximate the diode curve with a straight line. but small. 201. The circuit is now dc only. or piecewise-linear model. constant-voltage-drop. 200. The Equations This straight-line approximation allows us to write a linear equation relating the changes in diode current (around the Q-pt. Generalized diode circuit.

Diode Small-Signal Equivalent Circuit Introduction to Electronics 140 Repeating the linear equation from the previous page: ∆i D = K ∆v D (195) The coefficient K is the slope of the straight-line approximation. ∆iD becomes id . (195) with changes in notation. id and vd are the signal current and the signal voltage. The best choice (in a least-squared error sense) is a line tangent at pt. Diode curve with tangent at Q-point. respectively. K becomes 1/rd . Q !!! iD IDQ Q vD VDQ Fig. We rewrite eq. 202. We can choose any straight line we want. and ∆vD becomes vd : id = This is merely Ohm’s Law!!! 1 vd rd (196) rd is the dynamic resistance or small-signal resistance of the diode. . and must have units of Ω-1 .

4. where 1/rd is the slope of a line tangent at pt. notice from (198): V  IDQ ≈ IS exp DQ   nVT  So: (200) I ∂i D ≈ DQ ∂v D Q − po int nVT Notes: 1. The diode small-signal model is simply a resistor !!! . 2. 1 ∂i D = rd ∂v D Q − po int We use the diode forward-bias approximation: (197)  v   v  iD = IS exp D  − 1 ≈ IS exp D   nVT    nVT   Thus: (198) ∂ ∂v D   v  V  I = S exp DQ  IS exp D     nVT  Q − po int nVT  nVT   (199) But..Diode Small-Signal Equivalent Circuit Introduction to Electronics 141 Diode Small-Signal Resistance We need only to calculate the value of rd . once we know IDQ !!! IDQ can be estimated with simple diode models !!! Diode small-signal resistance rd varies with Q-point.e. i. 3. Q. ⇒ rd ≈ nVT IDQ (201) The calculation of rd is easy.

ID vd . Id This is the total instantaneous quantity. If a scalar it is an rms or effective value. (dc + ac.. Illustration of various currents. or bias + signal) This is the dc quantity. (i. iD VD . . id Vd . 203. this is a phasor quantity.e. (This is the total instantaneous quantity with the average removed) If a vector. the average value) This is the ac quantity.Notation Introduction to Electronics 142 Notation The following notation is standard: iD IDQ id iD t Fig. vD .

BJT Small-Signal Equivalent Circuit Introduction to Electronics 143 BJT Small-Signal Equivalent Circuit vs VDC + iB iC IBQ iB ib iE iB t Fig. vbe and ib will be approximately related by the slope of the BJT input characteristic. 205. This is identical to the diode small-signal development !!! Thus. BJT input characteristic. Generalized base current waveform.7 V Fig. at the Q-point. Fig. . First. Generalized BJT circuit. 206. let the signal component be small: |ib| << IBQ With the signal sufficiently small. note the total base current (bias + signal): iB = IBQ + ib This produces a total base-emitter voltage: vBE = VBEQ + vbe Now. the equations will have the same form: iB  ∂i ib =  B  ∂v BE  IBQ Q vBE  1 v be = v be rπ Q − po int   rπ ≈ VT IBQ (202) where (203) ~0. 204.

we have a simple current relationship: iC = β i B ⇒ i c = βi b (204) Combining eqs. we can turn our attention to the output (collector) side. this model applies identically to npn and to pnp devices.BJT Small-Signal Equivalent Circuit Introduction to Electronics 144 With rπ determined. . Because the bias point is “accounted for” in the calculation of rπ . If the BJT is in its active region. BJT small-signal equivalent circuit. 207. (202) through (204) we can construct the BJT small-signal equivalent circuit: B ib + vbe rπ ie E ic C β ib Fig.

RC Cout Cin Q1 + RE CE RL vo - The typical four-resistor bias circuit is shown in black. CE provides a short circuit around RE for signal currents only (dc currents cannot flow through CE . 208. .The Common-Emitter Amplifier Introduction to Electronics 145 The Common-Emitter Amplifier Introduction VCC R1 RS + vs + vin R2 Fig. Capacitors are chosen to appear as short circuits at frequencies contained in the signal (called midband frequencies). Standard common emitter amplifier circuit. so only signal currents can flow in the blue branches. and out of. . and from that we obtain the value of rπ . Cin and Cout couple the signal into. A standard dc analysis of the four-resistor bias circuit provides the Q-point.capacitors are open circuits at dc. the amplifier. .

2. Standard common emitter. Replace the BJT by its small-signal model. Replace all capacitors with short circuits. 210. . because they have zero signal component!!! The result is the small-signal equivalent circuit of the amplifier: RS + vs + vin R2 R1 rπ E B ib C β ib RC RL + vo - Fig. we: 1.The Common-Emitter Amplifier Introduction to Electronics 146 Constructing the Small-Signal Equivalent Circuit VCC R1 RS + vs + vin R2 Fig. Set all dc sources to zero. 3. 208 repeated) RC Cout Cin Q1 + RE CE RL vo - To construct small-signal equivalent circuit for entire amplifier. Small signal equivalent circuit of common emitter amplifier. 209. (Fig.

We combine equations to eliminate ib . Thus: v in = v be = i b rπ (205) v o = −βi bRL And: ′ (206) ′ ′ −βRL v o −βi bRL = = Av = v in i b rπ rπ (207) With RL removed (an open-circuit load). We write an equation on the input side to relate vin to ib . We write an equation on output side to relate vo to ib . Simplified small signal equivalent of common emitter amplifier. Voltage Gain Our usual focus is Av = vo /vin . Avo : Avo = v o −βRC = v in rπ (208) . and RC || RL = RL’: RS + vs + vin RB rπ E B ib C β ib R L’ + vo - Fig. we define the open-circuit voltage gain. or Avs = vo /vs . 2. we can design an approach: 1. Because ib is the only parameter common to both sides of the circuit. We concentrate on the former.The Common-Emitter Amplifier Introduction to Electronics 147 For convenience we let R1 || R2 = RB . 211. 3.

Input resistance of common emitter amplifier. 213. because ib = 0. We do not set dependent sources to zero!!! Thus: RS RB B ib rπ E Fig. Rin = vin /iin . Output resistance of common emitter amplifier. and set all independent sources to zero. the dependent source βib = 0 also. C βi b RC Ro Now. but only independent sources. iin B ib C β ib RL + vo - By definition. 212. we must remove the load.The Common-Emitter Amplifier Introduction to Electronics 148 Input Resistance Rin RS + vs + vin RB rπ E Fig.and: Ro = RC (210) . We can find this simply by inspection: Rin = RB || rπ (209) Output Resistance Recall that to find Ro .

215. hence the alternate name Common Collector Amplifier. vo is taken from the emitter. We have a four-resistor bias network. or common. 214. Standard emitter follower circuit. Emitter follower small-signal equivalent circuit. The collector terminal is grounded. Unlike the common-emitter amplifier. with RC = 0. B ib C βi b .The Emitter Follower (Common Collector Amplifier) Introduction to Electronics 149 The Emitter Follower (Common Collector Amplifier) Introduction VCC R1 RS + vs + vin R2 RE Cin Q1 Cout + RL vo - Fig. The small-signal equivalent is derived as before: RS + vs + vin R2 R1 || R2 = RB RE || RL = RL’ R1 rπ E (β+1)ib RE + R L vo Fig.

The Emitter Follower (Common Collector Amplifier)

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Voltage Gain
RS + vs + vin R2 R1 || R2 = RB RE || RL = RL’ R1 rπ E (β+1)ib RE + RL vo Fig. 216. Emitter follower small-signal equivalent (Fig. 215 repeated).

B ib

C

βib

Gain, Av = vo /vin , is found using the same approach described for the common-emitter amplifier. We write two equations of ib - one on the input side, one on the output side - and solve:

v in = ib rπ + (β + 1)ib RL v o = (β + 1)i bRL ′

(211)

(212)

(β + 1)RL ′ vo = Av = v in r + (β + 1)R ′ π L

(213)

Typical values for Av range from 0.8 to unity. The emitter (output) voltage follows the input voltage, hence the name emitter follower. The feature of the follower is not voltage gain, but power gain, high input resistance and low output resistance, as we see next . . .

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Input Resistance
Rin RS + vs + vin R2 R1 || R2 = RB R1 rπ E (β+1)ib RE RE || RL = RL RL + vo Rit B ib C

βib

Fig. 217. Calculating the input resistance of the emitter follower.

Note that :

Rin =

v in = RB || Rit , i in

where Rit =

v in ib

(214)

We’ve already written the equation we need to find Rit . It’s equation (211), from which: ′ (215) Rit = rπ + (β + 1)RL Thus

Rin = RB || rπ + (β + 1)RL ′

[

]

(216)

Compare this to the common emitter input resistance, which is generally much lower, at Rin = RB || rπ .

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Output Resistance

B RS R2 R1

ib rπ E (β+1)ib iy RE

C

β ib
itest + vtest R ot Ro

R 1||R 2||R S = R S’

Fig. 218. Circuit for calculating follower output resistance.

Notice that we have set the independent source to zero, and replaced RL by a test source. From the definition of output resistance:

Ro =
But

v test = RE || Rot , itest

where Rot =

v test v test = −(β + 1)ib iy

(217)

v test

= − i b RS ′ + rπ

(

)

RS ′ + rπ ∴ Rot = β +1

(218)

Compare this to the common emitter input resistance, which is much higher, at RC .

Review of Small-Signal Analysis

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Review of Small Signal Analysis
It’s presumed that a dc analysis has been completed, and rπ is known. 1. Draw the small-signal equivalent circuit. A. B. C. 2. 3. Begin with the transistor small signal model. For midband analysis, coupling and bypass capacitors replaced by short circuits. Set independent dc sources to zero.

Identify variables of interest. Write appropriate independent circuit equations. (This usually requires an equation on the “input” side and an equation on the “output” side of the small-signal equivalent circuit.)

4. 5.

Solve. Check units!!!

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FET Small-Signal Equivalent Circuit
The Small-Signal Equivalent

vs V DC +

iD

iD

iS
Q

IDSS IDQ vGS

Fig. 219. Generalized FET circuit.

VP

VGSQ

Fig. 220. FET transfer characteristic.

We restrict operation to the pinch-off region and note that the dc source and the circuit determine the Q-point. For small vs , the instantaneous operating pt. stays very near Q, and the transfer curve can be approximated with a line tangent at Q. Both vGS and iD have dc and ac components:
v GS = VGSQ + v gs
id G + vgs is S
Fig. 221. FET sm. sig. model.

and

i D = IDQ + i d

(219)

D gm vgs

VGSQ and IDQ are related by the secondorder FET characteristic, but if |vs| is small enough, vgs and id are related (almost) linearly:

i d = gmv gs
gm , is called the transconductance.

(220)

This leads immediately to the model at left.

FET transfer characteristic. (222) we have VGSQ − VP = IDQ K (224) Substituting this into eq. (222) gm = ∂ 2 K (v GS − VP ) ∂v GS [ ] Q = 2K (VGSQ − VP ) (223) But also from eq. finally.FET Small-Signal Equivalent Circuit Introduction to Electronics 155 Transconductance The coefficient gm is the slope of the tangent : iD IDSS Q IDQ vGS ∂i gm = D ∂v GS (221) Q VP VGSQ From the pinch-off region equation: i D = K (v GS − VP ) We obtain: 2 Fig. 222. because K = IDSS /VP2 we can write: (225) gm = 2 IDSS IDQ VP (226) . we see that the transconductance can also be written as: gm = 2 KIDQ Or. (223).

FET output characteristics.  ∂i D id =  ∂v GS  where   ∂i D v gs +  ∂v DS Q   = Q  v ds v ds = gmv gs + rd Q  (227) ∂i D ∂v DS 1 = slope of output char. This means that id is not dependent only on vgs . but also on vds. at Q rd (228) A single addition to the small-signal model accounts for rd : id G + v gs is S Fig. . But it is also observed in BJTs and can be included in the BJT small-signal model. FET small-signal model including FET output resistance. We can account for both dependencies by writing: Fig. 223. where the notation ro is used for output resistance. D g m v gs rd Output resistance is more noticeable in FETs than in BJTs.FET Small-Signal Equivalent Circuit Introduction to Electronics 156 FET Output Resistance Recall that FET output characteristics have upward slope. 224.

225. Small-signal equivalent circuit for the common source amplifier. 226. Capacitors are open circuits at dc. The self-bias circuit is shown in black. The small-signal equivalent is constructed in the standard manner: Rsig iin + vin G RG + vgs S D gmvgs rd RD + R L vo - vsig - + rd ||RD ||RL = RL’ Fig.The Common-Source Amplifier Introduction to Electronics 157 The Common Source Amplifier The Small-Signal Equivalent Circuit VDD RD Cout Rsig + vsig + vin RG RS CS + RL vo Cin Fig. . so only signal currents flow in the blue branches. Standard common source amplifier circuit. A standard dc analysis provides the value of gm .

we must remove RL . Output Resistance Remember. 226 repeated). For this circuit we can determine Ro by inspection: Ro = rd || RD (232) .The Common-Source Amplifier Introduction to Electronics 158 vsig - + Rsig iin + vin - G RG + vgs S D gmvgs rd RD + R L vo - rd ||RD ||RL = RL’ Fig. 227. Voltage Gain v in = v gs Thus: and v o = −gmv gs RL ′ (229) Av = vo ′ = −gmRL v in (230) Input Resistance Rin = v in = RG i in (231) Because no dc current flows through RG it can be extremely large. Common source small signal equivalent (Fig. and set all independent sources to zero.

229. Source follower circuit. Source follower small-signal equivalent circuit. 228. + RL vo - This follower uses fixed bias: IG = 0 ⇒ VGSQ = 0 ⇒ ID = IDSS Tremendously large Rin is obtained by sacrificing bias stability. . as we shall see.The Source Follower Introduction to Electronics 159 The Source Follower Small-Signal Equivalent Circuit VDD Rsig + vsig + vin Cin Cout RG RS Fig. The small-signal equivalent is constructed in the usual manner: Rsig iin + vin G RG + vgs S + RL vo gmvgs rd D vsig - + rd ||RS ||RL = RL’ RS Fig. which isn’t very important in this circuit anyway.

230. Voltage Gain This one requires a little more algebra. and solve for vo /vin :  1 ′ v o = (v in − v o ) gm +  RL RG      1  ′ 1 ′  RL v o = v in  gm + R 1 +  gm + RG  RG  L     (235) (236)  1 ′  gm +  RL RG   vo = = 0. (234) with eq. 229 repeated).5 to 0.The Source Follower Introduction to Electronics 160 vsig - + Rsig iin + vin - G RG + vgs S + RL vo gmvgs rd D rd ||RS ||RL = RL’ RS Fig. Source follower small-signal equivalent circuit (Fig. (233).8 typically Av = v in  1 ′ 1 +  gm +  RL RG   (237) . Beginning with: v in = v gs + v o ⇒ v gs = v in − v o (233) and v o = gmv gs ( ′ =  g v + v gs  R ′ = v  g + 1  R ′ + i in RL  m gs   gs  m RG  L RG  L   ) (234) We replace vgs in eq.

With the additional multiplying factor of RL’. 229 repeated). Rin can become extremely large!!! . Source follower small-signal equivalent circuit (Fig. (233) with eq. RG can be several MΩ. Input Resistance Replacing vo in eq.The Source Follower Introduction to Electronics 161 vsig - + Rsig iin + vin - G RG + vgs S + RL vo gmvgs rd D rd ||RS ||RL = RL’ RS Fig. 231. (234):  1 ′ v in = v gs + v o = v gs + v gs  gm +  RL RG   But vgs = iin RG : (238)  1 ′ v in = i inRG + i inRG  gm +  RL RG   Solving for vin /iin : (239) Rin = v in ′ = RG + (1 + gmRG )RL i in (240) Because IG = 0.

The Source Follower

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162

Rsig

G RG + vgs S gmvgs

D rd

RS

itest

+ vtest -

Fig. 232. Determining output resistance of the source follower.

Output Resistance
This calculation is a little more involved, so we shall be more formal in our approach. We remove RL , apply a test source, vtest , and set the independent source to zero. From a KCL equation at the source node:

itest =

v test v test v test + + − gmv gs RS rd RG + Rsig

(241)

But RG and Rsig form a voltage divider:

v gs = −

RG v test RG + Rsig

(242)

Substituting eq. (242) into eq. (241):

itest

 1 gmRG  1 1   = v test + + +  RS rd RG + Rsig RG + Rsig 

(243)

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163

Rsig

G RG + vgs S gmvgs

D rd

RS

itest

+ vtest -

Fig. 233. Determining output resistance of the source follower (Fig. 232 repeated).

Thus:

Ro =

v test 1 = gmRG 1 1 1 i test + + + RS rd RG + Rsig RG + Rsig

(244)

Finally, we recognize this form as that of resistances in parallel:

 R + Rsig  Ro = RS || rd || (RG + Rsig )||  G   gmRG 

(245)

Review of Bode Plots

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164

Review of Bode Plots
Introduction
The emphasis here is review. Please refer to an appropriate text if you need a more detailed treatment of this subject. Let us begin with a generalized transfer function:

 f  f   j  1 + j  fZ 2   fZ 1   Av (f ) =  f  1 + j  fP 1  
We presume the function is limited to certain features: G G G Numerator and denominator can be factored.

(246)

Numerator factors have only one of the two forms shown. Denominator factors have only the form shown.

Remember: G G Bode plots are not the actual curves, but only asymptotes to the actual curves. Bode magnitude plots are not based on the transfer function itself, but on the logarithm of the transfer function - actually, on 20 log Av . The total Bode response for Av(f) consists of the magnitude response and the phase response. Both of these consist of the sum of the responses to each numerator and denominator factor.

G

Review of Bode Plots

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165

The Bode Magnitude Response
Now, let’s review the Bode magnitude response of each term: The numerator term j
0 dB 20 dB/decade

f fZ1

:

fz1

The magnitude response increases 20 dB per decade for all f. For f = fZ1 the term has a magnitude of 1. Thus the magnitude response has an amplitude of 0 dB at fZ1 . The numerator term 1 + j

Fig. 234. Bode magnitude response for jf/fZ1 .

20 dB/decade

f fZ 2

:

0 dB fz2

For f << fZ2 the imaginary term is negligible; the magnitude is just 0 dB. For f >> fZ2 the imaginary term dominates, thus the magnitude increases 20 db per decade. The denominator term 1 + j

Fig. 235. Bode magnitude response for 1 + jf/fZ2 .

f fP 1

0 dB

:

fp -20 dB/decade

Fig. 236. Bode magnitude response for 1 + jf/fP1 .

For f << fP1 the imaginary term is negligible; the magnitude is just 0 dB. For f >> fP1 the imaginary term dominates, thus the magnitude decreases 20 db per decade (because the term is in the denominator).

Review of Bode Plots

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166

The Bode Phase Response
Now, let’s review the Bode phases response of each term:

+90O
Fig. 237. Bode phase response for jf/fZ1 .

The numerator term j

f fZ1

:

The phase response is simply 90o for all f. The numerator term 1 + j

+90O 10fz2 0O fz2 /10 45O/decade

f fZ 2

:

For f << fZ2 the imaginary term is negligible; the phase is just 0o. For f >> fZ2 the imaginary term dominates, thus the phase is 90o. At f = fZ2 , the term is 1 + j1; its phase is 45O.

Fig. 238. Bode phase response for 1 + jf/fZ2 .

0O fp /10 -45 /decade -90O 10fp
O

The denominator term 1 + j

f fP 1

:

For f << fZ2 the imaginary term is negligible; the phase is just 0o. For f >> fZ2 the imaginary term dominates, thus the phase is -90o. At f = fZ2 , the term is 1 + j1; its phase is -45O.

Fig. 239. Bode phase response for 1 + jf/fP1 .

240.” The term fb is called the halfpower frequency. Gain Magnitude in dB: From: Av = 1 f  12 +    fb  2 (249) . the break frequency. the corner frequency. For the sinusoidal steady state response we substitute j2πf for s: Av = 1 1 = 1 + j (2πRC )f 1 + j f fb where fb = 1 2πRC (248) This fits the generalized single-pole form from the previous page. The review of the details of the Bode response of a single-pole low-pass RC circuit begins with the s-domain transfer function: Av = Vo 1 = = Vin R + 1 sRC + 1 sC 1 sC (247) Note that there is a pole at s = -1/RC and zero at s = ∞ . Single-pole low-pass RC circuit. or the 3-dB frequency. except we’re using “fb” instead of “fP.Review of Bode Plots Introduction to Electronics 167 Single-Pole Low-Pass RC R + + Vin(s) 1/sC Vo(s) Fig.

The actual curve is shown in blue. . at high frequencies (f /fb >> 1): Av Av . -20 db per decade). at low frequencies (f /fb << 1): Av dB = −10 log(1) = 0 dB (251) And.. in red. (250). dB fb /10 -3 dB dB f  f  = −10 log  = −20 log   fb   fb  2 (252) fb 10fb 100fb f -20 dB Note that the latter equation decreases 20 dB for each factor of 10 increase in frequency (i.e. Bode magnitude plot for single-pole lowpass.Review of Bode Plots Introduction to Electronics 168 We obtain: Av dB f  = 20 log = 20 log(1) − 20 log 12 +   2  fb  f  2 1 +   fb  1 2   f 2 f  = −20 log 12 +   = −10 log1 +     fb    fb     2 (250) Bode Magnitude Plot: From eq. 241. -40 dB Fig.

243. . 242. deg 0O fb /10 fb 10fb 100fb f -45O -90O Fig. Trigonometric representation of transfer function phase angle. Av = 1 1+ j f fb (253) Re The transfer function phase angle is: θA = − arctan v f fb (254) The Bode phase plot shows the characteristic shape of this inverse tangent function: θ.Review of Bode Plots Introduction to Electronics 169 Bode Phase Plot: From the transfer function: Im f/fb θ 1 Fig. Bode phase plot for single-pole low-pass. The actual curve is shown in blue. shown in red.

244. we go directly to the resulting gain equation: Av dB f  f  = 20 log  − 20 log 1 +    fb   fb  2 (257) Recall from Fig. (234) that the first term is a straight line. (236). The total Bode magnitude response is merely the sum of these two responses. with +20 dB/dec slope. and a zero at s = 0. The last term is the same term from the low pass example. Single-pole high-pass RC circuit.Review of Bode Plots Introduction to Electronics 170 Single-Pole High-Pass RC 1/sC + + Vin(s) R Vo(s) Fig. The s-domain transfer function: Av = R 1 +R sC = sRC sRC + 1 (255) Note there is a pole at s = -1/RC. . For the sinusoidal steady state response we substitute j2πf for s: Av = j (2πRC )f = 1 + j (2πRC )f 1 + j f fb j f fb where fb = 1 2πRC (256) Bode Magnitude Plot: Because this is a review. which has the form of Fig. passing through 0 dB at fb .

Bode Phase Plot: The transfer function leads to the following phase equation: f fb This is just the low-pass phase plot shifted upward by 90o: θA = 90°− arctan v (258) θ. 246. in red. dB fb /10 -3 dB fb 10fb 100fb f -20 dB -40 dB Fig. . Bode phase plot for single-pole high-pass. 245. in red. Bode magnitude plot for single-pole high pass.Review of Bode Plots Introduction to Electronics 171 Adding the two individual responses gives: Av . deg 90O 45O 0O fb /10 fb 10fb f 100fb Fig. The actual curve is shown in blue. The actual curve is shown in blue.

Amplifier sm. In our midband amplifier analysis. Fig. determine the its model parameters.vo x Fig. eq. This time. eq. 248. of the amplifier section only. 247. though: (1) we can draw the sm. 249. split into sections. Representative amplifier circuit. ib RB r (2) analyze it. sig. and . Ro + vx Rin - β ib RC + A v . . drew the small-signal equivalent. we assumed the capacitors were short circuits. sig. . Model equivalent to amplifier section.Coupling Capacitors Introduction to Electronics 172 Coupling Capacitors Effect on Frequency Response VCC RB RS + vs + vin Source Amplifier Load Cin Q1 + RL vo RC Cout Fig. ckt. ckt. . and analyzed it for overall gain (or other parameters).

. the Bode magnitude plots from these high-pass circuits are simply horizontal lines at 0 dB. the amplifier (and resistive dividers) will shift this horizontal line (hopefully upward. which add to become a single horizontal line at 0 dB. . . . 247) as shown: RS + vs - Cin + vx Rin - Ro + Avo vx - Cout RL + vo - Fig. Of course. when we get to the first of the two pole frequencies. which will become 20log Av on the Bode magnitude plot.at midband . when we get to the second pole. . and are single-pole. . Note that both sides are identical topologically. mid Now let’s work our way lower in frequency. Suppose we begin somewhere above f1 and f2 . . because we probably want Av > 1). the plot drops at 40 dB/decade. our Bode magnitude plot begins to drop at 20 dB/decade. . see the illustration on the next page. 250. . .Coupling Capacitors Introduction to Electronics 173 . we already know how to find the midband gain. high-pass circuits: On the left: On the right: (259) f1 = 1 2πCin (RS + Rin ) f2 = 1 2πCout (Ro + RL ) (260) At frequencies above f1 and f2 . (3) redraw the entire circuit (Fig. . . Complete circuit redrawn with amplifier section replaced by its model.

Here f1 is assumed to be lower than f2 . 251. Analyze the circuit with the coupling capacitors replaced by short circuits to find the midband gain. Find the break frequency due to each coupling capacitor. Constructing the Bode Magnitude Plot for an Amplifier 1. Sketch the Bode magnitude plot by beginning in the midband range and moving toward lower frequencies. 3. . 2. Generalized Bode magnitude plot of an amplifier with coupling capacitors. Note that the presence of f1 moves the overall half-power frequency above f2 .Coupling Capacitors Introduction to Electronics 174 20 log Av mid 20 dB/dec f2 40 dB/dec f1 Fig.

5. RC-Coupled amplifiers: Coupling capacitors . Choose C values somewhat (approximately 1.5 times larger).more difficult design. Judicious choice can reduce overall cost of capacitors. 3. . Vales can change ±10 % with time and temperature. Choose fb for each RC circuit to meet overall -3 dB requirement.bias circuits interact . 4. Determine Thevenin resistance “seen” by each coupling capacitor. Calculate required capacitance values. but preferable.capacitors cost $ Direct-Coupled amplifiers: No capacitors . +80 %. Larger resistances mean smaller and cheaper capacitors.Design Considerations for RC-Coupled Amplifiers Introduction to Electronics 175 Design Considerations for RC-Coupled Amplifiers 1. larger than calculated Some C tolerances are as much as -20%. 2.

& Mid-Frequency Performance of CE Amplifiers Introduction to Electronics 176 Low. (Let RB = R1 || R2 . RE = REF + REB ) VCC RC Cout RS + vs + vin RB -VEE Fig.Low.& Mid-Frequency Performance of CE Amplifier Introduction We begin with two of the most common topologies of commonemitter amplifier: VCC R1 RS + vs + vin R2 REF REB RL CE Cin Q1 + vo RC Cout Fig. 252. Generic single-supply common emitter ckt. Generic dual-supply common emitter ckt. RE = REF + REB ) Cin Q1 REF REB RL CE + vo - . (Let RL’ = RL || RC . RL’ = RL || RC . 253.

We’ll leave this topic with the assumption that Ro ≈ RC . Midband Performance vo − βRL ′ −RL ′ = ≈ Av = . Ro = RC . The focus has been Av . if β >> 1 v in rπ + (β + 1)REF REF Av = s (261) vo Rin = Av vs RS + Rin (262) Rin = v in = RB || rπ + (β + 1)REF i in [ ] (263) For the equivalent circuit shown. (264) . but we can determine Ai also: vo io RC R RB R Ai = = v L = Av in = −β in i in RL RC + RL RB + R X Rin where RX = rπ + (β + 1)REF .Low. Generic small-signal equivalent of common emitter amplifier. but if we include the BJT output resistance ro in the equivalent circuit. 254. the calculation of Ro becomes much more involved.& Mid-Frequency Performance of CE Amplifiers Introduction to Electronics 177 Both common-emitter topologies have the same small-signal equivalent circuit: RS + vs + vin Rin RB r E iin B ib C io RC RL RL’ + vo REF β ib Fig.

.e. as REF increases. i. gain becomes independent of β !!! .) stability RC large for high Av and Ai RC small for low Ro .& Mid-Frequency Performance of CE Amplifiers Introduction to Electronics 178 Design Considerations G In choosing a device we should consider: Frequency performance Noise figure Power Dissipation Device choice may not be critical. RB large for high Rin and high Ai RB small for bias (Q-pt. high frequency response REF small (or zero) for maximum Av and Ai REF > 0 for larger Rin . G Design Tradeoffs: 1. improved high and low frequency response. 2.Low. Av ≈ -RL’/REF .. gain stability. reduced distortion 3. (261). low signal swing. G Gain Stability: Note from eq. .

The interaction is almost always negligible.& Mid-Frequency Performance of CE Amplifiers Introduction to Electronics 179 The Effect of the Coupling Capacitors RS + vs + vin RB rπ E REF iin Cin B ib C Cout RC io RL + vo - βib Fig.Low. we approximate the small-signal equivalent as shown. because the effects of Cin and CE interact slightly. equivalent of the CE amplifier at low frequencies. 255.Approximate sm. Cin and Cout remain so that their effect can be determined. with break frequencies of: 1 fb = (265) 2πRTheveninC Thus the effect of Cout is: fout = 1 2π (RC + RL )Cout fin = fin = 1 2πRinCin (266) And the effect of Cin is: v for Av = o v in (267) for Av = vo vs 1 2π (RS + Rin )Cin (268) Equations for fin are approximate. sig. Cin and Cout are then a part of independent single-pole high-pass circuits. . The effect of CE is ignored by replacing it with a short circuit. To determine the effect of the coupling capacitors.

and Av is at its lowest. dB CE = short ckt. sig.Low. Consider the following: At sufficiently high frequencies. f Fig. and is. there is not just a single-pole high-pass effect. Approximate common emitter sm. CE appears as a short circuit. . but Av is not zero!!! Thus. equivalent at low frequencies. the standard single-pole high-pass effect. This appears like. There must also be a zero at a frequency other than f = 0. 256. The total emitter resistance is at its highest. Thus the total emitter resistance is at its lowest.& Mid-Frequency Performance of CE Amplifiers Introduction to Electronics 180 The Effect of the Emitter Bypass Capacitor CE RS + vs + vin RB rπ E REF REB CE B ib C io + R L’ v o - β ib Fig. 257. At sufficiently low frequencies CE appears as an open circuit. Only the effect of CE is accounted for in this circuit. and Av is at its highest. as shown below: Av . Bode magnitude plot showing the effect of CE only. f1 f2 CE = open ckt.

From inspection we should see that: RThevenin = REB || R X = REB || (REF + RY ) (269) The difficulty is finding RY .Low. 259.& Mid-Frequency Performance of CE Amplifiers Introduction to Electronics 181 To find the pole frequency f1 we need the Thevenin resistance “seen” by CE : iin + vin RB rπ E REF REB B ib C io + R L ’ vo - βi b RY RX Rthevenin Fig. assuming RS = 0.e. which is undertaken below: ib + vbe r itest + vtest Fig. 258. Finding RY . Finding Thevenin R “seen” by CE . i. then RY becomes: RY = (RB || RS ) + rπ β +1 (273) . ic ib = v be v = − test rπ rπ (270) βib i test = −(β + 1)i b (271) RY = v test r = π β +1 itest (272) If RS ≠ 0. assuming we are interested in vo /vin ..

(276) is not a focus of this course. for Av = vo /vs : f1 = 1   r + (RB || RS   2πCE REB ||  REF + π  β +1    1 =∞ : jf2CE f1 = 1 (274) (275) The zero f2 is the frequency where ZE ( jf2 ) = RE || f2 = 1 2πCE REB (276) The mathematical derivation of eq.Low.& Mid-Frequency Performance of CE Amplifiers Introduction to Electronics 182 Thus. One example of the Bode plot of a CE amplifier. 260. f1 . for Av = vo /vin :   r  2πCE REB ||  REF + π   β + 1    Or. it is left for your own endeavor. and the zero f2 . One of many possible examples is shown at left. 20 log Av mid 20 dB/dec f1 40 dB/dec fout The Bode magnitude plot of a common emitter amplifier is the summation of the effects of poles fin . 60 dB/dec fin f2 40 dB/dec Fig. . fout .

262. 261. It is difficult to analyze a circuit with a feedback impedance. Miller + Vin - Iz Zin.the circuits will be equivalent at the input port. but can be any network with a common node. Circuit with feedback impedance Z. the input port won’t “know” the difference . so we wish to find a circuit that is equivalent at the input & output ports: “Black Box” Zout. Miller so that Iz is the same in both circuits. The black box is usually an amplifier. . The Miller Effect is one of them. If we can choose Zin. we need some additional tools.The Miller Effect Introduction to Electronics 183 The Miller Effect Introduction Before we can examine the high frequency response of amplifiers. Consider: Iz Z + Vin - “Black Box” + Vout = AvVin - Fig. Circuit to be made equivalent to the previous figure. Miller + Vout = AvVin - Fig.

say. among other things. . If |Av | is. 2. 262: (277) IZ = Vin Z in.. then Zin. Miller = Z 1 − Av (279) Using a similar approach. the circuits can be made equivalent at the output ports. 261: V − Vo Vin − AvVin Vin (1 − Av ) = = IZ = in Z Z Z And from Fig. If Av > 1 and real. Av and all the impedances can be complex (i. phasors). 3. Miller ≈ Z. 10 or larger. also.The Miller Effect Introduction to Electronics 184 Deriving the Equations From Fig. (277) and (278) equal. then Zout. Miller (278) Setting eqs. to construct oscillators. and solving: Z in. if: Av 1 =Z Zout . Though not explicitly shown in the derivation.e. Miller = Z 1 (280) Av − 1 1− Av Notes: 1. Miller is negative!!! This latter phenomenon is used.

263. ≈ a few tens of ohms rπ = dynamic resistance of base region. C E rx = ohmic resistance of base region. we can show that gm = β/rπ = ICQ /VT . Hybrid-π model of BJT. as described previously ro = collector resistance of BJT. The hybrid-π BJT model includes elements that are negligible at low frequencies and midband. but cannot be ignored at higher frequencies of operation: Cµ B rx + vπ B’ rπ Cπ rµ g mv π ro E Fig. as described previously rµ .The Hybrid-π BJT Model Introduction to Electronics 185 The Hybrid-π BJT Model π The Model This is another tool we need before we examine the high frequency response of amplifiers. ≈ 100 pF to 1000 pF gm = BJT transconductance. Cµ represent the characteristics of the reverse-biased collectorbase junction: rµ ≈ several Megohms Cµ ≈ 1 pF to 10 pF Cπ = diffusion capacitance of b-e junction.

265. .The Hybrid-π BJT Model Introduction to Electronics 186 Effect of Cπ and Cµ Cµ B rx + vπ B’ rπ Cπ rµ g mv π ro E C E Fig. Cout . where Cπ and Cµ have an effect. and CE appear as short circuits. and CE . especially when compared to typical values of Cin . At low and midband frequencies. Notice the small values of Cπ and Cµ .. To focus our attention. 264. Simplified hybrid-π BJT model using the Miller Effect and the other assumptions described in the text. Hybrid-π model of BJT (Fig. Cπ and Cµ appear as open circuits. we’ll assume rx ≈ 0 and rµ ≈ ∞ . Cout . and we’ll use the Miller Effect to replace Cµ : B + vπ B’ rπ C1 Cπ gmvπ C 2 ro E C E Fig. At high frequencies. 263 repeated). Cin .

266 have a single-pole low-pass effect. the pole due to C1 + Cπ will dominate. From the Miller Effect equations. As frequency increases they become short circuits. Thus there are two low-pass poles with the mathematical form: fb = fh1 fh2 1 2πCeqRThevenin (283) Fig. Typical amplifier response in the midband and high-frequency regions. especially when RL’ is included in the circuit. Miller Effect applied to hybrid-π model (Fig.The Hybrid-π BJT Model Introduction to Electronics 187 B + vπ - B’ rπ C1 Cπ gmvπ C 2 ro C E E Fig. all Cs in Fig. Because C1 + Cπ >> C2 . and vo approaches zero . . 267. 266. The pole due to C2 is usually negligible. fh1 is normally due to C1 + Cπ . and fh2 is normally due to C2 . 265 repeated). (279) and (280): C1 = Cµ (1 − Av ) ≈ Av Cµ (281)  1 C2 = Cµ 1 −  ≈ Cµ Av   (282) Individually.

The overall half-power frequency. 265 repeated).. Then: fH ≈ 1 1 ≈ 2πC1RThevenin 2π Av Cµ RThevenin (285) i. fH is approximately inversely proportional to |Av | !!! Amplifiers are sometimes rated by their Gain-Bandwidth Product. 268. Miller Effect applied to hybrid-π model (Fig. C1 > Cπ . let us be very approximate and presume that Cπ is negligibly small.The Hybrid-π BJT Model Introduction to Electronics 188 B + vπ - B’ rπ C1 Cπ gmvπ C 2 ro C E E Fig.e. which is approximately constant. is usually due to C1 + Cπ : fH ≈ fh1 = 1 2π (C1 + Cπ )RThevenin (284) For typical transistors. This is especially true for high gains where C1 dominates. . then. For a moment.

270. We choose the common-emitter amplifier to illustrate the techniques: VCC R1 RS + vs + vin R2 RE CE Cin Q1 + RL vo RC Cout Fig. Amplifier small-signal equivalent circuit using hybrid-π BJT model. 269. Now we use the hybrid-π equivalent for the BJT and construct the small-signal equivalent circuit for the amplifier: Cµ RS + vs + vin B rx B’ rπ Cπ rµ g mv π ro E RL’ = ro||RL||RC C RL||RC + RB = R1||R2 vπ E Fig. estimate) the high-frequency performance of an amplifier circuit. 208 repeated).High-Frequency Performance of the CE Amplifier Introduction to Electronics 189 High-Frequency Performance of CE Amplifier The Small-Signal Equivalent Circuit We now have the tools we need to analyze (actually. Standard common emitter amplifier (Fig. .

271. 272. Av = R S’ + v s’ B’ + vπ - vo ′ ≈ −gmRL vπ C (286) Cπ Cµ (1+gmRL’) g m vπ R L’ + vo - Fig. we endeavor only to calculate fh1 . Thus we ignore the effect of Cµ on the output side. and apply the Miller Effect on the input side only. Modified small-signal equivalent. Note that the Thevenin resistance Rs’ = rπ || [rx + (RB||RS)] Recognizing that the dominant high-frequency pole occurs on the input side. .High-Frequency Performance of the CE Amplifier Introduction to Electronics 190 High-Frequency Performance We can simplify the circuit further by using a Thevenin equivalent on the input side. and by assuming the effect of rµ to be negligible: Cµ RS’ + vs’ B’ + vπ Cπ g mv π C R L’ + vo - Fig. and assuming rµ is infinite. using a Thevenin equivalent on the input side. calculate the voltage gain. Final (approximate) equivalent after applying the Miller Effect.

Final (approximate) equivalent after applying the Miller Effect (Fig. 273.High-Frequency Performance of the CE Amplifier Introduction to Electronics 191 R S’ + v s’ - B’ + vπ Cπ Cµ (1+gmRL’) g m vπ C R L’ + vo - Fig. 272 repeated). So we have fh1 = where 1 ′ 2πRS Ctotal (287) ′  Ctotal = Cπ + Cµ 1 + gmRL    and (288) RS ′ = rπ || rx + (RB || RS ) [ ] (289) .

an example: 20 log Av mid 20 dB/dec f1 fh1 -20 dB/dec 40 dB/dec fout 60 dB/dec fin f2 40 dB/dec Fig. . the common-emitter. One example of the entire Bode magnitude response of a common emitter amplifier. We’ve estimated the frequency response of only one amplifier configuration.High-Frequency Performance of the CE Amplifier Introduction to Electronics 192 The CE Amplifier Magnitude Response Finally. . the lower and upper 3-dB frequencies are the most important. . though. Of this plot. as they determine the bandwidth of the amplifier: BW = fH − fL ≈ fh1 − f1 (290) where the latter approximation assumes that adjacent poles are far away. The techniques. can be applied to any amplifier circuit. 274. we can estimate the entire Bode magnitude response of an amplifier.

Realistically. And gain-bandwidth product is constant: ft = A0fb = Aof fbf (292) . then. This discussion is limited to voltage amplifiers. dB The transfer function. Many internally-compensated op amps have their BW restricted to prevent oscillation. producing the Bode magnitude plot shown: 100 20 log A0 80 60 40 20 0 1 10 102 103 104 105 ft = A0fb 106 f.Nonideal Operational Amplifiers Introduction to Electronics 193 Nonideal Operational Amplifiers In addition to operational voltage amplifiers. low-pass form: A(s ) = A0 s +1 2πfb (291) Fig. has a single-pole. Rin ranges from ≈ 1 MΩ in BJT op amps to ≈ 1 TΩ in FET op amps. Hz fb 20 dB/decade Av . Gain and Bandwidth: Ideally. Av = ∞ and BW = ∞ . Av ranges from 80 dB (104) to 140 dB (107). there are operational current amplifiers and operational transconductance amplifiers (OTAs). 275. Linear Imperfections Input and Output Impedance: Ideally. Rout ranges from less than 100 Ω in general purpose op amps. Rin = ∞ and Rout = 0. Realistically. to several kΩ in low power op amps. Typical op amp Bode magnitude response.

currents must be limited to a “safe” value. 276. It dt is caused by a current source driving the compensation capacitor. For examples. This is the maximum rate at which vO can change.5 V/µs. General purpose op amps have output currents in the range of tens of mA. the LM741 has an output current rating of ± 25 mA. vo Expected output Actual output t Fig. Slew-Rate Limiting: dv o ≤ SR . Illustration of op amp slew-rate limiting.Nonideal Operational Amplifiers Introduction to Electronics 194 Nonlinear Imperfections Output Voltage Swing: BJT op amp outputs can swing to within 2VBE of ± VSUPPLY . Output Current Limits: Of course. the LM741 has a SR of ≈ 0. FET op amp outputs an swing to within a few mV of ± VSUPPLY . . As an example. while the LM324 can source 30 mA and sink 20 mA. Some op amps have internal current limit protection.

Brumm. current into inverting input These also have a polarity as well as a magnitude. VIO : vO is not exactly zero when vI = 0. Input Offset Voltage. The input offset voltage VIO is defined as the value of an externally-applied differential input voltage such that vO = 0.B.. current into noninverting input II. D. It has a polarity as well as a magnitude. . but consist of base bias currents (BJT input stage) or gate leakage currents (FET input stage): II+ .Nonideal Operational Amplifiers Introduction to Electronics 195 Full-Power Bandwidth: This is defined as the highest frequency for which an undistorted sinusoidal output is obtainable at maximum output voltage: v o (t ) = VOM sin ωt ⇒ dv o dt = SR = ωVOM = 2πfVOM max (293) Solving for f and giving it a special notation: fFP = SR 2πVOM (294) DC Imperfections: Many of the concepts in this section are rightly credited to Prof. Input Currents: Currents into noninverting and inverting inputs are not exactly zero.

and the input offset current as the difference: I + II IB = I 2 + − and IIO = II − II + − (295) Data sheets give maximum magnitudes of these parameters. so we define the input bias current as the average of these.Nonideal Operational Amplifiers Introduction to Electronics 196 In general.IIO/2 + IB + IIO/2 Fig. 277. VIO input bias current. Modeling the DC Imperfections The definitions of G G G input offset voltage. IB and. DC error model of operational amplifier. IIO lead to the following dc error model of the operational amplifier: vv+ III + I VIO . .. input offset current.+ i=0 ideal op amp i=0 - vO IB . II+ ≠ II.

Inverting op amp configuration. 278 and 279 are set to zero. It is often equal to zero. Notice that these circuits become identical when we set the independent sources to zero: RN RF + R+ Fig. 279. especially if dc error does not matter.Nonideal Operational Amplifiers Introduction to Electronics 197 Using the DC Error Model Recall the standard noninverting and inverting operational amplifier configurations. Note the presence of the resistor R+ . 280. . Identical circuits result when the sources of Figs. RN - RF + - RN vIN RF - + + R+ + - R+ Fig. 278. vIN Fig. Noninverting op amp configuration.

And replace the ideal op amp of Fig. 282. With the help of Thevenin equivalents. external source set to zero. 280 with this model: RN RF VOE I - + R+ VIO + I+ Fig. virtually all op amp circuits reduce to Fig.+ i=0 ideal op amp i=0 - vO IB .IIO/2 + IB + IIO/2 Fig. 282 when the external sources are set to zero !!! . recall the dc error op amp model: vv+ I III + VIO .Nonideal Operational Amplifiers Introduction to Electronics 198 Now. using dc error model. 277 repeated). Op amp noninverting and inverting amplifiers. 281. DC error op amp model (Fig.

to zero. Also note carefully the polarity of VIO . we’ll first set I. Op amp configurations. from these two error components alone. 283. Using superposition. is:  R  VOE . Currents resulting from these sources are shown in red. using dc error model. Part A = −  1 + F  (VIO + R + I + ) RN   (297) . finally. The voltage at the noninverting input is v + = −VIO − R + I + (296) This voltage is simply the input to a noninverting amplifier. And. 282 repeated) We can now determine the dc output error for virtually any op amp configuration. (Fig.Nonideal Operational Amplifiers Introduction to Electronics 199 RN I - RF VOE Note that the source VIO can be “slid” in series anywhere in the input loop. so the dc output error. with external source set to zero. note that the dc error current sources have been omitted for clarity. We have already noted the dc output error as VOE . + R+ VIO + I + Fig.

must flow through RF . we write (298) as: VOE . finally.e. we let VIO = 0 and I+ = 0.= 0. we combine (297) and (299) to obtain the totally general result:  R  VOE = −  1 + F  (VIO + R + I + − R − I − )  RN  (301) . i. so there is no current through RN . Part B = RF I − (298) + R+ VIO + I + Fig. using dc error model.Nonideal Operational Amplifiers Introduction to Electronics 200 RN I - RF VOE Next. 282 repeated) Now we make use of a mathematical “trick. (Fig. Now v+ = v.” To permit factoring.. Op amp configurations. creating the dc output error component: VOE . 284. with external source set to zero.. The current I. Part B = where  R  RN + RF RN RF I − = 1 + F  R − I − RN RN + RF  RN  R− = RN RF = RF || RN RN + RF (299) (300) And. we consider just I.

The maximum offset current magnitude is 40 nA. i. Finding Worst-Case DC Output Error: G Setting vIN to 0. The maximum offset voltage magnitude is 2 mV. 100 kΩ The maximum bias current is 100 nA. (301):  R  VOE = −  1 + F  (VIO − R − I − ) RN   where (1 + RF /RN ) = 11. and comparing to Fig.e.= 9. 285. 2] mV (304) Note also that the polarity of VIO is unknown. Note the missing term because R+ = 0..e. i. 100] nA (302) A positive value for IB means into the chip. 282 and eq.. DC output error example. VIO ∈[−2.Nonideal Operational Amplifiers Introduction to Electronics 201 DC Output Error Example 10 kΩ vIN + vO + Fig.09 kΩ. IIO ∈[−40.e. i. 40] nA (303) Note that the polarity of IIO is unknown. (305) . and R. IB ∈[0..

I. measurements on a particular chip.(9.. Thus from eq. (305): VOE = −(11)(2 mV .Nonideal Operational Amplifiers Introduction to Electronics 202 G The term (VIO . Without additional knowledge. from eq.R.0) = −22 mV (306) G The term (VIO . . (305): VOE = −(11)[−2 mV .) takes its largest negative value for VIO = -2 mV and I.= 100 nA + 40 nA/2 = 120 nA. we can not determine error with any higher accuracy.) takes its largest positive value for VIO = +2 mV and I.R.09 kΩ)(120 nA )] = +34 mV (307) G Thus we know VOE will lie between -22 mV and +34 mV.= 0 (we cannot reverse the op amp input current so the lowest possible value is zero): Thus.I. e.g.

We do however know the value of input bias current. IB . .Nonideal Operational Amplifiers Introduction to Electronics 203 Canceling the Effect of the Bias Currents: Consider the complete dc error equation (301). we can’t know these values in general.so that these terms canceled. we can eliminate the effect of IB if we select R + = R − = RF || RN (310) This makes the average error due to currents be zero.we could choose the resistances R+ and R. repeated below:  R  VOE = −  1 + F  (VIO + R + I + − R − I − )  RN  (308) If we knew the exact values of I+ and I. However. Rewriting (308) to show the effect of the bias currents:  R  I  I    VOE = −  1 + F  VIO + R +  IB + IO  − R −  IB − IO     2 2   RN   (309)  R  I  = −  1 + F  VIO + (R + − R − )IB + (R + + R − ) IO  2  RN   Thus.

as we usually don’t know the internal resistances of v1 and v2 with certainty or predictability. To obtain high CMRR. Difference amplifier. R4 /R3 and R2 /R1 must be very closely matched. 286. in general. . 287. But this is impossible. The solution is an instrumentation-quality differential amplifier!!! v2 + R1 vID vID R1 + + R2 + vY + R R R2 vO R R v1 + Fig.Instrumentation Amplifier Introduction to Electronics 204 Instrumentation Amplifier Introduction v2 vID + v1 R3 R1 R2 Recall the basic difference amplifier: op amp vO = vO + R4 R2 (v 1 − v 2 ) R1 R4 R 2 = R3 R1 (311) only if: Fig. Instrumentation amplifier.

. and the 2nd stage is a difference amplifier with unity gain. Thus:  R  v O = v Y = 1 + 2  (v 1 − v 2 ) R1   (313) Instrumentation amplifiers are available in integrated form. Current through these resistances is: v iR1 = ID (312) 2R1 This current also flows through R2 . Simplified Analysis The input op amps present infinite input impedance to the sources. Because the op amps are ideal vID appears across the series R1 resistances. both with and without the R1 resistances built-in.Instrumentation Amplifier Introduction to Electronics 205 v2 + R1 vID vID R1 + + R2 + R + R R2 vO R R v1 + Fig. 288. thus the internal resistances of v1 and v2 are now negligible. 287 repeated). Instrumentation amplifier (Fig. The voltage vY is the sum of voltages across the R1 and R2 resistances.

(315).127 R nV Hz (316) This means that. crosstalk. k = Boltzmann’s constant = 1. and Vin is the noise voltage of a 10 kΩ resistance at Troom . Johnson Noise This is noise generated across a resistor’s terminals due to random thermal motion of electrons. 2. if we have a perfect. etc. T = resistor temperature in kelvins B = measurement bandwidth in Hz. at Troom = 293 K: 4kTR = 0.g. The open-circuit rms noise voltage across a resistor R is: er = 4kTRB (315) From eq.38 x 10-23 J/K. Johnson noise is white noise.27 µV with an ideal (noiseless) true-rms voltmeter.the same noise power in each Hz of bandwidth: pn = 4kTB (314) where. noiseless BPF with BW = 10 kHz. .Noise Introduction to Electronics 206 Noise We can define “noise” in two different ways: 1.) Random inherent mechanisms. Any undesired component in the signal (e. meaning it has a flat frequency spectrum .. radio-frequency interference. we would measure an output voltage VOUT of 1.

Shot Noise Shot noise arises because electric current flows in discrete charges.60 x 10-19 C B = measurement bandwidth in Hz. The significance of Johnson noise is that it sets a lower bound on the noise voltage present in any amplifier. which results in statistical fluctuations in the current. It follows a Gaussian distribution with a mean value of zero. (317) . This amplitude distribution has a flat spectrum with very “sharp” fluctuations. Johnson Noise Model: A voltage source er in series with a resistance R.Noise Introduction to Electronics 207 Johnson noise is random. The rms fluctuation is a dc current IDC is given by: Ir = 2qIDC B where. etc. q = electron charge = 1. The instantaneous amplitude is unpredictable and must be described probabilistically. signal source.

10 kHz measurement bandwidth. a junction diode).. (317) IDC 1A 1 µA 1 pA Ir 57 nA 57 pA 57 fA % fluctuation 0. actual noise is less than that given in eq. (317) assumes that the charge carriers act independently. from eq.e. caused by various sources. This is false for current in metallic conductor (e.g. (317). This is true for charge carriers crossing a barrier (e.0057% (-85 dB) 5. rather than equal power per Hz. a simple resistive circuit).Noise Introduction to Electronics 208 Shot Noise. 1/f noise is pink noise . 1/f Noise (Flicker Noise) This is additional. the model gives a pessimistic estimate for design purposes.0000057% 0. . noise found in real devices. i. which means equal power per decade of bandwidth.it has a 1/f spectrum. or excess..g.6% Eq. For this latter case.

2 µV/V Other mechanisms producing 1/f noise: G G G G G G Base current noise in transistors. Loudness of a piece of classical music vs.01 µV/V to 0. Yearly flow of the Nile (measured over past 2000 years).02 µV/V to 0.Noise Introduction to Electronics 209 As an example. Flow of sand in an hourglass. time. Cathode current noise in vacuum tubes.10 µV/V to 3 µV/V 0. The table below lists the excess noise for various resistor types. .05 µV/V to 0. per volt applied across the resistor. The amount of additional noise depends on resistor construction. Speed of ocean currents. and measured over one decade of bandwidth: Carbon-composition Carbon-film Metal-film Wire-wound 0. The entries are given in rms voltage. let’s look at 1/f noise in resistors: Fluctuations in resistance result in an additional noise voltage which is proportional to the current flowing in the resistance.2 µV/V 0.3 µV/V 0.

The frequency spectrum and amplitude characteristics depend on type of interference: Sharp spectrum. cables. Motors. . Lightning. Some circuits.. Radio and television stations. probabilistic amplitude: Automobile ignition noise. Broad spectrum. etc. switching regulators. etc.Noise Introduction to Electronics 210 Interference In this case any interfering signal or unwanted “stray” pickup constitutes a form of noise. are microphonic: Noise voltage or current is generated as a result of vibration. detectors. switches. relatively constant amplitude: 60 Hz interference.

measuring the rms noise output. Definitions. 289. . so it appears as 1/f noise. Conventions Any noisy amplifier can be completely specified for noise in terms of two noise generators. en increases at lower frequencies. and is expressed in nV / Hz at a specific frequency.Amplifier Noise Performance Introduction to Electronics 211 Amplifier Noise Performance Terms. Noise model of an amplifier. Amplifier Noise Voltage: Amplifier noise voltage is more properly called the equivalent shortcircuit input rms noise voltage. en is the noise voltage that appears to be present at an amplifier input if the input terminals are shorted. en and in : Rsig vsig en + in Noiseless Noisy amplifier Fig. dividing by amplifier gain (and further dividing by B ). It is measured by: G G G shorting the amplifier input. It is equivalent to a noisy offset voltage.

“subtracting” noise due to en and the resistor (we discuss adding and subtracting noise voltages later). dividing by amplifier gain (and further dividing by B ).it increases at higher frequencies for FETs. in is the apparent noise current at an amplifier input. measuring the rms noise output. the default definition is a ratio of signal power to noise power (delivered to the same resistance. Signal-to-Noise Ratio: Expressed in decibels. and measured with the same bandwidth and center frequency): P  SNR = 10log sig   Pn  v  SNR = 20log sig   en  dB (318) It can also be expressed as the ratio of rms voltages: dB (319) . in increases at lower frequencies for op amps and BJTs . and is expressed in pA / Hz at a specific frequency. It is equivalent to a noisy bias current.Amplifier Noise Performance Introduction to Electronics 212 Amplifier Noise Current: Amplifier noise current is more properly called the equivalent opencircuit input rms noise current. It is measured by: G G G G shunting the amplifier input with a resistor.

has the noise temperature Tn. 290. 290) that produces vn at its output with a noiseless input.Amplifier Noise Performance Introduction to Electronics 213 Noise Figure: This is a figure of merit for comparing amplifiers. noiseless amplifier (Fig. 291. It indicates how much noise an amplifier adds. 291) with a source resistance at T = Tn produces the same noise voltage at its output. Noisy amplifier with ideal input. An ideal. . Ideal amplifier with noisy input. Fig. A real amplifier (Fig. The definition is illustrated below: Av RS (T = 0) Real (noisy) Amplifier Vn Av RS (T = Tn) Noiseless Amplifier Vn Fig. Defined simply:  Psig / Pn  input  NF = 10log  Psig / Pn output    It can be written even more simply: NF = SNRinput − SNRoutput ( ( ) ) dB (320) (321) Note that NF will always be greater than 0 dB for a real amplifier. it gives the same information about an amplifier. Noise Temperature: An alternative figure of merit to noise figure.

usually 290 K For good. ( ) T ⇔ NF = 10 log n + 1   T  (322) NF is expressed in dB T is the ambient (room) temperature. Because noise is probabilistic. we don’t know instantaneous amplitudes. or noise ± signal. low-noise amplifier performance: NF << 3 dB and/or Tn << 290 K Adding and Subtracting Uncorrelated Quantities This applies to operations such as noise ± noise.g.: v total = v sig + en 2 2 2 (323) . As a result we can only add and subtract powers. This means squared amplitudes add (rms amplitudes do not). e.Amplifier Noise Performance Introduction to Electronics 214 Converting NF to/from Tn : Tn = T 10NF / 10 − 1 where.

We presume the input resistance of the noiseless amplifier is much larger than Rsig . the noise voltage resulting from in flowing through Rsig The total input noise is (assuming they are uncorrelated): et = er + en + i n Rsig 2 2 2 2 2 (324) For convenience. the Johnson noise of Rsig . 289 repeated). and describe the following amplifier noise sources: er . 292. i.the amplifier noise source (amplifier noise referred to the input). Noise model of an amplifier (Fig.Amplifier Noise Calculations Introduction to Electronics 215 Amplifier Noise Calculations Introduction Repeating our amplifier noise model: Rsig vsig en + in Noiseless Noisy amplifier Fig. en . the amplifier noise contribution with a noise-free Rsig : eeq = en + i n Rsig 2 2 2 2 (325) .e. in Rsig . (324) as the equivalent amplifier input noise. we define the last two terms of eq..

Amplifier Noise Calculations Introduction to Electronics 216 Calculating Noise Figure The noise figure of this amplifier may now be calculated. We use the definition of NF as the ratio of powers. amplifier noise voltage dominates. FET amplifiers have nearly zero noise current. the amplifier noise current dominates. NF data must include values of Rsig and frequency to have significance. so they have a clear advantage !!! Remember. and let Gp represent the amplifier power gain:  Psig / Pn   Psig input × Pn output  input   = 10 log NF = 10 log P  Psig / Pn  × Psig output    n input output   2 P sig input Gp et = 10 log 2  er Psig inputGp  ( ( ) ) ( ( )  = 10 log e   e )   er 2 + en 2 + i n 2Rsig 2  (326)    2  = 10 log 2  er   r  2 t  en 2 + i n 2Rsig 2   eeq 2   = 10 log 1 + 2  = 10 log 1 +   er 2 er     Observe that for small Rsig . while for large Rsig . .

295. for variousquiescent collector currents. frequency. for various quiescent collector currents . Here is some typical data for Motorola’s 2N5210 npn BJT: Fig. 294. for various quiescent collector currents. Fig. frequency. source resistance. Fig. 2N5210 total noise voltage at 100 Hz vs. 2N5210 noise current vs. 2N5210 noise voltage vs. 293.Typical Manufacturer’s Noise Data Introduction to Electronics 217 Typical Manufacturer’s Noise Data Introduction Manufacturers present noise data in various ways.

IC = 1 mA) from Fig. repeated here: et = er + en + i n Rsig 2 2 2 2 2 (327) Example #1 Calculate the total equivalent input noise per unit bandwidth. 295. . er ≈ 4. We simply follow eq. 294.97 nV / Hz (328) This compares favorably (within graphical error) with a value slightly greater than 7 nV / Hz obtained from Fig. (324). 295.Typical Manufacturer’s Noise Data Introduction to Electronics 218 The en . en ≈ 4. it would take many calculations of this type to produce the curves of Fig. a plot of total noise voltage. 293. 293 and 294 can be used to construct Fig. and take the square root of the resulting sum gives : et = 6.5 pA / Hz (f = 100 Hz. 2. IC = 1 mA) from Fig. Evaluating eq. et . (327) .02 nV / Hz from eq. and a collector bias current of 1 mA: 1.5 nV / Hz (f = 100 Hz. for various values of Rsig . (316). Of course. in data of Figs. 3. in ≈ 3.remembering to square the terms on the right-hand side. for a 2N5210 operating at 100 Hz with a source resistance of 1 kΩ. 295.

Rsig = 1 kΩ). source resistance. we calculate:  (5.70)2   = 10 log(3.79 dB NF = 10 log1 + 2   (4. ICQ = 1 mA. in . 1. 296.01) = 4. From eq. 2N5210 100-Hz noise figure vs.02)  (330) which compares favorably to the value of approx. .Typical Manufacturer’s Noise Data Introduction to Electronics 219 Example #2 Determine the narrow bandwidth noise figure for the amplifier of example #1 (f = 100 Hz. at various quiescent collector currents. (326). repeated here  en 2 + i n 2Rsig 2   NF = 10 log1 + 2   er   (329) with the values of en . and er from example #1. 5 dB obtained from the manufacturer’s data shown below: Fig.

Inc.References and Credits References for this section on noise are: 1... 1989. The Art of Electronics. May 1974.artofelectronics. 293 . Check it out at http://www. It is available on National’s website at http://www.motorola.com 3.Noise .References and Credits Introduction to Electronics 220 Noise . Noise Specs Confusing?..com .national.com 2. This text has a good treatment of noise. This is an excellent introduction to noise. are available from Motorola. The 2N5210 data sheets. Paul Horowitz and Winfield Hill. I highly recommend that you get a copy. at http://www.296 are a part. of which Figs. Cambridge University Press. and makes a good general electronics reference. New York. Application Note 104. National Semiconductor Corp. 2nd ed.

operated at its saturation levels: VO VDC VDC ideal VI VO actual Fig. The Ideal Case VI is either VDC (logic 1) or zero (logic 0). A logic inverter is essentially just an inverting amplifier. Ideal and actual inverter transfer functions. . VO is either zero (logic 0) or VDC (logic 1). Logic inverter. 297. The Actual Case We don’t know the exact transfer function of any individual logic inverter. DC supply connections are not normally shown.Introduction to Logic Gates Introduction to Electronics 221 Introduction to Logic Gates The Inverter We will limit our exploration to the logic inverter. the simplest of logic gates. VDC /2 VDC VI Fig. Manufacturer’s specifications give us a clue about the “range” of permitted input and output levels. 298.

VOL = highest “low” (logic 0) output voltage. 299.Introduction to Logic Gates Introduction to Electronics 222 Manufacturer’s Voltage Specifications G G G G VIH = lowest VI guaranteed to be “seen” as “high” (logic 1). . fn. VIL = highest VI guaranteed to be “seen” as “low” (logic 0). 300. Fig. without causing an error in the output logic level. forbidden regions Output: Logic 1 VOH Input sees Logic 1 VOH NMH VIH VOL VIL VIH VDC VIL VI NML Output: Logic 0 VOL 0 Input sees Logic 0 Fig. Mfr’s voltage specs illustrated with example transfer functions. Mfr’s voltage specs illustrated on a number line. It is the smaller of: NM H = VOH − VIH and NM L = VIL − VOL VDC (331) VO VDC tr. And with VI meeting the above specifications: VOH = lowest “high” (logic 1) output voltage. Noise Margin Noise margin is the maximum noise amplitude that can be added to the input voltage.

it is the smaller of: I  FOH = int OH   IIH  and (332) I  FOL = int OL   IIL  Fig. Fan-out illustrated. It must be an integer. Fig. IOL = highest current that output can sink with VO ≤ VOL . 302. Reference directions for mfr’s current specifications.Introduction to Logic Gates Introduction to Electronics 223 Manufacturer’s Current Specifications Note that the reference direction for both input and output currents is into the chip. Fan-Out Fan-out is defined as the maximum number of gates that can be driven without violating the voltage specifications. IIL = highest possible input current with VI ≤ VIL . G G G G IOH = highest current that output can source with VO ≥ VOH . IIH = highest possible input current with VI ≥ VIH . 301. (333) . of course.

Introduction to Logic Gates Introduction to Electronics 224 Power Consumption Static Power Consumption: The static power is the power required to run the chip when the output isn’t changing. Thus. When the switch goes high. It may be different when the output is high may be different than when the output is low. . Simple model of logic gate output. V DC R HIGH At the end of this charging cycle. 303. and presume the switch begins in the low position. consider the following logic gate model. we normally assume that it is merely the average of the two. the charge stored in CLOAD is: Q = CLOADVDC (334) S C LOAD R LOW VO And the energy required of VDC to deliver this charge is: E = QVDC = CLOADVDC 2 (335) Fig. CLOAD charges from VOL ( ≈ 0) to VOH ( ≈ VDC ). Dynamic Power Consumption: Because load capacitance is always present. To understand this. additional power is required when the output is changing states.

half is stored in the capacitor: 1 2 EC = CLOADVDC 2 (336) The remaining half of the energy required of VDC has been dissipated as heat in RHIGH . suppose VO is continually changing states. Finally. i. goes low.e. Logic gate model (Fig.. and the energy stored in CLOAD is dissipated in RLOW..e.Introduction to Logic Gates Introduction to Electronics 225 V DC R HIGH S C LOAD R LOW VO Of the energy required of VDC . The energy dissipated in the gate per period is: 2 CLOADVDC 2 (337) = CLOADVDC f T But energy per unit time is power. 304. the dynamic power dissipation: Pdynamic = CLOADVDC f 2 (338) .. Fig. Now the switch changes state. i. 303 repeated).e. with period T). with a frequency f (i. CLOAD discharges toward VOL ( ≈ 0).

fall time time interval for a waveform to rise from 10% to 90% of its total change time interval for a waveform to fall from 90% to 10% of its total change tPHL and tPLH .Introduction to Logic Gates Introduction to Electronics 226 Rise Time. and Propagation Delay We use the following definitions to describe logic waveforms: tr . . propagation delay time interval from the 50% level of the input waveform to 50% level of the output tPD . the average of tPHL and tPLH tr vI 100% 90% tf VOH 50% 10% 0% VOL t vO tPHL tPLH VOH 50% VOL t Fig. fall time. rise time tf . and propagation delay. average propagation delay simply. Fall Time. Generic examples of rise time. 305.

It is defined as the product of propagation delay (speed) and static power dissipation (power) per gate Note this product has units of energy. Currently. the speed-power product of logic families range from approximately from 5 pJ to 50 pJ .Introduction to Logic Gates Introduction to Electronics 227 Speed-Power Product The speed-power product provides a “figure of merit” of a logic family.

0 0.Introduction to Logic Gates Introduction to Electronics 228 TTL Logic Families & Characteristics hex inverter ⇒ 7404 74S04 74LS04 74AS04 74ALS04 74F04 LS low-power S ALS advanced LS 4 1 -400 8 20 -0.0 2.5 2.0 V for all TTL families 0.5 -1000 20 20 -0.B.5 2 7 -2000 20 20 -0. D.7 0.5 3.4 2.7 0. .8 V for all TTL families .4 3 19 -1000 20 50 -2.5 AS advanced S parameter standard S Schottky tPD Pstatic IOH IOL IIH IIL VOH VOL VIH VIL ns mW µA mA µA mA V V V V 10 10 -400 16 40 -1.6 2.6 2.5 10 2 -400 8 20 -0. table compiled by Prof.4 0.7 0. . Brumm F FAST 3 4 unit .1 3.0 0.

Ratings for IOH and IOL are given for the specific VOH and VOL . . table compiled by Prof.5 3 .0 -1.15 -0.0 -1.0 4. parameter 74HCT 74HC 4000 tPD Pstatic IOH IOL IIH IIL VOH VOL VIH VIL VDC ns unit 80 90 9 10 5 < 1 µW for all versions mA mA µA mA V V V V V -1.5 .5 1.5 2-6 -24 24 1.0 3.0 -1.5 0.0 4.4 0.5 1..5 0.0 1.15 -4.0 -1.36 1.4 3.0 0.4 1.4 2.0 2. D. and are specifications for driving auxiliary loads.4 3.36 0.0 -1.0 3.0 0. .0 3. esp.Introduction to Logic Gates Introduction to Electronics 229 CMOS Logic Families & Characteristics These are typical examples of the guaranteed values for VDC = 5 V.0 2. not other gates alone. Brumm ACT 5 74C AC .7 0.5 -24 24 1.5 0.5 1.0 2.5 3 .4 3.7 0. in the 4000 series.8 5±0.5 1.8 5±0.0 -1.0 1.4 3.0 2-6 -4.4 2. Output current ratings depend upon the specific gate type.B.0 3.

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MOSFET Logic Inverters
NMOS Inverter with Resistive Pull-Up
As Fig. 306 shows, this is the most basic of inverter circuits. Circuit Operation: The term NMOS implies an n-channel enhancement MOSFET. Using a graphical analysis technique, we can plot the load line on the output characteristics, shown below. When the FET is operating in its triode region, it pulls the output voltage low, i.e., toward zero. When the FET is in cutoff, the drain resistance pulls the output voltage up, i.e., toward VCC , which is why it is called a pull-up resistor. Because VGS = VI and VDS = VO , we can use Fig. 307 to plot the transfer function of this inverter.

V DD
Drain Current, ID

10 V

9 8V

VGS = 7 V VGS = 6 V

R pull-up VO VI

VGS = 5 V

VGS = 4 V VGS = 3 V

Fig. 306. NMOS inverter with resistive pull-up for the load.

Drain Voltage, VDS

Fig. 307. Ideal FET output characteristics, and load line for VDD = 10 V and Rpull-up = 10 kΩ.

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Output Voltage, VO

Input Voltage, VI

Fig. 308. Inverter transfer function.

Drawbacks: 1. A large R results in reduced VO for anything but the largest loads, and slows output changes for capacitive loads. 2. A small R results in excessive current, and power dissipation, when the output is low. The solution to both of these problems is to replace the pull-up resistor with an active pull-up.

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232

CMOS Inverter
VDD vSGP+ S + vSDP G D + vGSN
G

Circuit Operation: The CMOS inverter uses an active pull-up, a PMOS FET in place of the resistor.
VO

VI

+ vDSN - S

D

The PMOS and NMOS devices are complementary MOSFETs, which gives rise to the name CMOS. In the previous example, the resistor places a load line on the NMOS output characteristic.

Fig. 309. CMOS inverter.

Here, the PMOS FET places a load curve on the output characteristic. The load curve changes as VI changes !!! The NMOS output curves are the usual fare, and are shown in the figure below:
10 V 9 8V VGSN = 7 V VGSN = 6 V

Drain Current, ID

VGSN = 5 V

VGSN = 4 V VGSN = 3 V

Drain-Source Voltage of NMOS FET, VDSN Fig. 310. Ideal NMOS output characteristics.

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10 V

9 8V

VSGP = 7 V VSGP = 6 V

Drain Current, |ID|

VSGP = 5 V

VSGP = 4 V VSGP = 3 V

Source-Drain Voltage of PMOS FET, VSDP Fig. 311. Ideal PMOS output characteristics.

The PMOS output curves, above, are typical also, but on the input side of the PMOS FET:
v SGP = VDD − v GSN
(339)

This means we can re-label the PMOS curves in terms of vGSN. And, on the output side of the PMOS FET:
v SDP = VDD − v DSN
(340)

This means we can “rotate and shift” the curves to display them in terms of vDSN. This is done on the following page.

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VGSN = 3 V VGSN = 4 V (VSGP = 6 V)

2V 1

0V

Drain Current, |ID|

VGSN = 5 V (VSGP = 5 V)

VGSN = 6 V (VSGP = 4 V) VGSN = 7 V (VSGP = 3 V)

VDSN (= 10 V - VSDP ) Fig. 312. PMOS “load curves” for VDD = 10 V.

The curves above are the same PMOS output characteristics of Fig. 233, but they’ve been: 1. 2. Re-labeled in terms of vGSN . Rotated about the origin and shifted to the right by 10 V (i.e., displayed on the vDSN axis).

VDSN Fig. |ID| VGSN = 5 V VGSN = 5 V VGSN = 6 V VGSN = 7 V VGSN = 4 V VGSN = 3 V NMOS Drain-Source Voltage. vI transfer function using the output voltages determined in step 3. We do so in the following manner: 1. The figure below shows the NMOS output characteristics and the PMOS load curves plotted on the same set of axes: 10 V 9 8V VGSN = 7 V VGSN = 3 V 2 V 1 VGSN = 6 V 0V VGSN = 4 V Drain Current. for each value of vI chosen in the previous step. 310. . 4. We determine the output voltage from the intersection of the output characteristic and the load curve. NMOS output characteristics (in blue) and PMOS load curves (in green) plotted on same set of axes. We choose the single correct output characteristic and the single correct load curve for each of several values of vI . We plot the vO vs. 312.MOSFET Logic Inverters Introduction to Electronics 235 We can now proceed with a graphical analysis to develop the transfer characteristic. on the same set of axes. We plot the NMOS output characteristics of Fig. 3. and the PMOS load curves of Fig. 2. 313.

315. 313 That for VI = VGSN ≤ 2 V the NMOS FET (blue curves) is in cutoff. Appropriate NMOS and PMOS curves for vI = 4 V. Drain Current. |ID| VI = VGSN = 3 V NMOS Drain-Source Voltage. |ID| VI = VGSN = 4 V NMOS Drain-Source Voltage. as shown in the figures below. . so the intersection of the appropriate NMOS and PMOS curves is at VO = VDSN = 10 V. 314. VDSN Fig. VDSN Fig. we select the appropriate NMOS and PMOS curve.MOSFET Logic Inverters Introduction to Electronics 236 Note from Fig. Appropriate NMOS and PMOS curves for vI = 3 V. Drain Current. As VI increases above 2 V.

MOSFET Logic Inverters Introduction to Electronics 237 Because the ideal characteristics shown in these figures are horizontal. VDSN Fig. |ID| VI = VGSN = 6 V NMOS Drain-Source Voltage. Appropriate NMOS and PMOS curves for vI = 6 V. as can be seen below. 316. |ID| VI = VGSN = 5 V NMOS Drain-Source Voltage. their curves are symmetrical. VDSN Fig. and the true intersection is precisely in the middle: Drain Current. Drain Current. . Appropriate NMOS and PMOS curves for vI = 5 V. thus the curves will have an upward slope. However. the intersection of the two curves for VI = VGSN = 5 V appears ambiguous. Because the NMOS and PMOS devices are complementary. real MOSFETs have finite drain resistance. 317.

so the intersection is at VO = VDSN = 0 V. VDSN Fig. 319. |ID| VI = VGSN = 7 V NMOS Drain-Source Voltage. 298. VO Input Voltage. Collecting “all” the intersection points from Figs. For VI = VGSN ≥ 8 V. Appropriate NMOS and PMOS curves for vI = 7 V.MOSFET Logic Inverters Introduction to Electronics 238 Drain Current. Note the similarity to the ideal transfer function of Fig. . VI Fig. 318. the PMOS FET (green curves) is in cutoff. CMOS inverter transfer function. 314-318 (and the ones for other values of vI that aren’t shown here) allows us to plot the CMOS inverter transfer function: Output Voltage.

while the common-mode voltage vICM is the average of the two (a measure of how they are similar). vID /2 As shown above. 2728: Modeling Differential and Common-Mode Signals 1 1 2 vI1 + vI2 + vICM + + + vID /2 2 Fig. vID . This material is repeated from pp. any two signals can be modeled by a differential component. vICM . 41 repeated). Representing two sources by their differential and common-mode components (Fig. 320. . if: v I1 = v ICM + v ID 2 and v I 2 = v ICM − v ID 2 (341) Solving these simultaneous equations for vID and vICM : v ID = v I1 − v I 2 and v ICM = v I1 + v I 2 2 (342) Note that the differential voltage vID is the difference between the signals vI1 and vI2 . and a common-mode component.Differential Amplifier Introduction to Electronics 239 Differential Amplifier We first need to remind ourselves of a fundamental way of representing any two signal sources by their differential and common-mode components.

Differential amplifier with only a common-mode input. Differential amplifier.. vID = 0.Common-Mode Input: We let vI1 = vI2 = vICM.Differential Amplifier Introduction to Electronics 240 Basic Differential Amplifier Circuit VCC RC iC1 vI1 Q1 + vO1 + vOD + vO2 Q2 RC iC2 vI2 The basic diff amp circuit consists of two emitter-coupled transistors. We can describe the total instantaneous output voltages: v O1 = VCC − RC iC1 v O 2 = VCC − RC iC 2 (343) IBIAS -VEE Fig.e. v OD = 0 (347) . From circuit symmetry. And the total instantaneous differential output voltage: v OD = v O1 − v O 2 = RC (iC 2 − iC1) (344) VCC RC iC1 vICM Q1 + vOD + + vO1 vO2 Q2 RC iC2 vICM Case #1 . we can write: iE 1 = iE 2 = iC 1 = i C 2 = and IBIAS 2 (345) + - vICM IBIAS -VEE αIBIAS 2 (346) Fig. i. 322. 321.

7 V - Case #2B .3 V IBIAS vID /2 = -1 V + RC iC2 +1 V + 0. but Q2 is cutoff. We have vID = -2 V and vICM = 0.3 V IBIAS RC iC2 -1 V + -1. Note that Q1 is active. 324.Differential Amplifier Introduction to Electronics 241 VCC RC iC1 +1 V + Q1 0. Differential amplifier with -2 V differential input.3 V + vOD + + vO1 vO2 Q2 0. Differential amplifier with +2 V differential input. and that a differential input steers IBIAS from one side to the other. which reverses the polarity of the differential output voltage!!! We show this more formally in the following sections.Differential Input: This is a mirror image of Case #2A.7 V + vOD + + vO1 vO2 Q2 0. VCC RC iC1 -1 V + Q1 -1. Thus we have: iC2 = 0 v O 2 = VCC iC1 = αi E 1 = αIBIAS v O1 = VCC − αRC IBIAS v OD = −αRC IBIAS (348) (349) (350) (351) (352) + vID /2 = 1 V - -VEE Fig. Now Q2 is active and Q1 cutoff: iC1 = 0 v O1 = VCC iC 2 = αi E 2 = αIBIAS v O 2 = VCC − αRC IBIAS v OD = αRC IBIAS (353) (354) (355) (356) (357) + vID /2 = -1 V - -VEE Fig.Differential Input: Now we let vID = 2 V and vICM = 0. 323. These cases show that a common-mode input is ignored. .3 V vID /2 = 1 V + Case #2A .

325. and use the forwardbias approximation to the Shockley equation: V  iC1 = IS exp BE 1   VT  v  iC 2 = IS exp BE 2   VT  (358) IBIAS -VEE Fig. (359) Dividing eq. 321 repeated). Differential amplifier circuit (Fig. (358) by eq. (359): v v  − v BE 2  iC 1 = exp BE 1  = exp ID  iC 2 VT    VT  From eq.Large-Signal Analysis of Differential Amplifier Introduction to Electronics 242 Large-Signal Analysis of Differential Amplifier VCC RC iC1 vI1 Q1 + vOD + + vO1 vO2 Q2 RC iC2 vI2 We begin by assuming identical devices in the active region. (360) we can write: (360) v  iC 1 + 1 = 1 + exp ID  iC 2  VT  And we can also write: (361) αI iC 1 i +i + 1 = C1 C 2 = BIAS iC 2 iC 2 iC 2 (362) .

as vid changes from approximately -4VT (-100 mV) to +4VT (+100 mV)!!! . . (363) and (364): iC / αIBIAS vID / VT Fig. . the result is: αIBIAS iC 1 = (364)  v  1 + exp − ID   VT  The current-steering effect of varying vID is shown by plotting eqs.Large-Signal Analysis of Differential Amplifier Introduction to Electronics 243 Equating (361) and (362) and solving for iC2 : iC 2 = αIBIAS v  1 + exp ID   VT  (363) To find a similar expression for iC1 we would begin by dividing eqn. normalized differential input voltage. Note that IBIAS is steered from one side to the other . Normalized collector currents vs. (359) by (358) . for a differential amplifier. . . 326.

Large-Signal Analysis of Differential Amplifier Introduction to Electronics 244 Using (363) and (364).iC1 ): iC 2    v   v  αIBIAS exp − ID  exp − ID      2VT    2VT  αIBIAS  = =   v    v  v   v  1 + exp ID  exp − ID   exp ID  + exp − ID    VT    2VT    2VT   2VT   (365)   v   v  αIBIAS exp ID  exp ID      2VT   2VT   αIBIAS  = iC 1 =    v  v   v   v   1 + exp − ID  exp ID   exp ID  + exp − ID    2VT   2VT   2VT    VT     v  v  exp ID  − exp − ID   2VT   2VT  = −αIBIAS RC  v  v  exp ID  + exp − ID   2VT   2VT  v  v OD = −αIBIAS RC tanh ID   2VT  (366) v OD (367) (368) Thus we see that differential input voltage and differential output voltage are related by a hyperbolic tangent function!!! . and recalling that vOD = RC ( iC2 .

for |vID| much less than 25 mV!!! We usually say the transfer function is acceptably linear for a |vID| of 15 mV or less. normalized differential input voltage. This transfer function is linear only for |vID /VT| much less than 1. we can perform a small-signal analysis of this circuit !!! . 327. a small input signal is less than about 15 mV.e.Large-Signal Analysis of Differential Amplifier Introduction to Electronics 245 A normalized version of the hyperbolic tangent transfer function is plotted below: VOD / αRCIBIAS vID / VT Fig. If we can agree that.. for a differential amplifier. i. Normalized differential output voltage vs. for a differential amplifier.

This means that vICM can be any value. Thus we can construct the smallsignal equivalent circuit using exactly the same techniques that we studied previously: IBIAS -VEE Fig. Differential amplifier (Fig. 321 repeated). 329. Small-signal equivalent with a differential input. .Small-Signal Analysis of Differential Amplifier Introduction to Electronics 246 Small-Signal Analysis of Differential Amplifier Differential Input Only VCC RC iC1 vI1 Q1 + vOD + + vO1 vO2 Q2 RC iC2 vI2 We presume the input to the differential amplifier is limited to a purely differential signal. 328. We further presume that the differential input signal is small as defined in the previous section. REB is the equivalent ac resistance of the bias current source. RC ib1 + vid /2 rπ + vo1 + vod + vo2 - RC ib2 rπ vid /2 + vX βib1 βib2 (β+1)ib1 REB (β+1)ib2 Fig.

Diff. small-signal equivalent (Fig. 330.Small-Signal Analysis of Differential Amplifier Introduction to Electronics 247 RC ib1 + vid /2 rπ + vo1 + vod + vo2 - RC ib2 rπ vid /2 + vX βib1 βib2 (β+1)ib1 REB (β+1)ib2 Fig. amp. 329 repeated). We begin with a KVL equation around left-hand base-emitter loop: v id = i b1rπ + (β + 1)(i b1 + i b 2 )REB 2 and collect terms: v id = i b1 rπ + (β + 1)REB + i b 2 (β + 1)REB 2 (369) [ ] [ ] (370) We also write a KVL equation around right-hand base-emitter loop: v id = ib 2rπ + (β + 1)(ib1 + ib 2 )REB 2 and collect terms: − − v id = i b 2 rπ + (β + 1)REB + i b1 (β + 1)REB 2 (371) [ ] [ ] (372) .

the voltage vX must be zero. point X is at signal ground for all values of REB !!! The junction between the collector resistors is also at signal ground. small-signal equivalent (Fig. 331. because vX = (ib1 + ib2)REB . Diff. amp. Adding (370) and (372): 0 = (i b1 + i b 2 ) rπ + 2(β + 1)REB [ ] (373) Because neither resistance is zero or negative. it follows that (ib1 + ib 2 ) = 0 (374) and. 329 repeated).e.Small-Signal Analysis of Differential Amplifier Introduction to Electronics 248 RC ib1 + vid /2 rπ + vo1 + vod + vo2 - RC ib2 rπ vid /2 + vX βib1 βib2 (β+1)ib1 REB (β+1)ib2 Fig. and can be analyzed separately !!! . so the left half-circuit and the right half-circuit are independent of each other.. i.

Avds1 = v o1 −βRC = v id 2rπ (376) In the notation Avds the subscripts mean: v. so we may write: v βRC Avds 2 = o 2 = (377) v id 2rπ Finally. 332. single-ended output The right half-circuit is identical to Fig. so we may write the gain equation directly: −βRC v o1 v = o1 = v in v id / 2 2rπ (375) For vo1/vid we must multiply the denominator of eq. Thus.vo2 . but has an input of -vid /2. we have the result: Avdb = v od −βRC = v id rπ (378) where the subscript b refers to a balanced output. (375) by two: Fig. voltage gain d. we can refer to differential gain for either a single-ended output or a differential output.Small-Signal Analysis of Differential Amplifier Introduction to Electronics 249 Analysis of Differential Half-Circuit The circuit at left is just the smallsignal equivalent of a common emitter amplifier. because vod = vo1 . . 332. differential input s. Left half-circuit of differential amplifier with a differential input.

Small-Signal Analysis of Differential Amplifier Introduction to Electronics 250 RC ib1 + vid /2 rπ + vo1 + vod + vo2 - RC ib2 rπ vid /2 + vX βib1 βib2 (β+1)ib1 REB (β+1)ib2 Fig. Remember our hyperbolic tangent transfer function? Eq. which can be single-ended or balanced. Diff. Differential Input Resistance This is the small-signal resistance seen by the differential source: v id / 2 = rπ i b1 ⇒ v id = Rid = 2rπ i b1 (379) Differential Output Resistance This is the small-signal resistance seen by the load. . 329 repeated). small-signal equivalent (Fig. . amp. 333. We can determine this by inspection: Ros = RC and Rod = 2RC (380) . (378) is just the slope of that function. evaluated at vID = 0 !!! Other parameters of interest .

Small-signal equivalent with a common-mode input. we represent the equivalent ac resistance of the bias current source as two resistors in series: IBIAS -VEE Fig. We again construct the small-signal circuit using the techniques we studied previously. RC ib1 + vicm rπ + vo1 + vod + vo2 - RC ib2 + rπ vicm - βib1 βib2 (β+1)ib1 2REB (β+1)ib2 2REB Fig. As a bit of a trick. Differential amplifier (Fig. 334.Small-Signal Analysis of Differential Amplifier Introduction to Electronics 251 Common-Mode Input Only VCC RC iC1 vI1 Q1 + vO1 + vOD + vO2 Q2 RC iC2 vI2 We now restrict the input to a common-mode voltage only. This is. The resistance of the bias current source is represented by 2REB || 2REB = REB. . we let vID = 0. 321 repeated). 335.

the small-signal ground also decouples the left half-circuit from the right half-circuit. The voltage across each 2REB resistor is identical because the resistors are connected across the same nodes. Again we need only analyze one-half of the circuit !!! . the current iX is zero and we can remove the connection between the resistors !!! This “decouples” the left half-circuit from the right half-circuit at the emitters. Therefore. 336. Small-signal equivalent with a common-mode input.Small-Signal Analysis of Differential Amplifier Introduction to Electronics 252 RC ib1 + vicm rπ + vo1 + vod + vo2 - RC ib2 + rπ vicm iX = 0 βib1 βib2 (β+1)ib1 2REB (β+1)ib2 2REB Fig. At the top of the circuit. Note the current iX .

(381) gives Avcs . Common-mode input resistance: Because the same vicm source is connected to both bases: Ricm = v icm v 1 = icm = rπ + (β + 1)2REB ib1 + i b 2 2i b1 2 [ ] (383) Common-mode output resistance: Because we set independent sources to zero when determining Ro . so we may write the gain equation: RC ib1 + vicm rπ + vo1 or vo2 - βib1 − βRC v o1 v = o2 = v icm v icm rπ + (β + 1)2REB (381) 2REB Eq.Small-Signal Analysis of Differential Amplifier Introduction to Electronics 253 Analysis of Common-Mode Half-Circuit Again. the commonmode gain for a single-ended output. the circuit at left is just the small-signal equivalent of a common emitter amplifier (this time with an emitter resistor). the output for a balanced load will be zero: Avcd = 0 (382) Fig. Either half-circuit of diff. Because vo1 = vo2 . we obtain the same expressions as before: Ros = RC and Rod = 2RC (384) . 337. amp. with a common-mode input.

For a single-ended load: CMRR = Avds rπ + (β + 1)2REB βREB = ≈ Avcs rπ 2rπ (385) For a differential load CMRR is theoretically infinite because Avcd is theoretically zero. Avcd = 0 if the circuit is symmetrical (identical left. CMRR will be much greater than that given above. In a real circuit. To keep these two CMRRs in mind it may help to remember the following: G G Avcs = 0 if the bias current source is ideal (for which REB = ∞ ).and righthalves). CMRR is almost always expressed in dB: CMRRdB = 20logCMRR (386) .Small-Signal Analysis of Differential Amplifier Introduction to Electronics 254 Common-Mode Rejection Ratio CMRR is a measure of how well a differential amplifier can amplify a differential input signal while rejecting a common-mode signal.

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