Chapter 7 Fre<juency Response


corner frequency. The midband gain is found in the usual way when capaci-

tances an: eliminated from the circuit. .

This lime constant technique yields good results when all poles are real, as will be the case in this chapter. In addition. this technique does not determine the corner frequencies due to system zeros. The major benefit of using the time constant approach is that it gives infomation about which circuit elements affect the -3 dB freq uency of the ci rcuit. A coupling capaci tor prod uces a high-pass network. so the form or the Bode plot will be the same as that shown in Figure 7.5- Also, the maximum gain is determined when the coupling capacitor acts as a short circuit, as was assumed In Chapters 4 and 6.

The time constant for the circuit is a function or the equivalent resistance seen by the capacitor. The small-signal equivalent circuit is shown in Figure 1.I6(bl. If we set the independent voltage source equal to zero, the equivalent resistance seen by the coupling capacitor Cc is (R .... i + RJ The time constant is then


This is the same as Equation (7.30), which was determined by using a currentvoltage analysis.

output CoupHng CapscltOl': Common.Soun:e CJtcuIt

Figure 7.17(a) shows a common- source MOSFET amplifier. We assume that the resistance of tile signal generator IS much less (han RG and can therefore be neglected In this case, the output signal IS connected to Ihe load through a coupling capacitor.





R5~ ~




V .... R(i '"

, - 51) id1

~ "":"'"



Fig ure 7.17 (a) Cammon·sou fee drCLIitwilh output coupli ng capacitor Bftd (b) small-slgl8.1 equivalenl circuit

The small-signal equivalent circuit, assuming rlj is infinite, is shown in Figure 7 .17(b). The maximum output voltage. assuming C (_' isa s~on circuit, is

W"lm;_~= Km Vxi RD II RJ.l (7.34)

and the input voltage can be written as


Part I SelllicQnductor Devices a~d IlaMe Applicalion~

Therefore, the maximum small-signal gam is


Even though the coupling capacitor is in the output portion of the circuit, the Bode plot will still be that or a high-pass network, as shown in Figure 7.5. Using the time constant technique to determine the corner frequency will sub. stantially simplify the circuit analysis, since we do not Spetitically need to determine the transfer function for the frequency response.

The time constant is a function of the effective resistance seen by capacitor Cc, which is determined by setting all independent sources equal to zero. Since Vi :::::!t 0, tben v's == 0 and gmVgs = 0, and the effective resistance seen by Cc is (Rp + RL)' The time constant lS then


and the corner frequency is fL = l/'brTs,

o.slon Exampl. 1.4 Obldv.: The circuit in Figure 7.11(a) is to be \.1$00 as a simple audio amplifier. Design tile circuit such that the lower corner frequency is it;;;;;; 20Hz.

801111101'1: The corner frequency can be written in terms of ihe time constant; as follows:

I iL=m,s

The time constant is then

1 I

fS = 2n[ = ~20):;;;} 7.96ms

Therefore. from Equation (731) the coupling capacitance is

c;:;;; IS ::;;; 7.% x JO-l :;::4.71 x lO-7 F

c- Rp + Rt 6.7 x 10> + 10 x 103


~ Commem: Using the time constant technique to find the corner frequency is easier than using the circuit analysis approach.

TeS1 Your Understanding

7.7 For tbe circuit in Figure 7.I6{a), the parameters are: Rs; = O.II:.Q. RI = 20kS1. R2=2.2kO, RE;O.lkn, Rc=2Ul, Cc=41J..1.F. and Vee = lOV. Tbe transistor parameters are: VBE(onl = 0.7 V. {J = 200, and VA = 00. {a) Determine the expression rOf the time constant IS- (b) Determine the comer frequency and midband vol,age gain. (ADs. (a) fS':;: (R; + RSiKc. (b)j = 1.76Hz,..t. = -11.2)

Chapter 1 Frequency ResPQIlI;e


D7.8 Consider the .eircuit shown in Figure 7.17(111) with transistor parameters VTN = 2V. K~ = 0.5mAjV2,and .l. = O. Tile circuit parameters are RG = 50kO and RL = lOUl ( .. ) Determine new values of Rs and RD such that IDQ :; 0.8 rnA and tile quiescent drain voltage is V DQ ~ 0, (b) Find the requi red value or C c for a comer frequency off ~ 20 Hz. (Ans, (a) Rs ::: 2.18 kQ, RD = 6.15 kn, (b) Cc = 0.49 "F)

Output CoupUn" Capacitor! EmttteroFollower ClreuU An emitter follower with a coupling capacitor in the output portion of the circuit is shown in Figure 7.18(a). We assume that coupling capacitor eel> which is part of the original emitter follower, is very large, and that it acts as a short circuit to the input signal.




R£:= '"

10 till kO

-IOV -

I K"
lea "
~" Itt; = lit =
IOkn IOlQ (8)


Figure 7.18 (a) Emlttet·tollower circuit with ou'put coup6ing capacib" and (b) sman-Sigoal 8(JIi\lalent circuit

The small-signal equivalent circuit, including the small-signal transistor resistance r,,, is shown In Figure 7.lS(b). The equi v alent resistance seen by the coupling capacitor en is (R" -+ Rd. and the time constant is

rs = [R" + RLICo


where R,) is the output resistance as defined in Figure 7.18(b). As shown in Chapter 4. the output resistance is

R= R 1·lr II ~ [, JI + (Rsil RB)] }

I) £" l I + (J

lf we combine Equations (7.39) and (7.38), the time constant expression becomes fairly complicated. However, the current-vohage analysis of this circuit including en is even more cumbersome. The time constant technique again sImplifies 'he analysis substantially,


EKample 1.5 Ob~.,.: Determine the 3dB frequency of an eminer-follower amplifier circuit with. an output coupling capacitor.

Consider the circuit shown in Figure 7.18(a) with transisl(tr parameters fJ = 100, Vl//:'( 0 n) = 0.1 V. and VA!::; 120 V. The: output coupling capacitanQc: Is. Co ::=: I pF.

Part I Semioonductor Devices and Basic Applications

Solutt.on: A de analysis shows that I C"Q = 0.&38 mAo Therefore, the small-signal parameters are: r,.. = UOkQ, tm = 32.2mA/V, and r.; = J431cn.

From Equation (7.39), the output resistance R(J of the emitter follower is

s, := R£lIr~1I tlr,.. + (RsIIRS'}}}


~ IOIf14311{[11O+I~L511100)I} "" 1()IIJ43I1o.0356kQ


R~ 2!' 35.5 n

From Equation (7.38}, {he time constant JS

'rs "'" (Rr + RtlCC,l ~ [35-5 + I (lIn O-~I ~ J x I(I-? s The 3 dB frequency is then


h ;;;:. mrs = 21r(1O-') ~ 15.9 Hz

Comment: Determinmg the 3 dB or COrner frequency is very direct with the lime constant technique.


Figure 7.19 PSpice analysis >esults for the emitter-follower circuit in Figure 7.18(a)

~mputH VerHlcaHon: Based on a PSpiCe analysis, Figure 7.19 is a Bode plot of the voltage gain magnitude of the emiuer-follower circuit shown in Figure 7. 1 8(a}. The comer frequency is essentially identical to that obtained by the time constant technique. Also, the asymptotic value orthe small-signal voltage gain is A,. = 0.988, as expected for an emiuer-foliower (ir(;uit.

. ,...... ...... Tech",,,,: ~ Plot of Gal" Magnitude

I. For a particular capacitor in a circuit, determine whether the capacitor is producing a tow-pess or high-pass circuit. From this, sketch the general shape of the Bode plot.

Chapter 1 FrequcrK:)' Response

2. The corner frequency is found rrom/ = Ij2ll''I:" where the time constant is T = R.qC. The eq ui va len t resistance R.'1 is [he equi valent resistance seen by the capacitor.

l The maximum gain magnitude is the midband gain. Coupling, and bypass capacitors act as short circuits and load capacitors act as open circuits.

Test Your Understanding

7.'8 For the emitter-follower circuit shown in Figure 7.18(a). determine (he required value of C(~ ro yield a corner frequency of 10 Hz. (A ns. C .. = loW !-IF}

7.3.2 Load Capacitor Effecls

An amplifier output may be connected to a load or to the input or another amplifier> The model of the: load circuit input impedance is generally a capacitance in parallel with a resistance. In addition. there is a parasitic capacitance bel ween ground and the line that connects the amplifier output to the load circuit.

Figure 7>2rna) shows a MOSFETcommon-source amplifier with a load resistance RL and a load capacitance CI. connected to the output, and Figure 7>20(b) shows the small-signal equivalent circuit. The transistor small-signal output resistance r 0 is assumed to be i nfinite, This circuit configura tion is essennally the same as that in Figure 1.3, which is a low-pass network. At high frequencies. the impedance of CL decreases and acts as a shunt between the output and ground. and the output voltage tends toward zero. The Bode plot is similar to that shown in. Figure 7.8, wi th an upper corner frequency and a maximum gain asymptote.

The equivalent resistance seen by the load capaci tor C L is Ro II RL. Since we set Vi == O. then g,n VSII = 0, which means that me dependent current source does not affect the equivalent resistance.

The lime constant for this circuit is




.IT .~ l~-kU

"":'"" ""':+"

v,~ g",V~~

v "'. t-


-=- ":""




Agure 7.29 (a) MOSFET oomlYlQfHOl,lA;8i drruit with a load ¢lpElCitor and (b) small-aignaJ eQuiva\ent Cll'Cl.lit

PaT! I Semiconductor Devices and Basic Applkations

The maximum gain asymptote, which is found by assuming CL is an open circuit, is


ExamPle 7.6 obi.ct.,.: Determine the comer frequency and maximum gain asymptote of a MOSFET amplifier.

For the circuit in Figure 7.2(t(a); the parameters are: Rs "" 3.2 kn. R() = IOlr.l, RE.::= 20kO, and CL:::: lOpE The transistor parameters are: Vrr;;;;:: -2V, Kp;;;;;; 0.25 rnA/V2. and ).. -= O.

Solution; From the de analysis, we find that InQ =.(L5mA. VS(;i] = 3.41 V, and VSDQ :::: 3.41 V. The transconductance is therefore

gm = 2Kp( V SG + V Tf) == 2(0.25)(3.41 - 2)= 0.705 mA/V From Equation (7040), the time constant is

II' -= (RDItRdCr = I( 10 x IOJ)II(20 x l03)(1O x IO·I~) = 6.67 x l()-~ s



Therefore. the coraer frequency is


In =-= ;;;;;} 2.39 MHz

211"'1" p lJT'(66. '1 )< 10-9)

Finally, from Equation (7_41), the maximum gain asymptote is ~ &,,(RDIIRt_) ~ (O.705)(IO~20) _ 144

IA,·lma~ - 1 +g"lRs - L +(0.705)(3.2) - .

Comment: The BOOe plot for this circuit is similar to that in Figure 18, and il represents a low-pass network. The relatively large value of Rs results in a low voltage gain.

Computer Simulation: Figure 721 shows the results of a PSpice analysis of the circuit given in Figure 7.20(a). Figure 7.21(a' is a Bode plot of the voltage gain magnitude. The


_IO~ 106 )01 lJ)!l f(H~)

~-'~~i~'i~i~ii~i --~~i niETi"iil~~~1~iiTi"i"~I--_'~

~IW -190










FlsIure 7.21 PSpice~· results for me ciralit in Figure 720(a): (a) voIage gain magnitude re&pense, and ~b) phaSe response

Chapler 7 Frequency Response

midband gain is 1.44 and the comer frequency IS 2.4 MHz, which agrees extremely well with the hand analysis results. The phase of the voltage gain ~s shown in Figure 7.2t(b). The midband phase is -180 degrees, as expected. Also. as the frequeacy increases, the phase approaches -210 degrees. As was shown in Figure 7,9. a, phase change of-90 degrees is expected for a load capacitor.

Tesl Your Understanding

D7.10 The PMOS common-source circuit shown in Figure 7.20(a) has a load resistance R, =c IOkQ. The transistor parameters are: Vn• =0 -2V. K,,;;;;;; O.5mAfV~, and A =(l, (a) Dcsign the circuit such that I[.IQ ;;;;;; I rnA and '"51>{';;;;;; VSGQ' (b) Detennine the value of C,_ such that the comer frequency IS f;;; I MHz_ (Ans. (a) Rs = 1.59 kQ. Rp::::; 5kn. ((:.1 c, .:;;:; 47_7pF)

7.3.3 Coupling and L.oad Capacitors

A circuit with both a coupling capacitor and a load capacitor 15 shown in Figure 7.22(a), Since the values of the coupling capacitance and load capacitance differ by orders of magnitude, the corner frequencies are far apart and can be treated separately as discussed previously. The small-signal equivalent circuit is shown in Figure 7.22(b), assuming the transistor small-signal resistance r; is infinite.

The Bode plot or the voltage gain magnitude is similar to that shown in Figure 7.1l. The lower corner frequency iL is given by

. I

_It =-2 ~

1fT ..


where Ts is the time constant associated with the coupling capacitor Ct, and the upper corner frequency fu is given by

. I III =-. 27f'f1'


where 'Cp is the time constant associated with the load capacitor CL< It should be emphasized that Equations (7.42) and (7.43) are valid only as long as the two corner frequencies are far apart.

Using the small-signal equivalent circuit in Figure 7.22(b), we set the signal source equal (0 zero to find the equivalent resistance associated with the coupling capacitor. The related time constant is

TS = IRs + {Rdl R2I1R;)Cc where


R;= f" + (I + P}RF,

Similarly, the time constantrelated to CL is

Tp = (RdIRdCL



Part I Semiconductor Devices and Basic Applications

+5 V



"_.,,,,0-1 Ul

~r I ~

__ -_-_~-.o_<>v"

___ - JI> +

III UR2 = lin



Figure 7.22 (c) Circuil with both a coupling and a load caoacnor and (b) smaU·signa~ eQuivalent circu~

Since the two corner frequencies are far apart. the gain will reach a maximum value in the frequency range between _fl. and lH. which is the midband. We can calculate the midband gain hy assuming that the coupling capacitor is a short circuit and [he load capacitor is an open circuit.

From Figure 7.22(b), we see that in midband We nave


ii= ~

Rs + R] /lR211Ri



and the outputvoltage is Vo = -glt! V~(RdR!.J





Chapter 7 Frequency Response

Finally, combining Equations 0.41) through {750), we find the magnitude of the midband gain, as follows:

~A,I ~ r~;!

= gmr1r(RcnRtlCR1:~~~: R)CRs + (R~lIR2I1Ri)1)

(7 .S1)

E ... mple 7.7 ObiecUve: Determine the midband gain. corner frequencies. and bandwidth of a circuit containing both a coupling capacitor and a load cap-acitor.

Considerthe circuit shown in. Figure 7.22(a) with transistor paramesers V,t(on) = O.7V. j3~ 100. and V,(=.Xl.

Solutio": The de ana1ysi~ of this circuit yields a q uiescent collector current of l('Q = O.~ rnA. The transconductance is

_ Ico _ 0.99 _ ()V gm - 1/1' -0.026 - 3",1 mAl

and the base diffusion resistance is

!;r "" flY T = (lOO:~02ti) ;;;;; 2.63 kQ


The input resistance R/ is therefore

R, = r~ + (I + P)Rc = 2.63 + (101)(0.5) = 53.1 kQ From Equation (7,511. the midband gain is

I A,lm.~ = I ~;LaJ\ = gmr,,(RcIIRd(RI :~::~ R)([Rs + (R: ~R11IR,)I)

( 40115<7)( 1 )

= (38.1)(2.63)(SHIO) (40"5.7) + 53.1 [OJ + (40"5.11151I)J


IA •. III1~L = 6.16

The lime constant rs is r.~= (Xs + R1IIR211R,)Cc

;;:;: (0.1 x 10) + (5.7 x 101)11(40)( 103)11(53.1 x 101»(10 x 1 0-6) ~ 4.66 x 10-2 S


ts = 46,6m&

and the lime constant 7:p is

tp == (Rell Rr)Ci. = ((5)( m3)1I(l1} x 103))(15 x IO-I!) = 5 x IO-ss


tp= 5Q ns

The lower corner frequency is

1 I

/'L = -;;;;; J =: 3.4.2 Hz

211'ts 21r( 46.6 'j(. )Q~ )


Pari I Semiconductor Devices and BasiC A.pplications

and the upper corner frequency is


iN ;;;;;; 2:rrTp = 2l'1'(50 )( IO-~) ~ 3.1 SMHz

Finally. the bandwidth is

ilw ~ iH -fL = 3.1&MHz- 3.4 Hz ~ 3.18MHz

Comment: The two corner frequencies differ by approximately SIX orders of magnitude: therefore, considering one capacitor at a time is a valid approach.

A figure of merit for an amplifier is the gabt-bandwidth procIuct. Assuming the corner frequencies are far apart. 'he bandwidth is

and the maximum gain is IA.lma\' The gain-bandwidth product is therefore


Later we will show that, for a given load capacitance. this product is essentially a constant. We will also describe how trade-offs must be made between gain and bandwidth in amplifier design.

7.3.4 Bypass Capacllor EHects

In bipolar and FEr discrete amplifiers. emitter and source bypass capacitors are etten included so that emitter and source resistors can be used to stabilize the Q~point without sacrificing the small-signal gain. The bypass capacitors are assumed to act as short circuits at the Signal frequency. However, to guide us in choosing a bypass capacitor, we must determine the circuit response in the frequency range where these capacitors are neither open nor short circuits.

Figure 7.23(a) shows a common-emitter circuit with an emitter bypass capacitor. The small-signal equivalent circuit is shown in Figure 7.23(b). We

. v'



(b) Response


can find the small-signal voltage gain as a function or frequency, Using the impedance reflection rule, the small-signal input current is


I/>= _ r

Rs + r" + (1 + P)( REI~s~J


The total impedance in the emitter is multiplied by the factor (I + /1). The control voltage is


and the output voltage IS


Combining equations produces the small-signal voltage gain. as follows:

.) _ V~,(s) _ -gmrllRc

A,.(.~ - ~ - ( ~ 1

ViC!') )

- Rs + ';11 + (l + P) Rf.: sC £


Expanding the parallel combination of RE and )/sC£ and rearranging (eons. we find

-gll1'nRc (I +sRECE)

AL-=[Rs+rJT+(I+tl)RfIX"{1 + SR£(Rs+rJr)CE} IRs + '" + (I -+ .B)Rr1


Eq uation -(7.58) can be written in terms of time constants as

-gltl'1[Rc II + st'A l

A,. =IRs+r;r +(1 +p)Rdll +SC8J

The form of this transfer function is somewhat different from what we have previously encountered In that we have both a zero anda pole.

The Bode plot of the voltage gain magnitude has two limiting horizontal asymptotes. If we set s ::0:: Jw. we can then consider the limit as w -+ 0 and the limit <lSW _ 00. For w --+ i). Cc acts as an open circuit; for tv -400, CE acts as a short circuit. From Equation {7.58), we-have


gmr"Rc IA"I~,_o = IRs + r,.. + (l + .B.Rd

(7 .fit( a))


~mr"R("" IAFlw--e>.:> = R


From these results, we see that for w - 0; RF: is included in (he gain expression. and for i» --+ 00. R£ is not part of the gain expression, since it has been effectively shorted out by C E.

I f we assume that (he time cons (ants r A and llJ in Equation (1.59) differ s\lb:;\i.lnt'~l\y in magnitude, then the corner frequency due to TO is


_ I

flJ=- lrrty

(7.61 (a»


Part I SemkonductOi Devices and Basic Apllllcalions

and the corner frequency due (0 r A is

I fA=- 21fT",


The resulting Bode plot of the voltage gain magnitude is shown in Figure 7.24.



Flgu .... 7.24 Bode pkJt 01 the \I'OItage gain magnilude for UW circuit wilh an emtt. bypass capadtor

Example 7.' ObiedIn: Determine the corner frequencies and limiting horizontal asymptotes of a common-emitter circuit with an emitter bypass capacitor ..

Considerthe circuit in Figure 1.23(a) with parameters Re = 4k.0., Rc = 2 kQ, Rs = O.5kg, CE," = llAf, r: "" !iV, and V- = -5V. The transistor parameters are: fj = 100, V BE(on) = 0,1 V. and r ~ = 00.

SoIutf(ln: From the de analysis. we find the quiescent collector current as iCQ '" 1.06 rnA, The transconductance is

lcO 1.06

gm = JlT = 0.026 = 4(1.3 mA/V

and tile input base resistance is

r .. == ~VT = (100)(0.026) = 145kO

IcQ .1.06

The time constant r" is

'1 = Reel = (4 x IcY)(1 x 10-6):::;; 4-.:: IO-~ s and the time constant fB is


r 8 ~ -___:::~::...............;.;.;___:;-

[Rs + r II + (l + ,f)Rl]

(4 x IO~)(O.5 x 10) +2.45 x 10')(1 x JO-~) = [0.5 x 10)+2.45 x 10] +(101)(4)( l(}l)l


rs = 2.90 x lO~~ s

The corner frequencies are then


fA :..._ .= 10 i)= 39.8 Hz

~l.l 2n(4 K -

Chapter 7 Frequency Response




h ;:;;; 2lnB ;:;;; 211'(2.9 )( IO-l) '* 5.49kHz

The limiting low-frequency horizontal asymptote, given by Equation (76O(a))is

g",r .s; (40.8)(2.45X2)

I/U .. _o = [Rs + r .. + (I + ,tI}RE1 = [O_~ + 2.45 + (lOt )(4)]


IA.I.: ..... o = 0.49

The limiting high-frequency horizontal asymptote, given by Equation (7,6O(b» is IA,.L ...... '" = gmi'1IRC = (40.8)(2.45){2) = 6j.8

Rs + r, 05 + 2.45

Comment: Comparing the two limiting values of voltage gain, we see that including a bypass capacitor produces a large high-frequency gain.

Computer VerlHclilon: The results of a 'Spice analysis are given in Figure 7.25. The magnitude of ,be small-signal voltage pin is shown in Figure 7,25Ia). The two corner frequencies are approximately 19 Hz and 5600 Hz, which agree very weU with the results



Flau •• 7.25 PSpice ana1ysI$ reWls for the drcuIt with an tH'I'IitW tP.;pee$ capacit<H: (a) Wl1tag8 gain magnilude response and (b) phase respcII'I$EI


Part [ Semiconductor ~v~s and Basic Applications

from the time constant analysis. The two limiting magnitudes or 0.49 and 68 also correlate extremely well with the 'hand analysis results.

Figure 7.25(bJ is a plot of the phase response versus frequency, AI very low and very high freq uencies, where the capacitor acts as either an open circuit or short circuit. thephase is -180 degrees, as. expected for .1 common-emitter circuit, Between the (WI) comer frequencies, the phase changes substantially, approaching -90 degrees,

The analysis of an FET amplifier with a source bypass capacitor is essentially the same as for the bipolar circuit. The general form of the voltage gain expression is the same as Equation (7.59), and the Bode plot of the gain is essentially the same as that shown in Figure 7.24.

Test Your Understanding

-7.1 t The circuit shown 11'1 Figure 7.23(;;) has parameters v+ = 10 V, V- = -10 V, R.~ =O.jkn. RE "" 4kn, and Rc = 2H'i!. The transistor parameters arc: I-'H/:.(on)~. 0.1 V, VA = 00, and (J -"" 100. (a) Determine the value of C f: such that the low-frequency 3 dB point is fs :;;;; 200 Hz. (b) U sing the results from part (a). determineh (Am. (a) C F; = 49.5I.1F. (bl.l~ = 0.8.0 Hz)

7.3.5 Combined Effects; Coupling and Bypass Capacitcrs

When a circuit contains rnultiple capacitors. the frequency response analysis becomes more complex. In many amplifier applications. the circuit is ((I amplify an input signal whose frequency is confined to (he midband range. In this case, the actual frequency response outside the midband range is not of interest The end points of the midband range are defined to he (hose trequencies at which the gain decreases by 3dB from the maximum midband value. These endpoint frequencies are a function of the high- and low-frequency capacitors. These capacitors introduce a pole to the amplifier transfer function,

lf multiple coupling capacitors, tor example, exist in a circuu, one capacitor may introduce the pole that produces the 3 dB reduction in the maximum gain at the low frequency. This pole IS referred to as the dominant pole. A more detailed discussion of dominant poles is given in Chapter 12. At this point in the text, we will determine the frequency response of circuits containing multiple capacitors with a computer simulation.

As an example, Figure 7.26 shows a circuit with two coupling capacitors and an emitter bypass capacitor; all of which affect the circuit response at low frequencies. We could develop a transfer function that includes all the capacitors, but the analysis of such circuits is most easily handled by computer.

Figure 7.27 is the Bode plot of the voltage gain magnitude for the example circuit, taking into account the effects of the two coupling capacitors. In this case. the bypass capacitor is assumed to be a short circuit. The plots consider C! and Cz individually, as well as together. As expected, with IWO capacitors both acting at the same time. the slope is 4OdB/decade or 12 dB/octave. Since the poles are not far apart, in the actual circuit, we cannot consider the effect of each capacitor individually.


,,[:."'.," ~l Co

.:Ii .....

, -=- R~ = 2KO kil


Figure 7.2fI Circuit with two COJJpling capacitors a.ndan em1tter bypass capacitor

Chapter" 7 Frequency Response


10" 111111

Flour.7.27 PSpice results for each <Xl\IPling capacilor. and lI'1e combined effect tor the circuit in Figure 7:26 (CE ...... OCt}

Figure 7.2l:! is the Bode plot of the voltage gain magnitude, taking into account the emitter bypass capacitor and the two coupling capacitors, The plot shows the effect or the bypass capacitor, the effect of the two coupling capacitors. and the net effect of the three capacitors together, When all three capacitors are taken into account, the slope is continually changing; there is no definitive corner frequency. However, at approximately / = 150 Hz, [he curve is J dB below tile maximum asymptotic value, and this frequency is definedas the lower corner freqlll'JKY. or 101ttr ctrt:oiT rrequency.

F1'IIur& 7.28 PSprce resuHs for the two Q:)1.J!:Iling capacitOfS. Ihe bypass capacitOl"; and the combined et1ects

Test Your Understanding

·7.12 Consider the common-base circuit shown in Figure 7.29. Can the two coupling capacitors be treated separately'! (a) From a computer analysis, detenninc the cutoff frequency, Assume the parameter values are ~ = 100 aad Is = 2 x urIS A. (bfDetermine the midband s-mall-silftal voltage gain. (Am. (a) ildl = 1.2 kHi, (b) A~ = 118)



,E ·'1

Part 1 Semiconeuctor Device. and Basic Applications

-s v

-s V

Flgu~ 7.29 Figure for EK9fCise 7.12

Figure 7.30 figure for Exercise 7.13

-7.13 The common-emitter circuit shown in figure 7.30 contains both a coupling capacitor and an emitter bypass capacitor. (a) From a computer analysis, determine the 3 d B frequency. Assume the parameter values are fJ "" 100 and ls ;; 2 x 10-1 s A. (b I Determine the midband small-signal voltage gain. (Am: (a) f~dB::>;;: 515 Hz. (b) 1A.lm"~=-~ 74.4)


Thus far. we have considered the frequency response of circuits as a function of external resistors and capacitors, and we have assumed the transistor to be ideal. However, both bipolar transistors and FETs have internal capacitances that inHuence the high-frequency response of circuits. In this section, we will first develop an expanded small-signal hybriLI'lr model of the bipolar transistor, taking these capacitances into account. We will then use this model to analyze the frequency characteristics of the bipolar transistor.

7.4.1 Expanded Hybrld·1T Equ~yalent Circuit

When a bipolar transistor is "sed in .a linear amplifier cireui t. the transistor is biased in the forward-active region. and small sinusoidal voltages and currents are superimposed on the de voltages and currents. Figllre 7.31 (a) shows an npn bipolar transistor in a common-emitter configuration, along with the smallsignal voltages and currents, Figure 7.31(bl is a cross section of the npn transistor in a classic integrated circuit configuration. The C. D, and E terminals are the external connections '0 the transistor, and the C', B', and E' points are the idealized internalcollector, base. and emitter regions.

To construct the equivalent circuit of the transistor. we: will first consider various pairs of terminals, Figure 7.32(a) shows the equivalent circuit for (he connection between the external base input terminal and the external emitter terminal. Resistance rio is the base series resistance between 'be external base



Chapter 1 Frequency Response




Figure 7.31 (a) Commoo-emitter I"J)I'I bij)OBr transistor wHh small-signal currents arid V()~ and (b) cross seclkm (II an rtPfl bipolar trarn;iskll', ~ the hybrki-ll model

FJ, B'
v:t '. c~
(I) E'



Flgur.7.32 Oomponents 01 the hybrii;l-rr equivalent circuit: (a) baSE to emitter, (b) collector to emiHer, and (c) bl:Ise to coll9ctor

terminal B and the internal base region B'. the .8'-6' junction is forward biased; therefore. C, is the forward-biased junction capacitance and 'If is the forward-biased junction diffusion resi sta lice. Both parameters are functions of the junction current. Finally, 'r~ is the emitter series resistance between the external emiuer terminal and the internal emitter region, This resistance is usually very small, on tile order of] to 2 Q.

Figure 7J2(b) shows the equivalent circuit looking into the collector terminal. Resistance 'cis the collector series resistance between the ex ternal and inlernal collector connections, and capacitance C, is the junction capacitance of the reverse-biased collector-substrate iuncuon. The dependent current source, gmVJl' is the transistor collector current controlled by the internal base-emitter voltage. Resistance '" is the inverse of the output conductance g{> and is due primarily to the Early effect.

Finally. Figure 7J2(c) shows the equivalent circuit of the reverse-biased B '-e' junction. Capacitance eli is the reverse- biased junction capacitance, and rj~ is the reverse-biased diffusion resistance. Normally, 'lLis on the order of megohms and can be neglected. The value of e,. is usually much smaller than e .. : however. because ora phenomenon known as the Miller effect, ell usually cannot be neglected. (We will consider the Miller effect later in this chapter.)

The complete hybrid-a equivalent circuit for the bipolar transistor is shown in Figure 1.33.. The capacitances lead to frequency effects in the tranaetor. One


Pari i SemicondlKlOr Devices and BasK: Applications


v.. Lr_~_c~---4 -+-- _ ___J~' r c.


Figure 7.33 Hybrid,,,, equiva.ltnt cifCJU

result is that the galn is a function of the input signal frequency. Because of the large number of elements. a compuer simulation of this complete model is easier than a hand analysis. However, we can make some simplifications in order to evaluate some fundamental frequency effects of bipolar transistors,

7.4.2 Short-Circuit Current Gain

We can begin 10 understand the frequency effects of the bipolar transistor b-y first determining the sbort-dreuit current gaill, after simplifying the hybrid-If model. Figure 7,34 shows a simplified equivalent circuit for the transetor, in which we neglect the parasitic resistances rh, r.. and 'w the B-C diffusion resistance r J.t. and the substrate capacitance CJ. Also, the collector is connected to signal ground, Keep in mind that the transistor must still be biased in the forward-active region. We will determine the small-signal current gain A; :; ut;

Writing a KCL equation at the input node, Wf; find that

Vn Vii' V~ [I. ]

h = ~+-l-+-l- = J/n-+)w(Cn+ Cp.)

Tn _. _ __ r'lf

jwCn jwCJJ,


We see that VI'!' is no longer equal to Inr", since a portion of h is now shunted through elf and ew

From a KCL equation at the output node, we obtain


-,- + t, = gm VJI




c" c
CIf '6
E !!mVIf Chapter 1 Frequency Response



I" = V1T(Cm - jwel/-) The input voltage V" can then be written as


VJI= '.

~Km - laC,"

Substituting this expression for V". into Equation (7.62) yields

[r'JI + jw(ClT + C,,)]

1;,:;;:;lc· •

(gm - lwell)

The small-signal current gain usually designated as hie, becomes

A• _ ~ _ I _ {gm ~ jwC ~J

, - 1" - I". - [' ]

'" + jw(C;r + CJ,.I)

lf'we assame typical circuit parameter values of C; = 0.2 pF.Km = 50mAJV,

anda maximum frequency of f '= ]OOMHz, then we see that wC).! «g .... Therefore, to a good approximation, the small-signa' current gain is


(7. 63{cH




Since gm'". = ~, then the low frequency current gain is just p. as we previously assumed. Equation 0.66) shows that, in a bipolar transistor, the magnitude and phase or the current gain are both functions of the frequency.

Figure 7,35(a) is a Bode plot of the short-circuit current gain magnitude.

The corner frequency, which is also the beta cutorrrrequency h in this case, is given by

. I

h~-~-- 2;rrrlT(C;or + ell)

Figure 7.35(b) shows the phase of the current gain. As the frequency increases, the small-signal collector current is no longer in phase with the




Fig.~ 7 _35 Bode plots 1ct the shoft-clcuil wrrent gain~ (8) magnlude and Ib) 9f'i88&

Pall I Sanicondlldor Devices and Basic Applications

small-signal base current. At high frequencies. the collector current lags the input current by 90 degrees.

EJt • .,ple 7.9 Objectl".: Determine the 3 dB frequency of the short-circuit current gain ora bipolar transistor,

Consider a bipolar transistor with parameters r1: == 2.6kQ, C ... ::::; 2pFi and eJ, = 0.1 pF.

Sotulioa: From Equation (1.67), we have



f~:: 29.1 MHz

Comment High-frequency transistors must have small capacitances; therefore, small devices must be used.

Test Your Understanding

7.14 A bipolar transistor has parameters fr .. = 150, Cor=2pF. find Cp ;;;;;; OJ pF. and is biased at fCQ ~ 0_5 rnA_ Determine the bela cutoff frequency, (Ans, h ;;;;;; S,S7MHz)

1.t I A BJT is biased a! leo = 0_25mA" and its parameters are P .. = 100 and ell' = 0.1 pF. The beta cetof]' [requeney is frr = 11.5 MHz. Determine the capacitance C". (Ans, C,,- = 1-23 pF)

7.4~3 Cutoff Frequellc~

Figure 7J5{a) shows that the magnitude of the small-signal current gain decreases with increasing frequency. At frequency [r- which is the cute" frequeacy, this gain goes to 1. The CU(ofT frequency is a figure of merit for transistors,

From Equation (7.66), we can write the small-signal current gainin the


h fj ..

It = I +j(L)


where h is the beta cutoff frequency defined by Equation (7,67). The magnitude of hf¥ Is

Ihftl = fJ,! (7.69)



Chapter 7 Freqllefl(Y Response

At the cutoff frequency [r. Injel = I, and Equation (7.69) becomes

Ih,;.1 = I = ---;::==fJ::,,==

I +(zY

Normally. {J(j » I, which implies that IT »/". Then Eq uanon (1.70) can be written as





F req uency It! is also called the band wi d th of 1 he t ra nsistor. Therefo reo from Equation O.71(b», the cutoff frequency [r is the gain-bandwidth product of the transistor, or more commonly the unity-gain bandwidtll. From. Equation (7.67), the unity-gain bandwidth is

lr = f3o[ I.] :::: glf1

2JTr,,(C,. + C,') 21T(C", + C",)


Since the capacitances are a function of (he size of me transistor. we see again

that high frequency transistors imply small device sizes. Ir

The cutoff frequency!Tis also a function of the de collector current Ie, and the general characteristic of [r versus Ie is shown in Figure 7.36. The transconductance gm is directly proportional to 1(", but only a portion of ell is related to Ie. The ellloff frequency is therefore lower allow collector current levels, However, the cutoff frequency also decreases at high current levels, in the same way that fJ decreases at large currents.

The cutoff frequency Or unity-gain bandwidth of a transistor is usually specified on the device data sheets. Since the low-frequency current gain is also given. the bela cutoff frequency, or bandwidth, of the transistor can be determined from

I. ~h

~ --



The cutoff frequency of the general-purpose 2N2222A discrete bipolar transistor isfT = 300 MHz. For the MSC3130 discrete bipolar transistor, which has a special surface mount package, (he cutoff frequency is Ir = I .4GHz, This teUs us that very small transistors fabricated in integrated circuits can have cutoff frequencies in the tow GHz range.



Figure 7.3'3 ClJtoff trequeili:;y V6f$US GOIIeCtor current

E. .... mpteT .10 O~: Calculate the bandwidth f Jj and capacitance C". of a bipolar transistor.

Consider a transistor that has parameters I, = 500 MHz at Fe =1 rnA, p. = 100, and C", = 0.3 pF.


Part 1 Semiconductor Devices and Basic Applications

SoJution: From Equation (7< 73J. the bandwidth is iT 500

Ij! ~ - ~. ~ ~ 5 MHz

f30 100

The transconductance is

Ie I . .

g", = VT ... 0.026 = 385 mA/V

Tile ell" capacitance is determined from Equation (1.12). We have

,. gm


2:rr(C" + C~)


500 x 106 = 38.S )( IO-~

2n(C". + 03 x 10-12)

which yields err = 12.0 pf.

CommeDt Although the value of CIt may be mud. larger than that of C", CjJ cannot be neglected in circuit applications as we will see in (he next section.

The hybrid-Jt equivalent circuit for the bipolar transistor uses discrete or lumped elements. However; when cutoff frequencies are on the order of IT ~ 1 GHz and the transistor is operated at microwave frequencies, other parasitic elements and distributed parameters must be included in the transistor model. For simplicity, we will assume in this text that the hybrid-a model is sufficient to model the transistor characteristics up through the beta cutoff frequency.

Test Your Understanding

7.18 For the Irans1stor described in Example 7.10 and biased lit tile same Q~point. determine Ih!~1 and the phase at f = 50 MHz. (Ans. Ih, .. 1 ;;;;;; 9.95, Phase = -84·n

7.17 The parameters or a. transistor are: Po = 120, h= 500 MHz. r r :; 5 tn. and C~ ;;;;;; O.2pF. Determine C" and!,. (Ans'!1l "" 4.17MHl. C":;; 7.43pF)

7.18 A BJT is biased at lc :;;;;; I mAo and its parameters are: fJ~ ;;;;;; 150. C" = 4pF, and CjI. .= 0.5 pf'. Determine f~ and fT' (Ans. h ;;;;;; 9.07 MHz. iT = 1.3(j GHz)

7.4.4 Miller Effect and Miller Capacitance

As previously mentioned; the ell- capacitance cannot in reality be ignored. The Miller effect. or feedback effect; is a multiplication effect of CIJ. in circuit appliations.

Figure 7.37(a) is a common-emiuer circuit with a signal current source at {he input. We will determine the small-signal current gain Ai = loJiJ of the circuit. Figure 7.31(b) is the small-signal equivalent circuit, assuming the is suffidentl)' high for the coupling and bypass capacitors 10 act as short eircuus. The transistor mood is the simplified hybrid·;rr circuit in

Chapur 1 Fnquenq Respoase




C..,I ! I I

Flgur. 7 .31 (a~ C{lmmOO-emilter oWl wirh currenl soorc:e inpu1; (b} smalH;isJnal equivalent cirtuit with simplified ~lf model


Figure 7.34 (assuming ro = 00). Capacitor C~is a feedback element that connects the output back '0 the input. The output voltage and current will therefore .influence the input characteristics,

We can determine the effect or C,. on the input characteristics by finding an equivalent impedance ZA across the plane A·A in Figure 7.38{a), producing the equivalent circuit shown in Figure 7.38(b). The current [I from Figure 1.38(a) can be written as

V~ - II" (V V)'wC

[I == (If.iwC .. ) = Jr - o U jJ

Summing the currents at the output gives

II ::;: (V/t - V,,)(jwC,J ~gmVII' + ~~RL

or combining terms, we have

J c~

-'~--t--I~- ...... ---...---_--o ~ t I

I '::tl I I









FlOU1'9 7.38 (a) OUlpUt portion 01 small-sigoaI equivalent tlrcuit; (b) eqUvaIant impedance of !his portioII of \he CiJtUiI

I , I'='" i

Part I Semiconductor Devkes and Bask AjI~hcati.l)ns

From our previous discussion of Equation (7.65), we noted that IjwClJl 4.: g", for typical transistor parameters, so the left side of Equation (7 .75(b» is just -g".V ... If, for example. Rc ::::: RL -:::- 4kn and C ... = O.2pF. then IjwC,,\ « 1/ (RclIRL) for f « 4OOMHz. If Ihis condition i:s valid. then Equation (7.75(b» becomes


Va = -gm(RdRdVn-

Substituting this expression for Yo into Equation (7.74) yields Il=={V~ - [-gm(RcIlRdVJtJlJwCJ,


(7. 77(a))



From Equation (7. 77(b»~ we see that the equivalent impedance ZA in Figure 7.38(b) then corresponds to 3 capacitance whose value is


The small-signal equivalent circuit in Figure 7.37(b) can be redrawn as shown in Figure 7.39. Capacitance C ~ is caned the Miner espacihllace and the multiplication effect of C; is calJed the Miller effect (Note: If the condition UwC.u I « Ij(Rcll Rd is not valid. then the CjJ capacitance is also reflected in the output circuit.


v. '11: c~

r--r--~r-o v~



Flgur. 1 .39 Small-signa~ equrvalent circ\.lit; including lhe EMlJival(lflt Mille; ~

From the equivalent circuit in Figure 7.39. the input capacitance is now err + eM. rather than just ell" if C., had been ignored.

Example 7.11 otojectiw: Determll'l¢ the 3 dB frequency of the current gain rOT the circuit shown in Figure 7.39, both wirh and withnul the etTect of C,w,

The circuit parameters are: Rc:;;;: Rj_ = 4, r .. ;;; 2.6 tn.. RB -;;:; 200 ka, C, = 4pF, CI';;; O.2pF.andgll1 == 3S.SmA/V.

So'uUon: The OUIPUI current call be written as

Chapter 7 Frequency Response

Also, (he input voltage is

V" '" 1.[ R81Ir"tw~JjW~J

;;;;;/[ . RBII'II ]

" l+jw(R81~I'R)(C".+CM)

Therefore, the current gain is

A~ ==!!_~ _g .. (. Rc)[ . RJlII'" ]

. l, Rc+RL l+jw(RBII'II)(C~+CM)

The 3 dB frequency is


fHB ;;;;; ~:-=-"--:-:-C~ __ -

1:rr(R9m,,,-)(C~ + C.II)

Neglecting the effect of CI'(C,II = 0), we find that


fJ as ~ 2111(200 x 10l)II(2.6 x I O~)1(4 x 10- 12] ~ 15.5- MHz

The Miller capacitance is

eM "" Cp[ I + g .. (RcII RdJ == (0,2)[1 + (38.,5)(4~14)] "" IS.6pF

Taking into account the Miller capacitance, the 3 dB frequency is I

hdB = 21t(RBHr,,)(CII + eM) I


hclB e:;: 3,16MHz

Comment: The Miller effect. or multiplication factor of C,.. is 78, giving a Miller capacitance of eM = 15.6 pf, The Miller capacitance, in this case, is approximately a factor of four larger than Cr This means tbac the actual transistor bandwidth is approximately five times less than the bandwidth. expected if GjI. is neglected,

The Miller capacitance, from Equation (7.78), can be wrinen in the form

where A 1 is the internal base-to-collector voltage gain. The physical origill of the Miller effect is in the voltage gain factor appearing across the reedbackekment (I" A small input voltage JI" produces a large output voltage Vc ~ -1A.I· V" of the opposite polarity at the O\ltput of Cw Thus tbe voltagt across C~ is (! +IAy~)V~, which Induces a large current through C". For this reason, the effect or Cp On the inputportion of the circuit is significant

We can now see one of tbe trade-()ffs that can be made in an amplifier design. The tradeoffis between amplifier gain and bandwidth. If the gain is redaced, men the Millet capacitance will be reduced and tile bandwidth wilt be increased. We wiD consider this tradeolT again when we consider the cascode amplifier later 11'1 the chapter.

Or.culSlon: In Equation (7,75(b), we assumed that IjWC .... 1 «gJr!' which is valid even for lrequencies in the HlQ MHz range. Equation (7,75(b)) can then be written as


Part I Semiconductor Devices and Basic Applications

The right side of Equation P Jl()) implies drat a capacitance C" should be in parallel with Rc and RL in the OUtput portion (If the equivalent circuit in Figure 739 .. For Rc "" R[ = 4 kr.l: and CI' = 0.2 pF, we indicated that this capacitance is negligible for f «.400MHz [yielding Equation p,76{a))], However, in special circuits involving, for example, active loads. the equivalent Rc and RL resistances may be on the order or 100 kn. This means that the C I' capacitance III the output part of the circuli is not negligible for frequencies even in the low-megahertz range. We will consider a few special cases in which C1, In the output circuit is n01 negligible.

Test Your Understanding

-7 .. 1$10 For the circuit in Figure 7J7(a), the parameters are: R, = 200 kQ, R1;::: 220kQ, Rc= 2,2kQ, R[ = 4.7 Hl Rr:;;;;; I kil, i, = HMHQ, and Vee = 5 y_ The transistor parameters are: fjr' = 100, II BF.(on) "" 0.7 y, V" ;;;;;: 00, C" ;;;;; IOpf, and C .. = 2 pF. USing the simplified hybrid-a model shown in Figure ;_34, calculate: (a) the Miller capacitance, and [b) the 3dB frequency, (Ans, (a) e/lt ;0; I09pF, (b~f1dB = 0,505 MHz)


We have considered the expanded hybrid-or equivalent circuit of the bipolar transistor that models the high-rr¢ql,l~nc-y response of the transistor. We will now develop the high-frequency equivalent circuit of the FET that takes into account various capacitances in the device, We will develop the model for a MOSFET, but it also applies to JFETs a nd MESFETs.

7.5.1 High-Frequency Equivalent Circuit

We will construct the small-signal equivalent circuit or a MOSFET hom the basic MOSFET geometry, as described in Chapter 5. Figure 7.40 shows a model based on the inherent capacitances and resistances in ann-channel MOSFET, as well as 'he elements representing the basic device equations.


Flgur.7.40 Inhefenj r8$i$tanC8S and capacitan;:es in then-d'tannel MOSFET structure

Chapter 7 Frequency Response


We make one simplifyio.g assumption in the equivalent circuit: Tile source and substrate are both tied to ground.

Two capacitances connected to the gate are inherent in the transistor.

These capacitances, C~ and Cgd, represent (he Interaction between the gate and the channel inversion charge near the source and drain terminals. respectively, If the device IS biased in the nonsaturation region and "DS" is small, jne channel inversion charge is approximately uniform, which means thai

where C",( F /cm~) = "ru I lox ; The parameter "o~~ is the oxide permi ttivity, which for silicon MOSFETs is "[I.r = 3,9£'0' where fo == 8.85 X 10-14 F/em is the permittivity of free space. The parameter lo~ is the oxide thid:ness in em,

However, when the transistor is biased in the saturationregion, the channel is pinched orr at the drain and the inversion charge is no longer unifonn. Tile va I ue of CsJ essentially goes (0 zero, and Cgs approximately f<l.~ls (2/3) W LC/\. As an example, if a device has an oxide thickness of 500 A, a channel length of L.::o: 51J11l. and a channel width of W = 50l-lm, the value of fgs is C~.r ~ 0.12 pF.. The value of Cg.~ changes as the device size changes, but typical values are in the tenths of picofarad range.

The remaining, tWQ gate capacitances" C~p and C"Gp' are parasitic or everlap capacitances, so called because, in actual devices, the gate oxide overlaps the source and drain contacts, because of tolerances or other fabrication factors. As we will see, the drain overlap capacitance C~Jp lowers the bandwidth of the FET. The parameter Cds is the drain-to-substrate pn junction capacitance, and rs and id are the series resistances of the source and drain terminals. The internal gate-to-source. voltage controls the small-signal channel current through the transcon ducta nee.

The small-signal. equivalent circuit for the n-channel common-source MOSFET is shown in Figure 7.41. Voltage V; is the Infernal gate-to-source voltage 111at controls the channel current. We wilt assume that the gate-tosource and gate-to-drain capacitances, Ct, and Cgd• contain the parasitic overlap capacitances. One parameter, r~, shown in Figure 7.41 is not shown in Figure 7040, This resistance is associated with the slope of Iv versus VDS' 111 the ideal MOSFET biased in the saturation region, I D is independent of VDS' which means that r" is infinite. However, r p is finite in short-ehannel-leegth

© cg4 rd @
0-- II
+ .,.
v;. c~. T"
,,,,v; .•
v~< ®

Part I SemicondllCtor Devtces a nd Basic Applita tions

devices, because of channel-length modulation, and is therefore included in the equivalent circuit.

Source resistance r, can have a significant effect on the transistor characteristics. To illustrate, Figure 7.42 shows a simplified low-frequency equivalent circuit including r, but not roo For this circuit, the drain current is

Td =g",V;.r and the relationship between V gf and V ~ is

YtJ~ V~ + (gm V;Jr. = (1+ gmr~) r; (7.81)

From Equation (7.81). the drain current can 110W be written as






FIgure 7.42 Simplified Iow'(requency equlvaJent drcuit 01 1M fl'Channel common-sooroe t.«:>SFET Including SOUI'Qll ~i:stanee (~ but rot resista~ '0

Equation (7.83) shows that the source resistance reduces the effective transconductance, or the transistor gain.

The equivalent circuit of a p-channel MOSFET is exactly the same as that of an n-channel device, except that aU voltage polarities and current directions are reversed. The capacitances and resistances are the same for both models.

Test Your Understanding

7.20 An n-channel MOSFET bas parameters K;;;;;;;; O.4mAjVi, VrN;;;;;; 1 V, and J,. = O. (a) Determine the maximum source resistance such that the transconductance is reduced by no more than 20 percent frern its ideal ~all.te when Vus = 3 V. (b) Using tbe value of 'I calculated in part (a). determine how much gm is reduced from its ideal value wben Vos = 5 V. (Ans. (3.) 's= 1560, (b) 33.4%)

7.5.2 Unlty .. Galn Bandwidlh

As for the bipolar transistor, the unity-gain frequency or bandwidth is a figure ofmerit for the FETs. ]fwe neglect ,~. '.I, r/» and C~. and connect the drain 10 signal ground, the resulting equivalent small-signal circuit IS shown in Figure 7.43. Since the input gate impedance is no longer infini1e at high frequency, we

Chaplet' 1 Fnquency Retponst


Flgp" 7.43 Equivalenthigh-frequeney $lI1a1I-signal circuit of a MOSFET. for calcul&ting shon-ercut current gain

can define the short-circuit current gain. From that we can define and calculate the unity-gain bandwidth.

Writing a KCL equation at the input node, we find that

V8_, VgS .

II =~. ~l- + -1- = V~_.[Jw(C8' + CgJ)} (7.84)

jwCl1, jwCgJ

From a KCL equation at the output node, we obtain


-1-+ IrJ = gmVgs


(7. 85(a»)


/J"'" V1"(g,,, - jwCgJ) Solving Equation (7.S5(h») for Vgt produces


V,r., = .

(gm - lWegd)

Substituting Equation (7.86) into (7.84) yields

t, = Jp' [jw(Cg,,:+ Cgd)] !Em - JwCgI)

Therefore, the small-signal current gain is

1.1 gm - jwCgd

A i= - = -: '--___;:_---'~

Ii }w(C,;.1 + C([d)

If we assume typical values of Cga '='" 0.05 pF and gm = ] rnA/V. and a maximum frequency of f = 100 MHz. we find that wCtd «1m. The smallsignal current gain, to a good approximation, is then





A _lrJ Q< gill

1-1/ - j~C!!" .. + CgJ)

The unity-gain frequency Ir is defined as the frequency at which the magnitude of the short-circuit current gain goes to I. From Equation (1.89) we find that



Part I Semiconductor Devices <tOO Basic Applications

The urury-gain frequency or bandwidth is a parameter of the transistor and is independent of the circuit.

Example 7,12 ObJecti": Determine the unity-gain bandwidth or an fET.

Consider an n-channel MOSFET with parameters K~ ;;;;- O.25mA/V2, Vnol :;: 1 V.

A = 0, Ctd = 0.04 pF, and ex> = 0.2 pF, ASSUIJ\f the transistor is biased at V GS = 3 V,

Solullo.: The transconductance is

From Equation (7.90). the unitv-gain bandwidth. Or frequency. is

fr = 663 MHz

Comment As With bipolar transistors, high-frequency FETs require small capacitances and a small device size.

Typically, values ofe!:. for MQSFETs are in the range of 0-1 to O.5pF and values of C" are typically from O.ot to 0.04 pf'.

As previously stated. the equivalent circuit is the same for MOSFETs, JFETS, and MESFETs- For JFETs, and MESFETS, capacitances Cg~ and Cgd are depletion capacitances rather [han oxide capacitances. Typically, for JFETs, Cgs and ega are larger than for MOSFETs, while the values for MESFETs are smaller, Also, for MESFETs fabricated in gallium arsenide. the unity-gain bandwidths maybe in the range of tens of GHz. For this reason. gallium arsenide MESFETs are often used in microwave amplifiers.

Test Your Understanding

1 .. 21 For an a-channel MOSFET, the parameters are: K~ = 0.1 mAJV~. V TN ;;;;;; IV. )..;;;;;: 0, Cgd = 1),02 pF, Cf$:=;;; 0.25 pf. The device is biased ar IDQ ;;;;- O,4mA. Determine the unity-gain frequency. (Ans. fr ~ 332 MH~)

7.22 A MOSFEf bas a unity-gain bandwidth of Ir = 500 MHz_ Assume overlap capacitances of eM!' = C tdr = OJ)} pf. If the transistor is biased such that il'm = 0.5 rnA/V, determine Cr" (Assume Cgd is equal to the overlap capacirance.) {Ans, eJl" ~ Q.139pF)

7.. For 31 MOSFET. assume that gm = I rnA/V, The basic gate capacitances lire Cg~ = 004 pF, C~d ;;;;- 0, arid the o .. erlap capacitances are C!l>P= Cgtlp- Determine the maximum overlap capacitance for aunity-gain bandwidth of 350 MHz. (Am. C~"P= C .. ;;:; 0.0274 pF)


7.5.3 Miller Enect and Miller Capacitance

As for the bipolar transistor, the Miller effect and Miller capacitance are factors in the high-freq uency characteristics of FET circuits. Figure 7.44 is a simpli fied high-Ireq uency transistor model, with a load resistor RL connected 10 the output, We wiJl determine the current gain in order to demonstrate the impact of the Miller effect.


FISlur. 7.44 Equivalent high-frequency small-&gnal cii'Cuil of a MOSFET with a load resistance RJ.

Writing a Kirchhoff current law (KCL) equation at the input gate node, we have


where Ii is the input current. Likewise, summing currents at the output drain node, we have


We can combine Equations (7.91) and (7.92) to eliminate voltage Vd~' The input current is then


Normally, (IiJR,L C~d} is much less than I; therefore. we can neglect (jWRL Csd) and. Equation (7.93) becomes


Figure 1AS shows the equivalent circuit described by Equation (7.94). The parameter eM is the Miller capacitance and is given by


Equation (7.95) clearly shows (he effect of the parasitic drain overlap capacitance. When the transistor is biased in the saturation region, as in an amplifier circuit, the major contribution [0 the total gate-to-drain capacitance C1d is the overlap capacitance. This overlap capacitance is muluplied because of the Milh effect and may become a significant faoCtor in the bandwidth of an amplifier. Minimizing the overlap capacitance is one or the challenges of fabrication technology,

Pan I Semic<mdUClor Devices and Basic Applications

0 I
+- -
Vg• flour.l.45 MOSFET high-frequency circuit, InCluding tile equivalent Miler capacitance

The cutoff frequency J T of a MOSFET is defined as the frequency at which the current gain magnitude is 1, or the magnitude of the input current Ii is equal to the ideal load current h From Figure 7.45, ..... e see that


and the ideal load current is


The magnitude of the current gain is therefore


Setting Equation (7.98) equal to I, we find the cutoff frequency

j - 8m _~

T- -

21t'(Cgs + eM) 2'1f'CG


where CG is the equivatent input gate capacitance.

Example 7.13 Ob)ecll.,.: Determine the Miller capacitance and cutoff frequency of an FET circuit.

The a-channel MOSFET described in Example 7.12 is biased at the same current, ami a IOkQ load is connected to the output.

Solution: _ From Example 7.12, the transconductance is gm "" t rnA/V. The Miller capacitance is therefore

eM = C~il + g..,RtJ = (0.04)[1 + jl)(LO)] = 0.44 pF

From Equation (199). the cutoff frequency is

;;:; . gm =. IO-~ '= 2.49 x 108 Hz

iT 2l1'(,Cg• t eM) 2ni,O.2 + 0.44) x url2


IT ~ 249 MHz

COmmellit The Miller effect and equivalent MiliCI' capacitance reduce lbe cutoff frequency of an PET circuit, just 8$ they do in a bipolar circuit.

Chapter "I Frequellcy Response

Test Your Understanding

·7.24 for (he circuit in Figure 'I A6, the transistor parameters are: K; = 0.5 mA/Vz, V TN :::: 2 V. A ~ 0, C td = 0.1 pF, and C~, ""- I pf', Calcu late: (a) the Miller capacitance. and (h) the JdB frequency of the small-signal voltage gain, (Am. (a) eM = 0.617 pF, (b}fH:::: IO.9MHz)

Flgu,& 7.46 Figure lor EKet'Clse 7.24


In she last sections, we developed the high-freq uency equivalent circuits for the bipolar and field-effect transistors. We also discussed the Miller effect. which occurs when transistors are operating in a circuit configuration. In this section, we will expand our analysis of the high-frequency characteristics or transistor circuits.

Initially, we will 100k at the high-frequency response or the commonemitter and common-source configurations. We will then examine commonbase and common-gate circuits, and a eascode circuit that is a combination of the common-emitter and common-base circuits. Finally, we will analyze the high-frequency characteristics of emitter-follower and source-follower circuits. In the following examples, we wiil use Ihe same basic- bipolar transistor circuit so that a good comparison can be made bet ween the three circuit configurations,

7_6.1 Common-Em Iller and Common-Source CIrcuits

The transistor capacitances and the load capacitance in the common-emitter amplifier shown in Figure 7.47 affect the high-frequency response of the circuit. Initially, we will use a hand analysis to determioe the effects ofthc transistor on the high·frequency response. In fhis analysis, we \\JiD aasume that Cc and C£

Pan] Semicoeductor Devices and Basic A.pplkauQns


'~ ~

-::- H2


FtgUr6 7 •• 7 CommOl1-emiHtr ampirier

are short circuits, and Cl is an open circuit. A computer analysis will then be used to determine the effect of both the transistor and load capacitances.

The high-frequency small-signal equivalent circuit of the common-emitter circuit is shown in Figure 7.48(a) in which C L. is assumed to be an open circuit. We replace the capacitor CIA- with the equivalent Miller capacitance eM as shown in Figure 7.48(b). From 011r previous analysis of the Miller capacitance, we can write

(7 _tOO)

where the output resistance RJ is '"IIRtIiRL.

The upper 3 dB frequency can be determined by using the time constant technique. We can write

I iH=- 2lrf,


where "rp = RtqCeq. In this case, tbe equivalent capacitance is Ceq ::::: C 1f + eM' and the equivalent resistance is fhe effective resistance seen by the capacitance, R"i :; r",11 R811 Rs. The upper corner frequency is therefore


fH =: -21l"{-'-Ir-n R-B-~ R-s~1(~C:-,,~+-C"""'M-)



iB V" r",:

~ ~

figure 7 AI (a) ~ffequeney ~ draiI 01 ~r amplifier; (b) high~ 8Q,IivWnI: cicuI of ~ ampIiIer, incfudIng the Miler capac:i;Ianoe

Chapter 7 Frequency Response

We determine the midband voltage gain magnitude by assuming C~ and eM are open circuits. We find that

IAvlM = j yp.1 = g",R~[ RBlr,. ] (7.103)

1ViM RBlr .... +Rs

The Bode plot of the high-frequency voltage gain magnitude is shown in Figure 7.49,


[,1 f Figure 7.41 Bode pk:Jt 01 !he hfgtr.frequency voltage gain magnitude tor !he oommOll-ooJilter ~Iifier

Example 7.14 Olllecttn: Determine the upper corner fre<juenC)' and midband gain of a common-emitter circuit.

For the circuit in Figure 7.47, the parameters are; V+ ;;;;;; S V. v- = - 5 V, Rs "" 0.1 ln, R, = 4OH1. R2= 5.12kQ, R£ = IlSkO, Rc = 5kn. aod h "" JOkQ- The transistor parameters are: fl ;;;:; 150, VBf(on} = 0.7 V, V" "'- 00, C'/f ;:;; 35 pF, and CJiI = 4pF,

Sohrtloa: From a de analysis, we find Ihai 'co= 1.02mA_ The small-signal parameters are therefore

r". == fl V T = (1 SO)(O.()26} :::: 3.S21dl

Ico 1m


Iq! 1.02

}{m = V~ "" 0.026 :;;;;: 39.2 rnA/V

The Miller capacitance is then

CM;:;; C~(1 +g",R;_)~ CIt!t +g",(RcIIRdl


eM =:: (4)[J + (39.2)(51110)] ~ 5271'F and the upper Jd8 frequency is therefore

. I

III = -"-----,,.-----------~

. 2:rr[r"IR,'iIlR.dK,.+CMl



(1/ ;;;;;. 2.96 MHI

Finally, the midband gain is

,[ RllWr,; ]

IA"I,II "" g",RL RBHI''/f + s,

_ :I 0 [ 40115.nIl3.S2 ]

-(.9.2)(51IL ) 40115,72113,82+0-'


Commlilnl.: This example demonstrates (he importance of the Miller effect, The feedback capacitance C", is mUlti.plied by a factor or 132 (from 4 pF to 527 pF), and the resulting Miller capacitance eM is approximately 15 times larger than C'/f' The actual

Part I Semiconductor Devices alld Basic Application>

Comer frequency is therefore approximately IS times smaller than it would be if CIJ. were neglected.

PSpIce V.rNlcatlon: , Figure 7.50 Shows the results of'a PSpice analysis of this commonemitter circuit The computer values are: C" ;;:; 35.5 pF and C" = 3.89 pF.. The curve marked "ell only" is the circuit fre-quency response if C I' is neglected; the curve marked "C", and CIJ. only" is the response due to c~, CI" and the Miller effect There curves illustrate that the bandwidth of this circuit is drastically reduced by the Miller effect.

IAvl 200

Figure 7.SO PSpice analysis results for common-emitter ampli~er

The corner frequency is appmrimately 2.5 MHz and the midband gain is \25, which agree very well with the hand analysis results,

The curves marked "e!.. = 5pF" and "CL = ISOpF" show the circuit response if the transistor is ideal, with zero C2 and elf capacitances and a load capacitance connecred to the output- These results show (hat, for CL ;: 5pF, the circuit response is dominated by the Cp: and C~ capacitances of the transistor. However, if II large load capacitance, such as CL "". ISO pF, is connected to the output, the circuit response is dominated by the CL capacitance.

The high-frequency response of the common-source circuit is similar to that of the common-emitter circuit, and the discussion and conclusions are the same. Capacitance ell is replaced by CgJ, and CIL is replaced by Crd. The highfrequency small-signal equivalent circuit of the FET is then essentially identical to that of the bipolar transistor.

7_6_2 Commo~Base. Common-Gate,snd Cascode Circuits

As we have just seen, the bandwidth of thecommon-emitter and commonsource circuits is reduced by the Miller effect. To increase the bandwidth, the Miller effect, or the C IJ. multiplication factor. must be minimized or elimina ted. The common-base and common-gate amplifier configurations achieve this result. We will analyze a common-base circuit: the analysis is the same for the common-gate circuit.

Chapter 7 Freqeency Response

Common-Bsse Circuit

Figure 7.51 shows a common-base circuit The circuit configuration is the same as the common-emitter circuit considered previously. except a bypass capacitor is added to the base and the input is capacitively coupled to the emitter.



Flgur.7.51 Commoo·base amplifier

Figure 7.S2(a} shows the high-frequency equivalent circuit, with the coupling and bypass capacitors replaced by short circuits. Resistors RI and Rl are then effectively short circuited. Also, resistance ,.~ IS assumed to' be infinite. Capacitance C J1.which led to' the multiplication effect. is no longer between the input and output terminals. One side of capacitor CIJ is tied to signal ground.

Writing a KCL equation at the emitter, we find that

f Y VII" V;r - 0

e + gm Jt + (l/sC}1") + rll" _.


Since V". = -V ... Equation (7.104) becomes

t, 1 1

--:- = - = - + gm + sCI( Vi Z, r"

(7. lOS)

where Z, is the impedance looking into the emitter. Rearranging terms, we have


The equivalent input portion of the circuit is shown in Figure 7.S2(b).

Figure 7.52(c) shows the equivalent output portion of the circuit. Again, one side of Cp. is tied to ground. which eliminates the reedback or Miller multiplication effect. We then. expect the upper 3 dB frequency to be larger than that observed in the common-emitter configuration.

Panl Semiwnd~to( Devtces and Basic Apphcauors

Ro- ZI I
I +
v· R£ I.I< .. -\J~ r ~ Cit
, 1+/1
(b) ® C~
lilt To: (.)


Figure 1.52 {a) High-ffequeMcy oommcn-base EiQ,Jivalenl circUit, (b) equivalefltinput drcuit, and Ie). eQUiValent OUlput circuit

For the input portion of the circuit, the upper 3dB frequency is given by


where the time constant IS


ln the hand analysis, we assume thai Cz. is an open circuit Capacitance C" will also produce an upper 3dB frequency, given by

(7. I (I8{a))

where the time constant is

Tpjt ;::;:; [RcllRLl . c"

If CjI. is much smaller than C". we would expect the 3dB frequency [Hlf due to err to dominate the high-frequency response. However, the factor '11/(1 + (J) in the lime constant Th is small; therefore, the two time constants may be the same order of magnitude.

Exarnple 7.15 OtIjd".: Determine the upper corner frequencies and midband gain of a common-base circuit

COil sider the circuit shown ill Figure 7.5[ with circun parameters V"" = 5 V. y- ;;:: -$ V, R.s;;;;;; 0.1 kf.!. RI = 4OtQ, R2 = S.12kQ, Rf ""- 0.:5 kO, Rc = 5 kO, and RL "" IOUl (These art the same values as those used for the common-emitter circuit in Example 1.14.) The transistor parameters ate: fJ = I SiO, V 8E(on) = 0.7 V, VA = 00. C~ = J:SpF. and C,. = 4pF.

Solution; The de analysis is the same as In Example 1.14; therefore, (tQ"" I.02mA, gm = 39.2mA/V, andr, ~ 3.82 kQ. The time constant associated wilh e" is

tr~ = [C ~ ,6)IIRE~~Rs J . c,

= [c·:nl((O.5)U(O.!)] x 103(35 x Io-I~)


tp-,.;O O.619ns

The upper 3 dB frequency corresponding to ell' is therefore

jll.- = 2Jr~PR= 2H(O.6?~ )( 11)-9) ~ 234 MHz

The lime constant associated with ell in the output portion of Ihe circuit is ff'u ::::: IRcllRd . CI' = [SliIO] x 101(4 )( IO-I~} ~ I:U ns

The upper J dB frequency corresponding to Cp. is therefore


[" = _. ~ ~. .. 9 =} 12.0 MHz

• rUt 2'1Ur,. br(13.J x 10- )

So in this case, fHl' is tile dominant pole frequencj.

The ma~liitude of the midband voltage gain is

[ O,51(~) 1 .

= (~9.2)(51110) ~(3.82) ;;: 25.3

051 TIT +0.1

Cornment:The result. of this example show that the bandwidth of the common-base circuit is limited by the capacitance CIt ill the output portion of the circuit, The bandwidth of this particular circuit is 12 MHz, which is approximately a factor of four greater tban the bandwidth of the common-emitter circuit in Example 7.14.

Compute, Verllk:~[on: Figure 7.53 shows the results of a PSpice analysis of the common-base circuit. The computer values' are ell' = 35.SpF and C~ = 3.89pF, which are the same as those in Example 7,14, The curve' marked "C,. only" is [be circlJi[ frequency response if C p is neglected, The curve marked "ell and C IJ only" includes the elT ect of both C" a nd ell-. As t be hand analysis predicted. C,. dominates the ~imlit biihfrequency response.

Pari , Semiconductor Devices and BasLc Applications

Rg\lre 7.53 PSplc9 analysis reSults tor common-base drcuit

The comet frequency is approximately 13.5 MHz and the midband gain is 255, both of which agree very well with the hand analysis results,

The curves marked ·'C L = 5 pF'; and "C L = 150 pF" art the circuit response if the transistor is ideal and only a load capacitance is included. These results again show that if a load capacitance of CL ;;;;;; l50pF were connected to the output, the circuit response would be dominated by this capacitance. However. if a 5 pF load capacitor were connected to the output, the circuit response would be a function of both the CL and C., capacitances, since the two response characteristics are almostidenucal.

Cascode CircuIt

The cascode circuit. as shown in Figure 7.54, combines the advantages of the common-emitter and common-base circuits. The input signal is applied to the common-emitter circuit (01)' and the output signal from the common emitter



Chapter 7 Frequency Response


is fed into thecommon-base circuit (Qz), The input impedance to the commonemitter circuit (Q.) is relatively huge, and the load resistance seen by QI is the input impedance to the emitter of Q2and is fairly small The low output resistance seen by QI reduces the Miller multiplication factor on elL I and therefore extends the bandwidth of the circuit

Figure 7.S5(a) shows the high-frequency small-signal equivalent circuit.

The coupling and bypass capacitors are eq uivalent to short circuits, and resistance r ~ for Q2 is assumed to be infinite,

The input impedance to the emitter of Q2 is Z,..2- From Equation (7.1 06) in OUr previous analysis, we have

Z~l = cr~2fi)IIC:~J


The input portion of the small-signal equivalent ci rcuit can be transformed to that shown in Figure 7.55(b). The input impedance Zr~2 is again shown.

Cpl ®
lis ® C~l
<- @ -
RDI~· V;II'I r~1 r,,1
R111RJ -
Rs ('P:l Z;'l t
vr2 "K2 c1l2
V; "'." rlfl C,,-2
C~, C~'II
(C:) Figure 7.55 (a) Htgh-lreQuency equivalent Citeuit 01 Casood& configufBtioo, (b) refltlT8l1}9d tI!gh·~requency eq.Uvaient dfeuit, and (e) variation of the Iigh·treq.;ancy cireuit,. InctudIng the Miller Clp8¢itance

Part I Semiconductor Devices and Basic Applications

The input portion of the circuit shown in Figure 7.55(b) can be transformed to that given in Figure 7.55(c), which shows the Miller capacitance. The Miller capacitance eMI is included in the input. and capacitance Cpl is illcluded in the output portion of the Q 1 model. The possibility of including ellin the output circuit was discussed previously.

In the center of this equivalent circuit, r "I is in parallel with t 112/0 + fl).

Since rol is usually large, it can be approximated as an open circuit. The Miller capacitance IS then

eM! = C,,! [I +gml (/~2,6)] (1. no)

Transistors QI and Q2 are biased with essentially the same current; therefore,

rill ~ '.2 and gml = gm2


gml'rr2 = IJ which yields

eMI ~ 2 C"I (7.111)

Equation (1. Ill) shows that this cascode circuit greatly reduces the Miller multiplication factor.

The time constant related to C:rrl involves resistance r Jld(l + Pl. Since this resistance issmall, the time constant is small, and the corner frequency related to C1l! is very large. We can therefore neglect the effects of C,.I and C:rr2 in the center portion of the circuit.

The time constant for the input portion of the circuit is

Tf1f = (Rs~IRBdlr!lI]{C"-1 + eM\) (7.112(.))

where eMI = 2e"I' The corresponding 3 dB frequency is

1 INn = 21rth


Assuming C[ acts as an open circuit, the time constant of the: {)uIPUI portion of the circuit. from Figure 7.55. is

Tp/l. = [RcIlRd(C142) (7.113{II))

lind the corresponding corner frequency is

1 fHiJ = 2:rrrpJl


To determine the midband voltage gain we assume that all capacitances in the circuit in Figure 7.55(c) are open circuits. The output voltage is then

V" = -gil'll V1lz(R('IIRrJ (7.114)


(7. US)

Weo can neglect the eff ec I or r 0 j com paled to r IldO + fJ). A Iso, SJDce g I1d r 112 = P. Equation (7.115) becomes


and, from the input portion of the circuit,

I( _ RBI 11,,... V

~ Ifl ~ X j

R81llr,.., + Rs

Finally, combining equations, we find the midbaad voltage gain is

v~ [ RB.llr... ]

A.M = ~v. = -gml(RcHRL) R II + R

, HI '... S



If we compare Equation (7.118) to Equation (7.103) for the common-emitter circuit, we see that the expression for tbe midband gain oftbe cascode circuit is identical to that of the common-emitter circuit. The cascode circuit achieves a relatively large voltage gain. while extending the bandwidth.

Example 7.16 ObttcUv.: Determine the 348 frequencies and midband gain of a cascode circuit.

F or the circuit in Figure 7.S", the parameters are: V+ ~ 10 V. V- = -10 V.

Rs=O.lkn, RI =4l.5kO. R2=,-20.H:n. R3=18.3k.!2. Rc=5.4kO, Rc=5kQ, Rl. = IOkU. and CL = O. The transistor parameters are: P = ISO. VSE(on) = O.7Y, VA ='- CO, C, "'" 35pF. and C", = 4pF. '

Solution: Since f3 is large for each transistor. the quiescent collector current is essentially the same in each transistor and is I("Q =1.02 mAo The small-signal parameters are: f,,\ = r .. 2 -= rll = 3.82kn and gml = gm2 ... gm = 39.2mAJV.

From Equation (1.1 12(a)), the time consant related to the input portion of the circuit is

. TpJl = (R~.-"R81 AI"d(C>l1 + CUI)

Since Rf!1 ~ R211 R~ and eMI = 2CI'io then

11'" = [(O.I)1120JII28.3!}.&21)( 103(35 + 2(4)1)( 10-12 ~ 4.J6ns The corresponding 3dB frequency is

1 [

in" = brrp" :;:: 2n(4.16 x 10-9') ~ 38.3 MHz

From Equation (7.'1 J(a)), the time constant or the output portion of the circuit is fPI' = IRclIRdC.u2 = [51110] x [Q\4 x IO-n) ~ B3ns

and the corresponding 3 dB frequency is


fill' = 2nrpl' = 211'(13.3 !( 10-9) => 12 MHz

From Equation (7. t IS), the midband voltage gain is

. . [RBI~r". ]

~A.l,w = Kml(Rd RL) R'111/". + Rs

[ (20.5K28.3113.82) ]

= (39.2)(51110) (20.5 R28JII3.82) + (0.1) = I 26

Comment: As was the cue for tile common-base circuit, the 3 dB frequency Ior the cascode circuit is determined by capacitance Cp in the output slase. The bandwidth of the cascode circuit is 12 Mt; compared to appro:llimateJy 3 M Hz for the common-emitter circuit. The midbaod vol. gains for the two circuibl are essentially tbe same.

Part I SelnicondoclOT Devices and BasK: Applications

Con'Ipvter Verlftcatlon: Figure 7,56 shows the results of a PSl'ice analysis of the cascode circuit From the hand anal~is, the two comer frequencies are 11 Mz and. 38.3 MHz. Since these frequencies are fairly close, we expect the actual response to show the effects of both capacitances. This hypothesis is verified and demonstrated in the computer analysis results. The curves marked "en only" and "C, and CI' only" are fairly dose together, and their slopes ale steeper than -6dBfoctave, which shows thaI more than one capacitor is involved ill the response. At a frequency ofl2 MHz, the response curve is 3 dB below the maximum asymptotic gain, and the midband gain is

120. These values closely agree with the band analysis results.

The curves marked "CL= 5pP" and "CL = ISOpF" show the circuit response if tbe transistor is ideal and only a load capacitance is included.

Flgu,. 7.ti' PSpiCe analysis resutts lor cascode ci~uit

7.6.3 Emlner .. a.nd Sourc .. Foliower Circuits

In thi s seen on. we analyze the high- frequency res po nse 0 f the emi tter follower. We will analyze the same basic circuit configuration thai we have considered previously. The results and discussions also apply to the source follower.

Figure 7.57 shows anemater-foflower circuit with the output signal at the emitter capacitively coupled to a load. Figure i .58(a) shows the high-freq uency

Cha~ter 7 Freqllency Respome

small-signal equivalent circuit, with the coupling capacitors acting effectively as short circuits.

We will rearrange the circuit so tha.t we can gain a better insight into the circuit behavior. We see that C,.. is tied to ground potential and also that r, is in parallel with Rf; and RL• We may define

R;~ = R ... JRr.llr,)

In this analysis we neglect the effect of CL' Figure 7.S8(b) shows a rearrangement of the circuit.

-I fb ...

v~ r"





Flgur. 7.51 (a) Hi!jl-freqvency ~ circuit of errWtte r followef. (b) 188rT8nged highfrtqUeflcy equivalent circuit. and (e~ high-frequenCy equivalent cifCUil with effective input base impedance

We can find the impedance Z; looking into the base without capacitance C". The curren I I; entering the parallel combination of r 1r and elf is the same as that coming out of the combination. The output voltage is then




Pan I &:mtwndllClQr Devices and Basic Applicauons

Voltage VII is given by

V _ I;





y" = (l/r,.,) + se" Voltage Vh is

Vb = Y" + Va Therefore,

I Vh Vir + Vo

z; = fi = t;

b "

Combining Equations (1.119), (1.120), and (7-121), we obtain

Z' I R' gmR~ ,,=-+ L+--

y,. y,,-





Substituting the expression for YIf' we find

z; = I 1 x (1 +gmRiJ+ R[




This can then be written as

z; = 1 se" + Ri.

'.It{l + g",R[)+ (l + g"'lRi) Impedance zit is shewn in the equivalent Circuit in figure 7 .58( c).

Equation (7.123(b» shows that the effect of capacitance e" is reduced in the eminer-follower configuration.

Since the emiuer-Iollower circuit has a zero and two poles, a detailed analysis or the circuit is very tedious. From Equations (7,119) and (7.120), we have

(7 .I 23(1l) )


which yields a zero when y,. + gm = O. Using the definition of YIf' the zero occurs at

_ 1

Jo = (,)

2trCJ{ I; p

Since '!!/(l + fJ) is small, frequency 10 is usually very high.

If we make a simplifying assumption. we can determine an approximate value of one pole, In maay applications. the impedance of ~J{(l + g/>jRl.) in·


Chapter i FJequelK)' Response

parallel with C"J( I + gmRiJ is large compared to R~ If we neglect R~, then the time constant is

(7.1 16(a))

and the 3 dB frequency (or pole) is I

l« =: -.-



Example 7.17 OblKtlfe: Determine the: frequency of a zero and a pole in the high-frequency response of an emitter follower.

Consider the emirter-Iollower circuit in Figure 7.57 with parameters V+ = 5 V, V-; -5 V, RS' == 0.1 kQ, RJ = 4010, RJ = 5_72kQ, Rr. = O.5kfl:, and RL = lOUt The transistor parameters are: ~ = ISO, V tll;(on) = 0.7 V, VA"" 00, Cjj = 3-S pF, and C!J;;;;;;4pF.

SOlution: A.s in previous examples, the de analysis yields ICQ =1.02 rnA. Therefore, gm ;;:;; 39.2 mA/V and r, :; 3.81

hom Equation {7-125), the zero occurs at

1 I

I.. =:;;;;;; ~ 180MHz

. , 2ncllC ~ .8) brOS x lO-n)(3,g~;1 II),)

To determine the time constant for the higb-frequency pole calculation, we know that


The time conssam is therefore

The 3 dB frequency (or pole) is then


III "'- 2"1 P = 211'(0.566)( 1O~9) => 281 MHz

CCH1iment The frequencies for the zero and the pole are very high and lire not far apart. This makes the c.aiculaliolts suspect However, since the frequencies are high, the emitter follower is a wide-bandwidth circuit.

Compoute:r 1I.,IUc;.uon: Figure 7.59 shows the results of a PSpice analysi~ of the emitter follower. From the hand analysis, the 3dB frcql.lenCy is on tbe order 1>( 281 MHz. However, the computer results show the 3dB frequcnqto be .Pfltoximately 400 MHz. We masrkeep in. mind that at these bigh frequencies., distributed parameter

Pan I Semiconductor Devices and Basic Applications


UI~ ...,_.. _ ...... _

....... '" '" (otand C~ nnl~


Figure 1.59 PSpice analysts results to! emmer follower

effects may need. to be considered in the transistor (0 more accurately predict the frequency response.

Also shown in (he figure is the frequency response due to a 150 pF load capacitaace. Comparing this result to the common-emitter circuit, for example, we see that the bandwidth of the emitter-follower circuit l~ approximately two orders of magnitude larger.

7.6.4 High-Frequency Amplifier Design

Our analysis shows that the frequency response, or the high-frequency cutoff point. of an amplifier. depends 011 the transistor used. the circuit parameters. and the amplifier configuration-

We also saw that a computer simulation is easier than a hand analysis. particularly for the eminer-fouower circuit. However, tbe 'parameters of the actual transistor used in the circuit must be used in the simulation if it is to predict the circuit frequency response accurately Also. at high frequencies, additional parasitic capacitances, such as the collector-substrate capacitance. may need to be included. This was not done in our examples. Finally, ill highfrequency amplifiers, the parasitic capacitances of the interconnect lines between the devices in an Ie may also be a factor in the overall circuit response. Your Understanding

·7.25 The transistor In the circuit in Figure 7.60 has parameters tJ = 125. Vad on) "" O.7V. VA ""- 200V, CO' = 24pF, and C" """ JpF. {a) Calculate the Miller capacitance. {b) Determine the upper 3dB] Determine the small-signal midband voltage gain, (Ans, {a) e...,·"" 155pF. (b)IH = 1.21 MHz. (c) 1,4.~ = HoJ)

·7.25 For the circuit in Figure 7.6 L the transistor parameters are: K,,= I mA/Vl. V TN = 0.8'1, )_ "" 0, ellj ;;;;;; 2 pF, and C Ira = 0.2 pF. Determine: (a] (be Millt""f capacitance. (b) tile upper 3 dB frequency, and (c) the midband voltage gain. (d) Correlate the results from parts (b) and (I;) with a computer anaJysis, (Am, (a) eM = 1.62pf, (b)/If = 3,38 MHz, (c) IA.I = 4.63)

Chapter 1 Frequency Response

+5 V


R," 2Oj(!l ..... ee .• .,

-:- 50 k:a

-5 V

-5 v

Figure 7.61 Figure for E)($cise 7.26

Flgur~ 7.60 Figure f!)f Exercise 7.25

RS: I k.U~~

\ . •

- -

- IOV-=-

Figure: 1.'2 FiglJre for Exercise 7.27

., .27 Consider the common-base circuit in Figure 7.62. The transistor parameters are d = 100. VBrfon) =Q.7V, V,.j = 00. C~ = 24pF. and Cp = JpF. (a) Determine the upper 3 dB frequencies corresponding to the input and output portions of the equivalent circuic. (b) Calculate the small-signal midband voltage gain. (Ails. (a)fH~ "" 223 MH~ fHfL ;;;;;; 58.3 MHz, (b) A .. = [).869)

·7~a8 For the circuit in Figure 7.63. the transistor parameters are' VTN = 1 V, K. "" I mAJVl. ,l" = 0, ClId = O.4pF, and eJI' = 5 pF. Perform a computer simulation to derermine the upper 3 dB frequency and the midband small-signal voltage gain; (Ans. fH = 64.5 MHz, IA.I = 0.127)

Flg ... r.,.$3 Figure for Exercise 7.28

Pan I Semiconductor Devees and Basic Applications

-7.2' The cascode circuitin Figure 7.54 has parameters v+ = 12 V, Y- = 0, RI = 58.8 kO, Rz = 33.3 kO, RJ "" 7.92kQ, Rc "" 1.5 k.O, Rs = 1 kQ, RE '" 0.5 kO, and RL ~ 2kO. The transistor parameters are: /3 = 1.00. VBE(on) = O.7V, VA = 00, C. ;;;:; 24pF. and C~ = 3 pF. Let C l. be an Dpen circuit (a) Detennine the 3 dB frequencies corresponding to the input and output portions of the equivalentcircuit, (b) Calculate thesmallsignal midband voltage gain. (c) Correlate the results from parts (a) and (b) with a computer analysis. (Ans, (a)/HT!: = 1.l7MHz,fH).l = 33.6 MHz, (b) IA,.I ; 22.5)


• In this chapter, we studied the frequency response of transistor circuits. We determined tile effects due to circuit capacitors, induding coupling, bypass, and load capacitors, and also analyzed (he expanded equivalent circuits of BJTs and FETs to determine the frequency response of the transistors.

• A time constant tecbnique was developed so that Bode plots can be constructed without the need of deriving complex transfer functions. The Iligh and. low corner frequencies or J dB frequencies can be determined directly from the time constants.

• Coupling and bypass capacitors affect the low-frequency characteristics of a circuit.

In general, capacitance values in the microfarad range typically result in cutotT frequencies in the hertz or lens of hertz range. A load capacitor affects the highfrequency characteristics of a circuit. Load capacitances in the picofarad range typically result in cutoff frequencies in the vicinity of a megahertz or higher.

• An expanded hybrid-If" model fOT the bipolar transistor and ahigh-frequency model for the field-effect t ransis tor were developed. The capaci tances i acluded in there models result in reduced transistor gain at high frequencies. The cutoff frequency I!> a figure of merit for the transistor and .is defined as the frequency at which the magnitude of the current gain is unily.

• The Miller effect. is a multiplication of the base-collector or gate-drain capacitance due 10 feedback between tne output and input of the transistor circuit, The bandwidth of the amplifier is reduced by this effecl.

• The common-emuter (common-source) amplifier, in general, shows the greatest effect of the Miller multiplieation factor, so the bandwidth of this circuit is the smallest of tile three basic types of amplifiers. The common-base (common-gate) amplifier has a larger bandwidth because of a smallee Miller multiplication factor. The cascode confignrarioa, a combination of commoa-emiuer and common-base stages, combines the advantages of high gain and wide bandwidth. The emitter-follower (sourcefollower) amplifier generally has the largest bandwidth of the three basic amplifier configurations.


After studying this chapter, the reader should have the ability to:

" Construct the Bode plots of the gain magnitude and phase from a transfer function written in terms of the complex frequency s. (Section 7,2)

tI Construct the Bode plots of the gain magnitude and phase of electronic am.,.ifier circuits, taking into account circuit. capacitors, using the time constant technique (Section 1.3)

r/ Determine the short-circuit current gain versus frequency or a BJT and determine the Miller capacitatl« o-f a BJT circuit using the expanded hybrid-a equivalent ciraUl. (Se¢tic:n 1.4)

._ ••••••• ' ~ •• : _ •••• ~ ' ~_ ••• H HO_ " •• ·._· _ •• _ .. _ •• __ ••• _ _ •••• , _ _ ••• _ _ ....


Chapter 7 F~quency Response

II'Determine the. unity-gain bandwidth of an. FET and determine the Mil.1er capacitance of an FET circuit using the expanded small-signal equivalent circuit. (Section 7,5)

t/ Describe the relative frequency responses of the three basic amplifier configurations and the caseode amplifier, (Section 7.6)


I. Describe the general frequency response of an amplifier and define the lowfrceuency, midband.rand high-frequency ranges.

2. Describe the general characteristics of the equivalent circuits that appJy to the low-

frequency. midband, and high-frequency ranges.

], Describe what is meant by a system transfer function ill the s-domain 4. Wha I is the criterion thai defines a COrner, or 3 dB, frequency?

S. Dehne octave and decade.

n. Describe what is meant by the phase ofthe transfer function.

7. Describe the lime constanttechnique fo, determining the corner frequencies. l( Describe ihe general frequency response of a coupling capacitor.

9. Describe the general frequency response of a bypass capacitor.

10 Describe the geaeral frequency response of a load capacitor.

II . Sketch the expanded hybrid-e model of the 8lT.

12, Describe the short-circuit current gain versus frequency characteristics of tbe 811. 13. Deline the clitoif frequency for a BiT.

14, Describe the M iller effect and [he Miller capacitance.

15. What effect does the Miller capacitance have on th-e amplifier bandwidth? Ill. Sketch the expanded small-signal equivalent circuit of a MOSFET.

17. Define the cutoff frequency for a. MOSFET.

l:-:. What is the major contribution to the Miller capacitance in a MOSFEP jo'J. Why is there no! a Miller effect in a common-base circuit?

20. Describe the configuration of a cascade amplifier,

21. Why is the bandwidth of a cascode amplifier larger. in general. than that of a simple common-emitter amplifier?

22. Why is the bandwidth of the emitter-follower amplifier the largest of the three basic BJTamplifiers?

SectIon 7.2

System Transfer Functtons

7.1 (a] Determine the voltage transfer function T(s) = ro(J)Jv;(.l'~ for the circuit shown mFigure P7.1. (b) Sketch the BOOe magnitude plot and determine the corner frequency, ,c} Determine (he time response of the circuit to an input step function of magnitude V,>),

7.2 Repeat Problem 1.1 for the circuit III Figure P7.2.

~7.3 la) Derive the voltage transfer function T(.I) ;:;:; JI.( ... )/ Vj(s) for the circuit shown ~n Figure 7.10. taking both capacitors into account. (b) Let Rs = Rp= 10 kO, Cs = 1 ~F, and Cp = lOpF. Calc\llate the actual magnitude of the transfer function at it = I/H27r)(Rs + Rp)C,sJ and at /" = i/{{2Jr)(RsIR,.)C,]. How do lkse magnitudes


, .... .. .. ' ";~,,,', .. '::"

. ~

:, j~;!t;;:Hlj~

::'~ ~~E ~~:f..~iH~~, ~{3\ .. ::':t,¥r5r~~



, , ,::;',yr,"'~ :,':L'?:;:'


: : -,



Pan I Semiconductor Devices ami Basic Applications

compare to the maximum magnitude of Rp/(Rs + Rp)? [c) Repeat part (b) for Rs ;;;;;; Rp = 10kO: and c.'i' = C,. = OJ I.lF.

7.4 (a) For the two circuits in Figure PH. sketch the Bode magnitude plo~ and Bode phase plot of the voltage transfer function. (b) Verify the results of part {a) with a computer simulation.

RI '" to ill
R.= lOW
1'; VQ
Vi V.
R2'"'WkU R1=20W C2=IO,u~
-:- -:-
(a) (b)
.I, Cp FlgureP7,S

7.5 Consider the circuit in Figure PI.5 with a signal current source. The circuit parameters ate Ri "" 30 kil, Rr = to ill, Cs "= lO 1.1 F, and C r ;;;: 5[) pF~ (a) Determine the open-cilcuit lime constant associated with Cs and the short-circuit time constant associated with C" (b) Determine the corner frequencies and the magnitude of the transfer function T(s) = V<)(s)/ ] .. (5) at. midband. (0::) Sketch the Bode magnitude plot

7.1 A voltage transfer funcuon is given by TUn = 1/( 1 + j21f/d. [a) Show that the actual response all"" 1/(l1fr) is approximately -6 dB below the maximum value. What is the phase angle at this frequency? (b) What is the slope of the magnitude plot for f» l/(2lrr)? What i.s tbe phase allgie in this frequency range?

7.7 Sketch the Bode magnitude plots for the following functions;


(a) T(s) = ($ + 20}(s + 2000)

(b) n~);;;;- 10(s + IO} (s+ 1000)


7,8 Consider the circuit shown in. Figure 7.15 with parameters Rs ;;;0.5 H2, rJr = 5.2 kQ, g", = 29 mA(V, and RL'''=' 6 kn. The corner frequencies are II = 30 Hz and fH = 480 kHz (a) Calculate the midband voltage gain. (b) What are the o pen-circui I and short-circuit lime constants? (c) Determine Cc and c..

7,' For the circuit shown in Figure P7 .9, the parameters are: RJ ""'. 10 kO, R2 = 10 kO, R;! = 4OkO, and C= IOpF, Us,io, a computer slmulatiOIl, plot the magnitude and Jlbase of the vc!.tage transfer fundian. FMD the computer analysis, determine the

Cbapter 1 Freqeeney Response

frequency at which the magnitude of the voltage transfer function is 3 dB below the

maximum asymptotic value. .

1.10 The circuit shown in Figure 7.10 has parameters Rs ~ 1 kO, Rl'= IOkO, and Cs ;. Cp ~ 0.01 I1F. Usil\g PSpice, plot the magnitude and phase oflhe voltage transfer function. Determine the maximum value of the voltage transfer function. Determine the frequencies at which the magnitude IS 1/./2 of the peak value.

Section 7.3

Frequency .Response: Transistor Circuits

7.11 For the common-emitter circuu in Figure P7, 11. the transistor parameters are: fJ = 100. V9E(Qn) = O.7V, and VA = 00. (a) Calculate the lowe. corner frequency. (b) Determine the midband voltage gain. (c) Sketch the Bode plot of the voltage gain magnitude.

Figure P7.t1

07.1:2 Design the circuit shown in Figure P7.12 such that f DQ "" O.5mA. V DSQ= 4 .. 5 V. R~= 200 kQ. and the lower comer frequency is!L == 20Hz. The transistor parameters are: KM ;;;; 0,2 mA/V!, V TN '= J .5 V. and ). = O. Sketch the Bode plot of the voltage magnitude and phase.

D7.13 The transistor in the circuit in Figure P7.13 has parameters KII = 0.5mA/V2, V-m= 1 V, and)" =0. (a) Design the circuit such that IDQ= ImA and VDS{! =.)V.

+l V

-5 V


Pari I Semiconductor Devices and Basic Applications

(b) Derive the expression for the transfer function T(s) ;;;;;; /(J(s)j VM). What is the expression for the circuit time constant? (c) Determine C{- such that tile lower J dB frequency IS 10 Hz. l~) Verify the results of p-arts (a) and (c) with a computer simulation.

TD7.1.c The transistor ill the circuit in Figure P1_14 has parameters Kp :;:;; 0.5 rnA/V!, VTi> = -2 Vi and A = O. (a) Determine R"" (b) What is the-expression for the circuit time constant? (c) Determine Ct;:' such lhat the lower 3dB frequency is 20 Hz,




, . .----t;.


~ -9V


figure P7.14

Figure '7. '5

·D7.15 For the circuit in figure PJ.15, the transistor parameters are: {J "" 120. VBf(OO):;;;;;;O.7V; and, Vtf""SOV (a) Dt:sign a bias-stable circuit such that iCQ"'- 11llA. (b) Determine the output resistance R". (e) What is the lower 3 dB corner frequency?

7.16 The parameters of the transistor in the circuit in Figure P1.16 are Kp = I rnA/V2. I/TI';;;;;; -1.5V. and A = O. (a) Determine the quiescent and small-signal para meters or the transistor. (b) Find the time constants associated with en and en. (c) Is there a dominant pole [requency? Estimate the ~3dB frequency.

ItS "- 200 Q

Cn'" 4,7 i-iF

=r s v '"




"'07.1T A MOSFETamplifier with the configuration '" Figure P7.l7 is to be designed [Of lise in a telephone circuit. The magnitude of the voltage gain should be to in tbe midband range, and the midband frequency range sllould extend from 200 Hz III J kHz. (Note: A telephone's frequency range does not correspond to a high-fideiity system's} All resistor, capacitor, and MOSFEI parameters should be specified.

Chapter 1 fl"1Xfuency Response

1', O--'WV\r- ...... -~ 1'0

C"'100PF1 Figure P7.1'


"1.18 Consider the circuit in Figure P1.'S. (a) Derive the expression for the voltage transfer function T(s):;; V,,(.o:)/VM). Arrange the terms in the form T(~l Q; (I + Sf" )/( I + st"B)' (b) Sketch the Bode magnitude plot: (c) Determine the lime constants and cornu frequencies.

1.1' The circuit in Figure P7J9 is a simple output stage of an audio amplifier. The transistor parameters are f3 :: 200, V 8£(on) =:: (t.7 \I, and V_., ;;: 00. Determine Cc such ,hat the lower -3<18 frequency is 15 Hz.

v+~ lOY


ItB ~ 430 W


F)gure P7.20

D7.20 The parameters of the transistor in Ihe circuit in Figure P1.20 are {f = 100, Vu(on) ""O.7Y, and VA ""00. The time constant associated withCn is a factor of 100 larger than the time constant associated with en. (a) Determine eel su~h that. the -3dB frequency associated wtth this capacitor is 25Ht. (b) Determine eel.

-07.21 For the transistor in the circuit in Figure M.21. tbe parameters are: 1<." '"

O.5mA/V", VT,',I = 0.8 V, and ;I, ~ 0. (a) Design the circuit such that !()Q = O.5IllA and V DS{>=" 4 v. (b) Determine the "3 dB frequencies. (c} If the Rs resistor is replaced by a constant-current source producing the same TDQ quiescent current, determine the 3 dB corner frequencies,

Part I Semiconductor Devices and Basic ApplicllllQnS


-5V Figure P7.21


Figure P7 .23

*7.22 For the circuit in Figure 7,23(a) in the text, the parameters ate: V'" = lOY. v- =: ~ 10 V. Rs ~ O. RF; ~ 5 ka, andRe =- 1.5 to" The transistor parameters are V BE(on} ::: 0.7 V and VA = 00, and the transistor current gain fJ is in the range 75 :=; fj ::; 125. (a) Determine the value of CE such that the low-frequency 3dB point is [» $ 200 Hz. (b ) From the results of part (a). determ ine t he tau ge infreq ueacies It and fA'

~.23 The common-emitrer circuit in Figure PJ.23 has an emitter bypass capacitor. (8) Derive the expression for the small-signal voltage gain A~(s) = J~~(J)I V;(s). Write the erpression in a form simi 1M to tllM of Equatioll (7. 59}. (b) What ate the expressions for the time constaais T_A and t8~

7.24 In the common-base circuit in Figure 7,29 in the text, the transislor parameters are: (3 = 100, VES(on) = 0.1 V, and V~ = 00. A load capacitance CL = 15 pF is connected in parallel with R/.. Determine the upper 3 dB frequency and the small-signal midband voltage gain.

7.25 For the circuit in Figure P7.2S, the transistor parameters are; K~= a.5mA/V!, V TN = 2 V, and 1= O. Determine the maximum value of C L such thatthe bandwidth is at least BW = 5 MHz. State any approximations or assumptions that you make. WMC is the: magnitude of the small-signal midband voltage gain? Verify theresults with a computer simulation.

R~'" 41:0

Figure P7.25

Figure P7.28

-6'1 FtgureP7.29

Chapter 7 Frequeocy Response

7.26 The parameters of the transistor in the circuit in Figure P7.26 are fJ;::;; loo, VSE(on)"" O. 7V. and VA = 00. NegJect the: capacitance effects ()f the transistor. (a) Draw the three equivalent circuits that represent the amplifier in the low-frequency range, midband range, and the high frequency range. (b) Sketch the BOOe magnitude plot {c) Determine the value. of IA""I.:IB.fL' and/n.

R[= soo til

Figure '1.26


7 :27 In tbe eornrnen -sQIJ rce amplifier in Pi gure 7 .20( a) I [] the text, a source bypass capacitor is 10 be added between the source terminal and ground potential. The circuit and transistor parameters are 85 described in EK.alilple 7,6, (a) Derive the small·signal voltage gain expression, as a function of s, that describes the circuit behavior in the highfrequency range. (b] Whal is the expression fOT the time constant associated with the upper 3 dB frequency? (c) Determine the time constant, upper ~ db frequency, and small-signal midband voltage gain,

*7.28 Consider the common-base ci.['(:uit in Figure P7.28. Choose appropriate transistot parameters, (a) Using a computer analysis, generate the Bode plot of (he voltage gain rnagnirude from a very low frequency to the midband frequency range. At what frequency is the voltage gain magnitude 3 dB below the maximum value?" What is the slope of the curve at very low frequencies? (b) Using the {tSpi.ce analysis, determine the voltage gain magnitude, input resistance Ri• and output resistance R~ at midband.

·7.2' For the common-emitter circuit in Figure P7.29, choose appropriate transistor parameters and perform. a computer allllysis, Geaerateu.c Bode plot of the voltage gain

Pa.Il I SemioondUClor Devices and Basic Apphcauons

magnitude from a very low frequency to the midband frequency range. At what frequency is (he voltage gain magnitude 3dH below the maximum value? Docs one Capacitor dominate this 3 dB frequency? If so, which one?

"7.30 For the multitransisl()t" amplifier in Figure PUV, choose appropriate transistor parameters. The lower J dB frequency is to be less than or equal 10 20 Hz. Assume that all three coupling capacitors are equal. Let CB _ 00. Using a eomputer analysis, determine the maximum values of the coupling capacitors. Determine the slope of the BOOt: plot of (he voltage gain magnitude at very low frequencies.




Ra= 1:Z kl1

Figure P7.30


Frequency Response: Bipolar Transistor

1.31 A bipolar transistor is biased at lCQ = I rnA and bas parameters C~ = IOpF, CI-I = 2 pF, and flo = 120. Determine f.s and [r-

T.32 A high-frequency bipolar transistor is biased at lCQ "" 0.5 rnA and has parameters CI-I = {U5pF,jr "" 5GHz. and ~(J = 150. Determine C~ alldflJ·

T.33 For a bipolar IransisLOor, tbe unity-gain bandwidth ish = 2GHz and the lowfrequem;y current gain is Pc"" ISO. (a) Detenninefp. [b] Find the frequency at which (he magnitude ·of lifo is 1(1. The circuit in figure P7.34 is a hybrid-)!' equlvaJent circuit including the resislance 'tJ' (a) Derive the expression for the voltage gain transfer function A.(.'l) "" Vc(s)/Vi(s). (b) If the transistor is biased at ICQ = I mA, and if RL = 4kO and iJQ ;: 100, determine the midband voltage gain for (i) rs= 100 Q and (ii] 'h= 500 11. {c) For C1 = 2.2pF. determine (he -3dB frequency for (1) rs= 1000 and (ii)

r" = 5000.


4S9 Ki'p,<;;;:~~u,;;

r~]:~:'~i ~ .... . ".:'

.. -.;~:;...:;... ,'.~,


n~~·tr:::·: ;~/!:/'.'

:":;'"":-1 : ~.:;..:: ~ ~ : :'

·1,35 A common-emitter equivalent circuit is shown ill Figure Pl.35, (a) What is the expression for the Miller capacitance? (b) Derive the expression for the voltage gain A • .(s) = V,,(s)/Vj(.r) in tenus of the Miller capacitance and other circuit parameters. (c) Wh,lt is the expression for the upper 3 dB frequency?

Figure P7.35

7.36 For I he common-emitter circuit in Figure 7.37(a) in the text, assume that T_. == 00, R dl Rz= 5 kn, and Rc ;;;;;; RL = I kn. The transistor is biased at f CQ = 5 rnA and the parameters are: flo ;;;;;; 200, V,..;;;;;; 00, C" = 5 pf', and Ir 0:= 250 MHz, Determine the upper J dB frequency for the small-signal currentgain.

figure P7.37

*7.37 For the common-emitter circuit in Figure P1.31, assume the emitter bypass cepacuor Cf is very large. and the transistor parameters are: ~,,= tOO. V,,;(on) = 0.7 V. V., :;;: 00, Cj.< ~ 1 pF, and h= 400 MHz. Determine the tower and upper 3 dB frequencies for the small-signal voltage gain, Use the simplified bybrid-;rr model for the transistor.

Section 7.5

Frequency Response: The fET

7.38 A MOSFET is biased at /DQ ~ tOO !lA, and the parameters are: H)1l"C".~ = IS I1A/V2, W;::; 40j.Lm, L= lOflm, eg• =OJpL and CgiJ = O.OSpF.. Determine jj-,

7.3& A common-source equivalent drcuitis shown in Figure P7.39. The transistor rransconductance is gilt = 3 mA/V. (a} Calculate [be equivalmt Miller capacitance. (b) Determine the uper 3 dB frequency for the small-signal vohage gain.

Part 1 Semiconductor Device, and Basic Applic.ations

;,,- ill) =

15 til III k!l

Figure P7.39

7.40 Starting with the definition of unity-gain frequency, as given by Equation (7.90 •. neglect: the overlap capacitance, assume CgJ ~ 0 and Cgs 2!: m WLCo" and show thai

Since Tn is proportional to W, this relationship indicates that to increaseh.lhechannel length L must be small.

7.41 For an ideal n-channel MOSFET, (W /L) = 10. JJ.~ = 400cm2 /V-s, eM;;;;; 7.25 x IO-S F jcm1, and VTtI= 0.65 v. (Ill Determine the maximum source resistance such that the transconductance gm is reduced by no more than 2(1 percent from its ideal value when V(iS "" 5 V . (b) Using the value of rl calculated in part (a), determine how much g," is reduced from its ideal value when Vas ~ 3 V.

"'1.42 Figure P?42 shows the high-frequency equivalent circuit of an FET.lndud~ng <I source resistance 'r (a) Derive an expression for thelow-frequency current gain Ai ~J~jli' (b) Assuming R; is very large. derive an expression for the current gain transfer function AI(s) = l o (s)/I,{s). [c] How does the magnitude of tile current gain behave as r. increases?

I'· r

FIQure PT.oil


7.43 For the FET circuit in Figure P7.43. the transistor parameters are: K,,:::;;; I mA/V2, V Tf'J :0 2 V, ?> = 0, Cr. = 5pF. and C~d :::;;: I pF. (a) Draw the simplified high-frequency equivalent circuit. (b) Calculate the equivalent Miller capacitance. (c) Determine the upper 3dB frequency for the small-signal voltage gain and find the midband voltase gain.

Chapter 7 Fnxtuency Response

Flgur. P7.45

Section 7.6

High-Frequency Relponse of Translator Circuits

7~44 In the circuit in Figure P7.44, the t{ansistor parameters are: f3 "" 120, V et{on) = O.7V. v~ == lOOV. Cj.I == I pF, andJr; 6()()MHz. (a) Determine ell: and the equivalent Miller capacitance eM- Sute any approximations Or assumptions thai you make. (b) Find the upper 3dB frequency and the midband voltage gain.

+5 V


~7.45 In the circuit in Figure P1.4S, the transistor parameters are: fJ = 120, VBdcn) = 0.7 V, V ~ = 00, Cj; = 3 pF. andh = 250 MHz. Assume rhe emitter bypass capacitor CE and the coupling capacitor en are very large. (a) Determine the lower and upper 3 dB frequencies. Use the simp~fted h)'brid~l'f model for the transistor. (b) Sketch the Bode plot of the voltage gaifl magnitude.

7.46 The parameters of the transistor in the common-source circuit in Figure P7,46 are: K" = 2mA/V2, VT}' = -2 V,}., = f},Ol V-I, Cgs = U)pF. and Cf4;;:; 'pF. (a) Determine the equivalent Miller capacitance eM' (b) Find the upper 3 dB frequency and midband voltage gain.



Part 1 Semiconductor Devices and BilSic Applications

7.47 for the PMOS common-soutce circuu shown in Figure P7.47, tile transistor parameters arc: Vr»= -2V, K, = 1 mAIV2, ).,:=; 0, c,.;;o ISpF, and Cgd;;;;; 3 pF. (a) Determine the upper 3 dB frequency. (b) What is the equivalent Miller capacitance? State any assumptions Of approximations that you make. (c) Find the midband voltage gain .

.. 10 v

-to \I

Figure P7.47

.. 5 v

Figure P1.4$

·7 AI In 'be common-base circuit shown in Figure P7.48. the transistor parameters are: fJ = 100, J.i BE(on) ~ 0.7 V, V,! = 00, C I = IOpF, and CPo;;;;; I pF. (/I) Determine the upper 3dB frequencies corresponding 10 the input and output portions of the equivalent circuit. (b) Calculate the small-signal midband voltage gain. (c) If a load capacitor CL ~ 15pF is connected between the output and ground, determine if [he upper ldB frequency will be dominated by 'he CL load capacitor or by the transistor characteristics.

*7,49 Repeat Problem 7.48 for the common-base circuit In Figure P7.49. Assume V EB (on) =. 0.7 for the pnp transistor. The remaining transistor parameters are the same as given in Problem 7.4S.

FlO"'''' P1.4'

·7.$0 In ihe common-gate circuit 1(1 Figure P7.50, the transistor parameters art:

VrN = ) V, K~ = 3mA/V2, ).. = 0, C,~ = 15 pF, and Cgd ",.4pF. Determine tbe upper J dB frequency and midband voltage gain.

7.51 Con sider the comma n -gate circuit in Figure P1 51 wi th parameters V + = 5 V, V-=-5V, Rs=4kn, F.D=2kO, Rt=4kf.l. Rr;= 50k:Q, and R.=O.5tn. The transistor parameters are: Kp"'" ImA/V1, VTP=-O.sV, 1=6, Cg,=4pf, and C~ ;;;;;; I pF Determine the upper 3 dB frequency and midband vohag~ gain.

*7.52 for tho: cascode circult ill Figure 7.54 in the text, circuit parameters are the same as described in Example 7.16. The transistor parameters are: J3c = 120, VA = 00, V,£(on) = O.7V. ell = 12 pF, and CiJ = 2 pF. fa) If CL is an open circuit, determine the 3 dB frequencies corresponding to tbe inpu: and output portions of the equivalent circuit. {b) Determine tile midband voltage gain. (c) If a '(lad capacitance CL = 15 pF is connected tv the output, determine if the upper 3 dB frequency is dominated DY the load capacitance or by the transistor characteristics.


••• ' ••••• H ~ ~ ••••••••• -.~ : •• -."- •• ~ •••• _ •••••••• HW _ •••• _.· ••• ~ ·, .. _.~ _ .. P .. ,·~_ •• ~ •.,., •••• ., _. __ ._ •• - •••• ,., -.,._ •••• - ••••••••• ~ •• -- -.:.A. ~f


+5 V

~7.53 An emitter-follower circuit is sbowll in Figure P7.53. Assume the transistor parameters are: f30 = tOO, VA ~ 00, ell = 35 pF, and C,. = 4pF. From a PSpiq aulysis. determine the upper 3 dB €requency and midband vohage gain for: (a) RL = OJ kQ, (b) Rt. ;=: 2 kO, and (c) RL == 20ko. Explain an)' differences between the results,

+ [{I v


Figure P7.54

~1.54 For the source-follower circuit shown ,in Figure P7,54, assume the transstor parameters are: Vrr = -2 V, Kp = 2mA/V2, ,t = 0.02 V-I, CIf• = 5 pF, and C¥tI = 0.8 pF. From a PSpice analysis, dctennine the upper J dB frequency and midband

Part I Semiconductor Devices and Basic Applications

voltage gain for: (a) RL ::;; O.Z kr.!, (b) R[ = 2 tn. and (c) RL = 20 k!2.Explain any differences between the results.

"7,55 The emiuer-follower is a wide bandwidth circuit, but the voltage gain is slightly tess than unity. Figure P1.S5 shows <I cascade configuration of an emitter follower and a common emitter .. Investigate the possibility of obtaining the properties of wide bandwidth from the emitter follower and a large voltage gain from (he common emitter in a single circuit. Assume the traosislorparameters are identical and are: f3~.::::; I :SO. VA = 00. C~ ;;;;;: 24 pF, and C,. ~ 4 pF. Determine the upper 3 dB frequency and midband gain. How do these results compare to those of a cascode circuit?


Figure P7,55 The transistor circuit ill Figure P7.56 is a Darlington pair configuration. Assume f3~ = 100 and V ~ :::; co for each transistor, the capacitance values of Ql and Qz are identical and given bye" = 24pF and ell = 4pF. From a PSpice analysis, determine the tipper .3 dB frequency and midband voltage gain for: (a) Rtl ;;;;;; l!) kf2, (b) R£ I -=- 4Okn, and (c) Rn = 00. Explain any differences between the results.

+ tn \!


'! ;!Ow

-10 V


Chapter 1 Fl'e<:Il.Ieocy Response

'"7..S7 For the common-source circuit in Figure P7.57(a~ and the NMOS cascode circuit in Figure P7.S7(1J), all transistors have the following Identical parameters:

K,,;;;;; 1.2mAjV2, VTN = lV,A = 0, Crt;;;;; 5pF,and egl = O.8pF. From a PSpicesimula'ion Dr each circuit, determine the upper 3dB frequencies and (he midband voltage gains. Compare the 3 dB frequencies and midband. voltage gains.

(e) Figure P7 .57(.)

v+ = +IOV


Ftgu", PT.57(b)

*7.58 For the circuit in Figure P75&. the transistors are idenncal, and the parameters are: K" =4rnAjV1, VTN=2V, l=O, CgJ = lOpF, and C,d;;;;;; 2pF. The coupling capacitors are all equal al Cc = 4.1 j,LF. Using aPSpice analysis, determine the lower and upper 3 dB frequencies. What is the bandwidth and midband voltage gain? What value of load capacitance will change the bandwidth by a factor of two?

+10 V

~ rR •• an 1:.v=

I l;&'kJ}

.". ..,..

-IOV -IOV Figure P7.58


Part J Semicoeductor Devices and Baste Applicauons

[Note: Each design should be verified with a computer analysls.]

-07.59 A simplified hjgb-fretluency equivalent circuit of an FET amplifier with a source resistor Rs is shown Iii Figure P759. Including the source resistor decreases the small-signal voltage gain. IllVestiS&tt the amplifier bandwidth as a function of the source resistance to determine the trade-offs required bel .... oeen gain and. bandwidth in amplifier designs. (a) Derive an approximate single-pole expression for Ihe voltage gain A.(s) = V,,(s)/V1(s), the midband gain, and theupper 3 dB frequency. (b) Assume the circuit parameters are: R = I kn, RL = 4 tn, Crs ;;:: 5 pF, Cgd = I pF, and g", = 2 mAl V. Determine the magnitude of the midband gain and upper 3 dB frequency for Rs = 0, 100, 250, and 500 Q. (c) Plot the gain-bandwidth vetsus source resistance.

FI~ur' P1.S'

'07.60 (a) Design a common-emiuer amplifier using a 2N2222A transistor biased 31 Ic{!= I rnA and VeEQ = IOV, The available power supplies are ± 15 V, the load resislance is RL ~ 20HZ, the source resistance is Rs= 0.5 kQ, the input and output are ac coupled to the amplifier, and tbe lower 3 dB freqaeocy is to be Less than. 10 Hz- Design the circuit '0 maximize the midband gain. What is the upper 3dB frequency? (b} Repeal [he design for lco. = 50~. Assume Ir is the sallie as the case when let} = 1 rnA_ Compare the midband gain and bandwidth of the IWO designs.

·07.61 Design a bipolar amplifier with a midband gain of IA.I = 5(1 and a lower 3 dB frequency of 10 Hz. The available transistors are 2N2222A, and the available power supplies are ± 10 V_ All transistors m the circuit should be biased at approximately 0.5 rnA. The load resistance is RI. = ;5 Ul, the source resistance is R~· = 0.1 kQ, and (he input and output are 3C coupled to the amplifier. Compare the bandwidth of a single-stage design to that of a cascode design

·07.&2 A common-emitter amplifier is designed to provide a particular midband gail) and a particular bandwidth; using device A from Table P7.62. Assume ICI} = 1 mA Investigate the effect on midband gain lind bandwidth if devices Band C ale inserted Into the circuit. Which device provides the Iargest bandwidth? What is the gainbandwidth product ia each case?

TableP7.12 ()evice spmibtions for Probkm 7.62

Dflice fr (Mih) ell Ipm I '. Ul)


350 >IDO 500

2 5 2

100 100 50

IS 10 5

Chapter 7 Frequency Response

·B7.63 A simplified high-frequency equivalent circuit 0 fa common-emitter amplifier is shown in Figure P7.63. The input signal is coupled into the amplifier through Ca. the output signal is coupled to the load through eeJ, and the amplifier provides a midband gain of ~AMI and an upper 3 dB frequency OfjH. Compare this single-stage amplifier design to one in which three amplifier stages are used between the signal and load. In the three-stage amplifier, assumeall parameters are the same, except g", for each stage is one-third that or the single-stage amplifier. Compare the midband gains and the bandwidths.



: ':'

_All1plifie. $""ge--~

Figure P7 .63




Output Stages and Power Amplifiers


I n previous chapters, we dealt mainly with small-signal voltage gains, current gains, and impedance characrerisucs. In this chapter. we analyze and design circuits that deliver a specified power to a load. We will. therefore. be concerned with po w er dissipation in transistors, especially In the output stage since the output stage mU~I. deliver the signal power. Linearity in the output signal is still ;l priority, however. A figure or merit. for the output stage linearity characterist ie IS the total harmonic distortion {hat is present.

I nirially, we will look at the characteristics of power BJl5 and MOSFETs.

Such cnaracteristics indudethe current, voltage. and power ratings of these devices, a~ well as the safe operating area. The bea t generated in Ihese transistors from power dissipation must be removed in order to limit the device temperature to a specified maximum rated value. This maximum device ternperature is a function of the thermal resistance between the transistor and the ambient and determines the maximum safe operating power of the transistor,

One important aspect in (he design of power amplifiers is that I~ delivers the specified power to the load efficiently. Power amphfiers are classified according to the percent of time the output transistors are conducting, Three principal classes of power amplifiers are analyzed. In our discussion, we will determine the maximum possible conversion efficiency for each type of power amplifier.

An often-used output stage for power amplifiers, called a dass-Af circuit, uses complementary pairs of transistors. We will analyze several configurations of this type or output stage. in both BJT and MOSFET configurations. One principal goal of this chapter is that the reader will be able to understand the characteristics of a class ABoutput stage and design one to meet particular speciflcations.


A multistage amplifier may be required to deliver a large amount of power to a passive loud. This power may be in the form of a large current delivered to a relatively small load resistance such as an audio speaker, or may be in the form of a large voltage delivered to a relatively large load resistance such as in a

Pari I Semicooduclnr Devices lind &f>i~ Applkaliolls

switching power SUpply. The output stage of the power amplifier must be designed to meet tile power requirements. In this chapter, we are interested only in power amplifiers using BJTs or MOSFETS, and will not consider other types of power electronics that. for example, use thyristors.

Two important functions of the output stage are to provide a low output resistance so thai it can deliver the signal power to the load without loss of gain and to maintain linearity in the output signal. A low output resistance implies the use of emitter-follower or source-follower circuit configurations. A measure of the linearity or the output signal is the total harmollic distortion (THD). this figure of merit is the rms value of the harmonic components of the output signal. excluding the fundamental. expressed as a percentage or the fundamental,

A particular concern in the design of the output stage is to deliver {he required signal power to the load efficiently, This specification implies thai (he power dissipated in the transistors of the output stage should be as small as possible, The output transistors must be capable of delivering the required current to {he load, and musl be capable of sustaining the required output voltage.

We wiIJ initially discuss power transistors and will then consider several output stages of power amplifiers.


In our previous discussions, we have ignored any physical transistor limitations in terms of maximum current, voltage. and power. We implicitly assumed thai the transistors were capable of handling the current and voltage, and could handle the power dissipated within the transistor without suffering any damage.

However, since we are now discussing power amplifiers, we must be concerned with transistor limitations. Tbe limitations involve: maximum rated current (on the order of amperes). maximum rated voltage (on the order of 100 V), and maximum rated power (on the order of watts or lens of watts) , I We will consider these effects in 'he BJT and then in the MOSFET. The maximum power limitalion is related to the maximum allowed temperature of the transistor, which in tum is a function of the rate at which heat is removed. We will therefore briefly consider heat sinks and heat flow.

8.2.1 Power BJTs

Power transistors are large-area devices. Because of differences in geometry and doping concentrations, their properties tend to vary Crom those of the small-signal devices. Table 8.1 compares the parameters of a general-purpose small-signal BJT 10 those of two power BJTs_ The current gain is generally smaller in the power transistors, typically in (he range of 20 (0 100, and may be a strong function of collector current and temperature. Figure 8.1 shows typical current gain versus collector current characteristics for the 2N3055 power

'We mwt note that. in general. I~ madmum rated current and maximum riled voltage cannot oeeur at the 5a1lJe llmt.

Chapter 8 Output Stages and Power Amplifit;!'s


Table 8.1 Comparison m the characteristics and maximum raJings 01 a smaU-stgMI and power BJT

Sm .. II.s~nal BJT PiJowtr BJT Power
(lN1122Al (2N3055) BJT
40 60 250
0.8 IS 7
1.2 115 45
35-)(J() 520 12 10
300 0.8 I V'IO(rn.;"J (V) Idmax) IA)

PrJma\1 (Wl (at T.= 25"C) fj

[r (MHl)

..::: lOCI
.. SO
! 30
2S to . Common emitter :
ITT va 4\J
Tr-lOO~C ++ Ii f---
.- 2~ ~

t.. 5 .l

C).OI C).1n Ol OJ I 3 10 20

CoJlec1lJ'l' cumru 1(' (A)

Fig ure 8.1 TyPical de bela characteristics (hF£! versus Ie) fur 2N.3055

BIT at various temperatures. AI high current levefs, the current gain tends to drop olf significantly, and parasitic resistances in the base and collector regions may become significant. affecting the transistor terminal characteristics.

Themuimum "ted c(J.UectOt current lCral<:d may be related to: the maximum current that the wires connecting the semiconductor 10 the external terminals can handle; the collector current at which the current gain falls below a minimum specified value; or the current that leads to the maximum power dissipation when the transistor is in saturation.

The maximum voltage limitalion in a EllT is generally associated with avalanche breakdown in the reverse-biased base-collector junction. In the common-emitter configuration. the breakdown voltage mechanism also involves the transistor gain. as wen as the breakdo-wn phenomenon on the pn junction. Typical lc versus Yee characteristics are shown in Figure So2. The breakdown voltage when the base terminal is open circuited (f B = 0) is V CEO' From the data in Figure B.2. tbis value is approximately 130 V.

When the transistor is biased in the active region. the collector current begins to increase significantly before breakdown voltage V CEO is reached, and all the curves tend to merge to the same collector-emitter voltage once breakdown has occurred. The voltage at which these curves merge is denoted V C£(su~~ and is the minimum yoftage necessary to sustain the transistor in breakdown. From the data in Figure B.2. the value of V C£(.us) is approximately 1l5V.


Pan I Semiconductor Devices and Ba~IC Applicauons


~ "




] ~



Figure 8.2 Typical colletlor ClJrrent versus oollector-emitJer Vollage cnaracteristics 01 a bipolar trenseior, showing breakdown efloots

Another breakdown effect is called second breakdown. which occurs in a BJT operating at higb voltage and a fairly hlgh current Slight nonuniformines in current density produce local regions of increased heating that decreases the resistance of the semiconductor material. which in turn increases the current in those regions. This effect results in positive feedback. and the current continues [0 increase. producing a further increase in temperature. until the semiconductor material may actually melt. creating a short circuit between the collector and emitter and producing a permanent failure.

The instantaneous power dissipation in a BJT is given by


The base current is generally much smaller than the collector current; therefore. to a good approximation, the instantaneous power dissipation is


The average power. which is found by integrating Equation (8.2) over one cycle of the signal, is

1'(1 =.!. JT ~'aicdt T n

The average power dissipated in a BJT must be kept below a specified maximum value. t{l ensure that the temperature of the device remains below a maximum value. Ifwe assume that the collector current and collector-emitter voltage are de quantities. then at the maximum rated power PT for the iransis-


tor, we can write PT = Vale


The maximum current, voltage, and power lirnita tions can be illustrated on the lc versus V CE characteristics, as shown in Figure 8.3. The average power limitation Pr is a hyperbola described by Equation (8.4). The region where the transistor can be operated safely is known as the sare operating area (SOA) and is bounded by lema!' V CE~$IIS), PT. and the transistor's second breakdown

Chapter 8 Output Stages aad Power Am~lifler.s


Ma~ifl1llm currem hmit

1.01-- -....


Figure 8.3 The sal& operating area of a bipOlar transister plotted on: (a) linear scales and (b) logarithmic scales

characteristics curve, Figure 8.3(a) shows the safe operating area, using linear current and voltage scales; Figure 8J(b) shows the same characteristics using logarithmic scales,

The ic=vce operating point may move momentarily outside the safe operating area without damaging the transistor, but this depends on how far the Qpoint moves outside the area and for how long. For our purposes, we will assume that the device must remain within the safe operating it rea at all times.



Example 8.1 Ob~U": Determine the required, current, voltage, and power ratings of a power 8JT.

Consider the common-eminer circuit ill Figure 11..4. The parameters are RL = S Q and V ((' "" 24 V,

Solution: For V ce ;::,: 0, the maximum collector current is

v cc 24 Ic(max) = - =-8 = JA .RL

For Ie = O. the maximum collecior-emiuer voltage is

The 1000Id line is given by Vc,,= V cc- JCRL

and must remain within the safe operating area, as shown in Figure 8.5.

The transistor power dissipation is therefore

p[ = Vale = (Vce - JeRd1c = Vecle - IlR1.

The current at which the maximumpower occurs is found by setting the derivative of equation equal to zero as follows:


Figure 8.4 Figure for Example 8.1


Part I Semiconductor Devices and Basic Applications


Figure a.5 DC load Wne within the safe operaling area

which yields

Vee 24

Ie = 2RL = 2(8) =:; L5 A

The C-E voltage at the maximum power point is VeE = V cc ~ lcRL = 24- (1.5)(8) = 12 V

The maximum power dissipation in the transistor occurs at the center of !he load line. The maximum transistor power dissipation is therefore

PT"" VC'E1C = 12(15) = 18W

Comment To find a transistor for a given application. safety factors are normally used. For this example, a transistor with a. current rating greater thail 3A, a voltage rating greater than 24 V. and 11 power rating greater than 18 W would be required.

Power transistors, which are designed to handle large currents, require large emitter areas to maintain reasonable current densities. These transistors are usually designed with narrow emitter widths to minimize the parasitic base resistance, and may be fabricated as an in(er4igitated structure, as shown in Figure 8.6. Also, emitter ballast resistors, which aresmall resistors in each emitter leg, are usually incorporated in the design.. These resistors help maintain equal currents in each B-E junction.

8.2.2 Power MOSFETs

Table 8.2 lists the basic parameters of two n-channel power MOSFETs. The drain currents are in the ampere range and the breakdown voltages are in the hundreds of volts range. These transistors must also operate within a safe operating area as discussed for the BJTs.

Table •• 2 Charaderlstics 01 two poYtllf MOSFETs

VDS(ma,;) (V)

lo(ma,) (Rl T "" 25"q PolWI

151 t 7S

400 2 20

Cbaprer 8 Output Stages and PoWt;r Amplifiers


I / I

/ Ba,e

/ LeJll'liMl





Emiu('t ~rmin81








'\ \

" \

1 1 1

FIgure 8.' An interdigitated bipcKaf trsnsistor structure ShOWing Iile top view and crosssectional view

Power MOSFETs ditTei from bipolar power transistors both in operating principles and performance. The superior performance characteristics of power MOSFETs are: faster switching times, no secondbreakdown, and stable gain and response time over a wide temperature range. Figure 8.7(a} shows the transconductance of the 2N6757 versus ternperature. The variation with temperature of the MOSFET transconductance is less than the variation \0 tile BJT current gain shown in Figure 8. I .


r- " --

-- ~
Tr -55 '(
_,. i.- T,· 2S ~
--- - V ~ I ~
1'/ r; ~ ...- rJi 11S ~
h V
t Vru"'15\1
-----t-.-- 8 Ils p\ I~l
:1 o


Tlfain eumnl iD (A) (.)


80 ,us p"1~o: to! !III
i I
TJ= +125 "C -,
TJ'" 2PC, N
TJ" - 55 O-C" ~
..a~ IQ

I 2 ) 4 5 6

Ga~ voltage tV) (b)

Figure B.7 Typical ooar~tIcs for h6gh-p0wer MOSFETs; (a) transconductanc: Y$IW$ dIain current (b~ t~an6fer thafacjer:i8lD

A lso, since a MOSFET is a high Input impedance, voltage-controlled device, the drive circuitry is simpler. The gate of a lOA power MOSFET may be driven by the output of a standard logic circuit. In contrast if (he current gain or a lOA BJT is fj = 10, then a base current of I A is required for a collector current of 10 A. However, this required input current is much larger than the ourpu t drive capability of most logic circuits, which means that the drive circuitry for power B1Ts is more complicated.

The MOSFET is a majority carrier device. Majority carrier mobility decreases with increasing temperature. which makes the semiconductor more resistive. This means that MOSFETs are more immune to the thermal runaway effects and second breakdown phenomena experienced ill bipolars. Figure 8.7(b) shews typical If) versus Vus characteristics at several tempe sa tures, clearly demonstrating that at high current levels. the current actually decreases with increasing temperature, for a givengate-to-source voltage.

Power MOSFETs are often manufactured by a vertical or double-diffused process, called VMOS Of DMOS, respectively. The cross section of a VMOS device is shown in Figure 8.8(a) and the cross section or the DMOS device is shown in Figure S.8(b). The DMOS process can tie used to produce a large number of closely packed hexagonal cells on a single silicon chip. as shown in Figure 8.8(c~. Also, such MOSFETs can be paralleled to form large-area devices, without the need of an equivalent emitter ballast resistance to equalize the current density. A single power MOSFET chip rna)' contain as many as 25,000 paralleled cells.

Mukiple soarcecells ill1ertClllnectW by mel.ii.lliZ<lt~oo


Si!ico~ gate Mulijrl~ S0UI« cells

lI-t.!ni\ n:gi'oD n-drif region
n' n+
Dr"l~ Drain
(8) (b) (c) Figure 8.8 (a) Cross section of a VMOS device; ~b) cross section of DMOS device; Ie) HEXFET structure

Since the path between the drain and the source is essentially resistive, the on ft.!Sistance r d;;(on) is an important parameter jn the power capability of a MOSFET. Figure 8.9 shows a typical r.t.(oil) characteristic as a function of drain current. Values in the tens of milhohm range have been obtained.

'" o

Chapter S. OulPUI Slaces and Power Amplifiers



Ri4l°o" measured \:Vim current pulse of 2.0 fJ' dllf:llwn initial 1j '" 25 ·C (bealing effect of 2.(I /.B pulse is minimal)

11030 10 W 30 4050 eo 70

I o- drain current (..4.)

Figure 8.9 Typical r~tance V81"Sl,l5 drain Cl)rr~'lt characte-lls!Ics 01 a MOSfET

8.2.3 Heat Sinks

The power dissipated in a transistor increases its internal temperature above the am bien! umptrarure, I f the device or jultcrion temperature T, becomes too high, the transistor may suffer permanent damage. Specialprecautions must be taken in packaging power transistors and ill providing heat sinks so that heat C<1D be conducted from the transistor. Figures 8.10(a) and (b) show two packaging schemes, and Figure 8.1O(c) shows a typical heat sink.




Figure 8.10 Two packaging schem~: (8) and (b) lor jIOW(\t" Iran&l~1ots and ~c) lypica~ heal sirrll:

To de siga a .hear sink for a power transistor. we must first consider the concept of tllemud resist.-ce 0, which bas units of ~CIW. The temperature difference, T2 ~ T1. across an element with a thermal resistance fJ is


where P is the thermal power through tbe element. Temperature difference is the electrical analog of voltage, and power or heat Bow is the electrical analog of current


Pan I Semiconductor Devices and Basic Applications

.----....,..---oT ,,"v

Manufacturers' data sheets for power devices generally give the maximum operating junction or device temperature T'.Ql<l~ and the thermal resistance from the junction to the case OJ,. = O~v--ca$e.~ By definition, the thermal resisranee between the case and heat sink is 8.ase-~llk. and between the heat sink and ambient is 9!;1!k-~m~'

The temperature difference between the device and the ambient can now be

written as follows. when a heat sink i6 used:


where PD is the power dissipated in the device. Equation (8,6) may also be modeled by its equivalent electrical elements. as shown in Figure 8.11. The temperature difference across the elements, such as the case and heat sink, is the dissipated power Po multiplied by the applicable thermal resistance, which IS B~.5.e-snk for this example •

If a heat sink is not used, (he temperature difference between the device and ambient is written as


'> e,nl-oml>


L...-_-+ __ .o() r ......

FI;uC8 8.11 Electrical

equivalent circuit for heat !Iow T dev - T"m~ = pv(eJ~~-.;-a5e + 8<;,se-~mb} (8.7)

from lhe device 10 the

ambient where 9ca~-amb is the thermal resistance between the case and ambient,

Example 8.2 Obl.otl,e: Determine the maxim urn power dissipation in it. I ransistor Consider a power MOSFET for which the thermal resistance parameters are:

&dc:~~ClIIIC = 1.75 'C/W 9"aoc-.nk = I ~C/W

8,n~- .. iI'I~= 5-C/W i.i<~l<'-~rn~ "" 50 'C/W

The ambient temperature is Tamb = 30"C. and 'he maximum junction or device remperature is T"ma. "" Td.-., = 150 '"C

SoluUon: When> no heal sink IS used, the maximum device power dissipation is found from Equation (EUI as

~ Tj,rn;u. - Ta;mb _ ISO - 30 _ 2 32 W

P(Jmal - - - .

, aok.-cas.: + Oca~-;'mJ-. 1.75 + 50

When a heal sink is used, the maximum device power dissipation is rOlJnd from Equation (8,6) as.

Comment These results illustrate that she use of a heat sink allows more power to he dissipated in the device, while keeping the device temperature at or below its maximum limit.

21n thisshort diScllSSwn. we llse.a more descriptive subscfipt notation I;) help darify th.e discussien,

Chapter 8 Output Stages and Power Amplifiers


The maximum safe rower dissipation ill a device is a function of: (I) the temperature difference between the junction and case, and (2) the thermal resistance between the device a nd the case I':l&:~_(~, or

P _ T"max - T~~",

D max -

. (I M,' +case


A plot of PO.rmx versus TcaSR.' called thepewer lIe-rath.g curve of (he trail" sistor, is shown in Figure 8.12. The temperature at which the power derating curve crosses the horizontal axis corresponds to Tjro"". At this temperature, no additional temperature rise in the device can be tolerated: therefore. the allowed power dissipation must be zero, which implies a zero input signal.



PD,~ -

Toe = 2S0C

Figure 1.1:t A power derating cerve

The rated power of a. device is generally defined as the power at which the device reaches itsmaximum temperature, while the case temperature remains at room or ambient temperature, that is, T<;'jj9J'; -= 25 "C. Maintaining the case at ambient temperature Implies that the thermal resistance between the case and ambient is zero, or that an infinite heat sink is used. However. with nonzero values of 6caS(-s~k and O~k-amb, the case temperature rises above the ambient, and the maximum rated power of tile device cannot be achieved. This effect can be seen by examining the equivalent circuit model 10 Figure 8.11 . If the device temperature is at its maximum allowed value of Tde~ = T;,nuu, then as TC<li'e increases, the temperature difference across $de~-(;a>.e decreases, which means that the power through the element must decrease.

Example 8.3 Obld"': Determine the maximum safe power dissipation in a transistor.

COli sider a BJT wi ih a rated power or 20 W and a maxim u m junction temperar UTe of 1),ma .. = 175 "C. The transistor is mounted on a heal, sink with parameters 8c • .c-lDk :;; 1 "CfW and 6,.k-.mb = j ~CfW.

SoluUon: From Equation (8.S), the device-to-case tbermal resistance is

_ r,.mu - Toe _ 115 -:- 25 _ 75T/W

91,k"-Cio~ -' p - 20 -.


Pan 1 Semiconductor Devices and Basic AppliC3L!QnS

From Equation (8.6). the maximum power dissipation is

P _ 1j.m., - Tamb - ...

ede.-ca.o;, +O""",_",k + e,nk-amb

175 - 25 .

"" ~:) I :Ii '" ILl W I .. ++.

Comrlll.nt The actual maximum safe power dissipation in a device may be less than! the rated value. This occur> when the case temperature cannot be held at the ambient temperature. because ofthe nonzero thermal resistance factors between the case and ambient.

J;=lgure 8.13 Figw& for EII!tlrcise 8.1 and Example 8.4


FI.ure •. 14 Figure lor Exercise B.3

Test Your Understanding

8,;1 Consider the. common-source circuit shown In Figure 8.13. The parameters are Rn = 20r.! and VOD = 24 y, Determine the required current, voltage, and power ratings of the MOSFET. (Ails. ID(mall);;;- L2A, VDS(ma)() = 24 v, {',,(max);;;;;; 7.2 W)

8.2 Assume that. the BIT in the common-emitter circuit shown in Figure 8.4 has limiting factor; of: Jc.rna~ zz lA, V([IMI "=- 50V, and Pr = lOW. N~glecting second breakdown effects, determine the minimum value of RL such that the Q-point of the transistor always stays within the safe operating area for: (a) Vee = 30 V. and (b] Vce ='=" 15V. In each case, determine the maximum collector current and maximum rransisior jower dissipation. (Ans. (a) Ih = 22,5 Q, 1.33 A, P Qm. "" 10 W (b] R[ = 7.5 O. lc.« ... ;e 2 A, PQ.m .... :;: 7.5W)

8.3 For the ernitter-lollower circuit in Figure 8.14. the parameters are V("c;;;;;; IOV and Re :::: 200 n. The transistor current gain is {J;;;;;; 150, and the current and voltage limitations are I Cmu "" 200 rnA and V C£($u.<1 "" 50 V. Determine the minimum transistor power rating such that the transistor Q-point is always inside the safe operating area. (Am. Pm~x = O.SW)

8A A power MOSFET with 9okV-~~~ :;: 3 ·C;W is operating with an average drain current of iD ;;;;; I A and ali. average drain-source voltage ofVDS ;;;;;; 12Y. The device is mounted on a heat sink with parameters 9.nk-aroh ;;;;;: 4°CJW and. 6'!:a~-S!Ik ;;;;;; I ~C/W. If the ambient temperature is T ~b = 250(:, determine the temperature of the: (a) device. (b) case, and (c) heat sink. (Ans, (a) 121 "C (b) 35"C (c) 73 ~C)

8.$ The rated power ofa power BIT is PD.rated = ~W. tile maximum allowed junction temperature is ~.fM.' = 100 ·C, and the ambient temperature is T'lmb = 2S "C, The thermal resistance between the heat ~nk aad air is ~nk- .. mb = 2 ~Crw, and that between the case and heat sink. is 9,,_,-.nk :;;: 0.5 ~CfW. Find the maximum safe power dissipation and the temperature of the case. (Ans. P = 29.2 W, T.,.~ -'" 98 ~C)


Power amplifiers are classified according to the percent or time the output transistors are conducting, or "turned on." The four principal classifications are: class A, class B, class AB, and class C. These classifications are illustrated in Figure 8.15, for a sinusoidal input signal. In class-A operation. an output transistor is biased at a quiescent current.IQ and conducts for the entire cycle of tlte input signal. For cl.ass--B operltiott, an output transistor conducts for only

Chapter 8 OUlput Srages anri Power Amplili~rs



jCb f\ l ~
II· Zit 31t 4lf OJI 0 tr l1r JJr 4Jr 0t
(a) {b)
;l~ 1"
ICQ -=-=- - - -A - - -1.- ~A, I ..
0 It III 311" 41f WI 0 tt Itt J>r 41t <'Ill
(c) ~ Flgufe 8.15 CoIIectof current venus ttme dlaracteris1ics: (8) class·A a.ql1i6er, (b) class-B arnpIifi8f, (c) class-A.S 8fIll1ifler, and Cdt class-C amplifier

one-half of each sine wave input cycle. In £lass-AS operation, an output transistor is biased at a small quiescent current If} and conducts for slightly more than half a cycle. In contrast. in dass-C o~ration an output transistor conducts for less than half a cycle. We will analyze the biasing, load lines, and efficiency of each class or power amplifi~r,

8.3.1 Class·A Operation

The small-signal amplifiers considered in Chapters 4 and 6 were all biased for class-A operation. A basic common-emitter configuration is shown in Figure 8.l6(a). The bias circuitry has been omitted, for convenience. Also, in this stu'hird dass.-A amplifier configuration. no inductors or transformers are used.

The de load line is shown in Figure 8.16(b). TheQ~pojnt is assumed 10 be in the center of the load line, so that V CEQ = V ('c /2. If a sinusoidal input signal





T Thtte




Rgur.8.16 (a) Comtnon-enWer...,.,.... (b) de load 1IfIe. and (c) Instardaneous power cllnipation.,..,... time ",the _'-Of

Part I Semiconductor Devises and Basic Appli.<:ations

is applied, sinusoidal variations are induced in the collector current and collector-emitter voltage. The absolute possible variations are shown in the figure, although values or VCE= 0 and ic = UCQ cannot actually be attained.

The instantaneous power dissipation in the transistor, neglecting the base current, is

PQ = vceic (3.9)

For a sinusoidal input signal. the collector current and collector-emitter voltage can. be written

ie = ICQ + Ir sin il)J and


VeE = 2 - Vi'slnw,


If we consider the absolute possible variations. then fp = ICQ and Vp = V cell Therefore, the instantaneous power dissipation in the transistor. from Equation (8.9), is

(8, u:

Figure 8.t6(c) is a plot of the instantaneous transistor power dissipation.

Since the maximum power dissipation corresponds 10 tile quiescent value (see Figure 8.5), the transistor must be capable of handling a continuous power dissipation of JI (cfca/2 when the input signal is zero.

The power ronvenion effitiency is defined as

signal load power (PL) '1=

supply power(Ps)


wberePL is the average ac power delivered to the load and Ps is the average power supplied by the V rc power sources). For tbe standard class-A amplifier and sinusoidal inpu; signals, the average ac power delivered to the load is m V,lp. Using the absolute possible variations, we have

- (I)" (Vec) Vcclco

Pdmax) == 2 ""2 (/(Q) = 4


The average power supplied by the Vee source is

Ps = VetlcQ The maximum attainable conversion efficiency is therefore

! VcelcQ

TI(max) = 4 . ~ 25%

Vee Ice

We must keep in nind that the maximum possible conversion efficiency may change when a load is connected to the output of the amplifier. This efficiency is relatively low; therefore, standard class-A amplifiers are normally not used when signal powers greater than approximately 1 W are required.

Desian Poioter: We must emphasize that in. practice, a maximum signal voltage of Vccf2 and a maximum signal current oflcQ are not possible. The output signal voltage must be limited to smaller values in order to avoid transistor saturation and cutoff. and the resulting nonlinear distortion, The

(It 14)


Chapter g Outpm Stages, and Po-wer Ampliliefs

calculation for ttle maximum possible efficiency also neglects power dissjpation in the bias circuitry. Consequently, the realistic maximum conversion efficiency in a standard class-A amplifier is on the order of 20 percent or less.

Examp'a 8.4 Ob16dl..,.: Calculate the actual efficiency of a class-A om put stage.

Consider the common-source circuit in Figure 8.13. The circuit parameters are V Ill) == W V and Rn = 5. tn. and the transistor parameters are: K. = I rnA(Vl. II m= IV. and )" = O. Assume the output voltage swing is limited to tbe range between the transition point and l'OS = 9V. 10 minimize nonlinear distortion.

Sctutlon: Theload line is given by V os = V f)f) ~ loRD

At the transition point, we have V os{ sat) = V(;S - VfN


Jl~ '" K~( "<s - V TN)"

Combining these expressions, the transition point is determined from

J'n,{sat) ;;;; V/)/J - K~RD Vhs(sat)


(1 )(5)V~s(sat) +V n.dsat) - 10 ~ 0 which yields

V{J,~(Sllt) = JJ2 V

To obtain the maximum symmetrical swing under the conditions specified, we want the Q'jl(liO( midway between VJ).~ =132 V and V D$ = 9 V. or

VP.V)= 5.16V

The maximum ac component of voltage aCrOSS ihe load resistor is then ,~ ~ .lB4 siowl

and the average power delivered to the load is

'" -! _ (3.1::4)1 _ 14"" , .. ,

r s. -- 2 5 -.' mw

The quiescent drain current is found to be !O - 5_16

'oo =--5- = 0-950SmA

The average power supplied by the Von source is f\. "'" VDlIloQ;;;;;; (10)(0,968);;;;;; 9.68mW

and the power conversion efficiency, from Equation (8.12), is

Pl 1.47 0

'I = =-- = 9, '8 ~ 15.2 Yo

P5 .6

Comment: By limiting the swing in tile drain-source voltage. to avoidnonsaturauon aDd cutoff and the resulting nonlinear distortion. we reduce the oulpUi SLage power co nversi on e f~ciency considers bly, compared 10 the theoretical maxim umpossi ble 'faille of 25 percent for the standard class-A amptiliet.

Pal' I Semicond~r Devices and Basic Applicatioas

Class-A operation also applies to the emitter-follower. common-base, source-follower, and common-gate configurations. As previously stated, the circuits considered in Figures 8.13 and 8.16(a) are standard class-A amplifiers in that no inductors or transformers are used. Later in this chapter, we will analyze inductively coupled and transformer-coupled power amplifiers that also operate in the class-A mode. We will show that, for these circuits, the maximum conversion efficiency is 50 percent

Test Your Understanding

8.8 Consider the common-emitter output stage shown in Figure 8.I6(a). Let Vee = 15V and Itt. = 1 tn, and assume tbe Q-point is in the center of the load line. (a) Find the quiescent power dissipated in the transistor. (b) 1f the sinusoidal output signal is limited to a 11 V peak-to-peak value, determine: the average signal power d~livcred to the load, the pOWfT conversion efficiency, and the average power dissipated in the transistor. (Am. (a) Po = 56.3 mW (b. PL = 21.1 mW, 71 = 18.")%. PQ = 35.2mW)


c ....

~ 000

Flgure8.17 Agure fO( Exerdse e.7

*8 .. 1 For the common-source circuit shownin Figure 8.17, the Q-point is J'DSQ ;;:::; 4 V. (a) Find JD(}.' (b) The minimum value of the instamaneous drain current must be no less than (~IDQi and (he minimum value of the instantaneous drain-source voltage must be no less than "vs = 1.5 v. Determine the maximum peak-to-peak amplitude of a symmetrical siuusoidal output voltage. (c) For the conditions of part (b), calculate the power conversion efficiency, where the signal power is the power delivered to RL. (Ans, (3) IDQ = 60mA (b) Vp_p = 5.0 V (c)"h = 31.2SmW,·'1 ~ 5.2%)

8.3.2 Class-B Operation

Figure S.18 shows an output stage that consists of a complementary pair of bipolar transistors. When the input voltage is \'J= 0, both transistors are cut 0« and the output voltage is Vo ;;:::; 0, If we assume a B-E cut-in voltage of 0.6 V. then the output voltage Vo remains zero as long as the input voltage is in the fange -0.6 :s 'I s +0.6 v.

If '1/ becomes positive and is greater than O.6V. then Q~ turns on and operates as an emitter follower. The ]o~ current iL is positive and is supplied

Chapter g Output Stages and Powu Ampl.irters

Crossover Dlstottlon

through Q", and the B-E junction of Qp is reverse biased. If v! becomes negative by more (han O.6V, then Q, toms on and operates as anemiUer follower. TransistorQp is a sink for the load current. which means that it: is negative,

This circuit is called a eoaapIementarJ ~ll outPut stage. Transistor Q" conducts during the positive half of the input cycle, and Qp conducts during the" negative half-cycle. The transistors do not both conduct at the same time. I

Figure 8.19 shows the voltage transfer characteristics for this circuit. When either transistor is conducting. the voltage gain, which is the slope of the cerve, is essentially unity as a result of the emitter fonawer. Also, there is a range of input voltage around zero volts where both transistors are cut off and Vo is zero, This portion or the curve is called the de •• band, and it produces a crossover distortiol, as illustrated in Figure 8.20, for a sinuosidal input signal. (Crossover distortion can be virtually eliminated by biasing both Q" and Qp with a small quiescent collector current when VJ is zero, This techique is discussed in the next section.)

Flour.8.19 Voltage 1ransler ¢h.$.l'8d$ristiCs 01 basic COJ11C)lell1entary pwh-puU output SI8:ge

Figure 8.2G Crossover distortiOn of ba$k: COIIlJlIemerrtary push-pull ouIptJl stage

Eltample 8.5 ObJd'.: Determine the total harmonic distortion (THD) of the class B complementary push-pull output stage in Fieurf 8.1&.

A PSpice analysis wasperformed, WAlch yielded the harmonic coment of the output signal.

SoMlon: A 1 kHz sinusoidal signal with an. ampiitude of 2 V was applied to the input of the circuit shown in Figure 8.18. The circuit was biased at ± to V. The transistors wed in tbe circuit were lN3904 npn and 2NJ906 pnp devices. A \ kO load was connected to the output

The harmonic content for the first nitle harmonics IS shown in Table S.l We SC'C !bat the output is rieh in odd harmonics witb the 3kHz third harmonic being 18 percent as large as the I kHz principal ()utp~t iiignal. The Iota' UrmOD.1c distortion is 19.7 percent, whi<:h i! 1arp.

Pari 1 Semiconductor Devices and Basic Applications

T abl. 8.3 Harmorne content for Example 8.5

1.000E+03 1.1S1E+OO

2.000£+03 6.313E-03

3. OO()E+03 2. 103E-01

4.~OOE+03 4.984E-03

5.000E+03 8.064£-02

6.{}OOE+03 3. 456E-03

7.000E+03 2.2J5E-02

B.OOOE+03 2.019E-03

9.000£+03 b.61~E-03


1.000£+00 S.485£-D3 1.82112;-01 4.331E-03 7 .~06E-02 3.00)1;:-03 2.464.E-02 1. "J 54E-03 5.803E-OJ




-1. 793£+02




1.770E+02 -B.029E+Ol 1.472E+02 PERCENT

CGmlnent These mulls show the obvious effects of the dead band region. If the illput signal amplilude increases, the total harmonic distortion decreases. but if the amplitude decreases, (he total harmonic distortion will increase above the 19 percent value,

Power Efflclsncy

If we consider an idealized version of the circuit in Figure 8.18 in which the base-emitter tum-on voltages are zero, then each transistor would conduct for exactly one-halt cycle of the sinusoidal input signal, This circuit would be a class-B output stage, and the output voltage and load current would be replicas of the input signal. The colleeror-emitter voltages would also show the same sinusoidal variation.

Figure 8.21 illustrates the applicable de load line. The Q.point is at zero collector current, or at cutoff for both transistors. The quiescent power dissipation in each transistor is then zero.

The output voltage for this idealized class-B output stage can be written


Chapter 8 OU.pUl S.iges and Power Ampiirlft's

where the maximum possible value of Vpis Vec' The instantaneous power dissipation in Qrt is


and the collector current ill

. ~,.

1(,,, = - sm o» RJ_

for 0 ::: wi ::::: n, and 'Cn = 0



for 1< .:::: Wi ::: 21f, where V, is the peak. output voltage.

From Figure S.2i, we see that the coflector-emitter voltage can be written


1'('1:'" = Vee - Vpsinwr (1.19')

Therefore, the total instantaneous power dissipation \l\ QII is

Pel! = (Vcc' - VI' sin wt)(;: Sill WI) (8.20)

for 0 .::::: Wi'::; 'T, and

PQ" =0

for Jf S wi ::: 2:rr. The average power dissipation is. therefore

If If vI

~ ~ C('~ p P

PQn ::;~- 4R,L


The average power dissipation in transistor Qp is exactly the same as that for Qn> because of symmetry,

A plot of the average power dissipation in each transistor, as a function of Vp• is shown in Figure 8.22. The power dissipation first increases with increasing ousput voltage, reaches a maximum, and finally decreases wjth increasing Vp' We determine the maximum average power dissipation by setting the derivative of P QII with respect to Vp equal to zero, producing


- '(C

PQIl(max) =r Rl. (8.22)



ParI l Semiconductor Devices and Basic Applications

which occurs when


The average power delivered to the load is

_ I V~

PL =_._

2 RL


Since the current supplied by each power supply is half a sme wave, the average current is Yp/(nRL). The average power supplied by each. source is therefore

- . - (. VI')

Ps+ = r-: = Vce 1rRl


and the total average power supplied by the two sources is


From Equation (8.11), the conversion efficiency is

I V1 r

"2."Rt: "Jf VI'

'1- --.-

- 2 Vee ( Vp) - 4 Vir JfRl.


The maximum possible efficiency, which occurs when Vp = V cc- is It

I)(max} = '4 => 78.5%

This maximum efficiency value is substantially larger than thaI of the standard class-A amplifier.

From Equation (8.24), we find the maximum possible average power that call be delivered to the load, as follows:


- . 1 vIc Pdmax) = _._

1 RL.


Tbe actual conversion efficiency obtained in practice is less than the maximum value because of other circuie losses, and because the peak output voltage must remain less than Vee to avoid transistor saturation. As the output voltage amplitude increases, output signal distortion also increases. To limit this distortion to an acceptable level, the peak output voltage is usually limited to several volts below Vee, From Figure 8.22 and Equation (8.23), we see that the maximum transistor power dissipation occurs when V" = 2V eels At this peak output voltage, the conversion efficiency of the class-B amplifier is, from Equation (8.27).

11 =~. V = (~), ( =~ => 506/0

4 Vee ' 4 Vee 1r 2


Chapter 8 Output Stages and Power Amplifers

Test Your Understanding

8.8 Design an idealized class-B output stage. as shown in Figure 8.1 a, to deliver an average o(25W to au 8 {2 speaker. The peat output voltage must be no larger than SO percent of supply voltages Vee. Determine: (a) the required value of V cc- (b) the: peak current in each transistot, (c) the average power dissipated in each transistor, and (d) the power conversion efficiency. (Ans. (a) Sf cc= 2SV (b) Ip ;;:;; 2.5 A (c) PQ ~ 7.4 W (d) IJ :;::::

62.8%) .

8.8 For the idealized class-B output stage shown in Figure S.18, the parameters are Vee = 5Vand RL ~ won. The measured output signal is ~¢ ~ 4sinwt (V). Determine: (a) the average signal load power, (b) the peak current in each transistor, (c) the average power dissipated in each transistor, and (d) the power conversion efficiency. (Ans. (II.) h = 80 mW (b) t, = 40mA ({,';) PQ '= 23.7 mW (d) ,,= 62.B%}


8.3.3 Class·AB Operation

Crossover distortion can be virtually eliminated by applying a sma!! quiescent bias on each output transisror, for a zero input signal. This is called a class-AD output stage and is shown schematically in the circuit in Figure 8.23. If Q~ and Qp are matched. then (or VI =:: 0, VS8/2 is applied to the B-E junction of Q", YSB/2 is applied to me E-B junction of Qp. and Vo ::;;; O. The quiescent collector currents in each transistor are given by


As v, increases, the voltage at tile base of QIl increases and Vo increases.

Transistor Qn operates as an emitter follower, supplying the load current to Rt,. The output voltage is given by


490 I SenIiconduclor De1iJces and Basic Application.s

and the collector current of Q" (neglecting base currents) is


Since i"" must increase to supply the load current, V,tEn increases. Assuming V BB remeins constant, as VBfA increases, lIEBp decreases resulting in a decrease in icl"

As,,/ goes negative, the voltage at the base ofQp decreases and Vo decreases. Transistor Qp operates as an emitter follower. sinking current from. the load. As icp increases, vEBp increases. causing a decrease in vilE .. and ien.

Figure 8.24(a) shows the voltage transfer characteristics fot this class-AB output stage. If VBE" and 'E8p do not change significantly, then the voltage gain, OT the slope of the transfer curve, is essentially unity. A sinusoidal input signal voltage and the resulting -collector currents and load current are shown in Figures 8.24(b), (c), and (d), Each transistor conducts for more than onehalf cycle, which is the definition of class-A B operation.

There is a relationship between "ell and icp' We know that

V,I'::" + v£61' = VSB which can be written


VTlnC~,) + VrlnCZ;)= 2vr,nCJiQ)

Combining terms in Equation (8.341b»), we find . . . Ii

'(Il'er;;:;; CQ



(lice- vCE:($I1))
-(Vcc- V£dsat)
ie io. iep
;" -- .....
./ "
/ -,
I ....
Jf lit WI
(c) (b)


FIpn 1.24 Chanlcteriatic:e 011 ~ ou1put stage: (a) voltage transfer CU'Ve, (b' .......... input.,. (.;)~~ _, {d) CiIpUt amn!

Cl'oaplti't O\lIPU1 Stages and Power ADlJIllfleTS


The product of iCn and ie, is 11 cosntant: therefore. if lc« increases, it" decreases. but does nOI go to zero,

Since, for 3 zero input signal. q uiescent collector currents exist In the output transistors. the average power supplied by each socrce and the average power dissipated in each transistor are larger than lor a class-B configuration. This means that the power conversion efficiency for a class-All output stage is less than that for an idealized class-B circuit. In addition, ihe required power handling capability of the transistors ina class-All circuit must bes1ightly larger than in a class-B circuit However. since the quiescent collector currents leo are usually small compared to the peak current, this increase in power dissipation IS not great. The advantage of eliminating crossover distortion in the class~AB output stage greatly outweighs the slight disadvantage or reduced conversion efficiency and increased power dissipation,

ExampJe 8.6 ~ecHW): Determine the total harmonic distortion (THD) (J( Ihe class AS complementary push-pull output stage shown in Figure 8.23.

A ]>Spice analysis was performed, which yielded the harmonic content ofthe output signal.

Solvtlon: A I kHz sinusoidal signal with an amplitude of 2 V was applied to the input of {~C circuit, The bias voltages V 0,/2 wert varied. The circuit was biased at ± 10 V and a I k!:l road was connected to the output. Shown in Tab-Ie 8_4 are tile VBBi2 bias voltages applied, the quiescent transistor currents, and ihe toralharmcnic distortion (THD).

Table 8.4 Quiescen! coIJector CUTentS lind 100ai harmonic distortion of class-AS titcllil

r,,/2 (V) 'n; {mA) TIm (-4)
D.W QJ148 1.22 OJ3 0244
0,10 2,21} O,\IOIiS
0,15 13.3 0,0028 DIt4;u •• lon: With a peak input voltage or:l V lImj a I k!l load, the peak load current is on the order of 2 mAo From the results shown in Table 8.4, the THD decreases in the ratio of quiescent transistor current to peak load current increases. In other words, for a given input voltage. the sma lief tbe variation in coilec!or current when the signal is applied compared to tile quiescent collector current, tile smaller lhe distortion. However. there is a tri'lde-oif. As the quiescent transistor current increases, the power efficiency IS reduced. The circuit should be designed such thaf the transistor quescent current is the smallest value while meeting the maximum Ictal harmonic distortion specification.

Comm.nt: We see t ha I I he class- A B ou t pUI stage resul Is in a much smaller TH D value than the class-B circuit, bUI as with mostcircuits, there art no uniquely specified bias '0101 tu ges ,

Part I Semiconductor Devices aru:t Basic Applicatiom

A class-AS output stage using enhancement-mode MOSFETs is shown in Figure 8.25. If Mll and Mp are matched, and if Il} = 0, then V 88/2 is appned across the gate-source terminals of MN and the source-gate terminals of Mp. The quiescent drain currents established in each transistor are given by

iD~ = iDp = /DQ = K(V;B - IVTiy


As VI increases, the voltage at the gate of Mn increases and \'0 increases, lransistorMIt operates as a source follower) supplying the load current to RL• Since fPl! must increase to supply the load current, IIGSPI must also increase, Assuming V BB remains constant, an increase in VGSn implies a decrease in vSGp and a rcsu1ting decrease in iDp' As Vi goesnegative, the voltage at the base of Mp decreases and 110 decreases. Transistor Mp then operates as a source follower, sinking current from the load,

Example 8.1 ObIedln:Dek:rmine the required biasing in a MOSFET class-AD output stage.

The circuit is shown in Figure 8.25. The parameters are Y oo = I{) V and Rl, = lOR The transistors are matched, and the parameters are K = O.20A/V~ and IV TI = I V. The quiescent drain current is to be 20 percent of the load current when ~o = SV.

Flp,.8.25 t.«JSFET class·AS 0UIpuI stage

SOlution: For VQ =: S V, Ii ~ S/10 "" O.2SA

Then, for [0 = O.OSA when '0 = 0, we have

IDQ = 0.05 = K(V ~-WT(Y = (O.20{V;B - I r whlda yields

..... /2:E lSOV

Cbap~er i Output SUiaes ,,,.d Power Ampliftm


The input voltage for Vo positive is VBB

VI = 1'0 + ~GSIl - T

For VQ ;;;;; 5Y and i"" ~ h = 0.25 A, we have

{;;, fOB

VGs.. = V"K + IVrl = V 010 + I = .l.12V

The source-to-gate voltage or Up is

vSOI' = V 8B - V GSI:o = 3 - 2.12 = 0.38 V

which means that Mp is cut off and flJlt = iL, Finally, the input voltage is VI =5+2J2-1.5=5.62V

Comment Since VJ > fO, the vOltage gain of this output stage is less tban unit)', as expected,

Voltage VBS can be established in a MOSFET class-AB circuit by using additional enhancement-mode MOSFETs and a constant curtent lBiu' This will be considered in a problem at the end of the chapter.

T", Your Understanding

·8 ... 0 Consider the MOSFETclass-AB output stage shown in Figure S.2S, with the circui I and transistor pa rameters as given in Bxample 8.7. Let JI BB = J. 0 V. Dete.rmine the small·siJnai voltage gain Ay'; d~old'VJ evaluated at: (8) Vo= 0, and (b) '0 = 5.0V. (Ans, (a) A. = 0.889 (b) A. = 0.899)

8.3.4 Class-C Operation

The transistor circuit ac load line, including an extension beyond cutoff, is shown in Figure 8.26 . For dass-C operation, the transistor has a reverse-biased B-E voltage at the Q-point. This effect is illustrated in Figure 8.26. Note that


Q-p:.inl (~~VHoJ

Parll Scmicon4lK1cr Deviees 3T.1d Basic Appllca I ions

the collector current is not negative. but is zero at the quiescent point. The transistor conducts only when the input signal becomes sufficien[ly positive during its positive half-cycle. The transistor therefore conducts for less than a hall-cycle, which defines class-C operation.

Class-C amplifiers are capable of providing large amounts of power. with conversion efficiencies larger than 78.5 percent These amplifiers are normally used for radio-frequency (RF) circuits, with tuned RLC loads that are commonlyused in radio and television transmitters. The RLC circuits convert drive current pulses into sinusoidal signals, Since this is a specialized area, we will not analyze these circuits here.


The standard class-A amplifier was analyzed previously, and the maximum possible power conversion efficiency was found to be 25 percent. This conversion efficiency can be increased with (he use of iaductors and transformers.

8.4.1 Indudively Coupled. Ampnfier

Delivering a large power to a load generally requires both a large voltage and a high current. In a common-emitter circuit, this requirement can be met by replacing the collector resistor with an inductor, as shown in Figure 8.27(a). The inductor is a short circuit to a de current but acts as an open circuit to an ac signal operating at a sufficiently high frequency. The entire lie current is therefore coupled to the I (lad. We assume that el.:» RL at the lowest signal frequency.

The de arid ac load lines are shown in Figure 8.27(b). We assume that the resistance of the inductor is negligible. and that 'he emitter resistor value is small. The quiescent collector-emitter voltage is then approximately J! ('_fQ ~ Vee. The ac collector current is

. -Vc~

f -_-

" - RL

Rj· .tl __,

~I-~ :



F ....... 8.2:7 (a) Induc:tiwty ~ dala-A amplifier Mel {bl de and ac load lint$

Chapter 8 OlJIPUI Stages alld Power Amplifiers

To obtain the maximum symmetrical output-signal swing, which will in turn produce tile maximum power, we want


For (his condition, the acload line intersects the VeE axis at 2Vcc.

The use of an inductor or storage device results in an output ac voltage swing that is larger than V cc- The polarity of the induced voltage across the inductor may be such that the voltage adds to V cc- producing an output voltage that is larger than V ce.

The absolute maximum amplitude of the signal current in the load is ICQ; therefore, the maximum possible average signal power delivered to the load is

- I 2 I V~c P/,(max) ;;;;;:: 2:'CQRL :: '2' RL


U we neglect the power dissipation in the bias resistors R, and R2• the average power supplied by the Vee source is

- . vlr Ps;;:;: V(Ci('Q = .RL


The maximum possible power conversion efficiency is then I V~['

Pdmax) '2' RL 1

ij(max) = = -2- = - =} 50~%

Ps Vee 2


This demonstrates that •. in a standard class-A amplifier, replacing the collector resistor with an inductor doubles the maximum possible power conversion efficiency.


8.4.2 Transformer-Coupled Common-E miner Ampliller

The design of an inductively coupled amplifier to achieve high power conversion efficiency may be dilficult, depending on the relationship between the supply voltage Vee and the load resistance RLo The effective load resistance can be opurmzed by using a transformer with me proper turns ratio.

Figure &.28(a) shows a common-emitter amplifier with a transformercoupled load in the collector circuit.

The dc and ac load lines are shown in Figure 8.28(b). If we neglect any resistance in the transformer and assume IhatRE is small, the quiescent collector-emitter voltage is

VCEQ ~ Vee

The transformed load resistance is


Part 1 Semiconduclor Devices and Basic AppI~tiom


FilUM 8.28 (a, lransformer-coupled common-emitter amplifier and. (b) de and ac load lines


where a is the ratio of primary to secondary (urns, or simply the turns ratio. The turns ratio is designed to produce the maximum symmetrical swing in the output current and voltage; therefore,

R' ~ 2 V LC _ V c(' - ~ R L------lr L



The maximum average power delivered 10 the load is equal to the maximum average power delivered to the primary of the ideal transformer, as follows:

- I

PL<max) = 2: Vcclc»


where Vee and lcQ are the maximum possible amplitudes or the sinusoidal signals. If we neglect the power dissipation in the bias resistors R, and R2• the average power supplied by the J' cc source is

Ps = Vce/cQ

and the maximum possible power conversion efficiency is again I](max) = 50%

TeSI Your Understanding

·D8.11 For the inductively coupled amphfier shown in Figure &.27(a), the parameters are: Vcc=12V. Vu(on)=O.7V. R£=O.lkn, Rt..= I.SkO, and ~::7S. (a) Design R, and R2 for manmum symmetrical swing in the output current and voltage(Let RTH = (I + fj)R£.) (b) If the peak output voltage amplitude is limited to O,9VCf' and the peak output current amplitude is limited 10 O.91cQ, determine the average power delivered to the load, the average power dissipated in the transistor, and the power conversion efficiency. (Ans. (a) R, = 39.1 tn, R2 = 9.43 to (b) Pt:::; 3.8.9 mW,

"'fiQ = 57.1 mW, '1 = 40.5'%) -

Ch.$pter 8 OUlpul Sl.:l~ and Pow~ Amplifim

8.4.3 Transformer-Coupled Emltter~Followe, Amplifier

Since the emitter follower has a low output impedance, It is often used as the output stage of an amplifier. A transformer-coupled emitter follower is shown ill FigurcS.29(a). The de and ac load lines are shown in Figure K29(b). As before. the resistance of the transformer is assumed (0 be negligible.





FlgurI8.29 (a) Translarmer-coupled emitter-folloWer ampfifi8f and (b) ec and ~ load lines

The transformed load resistance is again Ri = c? Rl. By correctly designing the turns ratio, we can achieve the maximum symmetrical swing in the output voltage and current

The average power delivered to the load is

- I V;

PL ::::=-._

2 s,


where Vp is the peak amplitude of the sinusoidal output voltage. The maximum peak amplitude of the emitter voltage is lice. so that the maximum peak amplitude of the output signal is

The maximum average output signal power is therefore

_ I I Vp(max)t V~('

P/,(Iliax) "" ..,. R = 2 1R

- L a L


The maximum power conversion efficiency for this circuit is also 50 percent.

Part I Semiconductor Devices and Baslc Applicaliom

Delton example 8.8 ObJective: Design a transformer-coupled emitterfollower ampIilicr to deliver a specified signal power.

Consider the circuit shown in Figure 8.2~a). withparameten Vee = 24 V and RL = 3 O. The average power delivered 10 the load is to be 5 W. the peak amplitude of the signa] emitter current is to be no trION (ban ()<9IcQ• and that of the signal emitter voltage is to be no more than 0,9 Vee. Let fJ = 100,

So'u.on: The average power delivered to the load is given by Equation (8.45). The peat. output voltage must therefore be

Vp = J,~RII)l. = j2~8}(S) ;;:; 8.94 V and the peak output current is

v, 8.94

Ip = RL = ""8 ;;;;;; 1.12 A


V. ;;;; O.9V« = aV"


Q = O.9J'cc = (O.9:W24) = 2.42

V" 8.94

Also. since

l, = O.9!cQ = Ipla


I t, 1.12

Ice = 0,9 . -;; =' (0.9)(2.42) ;;;:;. [).s14 A

The maximum power dissipated in the transistor, for this class-A operation, is PQ = V CC1ql '"" (24)(0,5 t 4) ~ l2.3 W

so the transistor must be capable of handling this power.

Bias resistors R. and R. are found from a de analysis. The Thevenin equivalent voltage is

Vr« = IBQRTH + Vu(on) where


We also nave

J IrQ 0.514 ~ 14 A

J1Q = If = 100 => J. m

Since Vrn <: V c( and /1JQ ">;' SmA, then RTH cannot be unduly large, However, if RTH is small, then the power dissIpation in Rr and Rl becomes unacceptably high. We choose Rm = 2.51(0. so tbat


((TN = RI (RTf/Wee = RI (2.5)(24) = (5.14)(2.5) + 0.7

Therefore, R] = 4.43Hl and Rl = j,74kO,

.... Co~: The average power delivered by V cc (neglecting bias resistor effects) is P s = V cclco = 12.3 W. wt.ictl means that the power conversion ellkiellC:Y is tJ:- 5/12.3 "* 40.71%. The d1iciency wiU always be !es.s than tbc 50% maximum value, i( uansist(lr saturation and distortion arc to be minimized.

Chapter 8 Output Sla~ and Power Ampliftns

Test Your Understanding

-D8.12 A rransformer-coupled emitter- follower amplifier is shown in Figure 8.19(a). The parameters are: IIC(-=18V. VSE(OA) = 0.7 V, fJ= 100, a=IO, and R[=8Q. (a) Design R. and R] to deliver the maximum power 10 the load. The input resistance seen by the Vj source is to be 1.5 kr.!. (b) Iftbe peak amplitude of'the emiuer voltage vs is limited 100.9 Vee, and the peak amplitude ofthe emitter current iE: is limited to 0.9/cQ, determine the maximum amplitude of the output signal VOltage, and the average power delivered _10 the load. (Ans. (a) R, =.25.4kn. 112",,- 1.62kQ (b) I'~ = 1.62 V, I" = 203mA. PI_ =O.l64W)


A class-Aft OUIPU( stage eliminaies the crossover disioruon (hat occurs in a class- B circui t. I n 'his section. we will analyze several circuits that provide a small quiescent bias to the output transistors. Such circuits are used as the output stage of power amplifiers, as well as the output stage or operational amplifiers. and will be discussed in Chapter 13.

8.5.1 Class-AB Output Stage with Diode Biasing

1n a class-All circuit, the V SB voltage that provides the quiescent bias for the output transistors can be established by voltage drops across diodes, as shown in Figure S.30. A constant current ISias is used to establish the required voltage across the pair of diodes. or the diode-connected transistors, D, and Dz. Since D, and D2. are 110t necessarily matched with Q~ and Q,. the quiescent transistor currents may not be equal to IBia,;'

As the input voltage increases. the output voltage increases, causing an increase in ic/!' This in {Urn produces an increase in the base current i&. Since


Figure '.30 Class-AI!! Wput s\ag(t wiII'I quletoent .bias eeIabIIhed by diodes


Part I Semiconductor Devices and Basic Applications

the increase base current is supplied by IfJas' the current through D, and D2, and hence the voltage. V Bil. decreases slightly, Since voltage V BB does not remain constant in this circuit. the relationship between lCIl and icp. as given by Equanon (8.35), is nOI precisely valid for this situation. The analysis in the previous section must therefore be modified slightly. but the basic operation or this class-AB circuit is the same.

Design exlmpte 1.9 Objective: Design the class-AB output stage in Figure IUO to meet specific design criieria.

Assume lS(} ~ 3 K 10-14 A for DI and D2• lSQ = 10-13 A for Q". and Q~, and /J" = ~ = 75. let RL = 8 Q. The average power delivered to the load is to be 5 W. The peak output volta~ is 10 be no more thall 80 percent of Vee, and. tbe minimum "Blue of diode current ID is to be no less than SmA.

So.uUon: The average power delivered to the load, from Equation (8.24), is 1

- I Yp


::: Rl


The supply voltages must then be

Vp 8.94

Vce =- = -= 112V 0.8 0,8

At Ihis peak output voltage, the emitter current ofQn is approxunately equal to the I~ad current, or

and the base current is

iEn 1.12

i&l= -- ""._:::j. 14.7 rnA 1+ e: 76

For a minimum lo = SmA, we can choose iSla. ~ 20mA. For a zero input signal, neglecting base currents. we nnd that

( TD ) (20 x 10-3)

JiBS = 2Yrln fsD = 2(O<026)1~ 3 x 10-14 = 1.416V

The quiescent collector currents are then

I';Q = lSQe(Yk.ll)JVr = IO-lJeI.4U/M0261 ~ 67,OmA

For 110 = 8.94 V and iL = I, IlA. the Due current is i& = 14.7 mAo and If) = IBis. - i8J, = 5.3 rnA

The new value of V B8 is then

, (If)) (5.3 x 10-1) V

v". = 2Yr In 131) = 2(C.026)ln 3 x 10-14 = 1.141

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