Practical Analog Design Techniques

SECTION 1
SINGLE-SUPPLY AMPLIFIERS
Rail-to-Rail Input Stages
Rail-to-Rail Output Stages
Single-Supply Instrumentation Amplifiers
SECTION 2
HIGH SPEED OP AMPS
Driving Capacitive Loads
Cable Driving
Single-Supply Considerations
Application Circuits
SECTION 3
HIGH RESOLUTION SIGNAL CONDITIONING ADCs
Sigma-Delta ADCs
High Resolution, Low Frequency Measurement ADCs
SECTION 4
HIGH SPEED SAMPLING ADCs
ADC Dynamic Considerations
Selecting the Drive Amplifier Based on
ADC Dynamic Performance
Driving Flash Converters
Driving the AD9050 Single-Supply ADC
Driving ADCs with Switched Capacitor Inputs
Gain Setting and Level Shifting
External Reference Voltage Generation
ADC Input Protection and Clamping
Applications for Clamping Amplifiers
Noise Considerations in High Speed Sampling ADC Applications
SECTION 5
UNDERSAMPLING APPLICATIONS
Fundamentals of Undersampling
Increasing ADC SFDR and ENOB using External SHAs
Use of Dither Signals to Increase ADC Dynamic Range
Effect of ADC Linearity and Resolution on SFDR and
Noise in Digital Spectral Analysis Applications
Future Trends in Undersampling ADCs
SECTION 6
MULTICHANNEL APPLICATIONS
Data Acquisition System Considerations
Multiplexing
Filtering Considerations for Data Acquisition Systems
SHA and ADC Settling Time Requirements in Multiplexed Applications
Complete Data Acquisition Systems on a Chip
Multiplexing into Sigma-Delta ADCs
Simultaneous Sampling Systems
Data Distribution Systems using Multiple DACs
SECTION 7
OVERVOLTAGE EFFECTS ON ANALOG INTEGRATED CIRCUITS
Amplifier Input Stage Overvoltage
Amplifier Output Voltage Phase Reversal
Understanding and Protecting Integrated
Circuits from Electrostatic Discharge (ESD)
SECTION 8
DISTORTION MEASUREMENTS
High Speed Op Amp Distortion
High Frequency Two-Tone Generation
Using Spectrum Analyzers in High Frequency
Low Distortion Measurements
Measuring ADC Distortion using FFTs
FFT Testing
Troubleshooting the FFT Output
Analyzing the FFT Output
SECTION 9
HARDWARE DESIGN TECHNIQUES
Prototyping Analog Circuits
Evaluation Boards
Noise Reduction and Filtering for
Switching Power Supplies
Low Dropout References and Regulators
EMI/RFI Considerations
Sensors and Cable Shielding
1
SECTION 1
SINGLE-SUPPLY AMPLIFIERS
Rail-to-Rail Input Stages
Rail-to-Rail Output Stages
Single-Supply Instrumentation Amplifiers
2
SECTI ON 1
SI NGLE-SUP P LY AMP LI F I ERS
Ad ol f o Ga r ci a
Over t he last sever al year s, single-supply oper at ion has become an incr easingly
impor t ant r equir ement as syst ems get smaller , cheaper , and mor e por t able.
Por t able syst ems r ely on bat t er ies, and t ot al cir cuit power consumpt ion is an
impor t ant and oft en dominant design issue, and in some inst ances, mor e impor t ant
t han cost . This makes low-volt age/low supply cur r ent oper at ion cr it ical; at t he same
t ime, however , accur acy and pr ecision r equir ement s have for ced IC manufact ur er s
t o meet t he challenge of “doing mor e wit h less” in t heir amplifier designs.
SINGLE-SUPPLY AMPLIFIERS
Single Supply Offers:
Lower Power
Battery Operated Portable Equipment
Simplifies Power Supply Requirements
But Watch Out for:
Signal-swings limited, therefore more sensitive
to errors caused by offset voltage, bias current,
finite open-loop gain, noise, etc.
More likely to have noisy power supply because
of sharing with digital circuits
DC coupled, multi-stage single-supply circuits
can get very tricky!
Rail-to-rail op amps needed to maximize signal
swings
In a single-supply applicat ion, t he most immediat e effect on t he per for mance of an
amplifier is t he r educed input and out put signal r ange. As a r esult of t hese lower
input and out put signal excur sions, amplifier cir cuit s become mor e sensit ive t o
int er nal and ext er nal er r or sour ces. Pr ecision amplifier offset volt ages on t he or der
of 0.1mV ar e less t han a 0.04 LSB er r or sour ce in a 12-bit , 10V full-scale syst em. In
a single-supply syst em, however , a "r ail-t o-r ail" pr ecision amplifier wit h an offset
volt age of 1mV r epr esent s a 0.8LSB er r or in a 5V FS syst em, and 1.6LSB er r or in a
2.5V FS syst em.
Fur t her mor e, amplifier bias cur r ent s, now flowing in lar ger sour ce r esist ances t o
keep cur r ent dr ain fr om t he bat t er y low, can gener at e offset er r or s equal t o or
gr eat er t han t he amplifier ’s own offset volt age.
Gain accur acy in some low volt age single-supply devices is also r educed, so device
select ion needs car eful consider at ion. Many amplifier s having open-loop gains in t he
millions t ypically oper at e on dual supplies: for example, t he OP07 family t ypes.
However , many single-supply/r ail-t o-r ail amplifier s for pr ecision applicat ions
3
t ypically have open-loop gains bet ween 25,000 and 30,000 under light loading
(>10kohm). Select ed devices, like t he OPX13 family, do have high open-loop gains
(i.e., >1V/µV).
Many t r ade-offs ar e possible in t he design of a single-supply amplifier : speed ver sus
power , noise ver sus power , pr ecision ver sus speed and power , et c. Even if t he noise
floor r emains const ant (highly unlikely), t he signal-t o-noise r at io will dr op as t he
signal amplit ude decr eases.
Besides t hese limit at ions, many ot her design consider at ions t hat ar e ot her wise
minor issues in dual-supply amplifier s become impor t ant . For example, signal-t o-
noise (SNR) per for mance degr ades as a r esult of r educed signal swing. "Gr ound
r efer ence" is no longer a simple choice, as one r efer ence volt age may wor k for some
devices, but not ot her s. Syst em noise incr eases as oper at ing supply cur r ent dr ops,
and bandwidt h decr eases. Achieving adequat e bandwidt h and r equir ed pr ecision
wit h a somewhat limit ed select ion of amplifier s pr esent s significant syst em design
challenges in single-supply, low-power applicat ions.
Most cir cuit designer s t ake "gr ound" r efer ence for gr ant ed. Many analog cir cuit s
scale t heir input and out put r anges about a gr ound r efer ence. In dual-supply
applicat ions, a r efer ence t hat split s t he supplies (0V) is ver y convenient , as t her e is
equal supply headr oom in each dir ect ion, and 0V is gener ally t he volt age on t he low
impedance gr ound plane.
In single-supply/r ail-t o-r ail cir cuit s, however , t he gr ound r efer ence can be chosen
anywher e wit hin t he supply r ange of t he cir cuit , since t her e is no st andar d t o
follow. The choice of gr ound r efer ence depends on t he t ype of signals pr ocessed and
t he amplifier char act er ist ics. For example, choosing t he negat ive r ail as t he gr ound
r efer ence may opt imize t he dynamic r ange of an op amp whose out put is designed
t o swing t o 0V. On t he ot her hand, t he signal may r equir e level shift ing in or der t o
be compat ible wit h t he input of ot her devices (such as ADCs) t hat ar e not designed
t o oper at e at 0V input .
"RAIL-TO-RAIL" AMPLIFIERS
What exactly is “rail-to-rail”
Does the input common mode range (for guaranteed
CMMR) include: 0V, +Vs, both, or neither?
Output Voltage Swing (how close to the rails can you get
under load?)
Where is “ground”?
Complementary bipolar processes make rail-to-rail inputs
and outputs feasible (within some fundamental physical
limitations)
Implications for precision single-supply instrumentation
amps
4
Ear ly single-supply “zer o-in, zer o-out ” amplifier s wer e designed on bipolar pr ocesses
which opt imized t he per for mance of t he NPN t r ansist or s. The PNP t r ansist or s wer e
eit her lat er al or subst r at e PNPs wit h much poor er per for mance t han t he NPNs.
Fully complement ar y pr ocesses ar e now r equir ed for t he new-br eed of single-
supply/r ail-t o-r ail oper at ional amplifier s. These new amplifier designs do not use
lat er al or subst r at e PNP t r ansist or s wit hin t he signal pat h, but incor por at e par allel
NPN and PNP input st ages t o accommodat e input signal swings fr om gr ound t o t he
posit ive supply r ail. Fur t her mor e, r ail-t o-r ail out put st ages ar e designed wit h bipolar
NPN and PNP common-emit t er , or N-channel/P-channel common-sour ce amplifier s
whose collect or -emit t er sat ur at ion volt age or dr ain-sour ce channel on-r esist ance
det er mine out put signal swing wit h t he load cur r ent .
The char act er ist ics of a single-supply amplifier input st age (common-mode r eject ion,
input offset volt age and it s t emper at ur e coefficient , and noise) ar e cr it ical in
pr ecision, low-volt age applicat ions. Rail-t o-r ail input oper at ional amplifier s must
r esolve small signals, whet her t heir input s ar e at gr ound, or at t he amplifier ’s
posit ive supply. Amplifier s having a minimum of 60dB common-mode r eject ion over
t he ent ir e input common-mode volt age r ange fr om 0V t o t he posit ive supply (V
POS
)
ar e good candidat es. It is not necessar y t hat amplifier s maint ain common-mode
r eject ion for signals beyond t he supply volt ages: what is r equir ed is t hat t hey do not
self-dest r uct for moment ar y over volt age condit ions. Fur t her mor e, amplifier s t hat
have offset volt ages less t han 1mV and offset volt age dr ift s less t han 2µV/°C ar e
also ver y good candidat es for pr ecision applicat ions. Since i nput signal dynamic
r ange and SNR ar e equally if not mor e impor t ant t han out put dynamic r ange and
SNR, pr ecision single-supply/r ail-t o-r ail oper at ional amplifier s should have noise
levels r efer r ed-t o-input (RTI) less t han 5µVp-p in t he 0.1Hz t o 10Hz band.
Since t he need for r ail-t o-r ail amplifier out put st ages is dr iven by t he need t o
maint ain wide dynamic r ange in low-supply volt age applicat ions, a single-supply/r ail-
t o-r ail amplifier should have out put volt age swings which ar e wit hin at least 100mV
of eit her supply r ail (under a nominal load). The out put volt age swing is ver y
dependent on out put st age t opology and load cur r ent , but t he volt age swing of a
good out put st age should maint ain it s r at ed swing for loads down t o 10kohm. The
smaller t he V
OL
and t he lar ger t he V
OH
, t he bet t er . Syst em par amet er s, such as
“zer o-scale” or “full-scale” out put volt age, should be det er mined by an amplifier ’s
V
OL
(for zer o-scale) and V
OH
(for full-scale).
Since t he major it y of single-supply dat a acquisit ion syst ems r equir e at least 12- t o
14-bit per for mance, amplifier s which exhibit an open-loop gain gr eat er t han 30,000
for all loading condit ions ar e good choices in pr ecision applicat ions.
SINGLE-SUP P LY/RAIL-TO-RAI L OP AMP I NP UT STAGES
Wit h t he incr easing emphasis on low-volt age, low-power , and single-supply
oper at ion, t her e is some demand for op amps whose input common-mode r ange
includes both supply r ails. Such a feat ur e is undoubt edly useful in some
applicat ions, but engineer s should r ecognize t hat t her e ar e r elat ively few
applicat ions wher e it is absolut ely essent ial. These should be car efully dist inguished
5
fr om t he many applicat ions wher e common-mode r ange close t o t he supplies or one
t hat includes one of t he supplies is necessar y, but input r ail-r ail oper at ion is not .
In many single-supply applicat ions, it is r equir ed t hat t he input go t o only one of t he
supply r ails (usually gr ound). Amplifier s which will handle zer o-volt input s ar e
r elat ively easily designed using eit her PNP t r ansist or s (see OP90 and t he OPX93 in
Figur e 1.3) or N-channel J FETs (see AD820 family in Figur e 1.4). P-channel J FETs
can be used wher e input s must include t he posit ive supply r ail (but not t he negat ive
r ail) as shown in Figur e 1.4 for t he OP282/OP482.
OP90 AND OPX93 INPUT STAGE ALLOWS
INPUT TO GO TO THE NEGATIVE RAIL
Figure 1.3
In t he FET-input st ages of Figur e 1.4, t he possibilit y exist s for phase r ever sal as
input signals appr oach and exceed t he amplifier ’s linear input common-mode
volt age r anges. As descr ibed in Sect ion 7, int er nal amplifier st ages sat ur at e, for cing
subsequent st ages int o cut off. Depending on t he st r uct ur e of t he input st age, phase
r ever sal for ces t he out put volt age t o one of t he supply r ails. For n-channel J FET-
input st ages, t he out put volt age goes t o t he negat ive out put r ail dur ing phase
r ever sal. For p-channel J FET-input st ages, t he out put is for ced t o t he posit ive
out put r ail. New FET-input amplifier s, like t he AD820 family of amplifier s,
incor por at e design impr ovement s t hat pr event out put volt age phase r ever sal for
signals wit hin t he r at ed supply volt age r ange. Their input st age and second gain
st age even offer pr ot ect ion against out put volt age phase r ever sal for input signals
200mV more posit ive t han t he posit ive supply volt age.
6
AD820/AD822/AD824 INPUT INCLUDES NEGATIVE RAIL,
OP-282/OP-482 INCLUDES POSITIVE RAIL
Figure 1.4
As shown in Figur e 1.5, t r ue r ail-t o-r ail input st ages r equir e t wo long-t ailed pair s,
one of NPN bipolar t r ansist or s (or N-channel FETs), t he ot her of PNP t r ansist or s
(or p-channel FETs). These t wo pair s exhibit different offset s and bias cur r ent s, so
when t he applied input common-mode volt age changes, t he amplifier input offset
volt age and input bias cur r ent does also. In fact , when bot h cur r ent sour ces (I1 and
I2) r emain act ive t hr oughout t he ent ir e input common-mode r ange, amplifier input
offset volt age is t he average offset volt age of t he NPN pair and t he PNP pair . In
t hose designs wher e t he cur r ent sour ces ar e alt er nat ively swit ched off at some
point along t he input common-mode volt age, amplifier input offset volt age is
dominat ed by t he PNP pair offset volt age for signals near t he negat ive supply, and
by t he NPN pair offset volt age for signals near t he posit ive supply.
Amplifier input bias cur r ent , a funct ion of t r ansist or cur r ent gain, is also a funct ion
of t he applied input common-mode volt age. The r esult is r elat ively poor common-
mode r eject ion (CMR), and a changing common-mode input impedance over t he
common-mode input volt age r ange, compar ed t o familiar dual supply pr ecision
devices like t he OP07 or OP97. These specificat ions should be consider ed car efully
when choosing a r ail-r ail input op amp, especially for a non-inver t ing configur at ion.
Input offset volt age, input bias cur r ent , and even CMR may be quit e good over part
of t he common-mode r ange, but much wor se in t he r egion wher e oper at ion shift s
bet ween t he NPN and PNP devices.
7
RAIL-TO-RAIL INPUT STAGE TOPOLOGY
Figure 1.5
Many r ail-t o-r ail amplifier input st age designs swit ch oper at ion fr om one differ ent ial
pair t o t he ot her differ ent ial pair somewher e along t he input common-mode volt age
r ange. Devices like t he OPX91 family and t he OP279 have a common-mode
cr ossover t hr eshold at appr oximat ely 1V below t he posit ive supply. In t hese devices,
t he PNP differ ent ial input st age r emains act ive; as a r esult , amplifier input offset
volt age, input bias cur r ent , CMR, input noise volt age/cur r ent ar e all det er mined by
t he char act er ist ics of t he PNP differ ent ial pair . At t he cr ossover t hr eshold, however ,
amplifier input offset volt age becomes t he aver age offset volt age of t he NPN/PNP
pair s and can change r apidly. Also, amplifier bias cur r ent s, dominat ed by t he PNP
differ ent ial pair over most of t he input common-mode r ange, change polar it y and
magnit ude at t he cr ossover t hr eshold when t he NPN differ ent ial pair becomes
act ive. As a r esult , sour ce impedance levels should be balanced when using such
devices, as ment ioned befor e, t o minimize input bias cur r ent offset s and dist or t ion.
An advant age t o t his t ype of r ail-t o-r ail input st age design is t hat input st age
t r ansconduct ance can be made const ant t hr oughout t he ent ir e input common-mode
volt age r ange, and t he amplifier slews symmet r ically for all applied signals.
Oper at ional amplifier s, like t he OP284/OP484, ut ilize a r ail-t o-r ail input st age design
wher e bot h PNP and NPN t r ansist or pair s ar e act ive t hr oughout t he ent ir e input
common-mode volt age r ange, and t her e is no common-mode cr ossover t hr eshold.
Amplifier input offset volt age is t he aver age offset volt age of t he NPN and t he PNP
st ages. Amplifier input offset volt age exhibit s a smoot h t r ansit ion t hr oughout t he
ent ir e input common-mode volt age r ange because of car eful laser -t r imming of
r esist or s in t he input st age. In t he same manner , t hr ough car eful input st age
cur r ent balancing and input t r ansist or design, amplifier input bias cur r ent s also
exhibit a smoot h t r ansit ion t hr oughout t he ent ir e common-mode input volt age
r ange. The except ion occur s at t he ext r emes of t he input common-mode r ange,
8
wher e amplifier offset volt ages and bias cur r ent s incr ease shar ply due t o t he slight
for war d-biasing of par asit ic p-n junct ions. This occur s for input volt ages wit hin
appr oximat ely 1V of eit her supply r ail.
When both differ ent ial pair s ar e act ive t hr oughout t he ent ir e input common-mode
r ange, amplifier t r ansient r esponse is fast er t hr ough t he middle of t he common-
mode r ange by as much as a fact or of 2 for bipolar input st ages and by a fact or of
t he squar e r oot of 2 for FET input st ages. Input st age t r ansconduct ance det er mines
t he slew r at e and t he unit y-gain cr ossover fr equency of t he amplifier , hence
r esponse t ime degr ades slight ly at t he ext r emes of t he input common-mode r ange
when eit her t he PNP st age (signals appr oaching V
POS
) or t he NPN st age (signals
appr oaching GND) ar e for ced int o cut off. The t hr esholds at which t he
t r ansconduct ance changes occur appr oximat ely wit hin 1V of eit her supply r ail, and
t he behavior is similar t o t hat of t he input bias cur r ent s.
Applicat ions which init ially appear t o r equir e t r ue r ail-r ail input s should be car efully
evaluat ed, and t he amplifier chosen t o ensur e t hat it s input offset volt age, input bias
cur r ent , common-mode r eject ion, and noise (volt age and cur r ent ) ar e suit able. A
t r ue r ail-t o-r ail input amplifier should not gener ally be used if an input r ange which
includes only one r ail is sat isfact or y.
SINGLE-SUP P LY/RAIL-TO-RAI L OP AMP OUTP UT STAGES
The ear liest IC op amp out put st ages wer e NPN emit t er follower s wit h NPN cur r ent
sour ces or r esist ive pull-downs, as shown in Figur e 1.6. Nat ur ally, t he slew r at es
wer e gr eat er for posit ive-going t han for negat ive-going signals. While all moder n op
amps have push-pull out put st ages of some sor t , many ar e st ill asymmet r ical, and
have a gr eat er slew r at e in one dir ect ion t han t he ot her . This asymmet r y, which
gener ally r esult s fr om t he use of IC pr ocesses wit h bet t er NPN t han PNP
t r ansist or s, may also r esult in t he abilit y of t he out put t o appr oach one supply mor e
closely t han t he ot her .
In many applicat ions, t he out put is r equir ed t o swing only t o one r ail, usually t he
negat ive r ail (i.e., gr ound in single-supply syst ems). A pulldown r esist or t o t he
negat ive r ail will allow t he out put t o appr oach t hat r ail (pr ovided t he load impedance
is high enough, or is also gr ounded t o t hat r ail), but only slowly. Using an FET
cur r ent sour ce inst ead of a r esist or can speed t hings up, but t his adds complexit y.
9
OP AMP OUTPUT STAGES USING
COMPLEMENTARY DEVICES ALLOW PUSH-PULL DRIVE
Figure 1.6
An IC pr ocess wit h r elat ively well-mat ched (AC and DC) PNP and NPN t r ansist or s
allows bot h t he out put volt age swing and slew r at e t o be r easonably well mat ched.
However , an out put st age using BJ Ts cannot swing complet ely t o t he r ails, but only
t o wit hin t he t r ansist or sat ur at ion volt age (V
CESAT
) of t he r ails (see Figur e 1.7).
For small amount s of load cur r ent (less t han 100µA), t he sat ur at ion volt age may be
as low as 5 t o 10mV, but for higher load cur r ent s, t he sat ur at ion volt age can
incr ease t o sever al hundr ed mV (for example, 500mV at 50mA).
On t he ot her hand, an out put st age const r uct ed of CMOS FETs can pr ovide t r ue
r ail-t o-r ail per for mance, but only under no-load condit ions. If t he out put must
sour ce or sink cur r ent , t he out put swing is r educed by t he volt age dr opped acr oss
t he FETs int er nal "on" r esist ance (t ypically, 100ohms).
10
RAIL-TO-RAIL OUTPUT STAGE SWING
IS LIMITED BY Vcesat, Ron, AND LOAD CURRENT
Figure 1.7
In summar y, t he following point s should be consider ed when select ing amplifier s for
single-supply/r ail-t o-r ail applicat ions:
First , input offset volt age and input bias current s can be a funct ion of t he applied
input common-mode volt age (for t rue rail-t o-rail input op amps). Cir cuit s using t his
class of amplifier s should be designed t o minimize r esult ing er r or s. An inver t ing
amplifier configur at ion wit h a false gr ound r efer ence at t he non-inver t ing input
pr event s t hese er r or s by holding t he input common-mode volt age const ant . If t he
inver t ing amplifier configur at ion cannot be used, t hen amplifier s like t he
OP284/OP484 which do not exhibit any common-mode cr ossover t hr esholds should
be used.
S econd, since input bias current s are not always small and can exhibit different
polarit ies, source impedance levels should be carefully mat ched t o minimize
addit ional input bias current -induced offset volt ages and increased dist ort ion.
Again, consider using amplifier s t hat exhibit a smoot h input bias cur r ent t r ansit ion
t hr oughout t he applied input common-mode volt age.
Third, rail-t o-rail amplifier out put st ages exhibit load-dependent gain which
affect s amplifier open-loop gain, and hence closed-loop gain accuracy. Amplifier s
wit h open-loop gains gr eat er t han 30,000 for r esist ive loads less t han 10kohm ar e
good choices in pr ecision applicat ions. For applicat ions not r equir ing full r ail-r ail
swings, device families like t he OPX13 and OPX93 offer DC gains of 0.2V/µV or
mor e.
Lastly, no matter what claims are made, rail-to-rail output voltage swings are
funct ions of t he amplifier’s out put st age devices and load current. The sat ur at ion
volt age (V
CESAT
), sat ur at ion r esist ance (R
SAT
), and load cur r ent all affect t he
amplifier out put volt age swing.
11
These consider at ions, as well as t hose r egar ding r ail-t o-r ail pr ecision, have
implicat ions in many cir cuit s, namely inst r ument at ion amplifier s, which will be
cover ed in t he next sect ions.
THE TWO OP AMP I NSTRUMENTATI ON AMP LIFIER
TOP OLOGY
Ther e ar e sever al cir cuit t opologies for inst r ument at ion amplifier cir cuit s suit able
for single-supply applicat ions. The t wo op amp configur at ion is oft en used in cost -
and space-sensit ive applicat ions, wher e t ight mat ching of input offset volt age, input
bias cur r ent s, and open-loop gain is impor t ant . Also, when compar ed t o ot her
t opologies, t he t wo op amp inst r ument at ion amplifier cir cuit offer s t he lowest power
consumpt ion and low t ot al dr ift for moder at e-gain (G=10) applicat ions. Obviously, it
also has t he mer it of using a single dual op amp IC.
Figur e 1.8 shows t he t opology of a t wo op amp inst r ument at ion cir cuit which uses a
5t h gain-set t ing r esist or , R
G
. This addit ional gain-set t ing r esist or is opt ional, and
should be used in t hose applicat ions wher e a fine gain t r im is r equir ed. It s effect will
be included in t his analysis.
Cir cuit r esist or values for t his t opology can be det er mined fr om Equat ions 1.1
t hr ough 1.3, wher e R1 = R4. To maint ain low power consumpt ion in single-supply
applicat ions, values for R should be no less t han 10kohms:
R1 = R4 = R Eq. 1.1
R2 = R3 =
R
0.9G –1
Eq. 1.2
R
G
=
2R
0.06G
Eq. 1.3
wher e G equals t he desir ed cir cuit gain. Not e t hat in t hose applicat ions wher e fine
gain t r imming is not r equir ed, Eq. 1.2 r educes t o:
R2 = R3 =
R
G–1
Eq. 1.4
A nodal analysis of t he t opology will illust r at e t he behavior of t he cir cuit ’s nodal
volt ages and t he amplifier out put cur r ent s as funct ions of t he applied common-
mode input volt age (V
CM
), t he applied differ ent ial (signal) volt age (V
IN
), and t he
out put r efer ence volt age (V
REF
). These expr essions ar e summar ized in Equat ions
1.5 t hr ough 1.8, Eq. 1.12, and in Eq. 1.13 for posit ive, input differ ent ial volt ages. Due
t o t he st r uct ur e of t he t opology, expr essions for volt ages and cur r ent s ar e similar in
for m and magnit ude for negat ive, input differ ent ial volt ages.
12
Fr om t he figur e, expr essions for t he four nodal volt ages A, B, C, and V
OUT
as well
as t he out put st age cur r ent s of A1 (I
OA1
) and A2 (I
OA2
) have been developed. Not e
t hat t he dir ect ion of t he amplifier out put cur r ent s, I
OA1
and I
OA2
, is defined t o be
int o t he amplifier ’s out put st age. For example, if t he nodal analysis shows t hat I
OA1
and I
OA2
ar e posit ive ent it ies, t heir dir ect ion is int o t he device; t hus, t heir out put
st ages ar e sinking cur r ent . If t he analysis shows t hat t hey ar e negat ive quant it ies,
t heir dir ect ion is opposit e t o t hat shown; t her efor e, t heir out put st ages ar e sourcing
cur r ent .
Resist or s R
P1
and R
P2
at t he input s t o t he cir cuit ar e opt ional input cur r ent limit ing
r esist or s used t o pr ot ect t he amplifier input st ages against input over volt age.
Alt hough any r easonable value can be used, t hese r esist or s should be less t han
1kohm t o pr event t he unwant ed effect s of addit ional r esist or noise and bias
cur r ent -gener at ed offset volt ages. For pr ot ect ion against a specific level of
over volt age, t he int er est ed r eader should consult t he sect ion on over volt age effect s
on int egr at ed cir cuit s, found in Sect ion 7 of t his book.
THE TWO OP AMP INSTRUMENTATION AMPLIFIER
TOPOLOGY IN SINGLE-SUPPLY APPLICATIONS
Figure 1.8
Using half-cir cuit concept s and t he pr inciple of super posit ion, t he input signal
volt age, V
IN-
,on t he non-inver t ing input of A1 is set t o zer o. Since t he input signal,
V
IN+
, is applied t o t he non-inver t ing t er minal of A2, an expr ession for t he nodal
volt age at t he inver t ing t er minal of A1 is given by Eq. 1.5:
V
A
=V
CM
Eq. 1.5
An expr ession for t he out put volt age of A1 (node B) shows t hat it is dependent on
all t hr ee ext er nally applied volt ages (V
IN
, V
CM
, and V
REF
), and is illust r at ed in Eq.
1.6:
V
B
–V
IN +
R2
R
G
+ V
CM
1+
R2
R1
– V
REF
·
|
.

`
,

|
.

`
,

|
.

`
,

( )
R
R
2
1
Eq. 1.6
13
Since t he input signal, V
IN+
,as well as t he applied input common-mode volt age,
V
CM
, is applied t o t he non-inver t ing t er minal of A2, t hen t he expr ession for t he
volt age at A2’s inver t ing input (node C) is given by:
V
C
V
CM
· +
+
V
IN
Eq. 1.7
For t he case wher e R1 = R4 and R2 = R3, combining t he r esult s in Eq. 1.5, 1.6, and
1.7 yields t he familiar expr ession for t he cir cuit ’s out put volt age:
V
OUT
=(V
IN +
1+
R4
R3
+
2R4
R
G
+ V
REF
)
|
.

`
,
Eq. 1.8
At t his point , it is wor t h not ing t he behavior of t he cir cuit ’s nodal volt ages based on
t he applied ext er nal volt ages. Fr om Eq. 1.5 and Eq. 1.7, t he common-mode
component of t he cur r ent t hr ough R
G
is equal t o zer o, wher eas t he full differ ent ial
input volt age appear s acr oss it . Fur t her mor e, Eq. 1.6 has shows t hat A1 amplifies
t he applied common-mode input volt age by a fact or of (1 + R2/R1). In low-gain
applicat ions, t he r at io of R2 t o R
G
can be as small as 1:1 (for cir cuit gains gr eat er
t han or equal t o 2). Ther efor e, Equat ion 1.6 set s t he upper bound on t he input
common-mode volt age in low-gain applicat ions. If t he out put of A1 is allowed t o
sat ur at e at high input common-mode volt ages, t hen it will not have enough
“headr oom” t o amplify t he input signal, as shown in Eq. 1.6. Ther efor e, in or der for
A1 t o amplify accur at ely input signal volt ages for any cir cuit gain > 1 (cir cuit gains
equal t o 1 ar e not per mit t ed in t his t opology) r equir es t hat an upper bound on t he
t ot al applied input volt age (common-mode plus differ ent ial-mode volt ages) be
det er mined t o pr event amplifier out put volt age sat ur at ion. This upper bound can be
det er mined by t he desir ed cir cuit gain, G, and t he amplifier 's minimum out put high
volt age:
V
IN(TOTAL)
< V
OH(MIN)
0.9G–1
0.9G
– V
IN +
|
.

`
,

Eq. 1.9
In a similar fashion, a lower bound on t he t ot al applied input volt age is also
det er mined by cir cuit gain and t he amplifier ’s maximum out put low volt age:
V
IN(TOTAL)
> V
OL(MAX)
0.9G –1
0.9G
+ V
IN +
|
.

`
,

Eq. 1.10
For example, if a r ail-t o-r ail oper at ional amplifier exhibit ed a V
OL(MAX)
equal t o
10mV and a V
OH(MIN)
equal t o 4.95V, and if t he applicat ion r equir ed a cir cuit gain
of 10 t o pr oduce a 1V full-scale out put , t hen t he t ot al input volt age r ange would be
bounded by:
0.109 V < V
IN(TOTAL)
< 4.3 V
14
Ther efor e, t he r ange over which t he cir cuit will handle input volt ages wit hout
amplifier out put volt age sat ur at ion is given by:
V
OL(MAX)
0.9G –1
0.9G
+ V
IN +
< V
IN(TOTAL)
< V
OH(MIN)
0.9G–1
0.9G
– V
IN +
|
.

`
,

|
.

`
,

Eq. 1.11
In low-gain inst r ument at ion cir cuit s, t he usable input volt age r ange is limit ed and
asymmet r ic about t he supply mid-point volt age. To complet e t he nodal analysis of
t he t wo op amp inst r ument at ion cir cuit , expr essions for oper at ional amplifier out put
st age cur r ent s ar e shown in Equat ions 1.12 and 1.13:
( ) I
OA1
=(V
IN +
2
R
G
+
1
R3
+ V
REF
– V
CM
2
R1
)
|
.

`
,

|
.

`
,

Eq. 1.12
( ) I
OA2
= (–V
IN +
2
R
G
+
1
R3
+ V
CM
– V
REF
1
R4
)
|
.

`
,

|
.

`
,

Eq. 1.13
Equat ion 1.12 illust r at es t hat A1’s out put st age must be able t o sink cur r ent as a
funct ion of t he applied differ ent ial input volt age and t he out put r efer ence volt age.
On t he ot her hand, A1’s out put st age is r equir ed t o sour ce cur r ent over t he ent ir e
input volt age r ange. In t he single-supply case where t he circuit is required t o sense
small differential signals near ground, Eq. 1.6 and Eq. 1.12 both illustrate that A1’s
out put st age is required t o sink current while t rying t o maint ain a more negat ive
out put volt age t han it s own negat ive supply. A1 is t hus forced int o sat urat ion.
As shown in Eq. 1.13, A2’s out put st age sour ces cur r ent for posit ive differ ent ial
input volt ages wit h no differ ent ial or common-mode volt age const r aint s placed upon
it s out put by Eq. 1.8. Not e, however, t hat as a funct ion of t he applied common-mode
volt age, A2 is required t o sink current . Unfort unat ely, in t he absence of an input
signal, Eq. 1.13 shows that A2’s output stage may be forced into saturation, trying
t o sink current while maint aining it s out put volt age at V
OL
.
To cir cumvent t he cir cuit t opological and amplifier out put volt age limit at ions, a
r efer ence volt age should be used t o bias t he out put of t he cir cuit (A2’s out put ) in t he
middle of it s out put volt age swing, and not at exact ly one-half t he supply volt age:
V
REF
=
V
OH(MIN)
+ V
OL(MAX)
2
Eq. 1.14
The out put r efer ence volt age allows t he out put st ages of A1 and A2 t o sink or
sour ce cur r ent wit hout any out put volt age const r aint s. So long as Eq. 1.11 is used t o
define t o t ot al input volt age r ange, t hen amplifier behavior for differ ent ial- and
common-mode oper at ion is linear . To maximize out put signal dynamic r ange and
out put SNR, t he gain of t he inst r ument at ion amplifier cir cuit should be set
accor ding t o Eq. 1.15:
15
Circuit Ga in =
V
OH(MIN)
– V
OL(MAX)
2 V
IN(MAX)

Eq. 1.15
Under t hese oper at ing condit ions, t he differ ent ial out put volt age of t he
inst r ument at ion amplifier cir cuit is now measur ed r elat ive t o V
REF
and not t o
GND. Thus, negat ive full-scale input signals pr oduce out put volt ages near A2’s V
OL
,
and posit ive full-scale signals pr oduce out put volt ages near A2’s V
OH
. Ther efor e,
t he cir cuit 's input common-mode r ange and out put dynamic r ange ar e opt imized in
t er ms of t he desir ed cir cuit gain and amplifier out put volt age char act er ist ics.
For minimal impact of amplifier out put load cur r ent s on V
OH
and V
OL
, cir cuit
r esist or values should be gr eat er t han 10kohm in most single-supply applicat ions.
Thus, Equat ions 1.11, 1.14, and 1.15 can all be used t o design accur at e and
r epeat able t wo op amp inst r ument at ion amplifier cir cuit s wit h single-supply/r ail-t o-
r ail oper at ional amplifier s.
One fundament al limit at ion of t he t wo operat ional amplifier inst rument at ion
circuit is t hat since t he t wo amplifiers are operat ing at different closed-loop gains
(and t hus at different bandwidt hs), t here will be generally poor AC common-mode
rejection without the use of an AC CMR trim capacitor. For optimal AC CMR
performance, a t rimming capacit or should be connect ed bet ween t he invert ing
t erminal of A1 t o ground.
A TWO OP AMP , FET-I NP UT I NSTRUMENTATI ON
AMP LIFIER
Figur e 1.9 illust r at es a t wo op amp inst r ument at ion amplifier using t he AD822, a
dual J FET-input , r ail-t o-r ail out put oper at ional amplifier . The out put offset volt age
is set by V
REF
.
16
A SINGLE-SUPPLY, PROGRAMMABLE, FET-INPUT
INSTRUMENTATION AMPLIFIER
Figure 1.9
Dual oper at ional amplifier s, like t he AD822, make t hese t ypes of inst r ument at ion
amplifier s bot h cost - and power -efficient . In fact , when oper at ing on a single, +3 V
supply, t ot al cir cuit power consumpt ion is less t han 3.5mW. The AD822’s 2pA bias
cur r ent s minimize offset er r or s caused by unbalanced sour ce impedances.
Cir cuit per for mance is enhanced dr amat ically by t he use of a mat ched r esist or
net wor k. A t hin-film r esist or ar r ay set s t he cir cuit gain t o eit her 10 or 100 t hr ough
a DPDT (double-pole, double-t hr ow) swit ch. The ar r ay’s r esist or s ar e laser -t r immed
for a r at io mat ch of 0.01%, and exhibit a maximum differ ent ial t emper at ur e
coefficient of 5ppm/°C. Not e t hat in t his applicat ion cir cuit , t he fift h gain-set t ing
r esist or is not used. The use of t his gain t r im r esist or would int r oduce ser ious gain
and linear it y er r or s due t o t he r esist ance of t he double-pole, double-t hr ow swit ches.
A per for mance summar y and t r ansient r esponse of t his inst r ument at ion amplifier is
shown in Figur e 1.10. Not e t hat t he small-signal bandwidt h of t he cir cuit is
independent of supply volt age, and t hat t he r ail-t o-r ail out put pulse r esponse is well-
behaved. For gr eat er bandwidt h at t he expense of higher supply cur r ent , t he
funct ionally similar AD823 can also be used.
17
PERFORMANCE SUMMARY OF AD822 IN-AMP
Figure 1.10
THE THREE OP AMP I NSTRUMENTATI ON AMP LIFIER
TOP OLOGY
For t he highest pr ecision and per for mance, t he t hree op amp inst r ument at ion
amplifier t opology is opt imum for br idge and ot her offset t r ansducer applicat ions
wher e high accur acy and low nonlinear it y ar e r equir ed. This is at t he expense of
addit ional power consumpt ion over t he t wo op amp inst r ument at ion cir cuit (3
amplifier s ver sus 2 amplifier s). Fur t her mor e, like t he t wo op amp configur at ion, t he
input amplifier s can use one dual op amp for t ight mat ching of input offset volt age
mat ching, input bias cur r ent , and open-loop gain. Or , a single quad oper at ional
amplifier can be used for t he whole cir cuit , including a r efer ence volt age buffer , if
r equir ed.
Single-supply/r ail-t o-r ail amplifier s can be used in t his t opology, like t hat shown for
t wo op amp designs, if t he out put char act er ist ics of t he single-supply/r ail-t o-r ail
amplifier s ar e under st ood. As shown in Figur e 1.11, a gener alized, compr ehensive
analysis of t he st r uct ur e will illust r at e t he behavior of t he nodal volt ages and
amplifier out put cur r ent s as funct ions of t he applied common-mode input volt age
(V
CM
), t he applied differ ent ial (signal) volt age (V
IN
), and t he out put r efer ence
volt age (V
REF
). As shown in Eq. 1.16 t hr ough 1.27, t he nodal analysis was car r ied
out for posit ive-input differ ent ial volt ages; because of t he symmet r y in t he cir cuit ,
t he expr essions for t he nodal volt ages and amplifier out put cur r ent s car r ied out for
negat ive-input differ ent ial volt ages ar e ident ical.
18
THE UBIQUITOUS 3 OP AMP INSTRUMENTATION
AMPLIFIER IN SINGLE-SUPPLY APPLICATIONS
Figure 1.11
Using half-cir cuit concept s and t he pr inciple of super posit ion, t he signal volt age
applied t o t he non-inver t ing t er minal of A1 is set t o zer o. Since t he input signal is
applied t o t he non-inver t ing t er minal of A2, t hen an expr ession for t he out put
volt age of amplifier A1 (node A) for posit ive, differ ent ial input signals is given by Eq.
1.16:
V
A
=(–V
IN +
R1
R
G
+ V
CM
)
|
.

`
,
Eq. 1.16
Since t he volt age at t he inver t ing input of A1 must equal t he volt age at it s non-
inver t ing t er minal, t hen an expr ession for t he volt age at amplifier A1’s inver t ing
t er minal (node B) is given by Eq. 1.17:
V
B
= V
CM
Eq. 1.17
In a similar manner , t he volt age at A2’s inver t ing t er minal must equal t he volt age
on A2’s non-inver t ing t er minal:
V
C
= V
IN +
+ V
CM
Eq. 1.18
The expr ession for t he out put volt age of A2 (node D) shows t hat it is dependent
upon bot h t he input signal and t he applied input common-mode volt age:
V
D
=(V
IN +
R2
R
G
+ V
CM
) 1 +
|
.

`
,
Eq. 1.19
At t his point , it is wor t h not ing t he behavior of t he nodal volt ages of t he input
amplifier s as funct ions of t he applied differ ent ial input volt age and t he input
common-mode volt age. Fr om Eqs. 1.17 and 1.18, t he common-mode component of
19
t he cur r ent t hr ough t he gain set t ing r esist or , R
G
,is zer o – t he input st ages simply
buffer t he applied input common-mode volt age. In ot her wor ds, t he input st age
common-mode gain is unity.
On t he ot her hand, t he full differ ent ial input volt age appear s acr oss R
G
. In fact , Eq.
1.16 shows t hat A1 mult iplies and inver t s t he input differ ent ial volt age by a fact or of
(– R1/R
G
), while Eq. 1.19 shows t hat A2 mult iplies t he input volt age by a fact or of
(1+ R1/R
G
). For t he case wher e t he out put subt r act or st age is configur ed for a gain
of 1, all t he differ ent ial gain is set in t he input st age. Ther efor e, t he r at io of R1 t o
R
G
(or R2 t o R
G
) could be as small as 1:1 or as lar ge as 5000:1. Ther efor e, t o avoid
input amplifier out put volt age sat ur at ion r equir es an upper and a lower bound be
placed on t he t ot al input volt age (defined t o be common-mode plus differ ent ial-mode
volt ages). These bounds ar e set by t he gain of t he inst r ument at ion amplifier and t he
out put high and low volt age limit s of t he amplifier . The lower bound on t he t ot al
applied input volt age is given by Eq. 1.20:
V
IN(TOTAL)
> V
OL(MAX)
+
G-1
2
(V
IN +
|
.

`
,

) Eq. 1.20
An upper bound on t he t ot al input volt age can be det er mined in a similar fashion
and is also dependent on t he cir cuit gain and t he amplifier ’s minimum out put high
volt age:
V
IN(TOTAL)
< V
OH(MIN)

G+ 1
2
(V
IN +
|
.

`
,

) Eq. 1.21
For example, if a r ail-t o-r ail oper at ional amplifier exhibit ed a V
OL(MAX)
equal t o
10mV and a V
OH(MIN)
equal t o 4.95V, and if t he applicat ion r equir ed a cir cuit gain
of 10 for a 1V full-scale out put , t hen t he t ot al input volt age r ange would be bounded
by:
0.46 V < V
IN(TOTAL)
< 4.4 V
Ther efor e, for t he t hr ee op amp inst r ument at ion cir cuit , t he t ot al applied input
volt age r ange expr essed in t er ms of cir cuit gain and amplifier out put volt age limit s
is given by:
V
OL(MAX)
+
G- 1
2
(V
IN +
) < V
IN(TOTAL)
< V
OH(MIN)

G+1
2
(V
IN +
|
.

`
,

|
.

`
,

)
Eq. 1.22
20
Since t he non-inver t ing input of t he subt r act or amplifier A3 det er mines t he volt age
on it s inver t ing t er minal, an expr ession for t he volt ages at Nodes E and F is given
by Eq. 1.23:
V
E
= V
F
=(V
IN +
R6
R4 + R6
R2
R
G
+ V
CM
R6
R4 + R6
+ V
REF
R4
R4 + R6
)
|
.

`
,

+
|
.

`
,

|
.

`
,

|
.

`
,

1
Eq. 1.23
For t he case wher e R3, R4, R5, and R6 ar e all equal t o R (t ypically t he case for
inst r ument at ion amplifier gains gr eat er t han or equal t o 1), t hen t hese nodal
volt ages will set up at one-half t he applied out put volt age r efer ence (V
REF
) and at
one-half t he applied input common-mode volt age (V
CM
). Fur t her mor e, t he
component due t o t he amplified differ ent ial input signal is also at t enuat ed by a
fact or of t wo. Finally, Eq. 1.24 shows an expr ession for t he cir cuit ’s out put volt age in
it s familiar for m for R4 = R3 and R6 = R5:
V
OUT
=(V
IN +
R5
R3
2R1
R
G
+ V
REF
)
|
.

`
,

+
|
.

`
,
1 Eq. 1.24
Fr om Eq. 1.24, t he cir cuit out put volt age is only a funct ion of t he amplified input
differ ent ial volt age and t he out put r efer ence volt age. Pr ovided t hat R4 = R3 and R6
= R5, t he component of t he out put volt age due t o t he applied input common-mode
volt age is complet ely suppr essed. The only r emaining er r or volt age is t hat due t o
t he finit e CMR of A3 and t he r at io mat ch of R3 t o R5 and R4 t o R6. Also, in t he
absence of eit her an input signal or an out put r efer ence volt age, A3’s out put volt age
is equal t o zer o; in a single-supply applicat ion wher e r ail-t o-r ail out put amplifier s ar e
used, it is equal t o V
OL
.
To complet e t he analysis of t his inst r ument at ion cir cuit , expr essions for oper at ional
amplifier out put st age cur r ent s have been developed and ar e shown in Eqs. 1.25
t hr ough 1.27:
I
OA1
=
V
IN +
R1
R
G
1+
R3
R1
+ 1+
R2
R
G
R4
R4 + R6
+
V
REF
-V
CM
R3
R4
R4 + R6 R3
|
.

`
,

|
.

`
,

|
.

`
,

|
.

`
,

|
.

`
,

]
]
]
]
|
.

`
,

Eq. 1.25
I
OA2
= (–V
IN +
1 +
R2
R
G
1
R2
+
1
R4

1
R4
R6
R4 + R6

1
R2
+
V
REF
– V
CM
R4 + R6
)
|
.

`
,

|
.

`
,

]
]
]
|
.

`
,

¹
'
¹
¹
¹
¹
'
¹
¹
¹
Eq. 1.26
21
I
OA3
=
V
IN +
)
3 + R5
R1
R
G
+
R5
R3
+
2 R1 R5
R3 R
G
+
V
CM
V
REF
R3 + R5

⋅ ⋅

|
.

`
,


(
R
Eq. 1.27
Recall in t he analysis of t he t wo-amplifier inst r ument at ion cir cuit t hat amplifier
out put st age cur r ent s wer e defined t o be posit ive, if cur r ent flow is int o t he device,
t he amplifier is sinking cur r ent . Conver sely, if t he nodal analysis shows t hat out put
cur r ent s ar e negat ive quant it ies, t hen cur r ent flow is out of t he amplifier , and t he
amplifier is sourcing cur r ent .
Equation 1.25 illustrates that A1’s output stage must be able to sink current as a
funct ion of t he applied different ial input volt age and t he out put reference volt age.
On t he ot her hand, A1’s out put st age is required t o source current t hroughout t he
applied common-mode volt age. In t he single-supply case where t he circuit is
required to sense small differential signals near ground, Eq. 1.16 and Eq. 1.25 both
illust rat e t hat A1’s out put st age is required t o sink current while t rying t o maint ain
a more negat ive out put volt age t han it s own negat ive supply. A1 cannot sust ain
t his operat ing point , and t hus is forced int o out put sat urat ion.
As shown in Eq. 1.26, A2’s out put st age sour ces cur r ent for posit ive input signal
volt ages wit h no differ ent ial nor common-mode volt age const r aint s placed upon it s
out put by Eq. 1.19. A3’s out put st age is also r equir ed t o sour ce cur r ent ar ound it s
feedback r esist or as a funct ion of t he posit ive input differ ent ial volt age. Not e,
however , t hat as a funct ion of t he applied common-mode volt age, it is r equir ed t o
sink cur r ent . Unfort unat ely Eq. 1.24 showed t hat in t he absence of an input signal,
A3’s out put st age can be forced int o sat urat ion, t rying t o sink current while
maintaining its output voltage at A3’s V
OL
.
To cir cumvent cir cuit t opological and amplifier out put volt age limit at ions, t he r esult s
shown in Eq. 1.14 and Eq. 1.15 for t he t wo op amp inst r ument at ion cir cuit apply
equally well her e. The out put r efer ence volt age is chosen in t he middle of A1 and
A2’s out put volt age swing:
V
REF
=
V
OH(MIN)
+ V
OL(MAX)
2
Eq. 1.14
Similar ly, out put signal dynamic r ange and out put SNR ar e maximized if t he gain of
t he inst r ument at ion cir cuit is set accor ding t o Eq. 1.15:
Circuit Ga in =
V
OH(MIN)
– V
OL(MAX)
2 V
IN(MAX)

Eq. 1.15
Under t hese oper at ing condit ions, t he differ ent ial out put volt age of t he
inst r ument at ion amplifier cir cuit is now measur ed r elat ive t o V
REF
and not t o
GND. Thus, negat ive full-scale input signals yield out put volt ages near A3’s V
OL
,
and posit ive full-scale signals pr oduce out put volt ages near A3’s V
OH
. Thus, cir cuit
input common-mode r ange and out put dynamic r ange ar e opt imized in t er ms of t he
desir ed cir cuit gain and amplifier out put volt age char act er ist ics.
22
For minimal impact on V
OH
and V
OL
due t o amplifier out put load cur r ent s, cir cuit
r esist or values should be gr eat er t han 10kohm in single-supply applicat ions. Thus,
Equat ions 1.22, 1.14, and 1.15 can all be used t o design accur at e and r epeat able
t hr ee op amp inst r ument at ion amplifier cir cuit s wit h single-supply/r ail-t o-r ail
oper at ional amplifier s.
A COMP OSI TE, SINGLE-SUP P LY I NSTRUMENTATI ON
AMP LIFIER [3]
As it has been shown t hr oughout t his chapt er , oper at ion of high per for mance linear
cir cuit s fr om a single, low-volt age supply (5V or less) is a common r equir ement .
While t her e ar e many pr ecision single supply oper at ional amplifier s (some r ail-r ail),
such as t he OP213, t he OP291, and t he OP284, and some good single-supply
inst r ument at ion amplifier s, such as t he AMP04 and t he AD626 (bot h cover ed lat er ),
t he highest per for mance inst r ument at ion amplifier s ar e st ill specified for dual-
supply oper at ion.
One way t o achieve bot h high pr ecision and single-supply oper at ion t akes
advant age of t he fact t hat sever al popular t r ansducer s (e.g. st r ain gauges) pr ovide
an out put signal cent er ed ar ound t he (appr oximat e) mid-point of t he supply volt age
(or t he r efer ence volt age), wher e t he input s of t he signal condit ioning amplifier
need not oper at e near “gr ound” or t he posit ive supply volt age.
Under t hese condit ions, a dual-supply inst r ument at ion amplifier r efer enced t o t he
supply mid-point followed by a “r ail-t o-r ail” oper at ional amplifier gain st age pr ovides
ver y high DC pr ecision. Figur e 1.12 illust r at es one such high-per for mance
inst r ument at ion amplifier oper at ing on a single, +5V supply. This cir cuit uses an
AD620 low-cost pr ecision inst r ument at ion amplifier for t he input st age, and an
AD822 J FET-input dual r ail-t o-r ail out put oper at ional amplifier for t he out put st age.
A PRECISION SINGLE-SUPPLY INSTRUMENTATION
AMPLIFIER WITH RAIL-TO-RAIL OUTPUT
Figure 1.12
23
In t his cir cuit , R1 and R2 for m a volt age divider which split s t he supply volt age in
half t o +2.5V, wit h fine adjust ment pr ovided by a t r imming pot ent iomet er , P1. This
volt age is applied t o t he input of an AD822 which buffer s it and pr ovides a low-
impedance sour ce needed t o dr ive t he AD620’s out put r efer ence por t . The AD620’s
REFERENCE input has a 10kohm input r esist ance and an input signal cur r ent of
up t o 200µA. The ot her half of t he AD822 is connect ed as a gain-of-3 inver t er , so
t hat it can out put ±2.5V, “r ail-t o-r ail,” wit h only ±0.83V r equir ed of t he AD620. This
out put volt age level of t he AD620 is well wit hin t he AD620’s capabilit y, t hus
ensur ing high linear it y for t he “dual-supply” fr ont end. Not e t hat t he final out put
volt age must be measured wit h respect t o t he +2.5V reference, and not t o GND.
The gener al gain expr ession for t his composit e inst r ument at ion amplifier is t he
pr oduct of t he AD620 and t he inver t ing amplifier gains:
GAIN
k
R
G
R
F
R
I
· +
|
.

`
,

|
.

`
,

494
1
. Ω
Eq. 1.28
For t his example, an over all gain of 10 is r ealized wit h R
G
= 21.5kohm (closest
st andar d value). The t able (Figur e 1.13) summar izes var ious R
G
/gain values.
In t his applicat ion, t he t ot al input volt age applied t o t he input s of t he AD620 can be
up t o +3.5V wit h no loss in pr ecision. For example, at an over all cir cuit gain of 10,
t he common-mode input volt age r ange spans 2.25V t o 3.25V, allowing r oom for t he
±0.25V full-scale differ ent ial input volt age r equir ed t o dr ive t he out put ±2.5V about
V
REF
.
The inver t ing configur at ion was chosen for t he out put buffer t o facilit at e syst em
out put offset volt age adjust ment by summing cur r ent s int o t he buffer ’s feedback
summing node. These offset cur r ent s can be pr ovided by an ext er nal DAC, or fr om
a r esist or connect ed t o a r efer ence volt age.
The AD822 r ail-t o-r ail out put st age exhibit s a ver y clean t r ansient r esponse (not
shown) and a small-signal bandwidt h over 100kHz for gain configur at ions up t o 300.
Figur e 1.13 summar izes t he per for mance of t his composit e inst r ument at ion
amplifier . To r educe t he effect s of unwant ed noise pickup, a capacit or is
r ecommended acr oss A2’s feedback r esist ance t o limit t he cir cuit bandwidt h t o t he
fr equencies of int er est . Also, t o pr event t he effect s of input -st age r ect ificat ion, an
opt ional 1kHz filt er is r ecommended at t he input s of t he AD620.
24
PERFORMANCE SUMMARY OF THE +5V SINGLE-SUPPLY
AD620/AD822 COMPOSITE INSTRUMENTATION AMP
WITH RAIL-TO-RAIL OUTPUTS
Figure 1.13
LOW-SI DE AND HI GH-SI DE SI GNAL CONDI TI ONI NG
As pr evious discussions have shown, single-supply and r ail-t o-r ail oper at ional
amplifier s in t wo and t hr ee op amp inst r ument at ion amplifier cir cuit s impose
cer t ain limit s on t he usable input common-mode and out put volt age r anges of t he
cir cuit . Ther e ar e, however , many single-supply applicat ions wher e low- and high-
side signal condit ioning is r equir ed. For t hese applicat ions, novel cir cuit design
t echniques allow sensing of ver y small differ ent ial signals at GND or at V
POS
. Two
such devices, t he AMP04 and AD626, have been designed specifically for t hese
applicat ions.
As illust r at ed in Figur e 1.14, t he AMP04, a single-supply inst r ument at ion amplifier ,
uses a inver t ing-mode out put gain ar chit ect ur e, wher e an ext er nal r esist or , R
G
(connect ed bet ween t he AMP04’s Pins 1 and 8), is used as t he input r esist or t o A4,
and an int er nal 100kohm t hin-film r esist or , R1, ser ves as t he out put amplifier ’s
feedback r esist ance. Unit y-gain input buffer s A1 and A2 bot h ser ve t wo funct ions:
t hey pr esent a high impedance t o t he sour ce, and pr ovide a DC level shift t o t he
applied common-mode input volt age of one V
BE
for amplifier s A3 and A4. As a
r esult , t heir out put st ages can oper at e ver y close t he negat ive supply wit hout
sat ur at ing.
The input buffer s ar e designed wit h PNP t r ansist or s t hat allow t he applied common-
mode volt age r ange t o ext end t o 0V. In fact , t he usable input common-mode volt age
r ange of t he AMP04 act ually ext ends 0.25V below t he negat ive supply (alt hough not
guar ant eed, applied input volt ages t o any int egr at ed cir cuit should always r emain
wit hin it s t ot al supply volt age r ange). On t he ot her hand, since t he input buffer s ar e
PNP st ages, t he input common-mode volt age r ange does not include t he AMP04’s
posit ive supply volt age. When t he input s ar e dr iven wit hin 1V of t he posit ive r ail,
25
t he PNP input t r ansist or s ar e for ced int o cut off; and, as a r esult , input offset
volt ages and bias cur r ent s incr ease, and CMR degr ades.
SINGLE SUPPLY INSTRUMENTATION AMP HANDLES
ZERO-VOLTS INPUT AND ZERO-VOLTS OUTPUT (AMP04)
Figure 1.14
A pulsed-br idge t r ansducer -dr iver /amplifier illust r at es t he ut ilit y of t his low-power ,
single-supply inst r ument at ion amplifier cir cuit as shown in Figur e 1.15. Commonly
available 350ohm st r ain-gauge br idges ar e difficult t o apply in low-volt age, low-
power syst ems for a number of r easons, including t he r equir ement s for high br idge
dr ive cur r ent s and high sensit ivit y. For low-speed measur ement s, power limit at ions
can be over come by oper at ing t he br idge in a pulsed-power mode, r eading t he
amplified out put on a low-speed, low-dut y-cycle basis.
26
A LOW POWER, PULSED LOAD CELL BRIDGE AMPLIFIER
Figure 1.15
In t his cir cuit , an ext er nally gener at ed 800µs TTL/CMOS pulse is applied t o t he
SHUTDOWN input t o t he REF195, a +5V pr ecision volt age r efer ence. The REF195’s
shut down feat ur e is used t o swit ch bet ween a nor mal +5V DC out put if left open (or
at logic HIGH), and a low-power -down st andby st at e (5µA maximum cur r ent dr ain)
wit h t he shut down pin held low. The swit ched 5V out put fr om t he REF195 dr ives
t he br idge and supplies power t o t he AMP04. The AMP04 is pr ogr ammed for a gain
of 20 by t he 4.99kohm r esist or , which should be a st able film t ype (TCR = 50ppm/°C
or bet t er ) in close physical pr oximit y t o t he amplifier . Dynamic per for mance of t he
cir cuit is excellent , because t he AMP04’s out put set t les t o wit hin 0.5mV of it s final
value in about 230µs (not shown).
This appr oach allows fast measur ement speed wit h a minimum st andby power .
Gener ally speaking, wit h all act ive cir cuit r y essent ially being swit ched by t he
measur ement pulse, t he aver age cur r ent dr ain of t his cir cuit is det er mined by it s
dut y cycle. On-st at e cur r ent dr ain is about 15mA fr om t he 6V bat t er y dur ing t he
measur ement int er val (90mW peak power ). Ther efor e, an 800µs measur ement
st r obe once per second will dissipat e an aver age of 72µW, t o which is added t he
30µW st andby power of t he REF195. In any event , over all oper at ion is enhanced by
t he REF195’s low-dr opout r egulat ion char act er ist ics. The REF195 can oper at e wit h
supply volt ages as low as +5.4 V and st ill maint ain +5V out put oper at ion.
If low-fr equency filt er ing is desir ed, an opt ional capacit or can be connect ed bet ween
pins 6 and 8 of t he AMP04. However , a much longer st r obe pulse must be used so
t hat t he filt er can set t le t o t he cir cuit ’s r equir ed accur acy. For example, if a 0.1µF
capacit or is used for noise filt er ing, t hen t he R-C t ime const ant for med wit h t he
AMP04’s int er nal 100kohm r esist or is 10ms. Ther efor e, for a 10-bit set t ling
cr it er ion, 6.9 t ime const ant s, or 70ms, should be allowed. Obviously, t his will place
gr eat er demands upon syst em power , so t r ade-offs may be necessar y in t he amount
of filt er ing used.
27
Of cour se, t he amplified br idge out put appear s only dur ing t he measur ement
int er val, and is valid aft er 220µs unless filt er ing is used. Dur ing t his t ime, a sampled-
input ADC (analog-t o-digit al conver t er ) r eads V
OUT
, eliminat ing t he need for a
dedicat ed sample-and-hold cir cuit t o r et ain t he out put volt age. If 10-bit
measur ement s ar e sufficient , t he 5V br idge dr ive can also be assumed t o be
const ant (for 10-bit accur acy), because t he REF195 exhibit s a ±1mV (±0.02 %)
out put volt age t oler ance. For mor e accur at e measur ement s, a r at iomet r ic r eading
of t he br idge st at us can be obt ained by r eading t he br idge dr ive (V
REF
) as well as
V
OUT
.
On t he ot her hand, single-supply inst r ument at ion amplifier s, like t he AD626, shown
in Figur e 1.16, exhibit an input st age ar chit ect ur e t hat allows t he sensing of small
differ ent ial input signals, not only at it s posit ive supply, but beyond it as well. The
AD626 is a differ ent ial amplifier consist ing of a pr ecision balanced at t enuat or , a ver y
low-dr ift pr eamplifier (A1), and an out put buffer amplifier (A2). It has been
designed so t hat small differ ent ial signals can be accur at ely amplified and filt er ed in
t he pr esence of lar ge common-mode volt ages, wit hout t he use of any ot her ext er nal
act ive or passive component s.
AD626 SCHEMATIC ILLUSTRATES INPUT PROTECTION
AND SCALING RESISTORS AND ALLOWS
INPUT COMMON MODE VOLTAGE UP TO 6 x (Vs - 1V)
Figure 1.16
The simplified equivalent cir cuit in Figur e 1.16 illust r at es t he main element s of t he
AD626. The signal input s at Pins 1 and 8 ar e fir st applied t o t he dual r esist ive
at t enuat or s R1 t hr ough R4, whose pur pose is t o r educe t he peak common-mode
volt age at t he input s of A1. This allows t he applied differ ent ial volt age t o be
accur at ely amplified in t he pr esence of lar ge common-mode volt ages six t imes
gr eat er t han t hat which can be t oler at ed by t he act ual input t o A1. As a r esult , input
common-mode r eject ion ext ends t o 6×(V
s
– 1V). The over all common-mode er r or is
minimized by pr ecise laser t r imming of R3 and R4, t hus giving t he AD626 a
common-mode r eject ion r at io (CMRR) of at least 10,000:1 (80dB).
28
To minimize t he effect of spur ious RF signals at t he input s due t o r ect ificat ion at t he
input s t o A1, small filt er capacit or s C1 and C2, int er nal t o t he AD626, limit t he input
bandwidt h t o 1MHz.
The out put of A1 is connect ed t o t he input of A2 via a 100kohm r esist or (R12) t o
allow t he low-pass filt er ing t o t he signals of int er est . To use t his feat ur e, a capacit or
is connect ed bet ween Pin 4 and t he cir cuit ’s common. Equat ion 1.29 can be used t o
det er mine t he value of t he capacit or , based on t he cor ner fr equency of t his low-pass
filt er :
( )
C
LP
=
1
2 100 k f
LP
π⋅ ⋅ Ω
Eq. 1.29
wher e f
LP
= t he desir ed cor ner fr equency of t he low-pass filt er , in Hz.
The 200kohm input impedance of t he AD626 r equir es t hat t he sour ce r esist ance
dr iving t his amplifier should be less t han 1kohm t o minimize gain er r or . Also, any
mismat ch bet ween t he t ot al sour ce r esist ance of eit her input will affect gain
accur acy and common-mode r eject ion. For example, when oper at ing at a gain of 10,
an 80ohm mismat ch in t he sour ce r esist ance bet ween t he input s will degr ade cir cuit
CMR t o 68dB.
Out put amplifier , A2, oper at es at a gain of 2 or 20, t hus set t ing t he over all,
pr ecalibr at ed gain of t he AD626 (wit h no ext er nal component s) at 10 or 100. The
gain is set by t he feedback net wor k ar ound amplifier A2.
The out put of A2 uses an int er nal 10kohm r esist or t o –V
s
t o “pull down” it s out put .
In single-supply applicat ions wher e –V
s
equals GND, A2’s out put can dr ive a
10kohm gr ound-r efer enced load t o at least +4.7V. The minimum nominal “zer o”
out put volt age of t he AD626 is 30mV.
If pin 7 is left unconnect ed, t he gain of t he AD626 is 10. By connect ing pin 7 t o GND,
t he AD626’s gain can be set t o 100. To adjust t he gain of t he AD626 for gains
bet ween 10 and 100, a var iable r esist ance net wor k can be used bet ween pin 7 and
GND. This var iable r esist ance net wor k includes a fixed r esist or wit h a r heost at -
connect ed pot ent iomet er in ser ies. The int er est ed r eader should consult t he AD626
dat a sheet for complet e det ails for adjust ing t he gain of t he AD626. For t hese
applicat ions, a ±20% adjust ment r ange in t he gain is r equir ed. This is due t o t he on-
chip r esist or s absolut e t oler ance of 20% (t hese r esist or s, however , ar e r at io-
mat ched t o wit hin 0.1%).
An example of t he AD626 high-side sensing capabilit ies, Figur e 1.17 illust r at es a
t ypical cur r ent sensor int er face amplifier . The signal cur r ent is sensed acr oss t he
cur r ent shunt , R
s
. For r easons ment ioned ear lier , t he value of t he cur r ent shunt
should be less t han 1ohm and should be select ed so t hat t he aver age differ ent ial
volt age acr oss t his r esist or is t ypically 100mV. To gener at e a full-scale out put
volt age of +4V, t he AD626 is configur ed in a gain of 40. To accommodat e t he
t oler ance in t he cur r ent shunt , t he var iable gain-set t ing r esist or net wor k shown in
29
t he cir cuit has an adjust ment r ange of ±20%. Not e t hat sufficient headr oom exist s
in t he gain t r im t o allow at least a 10% over r ange (+4.4V).
AD626 HIGH-SIDE CURRENT MONITOR INTERFACE
Figure 1.17
I NSTRUMENTATI ON AMP LIFIER I NP UT-STAGE
RECTIFICATION
A well-known phenomenon in analog int egr at ed cir cuit s is RF r ect ificat ion,
par t icular ly in inst r ument at ion amplifier s and oper at ional amplifier s. While
amplifying ver y small signals, t hese devices can r ect ify unwant ed high-fr equency,
out -of-band signals. The r esult s ar e DC er r or s at t he out put in addit ion t o t he
want ed sensor signal. Unwant ed out -of-band signals ent er sensit ive cir cuit s
t hr ough t he cir cuit 's conduct or s which pr ovide a dir ect pat h for int er fer ence t o
couple int o a cir cuit . These conduct or s pick up noise t hr ough capacit ive, induct ive,
or r adiat ion coupling. Regar dless of t he t ype of int er fer ence, t he unwant ed signal is
a volt age which appear s in ser ies wit h t he input s.
All inst r ument at ion and oper at ional amplifier input st ages ar e eit her emit t er -
coupled (BJ T) or sour ce-coupled (FET) differ ent ial pair s wit h r esist ive or cur r ent -
sour ce loading. Depending on t he quiescent cur r ent level in t he devices and t he
fr equency of t he int er fer ence, t hese differ ent ial pair s can behave as high-fr equency
det ect or s. As it has been shown in [1], t his det ect ion pr ocess pr oduces spect r al
component s at t he har monics of t he int er fer ence as well at DC. It is t he DC
component t hat shift s int er nal bias levels of t he input st ages causing er r or s, which
can lead t o syst em inaccur acies. For a complet e t r eat ment of t his issue, including
analyt ical and empir ical r esult s, t he int er est ed r eader should consult Refer ence [1].
Since it is r equir ed t o pr event unwant ed signals and noise fr om ent er ing t he input
st ages, input filt er ing t echniques ar e used for t hese t ypes of devices. As illust r at ed
in Refer ence [1], t his t echnique uses an equivalent appr oach suggest ed for
oper at ional amplifier s. As shown in Figur e 1.18, low-pass filt er s ar e used in ser ies
30
wit h t he differ ent ial input s t o pr event unwant ed noise fr om r eaching t he input s.
Her e, capacit or s, C
X1
, C
X2
, and C
X3
, connect ed acr oss t he input s of t he
inst r ument at ion amplifier , for m common-mode (C
X1
and C
X2
) and differ ent ial-
mode (C
X3
) low-pass filt er s wit h t he t wo r esist or s, R
X
. Time const ant s R
X
-C
X1
and
R
X
-C
X2
should be well-mat ched (1% or bet t er ), because imbalances in t hese
impedances can gener at e a differ ent ial er r or volt age which will be amplified.
On t he ot her hand, an addit ional benefit of using a differ ent ially-connect ed
capacit or is t hat it can r educe common-mode capacit ive imbalance. This differ ent ial
connect ion helps t o pr eser ve high-fr equency AC common-mode r eject ion. Since
ser ies r esist or s ar e r equir ed t o for m t he low-pass filt er , er r or s due t o poor layout
(CMR imbalance), component t oler ance of R
X
(input bias cur r ent -induced offset
volt age) and r esist or t her mal noise must be consider ed in t he design pr ocess. In
applicat ions wher e t he sensor is an RTD or a r esist ive st r ain gauge, R
X
can be
omit t ed, pr ovided t he sensor is close t o t he amplifier .
EXTERNAL COMMON-MODE AND DIFFERENTIAL-MODE
INPUT FILTERS PREVENT RFI RECTIFICATION IN
INSTRUMENTATION AMPLIFIER CIRCUITS
Figure 1.18
31
REFERENCES
1. Syst ems Ap p li ca t i on Gu i d e , Chapt er 1, pg. 21-55, Analog Devices,
Incor por at ed, Nor wood, MA, 1993.
2. Li n e a r De s i gn Se mi n a r , Sect ion 1, pp. 19-22, Analog Devices,
Incor por at ed, Nor wood, MA, 1995.
3. Lew Count s, Pr oduct Line Dir ect or , Advanced Linear Pr oduct s,
Analog Devices, Incor por at ed, per sonal communicat ion, 1995.
4. Walt J ung, and J ames Wong, Op amp selection minimizes impact of
single-supply design, EDN, May 27, 1993, pp. 119-124.
5. E. J acobsen, and J . Baum, Home-brewed circuit s t ailor sensor out put s
t o specialized needs, EDN, J anuar y 5, 1995, pp. 75-82.
6. Walt J ung, Cor por at e St aff Applicat ions Engineer , Analog Devices,
Incor por at ed, per sonal communicat ion, J anuar y 27, 1995.
7. Walt J ung, Analog-S ignal-Processing Concept s Get More Efficient ,
Ele ct r on i c De s i gn An a log Ap p li ca t i on s I s s u e , J une 24, 1993,
pp. 12-27.
8. C.Kit chin and L.Count s , I n s t r u me n t a t i on Amp li fi e r Ap p li ca t i on
Gu i d e, Analog Devices, Incor por at ed, Nor wood, MA, 1991.
1
SECTION 2
HIGH SPEED OP AMPS
Driving Capacitive Loads
Cable Driving
Single-Supply Considerations
Application Circuits
2
SECTI ON 2
HI GH SP EED OP AMP S
Wa l t J u n g a n d Wa l t Kest er
Moder n syst em design incr easingly makes use of high speed ICs as cir cuit building
blocks. Wit h bandwidt hs going up and up, demands ar e placed on t he designer for
fast er and mor e power efficient cir cuit s. The default high speed amplifier has
changed over t he year s, wit h high speed complement ar y bipolar (CB) pr ocess ICs
such as t he AD846 and AD847 in use just about t en year s at t his wr it ing. Dur ing
t his t ime, t he gener al ut ilit y/availabilit y of t hese and ot her ICs have r aised t he “high
speed” common per for mance denominat or t o 50MHz. The most r ecent ext ended
fr equency complement ar y bipolar (XFCB) pr ocess high speed devices such as t he
AD8001/AD8002, t he AD9631/9632 and t he AD8036/AD8037 now ext end t he
oper at ing r ange int o t he UHF r egion.
Of cour se, a t r adit ional per for mance bar r ier has been speed, or per haps mor e
accur at ely, painless speed. While fast IC amplifier s have been ar ound for some t ime,
unt il mor e r ecent ly t hey simply haven’t been t he easiest t o use. As an example,
devices wit h subst ant ial speed incr eases over 741/301A er a t ypes, namely t he 318-
family, did so at t he expense of r elat ively poor set t ling and capacit ive loading
char act er ist ics. Moder n CB pr ocess par t s like t he AD84X ser ies pr ovide far gr eat er
speed, fast er set t ling, and do so at low user cost . St ill, t he applicat ion of high
per for mance fast amplifier s is never ent ir ely a cookbook pr ocess, so designer s st ill
need t o be war y of many int er -r elat ed key issues. This includes not just t he amplifier
select ion, but also cont r ol of par asit ics and ot her pot ent ially per for mance-limit ing
det ails in t he sur r ounding cir cuit .
It is wor t h under scor ing t hat r easons for t he "speed r evolut ion" lie not just in
affor dabilit y of t he new high speed ICs, but is also r oot ed in t heir ease of use.
Compar ed t o ear lier high speed ICs, CB pr ocess devices ar e gener ally mor e st able
wit h capacit ive loads (wit h higher phase mar gins in gener al), have lower DC er r or s,
consume less power for a given speed, and ar e all ar ound mor e "user fr iendly".
Taking t his a st ep fur t her , XFCB family devices, which ext end t he ut ilit y of t he op
amp t o lit er ally hundr eds of MHz, ar e under st andably less st r aight for war d in t er ms
of t heir applicat ion (as is any amplifier oper at ing over such a r ange). Thus, get t ing
t he most fr om t hese moder n devices definit ely st r esses t he “t ot al envir onment ”
aspect s of design.
Anot her major ease of use feat ur e found in t oday's linear ICs is a much wider r ange
of supply volt age char act er izat ion. While t he older ±15V st andar d is st ill much in
use, t her e is a t r end t owar ds including mor e per for mance dat a at popular lower
volt ages, such as ±5V, or +5V only, single supply oper at ion. The most r ecent devices
using t he lower volt age XFCB pr ocess use supply volt ages of eit her ±5V, or simply
+5V only. The t r end t owar ds lower supply volt ages is unmist akable, wit h a goal of
squeezing t he highest per for mance fr om a given volt age/power cir cuit envir onment .
These "ease of use" design aspect s wit h cur r ent ICs ar e illust r at ed in t his chapt er ,
3
along wit h par asit ic issues, opt imizing per for mance over supply r anges, and low
dist or t ion st ages in a var iet y of applicat ions.
DRI VI NG CAP ACI TI VE LOADS
Fr om syst em and signal fidelit y point s of view, t r ansmission line coupling bet ween
st ages is best , and is descr ibed in some det ail in t he next sect ion. However , complet e
t r ansmission line syst em design may not always be possible or pr act ical. In addit ion,
var ious ot her par asit ic issues need car eful consider at ion in high per for mance
designs. One such pr oblem par asit ic is amplifier load capacit ance, which pot ent ially
comes int o play for all wide bandwidt h sit uat ions which do not use t r ansmission line
signal coupling.
A gener al design r ule for wideband linear dr iver s is t hat capacit ive loading (cap
loading) effect s should always be consider ed. This is because PC boar d capacit ance
can build up quickly, especially for wide and long signal r uns over gr ound planes
insulat ed by t hin, higher K dielect r ic. For example, a 0.025” PC t r ace using a G-10
dielect r ic of 0.03” over a gr ound plane will r un about 22pF/foot (Refer ence 1). Even
r elat ively small load capacit ance (i.e., <100 pF) can be t r oublesome, since while not
causing out r ight oscillat ion, it can st ill st r et ch amplifier set t ling t ime t o gr eat er
t han desir able levels for a given accur acy.
The effect s of cap loading on high speed amplifier out put s ar e not simply
det r iment al, t hey ar e act ually an anat hema t o high qualit y signals. However , befor e-
t he-fact designer knowledge st ill allows high cir cuit per for mance, by employing
var ious t r icks of t he t r ade t o combat t he capacit ive loading. If it is not dr iven via a
t r ansmission line, r emot e signal cir cuit r y should be checked for capacit ive loading
ver y car efully, and char act er ized as best possible. Dr iver s which face poor ly defined
load capacit ance should be bullet -pr oofed accor dingly wit h an appr opr iat e design
t echnique fr om t he opt ions list below.
Shor t of a t r ue mat ched t r ansmission line syst em, a number of ways exist t o dr ive a
load which is capacit ive in nat ur e while maint aining amplifier st abilit y.
Custom capacitive load (cap load) compensation, includes two possible options,
namely a); overcompensation, and b); an intentionally forced-high loop noise gain
allowing crossover in a stable region. Both of these steps can be effective in special
situations, as they reduce the amplifier’s effective closed loop bandwidth, so as to
restore stability in the presence of cap loading.
Overcompensation of t he amplifier , when possible, r educes amplifier bandwidt h so
t hat t he addit ional load capacit ance no longer r epr esent s a danger t o phase mar gin.
As a pr act ical mat t er however , amplifier compensat ion nodes t o allow t his ar e
available on few high speed amplifier s. One such useful example is t he AD829,
compensat ed by a single capacit or at pin 5. In gener al, almost any amplifier using
ext er nal compensat ion can always be over compensat ed t o r educe bandwidt h. This
will r est or e st abilit y against cap loads, by lower ing t he amplifier ’s unit y gain
fr equency.
4
CAPACITIVE LOADING ON OP AMP GENERALLY REDUCES
PHASE MARGIN AND MAY CAUSE INSTABILITY,
BUT INCREASING THE NOISE GAIN OF THE CIRCUIT
IMPROVES STABILITY
Figure 2.1
Forcing a high noise gain, is shown in Figur e 2.1, wher e t he capacit ively loaded
amplifier wit h a noise gain of unit y at t he left is seen t o be unst able, due t o a 1/ß -
open loop r olloff int er sect ion on t he Bode diagr am in an unst able –12dB/oct ave
r egion. For such a case, quit e oft en st abilit y can be r est or ed by int r oducing a higher
noise gain t o t he st age, so t hat t he int er sect ion t hen occur s in a st able –6dB/oct ave
r egion, as depict ed at t he diagr am r ight Bode plot .
RAISING NOISE GAIN (DC OR AC) FOR
FOLLOWER OR INVERTER STABILITY
Figure 2.2
To enable a higher noise gain (which does not necessar ily need t o be t he same as t he
st age’s signal gain), use is made of r esist ive or RC pads at t he amplifier input , as in
Figur e 2.2. This t r ick is mor e br oad in scope t han over compensat ion, and has t he
advant age of not r equir ing access t o any int er nal amplifier nodes. This gener ally
allows use wit h any amplifier set up, even volt age follower s. The t echnique adds an
ext r a r esist or R
D
, which wor ks against R
F
t o for ce t he noise gain of t he st age t o a
level appr eciably higher t han t he signal gain (which is unit y in bot h cases her e).
Assuming t hat C
L
is a value which pr oduces a par asit ic pole near t he amplifier ’s
nat ur al cr ossover , t his loading combinat ion would likely lead t o oscillat ion due t o t he
5
excessive phase lag. However wit h R
D
connect ed, t he higher amplifier noise gain
pr oduces a new 1/ß - open loop r olloff int er sect ion, about a decade lower in
fr equency. This is set low enough t hat t he ext r a phase lag fr om C
L
is no longer a
pr oblem, and amplifier st abilit y is r est or ed.
A dr awback t o t his t r ick is t hat t he DC offset and input noise of t he amplifier ar e
r aised by t he value of t he noise gain, when t he opt ional C
D
is not pr esent . But , when
C
D
is used in ser ies wit h R
D
, t he offset volt age of t he amplifier is not r aised, and t he
gained-up AC noise component s ar e confined t o a fr equency r egion above
1/(2pi• R
D
• C
D
). A fur t her caut ion is t hat t he t echnique can be somewhat t r icky
when separ at ing t hese oper at ing DC and AC r egions, and should be applied
car efully wit h r egar d t o set t ling t ime (Refer ence 2). Not e t hat t hese simplified
examples ar e gener ic, and in pr act ice t he absolut e component values should be
mat ched t o a specific amplifier .
“Passive”cap load compensation, shown in Figure 2.3, is the most simple (and most
popular) isolation technique available. It uses a simple “out-of-the-loop”series resistor
R
X
to isolate the cap load, and can be used with any amplifier, current or voltage
feedback, FET or bipolar input.
OPEN-LOOP SERIES RESISTANCE ISOLATES CAPACITIVE
LOAD FOR AD811 CURRENT FEEDBACK OP AMP
(CIRCUIT BANDWIDTH = 13.5 MHz)
Figure 2.3
As not ed, t his t echnique can be applied t o vir t ually any amplifier , which is a major
r eason why it is so useful. It is shown her e wit h a cur r ent feedback amplifier
suit able for high cur r ent line dr iving, t he AD811, and it consist s of just t he simple
(passive) ser ies isolat ion r esist or , R
X
. This r esist or ’s minimum value for st abilit y
will var y fr om device t o device, so t he amplifier dat a sheet should be consult ed for
ot her ICs. Gener ally, infor mat ion will be pr ovided as t o t he amount of load
capacit ance t oler at ed, and a suggest ed minimum r esist or value for st abilit y
pur poses.
6
Dr awbacks of t his appr oach ar e t he loss of bandwidt h as R
X
wor ks against C
L
, t he
loss of volt age swing, a possible lower slew r at e limit due t o I
MAX
and C
L
, and a
gain er r or due t o t he R
X
-R
L
division. The gain er r or can be opt ionally compensat ed
wit h R
IN
, which is r at ioed t o R
F
as R
L
is t o R
X
. In t his example, a ±100mA out put
fr om t he op amp int o C
L
can slew V
OUT
at a r at e of 100V/µs, far below t he int r insic
AD811 slew r at e of 2500V/µs. Alt hough t he dr awbacks ar e ser ious, t his for m of cap
load compensat ion is never t heless useful because of it s simplicit y. If t he amplifier is
not ot her wise pr ot ect ed, t hen an R
X
r esist or of 50-100ohms should be used wit h
vir t ually any amplifier facing capacit ive loading. Alt hough a non-inver t ing amplifier
is shown, t he t echnique is equally applicable t o inver t er st ages.
Wit h ver y speed high amplifier s, or in applicat ions wher e lowest set t ling t ime is
cr it ical, even small values of load capacit ance can be disr upt ive t o fr equency
r esponse, but ar e never t heless somet imes inescapable. One case in point is an
amplifier used for dr iving ADC input s. Since high speed ADC input s quit e oft en look
capacit ive in nat ur e, t his pr esent s an oil/wat er t ype pr oblem. In such cases t he
amplifier must be st able dr iving t he capacit ance, but it must also pr eser ve it s best
bandwidt h and set t ling t ime char act er ist ics. To addr ess t his t ype of cap load case
per for mance, R
s
and C
L
dat a for a specified set t ling t ime is most appr opr iat e.
Some applicat ions, in par t icular t hose t hat r equir e dr iving t he r elat ively high
impedance of an ADC, do not have a convenient back t er minat ion r esist or t o dampen
t he effect s of capacit ive loading. At high fr equencies, an amplifier ’s out put
impedance is r ising wit h fr equency and act s like an induct ance, which in
combinat ion wit h C
L
causes peaking or even wor se, oscillat ion. When t he bandwidt h
of an amplifier is an appr eciable per cent age of device f
t
,t he sit uat ion is complicat ed
by t he fact t hat t he loading effect s ar e r eflect ed back int o it s int er nal st ages. In spit e
of t his, t he basic behavior of most ver y wide bandwidt h amplifier s such as t he
AD8001 is ver y similar .
In gener al, a small damping r esist or (R
s
) placed in ser ies wit h C
L
will help r est or e
t he desir ed r esponse (see Figur e 2.4). The best choice for t his r esist or ’s value will
depend upon t he cr it er ion used in det er mining t he desir ed r esponse. Tr adit ionally,
simply st abilit y or an accept able amount of peaking has been used, but a mor e st r ict
measur e such as 0.1% (or even 0.01%) set t ling will yield differ ent values. For a given
amplifier , a family of R
s
- C
L
cur ves exist s, such as t hose of Figur e 2.4. These dat a
will aid in select ing R
s
for a given applicat ion.
7
AD8001 R
S
REQIRED FOR VARIOUS CL VALUES
Figure 2.4
The basic shape of t his cur ve can be easily explained. When C
L
is ver y small, no
r esist or is necessar y. When C
L
incr eases t o some t hr eshold value an R
s
becomes
necessar y. Since t he fr equency at which t he damping is r equir ed is r elat ed t o t he
R
s
• C
L
t ime const ant , t he R
s
needed will init ially incr ease r apidly fr om zer o, and
t hen will decr ease as C
L
is incr eased fur t her . A r elat ively st r ict r equir ement , such
as for 0.1%, set t ling will gener ally r equir e a lar ger R
s
for a given C
L
, giving a cur ve
falling higher (in t er ms of R
s
) t han t hat for a less st r ingent r equir ement , such as
20% over shoot . For t he common gain condit ion of +2, t hese t wo cur ves ar e plot t ed in
t he figur e for 0.1% set t ling (upper -most cur ve) and 20% over shoot (middle cur ve). It
is also wor t h ment ioning t hat higher closed loop gains lessen t he pr oblem
dr amat ically, and will r equir e less R
s
for t he same per for mance. The t hir d (lower -
most ) cur ve illust r at es t his, demonst r at ing a closed loop gain of 10 R
s
r equir ement
for 20% over shoot for t he AD8001 amplifier . This can be r elat ed t o t he ear lier
discussion associat ed wit h Figur e 2.2.
The r ecommended values for R
s
will opt imize r esponse, but it is impor t ant t o not e
t hat gener ally C
L
will degr ade t he maximum bandwidt h and set t ling t ime
per for mance which is achievable. In t he limit , a lar ge R
s
• C
L
t ime const ant will
dominat e t he r esponse. In any given applicat ion, t he value for R
s
should be t aken as
a st ar t ing point in an opt imizat ion pr ocess which account s for boar d par asit ics and
ot her secondar y effect s.
Active or “in-the-loop”cap load compensation can also be used as shown in Figure
2.5, and this scheme modifies the passive configuration to provide feedback correction
for the DC & low frequency gain error associated with R
X
. In contrast to the passive
form, active compensation can only be used with voltage feedback amplifiers, because
current feedback amplifiers don’t allow the integrating connection of C
F.
8
ACTIVE “IN-LOOP” CAPACITIVE LOAD COMPENSATION
CORRECTS FOR DC AND LF GAIN ERRORS
Figure 2.5
This cir cuit r et ur ns t he DC feedback fr om t he out put side of isolat ion r esist or R
X
,
t hus cor r ect ing for er r or s. AC feedback is r et ur ned via C
F
, which bypasses R
X
/R
F
at
high fr equencies. Wit h an appr opr iat e value of C
F
(which var ies wit h C
L
, for fixed
r esist ances) t his st age can be adjust ed for a well damped t r ansient r esponse
(Refer ence 2,3). Ther e is st ill a bandwidt h r educt ion, a headr oom loss, and also
(usually) a slew r at e r educt ion, but t he DC er r or s can be ver y low. A dr awback is t he
need t o t une C
F
t o C
L
, as even if t his is done well init ially, any change t o C
L
will
alt er t he r esponse away fr om flat . The cir cuit as shown is useful for volt age feedback
amplifier s only, because capacit or C
F
pr ovides int egr at ion ar ound U1. It also can be
implement ed in inver t ing fashion, by dr iving t he bot t om end of R
IN
.
Internal cap load compensation involves the use of an amplifier which internally has
topological provisions for the effects of external cap loading. To the user, this is the
most transparent of the various techniques, as it works for any feedback situation, for
any value of load capacitance. Drawbacks are that it produces higher distortion than
does an otherwise similar amplifier without the network, and the compensation
against cap loading is somewhat signal level dependent.
9
AD817 SIMPLIFIED SCHEMATIC ILLUSTRATES INTERNAL
COMPENSATION FOR DRIVING CAPACITIVE LOADS
Figure 2.6
The int er nal cap load compensat ed amplifier sounds at fir st like t he best of all
possible wor lds, since t he user need do not hing at all t o set it up. Figur e 2.6, a
simplified diagr am of an amplifier wit h int er nal cap load compensat ion, shows how
it wor ks. The cap load compensat ion is t he C
F
-r esist or net wor k shown ar ound t he
unit y gain out put st age of t he amplifier - not e t hat t he dot t ed connect ion of t his
net wor k under scor es t he fact t hat it only makes it s pr esence felt for cer t ain load
condit ions.
Under nor mal (non-capacit ive or light r esist ive) loading, t her e is limit ed
input /out put volt age er r or acr oss t he out put st age, so t he C
F
net wor k t hen sees a
r elat ively small volt age dr op, and has lit t le or no effect on t he amplifier ’s high
impedance compensat ion node. However when a capacit or (or ot her heavy) load is
pr esent , t he high cur r ent s in t he out put st age pr oduce a volt age differ ence acr oss t he
C
F
net wor k, which effect ively adds capacit ance t o t he compensat ion node. Wit h t his
r elat ively heavy loading, a net lar ger compensat ion capacit ance r esult s, and r educes
t he amplifier speed in a manner which is adapt ive t o t he ext er nal capacit ance, C
L
.
As a point of reference, note that it requires 6.3mA peak to support a 2Vp-p swing
across a 100pF load at 10MHz.
Since t his mechanism is r esident in t he amplifier out put st age and it affect s t he
over all compensat ion char act er ist ics dynamically, it act s independent of t he specific
1
0
feedback hookup, as well as size of t he ext er nal cap loading. In ot her wor ds, it can be
t r anspar ent t o t he user in t he sense t hat no specific design condit ions need be set t o
make it wor k (ot her t han select ing an IC which employs it ). Some amplifier s using
int er nal cap load compensat ion ar e t he AD847 and t he AD817, and t heir dual
equivalent s, AD827 and AD826.
Ther e ar e, however , some caveat s also associat ed wit h t his int er nal compensat ion
scheme. As wit h t he passive compensat ion t echniques, bandwidt h decr eases as t he
device slows down t o pr event oscillat ion wit h higher load cur r ent s. Also, t his
adapt ive compensat ion net wor k has it s gr eat est effect when enough out put cur r ent
flows t o pr oduce significant volt age dr op acr oss t he C
F
net wor k. Conver sely, at
small signal levels, t he effect of t he net wor k on speed is less, so gr eat er r inging may
act ually be possible for some cir cuit s for lower -level out put s.
RESPONSE OF INTERNAL CAP LOAD
COMPENSATED AMPLIFIER VARIES WITH SIGNAL LEVEL
Figure 2.7
The dynamic nat ur e of t his int er nal cap load compensat ion is illust r at ed in Figur e
2.7, which shows an AD817 unit y gain inver t er being exer cised at bot h high and low
out put levels, wit h common condit ions of V
s
= ±15V, R
L
= 1kohm, C
L
= 1nF, and
using 1kohm input /feedback r esist or s. In bot h phot os t he input signal is on t he t op
t r ace and t he out put signal is on t he bot t om t r ace, and t he t ime scale is fixed. In t he
10Vp-p out put (A) phot o at t he left , t he out put has slowed down appr eciably t o
accommodat e t he capacit ive load, but set t ling is st ill r elat ively clean, wit h a small
per cent age of over shoot . This indicat es t hat for t his high level case, t he bandwidt h
r educt ion due t o C
L
is most effect ive. However , in t he (B) phot o at t he r ight , t he
200mVp-p out put shows gr eat er over shoot and r inging, for t he lower level signal.
The point is made t hat , t o some degr ee at least , t he r elat ive cap load immunit y of
t his t ype of int er nally cap load compensat ed amplifier is signal dependent .
1
1
Finally, because t he cir cuit is based on a nonlinear pr inciple, t he int er nal net wor k
affect s dist or t ion and load dr ive abilit y, and t hese fact or s influence amplifier
per for mance in video applicat ions. Though t he net wor k’s pr esence does not by any
means make devices like t he AD847 or AD817 unusable for video, it does not per mit
t he ver y lowest levels of dist or t ion and differ ent ial gain and phase which ar e
achievable wit h ot her wise compar able amplifier s (for example, t he AD818).
While t he individual t echniques for count er ing cap loading out lined above have
var ious specific t r adeoffs as not ed, all of t he t echniques have a ser ious common
dr awback of r educing speed (bot h bandwidt h and slew r at e). If t hese par amet er s
cannot be sacr ificed, t hen a mat ched t r ansmission line syst em is t he solut ion, and is
discussed in mor e det ail lat er in t he chapt er . As for choosing among t he cap load
compensat ion schemes, it would seem on t he sur face t hat amplifier s using t he
int er nal for m offer t he best possible solut ion t o t he pr oblem- just pick t he r ight
amplifier and for get about it . And indeed, t hat would seem t he “panacea” solut ion
for all cap load sit uat ions - if you use t he “r ight ” amplifier you never need t o t hink
about cap loading again. Could t her e be mor e t o it ?
Yes! The “got cha” of int er nal cap load compensat ion is subt le, and lies in t he fact
t hat t he dynamic adapt ive nat ur e of t he compensat ion mechanism act ually can
pr oduce higher levels of dist or t ion, vis-à-vis an ot her wise similar amplifier , without
t he C
F
-r esist or net wor k. Like t he old saying about no fr ee lunches, if you car e about
at t aining t op-not ch levels of high fr equency AC per for mance, you should give t he
issue of whet her t o use an int er nally compensat ed cap load amplifier mor e ser ious
t hought t han simply picking a t r endy device.
On t he ot her hand, if you have no r equir ement s for t he lowest levels of dist or t ion,
t hen such an amplifier could be a good choice. Such amplifier s ar e cer t ainly easier t o
use, and r elat ively for giving about loading issues. Some applicat ions of t his chapt er
illust r at e t he dist or t ion point specifically, quot ing per for mance in a dr iver cir cuit
wit h/wit hout t he use of an int er nal cap load compensat ed amplifier s.
Wit h incr eased gain bandwidt hs of gr eat er t han or equal t o 100MHz available in
t oday’s ICs, layout , gr ounding and t he cont r ol of par asit ics become much, much mor e
impor t ant . In fact , wit h t he fast est available ICs such as t he XFCB t ypes, t hese
issues simply cannot be ignor ed, t hey ar e cr it ical and must be addr essed for st able
per for mance. All high fr equency designs can pr ofit fr om t he use of low par asit ic
const r uct ion t echniques, such as descr ibed in Chapt er 9. In t he cir cuit discussions
which follow, similar met hods should be used for best r esult s, and in t he ver y high
fr equency cir cuit s (gr eat er t han 100MHz) it is mandat or y. Some common pit falls ar e
cover ed befor e get t ing int o specific cir cuit examples.
As wit h all wide bandwidt h component s, good PC boar d layout is cr it ical t o obt ain
t he best dynamic per for mance wit h t hese high speed amplifier s. The gr ound plane in
t he ar ea of t he op amp and it s associat ed component s should cover as much of t he
component side of t he boar d as possible (or fir st int er ior gr ound layer of a mult ilayer
boar d).
1
2
The gr ound plane should be r emoved in t he ar ea of t he amplifier input s and t he
feedback and gain set r esist or s t o minimize st r ay capacit ance at t he input . Each
power supply t r ace should be decoupled close t o t he package wit h a minimum of
0.1µF cer amic (pr efer ably sur face mount ), plus a 6.8µF or lar ger t ant alum capacit or
wit hin 0.5", as a char ge st or age r eser voir when deliver ing high peak cur r ent s (line
dr iver s, for example). Opt ionally, lar ger value convent ional elect r olyt ic can be used
in place of t he t ant alum t ypes, if t hey have a low ESR.
All lead lengt hs for input , out put , and feedback r esist or should be kept as shor t as
possible. All gain set t ing r esist or s should be chosen for low values of par asit ic
capacit ance and induct ance, i.e., micr owave r esist or s (buffed met al film r at her t han
laser -t r immed spir al-wound) and/or car bon r esist or s.
Micr ost r ip t echniques should be used for all input and out put lead lengt hs in excess
of one inch (Refer ence 1). Socket s should be avoided if at all possible because of t heir
par asit ic capacit ance and induct ance. If socket s ar e necessar y, individual pin sockets
such as AMP p/n 6-330808-3 should be used. These cont r ibut e far less st r ay
capacit ance and induct ance t han molded socket assemblies.
The effect s of inadequat e decoupling on har monic dist or t ion per for mance ar e
dr amat ically illust r at ed in Figur e 2.8. The left phot o shows t he spect r al out put of
t he AD9631 op amp dr iving a 100ohm load wit h pr oper decoupling (out put signal is
20MHz, 2V p-p). Not ice t hat t he second har monic dist or t ion at 40MHz is
appr oximat ely –70dBc. If t he decoupling is r emoved, t he dist or t ion is incr eased, as
shown in t he r ight phot o of t he same figur e. Figur e 2.8 (r ight -hand phot o) also shows
st r ay RF pickup in t he wir ing connect ing t he power supply t o t he op amp t est
fixt ur e. Unlike lower fr equency amplifier s, t he power supply r eject ion r at io of many
high fr equency amplifier s is gener ally fair ly poor at high fr equencies. For example,
at 20MHz, t he power supply r eject ion r at io of t he AD9631 is less t han 25dB. This is
t he pr imar y r eason for t he degr adat ion in per for mance wit h inadequat e decoupling.
The change in out put signal pr oduces a cor r esponding signal-dependent load cur r ent
change. The cor r esponding change in power supply volt age due t o inadequat e
decoupling pr oduces a signal-dependent er r or in t he out put which manifest s it self as
an incr ease in dist or t ion.
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3
EFFECTS OF INADEQUATE DECOUPLING ON
HARMONIC DISTORTION PERFORMANCE OF AD9631 OP AMP
Figure 2.8
Inadequat e decoupling can also sever ely affect t he pulse r esponse of high speed
amplifier s such as t he AD9631. Figur e 2.9 shows nor mal oper at ion and t he effect s of
r emoving all decoupling capacit or s on t he AD9631 in it s evaluat ion boar d. Not ice t he
sever e r inging on t he pulse r esponse for t he poor ly decoupled condit ion, in t he r ight
phot o. A Tekt r onix 644A, 500MHz digit izing oscilloscope was used t o make t he
measur ement (as well as t he pulse r esponses in Figur e 2.10, 2.14, 2.15, 2.16, and
2.17).
EFFECT OF INADEQUATE DECOUPLING
ON PULSE RESPONSE OF AD9631 OP AMP
Figure 2.9
The effect s of st r ay par asit ic capacit ance on t he inver t ing input of such high speed
op amps as t he AD8001 is shown in Figur e 2.10. In t his example, 10pF was
connect ed t o t he inver t ing input , and t he over shoot and r inging incr eased
significant ly. (The AD8001 was configur ed in t he inver t ing mode wit h a gain of –1,
and t he feedback and feedfor war d r esist or s wer e equal t o 649ohms). In some cases,
1
4
low-amplit ude oscillat ion may occur at fr equencies of sever al hundr ed megaher t z
when t her e is significant st r ay capacit ance on t he inver t ing input . Unfor t unat ely,
you may never act ually obser ve it unless you have a scope or spect r um analyzer
which has sufficient bandwidt h. Unwant ed oscillat ions at RF fr equencies will
pr obably be r ect ified and aver aged by devices t o which t he oscillat ing signal is
applied. This is r efer r ed t o as RF rectification and will cr eat e small unexplained dc
offset s which may even be a funct ion of moving your hand over t he PC boar d. It is
absolut ely essent ial when building cir cuit s using high fr equency component s t o have
high bandwidt h t est equipment and use it t o check for oscillat ion at fr equencies well
beyond t he signals of int er est .
EFFECT OF 10pF STRAY INVERTING INPUT CAPACITANCE
ON PULSE RESPONSE OF AD8001 OP AMP
Figure 2.10
Many of t hese pr oblems occur in t he pr ot ot ype phase due t o a disr egar d for high
fr equency layout and decoupling t echniques. The solut ions t o t hem lie in r igor ous
at t ent ion t o such det ails as above, and t hose descr ibed in Chapt er 9.
CABLE DRI VI NG
For a number of good r easons, wide bandwidt h amplifier syst ems t r adit ionally use
t r ansmission line int er connect ions, such as t hat shown in t he basic diagr am of
Figur e 2.11. This syst em uses a dr ive amplifier A, mat ched in t er ms of out put
impedance by t he 75ohm sour ce t er minat ion R
T
t o t he t r ansmission line connect ing
st ages A and B. In t his par t icular case t he line is a 75ohm coax, but in gener al it is a
wideband line mat ched at bot h ends, and can alt er nat ely be of t wist ed pair or
st r ipline const r uct ion. It is followed immediat ely by t he differ ent ial r eceiver cir cuit ,
B, which t er minat es t he line wit h a load R
TERM
, equal t o it s 75ohm impedance.
The r eceiver st age r ecover s a noise-fr ee 1V signal which is r efer enced t o syst em
gr ound B.
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5
SINGLE-ENDED DRIVER AND DIFFERENTIAL RECEIVER
Figure 2.11
When pr oper ly implement ed (i.e., t he line is sour ce and load t er minat ed in it s
char act er ist ic impedance), t his syst em pr esent s r esist ive-only loading t o dr ive
amplifier A. This fact or makes it near ideal fr om t he mut ual viewpoint s of amplifier
st abilit y, dist or t ion and fr equency r esponse, as well as minimizing line r eflect ions
and associat ed t ime domain aber r at ions. Ther e is an int r insic 2/1 (6dB) signal loss
associat ed wit h t he line’s sour ce and load t er minat ions, but t his is easily made up
by a 2x dr iver st age gain.
It is ver y impor t ant t o under st and t hat t he capacit ive-load compensat ion t echniques
descr ibed above ar e har dly t he per fect solut ion t o t he line-dr iving pr oblem. The most
foolpr oof way t o dr ive a long line (which could ot her wise pr esent a subst ant ial
capacit ive load) is t o use a t r ansmission line, a st andar d for signal dist r ibut ion in
video and RF syst ems for year s. Figur e 2.12 summar izes sever al impor t ant cable
char act er ist ics.
CABLE CAPACITANCE
All Interconnections are Really Transmission Lines Which Have a
Characteristic Impedance (Even if Not controlled)
The Characteristic Impedance is Equal to (L/C), where L and C are
the Distributed Inductance and Capacitance
Correctly Terminated Transmission Lines Have Impedances Equal to
Their Characteristic Impedance
Unterminated Transmission Lines Behave Approximately as
Lumped Capacitance at Frequencies << 1/t
p
, where t
p
= Propagation
Delay of Cable
Figure 2.12
A t r ansmission line cor r ect ly t er minat ed wit h pur e r esist ance (no r eact ive
component ) does not look capacit ive. It has a cont r olled dist r ibut ed capacit ance per
foot (C) and a cont r olled dist r ibut ed induct ance per foot (L). The char act er ist ic
impedance of t he line is given by t he equat ion Z
o
= sqr t (L/C). Coaxial cable is t he
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6
most popular for m of single-ended t r ansmission line and comes in char act er ist ic
impedances of 50ohms, 75ohms, and 93ohms.
Because of skin effect , it exhibit s a loss which is a funct ion of fr equency as shown in
Figur e 2.13 for sever al popular coaxial cables (Refer ence 5). Skin effect also affect s
t he pulse r esponse of long coaxial cables. The r esponse t o a fast pulse will r ise
shar ply for t he fir st 50% of t he out put swing, t hen t aper off dur ing t he r emaining
por t ion of t he edge. Calculat ions show t hat t he 10 t o 90% wavefor m r iset ime is 30
t imes gr eat er t han t he 0 t o 50% r iset ime when t he cable is skin effect limit ed
(Refer ence 5).
COAXIAL CABLE ATTENUATION VERSUS FREQUENCY
Figure 2.13
It is useful t o examine what happens for condit ions of pr oper and impr oper cable
sour ce/load t er minat ions. To illust r at e t he behavior of a high speed op amp dr iving a
coaxial cable, consider t he cir cuit of Figur e 2.14. The AD8001 dr ives 5 feet of 50ohm
coaxial cable which is load-end t er minat ed in t he char act er ist ic impedance of
50ohms. No t er minat ion is used at t he amplifier (dr iving) end. The pulse r esponse is
also shown in t he figur e.
The out put of t he cable was measur ed by connect ing it dir ect ly t o t he 50ohm input of
a 500MHz Tekt r onix 644A digit izing oscilloscope. The 50ohm r esist or t er minat ion is
act ually t he input of t he scope. The 50ohm load is not a per fect t er minat ion (t he
scope input capacit ance is about 10pF), so some of t he pulse is r eflect ed out of phase
back t o t he sour ce. When t he r eflect ion r eaches t he op amp out put , it sees t he closed-
loop out put impedance of t he op amp which, at 100MHz, is appr oximat ely 100ohms.
Thus, it is r eflect ed back t o t he load wit h no phase r ever sal, account ing for t he
negat ive-going "blip" which occur s appr oximat ely 16ns aft er t he leading edge. This is
equal t o t he r ound-t r ip delay of t he cable (2• 5ft • 1.6 ns/ft =16ns). In t he fr equency
domain (not shown), t he cable mismat ch will cause a loss of bandwidt h flat ness at
t he load.
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PULSE RESPONSE OF AD8001 DRIVING
5 FEET OF LOAD-TERMINATED 50 COAXIAL CABLE
Figure 2.14
Figur e 2.15 shows a second case, t he r esult s of dr iving t he same coaxial cable, but
now used wit h bot h a 50ohm sour ce-end as well as a 50ohm load-end t er minat ion.
This case is t he pr efer r ed way t o dr ive a t r ansmission line, because a por t ion of t he
r eflect ion fr om t he load impedance mismat ch is absor bed by t he amplifier ’s sour ce
t er minat ion r esist or . The disadvant age is t hat t her e is a 2x gain r educt ion, because
of t he volt age division bet ween t he equal value sour ce/load t er minat ions. However , a
major posit ive at t r ibut e of t his configur at ion, wit h mat ched sour ce and load
t er minat ions in conjunct ion wit h a low-loss cable, is t hat t he best bandwidt h flat ness
is ensur ed, especially at lower oper at ing fr equencies. In addit ion, t he amplifier is
oper at ed under near opt imum loading condit ions, i.e., a r esist ive load.
PULSE RESPONSE OF AD8001 DRIVING 5 FEET
OF SOURCE AND LOAD-TERMINATED 50 COAXIAL CABLE
Figure 2.15
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8
Sour ce-end (only) t er minat ions can also be used as shown in Figur e 2.16, wher e t he
op amp is sour ce t er minat ed by t he 50ohm r esist or which dr ives t he cable. The scope
is set for 1Mohm input impedance, r epr esent ing an appr oximat e open cir cuit . The
init ial leading edge of t he pulse at t he op amp out put sees a 100ohm load (t he 50ohm
sour ce r esist or in ser ies wit h t he 50ohm coax impedance. When t he pulse r eaches
t he load, a lar ge por t ion is r eflect ed in phase because of t he high load impedance,
r esult ing in a full-amplit ude pulse at t he load. When t he r eflect ion r eaches t he
sour ce-end of t he cable, it sees t he 50ohm sour ce r esist ance in ser ies wit h t he op
amp closed loop out put impedance (appr oximat ely 100ohms at t he fr equency
r epr esent ed by t he 2ns r iset ime pulse edge). The r eflect ed por t ion r emains in phase,
and appear s at t he scope input as t he posit ive-going "blip" appr oximat ely 16ns aft er
t he leading edge.
PULSE RESPONSE OF AD8001 DRIVING 5 FEET
OF SOURCE-TERMINATED 50 COAXIAL CABLE
Figure 2.16
Fr om t hese exper iment s, one can easily see t hat t he pr efer r ed met hod for minimum
r eflect ions (and t her efor e maximum bandwidt h flat ness) is t o use bot h sour ce and
load t er minat ions and t r y t o minimize any r eact ance associat ed wit h t he load. The
exper iment s r epr esent a wor st -case condit ion, wher e t he fr equencies cont ained in
t he fast edges ar e gr eat er t han 100MHz. (Using t he r ule-of-t humb t hat bandwidt h =
0.35/r iset ime). At video fr equencies, eit her load-only, or sour ce-only t er minat ions
may give accept able r esult s, but t he dat a sheet should always be consult ed t o
det er mine t he op amp's closed-loop out put impedance at t he maximum fr equency of
int er est . A major disadvant age of t he sour ce-only t er minat ion is t hat it r equir es a
t r uly high impedance load (high r esist ance and minimal par asit ic capacit ance) for
minimum absor pt ion of ener gy.
Now, for a t r uly wor st case, let us r eplace t he 5 feet of coaxial cable wit h an
uncont r olled-impedance cable (one t hat is lar gely capacit ive wit h lit t le induct ance).
Let us use a capacit ance of 150pF t o simulat e t he cable (cor r esponding t o t he t ot al
capacit ance of 5 feet of coaxial cable whose dist r ibut ed capacit ance is about
30pF/foot ). Figur e 2.17 shows t he out put of t he AD8001 dr iving a lumped 160pF
1
9
capacit ance (including t he scope input capacit ance of 10pF). Not ice t he over shoot
and r inging on t he pulse wavefor m due t o t he capacit ive loading. This example
illust r at es t he need t o use good qualit y cont r olled-impedance coaxial cable in t he
t r ansmission of high fr equency signals.
PULSE RESPONSE OF AD8001 DRIVING 160Pf || 50 LOAD
Figure 2.17
Li n e Dr i ver s
The single-ended line dr iver funct ion complement s t he r eceiver at t he t r ansmission
end (below). This t ype dr iver is usually non-inver t ing, and accept s a signal fr om a
high impedance boar d level sour ce, scales it , and buffer s it t o dr ive a sour ce mat ched
coaxial t r ansmission line of 50-100ohms. Typically, t he dr iver has a gain of 2 t imes,
which complement s t he 2/1 at t enuat ion of syst em sour ce/load t er minat ions. A gain-
of-t wo st age seems simple on t he sur face, but act ually many fact or s become involved
in opt imizing device and power supply select ion t o meet over all syst em per for mance
cr it er ia. Among t hese ar e bandwidt h/dist or t ion levels ver sus load impedance, supply
volt age/power consumpt ion, and device t ype.
For t unat ely, moder n ICs have become mor e complet e in t heir specificat ions, as well
as mor e flexible in t er ms of supply volt age, so t her e is much fr om which t o choose.
For high per for mance in such demanding applicat ions as wideband video, designer s
need a fully specified cir cuit envir onment , so t hat t he best choice can be easy. For
NTSC video syst ems, dist or t ion is usually r at ed in t er ms of differ ent ial gain and
differ ent ial phase, expr essed as change in per cent age for gain and change in degr ees
for phase, dr iving a r at ed load at t he 3.58MHz subcar r ier fr equency. While
t r adit ional 3dB bandwidt h is impor t ant , a mor e st r ingent specificat ion of 0.1dB
bandwidt h is also oft en used.
2
0
VIDEO LINE DRIVER USING THE AD818 VOLTAGE
FEEDBACK OP AMP HAS 50MHz BANDWIDTH (-0.1 dB)
Figure 2.18
An excellent single-ended, high per for mance line dr iver meet ing t hese guidelines is
shown in Figur e 2.18. Alt hough t his cir cuit uses inexpensive amplifier s, an AD818
(or 1/2 an AD828), it is st ill has excellent per for mance. St age gain is set at 2 t imes
by t he equal R
1
- R
2
values, which ar e also r elat ively low (500-1kohms), t o minimize
t he feedback t ime const ant . This volt age feedback op amp has maximum effect ive
bandwidt h when oper at ed at G=2, and has been opt imized for t his specific
applicat ion, t hus it is able t o achieve a 50MHz 0.1dB bandwidt h. For highest
linear it y, it does not use int er nal capacit ive load compensat ion. This fact or , plus a
high cur r ent (50mA) out put st age pr ovides t he gain linear it y r equir ed for high
per for mance video, and line dr iving applicat ions.
The NTSC video differ ent ial gain/phase per for mance of t his cir cuit is quit e good
wit h t he 150ohm loading pr esent ed by t he 75ohm sour ce t er minat ion R
T
plus t he
75ohm load, R
L
, and is t ypically on t he or der of 0.01%/0.05° for a 2Vp-p V
OUT
video
swing while oper at ing at ±15V. These figur es do degr ade for oper at ion at V
s
= ±5V,
but can be maint ained for supplies of ±10V or mor e. Thus t o minimize dist or t ion,
supplies of ±10V t o ±15V should be used. Ot her video gr ade op amps can also be used
for U1, but illust r at e t he pot ent ial for dist or t ion t r adeoffs. For example, t he AD817
(a similar op amp wit h int er nal cap load compensat ion, see above) achieves NTSC
video dist or t ion figur es of 0.04%/0.08° at V
s
=±15V for t he same 150ohm loading.
Supply bypassing for line dr iver s such as t his should include bot h local low
induct ance caps C1- C3, as well as lar ger value elect r olyt ics, for a char ge r eser voir t o
buffer heavy load cur r ent s. Tant alum t ypes can be used for C2 - C4, and t end t o
have bot h lower ESR and small physical size (bot h desir able), but t he 100µF
aluminum t ypes shown can also be used. Quiescent cur r ent of t his cir cuit is 7mA,
which equat es t o power dissipat ions of 210 and 70mW for V
s
=±15V and ±5V,
r espect ively.
2
1
VIDEO LINE DRIVER USING THE AD810 CURRENT FEEDBACK
OP AMP HAS DISABLE MODE, 65MHz BANDWIDTH (-3 dB)
AND 20MHz BANDWIDTH (-0.1 dB)
Figure 2.19
Figur e 2.19 shows anot her high-per for mance video line dr iver using t he AD810
cur r ent feedback amplifier . This cir cuit is also inexpensive and has higher slew r at e
and higher out put cur r ent . The AD810 has a 3dB bandwidt h of 65MHz, and a 0.1dB
bandwidt h of 20MHz, while t he quiescent cur r ent is only 8mA.
A unique feat ur e of t he AD810 is it s power -down mode. The DISABLE pin is act ive-
low t o shut t he device down t o a st andby cur r ent dr ain of 2mA, wit h 60dB input
isolat ion at 10MHz. This per mit s on/off cont r ol of a single amplifier , or "wir e or -ing"
t he out put s of a number of devices t o achieve a mult iplexing funct ion. Note: If the
AD810’s disabling function is not required, then the DIS ABLE pin can float, and it
operates conventionally.
Not e t hat when t he AD810 is used on differ ent power supplies, t he opt imum R
F
will
change (see t able... t his also will be t r ue for ot her cur r ent feedback amplifier s).
Ot her cur r ent feedback amplifier s suit able for t his dr iver funct ion ar e t he single
AD811, t he dual AD812, and t he t r iple AD813 (wit h t he AD813 also feat ur ing a
DISABLE funct ion).
2
2
VERY HIGH PERFORMANCE 5V VIDEO LINE DRIVER/
DISTRIBUTION AMPLIFIER HAS 440MHz BANDWIDTH (-3Db)
AND 110MHz BANDWIDTH (-0.1Db)
Figure 2.20
Figur e 2.20 illust r at es a ver y high per for mance video line dr iver , which has opt ional
dist r ibut ion amplifier feat ur es. This cir cuit uses t he AD8001 cur r ent feedback
amplifier as a gain-of-2 dual 75ohm line dr iver , gener ally similar t o t he above. Some
key per for mance differ ences which set t his cir cuit apar t lie in t he fact t hat t he op
amp employs a complement ar y UHF pr ocess. It is capable of ext r emely wideband
r esponse, due t o t he NPN/PNP f
t
s of 3-5GHz. This allows higher fr equency r esponse
at a lower power dissipat ion t han t he 500-600MHz f
t
complement ar y pr ocess par t s,
such as t he AD818 or AD810 above. The ext ended fr equency r esponse and lower
power helps achieve low dist or t ion at higher fr equencies, while oper at ing at a much
lower quiescent power on supply volt ages up t o 12V.
Because t he higher fr equency r esponse per mW of power , a higher out put dr ive is
possible. Her e, t his leads t o a per for mance differ ence in t hat t his cir cuit also doubles
as a dist r ibut ion amplifier , t hat is it can dr ive t wo 75ohm out put lines if desir ed.
Oper at ed fr om ±5V supplies as shown, t he cir cuit has 3dB bandwidt h of 440MHz.
Video dist or t ion for differ ent ial gain/phase is 0.01%/0.025° wit h one line dr iven (R
L
= 150ohms). Dr iving t wo lines (R
L
= 75ohms), t he differ ent ial gain er r or s ar e
essent ially t he same, while t he differ ent ial phase er r or s r ise t o about 0.07°. The
0.1dB bandwidt h of t his cir cuit is 110MHz, and t he quiescent power is 50mW wit h
t he ±5V supplies. Supply bypassing should follow t he same guidelines as t he
pr evious dr iver s, and t he gener al physical layout should follow t he RF const r uct ion
t echniques descr ibed above and in Chapt er 9.
SI NGLE -SUP P LY CONSI DERATI ONS
The t er m single-supply has var ious implicat ions, some of which ar e oft en fur t her
confused by mar ket ing hype, et c. As ment ioned above, t her e is a dist inct t r end
t owar d syst ems which r un on lower supply volt ages. For high speed designs wher e
2Vp-p swings ar e oft en t he nor m, ±5V power supplies have become st andar d. Ther e
2
3
ar e many obvious r easons for lower power dissipat ion, such as t he abilit y t o r un
wit hout fans, r eliabilit y issues, et c. Ther e ar e, t her efor e, many applicat ions for
single-supply ADCs ot her t han in syst ems which have only one supply volt age. In
many inst ances, t he lower power dr ain of a single-supply ADC can be t he r eason for
it s select ion, r at her t han t he fact t hat it r equir es just one supply.
Then, t her e ar e also syst ems which t r uly oper at e on a single power supply. In such
cases, it can oft en be difficult t o maint ain DC coupling fr om a sour ce all t he way t o
t he ADC. In fact , AC coupling is quit e oft en used in single-supply syst ems, wit h a
DC r est or at ion cir cuit pr eceding t he ADC. This is necessar y t o pr event t he loss of
dynamic r ange which could ot her wise occur , because of a need t o pr ovide maximum
headr oom t o an AC coupled signal of ar bit r ar y dut y cycle. In t he AC-coupled
por t ions of such syst ems, a “false gr ound” is oft en cr eat ed, usually cent er ed bet ween
t he r ails.
This int r oduces t he quest ion of an opt imum input volt age r ange for a single-supply
ADC. At fir st it would seem t hat a zer o-volt r efer enced input might be desir able. But
in fact , t his places sever e const r aint s on t he ADC dr iving amplifier in DC coupled
syst ems, as it must maint ain full linear it y at or near 0V out . In act ualit y, t her e is no
such t hing as a t r ue r ail-r ail out put amplifier , since all out put st age t ypes will have
finit e sat ur at ion volt age(s) t o t he +V
s
r ail or gr ound. Bipolar st ages come t he closest ,
and can go as low as an NPN V
CESAT
of gr ound (or , a complement ar y PNP can go
wit hin a V
CESAT
of t he + r ail). The exact sat ur at ion volt age is cur r ent dependent ,
and while it may be only a few mV at light cur r ent s, it can be sever al hundr ed mV
for higher load cur r ent s. The t r adit ional CMOS r ail-r ail out put st age looks like a
r esist or t o gr ound for zer o-volt out put s (or t o t he + r ail, for + out put s), so subst ant ial
load cur r ent s cr eat e pr opor t ionally higher volt age dr ops acr oss t hese r esist or s,
t her eby limit ing t he out put swing.
A mor e opt imum ADC input r ange is t hus one which includes neit her gr ound nor t he
posit ive supply, and a r ange cent er ed ar ound V
s
/2 is usually opt imum. For example,
an input r ange of 2Vp-p ar ound +2.5V is bounded by +1.5V and +3.5V. A
complement ar y common-emit t er t ype single-supply out put st age is quit e capable of
handling t his r ange.
For design and pr ocess r easons however , t he ADC input common-mode r ange may
be offset fr om t he ideal V
s
/2 volt age midpoint . Single-supply op amps dynamic
specificat ions such as dist or t ion, set t ling t ime, slew r at e, bandwidt h, et c. ar e
t ypically st at ed for a V
s
/2 out put bias condit ion. Dist or t ion and ot her dynamics can
degr ade if t he signal is offset subst ant ially in eit her dir ect ion fr om t his nominal
r ange.
The out put volt age r ange of an op amp is most oft en given for DC or low fr equency
out put signals. Dist or t ion may incr ease as t he signal appr oaches eit her high or low
sat ur at ion volt age limit s. For inst ance, a +5V op amp can have a dist or t ion
specificat ion of –60dBc for a 3Vp-p out put signal. If not st at ed ot her wise, t he
implicat ion is t hat t he signal is cent er ed ar ound +2.5V (or V
s
/2), i.e., t he sinewave is
bounded by +1V and +4V. If t he signal is offset fr om +2.5, dist or t ion may ver y well
incr ease.
2
4
Low dist or t ion op amp designs t ypically use a complement ar y emit t er follower
out put st age. This limit s t heir out put swing t o slight ly gr eat er t han 1 diode dr op of
t he r ails, in gener al mor e like 1V of t he r ails. In or der t o maint ain low dist or t ion at
high fr equencies, even mor e headr oom may be r equir ed, r educing t he available
peak-t o-peak swing.
The complement ar y common-emit t er out put st age allows t he out put t o appr oach
wit hin V
CESAT
of t he r ails. However , it does have a higher open-loop out put
impedance t han t hat of t he follower t ype of st age, and is mor e likely t o dist or t when
dr iving such non-linear loads as flash conver t er s. When dr iving const ant impedance
loads, dist or t ion per for mance can be equal t o or bet t er t hat t he follower t ype of
st age, but such a gener alizat ion obviously has it s limit at ions.
The input volt age r ange of a single-supply op amp may also be r est r ict ed. The abilit y
t o handle zer o-volt input signals can be r ealized by eit her a PNP bipolar t r ansist or
or N-channel J FET differ ent ial input st age. Including bot h supply r ails is r ar ely
r equir ed for high fr equency signal pr ocessing. Of cour se, t he posit ive r ail can be
included, if t he op amp design uses NPN bipolar s, or P-channel J FETs. For t r ue r ail-
r ail input capabilit y, t wo amplifier input st ages must oper at e in par allel, and t he
necessar y bias cr ossover point bet ween t hese st ages can r esult in dist or t ion and
r educed CMRR. This t ype of input st age ser ves DC and lower fr equency amplifier s
best .
In many cases, an amplifier may be AC-specified for low volt age single-supply
oper at ion, but neit her it s input nor it s out put can act ually swing ver y close t o t he
r ails. Such devices must use applicat ions designed so t hat bot h t he input and out put
common-mode r est r ict ions ar e not violat ed. This gener ally involves offset t ing t he
input s using some sor t of a false gr ound r efer ence scheme.
To summar ize, t her e ar e many t r adeoffs involved in single-supply high speed
designs. In many cases using devices specified for oper at ion on +5V, but wit hout
t r ue r ail inclusive input /out put oper at ion, can give best available per for mance. As
mor e high speed devices which ar e t r uly single-supply become available, t hey can be
added t o t he designer ’s bag of t r icks.
Di r ect Cou p li n g Requ i r es Ca r efu l Desi gn a n d Con t r olled
Levels
A design which oper at es on a single +5V supply wit h DC coupling is illust r at ed in
Figur e 2.21. This t ype of cir cuit is useful when t he input signal maximum amplit ude
is known, and a specified out put bias level is r equir ed t o int er face t o t he next st age
(such as t he ADC input r ange ment ioned).
2
5
CAREFUL BIASING AND CONTROLLED LEVELS ALLOW
DC COUPLING WITHIN SINGLE-SUPPLY SYSTEMS
Figure 2.21
Her e t he sour ce volt age is a ±2V 75ohm sour ce, which is DC coupled and t er minat ed
by R
T
. An AD812 amplifier is used, which has an input CM r ange of +1V t o +4V
(when oper at ing on +5V), and a minimum out put swing of 3Vp-p int o 1kohm on 5V.
It can easily swing t he r equir ed 2Vp-p at t he out put , so t her e is some lat it ude for
biasing it ar ound an out put level of V
s
/2. For unit y signal gain, equal value feedback
and input r esist or s ar e used. The R
F
and R
IN
values chosen ar e a slight compr omise
t o maximum bandwidt h (t he opt imum value is 715ohms), but t he input line is
t er minat ed pr oper ly at 75ohms (t he par allel equivalent value of R
T
and R
IN
).
The r esult ing r esist or values pr ovide a gain of about 1.95 t o t he DC volt age applied
t o pin 3, V
BIAS
. A volt age of 1.235V fr om a st able r efer ence sour ce such t he AD589
will fix t he st at ic out put DC level at 1.95• 1.235V, or 2.41V. Because of t he inver t ing
mode signal oper at ion, pin 2 of t he op amp does not change appr eciably wit h signal,
t her efor e t his node effect ively oper at es at a fixed DC level, equal t o V
BIAS
. As long
as t his bias volt age is well above t he amplifier ’s minimum CM r ange of +1V, t her e
should be no pr oblem. The RC net wor k at pin 3 pr ovides a noise filt er for t he diode.
If a mor e pr ecise out put DC level is r equir ed fr om t his st age, t hen V
BIAS
can be
adjust ed t o pr ovide it wit hout change t o t he st age’s signal gain.
Si n gle-Su p p ly Li n e Dr i ver s
By choosing a high fr equency op amp which is specified for oper at ion on low volt age
supplies, single-ended line dr iver s can also be adapt ed for single 5V supply
oper at ion. An example is t he 5V supply line dr iver cir cuit of Figur e 2.22, which also
illust r at es AC coupling in single-supply design.
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6
AC COUPLED SINGLE-SUPPLY LINE DRIVER
Figure 2.22
Speaking gener ally, t his cir cuit can use a number of op amps, bot h volt age and
cur r ent feedback t ypes. The out put of t he AD812 and AD813 devices can swing t o
wit hin about 1V of eit her r ail, allowing 3Vp-p out put s t o be deliver ed int o 150ohm
loads on 5V. While bandwidt h of t hese cur r ent feedback amplifier s does r educes wit h
low volt age oper at ion, t hey ar e st ill capable of a small signal 0.1dB bandwidt h on
t he or der of 10MHz, and good differ ent ial gain/phase per for mance, about
0.07%/0.06°, quit e good for a simple cir cuit . The AD817 and AD818 ar e not as clean
in per for mance, and not necessar ily r ecommended for 5V line dr iver s, but ar e
included as examples of mor e gener al pur pose volt age feedback t ypes oper able on
5V. For opt imizing t he bias and bandwidt h of any of t hese amplifier s, use t he
r esist or values fr om t he t able.
As would be expect ed, headr oom is cr it ical on such low supplies, so if not hing else,
biasing should be opt imized for t he volt age in use, via t he R5 value as not ed. R3 and
R4 ar e equal values, AC bypassed for minimum noise coupling fr om t he supply line.
All input and out put coupling capacit or s ar e lar ge in value, and ar e so chosen for a
minimum of low fr equency phase shift , for composit e video uses. They can be
r educed for applicat ions wit h higher low fr equency cut offs. C
OUT
is pot ent ially a
pr oblem in t he lar ge value shown, as lar ge elect r olyt ics can be induct ive. C5, a non-
cr it ical opt ional low induct ance shunt , can minimize t his pr oblem.
Obviously, t he st age cannot be dr iven beyond 3Vp-p at V
OUT
wit hout dist or t ion, so
oper at ing levels need t o maint ained conser vat ively below t his. The next sect ion
discusses AC coupling issues and headr oom in mor e det ail.
The AC coupling of ar bit r ar y wavefor ms can act ually int r oduce pr oblems which don’t
exist at all in DC coupled or DC r est or ed syst ems. These pr oblems have t o do wit h
2
7
t he wavefor m dut y cycle, and ar e par t icular ly acut e wit h signals which appr oach t he
r ails, as t hey can in low supply volt age syst ems which ar e AC coupled.
In an amplifier cir cuit such as t hat of Figur e 2.22, t he out put bias point will be equal
t o t he DC bias as applied t o t he op amp’s (+) input . For a symmet r ic (50% dut y cycle)
wavefor m of a 2Vp-p out put level , t he out put signal will swing symmet r ically about
t he bias point , or nominally 2.5V ±1V. If however t he pulsed wavefor m is of a ver y
high (or low) dut y cycle, t he AC aver aging effect of C
IN
and R4| | R5 will shift t he
effect ive peak level eit her high or low, dependent upon t he dut y cycle. This
phenomenon has t he net effect of r educing t he wor king headr oom of t he amplifier ,
and is illust r at ed in Figur e 2.23.
WAVEFORM DUTY CYCLE TAXES
HEADROOM IN AC COUPLED AMPLIFIERS
Figure 2.23
In Figur e 2.23 (A), an example of a 50% dut y cycle squar e wave of about 2Vp-p level
is shown, wit h t he signal swing biased symmet r ically bet ween t he upper and lower
clip point s of a 5V supply amplifier . This amplifier , for example, (an AD817 biased
similar ly t o Figur e 2.22) can only swing t o t he limit ed DC levels as mar ked, about
1V fr om eit her r ail. In cases (B) and (C), t he dut y cycle of t he input wavefor m is
adjust ed t o bot h low and high dut y cycle ext r emes while maintaining the same peak-
to-peak input level. At t he amplifier out put , t he wavefor m is seen t o clip eit her
negat ive or posit ive, in (B) and (C), r espect ively.
Since st andar d video wavefor ms do var y in dut y cycle as t he scene changes, t he
point is made t hat low dist or t ion oper at ion on AC coupled single supply st ages must
t ake t he dut y cycle headr oom degr adat ion effect int o account . If a st age has a 3Vp-p
out put swing available befor e clipping, and it must cleanly r epr oduce an ar bit r ar y
wavefor m, t hen t he maximum allowable amplit ude is less t han 1/2 of t his 3Vp-p
swing, t hat is <1.5Vp-p. An example of violat ing t his cr it er ia is cont ained t he 2Vp-p
wavefor m of Figur e 2.23, which is clipping for bot h t he high and low dut y cycles.
Not e t hat t he cr it er ia set down above is based on avoiding har d clipping, while
subt le dist or t ion incr eases may in fact t ake place at lower levels. This suggest s an
2
8
even mor e conser vat ive cr it er ia for lowest dist or t ion oper at ion such as composit e
NTSC video amplifier s.
Of cour se, amplifier s designed wit h r ail-r ail out put s and low dist or t ion in mind
addr ess t hese pr oblems most dir ect ly. One such device is t he AD8041, an XFCB
single-supply op amp designed for video applicat ions, and summar ized br iefly by
Figur e 2.24. As t hese dat a show, t his par t is designed t o pr ovide low NTSC video
dist or t ion while dr iving a single 75ohm sour ce t er minat ed load (in a cir cuit such as
Figur e 2.22).
RAIL-RAIL OUTPUT VIDEO OP AMPS ALLOW LOW
DISTORTION OUTPUT AND GREATEST FLEXIBILITY
Typical specifications for AD8041 op amp @ V
s
= +5V, T
A
= 25 C
Common Mode Range: -0.2V to +4V
Offset Voltage: 2mV
Bias Current: 1.2 A
Bandwidth: 80MHz
Slew Rate: 160V/ s
Differential Gain/Phase: 0.03%/ 0.03
(V
out
= 2Vp-p, R
L
=150 )
Output Current: 50mA (0.5V from rails)
Quiescent Current: 5mA
Disable Feature Allows Multiplexing
Figure 2.24
AP P LI CATI ON CI RCUI TS
A common video cir cuit r equir ement is t he mult iplexer , a st age which select s one of
“N” video input s, and t r ansmit s a buffer ed ver sion of t he select ed signal t o an out put
t r ansmission line. Video amplifier s which can oper at e int er nally in a swit ched mode,
such as t he AD810 and AD813, allow t his oper at ion t o be per for med dir ect ly in t he
video signal pat h wit h no addit ional har dwar e. This feat ur e is act ivat ed wit h t he use
of t he device’s disable pin, which when pulled low, disables t he amplifier and dr ops
power t o a low st at e. The AD810 is a single channel cur r ent feedback amplifier wit h
t his disable feat ur e, while t he AD813 offer s similar funct ionalit y, in a 14 pin, t hr ee
channel for mat . The high per for mance of t he AD813 on low volt ages allows it t o
achieve high per for mance on ±5V supplies, and t o be dir ect ly int er faced wit h
st andar d 5V logic dr iver s.
2:1 Vi d eo Mu lt i p lexer
The out put s of t wo AD810s can be wir ed t oget her t o for m a 2:1 mult iplexer wit hout
degr ading t he flat ness of t he gain r esponse. Figur e 2.25 shows a r ecommended
configur at ion, which r esult s in a 0.1dB bandwidt h of 20MHz and OFF channel
isolat ion of 77dB at 10MHz on ±5V supplies. The t ime t o swit ch bet ween channels is
about 750ns when t he disable pins ar e dr iven by open dr ain out put logic. Wit h t he
use of t he r ecommended 74HC04 as shown, t he swit ching t ime is about 180ns. The
swit ching t ime is only slight ly affect ed by t he signal level.
2
9
A 2:1 VIDEO MULTIPLEXER USING AD810s HAS -0.1dB
BANDWIDTH OF 20MHz AND SWITCHES IN 180ns
Figure 2.25
3:1 Vi d eo Mu lt i p lexer
A 3:1 video mult iplexer cir cuit using t he t r iple AD813 is shown in Figur e 2.26, and
feat ur es r elat ive simplicit y and high per for mance while oper at ing fr om ±5V power
supplies. The 3 st andar d 1Vp-p video input signals V
IN1
- V
IN3
dr ive t he 3 channels
of t he AD813, one of which is ON at a given moment . If say channel 1 is select ed,
amplifier sect ion 1 is enabled, by vir t ue of a logic HIGH signal on t he SELECT1 line
dr iving t he ENABLE input of t he fir st amplifier . The r emaining t wo amplifier
channels appear as open cir cuit s looking back int o t hem, but t heir feedback
net wor ks do appear as a load t o t he act ive channel. Cont r ol logic decoding is
pr ovided by U2, a 74HC238 1 of 8 logic decoder . The cont r ol lines A0 and A1 ar e
decoded as per t he t r ut h t able, which pr ovides select ion bet ween t he 3 input signals
and OFF, as not ed.
3
0
3:1 VIDEO MULTIPLEXER USING AD813 TRIPLE OP AMP
Figure 2.26
Some design subt let ies of t he cir cuit come about because of necessit y t o account for
sever al design cr it er ia. One is t he 590ohm value of feedback r esist or R1, t o pr ovide
opt imum r esponse t o t he AD813 cur r ent feedback amplifier ; anot her is t he par asit ic
loading of t he t wo unused gain r esist or net wor ks; a t hir d is t he sour ce t er minat ion of
t he line, 75ohms in t his case. While any given channel is ON, it dr ives not only load
r esist or R
L
, but also t he net dummy r esist ance R
X
/2, wher e R
X
is an equivalent
ser ies r esist ance equal t o R1 + R2 + R3. To pr ovide a net over all gain of unit y plus
and effect ive 75ohm sour ce impedance, t his set s t he r esist ance values of R1 + R2 +
R3 as shown.
3
1
SWITCHING CHARACTERISTICS OF 3:1 VIDEO MULTIPLEXER
Figure 2.27
Per for mance of t he cir cuit is excellent , wit h 0.1dB bandwidt h of 20MHz, and an OFF
st at e isolat ion of 60dB at 10MHz. Swit ching t ime is about 180ns, and is shown in
Figur e 2.27 swit ching bet ween t wo differ ent input s (t op t r ace) wit h t he cont r ol input
also shown (bot t om t r ace).
Vi d eo P r ogr a mma ble Ga i n Amp li fi er
Closely r elat ed t o t he 3:1 mult iplexer of Figur e 2.26 is a pr ogr ammable gain video
amplifier , or PGA, as shown in Figur e 2.28. Wit h a similar ly configur ed 2 line digit al
cont r ol input , t his cir cuit can be set up t o pr ovide 3 differ ent gain set t ings. This
makes it a useful t ool in var ious syst ems which can employ signal nor malizat ion or
gain r anging pr ior t o A/D conver sion, such as CCD syst ems, ult r asound, et c. The
gains can be binar y r elat ed as her e, or t hey can be ar bit r ar y. An ext r emely useful
feat ur e of t he AD813 cur r ent feedback amplifier t o t his applicat ion is t he fact t hat
t he bandwidt h does not r educe in inver se pr opor t ion, as gain is incr eased. Inst ead, it
st ays r elat ively const ant as gain is r aised. Thus mor e useful bandwidt h is available
at t he higher pr ogr ammed gains t han would be t r ue for a fixed gain-bandwidt h
pr oduct amplifier t ype.
3
2
GAIN OF 1, 2, 4 PROGRAMMABLE GAIN VIDEO AMPLIFIER
Figure 2.28
In t he cir cuit , channel 1 of t he AD813 is a unit y gain channel, channel 2 has a gain
of 2, and channel 3 a gain of 4, while t he four t h cont r ol st at e is OFF. As is indicat ed
by t he t able, t hese gains can var ied by adjust ment of t he R2/R3 or R4/R5 r at ios. For
t he gain r ange and values shown, t he PGA will be able t o maint ain a 3dB bandwidt h
of about 50MHz or mor e for loading as shown (a high impedance load of 1kohm or
mor e is assumed). Fine t uning of t he bandwidt h for a given gain set t ing can be
accomplished by t weaking t he absolut e values of t he feedback r esist or s (most
applicable at higher gains).
Di ffer en t i a l Dr i ver s
Many applicat ions r equir e gain/phase mat ched complement ar y or differ ent ial
signals. Among t hese ar e analog-digit al-conver t er (ADC) input buffer s, wher e
differ ent ial oper at ion can pr ovide lower levels of 2nd har monic dist or t ion for cer t ain
conver t er s. Ot her uses include high fr equency br idge excit at ion, and dr iver s for
balanced t r ansmission t wist ed pair lines such as UTP-5. While var ious t opologies
can be employed t o der ive differ ent ial dr ive signals, many cir cuit det ails as well as
t he t opologies t hemselves ar e impor t ant as t o how accur at e t wo out put s can be
maint ained.
I n ver t er -Follower Di ffer en t i a l Dr i ver
The cir cuit of Figur e 2.29 is useful as a high speed differ ent ial dr iver for dr iving
high speed 10-12 bit ADCs, differ ent ial video lines, and ot her balanced loads at
levels of 1-4Vr ms. As shown it oper at es fr om ±5V supplies, but it can also be adapt ed
t o supplies in t he r ange of ±5 t o ±15V. When oper at ed dir ect ly fr om ±5V as her e, it
3
3
minimizes pot ent ial for dest r uct ive ADC over dr ive when higher supply volt age
buffer s dr ive a ±5V power ed ADC, in addit ion t o minimizing dr iver power .
DIFFERENTIAL DRIVER USING INVERTER/FOLLOWER
Figure 2.29
In many of t hese differ ent ial dr iver s t he per for mance cr it er ia is high. In addit ion t o
low out put dist or t ion, t he t wo signals should maint ain gain/phase flat ness. In t his
dr iver , t wo sect ions of an AD812 dual cur r ent feedback amplifier ar e used for t he
channel A & B buffer s, U1A & U1B. This measur e can pr ovide inher ent ly bet t er
open-loop bandwidt h mat ching t han will t he use of t wo individual same par t number
singles (wher e bandwidt h var ies bet ween devices fr om differ ent manufact ur ing lot s).
The t wo buffer s her e oper at e wit h pr ecise gains of ±1, as defined by t heir r espect ive
feedback and input r esist ances. Channel B buffer U1B is convent ional, and uses a
mat ched pair of 715ohm r esist or s- t he value for using t he AD812 on ±5V supplies.
In channel A, non-inver t ing buffer U1A has an inher ent signal gain of 1, by vir t ue of
t he boot st r apped feedback net wor k R
FB1
and R
G1
(Refer ence 5). It also has a higher
noise gain, for phase mat ching. Nor mally a cur r ent feedback amplifier oper at ing as
a simple unit y gain follower would use one (opt imum) r esist or R
FB1
, and no gain
r esist or at all. Her e, wit h input r esist or R
G1
added, a U1A noise gain like t hat of
U1B r esult s. Due t o t he boot st r ap connect ion of R
FB1
-R
G1
, t he signal gain is
maint ained at unit y. Given t he mat ched open loop bandwidt hs of U1A and U1B,
similar noise gains in t he A-B channels pr ovide closely mat ched out put bandwidt hs
bet ween t he dr iver sides, a dist inct ion which gr eat ly impact s over all mat ching
per for mance.
In set t ing up a design for t he dr iver , t he effect s of r esist or gain er r or s should be
consider ed for R
G2
-R
FB2
. Her e a wor st case 2% mis-mat ch will r esult in less t han
0.2dB gain er r or bet ween channels A and B. This er r or can be impr oved simply by
specifying t ight er r esist or r at io mat ching, avoiding t r imming.
3
4
If desir ed, phase mat ching is t r immed via R
G1
, so t hat t he phase of channel A
closely mat ches t hat of B. This can be done for new cir cuit condit ions, by using a pair
of closely mat ched (0.1% or bet t er ) r esist or s t o sum t he A and B channels, as R
G1
is
adjust ed for t he best null condit ions at t he sum node. The A-B gain/phase mat ching
is quit e effect ive in t his dr iver , wit h t est r esult s of t he cir cuit as shown 0.04dB and
0.1° bet ween t he A and B out put signals at 10MHz, when oper at ed int o dual 150ohm
loads. The 3dB bandwidt h of t he dr iver is about 60MHz.
Net input impedance of t he cir cuit is set t o a st andar d line t er minat ion value such
as 75ohms (or 50ohms), by choosing R
IN
so t hat t he desir ed value r esult s wit h R
IN
in par allel wit h R
G2
. In t his example, an R
IN
value of 83.5ohms pr ovides a st andar d
input impedance of 75ohms when par alleled wit h 715ohms. For t he cir cuit just as
shown, dual volt age feedback amplifier t ypes wit h sufficient ly high speed and low
dist or t ion can also be used. This allows gr eat er fr eedom wit h r egar d t o r esist or
values using such devices as t he AD826 and AD828.
Gain of t he cir cuit can be changed if desir ed, but t his is not t ot ally st r aight for war d.
An easy st ep t o sat isfy diver se gain r equir ement s is t o simply use a t r iple amplifier
such as t he AD813, wit h t he t hir d channel as a var iable gain input buffer .
CROSS-COUPLED DIFFERENTIAL DRIVER
PROVIDES BALANCED OUTPUTS AND 250MHz BANDWIDTH
Figure 2.30
Cr oss-Cou p led Di ffer en t i a l Dr i ver
Anot her differ ent ial dr iver appr oach uses cr oss-coupled feedback t o get ver y high
CMR and complement ar y out put s at t he same t ime. In Figur e 2.30, by connect ing
AD8002 dual cur r ent feedback amplifier sect ions as cr oss-coupled inver t er s, t heir
out put s ar e for ced equal and opposit e, assur ing zer o out put common mode volt age.
3
5
The gain cell which r esult s, U1A and U1B plus cr oss-coupling r esist ances R
X
, is
fundament ally a differ ent ial input and out put t opology, but it behaves as a volt age
feedback amplifier wit h r egar d t o t he feedback por t at t he U1A (+) node. The gain of
t he st age fr om V
IN
t o V
OUT
is:
G
V
OUT
V
IN
2R1
R2
= =
wher e V
OUT
is t he differ ent ial out put , equal t o V
OUTA
– V
OUTB
.
This cir cuit has some unique benefit s. Fir st , differ ent ial gain is set by a single
r esist or r at io, so t her e is no necessit y for side-side r esist or mat ching wit h gain
changes, as is t he case for convent ional differ ent ial amplifier s (see line r eceiver s,
below). Second, because t he (over all) cir cuit emulat es a volt age feedback amplifier ,
t hese gain r esist ances ar e not as r est r ict ive as is t r ue in t he case of a convent ional
cur r ent feedback amplifier . Thus t hey ar e not highly cr it ical as t o absolut e value.
This is unlike st andar d applicat ions using cur r ent feedback amplifier s, and will be
t r ue as long as t he equivalent r esist ance seen by U1A is r easonably low (less t han
1kohm in t his case). Thir d, t he cell bandwidt h can be opt imized t o t he desir ed gain
by a single opt ional r esist or , R3, as follows. If for inst ance, a net gain of 20 is desir ed
(R1/R2=10), t he bandwidt h would ot her wise be r educed by r oughly t his amount ,
since wit hout R3 t he cell oper at es wit h a const ant gain-bandwidt h pr oduct . Wit h R3
pr esent however , advant age can be t aken of t he AD8002 cur r ent feedback amplifier
char act er ist ics. Addit ional int er nal gain is added by t he connect ion of R3, which,
given an appr opr iat e value, effect ively r aises gain-bandwidt h t o a level so as t o
r est or e t he bandwidt h which would ot her wise be lost by t he higher closed loop gain.
In t he cir cuit as shown, no R3 is necessar y at t he low wor king gain of 2 t imes
differ ent ial, since t he 511ohm R
X
r esist or s ar e alr eady opt imized for maximum
bandwidt h. Not e t hat t hese four mat ched r esist ances ar e somewhat cr it ical, and will
change in absolut e value wit h t he use of anot her cur r ent feedback amplifier . At
higher gain closed loop gains as set by R1/R2, R3 can be chosen t o opt imize t he
wor king t r ansconduct ance in t he input st ages of U1A and U1B, as follows:
R3
Rx
(R1 / R2) 1


As in any high speed inver t ing feedback amplifier , a small high-Q chip t ype feedback
capacit ance, C1, may be needed t o opt imize flat ness of fr equency r esponse. In t his
example, a 0.9pF value was found opt imum for minimizing peaking. In gener al,
pr ovision should be made on t he PC layout for an NPO chip capacit or in t he r ange of
0.5-2pF. This capacit or is t hen value select ed at boar d char act er izat ion for opt imum
fr equency r esponse.
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6
FREQUENCY RESPONSE OF AD8002 CROSS-COUPLED
DRIVER IS > 250MHz (C1 = 0.9pF 0.1pF)
Figure 2.31
For t he dual t r ace, 1-500MHz swept fr equency r esponse plot of Figur e 2.31, out put
levels wer e 0dBm int o mat ched 50ohm loads, t hr ough back t er minat ion r esist ances
R
TA
and R
TB
, at V
OUTA
and V
OUTB
. In t his plot t he ver t ical scale is 2dB/div, and
it shows t he 3dB bandwidt h of t he dr iver measur ing about 250MHz, wit h peaking
about 0.1dB. The four R
X
r esist or s along wit h R
TA
and R
TB
cont r ol low fr equency
amplit ude mat ching, which was wit hin 0.1dB in t he lab t est s, using 511ohm 1%
r esist or t ypes. For t ight est amplit ude mat ching, t hese r esist or r at ios can be mor e
closely cont r olled.
Due t o t he high gain-bandwidt hs involved wit h t he AD8002, t he const r uct ion of t his
cir cuit should follow RF r ules, wit h t he use of a gr ound plane, chip bypass capacit or s
of zer o lead lengt h at t he ±5V supply pins, and sur face mount r esist or s for lowest
induct ance.
Di ffer en t i a l Recei ver s
Anot her st andar d syst em applicat ion is t he line r eceiver funct ion, a st age which
accept s signals fr om a single-ended (or differ ent ial) t r ansmission line, and conver t s
t hem int o a buffer ed ver sion for local pr ocessing (r efer r ing back t o t he syst em
diagr am of Figur e 2.11). In a t ypical syst em, t her e is a single ended dr iving signal
V
IN
at t he or iginat ion point , a coaxial t r ansmission line wit h t he signal t er minat ed
in t he char act er ist ic line impedance at t he local end, and finally, a differ ent ial input
r eceiver . The syst em oper at es t he same in pr inciple for st andar d impedances of 50-
100ohms, as long as t he sour ce and load impedances mat ch t hat of t he line, under
which condit ions bandwidt h is maximized. In t he r eceiver , input impedance is
assumed high in r elat ion t o line impedance, and high common-mode r eject ion (CMR)
allows r eject ion of spur ious noise appear ing bet ween dr iver /r eceiver gr ounds. Noise
is r eject ed in pr opor t ion t o t he CMR of t he r eceiver amplifier , and t ypical CMR
per for mance goal for such a st age is 60-70dB or bet t er for fr equencies up t o 10MHz.
3
7
Funct ionally, t his syst em deliver s at t he out put of t he r eceiver st age a signal V
OUT
,
a r eplica of t he or iginal dr iving signal V
IN
. The r eceiver may also scale t he r eceived
signal, and may also be called on t o dr ive anot her t r ansmission line. Cr it ical
per for mance par amet er s for t he r eceiver ar e signal bandwidt h and dist or t ion
specificat ions. For line r eceiver s, video dist or t ion is r at ed in t er ms of differ ent ial
gain and differ ent ial phase at t he 3.58 MHz subcar r ier fr equency.
4 Resi st or Di ffer en t i a l Li n e Recei ver
Figur e 2.32 shows a low cost , medium per for mance line r eceiver using a high speed
op amp r at ed for video use. It is act ually a st andar d 4 r esist or inst r ument at ion
amplifier opt imized for high speed, wit h a differ ent ial t o single-ended gain of R2/R1.
Using low value, DC accur at e/AC t r immed r esist ances for R1-R4 and a high speed,
high CMR op amp pr ovides t he good per for mance. Pr act ically speaking however , at
low fr equencies r esist or mat ching can be mor e cr it ical t o over all CMR t han t he r at ed
CMR of t he op amp. For example, t he wor st case CMR (in dB) of t his cir cuit due t o
r esist or effect s is:
CMR
R
R
Kr
=
+










20
10
1
2
1
4
log
In t his expr ession t he t er m “Kr ” is a single r esist or t oler ance in fr act ional for m
(1%=0.01, et c.), and it is assumed t he amplifier has significant ly higher CMR
(gr eat er t han 100dB). Using discr et e 1% met al films for R1/R2 and R3/R4 yields a
wor st case CMR of 34dB, 0.1% t ypes 54dB, et c. Of cour se 4 r andom 1% r esist or s will
on t he aver age yield a CMR bet t er t han 34dB, but not dr amat ically so. A single sub-
st r at e dual mat ched pair t hin film net wor k is pr efer r ed, for r easons of best noise
r eject ion and simplicit y. One t ype suit able is t he Ohmt ek 1005, (Refer ence 6) which
has a r at io mat ch of 0.1%, which will pr ovide a wor st case low fr equency CMR of
66dB.
3
8
SIMPLE VIDEO LINE RECEIVER USING THE AD818 OP AMP
Figure 2.32
This cir cuit has an int er est ing and desir able side pr oper t y. Because of t he r esist or s
it divides down t he input volt age, and t he amplifier is pr ot ect ed against over volt age.
This allows CM volt ages t o exceed ±5V supply r ails in some cases wit hout hazar d.
Oper at ion at ±15V should const r ain t he input s wit hin t he r ails.
At fr equencies above 1MHz, t he br idge balance is dominat ed by AC effect s, and a
C1-C2 capacit ive balance t r im should be used for best per for mance. The C1
adjust ment is int ended t o allow t his, pr oviding for t he cancellat ion of st r ay layout
capacit ance(s) by elect r ically mat ching t he net C1-C2 values. In a given PC layout
wit h low and st able par asit ic capacit ance, C1 is best adjust ed once in 0.5pF
incr ement s, for best high fr equency CMR. Using designat ed PC pads, pr oduct ion
values t hen would use t he t r immed value. Good AC mat ching is essent ial t o
achieving good CMR at high fr equencies. C1-C2 should be t ypes similar physically,
such as NPO (or ot her st able) cer amic chip st yle capacit or s.
While t he cir cuit as shown has unit y gain, it can be gain-scaled in discr et e st eps, as
long as t he not ed r esist or r at ios ar e maint ained. In pr act ice, t his means using t aps
on a mult i-r at io net wor k for gain change, so as t o r aise bot h R2 and R4, in ident ical
pr opor t ions. Ther e is no ot her simple way t o change gain in t his r eceiver cir cuit .
Alt er nat ely, a scheme for cont inuous gain cont r ol wit hout int er act ion wit h CMR is t o
follow t his r eceiver wit h a scaling amplifier /dr iver wit h adjust able gain. The similar
AD828 dual amplifier allows t his wit h t he addit ion of only t wo r esist or s.
3
9
Video gain/phase per for mance of t his st age is dependent upon t he device is used for
U1 and t he oper at ing supply volt ages. Suit able volt age feedback amplifier s wor k
best at supplies of ±10 - ±15V, which maximizes op amp bandwidt h. And, while
many high speed amplifier s funct ion in t his cir cuit , t hose expr essly designed wit h
low dist or t ion video oper at ion per for m best . The cir cuit as shown can be used wit h
supplies of ±5 t o ±15V, but lowest NTSC video dist or t ion occur s for supplies of ±10V
or mor e, wher e differ ent ial gain/differ ent ial phase er r or s ar e less t han 0.01%/0.05°.
Oper at ing at ±5V t he dist or t ion r ises somewhat , but t he lowest power dr ain of
70mW occur s.
One dr awback t o t his cir cuit is t hat it does load a 75ohm video line t o some ext ent ,
and so should be used wit h t his loading t aken int o account . On t he plus side, it has
wide dynamic r ange for bot h signal and CM volt ages, plus t he inher ent over volt age
pr ot ect ion.
Act i ve Feed ba ck Di ffer en t i a l Li n e Recei ver
Fully int egr at ing t he line r eceiver funct ion eliminat es t he r esist or -r elat ed
dr awbacks of t he 4 r esist or line r eceiver , impr oving CMR per for mance, ease of use,
and over all cir cuit flexibilit y. An IC designed for t his funct ion is t he AD830 act ive
feedback amplifier (Refer ence 7,8). It s use as a differ ent ial line r eceiver wit h gain is
illust r at ed in Figur e 2.33.
VIDEO LOOP-THROUGH CONNECTION USING THE AD830
Figure 2.33
The AD830 oper at es as a feedback amplifier wit h t wo set s of fully differ ent ial
input s, available at pins 1-2 and 3-4, r espect ively. Int er nally, t he out put s of t he t wo
st ages ar e summed and dr ive a buffer out put st age. Bot h input st ages have high
CMR, and can handle differ ent ial signals up t o ±2V, and CM volt ages can r ange up
t o –V
s
+3V or +V
s
–2.1V, wit h a ±1V differ ent ial input applied. While t he AD830 does
not nor mally need pr ot ect ion against CM volt ages, if sust ained t r ansient volt age
beyond t he r ails is encount er ed, an opt ional pair of equal value (appr oximat ely
200ohms) r esist ances can be used in ser ies wit h pins 1-2.
4
0
In t his device t he over all feedback loop oper at es so t hat t he differ ent ial volt ages V
1-
2
and V
3-4
ar e for ced t o be equal. Feedback is t aken fr om t he out put back t o one
input differ ent ial pair , while t he ot her pair is dr iven by a differ ent ial input signal.
An impor t ant point of t his ar chit ect ur e is t hat high CM r eject ion is pr ovided by t he
t wo differ ent ial input pair s, so CMR isn’t dependent on r esist or br idges and t heir
associat ed mat ching pr oblems. The inher ent ly wideband balanced cir cuit and t he
quasi-float ing oper at ion of t he dr iven input pr ovide t he high CMR, which is t ypically
100dB at DC.
The gener al expr ession for t he U1 st age’s gain “G” is like a non-inver t ing op amp, or :
G
V
OUT
V
IN
R
R
= = + 1
2
1
For lowest DC offset , balancing r esist or R3 is used (equal t o R1| | R2).
In t his example of a video “loop-t hr ough” connect ion, t he input signal t apped fr om a
coax line and applied t o one input st age at pins 1-2, wit h t he scaled out put signal
t ied t o t he second input st age bet ween pins 3-4. Wit h t he R1-R4 feedback
at t enuat ion of 2/1, t he net r esult is t hat t he out put of U1, is t hen equal t o 2• V
IN
,
i.e., a gain of 2.
Funct ionally, t he input and local gr ounds ar e isolat ed by t he CMR of t he AD830,
which is t ypically 75dB at fr equencies below 1MHz, 60dB at 4.43MHz, and r elat ively
supply independent .
Wit h t he addit ion of an out put sour ce t er minat ion r esist or R
T
, t his cir cuit has an
over all loaded gain of unit y at t he load t er minat ion, R
L
. It is a gr ound isolat ing
video r epeat er , dr iving t he t er minat ed 75ohm out put line, deliver ing a final out put
equal t o t he or iginal input , V
IN
.
NTSC video per for mance will be dependent upon supplies. Dr iving a t er minat ed line
as shown, t he cir cuit has opt imum video dist or t ion levels for V
s
±15V, wher e
differ ent ial gain is t ypically 0.06%, and differ ent ial phase 0.08°. Bandwidt h can be
opt imized by t he opt ional 5.1pF (or 12pF) capacit or , C
A
, which allows a 0.1dB
bandwidt h of 10MHz wit h ±15V oper at ion. The differ ent ial gain and phase er r or s
det er ior at e about 2 or mor e t imes at ±5V.
4
1
REFERENCES:
1. Walt Kest er , Maintaining Transmission Line Impedances on the
PC Board, wit hin Chapt er 11 of Syst em Ap p li ca t i on s Gu i d e,
Analog Devices, 1993.
2. J oe Buxt on, Careful Design Tames High-S peed Op Amps,
Elect r on i c Desi gn , Apr il 11, 1991.
3. Walt J ung, Op Amps in Line-Driver and Receiver Circuits, Part 1,
An a log Di a logu e, Vol. 26-2, 1992.
4. William R. Blood, J r ., MECL Syst em Desi gn Ha n d book
(HB205, Rev.1), Mot or ola Semiconduct or Pr oduct s, Inc., 1988.
5. Dave Whit ney, Walt J ung, Applying a High-Performance Video
Operational Amplifier, An a log Di a logu e, 26-1, 1992.
6. Ohmt ek, Niagar a Falls, NY, (716) 283-4025.
7. Walt Kest er , Video Line Receiver Applications Using the AD830
Active Feedback Amplifier Topology, wit hin Chapt er 11 of Syst em
Ap p li ca t i on s Gu i d e, Analog Devices, 1993.
8. Walt J ung, Analog-S ignal-Processing Concepts Get More Efficient,
Elect r on i c Desi gn An a log Ap p li ca t i on s I ssu e, J une 24, 1993.
9. Walt J ung, Scot t Wur cer , Design Video Circuits Using High-S peed
Op-Amp S ystems, Elect r on i c Desi gn An a log Ap p li ca t i on s I ssu e,
November 7, 1994.
10. Thomas M. Fr eder iksen, I n t u i t i ve Op er a t i on a l Amp li fi er s,
McGr aw Hill, 1988.
11. D. St out , M. Kaufman, Ha n d book of Op er a t i on a l Amp li fi er
Ci r cu i t Desi gn , New Yor k, McGr aw-Hill, 1976.
12. J . Dost al, Op er a t i on a l Amp li fi er s, Elsevier Scient ific Publishing,
New Yor k, 1981.
13. 1992 Amp li fi er Ap p li ca t i on s Gu i d e, 1992, Analog Devices.
14. Walt er G. J ung, I C Op Amp Cook book , Th i r d Ed i t i on ,
SAMS (Division of Macmillan, Inc.), 1986.
15. W. A. Kest er , PCM S ignal Codecs for Video Applications,
SMP TE J ou r n a l, No. 88, November 1979, pp. 770-778.
4
2
16. IEEE S tandard for Performance Measurements of A/ D and D/ A
Converters for PCM Television Circuits, I EEE St a n d a r d 746-1984.
17. Tim Henr y, Analysis and Design of the Op Amp Current S ource,
Ap p li ca t i on Not e AN-587, Mot or ola, Inc., 1973.
1
SECTION 3
HIGH RESOLUTION
SIGNAL CONDITIONING ADCs
Sigma-Delta ADCs
High Resolution, Low Frequency
Measurement ADCs
2
SECTI ON 3
HI GH RESOLUTI ON SI GNAL
CONDI TI ONI NG ADCs
Wa l t Kest er , J a m es Br ya n t , J oe Bu xt on
The t r end in ADCs and DACs is t owar d higher speeds and higher r esolut ions at
r educed power levels. Moder n dat a conver t er s gener ally oper at e on ±5V (dual
supply) or +5V (single supply). Ther e ar e now a few conver t er s which oper at e on a
single +3V supply. This t r end has cr eat ed a number of design and applicat ions
pr oblems which wer e much less impor t ant in ear lier dat a conver t er s, wher e ±15V
supplies wer e t he st andar d.
Lower supply volt ages imply smaller input volt age r anges, and hence mor e
suscept ibilit y t o noise fr om all pot ent ial sour ces: power supplies, r efer ences, digit al
signals, EMI/RFI, and pr obably most impor t ant , impr oper layout , gr ounding, and
decoupling t echniques. Single-supply ADCs oft en have an input r ange which is not
r efer enced t o gr ound. Finding compat ible single-supply dr ive amplifier s and dealing
wit h level shift ing of t he input signal in dir ect -coupled applicat ions also becomes a
challenge.
In spit e of t hese issues, component s ar e now available which allow ext r emely high
r esolut ions at low supply volt ages and low power . This sect ion discusses t he
applicat ions pr oblems associat ed wit h such component s and shows t echniques for
successfully designing t hem int o syst ems.
LOW POWER, LOW VOLTAGE ADC DESIGN ISSUES
Low Power ADCs typically run on 5V, +5V, +5/+3V, or +3V
Lower Signal Swings Increase Sensitivity to All Types of Noise
(Device, Power Supply, Logic, etc.)
Device Noise Increases at Low Quiescent Currents
Bandwidth Suffers as Supply Current Drops
Input Common-Mode Range May be Limited
Selection of Zero-Volt Input/Output Amplifiers is Limited
Auto-Calibration Modes Highly Desirable at High Resolutions
Figure 3.1
3
SI GMA-DELTA ADCS
(COURTESY OF J AMES M. BRYANT)
Because Sigma-Delt a is such an impor t ant and popular ar chit ect ur e for high
r esolut ion (16 t o 24 bit s) ADCs, t he sect ion begins wit h a basic descr ipt ion of t his
t ype of conver t er .
Sigma-Delt a Analog-Digit al Conver t er s have been known for near ly t hir t y year s, but
only r ecent ly has t he t echnology (high-densit y digit al VLSI) exist ed t o manufact ur e
t hem as inexpensive monolit hic int egr at ed cir cuit s. They ar e now used in many
applicat ions wher e a low-cost , low-bandwidt h, low-power , high-r esolut ion ADC is
r equir ed.
Ther e have been innumer able descr ipt ions of t he ar chit ect ur e and t heor y of Sigma-
Delt a ADCs, but most commence wit h a maze of int egr als and det er ior at e fr om
t her e. In t he Applicat ions Depar t ment at Analog Devices, we fr equent ly encount er
engineer s who do not under st and t he t heor y of oper at ion of Sigma-Delt a ADCs and
ar e convinced, fr om st udy of a t ypical published ar t icle, t hat it is t oo complex t o
compr ehend easily.
Ther e is not hing par t icular ly difficult t o under st and about Sigma-Delt a ADCs, as
long as you avoid t he det ailed mat hemat ics, and t his sect ion has been wr it t en in an
at t empt t o clar ify t he subject . A Sigma-Delt a ADC cont ains ver y simple analog
elect r onics (a compar at or , a swit ch, and one or mor e int egr at or s and analog
summing cir cuit s), and quit e complex digit al comput at ional cir cuit r y. This cir cuit r y
consist s of a digit al signal pr ocessor (DSP) which act s as a filt er (gener ally, but not
invar iably, a low pass filt er ). It is not necessar y t o know pr ecisely how t he filt er
wor ks t o appr eciat e what it does. To under st and how a Sigma-Delt a ADC wor ks one
should be familiar wit h t he concept s of over-sampling, noise shaping, digital
filtering. and decimation.
SIGMA-DELTA ( - ) ADCs
Sigma-Delta ADCs are low-cost and have high resolution, excellent
DNL, low-power, although limited input bandwidth
A - ADC is Simple
The Mathematics, however is Complex
This section Concentrates on What Actually Happens!
Figure 3.2
4
SIGMA-DELTA ADC KEY CONCEPTS
Oversampling
Noise Shaping
Digital Filtering
Decimation
Figure 3.3
An ADC is a cir cuit whose digit al out put is pr opor t ional t o t he r at io of it s analog
input t o it s analog r efer ence. Oft en, but by no means always, t he scaling fact or
bet ween t he analog r efer ence and t he analog signal is unit y, so t he digit al signal
r epr esent s t he nor malized r at io of t he t wo.
Figur e 3.4 shows t he t r ansfer char act er ist ic of an ideal 3-bit unipolar ADC. The
input t o an ADC is analog and is not quant ized, but it s out put is quant ized. The
t r ansfer char act er ist ic t her efor e consist s of eight hor izont al st eps (when consider ing
t he offset , gain and linear it y of an ADC we consider t he line joining t he midpoint s of
t hese st eps).
TRANSFER CHARACTERISTIC OF
AN IDEAL 3-BIT UNIPOLAR ADC
Figure 3.4
Digit al full scale (all "1"s) cor r esponds t o 1 LSB below t he analog full scale (t he
r efer ence or some mult iple t her eof). This is because, as ment ioned above, t he digit al
code r epr esent s t he normalized r at io of t he analog signal t o t he r efer ence, and if t his
wer e unit y, t he digit al code would be all "0"s and "1" in t he bit above t he MSB.
5
The (ideal) ADC t r ansit ions t ake place at _ LSB above zer o and t her eaft er ever y
LSB, unt il 1_ LSB below analog full scale. Since t he analog input t o an ADC can
t ake any value, but t he digit al out put is quant ized, t her e may be a differ ence of up t o
_ LSB bet ween t he act ual analog input and t he exact value of t he digit al out put .
This is known as t he quantization error or quantization uncertainty. In AC
(sampling) applicat ions, t his quant izat ion er r or gives r ise t o quantization noise.
If we apply a fixed input t o an ideal ADC, we will always obt ain t he same out put ,
and t he r esolut ion will be limit ed by t he quant izat ion er r or .
Suppose, however , t hat we add some AC (dit her ) t o t he fixed signal, t ake a lar ge
number of samples, and pr epar e a hist ogr am of t he r esult s. We will obt ain
somet hing like t he r esult in Figur e 3.5. If we calculat e t he mean value of a lar ge
number of samples, we will find t hat we can measur e t he fixed signal wit h gr eat er
r esolut ion t han t hat of t he ADC we ar e using. This pr ocedur e is known as
over-sampling.
OVERSAMPLING WITH DITHER ADDED TO INPUT
Figure 3.5
The AC (dit her ) t hat we add may be a sine-wave, a t r i-wave, or Gaussian noise (but
not a squar e wave) and, wit h some t ypes of sampling ADCs (including Sigma-Delt a
ADCs), an ext er nal dit her signal is unnecessar y, since t he ADC gener at es it s own.
Analysis of t he effect s of differ ing dit her wavefor ms and amplit udes is complex and,
for t he pur poses of t his sect ion, unnecessar y. What we do need t o know is t hat wit h
t he simple over -sampling descr ibed her e, t he number of samples must be doubled for
each _bit of incr ease in effect ive r esolut ion.
If, inst ead of a fixed DC signal, t he signal t hat we ar e over -sampling is an AC signal,
t hen it is not necessar y t o add a dit her signal t o it in or der t o over -sample, since t he
signal is moving anyway. (If t he AC signal is a single t one har monically r elat ed t o
t he sampling fr equency, dit her may be necessar y, but t his is a special case.)
Let us consider t he t echnique of over -sampling wit h an analysis in t he fr equency
domain. Wher e a DC conver sion has a quantization error of up t o _ LSB, a sampled
dat a syst em has quantization noise. As we have alr eady seen, a per fect classical
6
N-bit sampling ADC has an r ms quant izat ion noise of q/(sqr t 12) unifor mly
dist r ibut ed wit hin t he Nyquist band of DC t o f
s
/2 (wher e q is t he value of an LSB
and f
s
is t he sampling r at e). Ther efor e, it s SNR wit h a full-scale sinewave input will
be (6.02N + 1.76) dB. If t he ADC is less t han per fect , and it s noise is gr eat er t han it s
t heor et ical minimum quant izat ion noise, t hen it s effective r esolut ion will be less
t han N -bits. Its ac t u al r eso lutio n ( o ft e n k n o wn as its E f fe c tiv e Nu m ber o f B its or
E N OB ) will be de f ine d by
ENOB
SNR dB
dB
=
− 176
6 02
.
.
.
SAMPLING ADC QUANTIZATION NOISE
Figure 3.6
If we choose a much higher sampling r at e, t he quant izat ion noise is dist r ibut ed over
a wider bandwidt h as shown in Figur e 3.7. If we t hen apply a digit al low pass filt er
(LPF) t o t he out put , we r emove much of t he quant izat ion noise, but do not affect t he
want ed signal - so t he ENOB is impr oved. We have accomplished a high r esolut ion
A/D conver sion wit h a low r esolut ion ADC.
7
OVERSAMPLING FOLLOWED BY DIGITAL FILTERING
AND DECIMATION IMPROVES SNR AND ENOB
Figure 3.7
Since t he bandwidt h is r educed by t he digit al out put filt er , t he out put dat a r at e may
be lower t han t he or iginal sampling r at e and st ill sat isfy t he Nyquist cr it er ion. This
may be achieved by passing ever y Mt h r esult t o t he out put and discar ding t he
r emainder . The pr ocess is known as "decimat ion" by a fact or of M. Despit e t he
or igins of t he t er m (decem is Lat in for t en), M can have any int eger value, pr ovided
t hat t he out put dat a r at e is mor e t han t wice t he signal bandwidt h. Decimat ion does
not cause any loss of infor mat ion (see Figur e 3.8).
DECIMATION
Figure 3.8
8
If we simply use over -sampling t o impr ove r esolut ion, we must over -sample by a
fact or of 2^2N t o obt ain an N-bit incr ease in r esolut ion. The Sigma-Delt a conver t er
does not need such a high over -sampling r at io because it not only limit s t he signal
passband, but also shapes t he quant izat ion noise so t hat most of it falls out side t his
passband.
If we t ake a 1-bit ADC (gener ally known as a compar at or ), dr ive it wit h t he out put of
an int egr at or , and feed t he int egr at or wit h an input signal summed wit h t he out put
of a 1-bit DAC fed fr om t he ADC out put , we have a fir st -or der Sigma-Delt a
modulat or as shown in Figur e 3.9. Add a digit al low pass filt er (LPF) and decimat or
at t he digit al out put , and we have a Sigma-Delt a ADC: t he Sigma-Delt a modulat or
shapes t he quant izat ion noise so t hat it lies above t he passband of t he digit al out put
filt er , and t he ENOB is t her efor e much lar ger t han would ot her wise be expect ed
fr om t he over -sampling r at io.
FIRST ORDER SIGMA-DELTA ADC
Figure 3.9
By using mor e t han one int egr at ion and summing st age in t he Sigma-Delt a
modulat or , we can achieve higher or der s of quant izat ion noise shaping and even
bet t er ENOB for a given over -sampling r at io as is shown in Figur e 3.10 for bot h a
fir st and second-or der Sigma-Delt a modulat or . The block diagr am for t he second-
or der Sigma-Delt a modulat or is shown in Figur e 3.11. Thir d, and higher , or der
Sigma-Delt a ADCs wer e once t hought t o be pot ent ially unst able at some values of
input - r ecent analyses using finite r at her t han infinit e gains in t he compar at or have
shown t hat t his is not necessar ily so, but even if inst abilit y does st ar t t o occur , it is
not impor t ant , since t he DSP in t he digit al filt er and decimat or can be made t o
r ecognize incipient inst abilit y and r eact t o pr event it .
9
SIGMA-DELTA MODULATORS
SHAPE QUANTIZATION NOISE
Figure 3.10
SECOND-ORDER SIGMA-DELTA ADC
Figure 3.11
Figur e 3.12 shows t he r elat ionship bet ween t he or der of t he Sigma-Delt a modulat or
and t he amount of over -sampling necessar y t o achieve a par t icular SNR.
1
0
SNR VERSUS OVERSAMPLING RATIO
FOR FIRST, SECOND, AND THIRD-ORDER LOOPS
Figure 3.12
The Sigma-Delt a ADCs t hat we have descr ibed so far cont ain int egr at or s, which ar e
low pass filt er s, whose passband ext ends fr om DC. Thus, t heir quant izat ion noise is
pushed up in fr equency. At pr esent , all commer cially available Sigma-Delt a ADCs
ar e of t his t ype (alt hough some which ar e int ended for use in audio or
t elecommunicat ions applicat ions cont ain bandpass r at her t han lowpass digit al
filt er s t o eliminat e any syst em DC offset s). Sigma-Delt a ADCs ar e available wit h
r esolut ions up t o 24-bit s for DC measur ement applicat ions (AD7710, AD7711,
AD7712, AD7713, AD7714), and wit h r esolut ions of 18-bit s for high qualit y digit al
audio applicat ions (AD1879).
But t her e is no par t icular r eason why t he filt er s of t he Sigma-Delt a modulat or
should be LPFs, except t hat t r adit ionally ADCs have been t hought of as being
baseband devices, and t hat int egr at or s ar e somewhat easier t o const r uct t han
bandpass filt er s. If we r eplace t he int egr at or s in a Sigma-Delt a ADC wit h bandpass
filt er s (BPFs), t he quant izat ion noise is moved up and down in fr equency t o leave a
vir t ually noise-fr ee r egion in t he pass-band (see Refer ence 1). If t he digit al filt er is
t hen pr ogr ammed t o have it s pass-band in t his r egion, we have a Sigma-Delt a ADC
wit h a bandpass, r at her t han a low pass char act er ist ic (see Figur e 3.13). Alt hough
st udies of t his ar chit ect ur e ar e in t heir infancy, such ADCs would seem t o be ideally
suit ed for use in digit al r adio r eceiver s, medical ult r asound, and a number of ot her
applicat ions.
1
1
REPLACING INTEGRATORS WITH RESONATORS
GIVES A BANDPASS SIGMA-DELTA ADC
Figure 3.13
A Sigma-Delt a ADC wor ks by over -sampling, wher e simple analog filt er s in t he
Sigma-Delt a modulat or shape t he quant izat ion noise so t hat t he SNR in the
bandwidth of interest is much lower t han would ot her wise be t he case, and by using
high per for mance digit al filt er s and decimat ion t o eliminat e noise out side t he
r equir ed passband. Because t he analog cir cuit r y is so simple and undemanding, it
may be built wit h t he same digit al VLSI pr ocess t hat is used t o fabr icat e t he DSP
cir cuit r y of t he digit al filt er . Because t he basic ADC is 1-bit (a compar at or ), t he
t echnique is inher ent ly linear .
Alt hough t he det ailed analysis of Sigma-Delt a ADCs involves quit e complex
mat hemat ics, t heir basic design can be under st ood wit hout t he necessit y of any
mat hemat ics at all. For fur t her discussion on Sigma-Delt a ADCs, r efer t o Refer ences
2 and 3.
SIGMA-DELTA SUMMARY
Linearity is Inherently Excellent
High Resolutions (16 - 24 Bits)
Ideal for Mixed-Signal IC Processes, no Trimming
No SHA Required
Charge Injection at Input Presents Drive Problems
Upper Sampling Rate Currently Limits Applications to
Measurement, Voiceband, and Audio, but Bandpass
Sigma-Delta Techniques Will Change This
Analog Multiplexing Applications are Limited by
Internal Filter Settling Time. Consider One Sigma-
Delta ADC per Channel.
Figure 3.14
1
2
HI GH RESOLUTI ON, LOW-FREQUENCY MEASUREMENT
ADCS
The AD7710, AD7711, AD7712, AD7713, and AD7714 ar e member s of a family of
sigma-delt a conver t er s designed for high accur acy, low fr equency measur ement s.
They have no missing codes at 24-bit s and useful r esolut ion of up t o 21.5-bit s
(AD7710, AD7711, AD7712, and AD7713), and 22.5 bit s (AD7714). They all use
similar sigma-delt a cor es, and t heir main differ ences ar e in t heir analog input s,
which ar e opt imized for differ ent t r ansducer s. The AD7714 is t he newest member of
t he family and is fully specified for eit her +5V (AD7714-5) or +3V (AD7714-3)
oper at ion.
The digit al filt er in t he sigma-delt a cor e may be pr ogr ammed by t he user for out put
updat e r at es bet ween 10Hz and 1kHz (AD7710, AD7711, AD7712), 2Hz and 200Hz
(AD7713), and 2Hz and 1kHz (AD7714). The effect ive r esolut ion of t hese ADCs is
inver sely pr opor t ional t o t he bandwidt h. For example, for 22.5-bit s of effect ive
r esolut ion, t he out put updat e r at e of t he AD7714 cannot exceed 10Hz. The AD771X
family is ideal for such sensor applicat ions as t hose shown in Figur e 3.15.
SIGNAL CONDITIONING, TRANSDUCER INPUT ADCs
THE AD7710, AD7711, AD7712, AD7713, AD7714
Ultra-High Resolution Measurement Systems
Implemented Using Conversion
Ideal for Applications Such As:

Weigh Scales
RTDs
Thermocouples
Strain Gauges
Process Control
Smart Transmitters
Medical
Figure 3.15
The AD771X family has a high level of int egr at ion which simplifies t he design of
dat a acquisit ion syst ems. For example, t he AD7710 (Figur es 3.16 and 3.17) has t wo
high impedance differ ent ial input s t hat can be int er faced dir ect ly t o many differ ent
sensor s, including r esist ive br idges. The t wo input s ar e select ed by t he int er nal
mult iplexer , which passes t he signal t o a pr ogr ammable gain amplifier (PGA). The
PGA has a digit ally pr ogr ammable gain r ange of 1 t o 128 t o accommodat e a wide
r ange of signal input s. Aft er t he PGA, t he signal is digit ized by t he sigma-delt a
modulat or . The digit al filt er not ch fr equency may be adjust ed fr om 10Hz t o 1kHz,
which allows var ious input bandwidt hs.
To achieve t his high accur acy, t he AD771X family has four differ ent int er nal
calibr at ion modes, including syst em and backgr ound calibr at ion. All of t hese
1
3
funct ions ar e cont r olled via a ser ial int er face. A benefit of t his ser ial int er face is t hat
t he AD771X-family fit s int o a 24-pin package, giving a small foot pr int for t he high
level of int egr at ion. All of t he par t s except t he AD7713 and AD7714 can oper at e on
eit her a single +5V or dual ±5V supplies. The AD7713 is designed exclusively for
single supply (+5V) oper at ion. The AD7714 is t he newest member of t he family and
is designed for eit her single +3V (AD7714-3) or single +5V (AD7714-5) low power
applicat ions. The AD771X family has <0.0015% non-linear it y.
THE AD771X-SERIES PROVIDES
A HIGH LEVEL OF INTEGRATION IN A 24-PIN PACKAGE
Figure 3.16
KEY FEATURES OF THE AD7710
0.0015% Nonlinearity
Two Channels with Differential Inputs
Programmable Gain Amplifier (G = 1 to 128)
Programmable Low Pass Filter
System or Self-Calibration Options
Single or Dual 5V Supply Operation
Microcontroller Serial Interface
Figure 3.17
1
4
The AD7710, AD7711, AD7712, and AD7713 have ident ical st r uct ur es of PGA,
sigma-delt a modulat or , and ser ial int er face. Their main differ ences ar e in t heir
input configur at ions. The AD7710 has t wo low level differ ent ial input s, t he AD7711
t wo low level differ ent ial input s wit h excit at ion cur r ent sour ces which make it ideal
for RTD applicat ions, t he AD7712 has one low level differ ent ial input and a single
ended high level input t hat can accommodat e signals of up t o four t imes t he
r efer ence volt age, and t he AD7713 is designed for loop-power ed applicat ions wher e
power dissipat ion is impor t ant . The AD7713 consumes only 3.5mW of power fr om a
single +5V supply.
The AD7714 is designed for eit her +3V (AD7714-3) or +5V (AD7714-5) single-supply,
low power applicat ions. It has a buffer bet ween t he mult iplexer and t he PGA which
can be enabled or bypassed using a cont r ol line. When t he buffer is act ive, it isolat es
t he analog input s fr om t he t r ansient cur r ent s and var iable impedance of t he
swit ched-capacit or PGA.
SUMMARY TABLE OF AD771X DIFFERENCES
AD7710:
2-Channel Low-Level Differential Inputs
AD7711:
1-Channel Low-Level Differential Input
1-Channel Low-Level Single-Ended Input
Excitation Current Sources for 3 or 4-Wire RTDs
AD7712:
1-Channel Low-Level Differential Input
1-Channel High-Level Single-Ended Input
AD7713:
2-Channel Low-Level Differential Inputs
1-Channel High-Level Single-Ended Input
Excitation Current Sources for 3 or 4-Wire RTDs
Single 5V Operation Only
Low Power (3.5mW)
No Internal Reference
AD7714:
3-Channel Low-Level Differential Inputs or 5-
Channel Pseudo-Differential Inputs
Single +3V (AD7714-3) or Single +5V (AD7714-5)
Low Power (1.5mW: AD7714-3)
No Internal Reference
Figure 3.18
Because of t he differ ences in analog int er faces, each device is best suit ed t o a
par t icular sensor or syst em applicat ion. In ot her wor ds, t he sensor and t he syst em
r equir ement s (i.e. t ype of sensor , single ver sus dual supply, power consumpt ion, et c.)
det er mine which conver t er should be used. Figur e 3.19 list s t he conver t er s, and t he
sensor s and applicat ions t o which t hey ar e best suit ed.
1
5
AD771X APPLICATIONS
AD7710:
Weigh Scales
Thermocouples
Chromatography
Strain Gauge
AD7711:
RTD Temperature Measurement
AD7712:
Smart Transmitters
Process Control
AD7713:
Loop-Powered Smart Transmitters
RTD Temperature Measurement
Process Control
Portable Industrial Instruments
AD7714:
Single +3V Supply Applications
Portable Industrial Instruments
Portable Weigh Scales
Figure 3.19
Alt hough t he AD7714 is oft en used as an example, t he following discussion applies
t o all t he conver t er s in t he family, wit h some minor except ions. The basic AD7714
ADC (see Figur e 3.20) is a swit ched capacit or sigma-delt a conver t er which oper at es
as has pr eviously been discussed in t his sect ion. The signals on t he input channels
pass t hr ough a swit ching mat r ix (mult iplexer ) and int o a bypassable buffer . The
buffer (available only in t he AD7714) allows t he input signals t o be isolat ed fr om t he
PGA swit ching t r ansient s and var iable impedance (PGA oper at ion will be descr ibed
shor t ly). The PGA gain is pr ogr ammable fr om 1 t o 128, t her eby allowing low level
signals t o be conver t ed wit hout t he need for ext er nal amplificat ion.
1
6
AD7714 SINGLE-SUPPLY MEASUREMENT ADC
Figure 3.20
The funct ional block diagr am of t he AD7714 shows t he PGA as separ at e fr om t he
sigma-delt a modulat or . In fact , it is par t of t he sigma-delt a int egr at or (see Figur e
3.21). The differ ent ial signal input char ges C2, which is t hen dischar ged int o t he
int egr at or summing node. This is done by closing S1 and S2, and t hen, aft er opening
t hem, closing S3 and S4. When t he PGA has a gain of 1 t his happens once per cycle
of t he basic 19.2kHz clock, but for gains of 2, 4, and 8 r espect ively it happens 2, 4, or
8 t imes per cycle. The int egr at or char ge is balanced by swit ching char ge in t he same
way fr om t he r efer ence int o C1, and t hence t o t he int egr at or summing node. The
polar it y of r efer ence swit ched depends on t he st at e of t he compar at or out put .
1
7
THE AD7714 - MODULATOR INCLUDES A PGA FUNCTION
Figure 3.21
At a gain of 8, t he sampling r at e is 153.6kHz. Higher swit ching r at es t han t his
would not allow C2 sufficient t ime t o char ge, so for PGA gains gr eat er t han 8, t he
value of t he r efer ence capacit or , C1, is r educed, r at her t han t he sampling r at e being
incr eased. Each t ime C1 is halved t he gain of t he syst em is doubled. The or iginal
value of C1 for gains of 1-8 is about 7pF in t he AD7714 and 20pF for t he ot her
member s of t he AD771X family.
The int er nal digit al filt er has t he sinc-cubed r esponse illust r at ed in Figur e 3.22. The
fir st not ch in t he filt er r esponse is pr ogr ammable accor ding t o t he for mula:
f
notch
f
clkin
128
1
Decimal Value of Digital Code
=











 ,
wher e f
clkin
is nor mally eit her 2.4576MHz or 1MHz for t he AD7714. The decimal
value of t he digit al code in t he above equat ion is loaded int o t he appr opr iat e r egist er
in t he AD7714. The mast er clock f
clkin
fr equency of 2.4576MHz is chosen because
50Hz and 60Hz may be obt ained by dir ect division as well as t he popular
communicat ions fr equencies of 19.2kHz and 9.6kHz.
1
8
AD7714 DIGITAL FILTER FREQUENCY RESPONSE
Figure 3.22
The fir st not ch fr equency is 3.82 t imes t he -3 dB fr equency, so t he not ch fr equency
must be chosen so t hat t he maximum signal fr equency falls wit hin t he filt er
passband.
The lower t he not ch fr equency, t he lower t he noise bandwidt h, and t her efor e t he
higher t he effect ive r esolut ion of t he conver t er . Mor eover , t he PGA gain will also set
limit s on t he achievable r esolut ion. Wit h a 2.5V span, 1 LSB in a 24-bit syst em is
only 150nV - wit h a gain of 128 it is 1.2nV!
As is evident fr om t heir pipeline ar chit ect ur e, sigma-delt a ADCs have a conver sion
t ime which is r elat ed t o t he bandwidt h of t he digit al filt er :- t he nar r ower t he
bandwidt h, t he longer t he conver sion. For a 10Hz not ch fr equency, t he AD7714 has
a 10Hz out put dat a r at e.
When t he input t o a sigma-delt a ADC changes by a lar ge st ep, t he ent ir e digit al
filt er must fill wit h t he new dat a befor e t he out put becomes valid, which is a slow
pr ocess. This is why sigma-delt a ADCs ar e somet imes said t o be unsuit able for
mult i-channel mult iplexed syst ems - t hey ar e not , but t he t ime t aken t o change
channels can be inconvenient . In t he case of t he AD771X-ser ies, four conver sions
must t ake place aft er a channel change befor e t he out put dat a is again valid (Figur e
3.23). The SYNC input pin r eset s t he digit al filt er , and if it used, dat a is valid on t he
t hir d out put aft er war ds, saving one conver sion cycle (when t he int er nal mult iplexer
is swit ched, t he SYNC is aut omat ically oper at ed). The SYNC input also allows
sever al AD771X ADCs t o be synchr onized.
1
9
THE RATE OF CONVERSION AND
SETTLING TIME DEPENDS ON THE FILTER SETTING
Figure 3.23
Alt hough t he AD771X sigma-delt a ADCs ar e 24-bit devices, it is not possible t o
obt ain 24 bit s of useful r esolut ion fr om a single sample because int er nal ADC noise
limit s t he accur acy of t he conver sion. We t hus int r oduce t he concept of "Effect ive
Resolut ion," or "Effect ive Number of Bit s," ENOB. This is a measur e of t he useful
signal-noise r at io of an ADC.
Noise in t he ADC is gener at ed by unwant ed signal coupling and by component s such
as r esist or s and act ive devices. Ther e is also int r insic quantization noise which is
inescapably linked t o t he analog-digit al conver sion pr ocess. As discussed in t he fir st
par t of t his sect ion, sigma-delt a ADCs use special t echniques t o shape t heir
quant izat ion noise and t hus r educe t heir over sampling r at io for a given ENOB, but
t hey cannot eliminat e quant izat ion noise ent ir ely.
In an ideal noise-fr ee ADC, it is possible t o posit ion a dc input signal so t hat t he
ADC digit al out put is always t he same code fr om sample t o sample. Ther e is no
quant izat ion noise pr esent , because only one code is being exer cised. In a r eal-wor ld
high r esolut ion ADC, however , t her e ar e int er nal noise sour ces which can cause t he
out put code t o change fr om sample t o sample for a const ant -value dc input signal.
Figur e 3.24 shows t he compar ison bet ween an ideal ADC and an one which has
int er nal noise. The r esult s ar e plot t ed as a hist ogr am, wher e t he ver t ical axis
r epr esent s t he number of occur r ences of each code out of t he t ot al number of 5000
samples used in t his example. In t he ideal ADC, all 5000 samples r esult in t he same
out put code. In t he pr act ical ADC, however , int er nal noise gener ally r esult s in a
dist r ibut ion of codes, cent er ed ar ound t he pr imar y code. In most cases, t he noise is
Gaussian, and a nor mal dist r ibut ion can be fit t ed t o t he point s on t he hist ogr am.
The st andar d deviat ion of t his dist r ibut ion, sigma, r epr esent s t he r ms value of t he
sum of all int er nal noise sour ces r eflect ed t o t he ADC out put , measur ed in LSBs.
This of cour se assumes a noise-fr ee input . The r ms value in LSBs can be conver t ed
easily t o an effect ive r ms volt age noise.
2
0
HISTOGRAM SHOWS THE EFFECT OF
INTERNAL ADC NOISE FOR A DC INPUT SIGNAL
Figure 3.24
The signal-t o-noise r at io can t hen be comput ed by dividing t he full scale ADC input
r ange by t he r ms noise comput ed fr om t he hist ogr am. The full scale input r ange for
t he AD771X-ser ies is equal t o t wice t he r efer ence volt age divided by t he gain of t he
PGA, and t he equat ion for calculat ing t he effective resolution in bit s is given by:
Effective Resolution log
2
2 V
REF
GAIN
1
RMS NOISE
=
×







DETERMINING EFFECTIVE RESOLUTION
Figure 3.25
Figur e 3.26 shows how RMS noise in an AD7714 var ies wit h gain and not ch
fr equency. Figur e 3.27 gives t he same r esult s in t er ms of effect ive r esolut ion, or
ENOB using t he pr evious equat ion. The effect ive out put noise comes fr om t wo
sour ces. t he fir st is t he elect r ical noise in t he semiconduct or devices used in t he
implement at ion of t he ADC fr ont end and t he modulat or (device noise). Secondly,
when t he analog input signal is conver t ed int o t he digit al domain, quant izat ion
noise is added.
2
1
The device noise is at a low level, and is lar gely independent of fr equency. The
quant izat ion noise st ar t s at an even lower level, but r ises r apidly wit h incr easing
fr equency t o become t he dominant noise sour ce. Consequent ly, lower filt er not ch
set t ings (below 100Hz appr oximat ely for f
clkin
= 2.4576MHz t end t o be device-noise
dominat ed, while higher not ch set t ings ar e dominat ed by quant izat ion noise.
Reducing t he filt er not ch and cut off fr equency in t he quant izat ion-noise dominat ed
r egion r esult s in a mor e dr amat ic impr ovement in noise per for mance t han it does in
t he device-noise dominat ed r egion. Fur t her mor e, quant izat ion noise is added aft er
t he PGA, so effect ive r esolut ion is lar gely independent of gain for t he higher filt er
not ch fr equencies. Meanwhile, device noise is added in t he PGA, and t her efor e
effect ive r esolut ion suffer s a lit t le at high gains for lower not ch fr equencies.
Addit ionally, in t he device-noise dominat ed r egion, t he out put noise (in µV) is
lar gely independent of r efer ence volt age, while in t he quant izat ion-noise dominat ed
r egion, t he noise is pr opor t ional t o t he value of t he r efer ence.
NOISE VARIES AS A FUNCTION
OF GAIN AND FILTER CUTOFF FREQUENCY
(AD7714-5, UNBUFFERED MODE, CLOCK = 2.4576 MHz)
Figure 3.26
EFFECTIVE RESOLUTION VERSUS
GAIN AND FIRST NOTCH FREQUENCY
(AD7714-5, UNBUFFERED MODE, CLOCK = 2.4576 MHz)
Figure 3.27
2
2
It is impor t ant t o dist inguish bet ween RMS and peak-t o-peak noise. Noise in a
sigma-delt a ADC has a Gaussian (or near Gaussian) dist r ibut ion. This means t hat if
one wait s long enough, any value of peak noise will event ually occur , and it is not
possible t o wr it e a specificat ion absolutely pr ohibit ing a specified value of noise
peak. For pr act ical pur poses, t he peak-t o-peak noise is defined as 6.6 t imes t he RMS
noise, since such peaks occur less t han 0.1% of t he t ime. The noise specified in t he
ENOB t able in Figur e 3.27 is expr essed in RMS t er ms. If a figur e for "noise-fr ee"
code r esolut ion is r equir ed, it will be appr oximat ely 3-bit s wor se: 20-bit s ENOB
becomes 17-bit s noise-fr ee code, et c. Since most applicat ions ar e concer ned wit h
noise power, however , t he RMS ENOB figur e is t he mor e commonly used.
This does not mean t hat t he or iginal 24-bit r esolut ion has no value, however .
Addit ional ext er nal filt er ing, t o nar r ower bandwidt hs t han t he int er nal filt er , can
fur t her impr ove t he r esolut ion and ENOB at t he expense of longer conver sion t imes.
The hist ogr am appr oach using a lar ge number of samples can also be used t o mor e
accur at ely define t he input signal.
ESTIMATING NOISE-FREE CODE RESOLUTION
Determined Using Peak-to-Peak Noise
Output RMS Noise 6.6 = Peak-to-Peak Noise
Factor of 6.6 is Approximately Equal to 3 bits:
log
2
(6.6) = 2.72
Therefore, subtract 3 bits from Effective Resolution Given in
Figure 3.27 to Determine Noise Free Code Resolution
Figure 3.28
The r esult s in Figur es 3.27 and 3.28 assume t he use of a low noise, heavily
decoupled ext er nal r efer ence and a noise-fr ee analog input . Noisy input s (and t he
r efer ence is an input ) r educe t he effect ive r esolut ion. For t his r eason, car eful
at t ent ion must be paid t o ext er nal noise sour ces. Figur e 3.29 list s aspect s of boar d
layout which may affect syst em noise, and hence t he ENOB of t he AD771X-ser ies.
2
3
OPTIMIZING NOISE PERFORMANCE
Pay Attention to Layout!
Use Ground Planes
Keep Analog PCB Tracks Short
Interface Directly with Transducer
Use Low Noise Amplifiers (AD797, OP-213, OP-177, AD707)
(Only if Required)
Connect Analog and Digital Grounds of Converters Together
at the Device, and Connect them to Analog Ground Plane
Route Digital PCB Tracks Clear of Analog Tracks
Filter Signal and Reference Inputs
Minimize Reference Noise
The Evaluation Board is an Example of Good Layout
Figure 3.29
The AD771X-ser ies is designed t o int er face dir ect ly wit h most t r ansducer s wit hout
t he need for ext er nal buffer ing or amplificat ion. If ext er nal amplifier s ar e used,
however , low noise devices such as t he OP-213 and AD797 should be chosen. To
det er mine if ext er nal amplifier s will lower t he AD771X syst em r esolut ion, t he t ot al
addit ional noise (in t he bandwidt h 0.1 Hz t o t he cut off fr equency set in t he AD771X)
should be calculat ed and compar ed wit h t he RMS noise figur es given in Figur e 3.26.
(Uncor r elat ed noise adds by r oot sum of squar es, so if t he addit ional noise is <50% of
t he AD7710 noise, it may be ignor ed; but if it exceeds t his level, it s effect on syst em
per for mance must be st udied car efully.)
An ext er nal filt er on t he input of t he AD771X-ser ies can impr ove it s noise
per for mance, because t he modulat or does not r eject noise at int eger mult iples of t he
sampling fr equency. This means t hat t her e ar e fr equency bands ±f
3dB
wide (f
3dB
is
t he cut off fr equency of t he int er nal digit al filt er ) wher e noise passes unat t enuat ed t o
t he out put . However , due t o t he AD771X high over sampling r at io, t hese bands
occupy only a small fr act ion of t he spect r um, and most br oadband noise is filt er ed.
The int er nal analog fr ont end pr ovides some filt er ing at t hese fr equencies (t he
at t enuat ion at 19.2kHz is appr oximat ely 70dB), but high level wideband noise can
degr ade syst em ENOB. A simple ext er nal RC low-pass filt er is gener ally sufficient t o
minimize t he effect s of t his noise, but t he r esist or and capacit or must be car efully
chosen so t hat t he gain accur acy of t he AD771X is not affect ed. If t he AD7714 is
used in t he buffer ed mode (i.e. t he int er nal buffer is act ive), t his r est r ict ion does not
apply.
2
4
INPUT FILTER HELPS REDUCE WIDEBAND NOISE
Figure 3.30
A simplified model of t he analog input of t he AD7714 in t he unbuffer ed mode is
shown in Figur e 3.31 (The AD7710, AD7711, AD7712, and AD7713 have similar
st r uct ur es). It consist s of a r esist or of appr oximat ely 7kohm (input mult iplexer on-
r esist ance) connect ed t o t he input t er minal and t o an analog swit ch which swit ches a
7pF sampling capacit or bet ween t he r esist or and gr ound, wit h a mar k-space r at io of
50%. The swit ching fr equency depends on f
clkin
and t he gain which is being used:
wit h a gain of unit y and t he st andar d clock fr equency of 2.4576MHz, t he swit ching
fr equency is 19.2kHz, and at gains of 2, 4, and 8 or mor e it is 38.4, 76.8, and
153.6kHz r espect ively.
If t he conver t er is wor king t o an accur acy of 20-bit s, t he capacit or must char ge wit h
an accur acy of 20-bit s. The input RC t ime const ant due t o t he swit ch on-r esist ance
(7kohm) and t he sampling capacit or (7pF) is 49ns. If t he char ge is t o achieve 20-bit
accur acy, it must char ge for at least 14x t he t ime const ant , or 686ns. Any ext er nal
r esist or in ser ies wit h t he input will incr ease t he t ime const ant , and t he char t in
Figur e 3.31 shows accept able values of ser ies r esist ance necessar y t o maint ain 20-
bit per for mance.
To det er mine t he minimum char ge t ime for 20-bit per for mance wit h an ext er nal
r esist ance R
ext
we use t he equat ion:
Minimum Char ge Time = 14(R
ext
+ 7kohm) x 7pF
The minimum char ge t ime must be less t han half t he per iod of t he swit ching signal
used (it has a 50% dut y cycle). The fast est swit ching fr equency wit h t he st andar d
2.4576MHz clock is 153.6kHz (for a gain of 8 or gr eat er ), and half of t hat clock
per iod is 3.3µs, which allows a maximum R
ext
of 26.8kohm. At lower gains R
ext
may
be lar ger .
2
5
AD7714 ANALOG INPUT STRUCTURE
(UNBUFFERED MODE)
Figure 3.31
It is not pr act ical t o use R
ext
in conjunct ion wit h a capacit or t o gr ound fr om t he
input pin of t he AD7710, AD7711, AD7712, or AD7713 (or t he AD7714 oper at ing in
t he unbuffer ed mode) t o make an ant i-aliasing filt er (wit h a cut off fr equency less
t han one-half t he input sampling fr equency), unless t he capacit or is dr amat ically
lar ger t han t he 7pF C
int
. This is because C
int
is dischar ged on ever y sampling clock
cycle and will r echar ge fr om t he filt er capacit or . Ther efor e, eit her t he filt er capacit or
must be so lar ge t hat char ging C
int
fr om it changes it s volt age by less t han an LSB
at 20-bit s (i.e. it is lar ger t han 7µF), or t he t ime const ant R
ext
C
ext
must be shor t
enough for C
ext
t o r echar ge befor e t he next clock cycle - in which case t he cut off
fr equency due t o R
ext
and

C
ext
is not low enough t o make an ant i-aliasing filt er
wit h r espect t o t he sampling fr equency. Ther e may, however , be some benefit in
such a filt er if t her e is input noise at high fr equencies. The dat a sheet s for t he
AD771X-ser ies cont ain t ables which give t he allowable ext er nal capacit or and
r esist or values as a funct ion of PGA gain for 16-bit and 20-bit gain accur acy (see
Figur e 3.32).
Not e t hat if an ext er nal R
ext
and C
ext
ar e used, t he capacit or t ype must have low
non-linear it ies and dielect r ic absor pt ion. Film t ypes such as polyst yr ene or
polypr opylene ar e r ecommended.
2
6
AD7714 EXTERNAL FILTER RESTRICTIONS ON R AND C FOR
NO 20-BIT GAIN ERROR (UNBUFFERED MODE ONLY)
Figure 3.32
The advant age of t he AD7714 oper at ing in t he buffer ed mode is t hat a t r ue input
ant ialiasing filt er can be used wit hout affect ing t he gain accur acy. The penalt y is
only a slight incr ease in noise (appr oximat ely 10%) and a small r educt ion in input
common-mode volt age r ange. If t he value of t he ser ies r esist or is lar ge, t he effect s of
t he input bias cur r ent must be consider ed, but t his er r or can be r emoved using t he
calibr at ion modes.
Some successive appr oximat ion and subr anging ADCs dr aw lar ge t r ansient cur r ent s
at t heir analog and r efer ence input s which load t heir r espect ive dr ive cir cuit r y and
cause er r or s. Oft en, special dr ive amplifier s wit h low out put impedance at
fr equencies well above t he conver sion clock fr equency ar e necessar y t o avoid t his
pr oblem, but t hese pr oblems do not occur wit h t he ver y small t r ansient loads of t he
AD771X devices. The oscilloscope phot ogr aph in Figur e 3.33 shows t he t r ansient
cur r ent in an AD7710. It was t aken wit h a 1kohm r esist or in ser ies wit h t he input t o
measur e t he change in cur r ent . This cir cuit pr oduces a 15mV spike of less t han 1µs
dur at ion. The cor r esponding peak pulse cur r ent is only 15µA, which per mit s t he use
of quit e high impedance signal sour ces wit h no r isk of degr ading t he ENOB. As
discussed ear lier , t he AD7714 oper at ing in t he buffer ed mode has no significant
t r ansient s on it s analog input .
2
7
INPUT TRANSIENT LOADING IS
MINIMAL IN THE AD77XX FAMILY
Figure 3.33
The AD771X family was designed t o simplify t r ansducer int er facing. Many t ypes of
t r ansducer s can be connect ed dir ect ly t o t he input of one of t he AD771X family
wit hout addit ional cir cuit r y, but some car e is necessar y t o achieve t he best possible
accur acy:- noise needs t o be minimized (a simple capacit or acr oss a r esist ive sensor
may be all t he filt er ing t hat is needed, but t his must be checked - noise is
par t icular ly impor t ant , because noise cannot be r emoved by t he syst em calibr at ion
which eliminat es gain and offset er r or s); t r ansducer sour ce impedance may affect
char ge t imes (as ment ioned above); and bias cur r ent s flowing in high impedance
t r ansducer s may cause er r or s, alt hough t hese can be r emoved by syst em calibr at ion.
In gener al, syst em calibr at ion can r emove most dc er r or s in syst ems using t he
AD771X family.
2
8
TRANSDUCER CONNECTION CONSIDERATIONS
Filter Noisy Signals
Use Shielded, Twisted Pair Cable (Shield Grounded at
AGND/DGND Connection Point at ADC, floating at transducer)
DC Leakage (bias) Current = 10pA can cause offset with
R
source
This causes drift over temperature
To Maintain Accuracy:

Minimize R
source
Use Differential inputs and balance R
source
Use system calibration techniques
Figure 3.34
Cir cuit r y connect ed t o t r ansducer s must gener ally be pr ot ect ed against over -volt age
fr om ESD, noise pickup, or accident al shor t s. If signals ar e likely t o go out side t he
posit ive or negat ive supplies, some for m of clamp is necessar y t o keep t hem wit hin
t hem. Figur e 3.35 shows a suit able cir cuit for pr ot ect ing AD771X devices. The
AD7710 has int er nal ESD pr ot ect ion diodes bet ween t he input and bot h supplies
which conduct when t he input exceeds eit her supply by mor e t han about 0.6V.
Excessive cur r ent in t hese diodes will vapor ize met al t r acks on t he chip and damage
t he cir cuit , so an ext er nal r esist or , R
p
, is necessar y t o limit cur r ent t o a safe 5mA
dur ing over -volt age event s. R
p
may be det er mined by a simple calculat ion:
R
p
V
max
V
supply
5mA
=

R
p
will cont r ibut e noise t o t he syst em ( t he basic J ohnson noise equat ion applies:
e
n
kTBR
p
= 4
wher e k is Bolt zmann's Const ant , T is t he absolut e t emper at ur e and B is t he
bandwidt h). If t he noise due t o R
p
is t oo high, R
p
can be r educed if ext er nal Schot t ky
diodes ar e used in addit ion t o t he diodes on t he chip.
2
9
INPUT OVERVOLTAGE PROTECTION
Figure 3.35
Ther e ar e no special r equir ement s for t hese Schot t ky diodes, as long as t hey have
low leakage cur r ent and can handle t he necessar y fault cur r ent levels while
maint aining a low t ur n-on volt age.
As impor t ant as t he analog signal input is t he r efer ence input . Figur e 3.36 shows a
simplified model of t he r efer ence input , which is ver y similar t o t hat of t he analog
input (wit h t he except ion of t he AD7714 oper at ing in t he buffer ed mode). The ser ies
r esist or is 5kohm, and t he value of t he capacit or depends on t he gain set t ing and t he
par t icular device. For gains of 1-8, t he capacit or is appr oximat ely 7pF for t he
AD7714. Above 8, t he capacit or 's value is halved for each doubling of gain. The value
of t he capacit or (G = 1-8) for ot her member s of t he AD771X ser ies is 20pF.
REFERENCE VOLTAGE CONSIDERATIONS
Figure 3.36
3
0
An impor t ant consider at ion in choosing a r efer ence for t he AD771X-ser ies is noise.
Many r efer ences have out put noise which exceeds t hat of t he AD771X and cause
r educed accur acy. Filt er ing may help in such cases, but a low noise r efer ence should
be select ed wher ever possible.
Alt hough t he AD7710, AD7711, and AD7712 have int er nal +2.5V r efer ences which
may be connect ed t o t heir posit ive r efer ence input , t heir use will degr ade t he
effect ive r esolut ion of t he ADCs by appr oximat ely 1 bit for filt er cut -off fr equencies
of 60Hz or less. The noise calculat ions using t he AD7710 int er nal r efer ence ar e
shown in Figur e 3.37. For opt imum noise per for mance, a low noise ext er nal
r efer ence such as t he AD780 should be used as shown in Figur e 3.38.
INTERNAL REFERENCE VOLTAGE NOISE
CONSIDERATIONS FOR AD7710, AD7711, AD7712 ADCs
Figure 3.37
USE A LOW NOISE EXTERNAL REFERENCE
FOR OPTIMUM NOISE PERFORMANCE AND RESOLUTION
Figure 3.38
3
1
The AD780 2.5V r efer ence has noise of 4µV p-p in t he r ange 0.1 t o 10Hz. This is
equivalent t o 0.606µV r ms (obt ained by dividing t he peak-t o-peak value by 6.6).
This gives 0.31µV r ms noise in t he 2.62Hz bandwidt h associat ed wit h a 10Hz updat e
r at e. This is negligible compar ed t o t he AD7710 inher ent noise of 1.7µV r ms (G = 1).
Wit h out put r at es of 1kHz or mor e, and cut off fr equency of 262Hz, t he noise of t he
AD780 may be r educed by 50% if a 0.1µF capacit or is connect ed t o it s out put (unlike
many IC volt age r efer ences, t he AD780 is st able wit h all values of capacit ive load).
CALCULATING REFERENCE NOISE CONTRIBUTION
Figure 3.39
The AD780 is also a suit able r efer ence for t he AD7714 ADC, whose noise wit h a
10Hz updat e r at e (G = 1, Vsupply = +5V) is 1.0µV r ms. When t he AD7714 is
oper at ing on a +3V supply, it r equir es a low-noise 1.25V r efer ence, and t he AD589 is
a suit able choice.
When t he AD771X-ser ies ADCs ar e oper at ed at higher out put r at es and higher
input bandwidt hs, t he ADC noise is significant ly higher , and less effect ive r esolut ion
is r equir ed. This allows t he use of higher noise, lower power r efer ences such as t he
REF192 (25µV p-p noise, 0.1 t o 10Hz) which only r equir es 45µA of quiescent cur r ent ,
compar ed t o 0.75mA for t he AD780.
Regar dless of t he r efer ence select ed, it should be pr oper ly decoupled in or der t o act
as a char ge r eser voir t o t r ansient load cur r ent s as well as a filt er for wideband noise.
This implies t hat t he r efer ence must be st able under capacit ive loads, which is not
necessar ily t he case in all r efer ences. In fact , some r efer ences act ually require an
ext er nal decoupling capacit or in or der t o maint ain st abilit y. Regar dless of t he
r efer ence select ed, t he dat a sheet should be car efully examined wit h r espect t o
out put capacit ive loading. Fur t her infor mat ion on applying volt age r efer ences can be
obt ained in Refer ences 5, 6, and 7.
3
2
LOW VOLTAGE REFERENCE SUMMARY
Figure 3.40
DC er r or s also affect conver sion accur acy, but AD771X devices can calibr at e
t hemselves t o cor r ect dc er r or s. The AD7710, AD7711, AD7712, and AD7713 have
four differ ent calibr at ion modes. These ar e summar ized in Figur e 3.41 and compr ise
Self Calibr at ion, Syst em Calibr at ion, Syst em-Offset Calibr at ion, and Backgr ound
Calibr at ion. Each calibr at ion cycle cont ains t wo conver sions, one each for zer o-scale
and for full-scale calibr at ion. The calibr at ion modes for t he AD7714 ar e similar ,
except t hat in t he Backgr ound-Calibr at ion Mode, only zer o-scale is calibr at ed.
AD771X OFFERS 4 CALIBRATION OPTIONS
Figure 3.41
To init iat e a calibr at ion cycle, t he appr opr iat e code must be sent t o t he cont r ol
r egist er . Aft er t he code is sent , t he AD771X aut omat ically conduct s t he ent ir e
oper at ion, and clear s t he cont r ol r egist er of t he calibr at ion command so t hat a
separ at e command t o st op calibr at ion is not necessar y. Since t he filt er in t he sigma-
delt a conver t er must pur ge it self of it s pr evious r esult for four out put updat e cycles
whenever t he input sees a full-scale st ep t he t ot al calibr at ion oper at ion t akes nine
such cycles.
Self Calibr at ion r emoves er r or s in an AD771X by connect ing t he input t o gr ound and
per for ming a conver sion, and t hen connect ing t he input t o V
r ef
and per for ming
anot her . The r esult s of t hese conver sions ar e used t o calibr at e t he device.
3
3
Backgr ound Calibr at ion is a var iat ion of Self Calibr at ion. The only differ ence is t hat
when an AD771X is placed in Backgr ound Calibr at ion mode, it cont inually
calibr at es it self at r egular int er vals wit hout fur t her inst r uct ions. This ensur es t hat
t he AD771X r emains calibr at ed r egar dless of dr ift . The Backgr ound Calibr at ion
cycle alt er nat es calibr at ion conver sions wit h signal conver sions: zer o
calibr at e/conver t signal/full-scale calibr at e/conver t signal/zer o calibr at e/et c. This
pr ovides cont inuous calibr at ion but r educes t he out put dat a r at e by a fact or of six.
Backgr ound Calibr at ion for t he AD7714 only calibr at es zer o-scale.
Syst em Calibr at ion is int ended t o calibr at e all t he element s pr ior t o t he ADC which
may cont r ibut e t o syst em er r or s, as well as t he ADC it self. (For example an
inst r ument at ion amplifier int r oduces er r or s int o a syst em due t o it s own offset , dr ift
and gain er r or . These er r or s can be r emoved by Syst em Calibr at ion.) However ,
Syst em Calibr at ion r equir es addit ional analog swit ches t o connect system input s t o
gr ound and a r efer ence as well as t o t he or iginal signal sour ce. The fir st st ep in
Syst em Calibr at ion r equir es ext er nal gr ounding of t he syst em input t er minal t o
calibr at e out offset s. The second st ep r equir es t hat t he input be connect ed t o a
r efer ence, which calibr at es gain er r or at full-scale. The Syst em Calibr at ion cycle
r equir es t he sending of t wo separ at e inst r uct ions t o t he cont r ol r egist er as well as
cont r ol of t he analog swit ches at t he syst em input . It must be r epeat ed r egular ly t o
cor r ect for dr ift wit h t ime and t emper at ur e.
The final calibr at ion mode is Syst em-Offset Calibr at ion. This calibr at es system
offset s, and the AD771X gain. Again, it r equir es ext er nal analog swit ches at t he
syst em input , and separ at e inst r uct ions for zer o and gain calibr at ion. For t he fir st
cycle, t he syst em input is connect ed t o gr ound and t he AD771X calibr at es for syst em
offset s. Dur ing t he second cycle, t he ADC input is connect ed t o t he r efer ence for
ADC gain calibr at ion.
CALIBRATION ISSUES
Figure 3.42
3
4
When calibr at ion is complet e, DRDY goes low - but it does not necessar ily go high as
soon as t he calibr at ion command is sent t o t he ADC, t her e may be a delay of up t o
one out put dat a cycle befor e it does so. Cont r oller s should t her efor e look for a 0 t o 1
t r ansit ion, r at her t han t he pr esence of a 0, on DRDY t o signal t he complet ion of a
calibr at ion aft er it has been commanded.
Calibr at ion is cr ucial t o achieving t he r at ed accur acy of AD771X devices and should
be per for med immediat ely aft er power -up and r epeat ed r egular ly. A 1.25µV/°C
t emper at ur e coefficient of input offset and a 2°C t emper at ur e change causes an LSB
of er r or in a 20-bit 2.5V syst em. Any r efer ence dr ift adds t o t he er r or . Fr equent
calibr at ion ensur es t hat t emper at ur e changes do not degr ade t he accur acy of
conver sions.
CALIBRATE OFTEN TO MAINTAIN ACCURACY
Temperature Drift can cause errors
Unipolar offset drift of 2.5 V is 1 LSB in a 20 bit system
(2.5V full-scale)
Reference voltage drift adds to this error
Calibration can remove gain errors created by input filters
Therefore, to minimize errors, calibrate often.
Always calibrate on power-up!
Calibration coefficients can be manually adjusted
Figure 3.43
When t he AD771X execut es a calibr at ion cycle, it saves t wo coefficient s in int er nal
r egist er s. One r egist er st or es t he full scale calibr at ion coefficient , FSC, and t he ot her
st or es t he zer o scale calibr at ion coefficient , ZSC. Adjust ing t he calibr at ion
coefficient s manually may be useful in some applicat ions. For example, in a weigh
scale applicat ion it may be necessar y t o inser t an offset t o account for a fixed weight .
It is possible t o r ead fr om and wr it e t o t he calibr at ion r egist er s of member s of t he
AD771X family, making adjust ment of calibr at ion coefficient s a st r aight for war d
t ask. Det ails of t his pr ocedur e ar e given in Refer ences 4 and 8.
A t ypical applicat ion of t he AD7710 is in a weigh scale (Figur e 3.44). These gener ally
use a r esist ive br idge as t heir sensing element and r equir e r esolut ion of at least
16-bit s and oft en mor e. The AD7710 dr amat ically simplifies t he design of such a
syst em: t he br idge is connect ed dir ect ly t o it s differ ent ial input s, making an ext er nal
inst r ument at ion amplifier unnecessar y. The excit at ion for t he br idge, and t he
r efer ence for t he AD7710, ar e pr ovided by an AD780, whose low noise helps t o
pr eser ve t he syst em ENOB. Because t he syst em bandwidt h is limit ed (bot h by t he
conver sion r at e select ed and t he filt er capacit or s on t he br idge) t he ENOB
achievable is quit e high (appr oximat ely 20-bit s) but t he conver sion (and out put dat a)
r at e is r at her low at 10Hz.
3
5
WEIGH SCALE APPLICATION USING THE AD7710
Figure 3.44
The conver t er s in t he AD771X family all have ser ial int er faces, which ar e
descr ibed in gr eat er det ail in t he dat a sheet . They have cont r ol r egist er s t hat cont r ol
all t heir oper at ions. Changing t he PGA gain, st ar t ing a calibr at ion, and changing
t he filt er par amet er s ar e all accomplished by wr it ing t o t he appr opr iat e r egist er . On
t he ot her hand, dat a can be r ead eit her as a 16-bit or a 24-bit oper at ion - one of t he
bit s in t he cont r ol r egist er cont r ols t he size of t he dat a wor d. The DRDY out put
indicat es when a conver sion is complet e and valid dat a is available in t he out put
r egist er .
Figur e 3.45 shows an isolat ed 4-wir e int er face t o t he AD7713 using common opt o-
isolat or s. Over 6kV of isolat ion is possible. The TFS, A0, and SYNC lines ar e t ied
t oget her at t he conver t er t o minimize t he number of cont r ol lines. Tying TFS t o AO
causes a wr it e t o t he device t o load dat a t o t he cont r ol r egist er , and any r ead
accesses t he dat a r egist er . The only r est r ict ions of t his met hod of cont r ol is t hat t he
cont r oller cannot wr it e t o t he calibr at ion r egist er s and cannot r ead fr om t he cont r ol
r egist er . In many applicat ions t hese capabilit ies ar e unnecessar y. Four
opt o-isolat or s car r y dat a and inst r uct ions fr om t he cont r oller t o t he ADC and a fift h,
wit h a 74HC125 on each side of t he isolat ion bar r ier , car r ies dat a t o t he cont r oller .
The AD7713 is ideal for t his par t icular applicat ion because it s low supply cur r ent
minimizes t he load on t he isolat ed power supply.
3
6
ISOLATED 4-WIRE INTERFACE USING AD7713
Figure 3.45
The AD771X family gener ally int er faces wit h some t ype of micr opr ocessor . Their
dat a sheet includes cir cuit s and micr o-code for int er facing t o t he 8051 and 68HC11
micr ocont r oller and t he ADSP-2103/2105 DSP pr ocessor . Figur e 3.46 shows how t he
AD7714 may be int er faced t o t he 68HC11 micr ocont r oller . The diagr am shows t he
minimum (t hr ee-wir e) int er face wit h CS on t he AD7714 har d-wir ed low. In t his
scheme, t he DRDY bit of t he AD7714 Communicat ions Regist er is monit or ed t o
det er mine when t he Dat a Regist er is updat ed. Ot her schemes ar e descr ibed in t he
AD7714 dat a sheet .
3
7
AD7714 TO 68HC11 MICROCONTROLLER INTERFACE
Figure 3.46
Int er facing t o t he ADSP-2103/2105 is also r elat ively st r aight for war d. The DRDY bit
of t he Communicat ions Regist er is again monit or ed t o det er mine when t he Dat a
Regist er in t he AD7714 is updat ed.
3
8
AD7714 TO ADSP-2103/2105 DSP INTERFACE
Figure 3.47
The AD771X sigma-delt a conver t er s ar e power ful t ools for building high accur acy
syst ems. Ever y one of t hem combines high r esolut ion, syst em calibr at ion, a
pr ogr ammable gain amplifier , and high impedance differ ent ial input s wit h gr eat
ease of design. Their adjust able digit al filt er s pr ovides flexibilit y in t he choice of
dat a r at es and r esolut ion and t heir ser ial int er face minimizes t heir pin count , so
t hat t hey fit in a 24-pin skinny DIP package, pr oviding a high degr ee of funct ionalit y
in a small space.
The AD7714 is especially suit able for low power applicat ions. Figur e 3.48 shows t he
t ot al supply cur r ent r equir ed as a funct ion of supply volt age for t wo clock
fr equencies: 2.4576MHz and 1MHz. These dat a ar e for an ext er nal clock wit h t he
AD7714 oper at ing in t he unbuffer ed mode. Figur e 3.48 illust r at es an impor t ant
point which is applicable t o a lar ge number of low power dat a conver t er s - t he t ot al
power dissipat ion is a funct ion of t he clock fr equency! Make sur e t o check t he dat a
sheet car efully for t his dependency when est imat ing t he t ot al power r equir ement .
The power dissipat ion of older , higher -power , bipolar dat a conver t er s was gener ally
much less sensit ive t o clock fr equency t han t he moder n low-power CMOS designs.
3
9
AD7714 TOTAL SUPPLY CURRENT
(EXTERNAL OSCILLATOR)
Figure 3.48
An ar ea wher e t he low power , single supply, t hr ee wir e int er face capabilit ies of t he
AD7714 is of benefit is in smar t t r ansmit t er s (Figur e 3.49). The ent ir e smar t
t r ansmit t er must oper at e fr om t he 4mA t o 20mA loop. Toler ances in t he loop mean
t hat t he amount of cur r ent available t o power t he ent ir e t r ansmit t er is as low as
3.5mA. The AD7714 consumes only 500µA, leaving 3mA available for t he r est of t he
t r ansmit t er . Not shown in Figur e 3.49 is t he isolat ed power sour ce r equir ed t o power
t he fr ont end cir cuit s, including t he AD7714.
SMART TRANSMITTER USING AD7714 OPERATES
ON 4mA TO 20mA LOOP CURRENT
Figure 3.49
4
0
REFERENCES
1. S .A.J antzi, M.Sn e lgr o v e & P.F.Fe r g uso n J r ., A 4t h - Or d e r B and pass
S i gm a- De l t a Mo du l ato r , I EEE J ou r n a l of Soli d St a t e Ci r cu i t s,
Vol. 38, No. 3, Mar ch 1993, pp.282-291.
2. Syst em Ap p li ca t i on s Gu i d e, Analog Devices, Inc., 1993, Sect ion 14.
3. Mi xed Si gn a l Desi gn Semi n a r , Analog Devices, Inc., 1991, Sect ion 6.
4. AD7710, AD7711, AD7712, AD7713, AD7714 Da t a Sh eet s,
Analog Devices.
5. Walt J ung, Getting the Most from IC Voltage References,
An a log Di a logu e, 28-1, 1994, pp. 13-21.
6. Walt J ung, Build an Ultra-Low-Noise Voltage Reference, Elect r on i c
Desi gn An a log Ap p li ca t i on s I ssu e, J une 24, 1993.
7. Li n ea r Desi gn Semi n a r , Analog Devices, Inc., 1995, Sect ion 8.
8. Syst em Ap p li ca t i on s Gu i d e, Analog Devices, Inc., 1993, Sect ion 6.
1
SECTION 4
HIGH SPEED
SAMPLING ADCs
ADC Dynamic Considerations
Selecting the Drive Amplifier Based on
ADC Dynamic Performance
Driving Flash Converters
Driving the AD9050 Single-Supply ADC
Driving ADCs with Switched Capacitor Inputs
Gain Setting and Level Shifting
External Reference Voltage Generation
ADC Input Protection and Clamping
Applications for Clamping Amplifiers
Noise Considerations in High Speed Sampling
ADC Applications
2
SECTI ON 4
HI GH SP EED SAMP LI NG ADCS
Wa l t Kest er
Moder n high speed sampling ADCs ar e designed t o give low dist or t ion and wide
dynamic r ange in signal pr ocessing syst ems. Realizat ion of specified per for mance
levels depends upon a number of fact or s ext er nal t o t he ADC it self, including pr oper
design of any necessar y suppor t cir cuit r y. The analog input dr ive cir cuit r y is
especially cr it ical, because it can degr ade t he inher ent ADC dynamic per for mance if
not designed pr oper ly.
Because of var ious pr ocess and design-r elat ed const r aint s, it is gener ally not
possible t o make t he input of a high speed sampling ADC t ot ally well-behaved, i.e.,
high impedance, low capacit ance, gr ound-r efer enced, fr ee fr om glit ches, imper vious
t o over dr ive, et c. Ther efor e, t he ADC dr ive amplifier must pr ovide excellent ac
per for mance while dr iving what may be a somewhat host ile load (depending upon
t he par t icular ADC select ed).
The t r end t owar d single-supply high speed designs adds addit ional const r aint s. The
input volt age r ange of high speed single-supply ADCs may not be gr ound r efer enced
(for valid design r easons), t her efor e level shift ing wit h single-supply op amps (which
may have limit ed common-mode input and out put r anges) is usually r equir ed,
unless t he applicat ion allows t he signal t o be ac coupled.
Alt hough t her e is no standard high speed ADC input st r uct ur e, t his sect ion
addr esses t he most common ones and pr ovides guidelines for pr oper ly designing t he
appr opr iat e input dr ive cir cuit r y.
Some sampling ADCs also r equir e ext er nal r efer ence volt ages. In ot her cases,
per for mance impr ovement s can be r ealized by using an ext er nal r efer ence in lieu of
an int er nal one. It is equally impor t ant t hat t hese r efer ence cir cuit s be designed
wit h ut most car e, since t hey t oo affect t he over all ADC per for mance.
3
HIGH SPEED, LOW VOLTAGE SAMPLING ADCs
Key Specifications for sampling ADCs:

Distortion
Noise
Distortion Plus Noise
Effective Number of Bits
Bandwidth (Full Power and Small Signal)
Sampling Rate
Modern Trends

Low Power: CMOS, BiMOS, or XFCB Processes
Low Voltage: 5V, +5V, +5V (Analog) / +3V (Digital)
Input Voltage Ranges not always Ground-Referenced
Analog Input Can Generate Transient Currents
Figure 4.1
ADC DYNAMI C CONSI DERATI ONS
In or der t o make int elligent decisions r egar ding t he input dr ive cir cuit r y, it is
necessar y t o under st and fir st exact ly how t he dynamic per for mance of t he ADC is
char act er ized. Moder n signal pr ocessing applicat ions r equir e ADCs wit h wide
dynamic r ange, high bandwidt h, low dist or t ion, and low noise. As well as having
t r adit ional dc specificat ions (offset er r or , gain er r or , differ ent ial linear it y er r or , and
int egr al linear it y er r or ), sampling ADCs (ADCs wit h an int er nal sample-and-hold
funct ion) ar e gener ally specified in t er ms of Signal-t o-Noise Rat io (SNR, or S/N),
Signal-t o-Noise-Plus Dist or t ion Rat io [S/(N+D), or SINAD], Effect ive Number of Bit s
(ENOB), Har monic Dist or t ion, Tot al Har monic Dist or t ion (THD), Tot al Har monic
Dist or t ion Plus Noise (THD+N), Int er modulat ion Dist or t ion (IMD), and Spur ious
Fr ee Dynamic Range (SFDR). Sampling ADC dat a sheet s may pr ovide some, but not
all of t hese ac specificat ions. The ac specificat ions ar e usually t est ed by applying
spect r ally pur e sinewaves t o t he ADC and analyzing it s out put in t he fr equency
domain wit h a Fast Four ier Tr ansfor m (FFT). The pr ocess is similar t o using an
analog spect r um analyzer t o measur e t he ac per for mance of an amplifier . Because of
t he quant izat ion pr ocess, however , an ADC pr oduces some er r or s not found in
amplifier s.
4
ADC DYNAMIC PERFORMANCE SPECIFICATIONS
Distortion Specifications: (Narrowband)

Harmonic Distortion
Total Harmonic Distortion (THD)
Spurious Free Dynamic Range (SFDR)
Intermodulation Distortion (IMD), Two-Tone Input
Noise Specifications: dc to f
s
/ 2

Signal-to-Noise Ratio without Harmonics (often called
SNR, or S/N)
Noise Plus Distortion Specifications: dc to f
s
/ 2

Signal-to-Noise and Distortion (S/N+D, SINAD), but often
referred to as SNR (check definition carefully when
evaluating ADCs), often converted to Effective Bits
(ENOB)
Total Harmonic Distortion Plus Noise (THD + N)
Broadband Noise can be reduced by filtering or averaging
Figure 4.2
An ideal N-bit ADC, sampling at a r at e f
s
, pr oduces quant izat ion noise having an
r ms value of q/(sqr t 12) measur ed in t he Nyquist bandwidt h dc t o f
s
/2, wher e q is t he
weight of t he Least Significant Bit (LSB). The value of q is obt ained by dividing t he
full scale input r ange of t he ADC by t he number of quant izat ion levels, 2^N. For
example, an ideal 10-bit ADC wit h a 2.048V peak-t o-peak input r ange has 2^10 =
1024 quant izat ion levels, an LSB of 2mV, and an r ms quant izat ion noise of
2mV/(sqr t 12) = 577µV r ms. The der ivat ion of t he t heor et ical value of quant izat ion
noise, q/(sqr t 12), makes t he assumpt ion t hat t he quant izat ion noise is not
cor r elat ed in any fashion t o t he input signal, and may t her efor e be t r eat ed as
Gaussian noise. This is nor mally t r ue, but in cer t ain cases wher e t he input sinewave
fr equency happens t o be an exact submult iple of t he sampling r at e, t he quant izat ion
noise may t end t o be concent r at ed at t he har monics of t he input signal, even t hough
t he r ms value is st ill appr oximat ely q/(sqr t 12).
Anot her way t o expr ess quant izat ion noise is t o conver t it int o a Signal-t o-Noise
r at io by dividing t he r ms value of t he input sinewave by t he r ms value of t he
quant izat ion noise. Nor mally, t his is measur ed wit h a full scale input sinewave, and
t he expr ession r elat ing t he t wo is given by t he well-known equat ion,
SNR N dB = + 602 176 . . .
An act ual ADC will pr oduce noise in excess of t he t heor et ical quant izat ion noise, as
well as dist or t ion pr oduct s caused by a non-linear t r ansfer funct ion. An FFT is used
t o calculat e t he r ms value of all t he dist or t ion and noise pr oduct s, and t he act ual
5
signal-t o-noise-plus-dist or t ion, S/(N+D), is comput ed. The above equat ion is solved
for N, yielding t he well-known expr ession for Effect ive Number of Bit s, ENOB:
ENOB
S N D
ACTUAL
dB
=
+ − / ( ) .
.
176
602
.
For example, if a 10-bit ADC has an act ual measur ed S/(N+D) of 56dB (t heor et ical
would be 61.96dB), t hen it will have 9 effect ive bit s, i.e., t he non-ideal 10-bit ADC
yields t he same per for mance as an ideal 9-bit one.
EFFECTIVE NUMBER OF BITS (ENOB)
INDICATES OVERALL DYNAMIC PERFORMANCE OF ADCs
S/(N+D) = 6.02N + 1.76dB (Theoretical)
ADC ACHIEVES S/(N+D) = XdB (Actual)
ENOB = (XdB - 1.76dB) / (6.02dB)
ENOB Includes Effects of All Noise and Distortion in the
bandwidth DC to f
s
/2
Figure 4.3
Even well-designed sampling ADCs have non-linear it ies which cont r ibut e t o non-
ideal low fr equency per for mance, and addit ionally, per for mance degr ades as t he
input fr equency is incr eased. A useful way t o evaluat e t he ac per for mance of ADCs is
t o plot Signal-t o-Noise Plus Dist or t ion, S/(N+D), (or conver t it t o ENOB) as a
funct ion of input fr equency. This measur ement is somewhat all-inclusive and
includes t he effect s of bot h noise and dist or t ion pr oduct s.
In some inst ances, SNR may be specified bot h wit h and wit hout t he dist or t ion
pr oduct s, and in ot her cases, dist or t ion may be specified separ at ely, eit her as
individual har monic component s, or as t ot al har monic dist or t ion (THD). Spur ious
Fr ee Dynamic Range (SFDR) is simply anot her way of descr ibing dist or t ion pr oduct s
and is t he r at io of t he signal level t o t he wor st fr equency spur , under a given set of
condit ions. Int er modulat ion Dist or t ion (IMD) is measur ed by applying t wo t ones (F1
and F2) t o t he ADC and det er mining t he r at io of t he power in one of t he t ones t o t he
var ious IMD as shown in Figur e 4.4. Unless ot her wise specified, t he t hir d-or der
pr oduct s which occur at t he fr equencies 2F1 – F2 and 2F2 – F1 ar e t he ones used in
t he measur ement because t hey lie close t o t he or iginal t ones and ar e difficult t o
filt er .
6
INTERMODULATION DISTORTION (IMD)
Figure 4.4
If we plot t he gain of an amplifier wit h a small signal of a few millivolt s or t ens of
millivolt s, we find t hat as we incr ease t he input fr equency, t her e is a fr equency at
which t he gain has dr opped by 3 dB. This fr equency is t he upper limit of t he small
signal bandwidth of t he amplifier and is set by t he int er nal pole(s) in t he amplifier
r esponse. If we dr ive t he same amplifier wit h a lar ge signal so t hat t he out put st age
swings wit h it s full r at ed peak-t o-peak out put volt age, we may find t hat t he upper
3dB point is at a lower fr equency, being limit ed by t he slew r at e of t he amplifier
out put st age. This high-level 3dB point defines t he large signal bandwidth of an
amplifier . When defining t he lar ge signal bandwidt h of an amplifier , a number of
var iables must be consider ed, including t he power supply, t he out put amplit ude (if
slew r at e is t he only limit ing fact or , it is obvious t hat if t he lar ge signal amplit ude is
halved, t he lar ge signal bandwidt h is doubled), and t he load. Thus lar ge signal
bandwidt h is a r at her uncer t ain par amet er in an amplifier , since it depends on so
many uncont r olled var iables - in cases wher e t he lar ge signal bandwidt h is less t han
t he small signal bandwidt h, it is bet t er t o define t he out put slew r at e and calculat e
t he maximum out put swing at any par t icular fr equency.
In an ADC, however , t he maximum signal swing is always full scale, and t he load
seen by t he signal is defined. It is t her efor e quit e r easonable t o define t he lar ge
signal bandwidt h (or full-power bandwidt h) of an ADC and r epor t it on t he dat a
sheet . In some cases, t he small signal bandwidt h may also be given.
7
ADC LARGE SIGNAL (OR FULL POWER) BANDWIDTH
With Small Signal, the Bandwidth of a Circuit is limited by its
Overall Frequency Response.
At High Levels of Signal the Slew Rate of Some Stage May
Control the Upper Frequency Limit.
In Amplifiers There are so many Variables that Large Signal
Bandwidth needs to be Redefined in every Individual Case, and
Slew Rate is a more Useful Parameter for a Data Sheet.
In ADCs the Maximum Signal Swing is the ADC’s Full Scale
Span, and is therefore Defined, so Full Power Bandwidth (FPBW)
may Appear on the Data Sheet.
HOWEVER the FPBW Specification Says Nothing About
Distortion Levels. Effective Number of Bits (ENOB) is Much More
Useful in Practical Applications.
Figure 4.5
However , t he lar ge signal bandwidt h t ells us t he fr equency at which t he amplit ude
r esponse of t he ADC dr ops by 3dB - it t ells us not hing at all about t he r elat ionship
bet ween dist or t ion and fr equency. If we st udy t he behavior of an ADC as it s input
fr equency is incr eased, we discover t hat , in gener al, noise and dist or t ion incr ease
wit h incr easing fr equency. This r educes t he r esolut ion t hat we can obt ain fr om t he
ADC.
If we dr aw a gr aph of t he r at io of signal-t o-noise plus dist or t ion (S/N+D) against it s
input fr equency, we find a much mor e discour aging gr aph t han t hat of it s fr equency
r esponse. The r at io of S/N+D can be expr essed in dB or as effect ive number of bit s
(ENOB) as discussed above. As we have seen, t he SNR of a per fect N-bit ADC (wit h
a full scale sinewave input ) is (6.02N + 1.76)dB. A gr aph of ENOB against t he
var iat ions of input amplit ude can be depr essing when we see just how lit t le of t he dc
r esolut ion of t he ADC can act ually be used, but can somet imes show int er est ing
feat ur es: t he ADC in Figur e 4.6, for inst ance, has a lar ger ENOB for signals at 10%
of FS at 1MHz t han for FS signals of t he same fr equency. A simple fr equency
r esponse cur ve cannot have plot s cr ossing in t his way.
8
ADC GAIN AND ENOB VERSUS FREQUENCY
SHOWS INPORTANCE OF ENOB SPECIFICATION
Figure 4.6
The causes of t he loss of ENOB at higher input fr equencies ar e var ied. The linear it y
of t he ADC t r ansfer funct ion degr ades as t he input fr equency incr eases, t her eby
causing higher levels of dist or t ion. Anot her r eason t hat t he SNR of an ADC
decr eases wit h input fr equency may be deduced fr om Figur e 4.7, which shows t he
effect s of phase jit t er on t he sampling clock of an ADC. The phase jit t er causes a
volt age er r or which is a funct ion of slew r at e and r esult s in an over all degr adat ion in
SNR as shown in Figur e 4.8. This is quit e ser ious, especially at higher input /out put
fr equencies. Ther efor e, ext r eme car e must be t aken t o minimize phase noise in t he
sampling/r econst r uct ion clock of any sampled dat a syst em. This car e must ext end t o
all aspect s of t he clock signal: t he oscillat or it self ( for example, a 555 t imer is
absolut ely inadequat e, but even a quar t z cr yst al oscillat or can give pr oblems if it
uses an act ive device which shar es a chip wit h noisy logic); t he t r ansmission pat h
(t hese clocks ar e ver y vulner able t o int er fer ence of all sor t s), and phase noise
int r oduced in t he ADC or DAC. A ver y common sour ce of phase noise in conver t er
cir cuit r y is aper t ur e jit t er in t he int egr al sample-and-hold (SHA) cir cuit r y.
9
EFFECTS OF APERATURE AND SAMPLING CLOCK JITTER
Figure 4.7
SNR DUE TO SAMPLING CLOCK JITTER (t
j
)
Figure 4.8
A decade or so ago, sampling ADCs wer e built up fr om a separ at e SHA and ADC.
Int er face design was difficult , and a key par amet er was aper t ur e jit t er in t he SHA.
Today, most sampled dat a syst ems use sampling ADCs which cont ain an int egr al
SHA. The aper t ur e jit t er of t he SHA may not be specified as such, but t his is not a
cause of concer n if t he SNR or ENOB is clear ly specified, since a guar ant ee of a
specific SNR is an implicit guar ant ee of an adequat e aper t ur e jit t er specificat ion.
However , t he use of an addit ional high-per for mance SHA will somet imes impr ove
1
0
t he high-fr equency ENOB of a sampling ADC, and may be mor e cost -effect ive t han
r eplacing t he ADC wit h a mor e expensive one.
It should be not ed t hat t her e is also a fixed component which makes up t he ADC
aper t ur e t ime. This component , usually called effective aperture delay time, does not
pr oduce an er r or . It simply r esult s in a t ime offset bet ween t he t ime t he ADC is
asked t o sample and when t he act ual sample t akes place (see Figur e 4.9). The
var iat ion or t oler ance placed on t his par amet er fr om par t t o par t is impor t ant in
simult aneous sampling applicat ions or ot her applicat ions such as I and Q
demodulat ion wher e sever al ADCs ar e r equir ed t o t r ack each ot her .
EFFECTIVE APERATURE DELAY TIME
Figure 4.9
The dist or t ion pr oduced by an ADC or DAC cannot be analyzed in t er ms of second
and t hir d-or der int er cept s, as in t he case of an amplifier . This is because t her e ar e
t wo component s of dist or t ion in a high per for mance dat a conver t er . One component
is due t o t he non-linear it y associat ed wit h t he analog cir cuit s wit hin t he conver t er .
This non-linear it y has t he familiar "bow" or "s"-shaped cur ve shown in Figur e 4.10.
(It may be polynomial or logar it hmic in for m). The dist or t ion associat ed wit h t his
t ype of non-linear it y is somet imes r efer r ed t o as soft dist or t ion and pr oduces low-
or der dist or t ion pr oduct s. This component of dist or t ion behaves in t he t r adit ional
manner , and is a funct ion of signal level. In a pr act ical dat a conver t er , however , t he
soft dist or t ion is usually much less t han t he ot her component of dist or t ion, which is
due t o t he differ ent ial nonlinear it y of t he t r ansfer funct ion. The conver t er t r ansfer
funct ion is mor e likely t o have discr et e point s of discont inuit y acr oss t he signal
r ange as shown in Figur e 4.10.
1
1
TRANSFER CHARACTERISTICS FOR “SOFT”
AND “HARD” DISTORTION IN ADCs
Figure 4.10
The act ual locat ion of t he point s of discont inuit y depends on t he par t icular dat a
conver t er ar chit ect ur e, but never t heless, such discont inuit ies occur in pr act ically all
conver t er s. Non-linear it y of t his t ype pr oduces high-or der dist or t ion pr oduct s which
ar e r elat ively unpr edict able wit h r espect t o input signal level, and t her efor e such
specificat ions as third order intercept point may be less r elevant t o conver t er s t han
t o amplifier s and mixer s. For lower -amplit ude signals, t his const ant level hard
dist or t ion causes t he SFDR of t he conver t er t o decrease as input amplit ude
decr eases. The soft dist or t ion in a well-designed conver t er is only significant for high
fr equency lar ge-amplit ude signals wher e it may r ise above t he har d dist or t ion floor .
In a pr act ical syst em design, t he ADC is usually select ed based pr imar ily on t he
r equir ed dynamic per for mance at t he r equir ed sampling r at e and input signal
fr equency, using one or mor e of t he above specificat ions. DC per for mance may be
impor t ant also, but is gener ally of less concer n in signal pr ocessing applicat ions.
Once t he ADC is select ed, t he appr opr iat e int er face cir cuit r y must be designed t o
pr eser ve t hese levels of ac and dc per for mance.
SELECTI NG THE DRI VE AMP LI FI ER BASED ON ADC
DYNAMI C P ERFORMANCE
The ADC dr ive amplifier per for ms sever al impor t ant funct ions in a syst em. Fir st , it
isolat es t he signal sour ce and pr ovides a low-impedance dr ive t o t he ADC input . A
low-impedance dc and ac dr ive sour ce is impor t ant because t he input impedance of
t he ADC may be signal-dependent , and t he input may also gener at e t r ansient load
cur r ent s dur ing t he act ual conver sion pr ocess. A low sour ce impedance at high
fr equencies minimizes t he er r or s pr oduced by t hese effect s. Second, t he dr ive
amplifier pr ovides t he necessar y gain and level shift ing t o mat ch t he signal t o t he
ADC input volt age r ange.
1
2
FUNCTIONS OF THE ADC DRIVE AMPLIFIER
Buffer the analog signal from the ADC input:

ADC input may not be a constant high impedance
ADC input may generate transient loads
Provide other functions:

Gain
Level Shifting
If the ADC input is constant high impedance with no transient
loading, do not use a buffer amplifier unless required for gain or
level shifting!!
Figure 4.11
The S/(N+D) plot of t he ADC should gener ally be used as t he fir st select ion cr it er ion
for t he dr ive amplifier . If t he Tot al Har monic Dist or t ion Plus Noise (THD+N) of t he
dr ive amplifier is always 6 t o 10dB bet t er t han t he S/(N+D) of t he ADC over t he
fr equency r ange of int er est , t hen t he over all degr adat ion in S/(N+D) caused by t he
amplifier will be limit ed t o bet ween appr oximat ely 0.5dB and 1db, r espect ively. This
will be illust r at ed using t wo st at e of t he ar t component s: t he AD9022 12 bit ,
20MSPS ADC and t he AD9631 op amp. A block diagr am of t he AD9022 is shown in
Figur e 4.12, and key specificat ions in Figur e 4.13. AD9631/AD9632 key
specificat ions ar e given in Figur e 4.14.
The AD9022 employs a t hr ee-pass subr anging ar chit ect ur e and digit al er r or
cor r ect ion. The analog input is applied t o a 300Ω at t enuat or and passed t o t he
sampling br idge of t he fir st int er nal t r ack-and-hold amplifier (T/H). The held value
of t he fir st T/H is applied t o a 5-bit flash conver t er and a second T/H. The 5-bit flash
conver t er r esolves t he most significant bit s (MSBs) of t he held analog volt age. These
5 bit s ar e r econst r uct ed via a 5-bit DAC and subt r act ed fr om t he or iginal T/H out put
signal t o for m a r esidue signal. A second T/H holds t he amplified r esidue signal
while it is encoded wit h a second 5-bit flash ADC. Again, t he 5-bit s ar e r econst r uct ed
and subt r act ed fr om t he second T/H out put t o for m a r esidue signal. This r esidue is
amplified and encoded wit h a 4-bit flash ADC t o pr ovide t he 3 least significant bit s
(LSBs) of t he digit al out put and one bit of er r or cor r ect ion. The digit al er r or
cor r ect ion logic combines t he dat a fr om t he t hr ee flash conver t er s and pr esent s t he
r esult as a 12-bit par allel digit al wor d. The out put st age is TTL (AD9022), or ECL
(AD9023). Out put dat a can be st r obed on t he r ising edge of t he ENCODE command.
1
3
AD9022 12-BIT, 20MSPS SAMPLING ADC
Figure 4.12
AD9022 ADC KEY SPECIFICATIONS
12-bit, 20MSPS Sampling ADC
TTL Outputs (AD9023 has ECL outputs)
On-Chip reference and SHA
High Spurious Free Dynamic Range (SFDR):

76dB @ 1MHz Input f
s
= 20MSPS
74dB @ 9.6MHz Input f
s
= 20MSPS
Analog Input Bandwidth: 110MHz
Well-Behaved analog input with no transients
Input Range: 1.024V, Input Impedance: 300 , 5pF
Dual Supplies (+5, -5.2V), 1.4W Power Dissipation
Figure 4.13
1
4
AD9632 OP AMP KEY SPECIFICATIONS
Current-Feedback performance with voltage-feedback amps
Small Signal Bandwidth: 320MHz (AD9631, G = +1)
250MHz (AD9632, G = +2)
Low Distortion: -113dBc @ 1MHz
- 95dBc @ 5Mhz
- 72dBc @ 20MHz
Slew Rate: 1300V / s
Settling Time: 16ns to 0.01%, 2V step
Low Noise: Voltage: 7nV/ Hz, Current: 2pA/ Hz
3V to 5V Supply Operation, 17mA Supply Current
Figure 4.14
Figur e 4.15 shows t he THD+N of t he AD9631 dr ive amplifier super imposed on t he
S/(N+D) plot for t he AD9022 ADC (12-bit s, 20MSPS). Not ice t hat t he amplifier
THD+ N is at least 10dB bet t er t han t he ADC S/(N+D) for input fr equencies up t o
about 10MHz (t he Nyquist fr equency). In per for ming t his compar ison, it is
impor t ant t hat t he dat a for t he op amp be obt ained under t he final oper at ing
condit ions encount er ed in t he act ual cir cuit , i.e., gain, signal level, power supply
volt age, et c.
AD9022 ADC S/(N+D) AND AD9631 OP AMP THD+N
PLOTTED AS A FUNCTION OF INPUT FREQUENCY
Figure 4.15
1
5
While S/(N+D) and THD+N ar e useful ac per for mance indicat or s, t her e ar e a
number of applicat ions wher e low dist or t ion is mor e impor t ant t han low noise. In
spect r al analysis using FFTs, or ot her applicat ions wher e aver aging t echniques can
be used t o r educe t he effect s of noise, t he amplifier THD and t he ADC dist or t ion
(gener ally SFDR) should be used as t he select ion cr it er ia. These char act er ist ics
should be plot t ed on t he same scale, and t he dr ive amplifier THD should be at least
6 t o 10dB bet t er t han t he ADC SFDR over t he fr equency r ange of int er est . Such a
plot for t he AD9631 op amp and t he AD9022 ADC is shown in Figur e 4.16.
AD9022 ADC SFDR AND AD9631 OP AMP THD
PLOTTED AS A FUNCTION OF INPUT FREQUENCY
Figure 4.16
The above ac select ion cr it er ion wor ks well if t he ADC input is r elat ively benign, but
may give over ly opt imist ic r esult s if t he input impedance is signal dependent , or t he
input pr oduces t r ansient cur r ent s. The exist ence of eit her of t hese t wo condit ions
r equir es fur t her invest igat ion. The implicat ions of signal-dependent input
impedance will be demonst r at ed using a flash conver t er . Dealing wit h ADC input
t r ansient cur r ent s will be illust r at ed by examining a fast single-supply sampling
ADC wit h a CMOS swit ched capacit or input st age.
DRI VI NG FLASH CONVERTERS
A t ypical flash conver t er (Figur e 4.17) gener ally exhibit s a signal-dependent input
impedance (oft en r efer r ed t o as non-linear input impedance), wher e t he effect ive
input capacit ance is a funct ion of signal level. The signal-dependent capacit ance can
be modeled as t he junct ion capacit ance of a diode, C
j
. At t he negat ive end of t he
input r ange, all t he par allel compar at or s in t he flash conver t er ar e "off", and t he
capacit ance is low (modeled by a r ever se-biased diode). At t he posit ive end of t he
input r ange, all compar at or s ar e "on", t her eby incr easing t he effect ive input
capacit ance (modeled by a zer o-biased diode). For t he example in t he diagr am, t he
Spice model (Figur e 4.18) for t he flash conver t er input under consider at ion is a
1
6
7.5nH induct or (simulat ing package pin and wir ebond induct ance), a 10pF fixed
capacit or , and a diode having a 6pF zer o-bias junct ion capacit ance (C
J O
). The t ot al
input capacit ance changes fr om 16pF (0V input ) t o 12.5pF (–2V input ) as shown in
Figur e 4.18. The 50ohm ser ies r esist or , R
s
, is r equir ed t o isolat e t he wideband op
amp out put fr om t he flash conver t er input capacit ance. Select ing t he cor r ect value
for t he ser ies r esist ance is cr it ical. If it is t oo low, t he wideband, low-dist or t ion op
amp may be unst able because of t he flash conver t er capacit ive load. If it is t oo lar ge,
t he dist or t ion due t o t he non-linear input impedance may become significant , and
bandwidt h will be r educed because of t he lowpass filt er for med by t he ser ies r esist or
and t he input capacit ance. Dat a sheet s for wideband low dist or t ion amplifier s
gener ally have cur ves showing t he opt imum value of ser ies r esist ance as a funct ion
of t he load capacit ance. Typical r ecommended r esist or values r ange fr om about
10ohms t o 100ohms, depending on t he amplifier and t he load capacit ance. In t he
model, a value of 50ohm was chosen. Figur e 4.19 shows t he simulat ed THD
pr oduced by t he equivalent cir cuit (assuming an ideal op amp, of cour se).
TYPICAL FLASH ADC BLOCK DIAGRAM
Figure 4.17
1
7
FLASH ADC INPUT MODEL SHOWS
CAPACITANCE IS A FUNCTION OF INPUT SIGNAL
Figure 4.18
ADC TOTAL HARMONIC DISTORTION VERSUS
INPUT FREQUENCY AS PREDICTED BY MODEL
Figure 4.19
1
8
DRI VI NG THE AD9050 SI NGLE-SUP P LY 10-BI T, 40MSP S
ADC
The AD9050 is a 10-bit , 40MSPS single supply ADC designed for wide dynamic
r ange applicat ions such as ult r asound, inst r ument at ion, digit al communicat ions,
and pr ofessional video. A block diagr am of t he AD9050 (Figur e 4.20) illust r at es t he
t wo-st ep subr anging ar chit ect ur e, and key specificat ions ar e summar ized in Figur e
4.21.
AD9050 10-BIT, 40MSPS SINGLE SUPPLY ADC
Figure 4.20
1
9
AD9050 10-BIT, 40MSPS ADC KEY SPECIFICATIONS
10-Bits, 40MSPS, Single +5V Supply
Selectable Digital Supply: +5V, or +3V
Low Power: 300mW on BiCMOS Process
On-Chip SHA and +2.5V reference
56dB S/(N+D), 9 Effective Bits, with 10.3MHz Input Signal
No input transients, Input Impedance 5k , 5pF
Input Range +3.3V 0.5V Single-Ended or Differential
28-pin SOIC / SSOP Packages
Ideal for Digital Beamforming Ultrasound Systems
Figure 4.21
The analog input cir cuit of t he AD9050 (see Figur e 4.22) is differ ent ial, but can be
dr iven eit her single-endedly or differ ent ially wit h equal per for mance. The input
signal r ange of t he AD9050 is ±0.5V cent er ed ar ound a common-mode volt age of
+3.3V.
AD9050 SIMPLIFIED INPUT CIRCUIT
Figure 4.22
The input cir cuit of t he AD9050 is a r elat ively benign and const ant 5kΩ in par allel
wit h appr oximat ely 5pF. Because of it s well-behaved input , t he AD9050 can be
dr iven dir ect ly fr om 50, 75, or 100ohm sour ces wit hout t he need for a low-dist or t ion
buffer amplifier . In ult r asound applicat ions, it is nor mal t o ac couple t he signal
(gener ally bet ween 1MHz and 15MHz) int o t he AD9050 differ ent ial input s using a
wideband t r ansfor mer as shown in Figur e 4.23 (A). Signal-t o-noise plus dist or t ion
(S/N+D) values of 57dB (9.2 ENOB) ar e t ypical for a 10MHz input signal. If t he
2
0
input signal comes dir ect ly fr om a 50, 75, or 100ohm single-ended sour ce, capacit ive
coupling as shown in Figur e 4.23 (B) can be used.
AC COUPLING INTO THE INPUT OF THE AD9050 ADC
Figure 4.23
DRI VI NG ADCS WI TH SWI TCHED CAP ACI TOR I NP UTS
Many ADCs, including fast sampling ones, have swit ched capacit or input cir cuit s.
Not only can t he effect ive input impedance be a funct ion of t he sampling r at e, but
t he swit ches (usually CMOS) may inject char ge on t he ADC's analog input . For
inst ance, t he int er nal t r ack-and-hold amplifier (THA) may gener at e a cur r ent spike
on t he analog input when it swit ches fr om t he track mode t o t he hold mode, and vice
ver sa. Ot her spikes may be gener at ed dur ing t he act ual conver sion. These fast
cur r ent spikes appear on t he out put of t he ext er nal ADC dr ive amplifier , pr oducing
cor r esponding volt age spikes (because of t he closed-loop high fr equency op amp
out put impedance), and conver sion er r or s will r esult if t he amplifier set t ling t ime t o
t hem is not adequat e.
The AD876 is a 10-bit , 20MSPS, low power (150mW), CMOS ADC wit h a swit ched
capacit or t r ack-and-hold input cir cuit . The over all block diagr am of t he ADC is
shown in Figur e 4.24, and key specificat ions ar e given in Figur e 4.25.
2
1
AD876 10-BIT, 20MSPS LOW POWER
SINGLE SUPPLY ADC SIMPLIFIED BLOCK DIAGRAM
Figure 4.24
AD876 LOW POWER SINGLE SUPPLY ADC
KEY SPECIFICATIONS
10-Bits, 20MSPS, Single-Supply
Low Power CMOS Design: 140mW
Standby Mode Power: <50mW
S/(N+D): 56dB @ 1MHz
55dB @ 3.58MHz
51dB @ 10MHz
Input Bandwidth: 250MHz
Input Range: 2V peak-to-peak
Differential Gain: 1%, Differential Phase: 0.5
Figure 4.25
Oper at ion of t he AD876 swit ched capacit or input cir cuit is illust r at ed in Figur e 4.26,
and t he associat ed swit ching wavefor ms in Figur e 4.27. The CMOS swit ches S1, S2,
and S3 cont r ol t he act ion of t he int er nal sample and hold. They ar e shown in t he
t r ack mode. Not ice t hat in t he t r ack mode, t he CMOS swit ch, S2, connect s t he input ,
V
IN
, t o t he 3pF hold capacit or which must be char ged by t he dr ive amplifier .
When t he cir cuit goes int o t he hold mode t he following sequent ial swit ching occur s:
S1 opens, S2 opens, and S3 closes (t he ent ir e sequence occur s in a few nanoseconds).
The held volt age acr oss C
H
is t hus t r ansfer r ed t o t he out put of t he int er nal op amp,
A1. Opening CMOS swit ch S2 inject s a small amount of char ge int o t he ADC input
(equivalent t o appr oximat ely 1mA of cur r ent , having a dur at ion of a few
nanoseconds). This cur r ent pr oduces a t r ansient volt age acr oss t he op amp closed
loop out put impedance (appr oximat ely 10ohms at 10MHz, and 100ohms at 100MHz)
2
2
in ser ies wit h t he 30ohm isolat ion r esist or , R
s
. The r esult ing volt age spike is
appr oximat ely 100mV, cor r esponding t o t he pr oduct of t he 1mA t r ansient and t he
t ot al ac sour ce impedance of 100ohms (t he op amp Z
o
of about 70ohms plus t he
30ohm isolat ion r esist or ). Dur ing t he hold mode, t he AD876 per for ms t he
conver sion, while t he input signal may cont inue t o change. The ADC input signal in
Figur e 4.27 goes fr om negat ive full scale (+1.7V) t o posit ive full scale (+3.7V) dur ing
t he fir st hold int er val shown in t he t iming diagr am. This r epr esent s a wor st case
condit ion, and input slew r at es (and t he cor r esponding char ging t r ansient ) ar e quit e
likely t o be less in a pr act ical applicat ion.
At t he end of t he conver sion, t he swit ches r et ur n t o t heir t r ack mode st at e in t he
following sequence: S3 opens, S1 closes, and S2 closes (t he ent ir e sequence occur s in
a few nanoseconds). When S2 closes, a small amount of char ge is inject ed int o t he op
amp out put , but t he dominant cur r ent spike (5mA) is t he inst ant aneous cur r ent
r equir ed t o char ge t he hold capacit or , C
H
, t o t he new signal value. The ext er nal
dr ive amplifier must t her efor e char ge C
H
t o t he new signal value and set t le t o t he
r equir ed accur acy (1/2 LSB, or 1mV) befor e t he init iat ion of t he next conver sion (t he
set t ling t ime must be less t han 25ns if t he ADC is sampling at it s maximum r at e of
20MSPS as shown). The char ging cur r ent dominat es and is shown on t he ADC input
wavefor m as a negat ive-going 500mV spike. The addit ion of an ext er nal capacit or ,
C
P
= 15pF, in par allel wit h t he ADC input helps absor b some of t he t r ansient char ge
and is small enough so t hat bandwidt h is not compr omised. The opt imum value of
15pF was det er mined empir ically.
AD876 ADC SWITCHED CAPACITOR INPUT CIRCUIT
Figure 4.26
2
3
AD876 ANALOG INPUT TRANSIENTS
SHOWN FOR SAMPLING FREQUENCY OF 20MSPS
-
Figure 4.27
An empir ical way t o det er mine if t he op amp t r ansient load cur r ent set t ling t ime is
adequat e is t o connect it t o t he ADC and obser ve t he ADC input dir ect ly wit h a fast
digit al oscilloscope which is not sensit ive t o over dr ive. If t his is not possible, a good
r ule of t humb is t o est imat e t he closed loop bandwidt h, f
cl
, r equir ed of t he op amp t o
meet t he r equir ed set t ling t ime. This is done as follows. The amplit ude of t he volt age
spike, V
er r or
(t ), at t he ADC input is est imat ed by mult iplying t he input st ep
cur r ent , Delt a I, by t he t ot al dr iving impedance, Z
out
, (composed of t he closed loop
out put impedance plus t he ser ies isolat ion r esist or , R
s
). The out put impedance of a
t ypical high speed op amp (bandwidt h of 50MHz or gr eat er ) is gener ally bet ween
50ohms and 100ohms at t he fr equencies cont ained in t he t r ansient . If we assume a
single-pole syst em wit h a bandwidt h of f
cl
, t he t r ansient exhibit s an exponent ial
decay descr ibed by t he following equat ion:
V
error
t I Z
out
e
t
( ) = ⋅


τ
.
Solving t he equat ion for t :
t
V
error
t
I Z
out
= −






 τ ln
( )

.
Subst it ut ing τ
π
=
1
2 f
cl
,and solving for f
cl
:
f
cl
t
V
error
t
I Z
out
= −







1

ln
( )

2
4
Now, let t = T
s
/2 = 1/2f
s
(wher e T
s
= Sampling Per iod = 1/f
s
),
and V
er r or
(t ) = q/2, q = weight of LSB:
f
cl
f
s
q
I Z
out
= −







π
ln
/ 2

,
t he minimum r equir ed op amp closed loop bandwidt h.
This equat ion det er mines t he minimum closed-loop op amp bandwidt h r equir ed
based on t he sampling r at e, LSB weight , and t he input volt age st ep (Delt a I)·Z
out
.
In t he example pr eviously shown for t he AD876 ADC, we can use t he above equat ion
t o est imat e t he r equir ed op amp closed loop bandwidt h by let t ing f
s
= 20MSPS, q =
2mV, and (Delt a I)·Z
out
= 500mV. Solving yields f
cl
= 39.6MHz. The AD812 closed-
loop bandwidt h is appr oximat ely 60MHz in t he configur at ion shown in Figur e 4.28,
which is mor e t han sufficient t o pr ovide adequat e set t ling t ime t o t he t r ansient . Key
specificat ions for t he AD812 single-supply op amp ar e given in Figur e 4.29.
SIMPLIFIED MODEL PREDICTS
INPUT TRANSIENT SETTLING TIME OF ADC DRIVE AMP
2
5
Figure 4.28
KEY SPECIFICATIONS OF AD812 DUAL OP AMP
Dual, Current Feedback, Low Current (11mA)
Specified for 15, 5, +5, and +3V
Input and Output CM Voltage Range (+1V to +4V), V
s
= +5V
Optimized for Video Applications:

Gain Flatness: 0.1dB to 40MHz
Differential Gain: 0.2%, Differential Phase: 0.02
145MHz Bandwidth (3dB)
1600V / s Slew Rate
50mA Output Current
Figure 4.29
It is gener ally t r ue t hat if you select t he op amp fir st based on t he r equir ed
dist or t ion per for mance at t he maximum input fr equency of int er est , t hen it s
bandwidt h will be much gr eat er t han t he ADC sampling r at e, and t he op amp will
have adequat e t r ansient load cur r ent set t ling t ime.
The dr ive amplifier select ion pr ocess can be summar ized as follows. Fir st , choose an
op amp which pr ovides t he necessar y bandwidt h, dist or t ion, and out put volt age
compat ible wit h t he ADC. A good ADC dat a sheet will r ecommend one or t wo op
amps, gener ally select ed t o opt imize ac per for mance at t he higher fr equencies.
However , ot her choices may be bet t er because of syst em consider at ions. For
example, many t r adeoffs ar e possible bet ween ac and dc per for mance. If ext r emely
low dist or t ion at low fr equencies is r equir ed (at t he expense of high fr equency
per for mance), ot her low dist or t ion amplifier s may pr ovide opt imum syst em
per for mance. Ot her fact or s such a single-supply ver sus dual-supply may influence
t he decision.
The next st ep is t o examine t he ADC dat a sheet car efully t o det er mine if t he input
st r uct ur e pr esent s any t r ansient loads t o t he op amp. If t r ansient loads ar e pr esent ,
t he op amp set t ling t ime is impor t ant , and t he ADC dat a sheet should be consult ed
for specific r equir ement s. If t he dat a sheet does not specify t he op amp set t ling t ime,
a conser vat ive appr oach is t o choose an op amp wit h a set t ling t ime (t o t he r equir ed
accur acy) of less t han one-half t he minimum sampling per iod. The r equir ed closed-
loop bandwidt h, f
cl
, cor r esponding t o t he set t ling t ime can be est imat ed using t he
pr ocedur e and equat ions pr eviously descr ibed. Finally, it is most impor t ant t o
const r uct a pr ot ot ype of t he syst em and per for m an act ual evaluat ion of t he
combined op amp and ADC per for mance. Manufact ur er 's evaluat ion boar ds ar e
useful for t his pur pose.
2
6
DRIVE OP AMP SELECTION CRITERIA BASED ON
ADC DYNAMIC PERFORMANCE: SUMMARY
Select Op Amp with distortion and noise better than ADC
Consider other factors also:

Output Voltage Swing must match ADC input
Single or Dual-Supply System?
DC Accuracy / Drift if DC coupled
Examine ADC for transient load currents, if any
Op amp must have sufficient closed-loop bandwidth to
settle to transient currents
Use exponential decay model to estimate required f
cl
Figure 4.30
GAI N SETTI NG AND LEVEL SHI FTI NG
In dc coupled applicat ions, t he dr ive amplifier must pr ovide t he r equir ed gain and
offset t o mat ch t he signal t o t he input volt age r ange of t he ADC. Figur e 4.31
summar izes var ious gain and level shift ing opt ions. The cir cuit of Figur e 4.31A
oper at es in t he non-inver t ing mode and uses a r efer ence volt age, V
r ef
, t o offset t he
out put . Gain and offset int er act accor ding t o t he equat ion:
V
out
R
R
V
in
R
R
V
ref
= +






− 1
2
1
2
1
The cir cuit in Figur e 4.31B oper at es in t he inver t ing mode, and t he signal gain is
independent of t he offset . The disadvant age of t his cir cuit is t hat t he addit ion of R3
incr eases t he noise gain, and hence t he sensit ivit y t o t he op amp input offset volt age
and noise. The input /out put equat ion is given by:
V
out
R
R
V
in
R
R
V
ref
= − −
2
1
2
3
The cir cuit in Figur e 4.31C oper at es in t he inver t ing mode, and t he offset is applied
t o t he non-inver t ing input , wit h no noise gain penalt y. This cir cuit is also at t r act ive
for single-supply applicat ions wher e V
r ef
> 0. The input /out put equat ion is given by:
V
out
R2
R1
V
in
R4
R3 R4
1
R2
R1
V
ref
= − +
+






+






2
7
OP AMP LEVEL SHIFTING CIRCUITS
Figure 4.31
A pr act ical example of a single-supply video signal-pr ocessing digit izing cir cuit is
shown in Figur e 4.32. The AD876 (10-bit , 20MSPS) ADC oper at es on a single +5V
supply, and it s nominal input volt age r ange is 2V peak-t o-peak cent er ed ar ound an
allowable common-mode volt age bet ween +2.7V and +3.1V. The input volt age r ange
of t he AD876 is set by ext er nal r efer ences. The AD812 dr ive amplifier is a fast video
op amp wit h a common-mode input volt age r ange of +1V t o +4V, and a +1V t o +4V
out put volt age r ange. Wit h t his amplifier /ADC combinat ion, opt imum per for mance
is obt ained by set t ing t he AD876 input common-mode volt age at +2.7V
(cor r esponding t o an upper and lower input r ange of +3.7 and +1.7V, r espect ively).
SINGLE-SUPPLY DC-COUPLED DRIVE CIRCUIT FOR
AD876 10-BIT, 20MSPS ADC USING AD812 OP AMP
Figure 4.32
2
8
The Thevenin equivalent cir cuit of t he video signal is a gr ound-r efer enced, 0 t o +2V
sour ce wit h a 75ohm sour ce impedance designed t o dr ive a 75ohm t er minat ed
coaxial cable, pr oducing a st andar d 0 t o +1V video signal level at t he load
t er minat ion, R
T
. (The video sour ce can also be modeled as a Nor t on equivalent
cir cuit wit h a 0 t o +26.7mA cur r ent sour ce in par allel wit h t he 75ohm sour ce
r esist ance.)
The AD812 op amp is oper at ed as an inver t ing level shift er , similar t o t he cir cuit
pr eviously shown in Figur e 4.31C. The feedback r esist or , R2, is chosen t o be
681ohms for opt imum flat ness over t he video bandwidt h per t he AD812 dat a sheet .
The feedfor war d r esist or , R1, is select ed t o give a signal gain of –2. The t er minat ion
r esist or , R
T
, is chosen so t hat t he par allel combinat ion of R
T
and R1 is 75ohms. The
common-mode volt age, V
cm
, r equir ed on t he non-inver t ing op amp input must now
be det er mined. Assume t hat t he video sour ce is zer o volt s. The cor r esponding op
amp out put volt age should be +3.7V. The common-mode volt age is det er mined by
t he volt age divider for med by R2, R1, R
T
, and t he 75ohm sour ce r esist ance:
V
cm
R
s
R
T
R
R
s
R
T
R R
V =
+
+ +





 =
+
+ +






= 37
1
1 2
37
42 340
42 340 681
133 .
||
||
. . .
The +1.33V common-mode volt age is der ived fr om t he AD680 +2.5V r efer ence using
a r esist or divider and is decoupled wit h a 10µF/25V t ant alum capacit or in par allel
wit h a 0.1µF low-induct ance cer amic one.
The AD9050 10-bit , 40MSPS single-supply ADC input r ange of ±0.5V is cent er ed
ar ound a common-mode volt age of +3.3V (cor r esponding t o an upper and lower limit
of +3.8V and +2.8V, r espect ively). An appr opr iat e single-supply dc-coupled dr ive
cir cuit based upon t he AD8011 low power , low dist or t ion op amp is shown in Figur e
4.33. The sour ce is a gr ound-r efer enced 0 t o +2V signal which is ser ies-t er minat ed in
75ohms. The t er minat ion r esist or , R
T
, is chosen such t hat t he par allel combinat ion
of R
T
and R1 is 75ohms. The AD8011 cur r ent -feedback op amp is configur ed for a
gain of –1. The feedback r esist or , R2, is t he value r ecommended for opt imum
bandwidt h. Assume t hat t he video sour ce is at zer o volt s. The cor r esponding ADC
input volt age should be +3.8V. The common-mode volt age, V
cm
, is det er mined fr om
t he following equat ion:
V
cm
R
s
R
T
R
R
s
R
T
R R
V =
+
+ +





 =
+
+ +






= 38
1
1 2
38
388 1000
38 8 1000 1000
194 .
||
||
.
.
.
.
The common-mode volt age, V
cm
, is der ived fr om t he common-mode volt age at t he
inver t ing input of t he AD9050. The +3.3V is buffer ed by t he AD820 single-supply
FET-input op amp. A divider net wor k gener at es t he r equir ed +1.94V for t he
AD8011, and a pot ent iomet er pr ovides offset adjust ment capabilit y.
The AD8011 cur r ent feedback op amp was chosen because of it s low power (5mW),
wide bandwidt h (200MHz), and low dist or t ion (–70dBc at 5MHz). It is fully specified
for bot h ±5V and +5V oper at ion. When oper at ing on a single +5V supply, t he input
common-mode r ange is +1.5V t o +3.5V, and t he out put swing is +1.2V t o +3.5V. The
high speed level-shift ing PNP t r ansist or at t he out put of t he AD8011 allows t he op
2
9
amp t o oper at e wit hin in it s r ecommended out put r ange and ensur es best dist or t ion
per for mance. Dist or t ion per for mance of t he ent ir e cir cuit including t he ADC is
bet t er t han –60dBc for an input fr equency of 10MHz and a sampling r at e of
40MSPS.
DC-COUPLED SINGLE-SUPPLY DRIVE CIRCUIT FOR
AD9050 10-BIT, 40MSPS ADC USING AD8011 OP AMP
Figure 4.33
AD8011 OP AMP KEY SPECIFICATIONS
Low Power: 1mA Current (5mW on +5V Supply)
Bandwidth: 320MHz (G=+1), 180MHz (G=+2)
Settling Time: 25ns to 0.1%
Low Distortion: -76dBc at 5MHz
Input Common Mode Voltage (+5V Supply): +1.5V to +3.5V
Output Voltage Swing (+5V Supply): +1.2V to +3.8V
Fully Specified for Single or Dual-Supply Operation
Figure 4.34
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0
HI GH SP EED SAMP LI NG ADC EXTERNAL REFERENCE
VOLTAGE GENERATI ON
Due t o pr ocess and design-r elat ed const r aint s, it is not always possible t o int egr at e
t he r efer ence and t he ADC on t he same chip. In some ADCs which do have an
int er nal r efer ence, per for mance impr ovement s (less noise and dr ift ) may be obt ained
by using an ext er nal r efer ence r at her t han t he int er nal one. We saw in t he case of
t he AD77XX ser ies t hat t his was t he case.
Ther e ar e a number of low-cost , low-noise, low-volt age r efer ences suit able for use
wit h high per for mance sampling ADCs. Refer ence volt ages of +1.25V, +2.048V,
+2.5V, +3.0V, +3.3V, +4.096V, and +4.5V ar e ideal for single-supply (+3V or +5V)
ADCs. (See Figur e 4.35).
LOW VOLTAGE REFERENCE SUMMARY
Figure 4.35
The AD876 r equir es t wo r efer ences: one for each end of it s input r ange which is
nominally set for +1.7V and +3.7V. The out put impedance of t he dr ive sour ces must
be low at high fr equencies t o absor b t he t r ansient cur r ent s gener at ed at t he ADC
r efer ence input t er minals by t he int er nal swit ched capacit or cir cuit s.
The cir cuit shown in Figur e 4.36 makes use of t he REF198 (+4.096V)
r efer ence (see pr evious discussion r egar ding t he analog input dr ive cir cuit for t he
AD876) and a dual FET-input single-supply op amp (AD822) t o gener at e t he t wo
volt ages. The AD876 r efer ence input s each have a FORCE (F) and SENSE (S) pin.
The Kelvin connect ion compensat es for t he volt age dr op in t he int er nal par asit ic
r esist ances (appr oximat ely 5ohms). The int er nal ADC r efer ence ladder impedance is
appr oximat ely 300ohms, r equir ing t he AD822s t o sour ce and sink appr oximat ely
6.7mA. Ther e is an addit ional r esist ance of appr oximat ely 300ohms in ser ies wit h
each SENSE line. The t wo r efer ence FORCE pins ar e decoupled at low and high
fr equencies using bot h a t ant alum and a cer amic capacit or . The addit ional 20µF
acr oss t he t wo SENSE pins adds addit ional decoupling for differ ent ial t r ansient s.
3
1
Not e t hat t he AD822 must be pr oper ly compensat ed t o dr ive t he lar ge capacit ive
load. Key specificat ions for t he AD822 ar e summar ized in Figur e 4.37.
REFERENCE VOLTAGE GENERATOR FOR
AD876 10-BIT, 20MSPS SINGLE-SUPPLY ADC
Figure 4.36
AD822 OP AMP KEY SPECIFICATIONS
True Single-Supply FET-Input Dual Op Amp
Complete Specifications for 15V, 5V, +5V, +3V
Input Voltage Range Extends 200mV Below Ground and to within
1V of +V
s
Output Goes to Within 5mV of Supplies (Open-Collector
Complementary Output Stage Limited by V
cesat
)
1.8MHz Unity-Gain Bandwidth
800 V Offset Voltage, 2 V/ C Offset Drift
Low Noise: 13nV/ Hz
Low Power: 800 A / Amplifier
Single Version Available (AD820)
Figure 4.37
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2
ADC I NP UT P ROTECTI ON AND CLAMP I NG
The input t o high speed ADCs should be pr ot ect ed fr om over dr ive t o pr event
cat ast r ophic damage or per for mance degr adat ion. A good r ule of t humb is never let
t he analog input exceed t he supply volt age by mor e t han 0.3V (t his not only applies
when t he supply is on, but also when it is off, i.e., if t he supply is off, t he analog
input should not exceed ±0.3V). In a dual supply syst em, t his r ule applies t o bot h
supplies. The r ule of t humb pr ot ect s most devices, but t he dat a sheet Absolut e
Maximum specificat ions should always be consult ed t o det er mine possible
except ions. In some ADCs, t he analog input is pr ot ect ed int er nally by diodes
connect ed t o t he supplies. In t hese cases, an ext er nal r esist or is r equir ed t o limit t he
input cur r ent t o 5mA or less under t he over volt age condit ion.
Sever al over dr ive pr ot ect ion schemes which use ext er nal diodes ar e shown in Figur e
4.38.
In Figur e 4.38A, t he op amp is power ed fr om ±15V, and t he ADC fr om ±5V. The
addit ion of t he Schot t ky diodes on t he input will pr event t he analog input fr om
exceeding t he ADC supplies. Some ADCs have int er nal diodes, but t he addit ion of
t he ext er nal ones ensur es pr ot ect ion for higher cur r ent s. An alt er nat ive solut ion is
t o gener at e t he ±5V for t he ADC fr om t he op amp ±15V supplies using t hr ee
t er minal r egulat or s (such as t he 78L05 and 79L05). This eliminat es possible
sequencing and over dr ive pr oblems, and power dissipat ion in t he r egulat or is not
excessive if low power CMOS ADCs ar e used (see Figur e 4.38B).
Wit h t he pr olifer at ion of high speed op amps and ADCs, bot h of which oper at e on
dual 5V supplies, t he sit uat ion shown in Figur e 4.38C is quit e common, and t her e is
no sequencing pr oblem pr ovided bot h t he amplifier and t he ADC ar e oper at ed fr om
t he same supplies.
Figur e 4.38D shows t he case wher e a flash conver t er (power ed fr om a single –5V
supply) is dr iven fr om an amplifier power ed fr om ±5 V. The ser ies r esist or and t he
Schot t ky diode pr ovide pr ot ect ion fr om for war d-biasing t he flash subst r at e diode
mor e t han a few t ent hs of a volt , t her eby pr event ing possible damage.
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3
ADC INPUT OVERVOLTAGE PROTECTION CIRCUITS
Figure 4.38
Specially designed high speed, fast r ecover y clamping amplifier s offer an at t r act ive
alt er nat ive t o designing ext er nal clamping/pr ot ect ion cir cuit s. The AD8036/AD8037
low dist or t ion, wide bandwidt h clamp amplifier s r epr esent a significant
br eakt hr ough in t his t echnology. These devices allow t he designer t o specify a high
(V
H
) and low (V
L
) clamp volt age. The out put of t he device clamps when t he input
exceeds eit her of t hese t wo levels. The AD8036/AD8037 offer super ior clamping
per for mance compar ed t o t r adit ional out put -clamping devices. Recover y t ime fr om
over dr ive is less t han 5ns.
The key t o t he AD8036 and AD8037's fast , accur at e clamp and amplifier
per for mance is t heir pr opr iet ar y input clamp ar chit ect ur e. t his new design r educes
clamp er r or s by mor e t han 10x over pr evious out put clamp based cir cuit s, as well as
subst ant ially incr easing t he bandwidt h, pr ecision, and ver sat ilit y of t he clamp
input s.
Figur e 4.39 is an idealized block diagr am of t he AD8036 connect ed as a unit y gain
volt age follower . The pr imar y signal pat h compr ises A1 (a 1200V/µs, 240MHz high
volt age gain, differ ent ial t o single-ended amplifier ) and A2 (a G=+1 high cur r ent
gain out put buffer ). The AD8037 differ s fr om t he AD8036 only in t hat A1 is
opt imized for closed-loop gains of t wo or gr eat er .
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4
AD8036/AD8037 CLAMP AMPLIFIER EQUIVALENT CIRCUIT
Figure 4.39
The input clamp sect ion is compr ised of compar at or s C
H
and C
L
, which dr ive swit ch
S1 t hr ough a decoder . The unit y-gain buffer s in ser ies wit h t he +V
IN
, V
H
, and V
L
input s isolat e t he input pins fr om t he compar at or s and S1 wit hout r educing
bandwidt h or pr ecision.
The t wo compar at or s have about t he same bandwidt h as A1 (240MHz), so t hey can
keep up wit h signals wit hin t he useful bandwidt h of t he AD8036. To illust r at e t he
oper at ion of t he input clamp cir cuit , consider t he case wher e V
H
is r efer enced t o
+1V, V
L
is open, and t he AD8036 is set for a gain of +1 by connect ing it s out put back
t o it s inver t ing input t hr ough t he r ecommended 140ohm feedback r esist or . Not e t hat
t he main signal pat h always oper at es closed loop, since t he clamping cir cuit only
affect s A1's noninver t ing input .
If a 0V t o +2V volt age r amp is applied t o t he AD8036's +V
IN
for t he connect ion just
descr ibed, V
OUT
should t r ack +V
IN
per fect ly up t o +1V, t hen should limit at exact ly
+1V as +V
IN
cont inues t o +2V.
In pr act ice, t he AD8036 comes close t o t his ideal behavior . As t he +V
IN
input
volt age r amps fr om zer o t o 1V, t he out put of t he high limit compar at or C
H
st ar t s in
t he off st at e, as does t he out put of C
L
. When +V
IN
just exceed V
H
(pr act ically, by
about 18mV), C
H
changes st at e, swit ching S1 fr om "A" t o "B" r efer ence level. Since
t he + input of A1 is now connect ed t o V
H
, fur t her incr eases in +V
IN
have no effect
on t he AD8036's out put volt age. The AD8036 is now oper at ing as a unit y-gain buffer
for t he V
H
input , as any var iat ion in V
H
, for V
H
> 1V, will be fait hfully pr oduced at
V
OUT
.
Oper at ion of t he AD8036 for negat ive input volt ages and negat ive clamp levels on
V
L
is similar , wit h compar at or C
L
cont r olling S1. Since t he compar at or s see t he
3
5
volt age on t he +V
IN
pin as t heir common r efer ence level, t he volt age V
H
and V
L
ar e
defined as "High" or "Low" wit h r espect t o +V
IN
. For example, if V
IN
is set t o zer o
volt s, V
H
is open, and V
L
is +1V, compar at or C
L
will swit ch S1 t o "C", so t he
AD8036 will buffer t he volt age on V
L
and ignor e +V
IN
.
The per for mance of t he AD8036/AD8037 closely mat ches t he ideal just descr ibed.
The compar at or 's t hr eshold ext ends fr om 60mV inside t he clamp window defined by
t he volt ages on V
L
and V
H
t o 60mV beyond t he window's edge. Swit ch S1 is
implement ed wit h cur r ent st eer ing, so t hat A1's + input makes a cont inuous
t r ansit ion fr om say, V
IN
t o V
H
as t he input volt age t r aver ses t he compar at or 's input
t hr eshold fr om 0.9V t o 1.0V for V
H
= 1.0V.
The pr act ical effect of t he non-ideal oper at ion is t o soft en t he t r ansit ion fr om
amplificat ion t o clamping modes, wit hout compr omising t he absolut e clamp limit set
by t he input clamping cir cuit . Figur e 4.40 is a gr aph of V
OUT
ver sus V
IN
for t he
AD8036 and a t ypical output clamp amplifier . Bot h amplifier s ar e set for G=+1 and
V
H
= +1V.
COMPARISON BETWEEN INPUT AND OUTPUT CLAMPING
Figure 4.40
The wor st case er r or bet ween V
OUT
(ideally clamped) and V
OUT
(act ual) is
t ypically 18mV t imes t he amplifier closed-loop gain. This occur s when V
IN
equals
V
H
(or V
L
). As V
IN
goes above and/or below t his limit , V
OUT
will st ay wit hin 5mV
of t he ideal value.
In cont r ast , t he out put clamp amplifier 's t r ansfer cur ve t ypically will show some
compr ession st ar t ing at an input of 0.8V, and can have an out put volt age as far as
200mV over t he clamp limit . In addit ion, since t he out put clamp causes t he amplifier
3
6
t o oper at e open-loop in t he clamp mode, t he amplifier 's out put impedance will
incr ease, pot ent ially causing addit ional er r or s, and t he r ecover y t ime is significant ly
longer .
It is impor t ant t hat a clamped amplifier such as t he AD8036/AD8037 maint ain low
levels of dist or t ion when t he input signals ar e close t he clamping volt ages. Figur e
4.41 shows t he second and t hir d har monic dist or t ion for t he amplifier s as t he out put
appr oaches t he clamp volt ages. The input signal is 20MHz, t he out put signal is 2V
peak-t o-peak, and t he out put load is 100ohms.
Recover y fr om st ep volt age which is t wo t imes over t he clamping volt age is shown in
Figur e 4.42. The input st ep volt age st ar t s at +2V and goes t o 0V (left -hand t r aces on
scope phot o). The input clamp volt age (V
H
) is set at +1V. The r ight -hand t r ace
shows t he out put wavefor m. The key specificat ions for t he AD8036/AD8037 clamped
amplifier s ar e summar ized in Figur e 4.43.
AD8036/AD8037 DISTORTION NEAR CLAMPING REGION,
OUTPUT = 2V p-p, LOAD = 100 , f = 20MHz
Figure 4.41
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7
AD8036 / AD8037 OVERDRIVE (2x) RECOVERY
Figure 4.42
AD8036 / AD8037 SUMMARY SPECIFICATIONS
Proprietary Input Clamping Circuit with Minimized Nonlinear
Clamping Region
Small Signal Bandwidth: 240MHz (AD8036), 270MHz (AD8037)
Slew Rate: 1500V/ s
1.5ns Overdrive Recovery
Low Distortion: -72dBc @ 20MHz (500 load)
Low Noise: 4.5nv/ Hz, 2pA/ Hz
20mA Supply Current on 5V
Figure 4.43
Figur e 4.44 shows t he AD9002 8-bit , 125MSPS flash conver t er dr iven by t he
AD8037 (240MHz bandwidt h) clamping amplifier . In t he cir cuit , t he bandwidt h of
t he AD8037 is 240MHz. The clamp volt ages on t he AD8037 ar e set t o +0.55 and –
0.55V, r efer enced t o t he ±0.5V input signal, wit h t he ext er nal r esist ive divider s. The
AD8037 also supplies a gain of t wo, and an offset of –1V (using t he AD780 volt age
r efer ence), t o mat ch t he 0 t o –2V input r ange of t he AD9002 flash conver t er . The
out put signal is clamped at +0.1V and –2.1V. This mult i-funct ion clamping cir cuit
t her efor e per for ms sever al impor t ant funct ions as well as pr event ing damage t o t he
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8
flash conver t er which occur s if it s input exceeds +0.5V, t her eby for war d biasing t he
subst r at e diode. The 1N5712 Schot t ky diode adds fur t her pr ot ect ion dur ing power -
up.
AD9002 8-BIT, 125MSPS FLASH CONVERTER
DRIVEN BY AD8037 CLAMP AMPLIFIER
Figure 4.44
The feedback r esist or , R2 = 301ohms, is select ed for opt imum bandwidt h per t he
manufact ur er 's dat a sheet r ecommendat ion. In or der t o give a gain of t wo, t he
par allel combinat ion of R1 and R3 must also equal R2:
R R
R R
R
1 3
1 3
2 301

+
= = Ω (near est 1% st andar d r esist or
value).
In addit ion, t he Thevenin equivalent out put volt age of t he AD780 +2.5V r efer ence
and t he R3/ R1 divider must be +1V t o pr ovide t he –1V offset at t he out put of t he
AD8037.
25 1
1 3
1
. ⋅
+
=
R
R R
volt
Solving t he t wo simult aneous equat ions yields R1 = 499ohms, R3 = 750ohms (using
t he near est 1% st andar d r esist or values).
Ot her input and out put volt ages r anges can be accommodat ed by appr opr iat e
changes in t he ext er nal r esist or s.
3
9
OTHER AP P LI CATI ONS FOR CLAMP I NG AMP LI FI ERS
The AD8036/AD8037's clamp out put can be set accur at ely and has a well cont r olled
flat level. This, along wit h wide bandwidt h and high slew r at e make t hem well
suit ed for a number of ot her applicat ions. Figur e 4.45 is a diagr am of a
pr ogr ammable level pulse gener at or . The cir cuit accept s a TTL t iming signal for it s
input and gener at es pulses at t he out put up t o 24V p-p wit h 2500V/µs slew r at e. The
out put levels can be pr ogr ammed t o anywher e in t he r ange bet ween –12V t o +12V.
PROGRAMMABLE PULSE GENERATOR USING
AD8037 CLAMP AMP AND AD811 OP AMP
Figure 4.45
The cir cuit uses an AD8037 oper at ing at a gain of t wo wit h an AD811 t o boost t he
out put t o t he ±12V r ange. The AD811 was chosen for it s abilit y t o oper at e wit h ±15V
supplies and it s high slew r at e.
R1 and R2 act as a level shift er t o make t he TTL signal levels appr oximat ely
symmet r ical above and below gr ound. This ensur es t hat bot h t he high and low logic
levels will be clamped by t he AD8037. For well cont r olled signal levels in t he out put
pulse, t he high and low out put levels r esult fr om t he clamping act ion of t he AD8037
and ar e not cont r olled by eit her t he high or low logic levels passing t hr ough a linear
amplifier . For good r ise and fall t imes at t he out put pulse, a logic family wit h high
speed edges should be used.
The high logic levels ar e clamped at 2 t imes t he volt age at V
H
, while t he low logic
levels ar e clamped at t wo t imes t he volt age at V
L
. The out put of t he AD8037 is
amplified by t he AD811 oper at ing at a gain of 5. The over all gain of 10 will cause t he
high out put level t o be 10 t imes t he volt age at V
H
, and t he low out put level t o be 10
t imes t he volt age at V
L
.
The clamping input s ar e addit ional input s t o t he input st age of t he AD8036/AD8037.
As such, t hey have an input bandwidt h compar able t o t he amplifier input s and lend
t hemselves t o some unique funct ions when t hey ar e dr iven dynamically.
Figur e 4.46 is a schemat ic for a full wave r ect ifier , somet imes called an absolut e
value gener at or . It wor ks well up t o 20MHz and can oper at e at significant ly higher
4
0
fr equencies wit h some degr adat ion in per for mance. The dist or t ion per for mance is
significant ly bet t er t han diode-based full-wave r ect ifier s, especially at high
fr equencies.
FULL-WAVE RECTIFIER USING AD8037 CLAMP AMP
Figure 4.46
The AD8037 is configur ed as an inver t ing amplifier wit h a gain of unit y. The input
dr ives t he inver t ing amplifier and also dir ect ly dr ives V
L
, t he lower level clamping
input . The high level clamping input , V
H
, is left float ing and plays no r ole in t he
cir cuit .
When t he input is negat ive, t he amplifier act s as a unit y-gain inver t er and out put s a
posit ive signal at t he same amplit ude as t he input , wit h opposit e polar it y. V
L
is
dr iven negat ive by t he input , so it per for ms no clamping act ion, because t he posit ive
out put signal is always higher t han t he negat ive level dr iving V
L
.
When t he input is posit ive, t he out put r esult is t he sum of t wo separ at e effect s.
Fir st , t he inver t ing amplifier mult iplies t he input by –1 because of t he unit y-gain
inver t ing configur at ion. This effect ively pr oduces as offset as explained above, but
wit h a dynamic level t hat is equal t o –1 t imes t he input . Second, alt hough t he
posit ive input is gr ounded (t hr ough 100ohms), t he out put is clamped at t wo t imes
t he volt age applied t o V
L
(a posit ive, dynamic volt age in t his case). The fact or of t wo
is because t he noise gain of t he amplifier is t wo.
The sum of t hese t wo act ions r esult s in an out put t hat is equal t o unit y t imes t he
input signal for posit ive input signals as shown in Figur e 4.47. An input /out put
scope phot o wit h an input signal of 20MHz and an amplit ude of ±1V is shown in
Figur e 4.48. Thus, for eit her posit ive or negat ive input signals, t he out put is unit y
t imes t he absolut e value of t he input signal. The cir cuit can be easily configur ed t o
pr oduce t he negat ive absolut e value of t he input by applying t he input t o V
H
r at her
t han V
L
.
4
1
FULL-WAVE RECTIFIER WAVEFORMS
Figure 4.47
FULL-WAVE RECTIFIER INPUT/OUTPUT SCOPE WAVEFORM
Figure 4.48
The cir cuit can get t o wit hin about 40mV of gr ound dur ing t he t ime when t he input
cr osses zer o. This volt age is fixed over a wide fr equency r ange, and is a r esult of t he
swit ching bet ween t he convent ional op amp input and t he clamp input . But because
4
2
t her e ar e no diodes t o r apidly swit ch fr om for war d t o r ever se bias, t he per for mance
far exceeds diode-based full wave r ect ifier s.
The 40mV offset can be r emoved by adding an offset t o t he cir cuit . A 27.4kohm input
r esist or t o t he inver t ing input will have a gain of 0.01, while changing t he gain of t he
cir cuit by only 1%. A plus or minus 4V dc level (depending on t he polar it y of t he
r ect ifier ) int o t his r esist or will compensat e for t he offset .
Full wave r ect ifier s ar e useful in many applicat ions including AM signal det ect ion,
high fr equency ac volt met er s, and var ious ar it hmet ic oper at ions.
The AD8037 can also be configur ed as an amplit ude modulat or as shown in Figur e
4.49. The posit ive input of t he AD8037 is dr iven wit h a squar e wave of sufficient
amplit ude t o pr oduce clamping act ion at bot h t he high and low levels. This is t he
higher fr equency car r ier signal. The modulat ion signal is applied t o bot h t he input of
a unit y gain inver t ing amplifier and t o V
L
, t he lower clamping input . V
H
is biased
at +0.5V.
AD8037 AMPLITUDE MODULATOR
Figure 4.49
4
3
AMPLITUDE MODULATED WAVEFORM
Figure 4.50
To under st and t he cir cuit oper at ion, it is helpful t o fir st consider a simpler cir cuit . If
bot h V
L
and V
H
ar e dc biased at –0.5V and t he car r ier and modulat ion input s
dr iven as above, t he out put would be a 2V p-p squar e wave at t he car r ier fr equency
r iding on a wavefor m at t he modulat ing fr equency. The inver t ing input (modulat ion
signal) is cr eat ing a var ying offset t o t he 2V p-p squar e wave at t he out put . Bot h t he
high and low levels clamp at t wice t he input levels on t he clamps because t he noise
gain of t he cir cuit is t wo.
When V
L
is dr iven by t he modulat ion signal inst ead of being held at a dc level, a
mor e complicat ed sit uat ion r esult s. The r esult ing wavefor m is composed of an upper
envelope and a lower envelope wit h t he car r ier squar e wave in bet ween. The upper
and lower envelopes ar e 180° out of phase as in a t ypical AM wavefor m.
The upper envelope is pr oduced by t he upper clamp level being offset by t he
wavefor m applied t o t he inver t ing input . This offset is t he opposit e polar it y of t he
input wavefor m because of t he inver t ing configur at ion.
The lower envelope is pr oduced by t he sum of t wo effect s. Fir st , it is offset by t he
wavefor m applied t o t he inver t ing input as in t he case of t he simpler cir cuit above.
The polar it y of t his offset is in t he same dir ect ion as t he upper envelope. Second, t he
out put is dr iven in t he opposit e dir ect ion of t he offset at t wice t he offset volt age by
t he modulat ion signal being applied t o V
L
. This r esult s fr om t he noise gain being
equal t o t wo, and since t her e is no inver sion in t his connect ion, it is opposit e polar it y
fr om t he offset .
The r esult at t he out put for t he lower envelope is t he sum of t hese t wo effect s, which
pr oduces t he lower envelope of an AM wavefor m. The dept h of modulat ion can be
modified by changing t he amplit ude of t he modulat ion signal. This changes t he
amplit ude of t he upper and lower envelope wavefor ms. The modulat ion dept h can
also be changed by changing t he dc bias applied t o V
H
. In t his case, t he amplit udes
4
4
of t he upper and lower envelope wavefor ms st ay const ant , but t he spacing bet ween
t hem changes. This alt er s t he r at io of t he envelope amplit ude t o t he amplit ude of t he
over all wavefor m.
NOI SE CONSI DERATI ONS I N HI GH SP EED SAMP LI NG
ADC AP P LI CATI ONS
High speed, wide bandwidt h sampling ADCs ar e opt imized for dynamic per for mance
over a wide r ange of analog input fr equencies. Because of t he wide bandwidt h fr ont
ends coupled wit h int er nal device and r esist or noise, DC input s gener ally pr oduce a
r ange of out put codes as shown in Figur e 4.51. The cor r ect code appear s most of t he
t ime, but adjacent codes appear wit h r educed pr obabilit y. If a nor mal pr obabilit y
densit y cur ve is fit t ed t o t his dist r ibut ion, t he st andar d deviat ion will be equal t o t he
equivalent r ms input noise of t he ADC.
OUTPUT HISTOGRAM OF AD9022 12-BIT, 20MSPS ADC
SHOWS EFFECTIVE INPUT NOISE OF 0.57LSB FOR DC INPUT
Figure 4.51
For inst ance, t he equivalent input noise of t he AD9022 12-bit , 20MSPS ADC is
appr oximat ely 0.57LSB r ms. This implies t hat t he best full scale sinewave signal-t o-
noise r at io t hat can be obt ained is appr oximat ely 68dB. (Full scale sinewave peak-t o-
peak amplit ude = 4096LSBs, or 1448LSBs r ms, fr om which t he SNR is calculat ed as
20 log10[1448/0.57] = 68dB). In fact , t he SNR of t he ADC is limit ed by ot her fact or s,
such as quant izat ion noise and dist or t ion.
When dr iving sampling ADCs wit h wideband op amps, t he out put noise of t he dr ive
amplifier can cont r ibut e t o t he over all ADC noise floor . A few quick calculat ions
4
5
should be made t o est imat e t he t ot al out put noise of t he op amp and see if it is
significant wit h r espect t o t he ADC noise.
The complet e noise model for an op amp is shown in Figur e 4.52. This model is
accur at e, pr ovided t her e is less t han 1 or 2dB peaking in t he closed-loop out put
fr equency r esponse. Excessive peaking in t he fr equency r esponse incr eases t he
effect s of t he wide band noise, and t he simple appr oximat ion will give opt imist ic
r esult s.
GENERALIZED OP AMP NOISE MODEL
Figure 4.52
It is r ar ely necessar y t o consider all noise sour ces, since sour ces which have noise
cont r ibut ions 50% smaller t han t he lar gest can be neglect ed. In high speed syst ems,
wher e t he r esist or s of t he sour ce and t he op amp feedback net wor k r ar ely exceed
1kohm, t he r esist or J ohnson noise can usually be neglect ed.
In t he case of volt age feedback op amps, t he input cur r ent noise can usually be
neglect ed. For cur r ent feedback op amps oper at ing at noise gains of appr oximat ely 4
or less, t he inver t ing input cur r ent noise gener ally dominat es. At higher noise gains,
however , t he effect s of volt age noise become significant and should be included.
4
6
SIMPLIFICATIONS IN NOISE CALCULATIONS
Voltage Feedback Op Amps:

Neglect Resistor Noise if Resistors < 1k
Neglect Input Current Noise
Current Feedback Op Amps:

Neglect Resistor Noise if Resistors < 1k
Neglect Non-Inverting Input Current Noise
Evaluate Effects of Both Input Voltage Noise
(Dominates at High Noise Gains)
and
Inverting Input Current Noise
(Dominates at Low Noise Gains)
Figure 4.53
As an example t o show t he effect s of noise, consider t he cir cuit shown in Figur e 4.54,
wher e t he AD9022 12-bit , 20MSPS ADC is dr iven by t he AD9632 low-dist or t ion op
amp. Because t he AD9632 is a volt age feedback op amp and t he ext er nal r esist or
values ar e less t han 1kohm, only t he volt age noise (4.3nV/r t Hz) is significant t o t he
calculat ion. Because t he AD9632 is oper at ed wit h a noise gain of 2, t he out put
volt age noise is 8.6nv/r t Hz (excluding any sour ce noise).
NOISE CALCULATIONS FOR AD9632 OP AMP DRIVING
AD9022 12-BIT, 20MSPS ADC
Figure 4.54
The bandwidt h for int egr at ion is eit her t he op amp closed-loop bandwidt h (250MHz),
or t he ADC input bandwidt h (110MHz), whichever is less. This is an impor t ant
point , because in most cases (especially when dealing wit h low-dist or t ion, wide
4
7
bandwidt h amplifier s), t he input of t he ADC act s as t he low pass filt er t o t he op amp
noise.
The calculat ion for t he op amp noise cont r ibut ion at t he ADC input is simple:
V
ni
nV
Hz
Hz V rms = • × × =
86
110 10
6
157 113
.
. µ
The fact or of 1.57 is r equir ed t o conver t t he single-pole 110MHz ADC input
bandwidt h int o an equivalent noise bandwidt h. The op amp cont r ibut ion of 113µV
r ms is less t han one-half t he effect ive input noise of t he AD9022 (0.57LSB = 285µV
r ms), and can t her efor e be neglect ed.
In most high speed syst em applicat ions, a passive ant ialiasing filt er (eit her lowpass
for baseband sampling, or bandpass for har monic or under sampling) is r equir ed.
Placing t his filt er bet ween t he op amp and t he ADC will fur t her r educe t he effect s of
t he dr ive amplifier noise.
PROPER POSITIONING OF THE ANITALIASING FILTER
WILL REDUCE THE EFFECTS OF THE OP AMP NOISE
Figure 4.55
The op amp noise r ar ely limit s t he per for mance of high speed syst ems. The lar gest
sour ce of unwant ed noise gener ally comes fr om impr oper at t ent ion t o good high
speed layout , gr ounding, and decoupling t echniques.
4
8
ADC NOISE SOURCES
ADC Distortion and Quantization Noise
ADC Equivalent Input Noise
Internal SHA Aperture Jitter
External Drive Amplifier
Poor Grounding and Decoupling Techniques
Poor Layout and Signal Routing Techniques
Noisy Sampling Clock
External Switching Power Supply
Figure 4.56
Pr oper power supply decoupling t echniques must be used on each PC boar d in t he
syst em. Figur e 4.57 shows an ar r angement which will ensur e minimum pr oblems.
The power supply input (usually br ought int o t he PC boar d on mult iple pins) is fir st
decoupled t o t he lar ge-ar ea low-impedance gr ound plane wit h a good qualit y, low
ESL and low ESR t ant alum elect r olyt ic capacit or . This capacit or bypasses low
fr equency noise t o t he gr ound plane. The fer r it e bead r educes high fr equency noise
t o t he r est of t he cir cuit . You should t hen place one low-induct ance cer amic capacit or
at each power pin on each IC. Ideally, you should use sur face-mount chip capacit or s
for minimum induct ance, but if you use leaded cer amics, be sur e t o minimize t he
lead lengt hs by mount ing t hem flush on t he PC boar d. Some ICs may r equir e an
addit ional small t ant alum elect r olyt ic capacit or (usually bet ween 1 and 5µF). The
dat a sheet s for each IC should pr ovide appr opr iat e r ecommendat ions, but when in
doubt , put t hem in!
4
9
PROPER POWER SUPPLY DECOUPLING AT EACH IC ON THE
PC BOARD IS CRITICAL TO ACHIEVING GOOD HIGH SPEED
SYSTEM PERFORMANCE
Figure 4.57
If a double-sided PC boar d is used, one side should be dedicat ed ent ir ely (at least
75% of t he t ot al ar ea) t o t he gr ound plane. The ICs ar e mount ed on t his side, and
connect ions ar e made on t he opposit e side. Because of component int er connect ions,
however , a few br eaks in t he gr ound plane ar e usually unavoidable. As mor e and
mor e of t he gr ound plane is eat en away for int er connect ions, it s effect iveness
diminishes. It is t her efor e r ecommended t hat mult ilayer PC boar ds be used wher e
component packing densit y is high. Dedicat e at least one ent ir e layer t o t he gr ound
plane.
When connect ing t o t he backplane, use a number of pins (30 t o 40%) on each PC
boar d connect or for gr ound. This will ensur e t hat t he low impedance gr ound plane is
maint ained bet ween t he var ious PC boar ds in a mult icar d syst em.
In pr act ically all high speed syst ems, it is highly desir able t o physically separ at e
sensit ive analog component s fr om noisy digit al component s. It is usually a good idea
t o also est ablish separ at e analog and digit al gr ound planes on each PC boar d as
shown in Figur e 4.58. The separ at e analog and digit al gr ound planes ar e cont inued
on t he backplane using eit her mot her boar d gr ound planes or "gr ound scr eens"
which ar e made up of a ser ies of wir ed int er connect ions bet ween t he connect or
gr ound pins. The gr ound planes ar e joined t oget her at t he syst em star ground , or
single-point ground, usually locat ed at t he common r et ur n point for t he power
supplies. The Schot t ky diodes ar e inser t ed t o pr event accident al dc volt ages fr om
developing bet ween t he t wo gr ound syst ems.
5
0
SEPARATING ANALOG AND DIGITAL GROUNDS
IN A MULTICARD, STAR GROUND SYSTEM
Figure 4.58
Sensit ive analog component s such as amplifier s and volt age r efer ences ar e
r efer enced and decoupled t o t he analog gr ound plane. The ADCs and DACs (and
even some mixed-signal ICs) should be treated as analog circuits and also grounded
and decoupled to the analog ground plane. At fir st glance, t his may seem somewhat
cont r adict or y, since a conver t er has an analog and digit al int er face and usually pins
designat ed as analog gr ound (AGND) and digit al gr ound (DGND). The diagr am
shown in Figur e 4.59 will help t o explain t his seeming dilemma.
5
1
PROPER GROUNDING OF ADCs, DACs,
AND OTHER MIXED-SIGNAL Ics
Figure 4.59
Inside an IC t hat has bot h analog and digit al cir cuit s, such as an ADC or a DAC, t he
gr ounds ar e usually kept separ at e t o avoid coupling digit al signals int o t he analog
cir cuit s. Figur e 4.59 shows a simple model of a conver t er . Ther e is not hing t he IC
designer can do about t he wir ebond induct ance and r esist ance associat ed wit h
connect ing t he pads on t he chip t o t he package pins except t o r ealize it 's t her e. The
r apidly changing digit al cur r ent s pr oduce a volt age at point B which will inevit ably
couple int o point A of t he analog cir cuit s t hr ough t he st r ay capacit ance, C
STRAY
. In
addit ion, t her e is appr oximat ely 0.2pF unavoidable st r ay capacit ance bet ween ever y
pin of t he IC package! It 's t he IC designer 's job t o make t he chip wor k in spit e of
t his. However , in or der t o pr event fur t her coupling, t he AGND and DGND pins
should be joined t oget her ext er nally t o t he analog gr ound plane wit h minimum lead
lengt hs. Any ext r a impedance in t he DGND connect ion will cause mor e digit al noise
t o be developed at point B; it will, in t ur n, couple mor e digit al noise int o t he analog
cir cuit t hr ough t he st r ay capacit ance.
The name "DGND" on an IC t ells us t hat t his pin connect s t o t he digit al gr ound of
t he IC. It does not say t hat t his pin must be connect ed t o t he digit al gr ound of t he
syst em.
It is t r ue t hat t his ar r angement will inject a small amount of digit al noise on t he
analog gr ound plane. These cur r ent s should be quit e small, and can be minimized by
ensur ing t hat t he conver t er input /or out put does not dr ive a lar ge fanout .
Minimizing t he fanout on t he conver t er 's digit al por t will also keep t he conver t er
logic t r ansit ions r elat ively fr ee fr om r inging, and t her eby minimize any pot ent ial
coupling int o t he analog por t of t he conver t er . The logic supply pin (V
D
) can be
fur t her isolat ed fr om t he analog supply by t he inser t ion of a small fer r it e bead as
shown in Figur e 4.60. The int er nal digit al cur r ent s of t he conver t er will r et ur n t o
gr ound t hr ough t he V
D
pin decoupling capacit or (mount ed as close t o t he conver t er
5
2
as possible) and will not appear in t he ext er nal gr ound cir cuit . It is always a good
idea (as shown in Figur e 4.60) t o place a buffer lat ch adjacent t o t he conver t er t o
isolat e t he conver t er 's digit al lines fr om any noise which may be on t he dat a bus.
Even t hough a few high speed conver t er s have t hr ee-st at e out put s/input s, t his
isolat ion lat ch r epr esent s good design pr act ice.
The buffer lat ch and ot her digit al cir cuit s should be gr ounded and decoupled t o t he
digit al gr ound plane of t he PC boar d. Not ice t hat any noise bet ween t he analog and
digit al gr ound plane r educes t he noise mar gin at t he conver t er digit al int er face.
Since digit al noise immunit y is of t he or der s of hundr eds or t housands of millivolt s,
t his is unlikely t o mat t er .
POWER SUPPLY, GROUNDING, AND DECOUPLING POINTS
Figure 4.60
The sampling clock gener at ion cir cuit r y should also be gr ounded and heavily-
decoupled t o t he analog gr ound plane. As pr eviously discussed, phase noise on t he
sampling clock pr oduces degr adat ion in syst em SNR.
Separ at e power supplies for analog and digit al cir cuit s ar e also highly desir able. The
analog supply should be used t o power t he conver t er . If t he conver t er has a pin
designat ed as a digit al supply pin (V
D
), it should eit her be power ed fr om a separ at e
analog supply, or filt er ed as shown in t he diagr am. All conver t er power pins should
be decoupled t o t he analog gr ound plane, and all logic cir cuit power pins should be
decoupled t o t he digit al gr ound plane. If t he digit al power supply is r elat ively quiet ,
it may be possible t o use it t o supply analog cir cuit s as well, but be ver y caut ious.
A low phase-noise cr yst al oscillat or should be used t o gener at e t he ADC sampling
clock, because sampling clock jit t er modulat es t he input signal and r aises t he noise
and dist or t ion floor . The sampling clock gener at or should be isolat ed fr om noisy
digit al cir cuit s and gr ounded and decoupled t o t he analog gr ound plane, as is t r ue
for t he op amp and t he ADC.
5
3
It is evident t hat we can minimize noise by paying at t ent ion t o t he syst em layout
and pr event ing differ ent signals fr om int er fer ing wit h each ot her . High level analog
signals should be separ at ed fr om low level analog signals, and bot h should be kept
away fr om digit al signals. We have seen elsewher e t hat in wavefor m sampling and
r econst r uct ion syst ems t he sampling clock (which is a digit al signal) is as vulner able
t o noise as any analog signal, but is as liable t o cause noise as any digit al signal, and
so must be kept isolat ed fr om bot h analog and digit al syst ems.
SIGNAL ROUTING IN MIXED SIGNAL SYSTEMS
Physically separate analog and digital signals.
Avoid crossovers between analog and digital signals.
Be careful with sampling clock and ADC/DAC analog runs.
Use lots of ground plane.
Use microstrip techniques at high frequencies for controlled
impedances and controlled return current paths.
Use surface mount components in high frequency systems to
minimize parasitic capacitance and inductance.
Figure 4.61
If a gr ound plane is used, as it should in be most cases, it can act as a shield wher e
sensit ive signals cr oss. Figur e 4.62 shows a good layout for a dat a acquisit ion syst em
wher e all sensit ive ar eas ar e isolat ed fr om each ot her and signal pat hs ar e kept as
shor t as possible. While r eal life is r ar ely as t idy as t his, t he pr inciple r emains a
valid one.
A PC BOARD LAYOUT SHOWING GOOD SIGNAL ROUTING
Figure 4.62
5
4
Ther e ar e a number of impor t ant point s t o be consider ed when making signal and
power connect ions. Fir st of all a connect or is one of t he few places in t he syst em
wher e all signal conduct or s must r un par allel - it is t her efor e a good idea t o separ at e
t hem wit h gr ound pins (cr eat ing a far aday shield) t o r educe coupling bet ween t hem.
EDGE CONNECTIONS
Separate sensitive signal by ground pins.
Keep down ground impedances with multiple (30-40% of total)
ground pins.
Have several pins for each power line.
Critical signals such as analog or sampling clocks may require a
separate connector (possibly coax), or microstrip techniques.
Figure 4.63
Mult iple gr ound pins ar e impor t ant for anot her r eason: t hey keep down t he gr ound
impedance at t he junct ion bet ween t he boar d and t he backplane. The cont act
r esist ance of a single pin of a PCB connect or is quit e low (of t he or der of 10
milliohms) when t he boar d is new - as t he boar d get s older t he cont act r esist ance is
likely t o r ise, and t he boar d's per for mance may be compr omised. It is t her efor e well
wor t hwhile t o affor d ext r a PCB connect or pins so t hat t her e ar e many gr ound
connect ions (per haps 30-40% of all t he pins on t he PCB connect or should be gr ound
pins). For similar r easons t her e should be sever al pins for each power connect ion,
alt hough t her e is no need t o have as many as t her e ar e gr ound pins.
It is t empt ing t o mount expensive ICs in socket s r at her t han solder ing t hem in
cir cuit - especially dur ing cir cuit development . Engineer s would do well not t o
succumb t o t his t empt at ion.
USE OF SOCKETS WITH HIGH PERFORMANCE ANALOG CURCUITS
DON’T! (If at all possible)
Use “Pin sockets” or “Cage jacks” such as Amp Part No:
5-330808-3 or 5-330808-6 (Capped & uncapped respectively)
Always test the effect of sockets by comparing system
performance with and without the use of sockets.
Do not change the type of socket or manufacturer used without
evaluating the effects of the change on performance.
Figure 4.64
Socket s add r esist ance, induct ance and capacit ance t o t he cir cuit and may degr ade
per for mance t o quit e unaccept able levels. When t his occur s, t hough, it is always t he
5
5
IC manufact ur er who is blamed - not t he use of a socket . Even low pr ofile, low
inser t ion for ce socket s cannot be r elied upon t o ensur e t he per for mance of high
per for mance (high speed or high pr ecision or , wor st of all, bot h) devices. As t he
socket ages and t he boar d suffer s vibr at ion, t he cont act r esist ance of low inser t ion
for ce socket s is ver y likely t o r ise. Wher e a socket must be used t he best per for mance
is achieved by using individual pin socket s (somet imes called "cage jacks") t o make
up a mult i-pin socket in t he PCB it self (see Sect ion 9).
It r eally is best not t o use IC socket s wit h high per for mance analog and mixed signal
cir cuit s. If t heir use can be avoided it should be. However at medium speeds and
medium r esolut ions t he t r ade-off bet ween per for mance and convenience may fall on
t he side of convenience. It is ver y impor t ant , when socket s ar e used, t o evaluat e
cir cuit per for mance wit h and wit hout t he socket chosen t o ensur e t hat t he t ype of
socket chosen r eally does have minimal effect on t he way t hat t he cir cuit behaves.
The effect s of a change of socket on t he cir cuit should be evaluat ed as car efully as a
change of IC would be, and t he dr awings should be pr epar ed so t hat t he change
pr ocedur es for a socket ar e as r igor ous as for an IC - in or der t o pr event a pur chase
cler k who knows not hing of elect r onics fr om devast at ing t he syst em per for mance in
or der t o save five cent s on a socket .
The swit ching-mode power supply offer s low cost , small size, high efficiency, high
r eliabilit y and t he possibilit y of oper at ing fr om a wide r ange of input volt ages
wit hout adjust ment . Unfor t unat ely, t hese supplies pr oduce noise over a br oad band
of fr equencies, and t his noise occur s as conduct ed noise, r adiat ed noise, and
unwant ed elect r ic and magnet ic fields. When used t o supply logic cir cuit s, even mor e
noise is gener at ed on t he power supply bus. The noise t r ansient s on t he out put lines
of swit ching supplies ar e shor t -dur at ion volt age spikes. Alt hough t he act ual
swit ching fr equencies may r ange fr om 10 t o 100kHz, t hese spikes can cont ain
fr equency component s t hat ext end int o t he hundr eds of megaher t z.
Because of t he wide var iat ions in t he noise char act er ist ics of commer cially available
swit ching supplies, t hey should always be pur chased in accor dance wit h a
specificat ion-cont r ol dr awing. Alt hough specifying swit ching supplies in t er ms of
r ms noise is common pr act ice, you should also specify t he peak amplit udes of t he
swit ching spikes under t he out put loading condit ions you expect in your syst em. You
should also insist t hat t he swit ching-supply manufact ur er infor m you of any int er nal
supply design changes t hat may alt er t he spike amplit udes, dur at ion, or swit ching
fr equency. These changes may r equir e cor r esponding changes in t he ext er nal power -
supply filt er ing net wor ks.
5
6
SWITCHING-MODE POWER SUPPLIES
Generate Conducted and Radiated Noise as Well as Electric and
Magnetic Fields (HF and LF)
Outputs Must be Adequately Filtered if Powering Sensitive
Analog Circuits
Optimum Filter Design Depends on Power Supply
Characteristics. Beware of Power Supply Design Changes.
Use Faraday Shields to Reduce HF Electric and HF Magnetic
Fields
Physically Isolate Supply from Analog Circuits
Temporarily Replace Switching Supply with Low-Noise Linear
Supply or Battery when Suspicious of Switching Supply Noise
Figure 4.65
Filt er ing swit ching supply out put s t hat pr ovide sever al amps and gener at e volt age
spikes having high fr equency component s is a challenge. For t his r eason, you should
place t he init ial filt er ing bur den on t he swit ching supply manufact ur er . Even so,
ext er nal filt er ing such as shown in Figur e 4.66 should be added. The ser ies
induct or s isolat e bot h t he out put and common lines fr om t he ext er nal cir cuit s.
Because t he load cur r ent s may be lar ge, make sur e t hat t he induct or s select ed do
not sat ur at e. Split -cor e induct or s or lar ge fer r it e beads make a good choice. Because
t he swit ching power supplies gener at e high and low fr equency elect r ic and magnet ic
fields, t hey should be physically separ at ed as far as possible fr om cr it ical analog
cir cuit r y. This is especially impor t ant in pr event ing t he induct ive coupling of low
fr equency magnet ic fields.
5
7
FILTERING A SWITCHING SUPPLY OUTPUT
Figure 4.66
5
8
REFERENCES
1. Li n ea r Desi gn Semi n a r , Analog Devices, 1995, Chapt er 4, 5.
2. Syst em Ap p li ca t i on s Gu i d e, Analog Devices, 1993, Chapt er 12, 13.
3. Amp li fi er Ap p li ca t i on s Gu i d e, Analog Devices, 1992, Chapt er 7.
4. Walt Kest er , Drive Circuitry is Critical to High-S peed S ampling ADCs,
Elect r on i c Desi gn Sp eci a l An a log I ssu e, Nov. 7, 1994, pp. 43-50.
5. Walt Kest er , Basic Characteristics Distinguish S ampling A/ D Converters ,
EDN, Sept . 3, 1992, pp. 135-144.
6. Walt Kest er , Peripheral Circuits Can Make or Break S ampling ADC
S ystems, EDN, Oct . 1, 1992, pp. 97-105.
7. Walt Kest er , Layout, Grounding, and Filtering Complete S ampling
ADC S ystem, EDN, Oct . 15, 1992, pp. 127-134.
8. Car l Mor eland, An 8-Bit 150MS PS S erial ADC, 1995 I SSCC Di gest of
Tech n i ca l P a p er s, Vol. 38, pp. 272.
9. Roy Gosser and Fr ank Mur den, A 12-Bit 50MS PS Two-S tage A/ D
Converter, 1995 I SSCC Di gest of Tech n i ca l P a p er s, p. 278.
1
SECTION 5
UNDERSAMPLING APPLICATIONS
Fundamentals of Undersampling
Increasing ADC SFDR and ENOB using External SHAs
Use of Dither Signals to Increase ADC Dynamic Range
Effect of ADC Linearity and Resolution on SFDR and
Noise in Digital Spectral Analysis Applications
Future Trends in Undersampling ADCs
2
SECTI ON 5
UNDERSAMP LI NG AP P LI CATI ONS
Wa l t Kest er
An excit ing new applicat ion for wideband, low dist or t ion ADCs is called
undersampling, harmonic sampling, bandpass sampling, or S uper-Nyquist
S ampling. To under st and t hese applicat ions, it is necessar y t o r eview t he basics of
t he sampling pr ocess.
The concept of discr et e t ime and amplit ude sampling of an analog signal is shown in
Figur e 5.1. The cont inuous analog dat a must be sampled at discr et e int er vals, t
s
,
which must be car efully chosen t o insur e an accur at e r epr esent at ion of t he or iginal
analog signal. It is clear t hat t he mor e samples t aken (fast er sampling r at es), t he
mor e accur at e t he digit al r epr esent at ion, but if fewer samples ar e t aken (lower
sampling r at es), a point is r eached wher e cr it ical infor mat ion about t he signal is
act ually lost . This leads us t o t he st at ement of Shannon's Infor mat ion Theor em and
Nyquist 's Cr it er ia given in Figur e 5.2. Most t ext books st at e t he Nyquist t heor em
along t he following lines: A signal must be sampled at a rate greater than twice its
maximum frequency in order to ensure unambiguous data. The gener al assumpt ion
is t hat t he signal has fr equency component s fr om dc t o some upper value, f
a
. The
Nyquist Cr it er ia t hus r equir es sampling at a r at e f
s
> 2f
a
in or der t o avoid
over lapping aliased component s. For signals which do not ext end t o dc, however , t he
minimum r equir ed sampling r at e is a funct ion of t he bandwidth of t he signal as well
as it s posit ion in t he fr equency spect r um.
SAMPLING AN ANALOG SIGNAL
Figure 5.1
3
SHANNON’S INFORMATION THEOREM
AND NYQUIST’S CRITERIA
Shannon:

An Analog Signal with a Bandwidth of f
a
Must be Sampled
at a Rate of f
s
>2f
a
in Order to Avoid the Loss of
Information.
The signal bandwidth may extend from DC to f
a
(Baseband
Sampling) or from f
1
to f
2
, where f
a
= f
2
- f
1
(Undersampling,
Bandpass Sampling, Harmonic Sampling, Super-Nyquist)
Nyquist:

If f
s
<2f
a
, then a Phenomena Called Aliasing Will Occur.
Aliasing is used to advantage in undersampling
applications.
Figure 5.2
In or der t o under st and t he implicat ions of aliasing in bot h t he t ime and fr equency
domain, fir st consider t he four cases of a t ime domain r epr esent at ion of a sampled
sinewave signal shown in Figur e 5.3. In Case 1, it is clear t hat an adequat e number
of samples have been t aken t o pr eser ve t he infor mat ion about t he sinewave. In Case
2 of t he figur e, only four samples per cycle ar e t aken; st ill an adequat e number t o
pr eser ve t he infor mat ion. Case 3 r epr esent s t he ambiguous limit ing condit ion wher e
f
s
=2f
a.
If t he r elat ionship bet ween t he sampling point s and t he sinewave wer e such
t hat t he sinewave was being sampled at pr ecisely t he zer o cr ossings (r at her t han at
t he peaks, as shown in t he illust r at ion), t hen all infor mat ion r egar ding t he sinewave
would be lost . Case 4 of Figur e 5.3 r epr esent s t he sit uat ion wher e f
s
<2f
a
, and t he
infor mat ion obt ained fr om t he samples indicat es a sinewave having a fr equency
which is lower t han f
s
/2, i.e. t he out -of -band signal is aliased int o t he Nyquist
bandwidt h bet ween dc and f
s
/2. As t he sampling r at e is fur t her decr eased, and t he
analog input fr equency f
a
appr oaches t he sampling fr equency f
s
, t he aliased signal
appr oaches dc in t he fr equency spect r um.
4
TIME DOMAIN EFFECTS OF ALIASING
Figure 5.3
The cor r esponding fr equency domain r epr esent at ion of t he above scenar io is shown
in Figur e 5.4. Not e t hat sampling t he analog signal f
a
at a sampling r at e f
s
act ually
pr oduces t wo alias fr equency component s, one at f
s
+f
a
, and t he ot her at f
s
–f
a
. The
upper alias, f
s
+f
a
, seldom pr esent s a pr oblem, since it lies out side t he Nyquist
bandwidt h. It is t he lower alias component , f
s
–f
a
, which causes pr oblems when t he
input signal exceeds t he Nyquist bandwidt h, f
s
/2.
5
FREQUENCY DOMAIN EFFECTS OF ALIASING
Figure 5.4
Fr om Figur e 5.4, we make t he ext r emely impor t ant obser vat ion t hat regardless of
where the analog signal being sampled happens to lie in the frequency spectrum (as
long as it does not lie on multiples of f
s
/ 2), the effects of sampling will cause either
the actual signal or an aliased component to fall within the Nyquist bandwidth
between dc and f
s
/ 2. Ther efor e, any signals which fall out side t he bandwidt h of
int er est , whet her t hey be spur ious t ones or r andom noise, must be adequat ely
filt er ed before sampling. If unfilt er ed, t he sampling pr ocess will alias t hem back
wit hin t he Nyquist bandwidt h wher e t hey can cor r upt t he want ed signals.
Met hods exist which use aliasing t o our advant age in signal pr ocessing applicat ions.
Figur e 5.5 shows four cases wher e a signal having a 1MHz bandwidt h is locat ed in
differ ent por t ions of t he fr equency spect r um. The sampling fr equency must be
chosen such t hat t her e is no over lapping of t he aliased component s. In gener al, t he
sampling fr equency must be at least t wice t he signal bandwidt h, and t he sampled
signal must not cr oss an int eger mult iple of f
s
/2.
6
MINIMUM SAMPLING RATE REQUIRED FOR NON-
OVERLAPPING ALIASING OF A 1MHz BANDWIDTH SIGNAL
Figure 5.5
In t he fir st case, t he signal occupies a band fr om dc t o 1MHz, and t her efor e must be
sampled at gr eat er t han 2MSPS. The second case shows a 1MHz signal which
occupies t he band fr om 0.5 t o 1.5MHz. Not ice t hat t his signal must be sampled at a
minimum of 3MSPS in or der t o avoid over lapping aliased component s. In t he t hir d
case, t he signal occupies t he band fr om 1 t o 2MHz, and t he minimum r equir ed
sampling r at e for no over lapping aliased component s dr ops back t o 2MSPS. The last
case shows a signal which occupies t he band fr om 1.5 t o 2.5MHz. This signal must
be sampled at a minimum of 2.5MSPS t o avoid over lapping aliased component s.
This analysis can be gener alized as shown in Figur e 5.6. The act ual minimum
r equir ed sampling r at e is a funct ion of t he r at io of t he highest fr equency component ,
f
MAX
, t o t he t ot al signal bandwidt h, B. Not ice for lar ge r at ios of f
MAX
t o t he
bandwidt h, B, t he minimum r equir ed sampling fr equency appr oaches 2B.
7
MINIMUM REQUIRED SAMPLING RATE AS A FUNCTION OF
THE RATIO OF THE HIGHEST FREQUENCY COMPONENT
TO THE TOTAL SIGNAL BANDWIDTH
Figure 5.6
Let us consider t he case of a signal which occupies a bandwidth of 1MHz and lies
bet ween 6 and 7MHz as shown in Figur e 5.7. Shannon's Infor mat ion Theor em st at es
t hat t he signal (bandwidt h = 1MHz) must be sampled at least at 2MSPS in or der t o
r et ain all t he infor mat ion (avoid over lapping aliased component s). Assuming t hat
t he ADC sampling r at e, f
s
, is 2MSPS, addit ional sampling fr equencies ar e gener at ed
at all int eger mult iples of f
s
: 4MHz, 6MHz, 8MHz, et c. The act ual signal bet ween 6
and 7MHz is aliased ar ound each of t hese sampling fr equency har monics, f
s
, 2f
s
, 3f
s
,
4f
s
, ...., hence t he t er m harmonic sampling. Not ice t hat any one of t he aliased
component s is an accur at e r epr esent at ion of t he or iginal signal (t he fr equency
inver sion which occur s for one-half of t he aliased component s can be r emoved in
soft war e). In par t icular , t he component lying in t he baseband r egion bet ween dc and
1MHz is t he one calculat ed using a Fast Four ier Tr ansfor m, and is also an accur at e
r epr esent at ion of t he or iginal signal, assuming no ADC conver sion er r or s. The FFT
out put t ells us all t he char act er ist ics of t he signal except for it s or iginal posit ion in
t he fr equency spect r um, which was apr ior i knowledge.
8
INTERMEDIATE FREQUENCY (IF) SIGNAL BETWEEN
6 AND 7 MHz IS ALIASED BETWEEN DC AND 1MHz
BY SAMPLING AT 2MSPS
Figure 5.7
A popular applicat ion of under sampling is in digit al r eceiver s. A simplified block
diagr am of a t r adit ional digit al r eceiver using baseband sampling is shown in Figur e
5.8. The mixer in t he RF sect ion of t he r eceiver mixes t he signal fr om t he ant enna
wit h t he RF fr equency of t he local oscillat or . The desir ed infor mat ion is cont ained in
r elat ively small bandwidt h of fr equencies Delt a f. In act ual r eceiver s, Delt a f may
be as high as a few megaher t z. The local oscillat or fr equency is chosen such t hat t he
Delt a f band is cent er ed about t he IF fr equency at t he bandpass filt er out put .
Popular IF fr equencies ar e gener ally bet ween 10 and 100MHz. The det ect or t hen
t r anslat es t he Delt a f fr equency band down t o baseband wher e it is filt er ed and
pr ocessed by a baseband ADC. Act ual r eceiver s can have sever al st ages of RF and IF
pr ocessing, but t he simple diagr am ser ves t o illust r at e t he concept s.
SIMPLIGIED DIGITAL RECEIVER
USING BASEBAND SAMPLING
Figure 5.8
In a r eceiver which uses dir ect IF-t o-digit al t echniques (oft en called undersampling,
harmonic, bandpass, or IF sampling), t he IF signal is applied dir ect ly t o a wide
bandwidt h ADC as shown in Figur e 5.9. The ADC sampling r at e is chosen t o be at
least 2 Delt a f. The pr ocess of sampling t he IF fr equency at t he pr oper r at e causes
one of t he aliased component s of Delt a f t o appear in t he dc t o f
s
/2 Nyquist
9
bandwidt h of t he ADC out put . DSP t echniques can now be used t o pr ocess t he
digit al baseband signal. This appr oach eliminat es t he det ect or and it s associat ed
noise and dist or t ion. Ther e is also mor e flexibilit y in t he DSP because t he ADC
sampling r at e can be shift ed t o t une t he exact posit ion of t he ∆f signal wit hin t he
baseband.
The obvious pr oblem wit h t his appr oach is t hat t he ADC must now be able t o
accur at ely digit ize signals which ar e well out side t he dc t o f
s
/2 Nyquist bandwidt h
which most ADCs wer e designed t o handle. Special t echniques ar e available,
however , which can ext end t he dynamic r ange of ADCs t o include IF fr equencies.
SIMPLIFIED DIGITAL RECIEVER
USING IF SAMPLING
Figure 5.9
Let us consider a t ypical example, wher e t he IF fr equency is 72.5MHz, and t he
desir ed signal occupies a bandwidt h of 4MHz (B=4MHz), cent er ed on t he IF
fr equency (see Figur e 5.10). We know fr om t he pr evious discussion t hat t he
minimum sampling r at e must be gr eat er t han 8MHz, pr obably on t he or der of
10MHz in or der t o pr event dynamic r ange limit at ions due t o aliasing. If we place t he
sampling fr equency at t he lower band-edge of 70MHz (72.5–2.5), we will definit ely
r ecover t he aliased component of t he signal in t he dc t o 5MHz baseband. Ther e is,
however , no need t o sample at t his high r at e, so we may choose any sampling
fr equency 10MHz or gr eat er which is an int eger sub-mult iple of 70MHz, i.e., 70÷2 =
35.000MHz, 70÷3 = 23.333MHz, 70÷4 = 17.500MHz, 70÷5 = 14.000MHz, 70÷6 =
11.667MHz, or 70÷7 = 10.000MHz. We will t her efor e choose t he lowest possible
sampling r at e of 10.000MHz (70÷7).
1
0
INTERMEDIATE FREQUENCY (IF) SIGNAL
AT 72.5MHz ( 2MHz) IS ALIASED BETWEEN
DC AND 5MHz BY SAMPLING AT 10MSPS
Figure 5.10
Ther e is an advant age in choosing a sampling fr equency which a sub-mult iple of t he
lower band-edge in t hat t her e is no fr equency inver sion in t he baseband alias as
would be t he case for a sampling fr equency equal t o a sub-mult iple of t he upper
band-edge. (Fr equency inver sion can be easily dealt wit h in t he DSP soft war e should
it occur , so t he issue is not ver y impor t ant ).
Under sampling applicat ions such as t he one just descr ibed gener ally r equir e
sampling ADCs which have low dist or t ion at t he high input IF input fr equency. For
inst ance, in t he example just discussed, t he ADC sampling r at e r equir ement is only
10MSPS, but low dist or t ion is r equir ed (pr efer ably 60 t o 80dB SFDR) at t he IF
fr equency of 72.5MHz.
A lar ge oppor t unit y for bandpass sampling is in digit al cellular r adio base st at ions.
For syst ems which have RF fr equencies at 900MHz, 70MHz is a popular fir st -IF
fr equency. For syst ems using an RF fr equency of 1.8GHZ, fir st -IF fr equencies
bet ween 200 and 240MHz ar e oft en used.
In br oadband r eceiver applicat ions, one ADC digit izes mult iple channels in t he
r eceive pat h. Individual channel select ion and filt er ing is done in t he digit al domain.
Nar r owband channel char act er ist ics such as bandwidt h, passband r ipple, and
adjacent channel r eject ion can be cont r olled wit h changes t o digit al par amet er s (i.e.
filt er coefficient s). Such flexibilit y is not possible when nar r owband analog filt er s ar e
in t he r eceive pat h.
Figur e 5.11 illust r at es t he kind of input spect r um an ADC must digit ize in a
mult ichannel design. The spect r al lines r epr esent nar r owband signal input s fr om a
var iet y of signal sour ces at differ ent r eceived power levels. Signal "C" could
r epr esent a t r ansmit t er locat ed r elat ively far away fr om t he signal sour ces "A" and
"B". However , t he r eceiver must r ecover all of t he signals wit h equal clar it y. This
r equir es t hat dist or t ion fr om t he fr ont -end RF and IF signal pr ocessing component s,
1
1
including t he ADC, not exceed t he minimum accept able level r equir ed t o demodulat e
t he weakest signal of int er est . Clear ly, t hir d-or der int er modulat ion dist or t ion
gener at ed by "A" and "B" (2B - A, and 2A - B) will dist or t signals C and D if t he
nonlinear it ies in t he fr ont -end ar e sever e. St r ong out -of-band signals can also
int r oduce dist or t ion; signal "E" in Figur e 5.11 shows a lar ge signal t hat is par t ially
at t enuat ed by t he ant ialiasing filt er . In many syst ems, t he power level of t he
individual t r ansmit t er s is under cont r ol of t he base st at ion. This capabilit y helps t o
r educe t he t ot al dynamic r ange r equir ed.
BROADBAND DIGITAL RECEIVER ADC INPUT
Figure 5.11
In br oadband r eceiver applicat ions (using an RF fr equency of appr oximat ely
900MHz, and a fir st -IF fr equency of 70MHz), SFDR r equir ement s for t he ADC ar e
t ypically 70 t o 80dBc. Signal bandwidt hs bet ween 5MHz and 10MHz ar e common,
r equir ing cor r esponding sampling r at es of 10MSPS t o 20MSPS.
Sampling ADCs ar e gener ally designed t o pr ocess signals up t o Nyquist (f
s
/2) wit h a
r easonable amount of dynamic per for mance. As we have seen, however , even t hough
t he input bandwidt h of a sampling ADC is usually much gr eat er t han it s maximum
sampling r at e, t he SFDR and effect ive bit (ENOB) per for mance usually decr eases
dr amat ically for full scale input signals much above f
s
/2. This implies t hat t he
select ion cr it er ia for ADCs used in under sampling applicat ions is SFDR or ENOB at
t he IF fr equency, r at her t han sampling r at e.
The gener al pr ocedur e for select ing an ADC for an under sampling applicat ion is not
st r aight for war d. The signal bandwidt h and it s locat ion wit hin t he fr equency
spect r um must be known. The bandwidt h of t he signal det er mines t he minimum
sampling r at e r equir ed, and in or der t o ease t he r equir ement on t he ant ialiasing
filt er , a sampling r at e of 2.5 t imes t he signal bandwidt h wor ks well. Aft er
det er mining t he appr oximat e sampling fr equency needed, select t he ADC based on
t he r equir ed SFDR, S/(N+D), or ENOB at t he IF fr equency. This is wher e t he
dilemma usually occur s. You will find t hat an ADC specified for a maximum
sampling r at e of 10MSPS, for inst ance, will not have adequat e SFDR at t he IF
fr equency (72.5MHz in t he example above), even t hough it s per for mance is excellent
up t o it s Nyquist fr equency of 5Mhz. In or der t o meet t he SFDR, S/(N+D), or ENOB
1
2
r equir ement , you will gener ally r equir e an ADC having a much higher sampling r at e
t han is act ually needed.
Figur e 5.12 shows t he appr oximat e SFDR ver sus input fr equency for t he
AD9022/AD9023 (20MSPS), AD9026/AD9027 (31MSPS), and t he AD9042 (40MSPS)
ser ies of low dist or t ion ADCs. Not ice t hat t he AD9042 has super ior SFDR
per for mance.
SFDR COMPARISON BETWEEN 12-BIT SAMPLING ADCs
Figure 5.12
The AD9042 is a st at e-of-t he-ar t 12-bit , 40MSPS t wo st age subr anging ADC
consist ing of a 6-bit coar se ADC and a 7-bit r esidue ADC wit h one bit of over lap t o
cor r ect for any DNL, INL, gain or offset er r or s of t he coar se ADC, and offset er r or s
in t he r esidue pat h. A block diagr am is shown in Figur e 5.13. A pr opr iet ar y gr ay-
code ar chit ect ur e is used t o implement t he t wo int er nal ADCs. The gain alignment s
of t he coar se and r esidue, likewise t he subt r act ion DAC, r ely on t he st at ist ical
mat ching of t he pr ocess. As a r esult , 12-bit int egr al and differ ent ial linear it y is
obt ained wit hout laser t r im. The int er nal DAC consist s of 126 int er digit at ed cur r ent
sour ces. Also on t he DAC r efer ence ar e an addit ional 20 int er digit at ed cur r ent
sour ces t o set t he coar se gain, r esidue gain, and full scale gain. The int er digit izat ion
r emoves t he r equir ement for laser t r im. The AD9042 is fabr icat ed on a high speed
dielect r ically isolat ed complement ar y bipolar pr ocess. The t ot al power dissipat ion is
only 575mW when oper at ing on a single +5V supply.
1
3
BLOCK DIAGRAM OF AD9042 12-BIT, 40MSPS ADC
Figure 5.13
AD9042 12-BIT, 40MSPS ADC KEY SPECIFICATIONS
Input Range: 1V peak-to-peak, V
cm
= +2.4V
Input Impedance: 250 to V
cm
Effective Input Noise: 0.33LSBs rms
SFDR at 20MHz Input: 80dB
S/(N+D) at 20MHz Input = 66dB
Digital Outputs: TTL Compatible
Power Supply: Single +5V
Power Dissipation: 575mW
Fabricated on High Speed Dielectrically Isolated Complementary
Bipolar Process
Figure 5.14
The out st anding per for mance of t he AD9042 is par t ly due t o t he use of differ ent ial
t echniques t hr oughout t he device. The low dist or t ion input amplifier conver t s t he
single-ended input signal int o a differ ent ial one. If maximum SFDR per for mance is
desir ed, t he signal sour ce should be coupled dir ect ly int o t he input of t he AD9042
wit hout using a buffer amplifier . Figur e 5.15 shows a met hod using capacit ive
coupling.
1
4
INPUT STRUCTURE OF AD9042 ADC IS
DESIGNED TO BE DRIVEN DIRECTLY FROM 50
SOURCE FOR BEST SFDR
Figure 5.15
I NCREASI NG ADC SFDR AND ENOB USI NG EXTERNAL
SHAS
An ext er nal SHA can incr ease t he SFDR and ENOB of a sampling ADC for
under sampling applicat ions if pr oper ly select ed and int er faced t o t he ADC. The SHA
must have low hold-mode dist or t ion at t he fr equency of int er est . In addit ion, t he
acquisit ion t ime must be shor t enough t o oper at e at t he r equir ed sampling
fr equency. Figur e 5.17 shows t he effect s of adding a SHA t o an 8-bit flash conver t er .
The ADC is clocked at 20MSPS, and t he input fr equency t o t he ADC is 19.98MHz.
The scope phot o shows t he "beat " fr equency of 2kHz r econst r uct ed wit h an 8-bit
DAC. Not ice t hat wit hout t he SHA, t he ADC has non-linear it ies and missing codes.
The addit ion of t he SHA (pr oper ly select ed and t imed) gr eat ly impr oves t he linear it y
and r educes t he dist or t ion.
1
5
THE ADDITION OF AN EXTERNAL WIDEBAND LOW
DISTORTIOIN SHA EXTENDS THE LOW FREQUENCY
PERFORMANCE OF THE ADC TO HIGHER FREQUENCIES
Figure 5.16
EFFECTS OF EXTERNAL SHA ON FLASH ADC
PERFORMANCE FOR f
in
= 19.98MHz, f
s
= 20.00MSPS
Figure 5.17
1
6
Most SHAs ar e specified for dist or t ion when oper at ing in t he t r ack mode. What is of
r eal int er est , however , is t he signal dist or t ion in t he hold mode when t he SHA is
oper at ing dynamically. The AD9100 (30MSPS) and AD9101(125MSPS) ar e ult r a-
fast SHAs and ar e specified in t er ms of hold-mode dist or t ion. The measur ement is
done using a high per for mance low dist or t ion ADC (such as t he AD9014 14-bit ,
10MSPS) t o digit ize t he held value of t he SHA out put . An FFT is per for med on t he
ADC out put , and t he dist or t ion is measur ed digit ally. For sampling r at es gr eat er
t han 10MSPS, t he ADC is clocked at an int eger sub-mult iple of t he SHA sampling
fr equency. This causes a fr equency t r anslat ion in t he FFT out put because of
under sampling, but t he dist or t ion measur ement st ill r epr esent s t hat of t he SHA
which is oper at ing at t he higher sampling r at e. The AD9100 is opt imized for low
dist or t ion up t o 30MSPS, while t he AD9101 will pr ovide low dist or t ion per for mance
up t o a sampling r at e of 125MSPS. The low dist or t ion per for mance of t hese SHAs is
pr imar ily due t o t he ar chit ect ur e which differ s fr om t he classical open-loop SHA
ar chit ect ur e shown in Figur e 5.18.
CLASSIC OPEN-LOOP SHA ARCHITECTURE
Figure 5.18
The sampling swit ch in t he classic open-loop ar chit ect ur e is not wit hin a feedback
loop, and t her efor e dist or t ion is subject t o t he non-linear it y of t he swit ch. The
AD9100/AD9101 ar chit ect ur e shown in Figur e 5.19 ut ilizes swit ches inside t he
feedback loop t o achieve bet t er t han 12-bit AC and DC per for mance. The devices ar e
fabr icat ed on a high speed complement ar y bipolar pr ocess. In t he t r ack mode, S1
applies t he buffer ed input signal t o t he hold capacit or , C
H
, and S2 pr ovides negat ive
feedback t o t he input buffer . In t he hold mode, bot h swit ches ar e disconnect ed fr om
t he hold capacit or , and negat ive feedback t o t he input buffer is supplied by S1. This
ar chit ect ur e pr ovides ext r emely low hold-mode dist or t ion by maint aining high loop
gains at high fr equency. The out put buffer can be configur ed t o pr ovide volt age gain
(AD9101), which allows t he swit ches t o oper at e on lower common-mode volt age,
t her eby giving lower over all dist or t ion.
1
7
CLOSED-LOOP SHA ARCHITECTURE
PROVIDES LOW DISTORTION AND HIGH SPEED
(AD9100, AD9101)
Figure 5.19
The hold-mode SFDR of t he AD9100 is a funct ion of t he peak-t o-peak input signal
level and fr equency as shown in Figur e 5.20. Not ice t he dat a was t aken as a
sampling fr equency of 10MSPS for t hr ee input amplit udes. The t est configur at ion of
Figur e 5.21 was used t o collect t he dat a. For each input amplit ude, t he gain of t he op
amp bet ween t he AD9100 and t he AD9014 ADC was adjust ed such t hat t he signal
int o t he AD9014 was always full scale (2V peak-t o-peak). Not ice t hat opt imum
SFDR was obt ained wit h a 200mV p-p input signal. Timing bet ween t he SHA and
t he ADC is cr it ical. The SHA acquisit ion t ime should be long enough t o achieve t he
desir ed accur acy, but shor t enough t o allow sufficient hold-t ime for t he ADC fr ont -
end t o set t le and yield a low-dist or t ion conver sion. For t he t est configur at ion shown,
t he opt imum per for mance was achieved using an acquisit ion t ime of 20ns and a hold
t ime of 80ns. The ADC is clocked close t o t he end of t he SHA's hold t ime. Best
per for mance in t his t ype of applicat ion is always achieved by opt imizing t he t iming
in t he act ual cir cuit .
1
8
AD9100 HOLD-MODE SFDR MEASURED AT
A SAMPLING RATE OF 10MSPS
Figure 5.20
TEST CONFIGURATION AND TIMING FOR
MEASURING AD9100 SFDR AT 10MSPS
Figure 5.21
Figur e 5.22 shows t he SFDR of t he AD9100 super imposed on t he SFDR of t he
AD9026/AD9027 and t he AD9042 ADCs. These dat a indicat e t hat t he AD9100 will
significant ly impr ove t he SFDR of t he AD9026/AD9027 ADC at t he higher input
fr equencies. The per for mance of t he AD9042 indicat es t hat SFDR impr ovement s will
only occur at input fr equencies above 40MHz.
1
9
SFDR PERFORMANCE OF AD9100 SHA,
AD9026/AD9027 ADC, AND AD9042 ADC
Figure 5.22
The per for mance of t he AD9100 SHA dr iving t he AD9026/AD9027 ADC at a
sampling fr equency of 10MSPS is shown in Figur e 5.23. The input signal is a 200mV
peak-t o-peak 71.4MHz sinewave. The amplifier bet ween t he SHA and t he ADC is
adjust ed for a gain of 10. The SFDR is 72dBc, and t he SNR is 62dB.
FFT OUTPUT FOR AD9100 SHA DRIVING AD9026 ADC:
INPUT = 200mV p-p, G = 10, f
s
= 10MSPS, f
in
= 71.4MHz
Figure 5.23
Similar dynamic r ange impr ovement s can be achieved wit h high speed flash
conver t er s at higher sampling r at es wit h t he AD9101 SHA. The ar chit ect ur e is
2
0
similar t o t he AD9100, but t he out put buffer amplifier is opt imized for a gain of 4
(see Figur e 5.24). This configur at ion allows t he fr ont end sampler t o oper at e at
r elat ively low signal amplit udes, r esult ing in dr amat ic impr ovement in hold-mode
dist or t ion at high input fr equencies and sampling r at es up t o 125MSPS. The
AD9101 has an input bandwidt h of 350MHz and an acquisit ion t ime of 7ns t o 0.1%
and 11ns t o 0.01%.
AD9101 125MSPS SHA
Figure 5.24
A block diagr am and a t iming diagr am is shown for t he AD9101 dr iving t he AD9002
8 bit flash conver t er at 125MSPS (Figur e 5.25). The cor r esponding dynamic r ange
wit h and wit hout t he AD9101 is shown in Figur e 5.26.
2
1
AD9101 SHA DRIVING AD9002 8-BIT, 125MSPS
FLASH CONVERTER FOR IMPROVED DYNAMIC RANGE
Figure 5.25
AD9002 DYNAMIC PERFORMANCE
WITH AND WITHOUT AD9101 SHA
Figure 5.26
2
2
USE OF DI THER SI GNALS TO I NCREASE ADC DYNAMI C
RANGE
In t he development of classical ADC quant izat ion noise t heor y, t he assumpt ion is
usually made t hat t he quant izat ion er r or signal is uncor r elat ed wit h t he ADC input
signal. If t his is t r ue, t hen t he quant izat ion noise appear s as r andom noise spr ead
unifor mly over t he Nyquist bandwidt h, dc t o f
s
/2, and it has an r ms value equal t o
q/(sqr t 12). If, however , t he input signal is locked t o an non-pr ime int eger sub-
mult iple of f
s
, t he quant izat ion noise will no longer appear as unifor mly dist r ibut ed
r andom noise, but inst ead will appear as har monics of t he fundament al input
sinewave. This is especially t r ue if t he input is an exact even submult iple of f
s
.
Figur e 5.27 illust r at es t he point using FFT simulat ion for an ideal 12 bit ADC. The
FFT r ecor d lengt h was chosen t o be 4096. The spect r um on t he left shows t he FFT
out put when t he input signal is an exact even submult iple (1/32) of t he sampling
fr equency (t he fr equency was chosen so t hat t her e wer e exact ly 128 cycles per
r ecor d). The SFDR is appr oximat ely 78dBc. The spect r um on t he r ight shows t he
out put when t he input signal is such t hat t her e ar e exact ly 127 cycles per r ecor d.
The SFDR is now about 92dBc which is an impr ovement of 14dB. Signal-cor r elat ed
quant izat ion noise is highly undesir able in spect r al analysis applicat ions, wher e it
becomes difficult t o differ ent iat e bet ween r eal signals and syst em-induced spur ious
component s, especially when sear ching t he spect r um for t he pr esence of low-level
signals in t he pr esence of lar ge signals.
EFFECTS OF SAMPLING A SIGNAL WHICH IS AN EXACT EVEN
SUB-MULTIPLE OF THE ADC SAMPLING FREQUENCY
(M = 4096, IDEAL 12-BIT ADC SIMULATION)
Figure 5.27
Ther e ar e a number of ways t o r educe t his effect , but t he easiest way is t o add a
small amount of br oadband r ms noise t o t he ADC input signal as shown in Figur e
5.28. The r ms value of t his noise should be equal t o about 1/2 LSB. The effect of t his
is t o r andomize t he quant izat ion noise and eliminat e it s possible signal-dependence.
In most syst ems, t her e is usually enough r andom noise pr esent on t he input signal
so t hat t his happens aut omat ically. This is especially likely when using high speed
ADCs which have 12 or mor e bit s of r esolut ion and a r elat ively small input r ange of
2V p-p or less. The t ot al noise at t he ADC is composed of t he noise of t he input
signal, t he effect ive input noise of t he ADC, and an addit ional component caused by
2
3
t he effect s of t he sampling clock jit t er . In most cases, t he r ms value of t he t ot al ADC
input noise is gr eat er t han 1/2 LSB.
THE ADDITION OF WIDEBAND GAUSSIAN NOISE
TO THE ADC INPUT RANDOMIZES QUANTIZATION
NOISE AND REMOVES INPUT SIGNAL DEPENDENCE
Figure 5.28
EFFECT OF ADC LI NEARI TY AND RESOLUTI ON ON SFDR
AND NOI SE I N DI GI TAL SP ECTRAL ANALYSI S
AP P LI CATI ONS
In or der t o under st and t he r elat ionships bet ween ADC r esolut ion, noise, and
Spur ious Fr ee Dynamic Range (SFDR), it is fir st necessar y t o r eview t he some of t he
issues r elat ing t o digit al spect r al analysis, specifically t he FFT. The FFT t akes a
discr et e number of t ime samples, M, and conver t s t hem int o M/2 discr et e spect r al
component s. The spacing bet ween t he spect r al lines is Delt a f = f
s
/M. When a full
scale sinewave signal is applied t o an ADC having a r esolut ion of N bit s, t he
t heor et ical r ms signal t o r ms noise r at io is 6.02N + 1.76dB. If t he quant izat ion noise
is uncor r elat ed wit h t he signal, it appear s as gaussian noise spr ead unifor mly over
t he bandwidt h dc t o f
s
/2. The FFT act s as a nar r owband filt er wit h a bandwidt h of
Delt a f, and t he FFT noise floor is t her efor e 10log
10
(M/2) dB below t he br oadband
quant izat ion noise level (6.02N + 1.76dB). The FFT noise floor is pushed down by
3dB each t ime t he FFT r ecor d lengt h, M, is doubled (see Figur e 5.29). This r educt ion
in t he noise floor is t he same effect achieved by nar r owing t he bandwidt h of an
analog spect r um analyzer t o a bandwidt h of f
s
/M.
For example, a 4096 point FFT has a noise floor which is 33dB below t he t heor et ical
br oadband r ms quant izat ion noise floor of 74dB for a 12-bit ADC as shown in Figur e
5.30 (wher e t he aver age noise floor is about 74 + 33 = 107dB below full scale). Not ice
t hat t her e ar e r andom peaks and valleys ar ound t he aver age FFT noise floor . These
2
4
peaks (due t o quant izat ion noise, FFT ar t ifact s, and r oundoff er r or ) limit t he ideal
SFDR t o about 92dBc.
RELATIONSHIP BETWEEN AVERAGE NOISE IN FFT BINS
AND BROADBAND RMS QUANTIZATION NOISE LEVEL
Figure 5.29
2
5
NOISE FLOOR FOR AN IDEAL 12-BIT ADC
USING 4096-POINT FFT
Figure 5.30
Appr oximat ely t he same dynamic r ange could be achieved by r educing t he r esolut ion
of t he ADC t o 11 bit s and using a 16,384 point FFT. Ther e is a t r adeoff, however ,
because lower r esolut ion ADCs t end t o have quant izat ion noise which is cor r elat ed
t o t he input signal, t her eby pr oducing lar ger fr equency spur s. Aver aging t he r esult s
of sever al FFTs will t end t o smoot h out t he FFT noise floor , but does not hing t o
r educe t he aver age noise floor .
Using mor e bit s impr oves t he SFDR only if t he ADC AC linear it y impr oves wit h t he
addit ional bit s. For inst ance, t her e would be lit t le advant age in using a 14-bit ADC
which has only 12-bit linear it y. The ext r a bit s would only ser ve t o slight ly r educe t he
over all noise floor , but t he impr ovement in SFDR would be only mar ginal.
FUTURE TRENDS I N UNDERSAMP LI NG ADCS
Fut ur e ADCs specifically designed for under sampling applicat ions will incor por at e
t he pr eviously discussed t echniques in a single-chip designs. These ADCs will be
char act er ized by t heir wide SFDR at input fr equencies ext ending well above t he
Nyquist limit , f
s
/2. The basic ar chit ect ur e of t he digit al IF r eceiver is shown in
Figur e 5.31. The addit ion of a low-dist or t ion PGA under DSP cont r ol incr eases t he
dynamic r ange of t he syst em. IF fr equencies associat ed wit h 900MHz digit al cellular
base st at ions ar e t ypically ar ound 70MHz wit h bandwidt hs bet ween 5 and 10MHz.
SFDR r equir ement s ar e bet ween 70 and 80dBc. On t he ot her hand, 1.8GHZ digit al
r eceiver s t ypically have IF fr equencies bet ween 200 and 240MHz wit h bandwidt hs of
1MHz. SFDR r equir ement s ar e t ypically 50dBc.
2
6
DIRECT IF TO DIGITAL RECEIVER USING PGA
TO INCREASE SYSTEM DYNAMIC RANGE
Figure 5.31
The bandpass sigma-delt a ar chit ect ur e offer s int er est ing possibilit ies in t his ar ea.
Tr adit ional sigma-delt a ADCs cont ain int egr at or s, which ar e lowpass filt er s. They
have passbands which ext end fr om DC, and t he quant izat ion noise is pushed up int o
t he higher fr equencies. At pr esent , all commer cially available sigma-delt a ADCs ar e
of t his t ype (alt hough some which ar e int ended for use in audio or
t elecommunicat ions cont ain bandpass filt er s t o eliminat e any DC r esponse).
Ther e is no par t icular r eason why t he filt er s of t he sigma-delt a modulat or should be
lowpass filt er s, except t hat t r adit ionally ADCs have been t hought of as being
baseband devices, and t hat int egr at or s ar e somewhat easier t o const r uct t han
bandpass filt er s. If we r eplace t he int egr at or s in a sigma-delt a ADC wit h bandpass
filt er s as shown in Figur e 5.32, t he quant izat ion noise is moved up and down in
fr equency t o leave a vir t ually noise-fr ee r egion in t he passband (see Figur e 5.33). If
t he digit al filt er is t hen pr ogr ammed t o have it s passband in t his noise-fr ee r egion,
we have a sigma-delt a ADC wit h a bandpass, r at her t han a lowpass char act er ist ic.
2
7
REPLACING INTEGRATORS WITH BANDPASS
FILTERS GIVES A BANDPASS SIGMA-DELTA ADC
Figure 5.32
NOISE SHAPING FUNCTIONS FOR TRADITIONAL AND
BANDPASS SIGMA-DELTA ADCs
Figure 5.33
The t heor y is st r aight for war d, but t he development of a sigma-delt a ADC is
expensive, and t her e is no univer sal agr eement on ideal char act er ist ics for such a
bandpass sigma-delt a ADC, so developing such a conver t er fr om scr at ch t o ver ify t he
t heor y would be unlikely t o yield a commer cial pr oduct . Resear cher s at Analog
Devices and t he Univer sit y of Tor ont o (See Refer ences 16, 17, and 18) have t her efor e
modified a commer cial baseband (audio) sigma-delt a ADC chip by r ewir ing it s
int egr at or s as swit ched capacit or bandpass filt er s and r epr ogr amming it s digit al
2
8
filt er and decimat or . This has pr ovided a fast , and compar at ively inexpensive, pr oof
of t he concept , but at t he expense of r elat ive low Effect ive Bit s (11-bit s), t he r esult of
less t han ideal bandpass filt er s. Never t heless t he r esult s ar e ext r emely encour aging
and open t he way t o t he design of pur pose-built bandpass sigma-delt a ADC chips for
specific ASIC applicat ions, especially, but not exclusively, r adio r eceiver s.
The over all per for mance char act er ist ics of t he exper iment al ADC ar e shown in
Figur e 5.34. The device was designed t o digit ize t he popular r adio IF fr equency of
455kHz.
SUMMARY OF RESULTS FOR EXPERIMENTAL
BANDPASS SIGMA-DELTA ADC
Center Frequency: 455kHz
Bandwidth: 10kHz
Sampling Rate: 1.852MSPS
Oversampling Ratio: 91
SNR in Specified Band: 65dB
Supply: 5V, Power: 750mW
Process: 3 m CMOS, Active Area: 1.8 x 3.4 mm
Figure 5.34
In t he fut ur e it may be possible t o have such bandpass sigma-delt a ADCs wit h user -
pr ogr ammable digit al filt er coefficient s, so t hat t he passband of a r eceiver could be
modified dur ing oper at ion in r esponse t o t he char act er ist ics of t he signal (and t he
int er fer ence!) being r eceived. Such a funct ion is ver y at t r act ive, but difficult t o
implement , since it would involve loading, and st or ing, sever al hundr eds or even
t housands of 16-22 bit filt er coefficient s, and would consider ably incr ease t he size,
and cost , of t he conver t er .
A feat ur e which could be added compar at ively easily t o a sigma-delt a ADC is a mor e
complex digit al filt er wit h separ at e r efer ence (I) and quadr at ur e (Q) out put s. Such a
feat ur e would be most valuable in many t ypes of r adio r eceiver s.
Technology exist s t oday which should allow t he bandpass sigma-delt a ar chit ect ur e
t o achieve 16-bit r esolut ion, SFDR of 70 t o 80dBc, and an effect ive t hr oughput r at e
of 10 t o 20MSPS (input sampling r at e = 100MSPS, cor r esponding t o an
over sampling r at io of 5 t o 10). This would allow 40MHz IF wit h a 2MHz bandwidt h
t o be digit ized dir ect ly.
2
9
CHARACTERISTICS OF A BANDPASS SIGMA-DELTA
ADC DESIGN FOR IF-SAMPLING
IF Frequency: 40 to 70MHz
Signal Bandwidth: 2MHz
Input Sampling Rate: 100MSPS
Output Data Rate: 10 to 20MSPS
Process: BiCMOS
Figure 5.35
EFFECTS OF SAMP LI NG CLOCK J I TTER I N
UNDERSAMP LI NG AP P LI CATI ONS
The effect s of sampling clock jit t er on Signal-t o-Noise Rat io (SNR) and Effect ive Bit
(ENOB) per for mance discussed in Sect ion 3 ar e even mor e dr amat ic in
under sampling applicat ions because of t he higher input signal fr equencies. Figur e
5.36 shows t he r elat ionship bet ween sampling clock jit t er and SNR pr eviously
pr esent ed.
Consider t he case wher e t he IF fr equency is 70MHz, and 12-bit dynamic r ange is
r equir ed (70 t o 80dB). Fr om Figur e 5.36, t he r ms sampling clock jit t er r equir ed t o
maint ain t his SNR is appr oximat ely 1ps r ms. This assumes an ideal ADC wit h no
int er nal aper t ur e jit t er . ADC aper t ur e jit t er combines wit h t he sampling clock jit t er
in an r ms manner t o fur t her degr ade t he SNR.
SNR DUE TO SAMPLING CLOCK JITTER (t
j
)
Figure 5.36
3
0
The implicat ions of t his analysis ar e ext r emely impor t ant in under sampling
applicat ions. The ADC aper t ur e jit t er must be minimal, and t he sampling clock
gener at ed fr om a low phase-noise quar t z cr yst al oscillat or . Fur t her mor e, t he
oscillat or should use discr et e bipolar and FET devices in t he cir cuit s r ecommended
by t he cr yst al manufact ur er s. The popular oscillat or design which uses a r esist or ,
one or mor e logic gat es, a quar t z cr yst al, and a couple of capacit or s should never be
used! For ver y high fr equency clocks, a sur face acoust ic wave (SAW) oscillat or is
pr efer able.
SAMPLING CLOCK OSCILLATORS
Figure 5.37
The sampling clock should be isolat ed as much as possible fr om t he noise pr esent in
t he digit al par t s of t he syst em. Ther e should be few or no logic gat es in t he sampling
clock pat h, as a single ECL gat e has appr oximat ely 4ps r ms t iming jit t er . The
sampling clock gener at ion cir cuit r y should be on separ at e chips, per haps wit h
separ at ely decoupled power supplies, fr om t he r emainder of t he digit al syst em, and
t he sampling clock signal lines should not be locat ed wher e t hey can pick up digit al
noise fr om t he r est of t he syst em. All sampling clock cir cuit r y should be gr ounded
and decoupled t o t he analog gr ound plane, as would be t he case for a cr it ical analog
component .
Of cour se, t he sampling clock is it self a digit al signal. It has as much pot ent ial for
causing noise in t he analog par t of t he syst em as any ot her digit al signal. We
t her efor e see t hat a sampling clock is ver y inconvenient , as it must be isolat ed fr om
bot h t he analog and digit al par t s of t he syst em.
Because t he sampling clock jit t er is wideband and t her efor e cr eat es wideband
r andom noise, digit al filt er ing can be used t o r educe it s effect s in a syst em. In t he
case of an FFT, however , doubling t he FFT r ecor d lengt h r educes t he noise floor by
only 3dB.
This discussion illust r at es t he basic fact t hat under sampling syst ems have
fundament al limit at ions wit h r espect t o t heir abilit y t o pr ocess wide dynamic r ange
br oadband signals, and syst em t r adeoffs bet ween br oadband and nar r owband
appr oaches must ult imat ely be made in t he design of such syst ems.
3
1
SAMPLING CLOCK NOISE
Low phase-noise crystal (or SAW) oscillators mandatory in high
frequency undersampling applications
Ground and decouple sampling clock circuitry to the Analog
Ground Plane!
Route sampling clock away from digital and analog signals
Digital filtering techniques can be used to reduce the effects of
sampling clock phase noise
Sampling clock noise can ultimately dictate the tradeoffs
between broadband and narrowband digital receivers
Figure 5.38
3
2
REFERENCES
1. Syst em Ap p li ca t i on s Gu i d e, Analog Devices, 1993, Chapt er 15.
2. Richar d Gr oshong and St ephen Ruscak, Undersampling Techniques
S implify Digital Radio, Elect r on i c Desi gn , May 23, 1991, pp. 67-78.
3. Richar d Gr oshong and St ephen Ruscak, Exploit Digital Advantages
In An S S B Receiver, Elect r on i c Desi gn , J une 13, 1991, pp. 89-96.
4. Richar d G. Lyons, How Fast Must You S ample?, Test a n d Mea su r emen t
Wor ld , November , 1988, pp. 47-57.
5. Richar d C. Webb, IF S ignal S ampling Improves Receiver Detection
Accuracy, Mi cr owa ves a n d RF, Mar ch, 1989, pp. 99-103.
6. J eff Kir st en and Tar lt on Fleming, Undersampling Reduces
Data-Acquisition Costs For S elect Applications, EDN, J une 21, 1990,
pp 217-228.
7. Hans St eyskal and J ohn F. Rose, Digital Beamforming For Radar
S ystems, Mi cr owa ve J ou r n a l, J anuar y, 1989, pp. 121-136.
8. Tom Gr at zek and Fr ank Mur den, Optimize ADCs For Enhanced
S ignal Processing, Mi cr owa ves a n d RF, Vol. 30, No.3, Mar ch, 1991,
pp. 129-136.
9. Howar d Hilt on, 10-MHz ADC With 110dB Linearity, Hi gh Sp eed ADC
Con fer en ce, Las Vegas, Apr il 21-22, 1992.
10. Howar d Hilt on, 10MS ample/ S econd ADC With Filter And Memory, Hi gh
Sp eed ADC Con fer en ce, Las Vegas, Apr il 21-22, l992.
11. Dan Ast a, Recent Dynamic Range Characterization of Analog-to-Digital
Converters for S pectral Analysis Applications, P r oject Rep or t AST-14,
MIT Lincoln Labor at or y, Lexingt on, MA, J uly 9, 1991.
12. Fr ed H. Ir ons and T.A. Rebold, Characterization of High-Frequency
Analog-to-Digital Converters for S pectral Analysis Applications, P r oject
Rep or t AST-2, MIT Lincoln Labor at or y, November 28, 1986.
13. F. H. Ir ons, Dynamic Characterization and Compensation of Analog-to-
Digital Converters, I EEE I n t er n a t i on a l Symp osi u m on Ci r cu i t s a n d
Syst ems, May 1986, San J ose, CA. Cat alog No. CH2255-8/86/0000-1273.
14. T.A. Rebold and F. H. Ir ons, A Phase-Plane Approach to the Compensation
of High-S peed Analog-to-Digital Converters, I EEE I n t er n a t i on a l
Symp osi u m on Ci r cu i t s a n d Syst ems, Philadelphia, PA, May, 1987.
3
3
15. Dan Ast a and Fr ed H. Ir ons, Dynamic Error Compensation of Analog-to-
Digital Converters, Th e Li n coln La bor a t or y J ou r n a l, Vol. 2, No. 2, 1989,
pp. 161-182.
16. J ames M. Br yant , Bandpass S igma-Delta ADCs for Direct IF Conversion,
DSP - Th e En a bli n g Tech n ology for Commu n i ca t i on s, RAI
Congr escent r um, Amst er dam, Net her lands, 9-10 Mar ch 1993.
17. S.A. J ant zi, M. Snelgr ove, P.F. Fer guson, J r ., A 4th-Order Bandpass
S igma-Delta Modulator, P r oceed i n gs of t h e I EEE 1992 Cu st om
I n t egr a t ed Ci r cu i t s Con fer en ce, pp. 16.5.1-4.
18. S.A. J ant zi, R. Schr eier , and M. Snelgr ove, A Bandpass S igma-Delta
Convertor for a Digital AM Receiver, P r oceed i n gs of t h e I EE
I n t er n a t i on a l Con fer en ce on An a logu e-t o-Di gi t a l a n d Di gi t a l-t o-
An a logu e Con ver si on , Swansea, UK., Sept ember , 1991, pp. 75-80.
19. S.A. J ant zi, W. Mar t in Snelgr ove, and Paul F. Fer guson, J r ., A Fourth-
Order Bandpass S igma-Delta Modulator, I EEE J ou r n a l of Soli d -St a t e
Ci r cu i t s, Vol. 38, No. 3, Mar ch 1993, pp. 282-291.
20. Bar r ie Gilber t , A Low Noise Wideband Variable-Gain Amplifier Using
an Interpolated Ladder Attenuator, I EEE I SSCC Tech n i ca l Di gest ,
1991, pages 280, 281, 330.
21. Bar r ie Gilber t , A Monolithic Microsystem for Analog S ynthesis of
Trigonometric Functions and their Inverses, I EEE J ou r n a l of Soli d
St a t e Ci r cu i t s, Vol. SC-17, No. 6, December 1982, pp. 1179-1191.
22. 1992 Amp li fi er Ap p li ca t i on s Gu i d e, Analog Devices, Nor wood MA,
1992.
23. Car l Mor eland, An 8-Bit 150MS PS S erial ADC, 1995 I SSCC Di gest of
Tech n i ca l P a p er s, Vol. 38, pp. 272.
24. Roy Gosser and Fr ank Mur den, A 12-Bit 50MS PS Two-S tage A/ D
Converter, 1995 I SSCC Di gest of Tech n i ca l P a p er s, p. 278.
1
SECTION 6
MULTICHANNEL APPLICATIONS
Data Acquisition System Considerations
Multiplexing
Filtering Considerations for Data Acquisition Systems
SHA and ADC Settling Time Requirements in
Multiplexed Applications
Complete Data Acquisition Systems on a Chip
Multiplexing into Sigma-Delta ADCs
Simultaneous Sampling Systems
Data Distribution Systems using Multiple DACs
2
SECTI ON 6
MULTI CHANNEL AP P LI CATI ONS
Wa l t Kest er , Wes Fr eem a n
DATA ACQUI SI TI ON SYSTEM CONFI GURATI ONS
Ther e ar e many applicat ions for dat a acquisit ion syst ems in measur ement and
pr ocess cont r ol. All dat a acquisit ion applicat ions involve digit izing analog signals for
analysis using ADCs. In a measur ement applicat ion, t he ADC is followed by a digit al
pr ocessor which per for ms t he r equir ed dat a analysis. In a pr ocess cont r ol
applicat ion, t he pr ocess cont r oller gener at es feedback signals which t ypically must
be conver t ed back int o analog for m using a DAC.
Alt hough a single ADC digit izing a single channel of analog dat a const it ut es a dat a
acquisit ion syst em, t he t er m data acquisition gener ally r efer s t o mult i-channel
syst ems. If t her e is feedback fr om t he digit al pr ocessor , DACs may be r equir ed t o
conver t t he digit al r esponses int o analog. This pr ocess is oft en r efer r ed t o as data
distribution.
Figur e 6.1 shows a dat a acquisit ion/dist r ibut ion pr ocess cont r ol syst em wher e each
channel has it s own dedicat ed ADC and DAC. An alt er nat ive configur at ion is shown
in Figur e 6.2, wher e analog mult iplexer s and demult iplexer s ar e used wit h a single
ADC and DAC. In most cases, especially wher e t her e ar e many channels, t his
configur at ion pr ovides an economical alt er nat ive.
DATA ACQUISITION SYSTEM
USING ADC / DAC PER CHANNEL
Figure 6.1
3
DATA ACQUASITION SYSTEM USING ANALOG
MULTIPLEXING / DEMULTIPLEXING AND SINGLE ADC / DAC
Figure 6.2
Ther e ar e many t r adeoffs involved in designing a dat a acquisit ion syst em. Issues
such as filt er ing, amplificat ion, mult iplexing, demult iplexing, sampling fr equency,
and par t it ioning must be r esolved.
MULTI P LEXI NG
Mult iplexing is a fundament al par t of a dat a acquisit ion syst em. Mult iplexer s and
swit ches ar e examined in mor e det ail in Refer ence 1, but a fundament al
under st anding is r equir ed t o design a dat a acquisit ion syst em. A simplified diagr am
of an analog mult iplexer is shown in Figur e 6.3. The number of input channels
t ypically r anges fr om 4 t o 16, and t he devices ar e gener ally fabr icat ed on CMOS
pr ocesses. Some mult iplexer s have int er nal channel-addr ess decoding logic and
r egist er s, while wit h ot her s, t hese funct ions must be per for med ext er nally. Unused
mult iplexer input s must be gr ounded or sever e loss of syst em accur acy may r esult .
The key specificat ions ar e switching time, on-resistance, on-resistance modulation,
and off-channel isolation (crosstalk). Mult iplexer swit ching t ime r anges fr om about
50ns t o over 1µs, on-r esist ance fr om 25ohms t o sever al hundr ed ohms, and off-
channel isolat ion fr om 50 t o 90dB. The use of t r ench isolat ion has eliminat ed lat ch-
up in mult iplexer s while yielding impr ovement s in speed at low supply volt ages.
4
SIMPLIFIED DIAGRAM OF A
TYPICAL ANALOG MULTIPLEXER
Figure 6.3
MULTIPLEXER KEY SPECIFICATIONS
Switching Time: 50ns to >1 s
On-Resistance: 25 to hundreds of ’s
On-Resistance Modulation (Ron change with signal level)
Off-Channel Isolation: 50 to 90 dB
Overvoltage Protection
Figure 6.4
5
WHAT’S NEW IN MULTIPLEXERS?
Trench Isolation gives high speed, latch-up protection, and low-
voltage operation
ADG511, ADG512, ADG513: +3.3V, +5V, 5V specified
Ron < 50 @ 5V
Switching Time: <200ns @ 5V

ADG411, ADG412, ADG413: 15V, +12V specified
Ron < 35 @
15V Switching Time: <150ns @ 15V
ADG508F, ADG509F, ADG528F: 15V specified
Ron < 300
Switching Time: < 250ns
Fault-Protection on Inputs and Outputs
Figure 6.5
Mult iplexer on-r esist ance is gener ally slight ly dependent on t he signal level (oft en
called R
on
modulat ion). This will cause signal dist or t ion if t he mult iplexer must
dr ive a load r esist ance, t her efor e t he mult iplexer out put should t her efor e be isolat ed
fr om t he load wit h a suit able buffer amplifier . A separ at e buffer is not r equir ed if
t he mult iplexer dr ives a high input impedance, such as a PGA, SHA or ADC - but
bewar e! Some SHAs and ADCs dr aw high fr equency pulse cur r ent at t heir sampling
r at e and cannot t oler at e being dr iven by an unbuffer ed mult iplexer . A det ailed
analysis of mult iplexer s can be found in Refer ence 1, Sect ion 8, or Refer ence 2,
Sect ion 2.
An M-channel mult iplexed dat a acquisit ion syst em is shown in Figur e 6.6. The
mult iplexer out put dr ives a PGA whose gain can be adjust ed on a per -channel basis
depending on t he channel signal level. This ensur es t hat all channels ut ilize t he full
dynamic r ange of t he ADC. The PGA gain is changed at t he same t ime as t he
mult iplexer is swit ched t o a new channel. The ADC Convert Command is applied
aft er t he mult iplexer and t he PGA have set t led t o t he r equir ed accur acy (1LSB). The
maximum sampling fr equency (when swit ching bet ween channels) is limit ed by t he
mult iplexer swit ching t ime t
mux
, t he PGA set t ling t ime t
pga
, and t he ADC
conver sion t ime t
conv
as shown in t he for mula.
6
MULTIPLEXED DATA AQUISITION
SYSTEM WITH PGA AND SAR ADC
Figure 6.6
In a mult iplexed syst em it is possible t o have a posit ive fullscale signal on one
channel and a negat ive fullscale signal on t he ot her . When t he mult iplexer swit ches
bet ween t hese channels it s out put is a fullscale st ep volt age. All element s in t he
signal pat h must set t le t o t he r equir ed accur acy (1LSB) befor e t he conver sion is
made. The effect of inadequat e set t ling is dc cr osst alk bet ween channels.
The SAR ADC chosen in t his applicat ion has no int er nal SHA (similar t o t he
indust r y-st andar d AD574-ser ies), and t her efor e t he input signal must be held
const ant (wit hin 1LSB) dur ing t he conver sion t ime in or der t o pr event encoding
er r or s. This defines t he maximum r at e-of-change of t he input signal:
dv
dt
LSB
t
conv
max

1
The amplit ude of a fullscale sinewave input signal is equal t o (2^N)/2, or 2^(N-1),
and it s maximum r at e-of change is

dv
dt
max
2 f
max
2
N 1
f
max
2
N
= ⋅

= ⋅ π π
Set t ing t he t wo equat ions equal, and solving for f
max
,
f
N
t
conv
max


1
2 π
For example, if t he ADC conver sion t ime is 20µsec (cor r esponding t o a maximum
sampling r at e of slight ly less t han 50kSPS), and t he r esolut ion is 12-bit s, t hen t he
7
maximum channel input signal fr equency is limit ed t o 4Hz. This may be adequat e if
t he signals ar e DC, but t he lack of a SHA funct ion sever ely limit s t he abilit y t o
pr ocess dynamic signals.
Adding a SHA funct ion t o t he ADC as shown in Figur e 6.7 allows pr ocessing of much
fast er signals wit h almost no incr ease in syst em complexit y, since sampling ADCs
such as t he AD1674 have t he SHA funct ion on-chip.
THE ADDITION OF A SHA FUNCTION TO THE ADC
ALLOWS PROCESSING OF DYNAMIC INPUT SIGNALS
Figure 6.7
TYPICAL TIMING DIAGRAM FOR
MULTIPLEXED DATA ACQUISITION SYSTEM USING SHA
Figure 6.8
The t iming is adjust ed such t hat t he mult iplexer and t he PGA ar e swit ched
immediat ely following t he acquisit ion t ime of t he SHA. If t he combined mult iplexer
and PGA set t ling t ime is less t han t he ADC conver sion t ime (see Figur e 6.8), t hen
t he maximum sampling fr equency of t he syst em is given by:
8
f
s
t
acq
t
conv

+
1
The AD1674 has a conver sion t ime of 9µs, an acquisit ion t ime of 1µs t o 12-bit s, and a
sampling r at e of 100kSPS is possible, if all t he channels ar e addr essed. The per -
channel sampling r at e is obt ained by dividing t he ADC sampling r at e by M.
FI LTERI NG CONSI DERATI ONS I N DATA ACQUI SI TI ON
SYSTEMS
Filt er ing in dat a acquisit ion syst ems not only pr event s aliasing of unwant ed signals
but also r educes noise by limit ing bandwidt h. In a mult iplexed syst em, t her e ar e
basically t wo places t o put filt er s: in each channel, and at t he mult iplexer out put .
FILTERING IN A DATA ACQUISITION SYSTEM
Figure 6.9
The filt er at t he input of each channel is used t o pr event aliasing of signals which
fall out side t he Nyquist bandwidt h. The per -channel sampling r at e (assuming each
channel is sampled at t he same r at e) is f
s
/M, and t he cor r esponding Nyquist
fr equency is f
s
/2M. The filt er should pr ovide sufficient at t enuat ion at f
s
/2M t o
pr event dynamic r ange limit at ions due t o aliasing.
A second filt er can be placed in t he signal pat h bet ween t he mult iplexer out put and
t he ADC, usually bet ween t he PGA and t he SHA. The cut off fr equency of t his filt er
must be car efully chosen because of it s impact on set t ling t ime. In a mult iplexed
syst em such as shown in Figur e 6.7, t her e can be a fullscale st ep volt age change at
t he mult iplexer out put when it is swit ched bet ween channels. This occur s if t he
signal on one channel is posit ive fullscale, and t he signal on t he adjacent channel is
negat ive fullscale. Fr om t he t iming diagr am shown in Figur e 6.8, t he signal fr om t he
filt er has essent ially t he ent ir e conver sion per iod (1/f
s
) t o set t le fr om t he st ep
volt age. The signal should set t le t o wit hin 1LSB of t he final value in or der not t o
int r oduce a significant er r or . The set t ling t ime r equir ement t her efor e places a lower
limit on t he filt er 's cut off fr equency. The single-pole filt er set t ling t ime r equir ed t o
maint ain a given accur acy is shown in Figur e 6.10. The set t ling t ime r equir ement is
9
expr essed in t er ms of t he filt er t ime const ant and also t he r at io of t he filt er cut off
fr equency, f
c2
,t o t he ADC sampling fr equency, f
s
.
SINGLE-POLE FILTER SETTLING
TIME TO REQUIRED ACCURACY
Figure 6.10
As an example, assume t hat t he ADC is a 12-bit one sampling at 100kSPS. Fr om t he
t able in Figur e 6.10, 8.32 t ime const ant s ar e r equir ed for t he filt er t o set t le t o 12-bit
accur acy, and
f
c
f
s
2
132 ≥ . , or f
c2
≥ 132kSPS.
While t his filt er will help pr event wideband noise fr om ent er ing t he SHA, it does not
provide the same function as the antialiasing filters at the input of each channel.
The above analysis assumes t hat t he mult iplexer /PGA combined set t ling t ime is
significant ly less t han t he filt er set t ling t ime. If t his is not t he case, t hen t he filt er
cut off fr equency must be lar ger , and in most cases it should be left out ent ir ely in
favor of per -channel filt er s.
SHA AND ADC SETTLI NG TI ME REQUI REMENTS I N
MULTI P LEXED AP P LI CATI ONS
We have discussed t he impor t ance of t he fullscale set t ling t ime of t he
mult iplexer /PGA/filt er combinat ion, but what is equally impor t ant is t he abilit y of
t he ADC t o acquir e t he final value of t he st ep volt age input signal t o t he r equir ed
accur acy. Failur e of any link in t he signal chain t o set t le will r esult in dc cr osst alk
bet ween adjacent channels and loss of accur acy. If t he dat a acquisit ion syst em uses
a separ at e SHA and ADC, t hen t he key specificat ion t o examine is t he SHA
acquisition time, which is usually specified as a t he amount of t ime r equir ed t o
acquir e a fullscale input signal t o 0.1% accur acy (10-bit s) or 0.01% accur acy (13-
1
0
bit s). In most cases, bot h 0.1% and 0.01% t imes ar e specified. If t he SHA acquisit ion
t ime is not specified for 0.01% accur acy or bet t er , it should not be used in a 12-bit
mult iplexed applicat ion.
If t he ADC is a sampling one (wit h int er nal SHA), t he SHA acquisit ion t ime
r equir ed t o achieve a level of accur acy may st ill be specified, as in t he case of t he
AD1674 (1µs t o 12-bit accur acy). SHA acquisit ion t ime and accur acy ar e not dir ect ly
specified for some sampling ADCs, so t he transient response specificat ion should be
examined. The t r ansient r esponse of t he ADC (set t ling t ime t o wit hin 1 LSB for a
fullscale st ep input ) must be less t he 1/f
s
, wher e f
s
is t he ADC sampling r at e. This
oft en ignor ed specificat ion may become t he weakest link in t he signal chain. In some
cases neit her t he SHA acquisit ion t ime t o specified accur acy nor t he t r ansient
r esponse specificat ion may appear on t he dat a sheet for t he par t icular ADC, in
which case it is pr obably not accept able for mult iplexed applicat ions. Because of t he
difficult y in measur ing and achieving bet t er t han 12-bit set t ling t imes using discr et e
component s, t he accur acy of most mult iplexed dat a acquisit ion syst ems is limit ed t o
12-bit s. Designing mult iplexed syst ems wit h gr eat er accur acy is ext r emely difficult ,
and using a single ADC per channel should be st r ongly consider ed at higher
r esolut ions.
SHA AND ADC CONSIDERATIONS IN
MULTIPLEXED DATA ACQUISITION SYSTEMS
Examine SHA Acquisition Time Specification to Required
Accuracy:

0.1% = 10-bits
0.01% = 13-bits

If Sampling ADC, SHA Acquisition Time may not be given, so
examine Transient Response Specification

Inadequate Settling Results in Loss of Accuracy and Causes DC
Crosstalk Between Channels

Multiplexing at greater than 12-bits Accuracy, or at Video Speeds
is Extremely Difficult!
Figure 6.11
COMP LETE DATA ACQUI SI TI ON SYSTEMS ON A CHI P
VLSI mixed-signal pr ocessing allows t he int egr at ion of lar ge and complex dat a
acquisit ion cir cuit s on a single chip. Most signal condit ioning cir cuit s including
mult iplexer s, PGAs, and SHAs, may now be manufact ur ed on t he same chip as t he
ADC. This high level of int egr at ion per mit s dat a acquisit ion syst ems t o be specified
and t est ed as a single complex funct ion.
Such funct ionalit y r elieves t he designer of most of t he bur den of t est ing and
calculat ing er r or budget s. The DC and AC char act er ist ics of a complet e dat a
1
1
acquisit ion syst em ar e specified as a complet e funct ion, which r emoves t he necessit y
of calculat ing per for mance fr om a collect ion of individual wor st case device
specificat ions. A complet e monolit hic syst em should achieve a higher per for mance at
much lower cost t han would be possible wit h a syst em built up fr om discr et e
funct ions. Fur t her mor e, syst em calibr at ion is easier and in fact many monolit hic
DASs ar e self calibr at ing.
Wit h t hese high levels of int egr at ion, it is bot h easy and inexpensive t o make many
of t he par amet er s of t he device pr ogr ammable. Par amet er s which can be
pr ogr ammed include gain, filt er cut off fr equency, and even ADC r esolut ion and
conver sion t ime, as well as t he obvious digit al/MUX funct ions of input channel
select ion, out put dat a for mat , and unipolar /bipolar r ange.
The AD7890 is an example of a highly int egr at ed monolit hic dat a acquisit ion
syst em. It has 8 mult iplexed input channels, a SHA, an int er nal volt age r efer ence,
and a fast 12-bit ADC. Input scaling allows up t o ±10V input s when oper at ing on a
single +5V supply. It s block diagr am is shown in Figur e 6.12, and key specificat ions
ar e summar ized in Figur e 6.13. Bot h AC and DC par amet er s ar e fully specified,
simplifying t he pr epar at ion of an er r or budget , and t hr ee t ypes ar e available wit h
t hr ee differ ent st andar d input r anges:-
AD7890-10 ±10 V
AD7890-5 0 t o 5V
AD7890-2 0 t o +2.5V
AD7890 8-CHANNEL, 12-BIT, 100kSPS
COMPLETE DATA ACQUISITION SYSTEM
Figure 6.12
1
2
AD7890 SPECIFICATIONS
ADC Conversion Time: 5.9 s
SHA Acquisition Time: 2 s
117kSPS Throughput Rate (Includes 0.6 s Overhead)
AC and DC Specifications
Single +5V Operation
Low Power Drain:

Operational: 30mW
Power Down Mode 1mW

Standard Input Ranges

AD7890 - 10: 10V
AD7890 - 5: 0 to +5V
AD7890 - 2: 0 to +2.5V
Figure 6.13
The input channel select ion is via a ser ial input por t . A t ot al of 5 bit s of dat a cont r ol
t he AD7890 via a ser ial por t :- 3 addr ess bit s select t he input channel, a
CONV bit st ar t s t he A-D conver sion, and 1 in t he STBY r egist er places t he device in
a power -down mode wher e it s power consumpt ion is under 1mW. All t iming t akes
place on t he chip and a single ext er nal capacit or cont r ols t he acquisit ion t ime of t he
int er nal t r ack-and-hold. A-D conver sion may also be init iat ed ext er nally using t he
CONVST pin.
Wit h t he ser ial clock r at e at it s maximum of 10MHz, t he achievable t hr oughput r at e
for t he AD7890 is 5.9µs (conver sion t ime) plus 0.6µs (six ser ial clocks of int er nal
over head) plus 2µs (acquisit ion t ime). This r esult s in a minimum t hr oughput t ime of
8.5µs (equivalent t o a t hr oughput r at e of 117kSPS). The AD7890 dr aws 30mW fr om
a +5V supply.
The ent ir e family of AD789X 12-bit dat a acquisit ion ADCs is shown in Figur e 6.14.
The AD7890 and AD7891 ar e complet e 8-channel dat a acquisit ion syst ems, while
t he AD7892, AD7893, and AD7896 ar e designed for use on a single channel, or wit h
an ext er nal mult iplexer .
1
3
AD789X SERIES OF 12-BIT ADCs FOR DATA ACQUISITION
Figure 6.14
The AD785X 12-bit low power dat a acquisit ion ADCs have been designed and fully
specified for eit her +3V or +5V oper at ion. This family includes par allel and ser ial
single and 8-channel ver sions. The devices have self or syst em calibr at ion modes for
offset , gain, and t he int er nal SAR DAC.
AD785X SERIES OF 3V / 5V 12-BIT ADCs
Figure 6.15
MULTI P LEXI NG I NP UTS TO SI GMA-DELTA ADCS
As was discussed in Sect ion 3, t he digit al filt er is an int egr al par t of a sigma-delt a
ADC. When t he input t o a sigma-delt a ADC changes by a lar ge st ep, t he ent ir e
digit al filt er must fill wit h t he new dat a befor e t he out put becomes valid, which is a
slow pr ocess. This is why sigma-delt a ADCs ar e somet imes said t o be unsuit able for
mult i-channel mult iplexed syst ems - t hey ar e not inher ent ly so, but t he t ime t aken
t o change channels can be inconvenient .
As an example, t he AD7710-family of ADCs cont ains an on-chip mult iplexer (see
Figur e 6.16), and t he digit al filt er (fr equency r esponse shown in Figur e 6.17)
1
4
r equir es t hr ee conver sion cycles (300ms at a 10Hz t hr oughput r at e) t o set t le. It is
t hus possible t o mult iplex sigma-delt a conver t er s, pr ovided adequat e t ime is allowed
for t he int er nal digit al filt er t o set t le.
THE AD771X-SERIES PROVIDES A
HIGH LEVEL OF INTEGRATION IN A 24-PIN PACKAGE
Figure 6.16
AD7710 DIGITAL FILTER FREQUENCY RESPONSE
Figure 6.17
1
5
THE RATE OF CONVERSION AND
SETTLING TIME DEPENDS ON THE FILTER SETTING
Figure 6.18
In t he case of t he AD771X-ser ies, four conver sions must t ake place aft er a channel
change befor e t he out put dat a is again valid (Figur e 6.18). The SYNC input pin
r eset s t he digit al filt er and, if it is used, dat a is valid on t he t hir d out put aft er war ds,
saving one conver sion cycle. When t he int er nal mult iplexer is swit ched, t he SYNC is
aut omat ically oper at ed.
If sigma-delt a ADCs ar e used in mult i-channel applicat ions, consider using one
sigma-delt a ADC per channel as shown in Figur e 6.19. This eliminat es t he
r equir ement for an analog mult iplexer but r equir es t hat t he out put s be synchr onized
in simult aneous sampling applicat ions. Alt hough t he input s ar e sampled at t he
same inst ant at a r at e Kf
s
, t he decimat ed out put fr equency, f
s
, is gener ally der ived
int er nally in each ADC by dividing t he input sampling fr equency by K (t he
over sampling r at e). The out put dat a must t her efor e be synchr onized by t he same
clock at a fr equency f
s
.
1
6
SYNCHRONIZING MULTIPLE SIGMA-DELTA ADCs
IN SIMULTANEOUS SAMPLING APPLICATIONS
Figure 6.19
Pr oduct s such as t he AD7716 include mult iple sigma-delt a ADCs in a single IC, and
pr ovide t he synchr onizat ion aut omat ically. The AD7716 is a quad sigma-delt a ADC
wit h up t o 22-bit r esolut ion and an over -sampling r at e of 570kSPS. A funct ional
diagr am of t he AD7716 is shown in Figur e 6.20 and some of it s key feat ur es in
Figur e 6.21. The device does not have a "st ar t conver sion" cont r ol input , but samples
cont inuously. The cut off fr equency of t he digit al filt er s (which may be changed
dur ing oper at ion, but only at t he cost of a loss of valid dat a for a shor t t ime while t he
filt er s clear ) is pr ogr ammed by dat a wr it t en t o t he DAS. The out put r egist er is
updat ed at a r at e which depends on t he cut off fr equency chosen. The AD7716
cont ains an aut o-zer oing syst em t o minimize input offset dr ift .
1
7
AD7716 22-BIT QUAD SIGMA-DELTA ADC
Figure 6.20
AD7716 QUAD SIGMA-DELTA ADC KEY FEATURES
Up to 22-Bit Resolution, 4 Input Channels
Architecture, 570kSPS Oversampling Rate
On-Chip Lowpass Filter, Programmable from 36.5Hz to 584Hz
Serial Input / Output Interface
5V Power Supply Operation
Low Power: 50mW
Figure 6.21
SI MULTANEOUS SAMP LI NG SYSTEMS
Ther e ar e cer t ain applicat ions wher e it is desir able t o sample a number of channels
simult aneously such as in-phase and quadr at ur e (I and Q) signal pr ocessing. A
t ypical configur at ion is shown in Figur e 6.22. Each channel r equir es it s own filt er
and SHA. Each SHA is simult aneously placed in t he hold mode by a common
command signal. Dur ing t he input SHAs' hold t ime t he mult iplexer is sequent ially
swit ched fr om channel t o channel, and t he single non-sampling ADC is used t o
digit ize t he signal on each channel. The maximum ADC sampling r at e is t he
r ecipr ocal of t he sum of t he mult iplexer set t ling t ime, t
mux
, and t he ADC
conver sion t ime, t
conv
.
1
8
f
s
t
mux
t
conv
2
1

+
The maximum per -channel sampling fr equency is det er mined by M, t
mux
, t
conv
,
and t he acquisit ion t ime of t he simult aneous SHAs, t
acq1
.
( )
f
s
t
acq
M t
mux
t
conv
1
1
1

+ +
SIMULTANEOUSLY SAMPLED DATA ACQUISITION
SYSTEM USING NON-SAMPLING ADC
Figure 6.22
If a sampling ADC is used t o per for m t he conver sion (see Figur e 6.23), t he
acquisit ion t ime of t he second SHA, t
acq2
, must be consider ed in det er mining t he
maximum ADC sampling r at e, f
s2
. The mult iplexer should be swit ched t o t he next
channel aft er t he single SHA goes int o t he hold mode. If t he mult iplexer set t ling
t ime is less t han t he ADC conver sion t ime, t hen t he maximum ADC sampling r at e
f
s2
is t he r ecipr ocal of t he sum of t he SHA acquisit ion t ime and t he ADC conver sion
t ime.
f
s
t
acq
t
conv
2
1
2

+
The maximum input sampling fr equency is less t han t his value divided by M, wher e
M is t he number of channels. Addit ional t iming over head (t
acq1
) is r equir ed for t he
simult aneous SHAs t o acquir e t he signals.
f
s
t
acq
M t
conv
t
acq
1
1
1 2
<
+ + ( )
1
9
SIMULTANEOUS SAMPLING DATA ACQUISITION SYSTEM
USING SAMPLING ADC
Figure 6.23
USI NG MULTI P LE -DACS TO SI MP LI FY DATA DI STRI BUTI ON
SYSTEMS
Wes Fr eem a n
In many indust r ial and pr ocess cont r ol applicat ions, mult iple pr ogr ammable volt age
sour ces ar e r equir ed. Tr adit ionally, t hese applicat ions have r equir ed a lar ge number
of component s, but r ecent pr oduct development s have gr eat ly r educed t he par t s
count wit hout compr omising per for mance.
DATA DISTRIBUTION SYSTEM USING MULTIPLE DACs
Many systems require multiple, programmable voltages
Automatic Test Equipment (ATE)
Robotics
Industrial Automation
System Calibration
Ultrasound/Sonar Power Gain and Receiver Level
Figure 6.24
Mult iple volt age out put s can eit her be der ived by demult iplexing t he out put of a
single DAC or by employing mult iple DACs. These t wo appr oaches ar e shown in
Figur e 6.25. In t he demult iplexed cir cuit , one DAC feeds t he input s of sever al
sample-and-hold amplifier s (SHA). The equivalent digit al value for t he analog
out put is applied t o t he DAC, and t he appr opr iat e SHA is select ed. Aft er t he DAC
set t ling t ime and SHA acquisit ion t ime r equir ement s have been met , t he SHA can
be deselect ed and t he next channel updat ed. Once a SHA is deselect ed, t he out put
volt age will begin t o dr oop at a r at e specified for t he SHA. Thus, t he SHA must be
r efr eshed befor e t he out put volt age dr oop exceeds t he r equir ed accur acy (t ypically
1/2 LSB).
2
0
OPTIONS FOR ANALOG DATA DISTRIBUTION
Figure 6.25
The mult iple DAC applicat ion is st r aight for war d. One DAC is pr ovided for each
channel, and an addr ess decoder simply select s t he appr opr iat e DAC. No r efr esh is
r equir ed.
The DAC plus SHA syst em evolved because, in t he past , DACs wer e mor e expensive
t han SHAs. This sit uat ion was par t icular ly t r ue for DACs wit h r esolut ion above 8
bit s. In addit ion, mult iple-SHAs wit h on-chip hold capacit or s r educed t he par t s
count , pr int ed cir cuit boar d ar ea, and cost of demult iplexed DAC syst ems. Finally,
t he demult iplexed DAC only r equir es one calibr at ion st ep, since t he same DAC
pr ovides t he out put volt age for each of t he out put channels. Of cour se, single-
calibr at ion is only valid if t he SHA does not int r oduce unaccept able er r or s. For
example, t he SMP08 is an 8-channel SHA which exhibit s a 10mV maximum offset
volt age and is accur at e t o 1/2 LSB when demult iplexing an 8-bit , 5V full-scale DAC.
WHY DEMULTIPLEX A SINGLE DAC?
Cost of DAC > Cost of SHA
Multichannel SHAs (e.g. SMP-08/SMP-18)
Reduce Parts Count

Only One Calibration Required
Figure 6.26
A r epr esent at ive 16-channel, 8-bit demult iplexed dat a dist r ibut ion syst em is shown
in Figur e 6.27. The DAC8228 pr oduces a volt age out put which is applied t o t he input
of 16 SHAs. The DAC digit al value is wr it t en int o t he DAC8228 at t he same t ime as
t he channel addr ess is pr esent ed t o t he SHA. Aft er t he SHA’s acquisit ion t ime
r equir ement has been sat isfied, t he next channel can be r efr eshed. The SMP08’s
acquisit ion t ime t o 0.1% is 7µs, so t he maximum dat a t r ansfer r at e is t he r ecipr ocal
of t he acquisit ion t ime, or 140kHz.
2
1
A 16-CHANNEL 8-BIT DATA DISTRIBUTION SYSTEM
USING A SINGLE MULTIPLEXED DAC
Figure 6.27
Once a SHA channel is deselect ed, t he input bias cur r ent of t he amplifier begins t o
dischar ge t he hold capacit or . The r at e at which t he capacit or volt age changes is
specified on t he SHA dat a sheet as t he droop rate. Wit h a maximum dr oop r at e of
20mV/s, t he SMP08 can maint ain 8-bit accur acy (1/2 LSB at 5V full scale) pr ovided
r efr eshing occur s once each 500ms.
The SMP08 is a complet e, single-chip 8-channel SHA, which incor por at es analog
swit ches, hold capacit or s, amplifier s, and addr ess decoder s. Each SMP08 r eplaces 17
component s (8 SHAs, 8 hold capacit or s, and one decoder ). Even wit h t his level of
int egr at ion, however , t he complet e dat a dist r ibut ion cir cuit st ill r equir es six
component s.
Oper at ion of t he demult iplexed DAC is shown in Figur e 6.28. Wit h t he DAC out put
at 5V, t he syst em r efr eshes CH0 once each second. The upper t r ace is t he addr ess
decode out put which goes low t o select CH0. The lower t r ace is t he out put of CH0’s
SHA. While t he addr ess input is low, t he DAC’s out put is connect ed t o t he input of
CH0’s SHA. When t he addr ess input goes high, t he SMP08 maint ains less t han 1/4
LSB er r or for one second. Thus, t he dr oop r at e of t his par t icular SMP08 is about
2mV/sec. The phot o also shows a 1mV hold st ep when swit ching fr om sample t o hold
mode.
2
2
REFRESHING THE MULTIPLEXED DAC
Figure 6.28
At fir st glance, demult iplexed DAC syst ems may appear t o be mor e cost -effect ive
t han mult iple DACs. However , sever al fact or s combine t o r educe t he syst em cost
when a mult iple DAC is used (Figur e 6.29). For example, advances in int egr at ed
cir cuit fabr icat ion, t r imming and t est ing have combined t o impr ove yields and
r educe cost s. Pr ocess impr ovement s pr oduce t r ansist or s and r esist or s wit h bet t er
mat ching, which r educes t r imming r equir ement s. At t he same t ime, impr ovement s
in laser t r imming and t est ing per mit mor e accur at e mat ching of mult iple devices on
one die. While t hese advances also have an effect on t he cost s of demult iplexed
syst ems, t he economics of IC fabr icat ion ar e such t hat t he impact of impr ovement s is
r elat ively gr eat er on mult iple DAC devices. As a r esult of t hese impr ovement s,
mult iple DACs ar e ver y cost compet it ive wit h demult iplexed syst ems on a per -
channel basis.
2
3
WHY USE A MULTIPLE-DAC SOLUTION?
Cost

Laser Trimming Aids Matching
Lower Parts Count
Reduced Design Time
Additional System Features

Less Microcontroller Overhead
Faster Update Rate
Synchronized Outputs
Power-On Reset
Read-Back Capability
Serial Interface
Figure 6.29
Anot her advant age of t he mult iple-DAC syst em is r educed par t s count . While cost
est imat es may var y, t he advant ages of eliminat ing component s in a design cannot be
ignor ed. Among t hese advant ages ar e r educed pin count , pr int ed cir cuit boar d ar ea,
invent or y, incoming inspect ion, and pur chasing t r ansact ions.
Reducing design t ime also cont r ibut es t o cost savings. Fr om a design engineer ing
point of view, design t ime is bot h a cr it ical and a ver y visible fact or in t he "t ime-t o-
mar ket " equat ion. Reducing par t s count can have a major impact on design t ime by
r educing device evaluat ion t ime, int er face t iming analyses, er r or budget analyses,
pr int ed cir cuit boar d layout , et c.
The r eal advant ages of t he single-chip mult iple DAC, however , lie in t he feat ur es
t hat ar e difficult or impossible t o add wit h a demult iplexed cir cuit . These
advant ages include:
1. No refresh cycle is required. As pr eviously ment ioned, t he demult iplexed DAC
must const ant ly be r efr eshed. The minimum t ime bet ween r efr esh cycles is set by
t he r equir ed syst em accur acy (t ypically 1/2 LSB), SHA dr oop r at e, and LSB volt age
value. Specifically,
Minimum Re fresh Time =
V
FS
/ 2
2
N
Droop Rate ×
wher e V
FS
= DAC full scale volt age and
N = DAC r esolut ion in bit s.
Const ant ly r efr eshing a demult iplexed DAC put s a soft war e bur den on t he syst em.
In par t icular , not ice t hat t he r efr esh t ime is halved for each addit ional bit of
r esolut ion. For example, if t he DAC r esolut ion is incr eased fr om 8-bit s t o 12-bit s t he
2
4
DAC must be r efr eshed 16 t imes mor e oft en. Soft war e bur den vs. har dwar e savings
t r adeoffs must be evaluat ed car efully in high r esolut ion syst ems.
2. Faster data update rates are possible. In addit ion t o r equir ing const ant r efr esh,
t he r at e at which t he mult iplexed DAC can be updat ed is limit ed by t he sequent ial
ar chit ect ur e of t he syst em. Thus, t he acquisit ion t ime of t he SHA is mult iplied by
t he number of channels. For t he cir cuit of Figur e 6.27, t he best -case t ime for
updat ing all 16 DAC values, assuming a 7µs SHA acquisit ion t ime, will be:
t
s
= 16·7µs = 112µs
Mult iple DACs, on t he ot her hand, can usually be t r eat ed as memor y or input /out put
locat ions, and updat ed at or near t he maximum cycle t ime of t he micr ocont r oller .
Consecut ive DACs can be loaded wit h dat a while pr eviously-loaded DACs ar e
set t ling t o t heir final values. Since t he digit al t r ansfer r at e is usually fast er t han t he
set t ling t ime of t he DAC, t he mult iple-DAC syst em updat e r at e is much fast er t han
t he demult iplexed DAC r at e.
3. Multiple DACs can offer synchronized outputs. Ser vo, ATE, and ot her syst ems can
benefit fr om mult iple out put s which change simult aneously. Many mult iple DACs,
such as t he quad 8-bit AD7225 and oct al 12-bit AD7568, ar e double-buffer ed. Dat a
can be loaded int o st or age lat ches sequent ially, t hen t r ansfer r ed simult aneously t o
t he DAC lat ches when a separ at e “load” pin is br ought low. For higher t hr oughput ,
new dat a can be loaded int o t he st or age lat ches as soon as t he “load” pin r et ur ns
high. In t his case, t he new dat a is loaded dur ing t he set t ling t ime of t he DACs, so
t he t hr oughput r at e is maximized.
4. Multiple DACs usually have a power-on reset feature. Many syst ems must assume
a known st at e upon power -up. For example, a pr ogr ammable power supply should
not out put r andom volt ages when t ur ned on. Sever al DACs, such as t he quad 12-bit
DAC8412/DAC8413 and oct al 8-bit DAC8800, pr ovide a r eset feat ur e which set s all
of t he DACs t o a known st at e. In most cases, t he DAC out put is r eset t o zer o. The
DAC8412, however , will r eset t o mid-scale. This feat ur e pr ovides a zer o-volt out put
at r eset when t he DAC is configur ed for a bipolar out put .
5. S ome multiple DACs’ registers feature data readback. On some mult iple DACs, t he
dat a bus is act ually bi-dir ect ional, and t he value wr it t en int o t he DAC r egist er can
also be r ead back by t he cont r oller . This feat ur e pr ovides t he oppor t unit y for
har dwar e and soft war e er r or checking. Since t he DAC values do not have t o be
saved by t he cont r oller , addit ional dat a st or age is also available for minimum-
memor y micr ocomput er applicat ions.
6. To save real estate and parts count, some multiple DACs use serial data interfaces.
Only t wo or t hr ee pins ar e r equir ed, at bot h t he cont r oller and t he DAC, t o t r ansfer
dat a. Cr eat ing a ser ial dat a int er face for a demult iplexed-DAC syst em r equir es
sever al addit ional packages t o decode t he ser ial addr ess, even if a ser ial-input DAC
is specified. Dr amat ic r educt ions in pin count can be obt ained when a mult iple DAC
wit h ser ial input is specified. For example, t he DAC8420 pr ovides four , 12-bit
volt age out put DACs in one 16-pin package.
2
5
A ser ial dat a int er face is inher ent ly slower t han a par allel int er face. While t his is
usually a pr oblem only in high speed syst ems, t he slower ser ial dat a r at e does
exacer bat e t he demult iplexed-DAC’s r efr esh r equir ement s.
A t wo chip solut ion t o t he dat a dist r ibut ion challenge is shown in Figur e 6.30. The
AD8600 is a mult iple-channel DAC which combines 32 r egist er s, 16 DACs, 16
volt age out put buffer s, cont r ol logic, and an addr ess decoder in a single 44-pin
package.
A 16-CHANNEL 8-BIT DATA DISTRIBUTION
SYSTEM USING A 16-CHANNEL DAC
Figure 6.30
Int er facing t o t he AD8600 is easy. The DACs ar e simply t r eat ed as 16 memor y or I/O
locat ions. Updat ing t he value of any DAC is mer ely a mat t er of wr it ing t he DAC
value, via an 8-bit dat a bus, t o t he appr opr iat e addr ess. If desir ed, dat a can be
wr it t en int o t he input r egist er s wit hout affect ing t he DAC values. When t he LOAD
input is pulled low, all DAC out put s will change simult aneously. Holding LOAD low
causes t he out put of each DAC t o change as soon as t he WRITE command occur s.
This 16-channel, single chip DAC r educes par t s count by 66% over t he
demult iplexed DAC solut ion. Invent or y and assembly cost s, pr int ed cir cuit boar d
ar ea, and design t ime ar e all r educed. Refr eshing t he DAC values is not r equir ed, so
soft war e over head is eliminat ed.
When evaluat ed solely on t he cost of component s, t he demult iplexed single DAC
appr oach is about 40% less expensive t han t he mult iple DAC. On a syst em cost
basis, however , t he advant ages of t he mult iple DAC make it t he cost as well as t he
per for mance winner . A compar ison of t he t wo appr oaches is shown in Figur e 6.31.
The cost advant ages of t he DAC8300 solut ion include:
2
6
COMPARING REPRESENTATIVE 16-CHANNEL,
8-BIT DATA DISTRIBUTION SYSTEMS
Figure 6.31
1. Reduced design time. All of t he DAC syst em specificat ions ar e defined in t he
mult iple DAC dat a sheet . The demult iplexed DAC, on t he ot her hand, r equir es
analysis of t he DC and AC par amet er s of bot h t he DAC and SHA, as well as t he
r elat ionship bet ween t hese par amet er s. (For example, must t he DAC set t ling t ime
be added t o t he SHA acquisit ion t ime, or , since t he DAC set t ling t ime is only 2µs
compar ed t o 7µs for t he SHA, can t he DAC set t ling t ime be ignor ed? Updat ing each
channel in 7µs inst ead of 9µs r educes r efr esh over head by about 20%, but t his is only
valid if syst em specificat ions ar e met . Clear ly, pr ot ot ype evaluat ion is r equir ed).
2. Parts count is reduced by 66%. As pr eviously ment ioned, cost s for pur chasing,
invent or y and assembly ar e r educed.
3. The number of PC board holes (that is, the pin count) is reduced. The number of
holes t hat ar e r equir ed in t he PC boar d is anot her measur e of assembly cost . On t his
basis, t he mult iple DAC wins by about 30%
4. No refresh is required. This fact eliminat es t he soft war e r equir ed t o pr ovide
t iming for t he demult iplexed DAC, and may also fr ee up t he use of a t imer on t he
micr ocont r oller .
Alt hough t he cost savings list ed above ar e significant , t he mult iple DAC’s
impr ovement s t o syst em per for mance ar e even mor e impor t ant in most applicat ions.
The syst em impr ovement s include:
1. Reduced output ripple. The demult iplexed DAC out put will always have r ipple,
caused by t he dr oop r at e of t he SHA.
2. Faster update rate. The delay t ime imposed by t he SHA acquisit ion t ime is
eliminat ed, so t he AD8600 cir cuit can load new DAC values in as lit t le as 80ns. To
updat e 16 DACs, including an 80ns load pulse t o change all DAC out put s
simult aneously, and allowing 2µs for DAC set t ling, r equir es:
2
7
t
s
= (16 + 1) ·80ns + 2µs = 3.3µs.
The demult iplexed DAC, as was shown pr eviously, is limit ed by t he fact t hat t he
acquisit ion t ime of t he SHA is mult iplied by t he sequent ial ar chit ect ur e of t he
syst em. The mult iple DAC has r educed t he r efr esh t ime fr om 112µs t o only 3.3µs. In
applicat ions such as aut omat ic t est equipment , t he effect s of a 3300% impr ovement
in t est value updat e t ime ar e significant . The demult iplexed DAC cir cuit can be
impr oved somewhat by specifying fast er SHAs, but t he incr eased dr oop r at e of a
fast er SHA will demand t hat r efr esh be per for med even mor e fr equent ly. The
incr eased r efr esh may offset t he speed advant age of t he fast er SHA.
3. S imultaneous DAC output changes. Wit h double-buffer ed dat a lat ches, each of t he
DAC values can be loaded sequent ially, but t he out put s will change simult aneously.
If desir ed, of cour se, any of t he DACs can be updat ed individually.
4. A DAC reset input. At syst em power up, or dur ing power fault r ecover y, set t ing
t he r eset input t o a logic low will for ce all DAC r egist er s int o t he zer o st at e. This will
asynchr onously place zer o-volt s on all of t he DAC out put s.
5. Data readback. The DAC has a bi-dir ect ional dat a bus, so t hat t he value wr it t en
int o t he DAC r egist er can also be r ead back by t he cont r oller . This feat ur e pr ovides
t he oppor t unit y for har dwar e and soft war e er r or checking and can be especially
useful dur ing syst em debugging. Since t he DAC values do not have t o be saved in
memor y by t he cont r oller , an addit ional 16 byt es of dat a st or age is also available for
minimum-memor y micr ocomput er applicat ions.
Mult iple DACs ar e offer ed in a wide var iet y of configur at ions, r esolut ion, digit al
int er face, and analog out put . For example, dual, quad, and oct al ver sions of bot h 8-
bit and 12-bit devices ar e available. Ser ial dat a int er faces ar e also available, for
r educed pin count . A 1994 select ion guide (Refer ence 5) fr om Analog Devices
cont ains 12 mult iple DAC pr oduct s which have a ser ial dat a int er face.
Many mult iple DACs ar e used in aut omat ic calibr at ion or syst em nulling
applicat ions. A t ypical device for t hese t asks is t he AD8842, an oct al 8-bit Tr imDAC
®
(Figur e 6.32). This device includes a ser ial dat a input for DAC dat a and addr ess,
eight DAC r egist er s, and eight volt age-out put DACs.
2
8
AD8842 OCTAL 8-BIT SERIAL INPUT TrimDAC
Figure 6.32
This device int r oduces a capabilit y which is impossible wit h a demult iplexed DAC:
the ability to have different reference voltages for each DAC channel. The out put
volt age of each channel of t he AD8842 is simply:
V
OUT
= V
IN

D
• −






128
1
wher e D is a r epr esent at ion of t he DAC input value (t hat is, 0 t o 255 for an 8-bit
DAC). The value of V
IN
can be eit her posit ive or negat ive, DC or AC, allowing each
DAC a 4-quadr ant mult iplying capabilit y. Since V
IN
can be an AC signal, t he DACs
can be also be used as a pr ogr ammable gain cont r ol for signals up t o 50kHz. V
IN
,
t he analog input , exhibit s a fixed input r esist ance of about 20kohms, so dr iving it ,
eit her fr om a DC volt age r efer ence or fr om an AC sour ce, is easy.
The AD8842 is an example of t he r educt ion in pin count which is possible when a
ser ial dat a int er face is used. It combines 8 volt age out put DACs, under 3-wir e ser ial
int er face and an asynchr onous pr eset input , int o a single 24-pin DIP or SOIC
package. To updat e any DAC, t he DAC out put value and addr ess ar e shift ed int o t he
ser ial input r egist er . A logic LOW on t he LD input t hen t r ansfer s t he dat a t o t he
appr opr iat e DAC r egist er . The last bit of t he ser ial input shift r egist er is also
available on t he ser ial dat a out put , so t hat mult iple AD8842s can be daisy-chained
wit hout addit ional logic. Alt hough t he digit al dat a can be loaded at an 8MHz r at e,
each DAC out put r equir es 5.4µs t o set t le t o ± 1 LSB.
Ot her key feat ur es of t he AD8842 ar e shown in Figur e 6.33. The pr eset (PR) input
can be used t o for ce t he out put s of all t he DACs t o 0V when power is fir st applied, or
aft er a power fault . Placing a logic low on PR will for ce a value of 128 base10 (80
2
9
base16) int o all of t he DAC r egist er s. As can be seen fr om t he out put volt age
equat ion shown in Figur e 6.32, a DAC value of 128 base 10 pr oduces a 0V out put .
AD8842 KEY FEATURES
Eight Individual Channels
3-Wire Serial Data Input, 8MHz Loading Rate
Asynchronous Reset Input
50kHz, 4-Quadrant Multiplexing Bandwidth
Replaces 8 Potentiometers
Constant 20k Input Resistance
4V Output Swing
Low Power: 95mW on 5V Supplies
24-pin Narrow DIP or SO Package
Figure 6.33
The AD8842 Tr imDAC
®
can also r eplace 8 pot ent iomet er s in volt age nulling
applicat ions. Unlike a t r imming pot ent iomet er , however , t he Tr imDAC
®
can
gener at e bot h posit ive and negat ive volt ages fr om a posit ive r efer ence volt age. This
is a significant advant age in many applicat ions, because t he nulling volt age can be
der ived fr om a ver y st able syst em r efer ence volt age. Obt aining a bipolar nulling
volt age wit h a pot ent iomet er nor mally r equir es eit her pr oviding t wo separ at e
posit ive and negat ive r efer ence volt ages, or connect ing one end of t he pot t o t he
negat ive power supply. Since power supplies ar e t ypically noisy and poor ly r egulat ed
when compar ed t o t he syst em r efer ence volt age, per for mance will be degr aded if t he
power supply must be used.
The effect of a ser ial int er face on pin count becomes even mor e evident as t he DAC
r esolut ion incr eases. For example, t he AD8522 squeezes t wo 12-bit DACs, a 2.5V
r efer ence, a double-buffer ed ser ial input , and t wo r eset cont r ol input s int o a single
14-pin package (Figur e 6.34). A companion par t , t he AD8582, has similar feat ur es
but r equir es 24 pins because it has a par allel int er face.
3
0
AD8522: WORLD’S SMALLEST (SO-14, PDIP-14)
COMPLETE DUAL 12-BIT DAC
Figure 6.34
The AD8522’s 2.5V r efer ence is available on t he V
REF
pin t o pr ovide a r efer ence for
ot her dat a acquisit ion por t ions of t he syst em or for r at iomet r ic applicat ions. The
r efer ence out put can also be used t o cr eat e a vir t ual gr ound for applicat ions wher e a
quasi-bipolar out put is desir ed. The V
REF
pin cannot , however , be used as a
r efer ence input .
As wit h t he AD8842 oct al DAC, bot h AD8522 DAC r egist er s can be asynchr onously
for ced t o a half-scale value (2048 base 10 or 800 base 16). This act ion set s a 0V
r eading for quasi-bipolar applicat ions. Bot h r egist er s of t he AD8522 can also be r eset
t o a "000" value, which pr ovides a 0V r eset for unipolar applicat ions. Ot her key
feat ur es of t he AD8522 ar e shown in Figur e 6.35.
AD8522 KEY FEATURES
Space-Saving SOIC-14 Package, only 1.5mm Height!
Low Power: 10mW max
No External Components, No Adjustments Necessary
+5V Operation Guaranteed Down to 4.5V Minimum
4.095V Full Scale (1mV/LSB), Fully Trimmed
Buffered Rail-to-Rail Voltage Outputs
2.5 V VREF Output Pin - Useful for establishing virtual ground in
bipolar applications
Midscale or Zero-Scale Present
Double-Buffered 3-Wire Serial Data Input
Software and Hardware A/B DAC Select
Figure 6.35
3
1
The AD8522 int r oduces t wo new concept s t o t he mult i-channel dat a dist r ibut ion
discussion. The fir st new concept is t he complete DAC (Figur e 6.36). All of t he
syst ems ment ioned pr eviously have r equir ed a separ at e ext er nal r efer ence, which
had t o be adjust ed t o set t he DAC’s full scale out put volt age. The AD8522, on t he
ot her hand, has an on-chip bandgap r efer ence which is laser -t r immed dur ing
pr oduct ion t o pr ovide a full scale out put volt age of 4.095V (t hat is, 1mV/LSB). Since
t he volt age r efer ence, DAC, and volt age out put amplifier s ar e on a single chip, t he
ent ir e DAC syst em specificat ion is cont ained in t he AD8522’s dat a sheet
specificat ions. This eliminat es t he necessit y of evaluat ing sever al separ at e devices,
as well as calculat ing t he er r or cont r ibut ions of each device, and fur t her
demonst r at es t he significant r educt ion in design t ime which r esult s fr om r educing
package count . In addit ion, syst em cost is r educed and r eliabilit y is impr oved
because t he calibr at ion oper at ion is eliminat ed.
EQUIVALENT SCHEMATIC OF AD8522 ANALOG SECTION
Figure 6.36
The ot her concept which has not been discussed pr eviously is low-volt age, single
supply oper at ion. It is at t his point t hat demult iplexed DAC syst ems r apidly become
impr act ical. One effect of a low supply volt age is t hat t he value of t he least
significant bit must be r educed. For single +5V oper at ion, t he pr act ical limit on full
scale volt age at 12-bit s is t ypically 4.096V . This yields an LSB value of 1mV for a
12-bit DAC, which means t hat t he t ot al SHA er r or budget , including offset volt age,
dr oop r at e and hold st ep, must not exceed ±500µV in or der t o limit er r or s t o 1/2 LSB.
Impr oving t he dr oop r at e and hold st ep er r or s of a mult i-channel SHA is difficult
because of t he limit ed size of t he on-chip capacit or s. As t he value of t he hold
capacit or s incr ease, die size and cost r ise r apidly. Adding individual SHAs wit h
ext er nal hold capacit or s is possible, but r apidly incr eases t he component count .
Again, t he mult i-channel DAC is a super ior solut ion.
Anot her r equir ement for single-supply, low volt age oper at ion is r ail-t o-r ail
oper at ion. Single-supply bipolar amplifier s, using common-emit t er out put st ages,
ar e limit ed in some low volt age applicat ions because t he sat ur at ion volt age of t he
out put t r ansist or s limit s out put volt age swing. The AD8522 employs P-channel and
3
2
N-channel MOSFETs (Figur e 6.37) t o pr ovide wide out put volt age swing while
oper at ing fr om a single +5 V supply. The out put of t his t ype of st age (at a supply
r ail) looks like t he on-r esist ance of t he P or N-channel FET connect ed t o t he r ail.
Obviously, t his on-r esist ance begins t o limit t he out put swing as t he out put load
cur r ent is incr eased.
AD8522 RAIL-TO-RAIL OUTPUT PERFORMANCE
YIELDS 5mA WITH 60mA SHORT CIRCUIT CURRENT
Figure 6.37
The effect of a ser ial int er face on pin count is demonst r at ed by compar ing t he
AD8522 wit h t he similar AD8582. The lat t er par t has a 12-bit par allel int er face, and
r equir es 24 pins ver sus 14 pins for t he ser ial dat a ver sion.
AD8582 COMPLETE DUAL 12-BIT
SINGLE +5V SUPPLY DAC
Figure 6.38
One significant advant age of t he par allel int er face is, of cour se, higher speed. The
par allel device can updat e bot h 12-bit DACs in 100ns. The ser ial dat a ver sion, on t he
ot her hand, r equir es 32 clock cycles t o ent er t he dat a for t wo DACs. Wit h a
maximum clock fr equency of 14MHz, t his r esult s in a dat a updat e per iod of 2.2µs.
3
3
The par allel-dat a ver sion also includes complet e dual-r ank dat a lat ches, so t hat bot h
DACs can be updat ed simult aneously (Figur e 6.39).
AD8582 KEY FEATURES
Complete Dual 12-bit DAC
No External Components
Single +5 Operation
1mV/bit with 4.095V Full Scale
True Voltage Output, 5mA Drive
Parallel Input Register with Fast 30ns Chip Select
Double-Buffered for Simultaneous A and B Output Update
Reset Pin Forces Output to Zero Volts or half Scale, Depending
on MSB Pin
Low Power: 5mW
Figure 6.39
The logical ext ension of a ser ial dat a int er face and low volt age CMOS t echnology is
expr essed in Figur e 6.40. While not a mult i-channel device, t he AD8300 does pack a
complet e 12-bit volt age out put DAC int o a single 8-pin package. No ext er nal
component s ar e r equir ed, except for supply bypass capacit or s. Since it is capable of
oper at ing fr om a single 3V supply, t his device is ideal for bat t er y-power ed
applicat ions.
A 12-BIT, +3V DAC SYSTEM BASED ON AD8300
Figure 6.40
3
4
The AD8300 has only one analog pin, which is t he DAC’s volt age out put . Wit h only
one analog pin, t he AD8300 is an ideal device for designer s whose exper ience is
mainly digit al. All analog cir cuit r y, except for t he analog volt age out put pin, is
t r anspar ent t o t he user . Double-buffer ed dat a lat ches pr event t he DAC out put fr om
changing while new dat a is being shift ed int o t he AD8300.
AD8300 BLOCK DIAGRAM
Figure 6.41
The AD8300 is laser -t r immed dur ing pr oduct ion, so no calibr at ion or ot her
adjust ment s ar e r equir ed. The DAC value is simply shift ed int o t he ser ial dat a
input , and t he analog out put r esponds wit h a pr e-t r immed value of:
V
OUT
= D·0.5mV,
wher e D is a decimal number which r epr esent s t he DAC input value (t hat is, 0 t o
4095). The full-scale out put volt age is 2.0475V, which is appr opr iat e for t he
minimum supply volt age of 2.7V. The DAC out put can be asynchr onously set t o 0V
wit h t he CLR input , if a power -on r eset is r equir ed.
3
5
KEY FEATURES OF THE AD8300 DAC
Complete Voltage Output 12-bit DAC
Single +3V Operation
No External Components
2.0475V Full Scale Output (0.5mV/bit)
6 s Output Settling Time
Serial Data Input
Asynchronous Clear Input
Low Power; 3.6mW

PCMCIA-Compatible SO-8 Package (1.5mm package height)
Figure 6.42
The dat a dist r ibut ion syst ems discussed so far have illust r at ed t he t r adeoffs
bet ween demult iplexing a single DAC and using a single chip, mult iple-channel
DAC. Bot h of t hese concept s assume t hat t he syst em being designed r equir es sever al
analog volt ages in close physical pr oximit y t o each ot her . The design consider at ions
change, however , for syst ems wher e differ ent cir cuit element s ar e not physically
close. Analog signal t r aces should be kept as shor t as possible t o r educe er r or sour ces
such as leakage and noise pickup. Digit al signals have mor e noise immunit y t han
analog signals, so t he r ule of t humb is t o locat e t he DAC as close t o it s associat ed
analog cir cuit r y as possible.
A complet e DAC wit h ser ial input can ut ilize it s small size t o place t he analog
volt ages near t he cir cuit s t hey cont r ol wit h minimal impact on over all PC boar d
ar ea. Two AD8300s, for example, have a t ot al of only 16 pins. This is only t wo pins
mor e t han t he pr eviously-discussed dual-12-bit DAC, yet t he t wo single DACs can be
locat ed dir ect ly adjacent t o subsequent cir cuit s (Figur e 6.43). This eliminat es long
PC boar d t r aces (for t he analog signal) and r educes noise pickup. Mult iple AD8300s
can be accessed wit h one ser ial dat a bus, and t he out put s of t he DACs can change
eit her synchr onously or asynchr onously.
3
6
REMOTE, MULTI-CHANNEL DATA DISTRIBUTION
Figure 6.43
3
7
REFERENCES
1. Li n ea r Desi gn Semi n a r , Analog Devices, 1995, Chapt er 7.
2. Syst em Ap p li ca t i on s Gu i d e, Analog Devices, 1993, Chapt er 2.
3. Dan Sheingold, An a log-Di gi t a l Con ver si on Ha n d book ,
Th i r d Ed i t i on , Pr ent ice-Hall, 1986.
4. Adolfo A. Gar cia, Applications of the S MP-04 and the S MP-08/ S MP-18,
Quad and Octal S ample-and-Hold Amplifiers, Ap p li ca t i on Not e AN-204,
Analog Devices, 1991.
5. A S election Guide for S erial DACs, Document Number G1982,
Analog Devices, 1994.
1
SECTION 7
OVERVOLTAGE EFFECTS ON
ANALOG INTEGRATED CIRCUITS
Amplifier Input Stage Overvoltage
Amplifier Output Voltage Phase Reversal
Understanding and Protecting Integrated
Circuits from Electrostatic Discharge (ESD)
2
SECTI ON 7
OVERVOLTAGE EFFECTS ON
ANALOG I NTEGRATED CI RCUI TS
Ad ol f o Ga r ci a , Wes Fr eem a n
One of t he most commonly asked applicat ions quest ions is: “What happens if
ext er nal volt ages ar e applied t o an analog int egr at ed cir cuit wit h t he supplies
t ur ned off?” This quest ion descr ibes sit uat ions t hat can t ake on many differ ent
for ms: fr om light ning st r ikes on cables which pr opagat e ver y high t r ansient volt ages
int o signal condit ioning cir cuit s, t o walking acr oss a car pet and t hen t ouching a
pr int ed cir cuit boar d full of sensit ive pr ecision cir cuit s. Regar dless of t he sit uat ion,
t he gener al issue is t he effect of over volt age st r ess (and, in some cases, abuse) on
analog int egr at ed cir cuit s. The discussion which follows will be limit ed in gener al t o
oper at ional amplifier s, because it is t hese devices t hat most oft en int er face t o t he
out side wor ld. The pr inciples developed her e can and should be applied t o all analog
int egr at ed cir cuit s which ar e r equir ed t o condit ion or digit ize analog wavefor ms.
These devices include (but ar e not limit ed t o) inst r ument at ion amplifier s, analog
compar at or s, sample-and-hold amplifier s, analog swit ches and mult iplexer s, and
analog-t o-digit al conver t er s.
AMP LI FI ER I NP UT STAGE OVERVOLTAGE
In r eal wor ld signal condit ioning, sensor s ar e oft en used in host ile envir onment s
wher e fault s can and do occur . When t hese fault s t ake place, signal condit ioning
cir cuit r y can be exposed t o lar ge volt ages which exceed t he power supplies. The
likelihood for damage is quit e high, even t hough t he component s’ power supplies
may be t ur ned on. Published specificat ions for oper at ional amplifier absolut e
maximum r at ings st at e t hat applied input signal levels should never exceed t he
power supplies by mor e t han 0.3V or , in some devices, 0.7V. Exceeding t hese levels
exposes amplifier input st ages t o pot ent ially dest r uct ive fault cur r ent s which flow
t hr ough int er nal met al t r aces and par asit ic p-n junct ions t o t he supplies. Wit hout
some t ype of cur r ent limit ing, unpr ot ect ed input differ ent ial pair s (BJ Ts or FETs)
can be dest r oyed in a mat t er of micr oseconds. Ther e ar e, however , some devices wit h
built -in cir cuit r y t hat can pr ovide pr ot ect ion beyond t he supply volt ages, but in
gener al, absolut e maximum r at ings must st ill be obser ved.
3
INPUT STAGE OVERVOLTAGE
INPUT SHOULD NOT EXCEED ABSOLUTE MAXIMUM RATINGS
(Usually Specified With Respect to Supply Voltages)
A Common Specification Requires the Input Signal <|V
s
| 0.3V
Input Voltage Should be Held Near Zero in the Absence of
Supplies
Input Stage Conduction Current Needs to be Limited (Rule of
Thumb: 5mA)
Avoid Reverse Bias Junction Breakdown in Input Stage Base-
Emitter Junctions
Differential and Common-Mode Ratings may Differ
No Two Amplifiers are exactly the Same
Some Op Amps Contain Input Protection (Voltage Clamps,
Current Limits, or Both), but Absolute Maximum Ratings Must
Still be Observed
Figure 7.1
Alt hough mor e r ecent vint age oper at ional amplifier s designed for single-supply or
r ail-t o-r ail oper at ion ar e now including infor mat ion wit h r egar d t o input st age
over volt age effect s, t her e ar e ver y many amplifier s available t oday wit hout such
infor mat ion pr ovided by t he manufact ur er . In t hose cases, t he cir cuit designer using
t hese component s must ascer t ain t he input st age cur r ent -volt age char act er ist ic of
t he device in quest ion befor e st eps can be t aken t o pr ot ect it . All amplifier s will
conduct cur r ent t o t he posit ive/negat ive supply, pr ovided t he applied input volt age
exceeds some int er nal t hr eshold. This t hr eshold is device dependent , and can r ange
fr om 0.7V t o 30V, depending on t he int er nal const r uct ion of t he input st age.
Regar dless of t he t hr eshold level, ext er nally gener at ed fault cur r ent s should be
limit ed t o no mor e t han ±5mA.
Many fact or s cont r ibut e t o t he cur r ent -volt age char act er ist ic of an amplifier ’s input
st age: int er nal differ ent ial clamping diodes, cur r ent -limit ing ser ies r esist ances,
subst r at e pot ent ial connect ions, and differ ent ial input st age t opologies (BJ Ts or
FETs). Input pr ot ect ion diodes used as differ ent ial input clamps ar e t ypically
const r uct ed fr om t he base-emit t er junct ions of NPN t r ansist or s. These diodes
usually for m a par asit ic p-n-junct ion t o t he negat ive supply when t he applied input
volt age exceeds t he negat ive supply. Cur r ent -limit ing ser ies r esist ances used in t he
input st ages of oper at ional amplifier s can be fabr icat ed fr om t hr ee t ypes of mat er ial:
n- or p-t ype diffusions, polysilicon, or t hin-films (SiCr , for example). Polysilicon and
t hin-film r esist or s ar e fabr icat ed over t hin layer s of oxide which pr ovide an
insulat ing bar r ier t o t he subst r at e; as such, t hey do not exhibit any par asit ic p-n
junct ions t o eit her supply. Diffused r esist or s, on t he ot her hand, exhibit p-n
4
junct ions t o t he supplies because t hey ar e const r uct ed fr om eit her p- or n-t ype
diffusion r egions. The subst r at e pot ent ial of t he amplifier is t he most cr it ical
component , for it will det er mine t he sensit ivit y of an amplifier ’s input cur r ent -
volt age char act er ist ic t o supply volt age.
The configur at ion of t he amplifier ’s input st age also plays a lar ge r ole in t he cur r ent -
volt age char act er ist ic of t he amplifier . Input differ ent ial pair s of oper at ional
amplifier s ar e const r uct ed fr om eit her bipolar t r ansist or s (NPN or PNP) or field-
effect t r ansist or s (junct ion or MOS, N- or P-channel). While t he bipolar input
differ ent ial pair s do not have any dir ect pat h t o eit her supply, FET differ ent ial pair s
do. For example, an n-channel J FET for ms a par asit ic p-n junct ion bet ween it s
backgat e and t he p-subst r at e t hat ener gizes when V
IN
+ 0.7V < V
NEG
. As
ment ioned pr eviously, many manufact ur er s of analog int egr at ed cir cuit s do not
pr ovide any det ails wit h r egar d t o t he behavior of t he device’s input st r uct ur e.
Eit her simplified schemat ics ar e not pr ovided or , if t hey ar e shown, t he behavior of
t he input st age under an over volt age condit ion is omit t ed. Ther efor e, ot her measur es
must be t aken in or der t o ident ify t he conduct ion pat hs.
A st andar d t r ansist or cur ve t r acer can be configur ed t o det er mine t he cur r ent -
volt age char act er ist ic of any amplifier r egar dless of input cir cuit t opology. As shown
in Figur e 7.2, bot h amplifier supply pins ar e connect ed t o gr ound, and t he collect or
out put dr ive is connect ed t o one of t he amplifier ’s input s. The cur ve t r acer applies a
DC r amp volt age and measur es t he cur r ent flowing t hr ough t he input st age. In t he
event t hat a t r ansist or cur ve t r acer is not available, a DC volt age sour ce and a
mult imet er can be subst it ut ed for t he cur ve t r acer . A 10kohm r esist or should be
used bet ween t he DC volt age sour ce and t he amplifier input for addit ional
pr ot ect ion. Ammet er r eadings fr om t he mult imet er at each applied DC volt age will
yield t he same r esult as t hat pr oduced by t he cur ve t r acer . Alt hough eit her input
can be t est ed (bot h input s should), it is r ecommended t hat t he unused input is left
open; ot her wise, addit ional junct ions could come int o play and would complicat e
mat t er s fur t her . Evaluat ions of cur r ent feedback amplifier input st ages ar e mor e
difficult because of t he lack of symmet r y bet ween t he input s. As a r esult , bot h input s
should be char act er ized for t heir individual cur r ent -volt age char act er ist ics.
5
OVER-VOLTAGE CURVE TRACER TEST SETUP
Figure 7.2
Once t he input cur r ent -volt age char act er ist ic has been det er mined for t he device in
quest ion, t he next st ep is t o det er mine t he minimum level of r esist ance r equir ed t o
limit fault cur r ent s t o ±5mA. Equat ion 7.1 illust r at es t he comput at ion for R
s
when
t he input over volt age level is known:
R
s
V
IN(MAX)
V
SUPPLY
5 mA
=

Eq. 7.1
The wor st case condit ion for over volt age would be when t he power supplies ar e
init ially t ur ned off or disconnect ed. In t his case, V
SUPPLY
is equal t o zer o. For
example, if t he input over volt age could r each 100V under some t ype of fault
condit ion, t hen t he ext er nal r esist or should be no smaller t han 20kohms. Most
oper at ional amplifier applicat ions only r equir e pr ot ect ion at one input ; however ,
t her e ar e a few configur at ions (differ ence amplifier s, for example) wher e bot h input s
can be subject ed t o over volt age and bot h must be pr ot ect ed. The need for pr ot ect ion
on bot h input s is much mor e common wit h inst r ument at ion amplifier s.
6
OVERVOLTAGE EFFECTS
Junctions may be Forward Biased if the Current is Limited
In General a Safe Current Limit is 5mA
Reverse Bias Junction Breakdown is Damaging Regardless of
the Current Level
When in Doubt, Protect with External Diodes and Series
Resistances
Curve Tracers Can be Used to Check the Overvoltage
Characteristics of a Device
Simplified Equivalent Circuits in Data Sheets do not tell the
Entire Story!!!
Figure 7.3
AMP LI FI ER OUTP UT VOLTAGE P HASE REVERSAL
Some oper at ional amplifier s exhibit out put volt age phase r ever sal when one or bot h
of t heir input s exceeds t heir input common-mode volt age r ange. Phase r ever sal is
usually associat ed wit h J FET (n- or p-channel) input amplifier s, but some bipolar
devices (especially single-supply amplifier s oper at ing as unit y-gain follower s) may
also be suscept ible. In t he vast major it y of applicat ions, out put volt age phase
r ever sal does not har m t he amplifier nor t he cir cuit in which t he amplifier is used.
Alt hough a number of oper at ional amplifier s suffer fr om phase r ever sal, it is r ar ely
a pr oblem in syst em design. However , in ser vo loop applicat ions, t his effect can be
quit e hazar dous. For t unat ely, t his is only a t empor ar y condit ion. Once t he
amplifier ’s input s r et ur n t o wit hin it s nor mal oper at ing common-mode r ange, out put
volt age phase r ever sal ceases. It may st ill be necessar y t o consult t he amplifier
manufact ur er , since phase r ever sal infor mat ion r ar ely appear s on device dat a
sheet s. Summar ized as follows is a list of r ecent vint age Analog Devices amplifier
pr oduct s t hat ar e now including out put volt age phase r ever sal
char act er izat ion/comment ar y:
Si n gle-Su p p ly/
Ra i l-t o-Ra i l
Du a l Su p p ly
OP295/OP495 OP282/OP482
OP113/OP213/OP413 OP285
OP183/OP283 OP467
OP292/OP492 OP176
OP191/OP291/OP491 BUF04
OP279
AD820/AD822/AD824
OP193/OP293/OP493
7
In BiFET oper at ional amplifier s, phase r ever sal may be pr event ed by adding an
appr opr iat e r esist ance in ser ies wit h t he amplifier ’s input t o limit t he cur r ent .
Bipolar input devices can be pr ot ect ed by using a Schot t ky diode t o clamp t he input
t o wit hin a few hundr ed millivolt s of t he negat ive r ail. For a complet e descr ipt ion of
t he out put volt age phase r ever sal effect , please consult Refer ence 1.
BEWARE OF AMPLIFIER OUTPUT PHASE REVERSAL
Sometimes Occurs in FET and Bipolar Input (Especially Single-
Supply) Op Amps when Input Exceeds Common Mode Range
Does Not Harm Amplifier, but may be Disastrous in Servo
Systems!
Not Usually Specified on Data Sheet, so Amplifier Must be
Checked
Easily Prevented:

BiFETs:
Add Appropriate Input Series Resistance
(Determined Empirically, Unless
Provided in Data Sheet)
Bipolars:
Use Schlottky Diode Clamps to the
Supply Rails.
Figure 7.4
Rail-t o-r ail oper at ional amplifier s pr esent a special class of pr oblems t o t he
int egr at ed cir cuit designer , because t hese t ypes of devices should not exhibit any
abnor mal behavior t hr oughout t he ent ir e input common-mode r ange. In fact , it is
desir able t hat devices used in t hese applicat ions also not exhibit any abnor mal
behavior if t he applied input volt ages exceed t he power supply r ange. One of t he
mor e r ecent vint age r ail-t o-r ail input /out put oper at ional amplifier s, t he OPX91
family (t he OP191, t he OP291, and t he OP491), includes addit ional component s t hat
pr event over volt age and damage t o t he device. As shown in Figur e 7.5, t he input
st age of t he OPX91 devices use six diodes and t wo r esist or s t o clamp t he input
t er minals t o each ot her and t o t he supplies. D1 and D2 ar e base-emit t er NPN diodes
which ar e used t o pr ot ect t he bases of Q1-Q2 and Q3-Q4 against avalanche
br eakdown when t he applied differ ent ial input volt age t o t he device exceeds 0.7V.
Diodes D3-D6 ar e diodes for med fr om subst r at e PNP t r ansist or s t hat clamp t he
applied input volt ages on t he OPX91 t o t he supply r ails.
8
A CLOSER LOOK AT THE OP-X91 INPUT STAGE
REVEALS ADDITIONAL DEVICES
Figure 7.5
An int er est ing benefit fr om using subst r at e PNPs as clamp diodes is t hat t heir
collect or s ar e connect ed t o t he negat ive supply; t hus, when t he applied input volt age
exceeds eit her supply r ail, t he diodes ener gize, and t he fault cur r ent s ar e diver t ed
dir ect ly t o t he supply and not t hr ough or int o t he device’s input st age. Ther e ar e also
5kohm r esist or s in ser ies wit h each of t he input s t o t he OPX91 t o limit t he fault
cur r ent t hr ough D1 and D2 when t he differ ent ial input volt age exceeds 0.7V. Not e
t hat t hese 5kohm r esist or s ar e p-t ype diffusions placed inside an n-well, which is
t hen connect ed t o t he posit ive supply. When t he applied input volt age exceeds t he
posit ive supply, some of t he fault cur r ent gener at ed is also diver t ed t o V
POS
and
away fr om t he input st age. As a r esult of t hese measur es, t he input over volt age
char act er ist ic of t he OPX91 is well behaved as shown in Figur e 7.6. Not e t hat t he
combinat ion of t he 5kohm r esist or s and clamp diodes safely limit s t he input cur r ent
t o less t han 2mA, even when t he input s of t he device exceed t he supply r ails by 10V.
9
INTERNAL 5k RESISTORS PLUS IINPUT CLAMP
DIODES COMBINE TO PROTECT OP-X91 DEVICES
AGAINST OVERVOLTAGE
Figure 7.6
As an added safet y feat ur e, an addit ional pair of diodes is used in t he input st age
acr oss Q3 and Q4 t o pr event subsequent st ages int er nal t o t he OPX91 fr om
collapsing (t hat is, for ced int o cut off). If t hese st ages wer e for ced int o cut off, t hen t he
amplifier would under go out put volt age phase r ever sal when t he input s exceeded
t he posit ive input common mode volt age. An illust r at ion of t he diodes’ effect iveness
is shown in Figur e 7.7. Her e, t he OPX91 family can safely handle a 20Vp-p input
signal on ±5V supplies wit hout exhibit ing any sign of out put volt age phase r ever sal
or ot her anomalous behavior . Wit h t hese amplifier s, no ext er nal clamping diodes ar e
r equir ed.
1
0
ADDITION OF TWO CLAMP DIODES PROTECTS OP-X91
DEVICES AGAINST OUTPUT PHASE REVERSAL
Figure 7.7
For t hose amplifier s wher e ext er nal pr ot ect ion is clear ly r equir ed against bot h
over volt age abuse and out put phase r ever sal, a common t echnique is t o use a ser ies
r esist ance, R
s
, t o limit fault cur r ent , and Schot t ky diodes t o clamp t he input signal
t o t he supplies, as shown in Figur e 7.8.
1
1
GENERALIZED EXTERNAL PROTECTION SCHEME
AGAINST INPUT OVERVOLTAGE ABUSE AND OUTPUT
VOLTAGE PHASE REVERSAL IN SINGLE-SUPPLY OP AMPS
Figure 7.8
The ext er nal input ser ies r esist ance, R
s
, will be pr ovided by t he manufact ur er of t he
amplifier , or det er mined empir ically by t he user wit h t he met hod pr eviously shown
in Figur e 7.2 and Eq. 7.1. Mor e oft en t han not , t he value of t his r esist or will pr ovide
enough pr ot ect ion against out put volt age phase r ever sal, as well as limit ing t he
fault cur r ent t hr ough t he Schot t ky diodes.
It is evident t hat whenever r esist ance is added in ser ies wit h an amplifier 's input ,
it s offset and noise per for mance will be affect ed. The effect s of t his ser ies r esist ance
on cir cuit noise can be calculat ed using t he following equat ion.
( )
( )
( )
E
n,t ot al
e
n,op amp
2
+ e
n,R
s
2
+ R
s amp
2
= ⋅ i
n op ,
The t her mal noise of t he r esist or , t he volt age noise due t o amplifier noise cur r ent
flowing t hr ough t he r esist or , and t he input noise volt age of t he amplifier ar e added
t oget her (in r oot -sum-squar e manner , since t he noise volt ages ar e uncor r elat ed) t o
det er mine t he t ot al input noise and may be compar ed wit h t he input volt age noise in
t he absence of t he pr ot ect ion r esist or .
A pr ot ect ion r esist or in ser ies wit h an amplifier input will also pr oduce a volt age
dr op due t o t he amplifier bias cur r ent flowing t hr ough it . This dr op appear s as an
incr ease in t he cir cuit offset volt age (and, if t he bias cur r ent changes wit h
t emper at ur e, offset dr ift ). In amplifier s wher e bias cur r ent s ar e appr oximat ely
equal, a r esist or in ser ies wit h each input will t end t o balance t he effect and r educe
t he er r or . The effect s of t his addit ional ser ies r esist ance on t he cir cuit ’s over all offset
volt age can be calculat ed:
1
2
V
os t ot al
V
os
I
b
R
s ( )
= +
For t he case wher e R
FB
= R
s
or wher e t he sour ce impedance levels ar e balanced,
t hen t he t ot al cir cuit offset volt age can be expr essed as:
V
os(t ot al)
V
os
I
os
R
s
= +
To limit t he addit ional noise of R
FB
, it can be shunt ed wit h a capacit or .
When using ext er nal clamp diodes t o pr ot ect oper at ional amplifier input s, t he effect s
of diode junct ion capacit ance and leakage cur r ent should be evaluat ed in t he
applicat ion. Diode junct ion capacit ance and R
s
will add an addit ional pole in t he
signal pat h, and diode leakage cur r ent s will double for ever y 10°C r ise in ambient
t emper at ur e. Ther efor e, low leakage diodes should be used such t hat , at t he highest
ambient t emper at ur e for t he applicat ion, t he t ot al diode leakage cur r ent is less t han
one-t ent h of t he input bias cur r ent for t he device at t hat t emper at ur e. Anot her issue
wit h r egar d t o t he use of Schot t ky diodes is t he change in t heir for war d volt age dr op
as a funct ion of t emper at ur e. These diodes do not , in fact , limit t he signal t o ±0.3V at
all ambient t emper at ur es, but if t he Schot t ky diodes ar e at t he same t emper at ur e as
t he op amp, t hey will limit t he volt age t o a safe level, even if t hey do not limit it at
all t imes t o wit hin t he dat a sheet r at ing. This is t r ue if over -volt age is only possible
at t ur n-on, when t he diodes and t he op amp will always be at t he same t emper at ur e.
If t he op amp is war m when it is r epower ed, however , st eps must be t aken t o ensur e
t hat diodes and op amp ar e at t he same t emper at ur e.
UNDERSTANDI NG AND PROTECTI NG I NTEGRATED
CI RCUI TS FROM ELECTROSTATI C DI SCHARGE (ESD)
Wes Fr eem a n
Int egr at ed cir cuit s can be damaged by t he high volt ages and high peak cur r ent s t hat
can be gener at ed by elect r ost at ic dischar ge. Pr ecision analog cir cuit s, which oft en
feat ur e ver y low bias cur r ent s, ar e mor e suscept ible t o damage t han common digit al
cir cuit s, because t he t r adit ional input -pr ot ect ion st r uct ur es which pr ot ect against
ESD damage also incr ease input leakage.
The keys t o eliminat ing ESD damage ar e: (1) awar eness of t he sour ces of ESD
volt ages, and (2) under st anding t he simple handling st eps t hat will dischar ge
pot ent ial volt ages safely.
The basic definit ions r elat ing t o ESD ar e given in Figur e 7.9. Not ice t hat t he ES D
Failure Threshold level r elat es t o any of t he IC dat a sheet limit s, and not simply t o a
catastrophic failure of t he device. Also, t he limit s apply t o each pin of t he IC, not just
t o t he input and out put pins.
1
3
ESD DEFINITIONS
ESD (Electrostatic Discharge):

A single fast, high current transfer of electrostatic charge.
Direct contact between two objects at different
potentials.
A high electrostatic field between two objects when
they are close in proximity.
ESD Failure Threshold:
The highest voltage level at which all pins on a device can
be subjected to ESD zaps without failing any 25 C data
sheet limits
Figure 7.9
The gener at ion of st at ic elect r icit y caused by r ubbing t wo subst ances t oget her is
called t he triboelectric effect. St at ic char ge can be gener at ed eit her by dissimilar
mat er ials (for example, r ubber -soled shoes moving acr oss a r ug) or by separ at ing
similar mat er ials (for example, pulling t r anspar ent t ape off of a r oll).
A wide var iet y of common human act ivit ies can cr eat e high elect r ost at ic char ge.
Some examples ar e given in Figur e 7.10. The values shown will occur wit h a fair ly
high r elat ive humidit y. Low humidit y, such as can occur indoor s dur ing cold
weat her , can gener at e volt ages 10 t imes (or mor e) gr eat er t han t he values shown.
1
4
EXAMPLES OF ELECTROSTATIC CHARGE GENERATION
Person walks across a typical carpet.
1000-1500V generated
Person walks across a typical vinyl floor.
150 - 250V generated
Person handles instructions protected by clear plastic covers.
400 - 600V generated
Person handles polyethylene bags.
1000 - 1200V generated
Person pours polyurethane foam into a box.
1200 - 1500V generated
An IC slides down a grounded handler chute.
50 - 500V generated
An IC slides down an open conductive shipping tube.
25 - 250V generated
Note:
Above values can occur in a high (≈60%) RH environment. For low RH (≈30%),
generated voltages can be >10 times those listed above!
Figure 7.10
In an effor t t o st andar dize t he t est ing and classificat ion of int egr at ed cir cuit s for
ESD r obust ness, ESD models have been developed (Figur e 7.11). These models
at t empt t o simulat e t he sour ce of ESD volt age. The assumpt ions under lying t he
t hr ee commonly-used models ar e differ ent , so r esult s ar e not dir ect ly compar able.
MODELING ELECTRONIC POTENTIAL
Three Models:

1. Human Body Model (HBM)
2. Machine Model (MM)
3. Charged Device Model (CDM)

Model Correlation:
Low - Assumptions are Different
Figure 7.11
The most -oft en encount er ed ESD model is t he Human Body Model (HBM). This
model simulat es t he appr oximat e r esist ance and capacit ance of a human body wit h a
simple RC net wor k. The capacit or is char ged t hr ough a high volt age power supply
(HVPS) and t hen dischar ged (using a high volt age swit ch) t hr ough a ser ies r esist or .
1
5
The RC values for differ ent individuals will, of cour se, var y. However , t he HBM has
been st andar dized by MIL-STD-883 Met hod 3015 Elect r ost at ic Dischar ge Sensit ivit y
Classificat ion, which specifies R-C combinat ions of 1.5kohm and 100pF. (R, C, and L
values for all t hr ee ESD models ar e shown in Figur e 7.12.)
ESD MODELS APPLICABLE TO ICs
Human Body Model (HBM)
Simulates the discharge event that occurs when a person
charged to either a positive or negative potential touches an
IC at different potential.
RLC: R = 1.5k , L 0nH, C = 100pF
Machine Model (MM)
Non-real-world Japanese model based on worst-case HBM.
RLC: R 0 , L 500nH, C = 200pF
Charged Device Model (CDM)
Simulates the discharge that occurs when a pin on an IC,
charged to either a positive or negative potential, contacts a
conductive surface at a different (usually ground) potential.
RLC: R = 1 , L 0nH, C= 1 - 20pF
Figure 7.12
The Machine Model (MM) is a wor st -case Human Body Model. Rat her t han using an
average value for r esist ance and capacit ance of t he human body, t he MM assumes a
wor st -case value of 200pF and 0ohms. The 0ohm out put r esist ance of t he MM is also
int ended t o simulat e t he dischar ge fr om a char ged conduct ive object (for example, a
char ged DUT socket on an aut omat ic t est syst em) t o an IC pin, which is how t he
Machine Model ear ned it s name. However , t he MM does not simulat e many known
r eal-wor ld ESD event s. Rat her , it models t he ESD event r esult ing fr om a ideal
volt age sour ce (in ot her wor ds, wit h no r esist ance in t he dischar ge pat h). EIAJ
Specificat ion ED-4701 Test Met hod C-111 Condit ion A and ESD Associat ion
Specificat ion S5.2 pr ovide guidelines for MM t est ing.
The Char ged Device Model (CDM) or iginat ed at AT&T. This model differ s fr om t he
HBM and t he MM, in t hat t he sour ce of t he ESD ener gy is t he IC it self. The CDM
assumes t hat t he int egr at ed cir cuit die, bond wir es, and lead fr ame ar e char ged t o
some pot ent ial (usually posit ive wit h r espect t o gr ound). One or mor e of t he IC pins
t hen cont act s gr ound, and t he st or ed char ge r apidly dischar ges t hr ough t he
leadfr ame and bond wir es. Typical examples of t r iboelect r ic char ging followed by a
CDM dischar ge include:
1
6
1. An IC slides down a handler chut e and t hen a cor ner pin cont act s a gr ounded st op
bar .
2. An IC slides down an open conduct ive shipping t ube and t hen a cor ner pin
cont act s a conduct ive sur face.
The basic concept of t he CDM is differ ent t han t he HBM and MM in t wo ways. Fir st ,
t he CDM simulat es a char ged IC dischar ging t o gr ound, while t he HBM and MM
bot h simulat e a char ged sour ce dischar ging int o t he IC. Thus, cur r ent flows out of
t he IC dur ing CDM t est ing, and int o t he IC dur ing HBM and MM t est ing. The
second differ ence is t hat t he capacit or in t he CDM is t he capacit ance of t he package,
while t he HBM and MM use a fixed ext er nal capacit or .
Unlike t he HBM and MM, CDM ESD t hr esholds may var y for t he same die in
differ ent packages. This occur s because t he device under t est (DUT) capacit ance is a
funct ion of t he package. For example, t he capacit ance of an 8-pin package is
differ ent t han t he capacit ance of a 14-pin package. CDM capacit ance values can var y
fr om about 1 t o 20pF. The device capacit ance is dischar ged t hr ough a 1ohm r esist or .
Schemat ic r epr esent at ions of t he t hr ee models ar e shown in Figur e 7.13. Not ice t hat
C1 in t he HBM and MM ar e ext er nal capacit or s, while C
PKG
in t he CDM is t he
int er nal capacit ance of t he DUT.
The HBM dischar ge wavefor m is a pr edicable unipolar RC pulse, while t he MM
dischar ge shows r inging because of t he par asit ic induct ance in t he dischar ge pat h
(t ypically 500nH.). Ideally, t he CDM wavefor m is also a single unipolar pulse, but
t he par asit ic induct ance in ser ies wit h t he 1ohm r esist or slows t he r ise t ime and
int r oduces some r inging.
SCHEMATIC RESPRESENTATION OF ESD
MODELS AND TYPICAL DISCHARGE WAVEFORMS
Figure 7.13
1
7
The significant feat ur es of each ESD model ar e summar ized in Figur e 7.14. The
peak cur r ent s shown for each model ar e based on a t est volt age of 400V. Peak
cur r ent is lowest for t he HBM because of t he r elat ively high dischar ge r esist ance.
The CDM dischar ge has low ener gy because device capacit ance is only in t he r ange
of 1pF t o 20pF, but peak cur r ent is high. The MM has t he highest ener gy dischar ge,
because it has t he highest capacit ance value (Power = 0.5 CV^2).
COMPARISON OF HBM, MM, AND CDM ESD MODELS
Figure 7.14
Figur e 7.15 compar es 400V dischar ge wavefor ms of t he CDM, MM, and HBM, wit h
t he same cur r ent and t ime scales.
1
8
RELATIVE COMPARISON OF 400V
HBM, MM, AND CDM DISCHARGES
Figure 7.15
The CDM wavefor m cor r esponds t o t he shor t est known r eal-wor ld ESD event . The
wavefor m has a r ise t ime of <1ns, wit h t he t ot al dur at ion of t he CDM event only
about 2ns. The CDM wavefor m is essent ially unipolar , alt hough some r inging occur s
at t he end of t he pulse t hat r esult s in small negat ive-going peaks. The ver y shor t
dur at ion of t he over all CDM event r esult s in an over all dischar ge of r elat ively low
ener gy, but peak cur r ent is high.
The MM wavefor m consist s of bot h posit ive- and negat ive-going sinusoidal peaks,
wit h a r esonance fr equency of 10MHz t o 15MHz. The init ial MM peak has a t ypical
r ise t ime of 14ns, and t he t ot al pulse dur at ion is about 150ns. The mult iple high
cur r ent , moder at e dur at ion peaks of t he MM r esult in an over all dischar ge ener gy
t hat is by far t he highest of t he t hr ee models for a given t est volt age.
The r iset ime for t he unipolar HBM wavefor m is t ypically 6-9ns, and t he wavefor m
decays exponent ially t owar ds 0V wit h a fall t ime of appr oximat ely 150ns. (Met hod
3015 r equir es a r ise t ime of <10ns and a delay t ime of 150ns ± 20ns, wit h decay t ime
defined as t he t ime for t he wavefor m t o dr op fr om 100% t o 36.8% of peak cur r ent ).
The peak cur r ent for t he HBM is 400V/1500ohms, or 0.267A, which is much lower
t han is pr oduced by 400V CDM and MM event s. However , t he r elat ively long
dur at ion of t he t ot al HBM event st ill r esult s in an over all dischar ge of moder at ely
high ener gy.
As pr eviously not ed, t he MM wavefor m is bipolar while HBM and CDM wavefor ms
ar e pr imar ily unipolar . However , HBM and CDM t est ing is done wit h bot h posit ive
and negat ive polar it y pulses. Thus all t hr ee models st r ess t he IC in bot h dir ect ions.
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9
MIL-STD-883 Met hod 3015 classifies ICs for ESD failur e t hr eshold. The
classificat ion limit s, shown in Figur e 7.16, ar e der ived using t he HBM shown in
Figur e 7.13. Met hod 3015 also mandat es a mar king met hod t o denot e t he ESD
classificat ion. All milit ar y gr ade Class 1 and 2 devices have t heir packages mar ked
wit h one or t wo “Delt a” symbols, r espect ively, while class 3 devices (wit h a failur e
t hr eshold >4kV) do not have any ESD mar king. Commer cial and indust r ial gr ade IC
packages may not be mar ked wit h any ESD classificat ion symbol.
CLASSIFYING AND MARKING ICs FOR ESD
PER MIL-883C, METHOD 3015
Figure 7.16
Not ice t hat t he Class 1 limit includes all devices which do not pass a 2kV t hr eshold.
However , a Class 1 r at ing does not imply t hat all devices wit hin t hat class will pass
1,999V. In any event , t he emphasis must be placed on eliminat ing ESD exposur e,
not on at t empt ing t o decide how much ESD exposur e is ‘safe.’
A det ailed discussion of IC failur e mechanisms is beyond t he scope of t his seminar ,
but some t ypical ESD effect s ar e shown in Figur e 7.17.
UNDERSTANDING ESD DAMAGE
ESD Failure Mechanisms:

Dielectric or junction damage
Surface charge accumulation
Conductor fusing.
ESD Damage Can Cause:
Increased leakage
Reduced performance
Functional failures of ICs.
ESD Damage is often Cumulative:

For example, each ESD “zap” may increase junction
damage until, finally, the device fails.
Figure 7.17
2
0
For t he design engineer or t echnician, t he most common manifest at ion of ESD
damage is a cat ast r ophic failur e of t he IC. However , exposur e t o ESD can also cause
incr eased leakage or degr ade ot her par amet er s. If a device appear s t o not meet a
dat a sheet specificat ion dur ing evaluat ion, t he possibilit y of ESD damage should be
consider ed.
Special car e should be t aken when br eadboar ding and evaluat ing ICs. The effect s of
ESD damage can be cumulat ive, so r epeat ed mishandling of a device can event ually
cause a failur e. Inser t ing and r emoving ICs fr om a t est socket , st or ing devices
dur ing evaluat ion, and adding or r emoving ext er nal component s on t he br eadboar d
should all be done while obser ving pr oper ESD pr ecaut ions. Again, if a device fails
dur ing a pr ot ot ype syst em development , r epeat ed ESD st r ess may be t he cause.
The key wor d t o r emember wit h r espect t o ESD is prevention. Ther e is no way t o un-
do ESD damage, or t o compensat e for it s effect s.
THE MOST IMPORTANT THING TO
REMEMBER ABOUT ESD DAMAGE
ESD DAMAGE CANNOT BE “CURED”!
Circuits cannot be tweaked, nulled, adjusted, etc., to compensate
for ESD damage.

ESD DAMAGE MUST BE PREVENTED!
Figure 7.18
Since ESD damage can not be undone, t he only cur e is pr event ion. Luckily,
pr event ion is a simple t wo-st ep pr ocess. The fir st st ep is r ecognizing ESD-sensit ive
pr oduct s, and t he second st ep is under st anding how t o handle t hese pr oduct s.
PREVENTING ESD DAMAGE TO ICs
Two key elements in protecting circuits from ESD damage
are:
Recognizing ESD-sensitive products
Always handling ESD-sensitive products at a grounded
workstation.
Figure 7.19
All st at ic sensit ive devices ar e shipped in pr ot ect ive packaging. ICs ar e usually
cont ained in eit her conduct ive foam or in ant ist at ic t ubes. Eit her way, t he cont ainer
is t hen sealed in a st at ic-dissipat ive plast ic bag. The sealed bag is mar ked wit h a
dist inct ive st icker , such as is shown in Figur e 7.20, which out lines t he appr opr iat e
handling pr ocedur es.
2
1
RECOGNiZING ESD-SENSITIVE DEVICES
Figure 7.20
Once ESD-sensit ive devices ar e ident ified, pr ot ect ion is easy. Obviously, keeping ICs
in t heir or iginal pr ot ect ive packaging as long as possible is t he fir st st ep. The second
st ep is t o dischar ge pot ent ial ESD sour ces befor e damage t o t he IC can occur . The
HBM capacit ance is only 100pF, so dischar ging a pot ent ially danger ous volt age can
be done quickly and safely t hr ough a high impedance. Even wit h a sour ce r esist ance
of 10Megohms, t he 100pF will be dischar ged in less t han 100milliseconds.
The key component r equir ed for safe ESD handling is a wor kbench wit h a st at ic-
dissipat ive sur face, as shown in Figur e 7.21. This sur face is connect ed t o gr ound
t hr ough a 1Megohm r esist or , which dissipat es st at ic char ge while pr ot ect ing t he
user fr om elect r ical shock hazar ds caused by gr ound fault s. If exist ing bench t ops
ar e nonconduct ive, a st at ic-dissipat ive mat should be added, along wit h a dischar ge
r esist or .
2
2
WORKSTATION FOR HANDLING
ESD-SENSITIVE DEVICES
Figure 7.21
Not ice t hat t he sur face of t he wor kbench has a moder at ely high sheet r esist ance. It
is neit her necessar y nor desir able t o use a low-r esist ance sur face (such as a sheet of
copper -clad PC boar d) for t he wor k sur face. Remember , t he CDM assumes t hat a
high peak cur r ent will flow if a char ged IC is dischar ged t hr ough a low impedance.
This is pr ecisely what happens when a char ged IC cont act s a gr ounded copper clad
boar d. When t he same char ged IC is placed on t he sur face shown in Figur e 7.21,
however , t he peak cur r ent is not high enough t o damage t he device.
A conduct ive wr ist st r ap is also r ecommended while handling ESD-sensit ive devices.
The wr ist st r ap ensur es t hat nor mal t asks, such as peeling t ape off of packages, will
not cause damage t o ICs. Again, a 1Megohm r esist or , fr om t he wr ist st r ap t o gr ound,
is r equir ed for safet y.
When building pr ot ot ype br eadboar ds or assembling PC boar ds which cont ain ESD-
sensit ive devices, all passive component s should be inser t ed and solder ed befor e t he
ICs. This pr ocedur e minimizes t he ESD exposur e of t he sensit ive devices. The
solder ing ir on must , of cour se, have a gr ounded t ip.
Pr ot ect ing ICs fr om ESD r equir es t he par t icipat ion of bot h t he IC manufact ur er and
t he cust omer . IC manufact ur er s have a vest ed int er est in pr oviding t he highest
possible level of ESD pr ot ect ion for t heir pr oduct s. IC cir cuit designer s, pr ocess
engineer s, packaging specialist s and ot her s ar e const ant ly looking for new and
impr oved cir cuit designs, pr ocesses, and packaging met hods t o wit hst and or shunt
ESD ener gy (Figur e 7.22)
2
3
ANALOG DEVICES’ COMMITMENT
Analog Devices is committed to helping our customers prevent
ESD damage by:

Building products with the highest level of ESD protection
commensurate with performance requirements
Protecting products from ESD during shipment
Helping customers to avoid ESD exposure during
manufacture
Figure 7.22
A complet e ESD pr ot ect ion plan, however , r equir es mor e t han building-ESD
pr ot ect ion int o ICs. User s of ICs must also pr ovide t heir employees wit h t he
necessar y knowledge of and t r aining in ESD handling pr ocedur es (Figur e 7.23).
ESD PROTECTION REQUIRES A PARTNERSHIP
BETWEEN THE IC SUPPLIER AND THE CUSTOMER
ANALOG DEVICES:
Circuit Design and Fabrication -
Design and manufacture products with the highest level
of ESD protection consistent with required analog and
digital performance.
Pack and Ship -
Pack in static dissipative material. Mark packages with
ESD warning.
CUSTOMERS:
Incoming Inspection -
Inspect at grounded workstation. Minimize handling.
Inventory Control -
Store in original ESD-safe packaging. Minimize Handling.
Manufacturing -
Deliver to work are in original ESD-safe packaging. Open
packages only at grounded workstation. Package
subassemblies in static dissipative packaging.
Pack and Ship -
Pack in static dissipative material if required.
Replacement or optional boards may require special
attention.
Figure 7.23
2
4
The ESD P r ot ect i on Ma n u a l is available fr om Analog Devices’ lit er at ur e
depar t ment . This manual pr ovides addit ional infor mat ion on st at ic-dissipat ive wor k
sur faces, packaging mat er ials, pr ot ect ive clot hing, ESD t r aining, and ot her subject s.
ESD PROTECTION MANUAL
Contact Analog Devices’ literature department for a
copy of the ESD Prevention Manual, which has
further information on:
Handling Instructions
Packaging
Static-Safe Facilities
Other ESD Issues
Figure 7.24
2
5
REFERENCES
1. Amp li fi er Ap p li ca t i on s Gu i d e, Sect ion XI, pp. 1-10, Analog Devices,
Incor por at ed, Nor wood, MA, 1992.
2. Syst ems Ap p li ca t i on s Gu i d e, Sect ion 1, pp. 56-72, Analog Devices,
Incor por at ed, Nor wood, MA, 1993.
3. Li n ea r Desi gn Semi n a r , Sect ion 1, pp. 19-22, Analog Devices,
Incor por at ed, Nor wood, MA, 1994.
4. ESD P r even t i on Ma n u a l, Analog Devices, Inc.
5. MIL-S TD-883 Method 3015, Electrostatic Discharge S ensitivity
Classification. Available fr om St andar dizat ion Document Or der Desk,
700 Robbins Ave., Building #4, Sect ion D, Philadelphia, PA 19111-5094.
6. EIAJ ED-4701 Test Method C-111, Electrostatic Discharges. Available fr om
t he J apan Elect r onics Bur eau, 250 W 34t h St ., New Yor k NY 10119, At t n.:
Tomoko.
7. ES D Association S tandard S 5.2 for Electrostatic Discharge (ES D) S ensitivity
Testing -Machine Model (MM)- Component Level. Available fr om t he ESD
Associat ion, Inc., 200 Liber t y Plaza, Rome, NY 13440.
8. ES D Association Draft S tandard DS 5.3 for Electrostatic Discharge (ES D)
S ensitivity Testing - Charged Device Model (CDM) Component Testing.
Available fr om t he ESD Associat ion, Inc., 200 Liber t y Plaza, Rome, NY
13440.
9. Niall Lyne, Electrical Overstress Damage to CMOS Converters, Ap p li ca t i on
Not e AN-397, Analog Devices, 1995.
1
SECTION 8
DISTORTION MEASUREMENTS
High Speed Op Amp Distortion
High Frequency Two-Tone Generation
Using Spectrum Analyzers in High Frequency
Low Distortion Measurements
Measuring ADC Distortion using FFTs
FFT Testing
Troubleshooting the FFT Output
Analyzing the FFT Output
2
SECTI ON 8
DI STORTI ON MEASUREMENTS
HI GH SP EED OP AMP DI STORTI ON
Wa l t Kest er
Dynamic r ange of an op amp may be defined in sever al ways. The most common
ways ar e t o specify Har monic Dist or t ion, Tot al Har monic Dist or t ion (THD), or Tot al
Har monic Dist or t ion Plus Noise (THD + N).
Har monic dist or t ion is measur ed by applying a spect r ally pur e sinewave t o an op
amp in a defined cir cuit configur at ion and obser ving t he out put spect r um. The
amount of dist or t ion pr esent in t he out put is usually a funct ion of sever al
par amet er s: t he small- and lar ge-signal nonlinear it y of t he amplifier being t est ed,
t he amplit ude and fr equency of t he input signal, t he load applied t o t he out put of t he
amplifier , t he amplifier 's power supply volt age, pr int ed cir cuit boar d layout ,
gr ounding, power supply decoupling, et c. Ther efor e, any dist or t ion specificat ion is
r elat ively meaningless unless t he exact t est condit ions ar e specified.
Har monic dist or t ion may be measur ed by looking at t he out put spect r um on a
spect r um analyzer and obser ving t he values of t he second, t hir d, four t h, et c.,
har monics wit h r espect t o t he amplit ude of t he fundament al signal. The value is
usually expr essed as a r at io in %, ppm, dB, or dBc. For inst ance, 0.0015% dist or t ion
cor r esponds t o 15ppm, or –96.5dBc. The unit "dBc" simply means t hat t he
har monic's level is so many dB below t he value of t he "car r ier " fr equency, i.e., t he
fundament al.
Har monic dist or t ion may be expr essed individually for each component (usually only
t he second and t hir d ar e specified), or t hey all may be combined in a r oot -sum-
squar e (RSS) fashion t o give t he Tot al Har monic Dist or t ion (THD). The dist or t ion
component which makes up Tot al Har monic Dist or t ion is usually calculat ed by
t aking t he r oot sum of t he squar es of t he fir st five or six har monics of t he
fundament al. In many pr act ical sit uat ions, however , t her e is negligible er r or if only
t he second and t hir d har monics ar e included. This is because t he RSS pr ocess causes
t he higher -or der t er ms t o have negligible effect on t he THD, if t hey ar e 3 t o 5 t imes
smaller t han t he lar gest har monic. For example,
010
2
003
2
00109 0104 01 . . . . . + = = ≈
3
DEFINITIONS OF THD AND THD + N
Figure 8.1
It is impor t ant t o not e t hat t he THD measur ement does not include noise t er ms,
while THD + N does. The noise in t he THD + N measur ement must be int egr at ed
over t he measur ement bandwidt h. In audio applicat ions, t he bandwidt h is nor mally
chosen t o be ar ound 100kHz. In nar r ow-band applicat ions, t he level of t he noise may
be r educed by filt er ing. On t he ot her hand, har monics and int er modulat ion pr oduct s
which fall wit hin t he measur ement bandwidt h cannot be filt er ed, and t her efor e may
limit t he syst em dynamic r ange. It should be evident t hat t he THD+N
appr oximat ely equals THD if t he r ms noise over t he measur ement bandwidt h is
sever al t imes less t han t he THD, or even t he wor st har monic. It is wor t h not ing t hat
if you know only t he THD, you can calculat e t he THD+N fair ly accur at ely using t he
amplifier 's volt age- and cur r ent -noise specificat ions. (Ther mal noise associat ed wit h
t he sour ce r esist ance and t he feedback net wor k may also need t o be comput ed). But
if t he r ms noise level is significant ly higher t han t he level of t he har monics, and you
ar e only given t he THD+N specificat ion, you cannot comput e t he THD.
Special equipment is oft en used in audio applicat ions for a mor e sensit ive
measur ement of t he noise and dist or t ion. This is done by fir st using a bandst op filt er
t o r emove t he fundament al signal (t his is t o pr event over dr ive dist or t ion in t he
measur ing inst r ument ). The t ot al r ms value of all t he ot her fr equency component s
(har monics and noise) is t hen measur ed over an appr opr iat e bandwidt h. The r at io t o
t he fundament al is t he THD+N specificat ion.
Audio fr equency amplifier s (such as t he OP-275) ar e opt imized for low noise and low
dist or t ion wit hin t he audio bandwidt h (20Hz t o 20kHz). In audio applicat ions, t ot al
har monic dist or t ion plus noise (THD+N) is usually measur ed wit h specialized
equipment , such as t he Audio Pr ecision Syst em One. The out put signal amplit ude is
measur ed at a given fr equency (e.g., 1kHz); t hen t he fundament al signal is r emoved
wit h a bandst op filt er , and t he syst em measur es t he r ms value of t he r emaining
fr equency component s, which cont ain bot h har monics and noise. The noise and
har monics ar e measur ed over a bandwidt h t hat will include t he highest har monics,
4
usually about 100kHz. The measur ement is swept over t he fr equency r ange for
var ious condit ions.
THD+N r esult s for t he OP-275 ar e plot t ed in Figur e 8.2 as a funct ion of fr equency.
The signal level is 3V r ms, and t he amplifier is connect ed as a unit y-gain follower .
The dat a is shown for t hr ee load condit ions: 600ohm, 2kohm, and 10kohm. Not ice
t hat a THD+N value of 0.0008% cor r esponds t o 8ppm, or –102dBc. The input volt age
noise of t he OP-275 is t ypically 6nV/r t Hz @1kHz, and int egr at ed over an 80kHz
noise bandwidt h, yields an r ms noise level of 1.7µV r ms. For a 3V r ms signal level,
t he cor r esponding signal-t o-noise r at io is 125dB. Because t he THD is consider ably
gr eat er t han t he noise level, t he THD component is t he pr imar y cont r ibut or .
Mult iple plot s wit h var iable bandwidt hs can be used t o help separ at e noise and
dist or t ion.
THD + N FOR THE OP -275 OVER 100kHz BANDWIDTH
IS DOMINATED BY DISTORTION
Figure 8.2
Now, consider t he AD797, a low noise amplifier (1nV/r t Hz) wher e measur ement
equipment dist or t ion, and not t he amplifier dist or t ion, limit s t he measur ement . The
THD specificat ion for t he AD797 is 120dBc @20kHz, and a plot is shown in Figur e
8.3. The dist or t ion is at t he limit s of measur ement of available equipment , and t he
act ual amplifier noise is even lower by 20dB. The measur ement was made wit h a
spect r um analyzer by fir st filt er ing out t he fundament al sinewave fr equency ahead
of t he analyzer . This is t o pr event over dr ive dist or t ion in t he spect r um analyzer . The
fir st five har monics wer e t hen measur ed and combined in an RSS fashion t o get t he
THD figur e. The legend on t he gr aph indicat es t hat t he measur ement equipment
"floor " is about 120dBc; hence at fr equencies below 10kHz, t he THD may be even
less.
5
THD OF THE AD797 OP AMP SHOWS MEASUREMENT LIMIT
AT -120dBc, WHILE AMPLIFIER NOISE FLOOR IS AT -140dBc
(1nV/ Hz INTEGRATED OVER 100kHz BANDWIDTH)
Figure 8.3
To calculat e t he AD797 noise, mult iply t he volt age noise spect r al densit y (1nV/r t Hz)
by t he squar e r oot of t he measur ement bandwidt h t o yield t he device's r ms noise
floor . For a 100kHz bandwidt h, t he noise floor is 316nV r ms, cor r esponding t o a
signal-t o-noise r at io of about 140dB for a 3V r ms out put signal.
Rat her t han simply examining t he THD pr oduced by a single t one sinewave input , it
is oft en useful t o look at t he dist or t ion pr oduct s pr oduced by t wo t ones. As shown in
Figur e 8.4, t wo t ones will pr oduce second and t hir d or der int er modulat ion pr oduct s.
The example shows t he second and t hir d or der pr oduct s pr oduced by applying t wo
fr equencies, f
1
and f
2
, t o a nonlinear device. The second or der pr oduct s locat ed at f
2
+ f
1
and f
2
– f
1
ar e locat ed far away fr om t he t wo t ones, and may be r emoved by
filt er ing. The t hir d or der pr oduct s locat ed at 2f
1
+ f
2
and 2f
2
+ f
1
may likewise be
filt er ed. The t hir d or der pr oduct s locat ed at 2f
1
– f
2
and 2f
2
– f
1
, however , ar e close
t o t he or iginal t ones, and filt er ing t hem is difficult . Thir d or der IMD pr oduct s ar e
especially t r oublesome in mult i-channel communicat ions syst ems wher e t he channel
separ at ion is const ant acr oss t he fr equency band.
6
SECOND AND THIRD-ORDER INTERMODULATION
PRODUCTS FOR f
1
= 5MHz and f
2
= 6MHz
Figure 8.4
Int er modulat ion dist or t ion pr oduct s ar e of special int er est in t he RF ar ea, and a
major concer n in t he design of r adio r eceiver s. Thir d-or der IMD pr oduct s can mask
out small signals in t he pr esence of lar ger ones. Thir d or der IMD is oft en specified in
t er ms of t he third order intercept point as shown in Figur e 8.5. Two spect r ally pur e
t ones ar e applied t o t he syst em. The out put signal power in a single t one (in dBm) as
well as t he r elat ive amplit ude of t he t hir d-or der pr oduct s (r efer enced t o a single
t one) is plot t ed as a funct ion of input signal power . If t he syst em non-linear it y is
appr oximat ed by a power ser ies expansion, t he second-or der IMD amplit udes
incr ease 2dB for ever y 1dB of signal incr ease. Similar ly, t he t hir d-or der IMD
amplit udes incr ease 3dB for ever y 1dB of signal incr ease. Wit h a low level t wo-t one
input signal, and t wo dat a point s, dr aw t he second and t hir d or der IMD lines as ar e
shown in Figur e 8.5, because one point and a slope det er mine each st r aight line.
Once t he input r eaches a cer t ain level, however , t he out put signal begins t o soft -
limit , or compr ess. But t he second and t hir d-or der int er cept lines may be ext ended
t o int er sect t he ext ension of t he out put signal line. These int er sect ions ar e called t he
second- and third order intercept points, r espect ively. The values ar e usually
r efer enced t o t he out put power of t he device expr essed in dBm. Anot her par amet er
which may be of int er est is t he 1dB compression point. This is t he point at which t he
out put signal is compr essed by 1dB fr om t he ideal input /out put t r ansfer funct ion.
This point is also shown in Figur e 8.5.
I
7
NTERCEPT POINTS, GAIN COMPRESSION, AND IMD
Figure 8.5
Knowing t he t hir d or der int er cept point allows calculat ion of t he appr oximat e level
of t he t hir d-or der IMD pr oduct s as a funct ion of out put signal level. Figur e 8.6
shows t he t hir d or der int er cept value as a funct ion of fr equency for t he AD9622
volt age feedback amplifier .
8
AD9622 THIRD ORDER IMD INTERCEPT
VERSUS FREQUENCY
Figure 8.6
Assume t he op amp out put signal is 5MHz and 2V peak-t o-peak int o a 100ohm load
(50ohm sour ce and load t er minat ion). The volt age int o t he 50ohm load is t her efor e
1V peak-t o-peak, cor r esponding t o +4dBm. The value of t he t hir d or der int er cept at
5MHz is 36dBm. The differ ence bet ween +36dBm and +4dBm is 32dB. This value is
t hen mult iplied by 2 t o yield 64dB (t he value of t he t hir d-or der int er modulat ion
pr oduct s r efer enced t o t he power in a single t one). Ther efor e, t he int er modulat ion
pr oduct s should be –64dBc (dB below car r ier fr equency), or at a level of –60dBm.
Figur e 8.7 shows t he gr aphical analysis for t his example.
9
USING THE THIRD ORDER INTERCEPT POINT
TO CALCULATE IMD PRODUCT FOR THE AD9622 OP AMP
Figure 8.7
HI GH F REQUENCY TWO-TONE GENERATI ON
Gener at ing t est signals wit h t he spect r al pur it y r equir ed t o make low dist or t ion high
fr equency measur ement s is a challenging t ask. A t est set up for gener at ing a single
t one is shown in Figur e 8.8. The sinewave oscillat or should have low phase noise
(e.g., Mar coni 2382), especially if t he device under t est is an ADC, wher e phase noise
incr eases t he ADC noise floor . The out put of t he oscillat or is passed t hr ough a
bandpass (or lowpass) filt er which r emoves any har monics pr esent in t he oscillat or
out put . The dist or t ion should be 6dB lower t han t he desir ed accur acy of t he
measur ement . The 6dB at t enuat or isolat es t he DUT fr om t he out put of t he filt er .
The impedance at each int er face should be maint ained at 50ohms for best
per for mance (75ohm component s can be used, but 50ohm at t enuat or s and filt er s ar e
gener ally mor e r eadily available). The t er minat ion r esist or , R
T
, is select ed so t hat
t he par allel combinat ion of R
T
and t he input impedance of t he DUT is 50ohms.
LOW DISTORTION SINGLE-TONE GENERATOR
Figure 8.8
1
0
Befor e per for ming t he act ual dist or t ion measur ement , t he oscillat or out put should
be set t o t he cor r ect fr equency and amplit ude. Measur e t he dist or t ion at t he out put
of t he at t enuat or wit h t he DUT r eplaced by a 50ohm t er minat ion r esist or (gener ally
t he 50ohm input of a spect r um analyzer . Next , r eplace t he 50ohm load wit h R
T
and
t he DUT. Measur e t he dist or t ion at t he DUT input a second t ime. This allows non-
linear DUT loads t o be ident ified. Non-linear DUT loads (such as flash ADCs wit h
signal-dependent input capacit ance, or swit ched-capacit or CMOS ADCs) can
int r oduce dist or t ion at t he DUT input .
Gener at ing t wo t ones suit able for IMD measur ement s is even mor e difficult . A low-
dist or t ion t wo-t one gener at or is shown in Figur e 8.9. Two bandpass (or lowpass)
filt er s ar e r equir ed as shown. Har monic suppr ession of each filt er must be bet t er
t han t he desir ed measur ement accur acy by at least 6dB. A 6dB at t enuat or at t he
out put of each filt er ser ves t o isolat e t he filt er out put s fr om each ot her and pr event
possible cr oss-modulat ion. The out put s of t he at t enuat or s ar e combined in a passive
50ohm combining net wor k, and t he combiner dr ives t he DUT. The oscillat or out put s
ar e set t o t he r equir ed level, and t he IMD of t he final out put of t he combiner is
measur ed. The measur ement should be made wit h a single t er minat ion r esist or , and
again wit h t he DUT connect ed t o ident ify non-linear loads.
LOW DISTORTION TOW TONE GENERATOR
Figure 8.9
USI NG SP ECTRUM ANALYZERS I N HI GH FREQUENCY
LOW DI STORTI ON MEASUREMENTS
Analog spect r um analyzer s ar e most oft en used t o measur e amplifier dist or t ion.
Most have 50ohm input s, t her efor e an isolat ion r esist or bet ween t he device under
t est (DUT) and t he analyzer is r equir ed t o simulat e DUT loads gr eat er t han 50ohms.
Aft er adjust ing t he spect r um analyzer for bandwidt h, sweep r at e, and sensit ivit y,
check it car efully for input over dr ive. The simplest met hod is t o use t he var iable
at t enuat or t o int r oduce 10dB of at t enuat ion in t he analyzer input pat h. Bot h t he
signal and any har monics should be at t enuat ed by a fixed amount (10dB, for
inst ance) as obser ved on t he scr een of t he spect r um analyzer . If t he har monics ar e
at t enuat ed by mor e t han 10dB, t hen t he input amplifier of t he analyzer is
int r oducing dist or t ion, and t he sensit ivit y should be r educed. Many analyzer s have a
1
1
but t on on t he fr ont panel for int r oducing a known amount of at t enuat ion when
checking for over dr ive.
MEASURING AMPLIFIER DISTORTION REQUIRES
CARE TO PREVENT ANALYZER OVERDRIVE
Figure 8.10
Anot her met hod t o minimize sensit ivit y t o over dr ive is shown in Figur e 8.11. The
amplit ude of t he fundament al signal is fir st measur ed wit h t he not ch filt er swit ched
out . The har monics ar e measur ed wit h t he not ch filt er swit ched in. The inser t ion
loss of t he not ch filt er , XdB, must be added t o t he measur ed level of t he har monics.
1
2
NOTCH FILTER REMOVES THE FUNDAMENTAL
SIGNAL TO MINIMIZE ANALYZER OVERDRIVE
Figure 8.11
MEASURI NG ADC DI STORTI ON USI NG FFTS
The speed of per sonal comput er s and t he availabilit y of suit able soft war e now makes
DSP bench t est ing of high speed ADCs r elat ively easy. A block diagr am of a t ypical
DSP PC-based t est syst em is shown in Figur e 8.12. In or der t o per for m any DSP
t est ing, t he fir st r equir ement is a high speed buffer memor y of sufficient widt h and
dept h. High speed logic analyzer s make a convenient memor y and eliminat e t he
need for designing special har dwar e. The HP1663A is a 100MHz logic analyzer
which has a simple IEEE-488 out put por t for easy int er facing t o a per sonal
comput er . The analyzer can be configur ed as eit her a 16-bit wide by 8k deep, or a 32-
bit wide by 4k deep memor y. This is mor e t han sufficient t o t est a high speed ADC at
sample r at es up t o 100MHz. For higher sample r at es, fast er logic analyzer s ar e
available, but ar e fair ly cost ly. An alt er nat ive t o using a high speed logic analyzer is
t o oper at e t he ADC at t he desir ed sample r at e, but only clock t he final out put
r egist er at an even sub-mult iple of t he sample clock fr equency. This is somet imes
called decimation and is useful for r elaxing memor y r equir ement s. If an FFT is
per for med on t he decimat ed out put dat a, t he fundament al input signal and it s
associat ed har monics will be pr esent , but t r anslat ed in fr equency. Simple algor it hms
can be used t o find t he locat ions of t he signal and it s har monics pr ovided t he
or iginal signal fr equency is known.
1
3
A SIMPLE PC-BASED TEST SYSTEM
Figure 8.12
FFT TESTI NG
Easy t o use mat hemat ical soft war e packages, such as Mat hcad™ (available fr om
Mat hSoft , Inc., 201 Br oadway, Cambr idge MA, 02139) ar e available t o per for m fast
FFTs on most 486-based PCs. The use of a co-pr ocessor allows a 4096-point FFT t o
r un in a few seconds on a 75MHz,486 PC. The ent ir e syst em will r un under t he
Windows envir onment and pr ovide gr aphical displays of t he FFT out put spect r um.
It can be pr ogr ammed t o per for m SNR, S/(N+D), THD, IMD, and SFDR
comput at ions. A simple QuickBasic pr ogr am t r ansfer s t he dat a st or ed in t he logic
analyzer int o a file in t he PC via t he IEEE-488 por t (Refer ence 3, Sect ion 16).
Pr oper ly under st anding of FFT fundament als is necessar y in or der t o achieve
meaningful r esult s. The fir st st ep is t o det er mine t he number of samples, M, in t he
FFT r ecor d lengt h. In or der for t he FFT t o r un pr oper ly, M must be a power of 2.
The value of M det er mines t he fr equency bin width, Delt a f = f
s
/M. The lar ger M, t he
mor e fr equency r esolut ion. Figur e 8.13 shows t he r elat ionship bet ween t he aver age
noise floor of t he FFT wit h r espect t o t he br oadband quant izat ion noise level. Each
t ime M is doubled, t he aver age noise in t he Delt a f bandwidt h decr eases by 3dB.
Lar ger values of M also t end t o give mor e r epeat able r esult s fr om r un t o r un (see
Figur e 8.13).
1
4
RELATIONSHIP BETWEEN AVERAGE NOISE IN FFT BINS
AND BROADBAND RMS QUANTIZATION NOISE LEVEL
Figure 8.13
M values of 512 (for 8-bit ADCs), 2048 (for 10-bit ADCs), and 4096 (for 12-bit ADCs)
have pr oven t o give good accur acy and r epeat abilit y. For ext r emely wide dynamic
r ange applicat ions (such as spect r al analysis) M=8192 may be desir able. It should be
not ed t hat aver aging t he r esult s of sever al FFTs will t end t o smoot h out t he noise
floor , but will not change t he aver age value of t he floor .
In or der t o obt ain spect r ally pur e r esult s, t he FFT dat a window must cont ain an
exact int egr al number of sinewave cycles as shown in Figur e 8.14. These fr equency
r at ios must be pr ecisely obser ved t o pr event end-point discont inuit y. In addit ion, it
is desir able t hat t he number of sinewave cycles cont ained wit hin t he dat a window be
a pr ime number . This met hod of FFT t est ing is r efer r ed t o as coherent t est ing
because t wo locked fr equency synt hesizer s ar e used t o insur e t he pr oper r at io
(coher ence) bet ween t he sampling clock and t he sinewave fr equency. The
r equir ement s for coher ent sampling ar e summar ized in Figur e 8.15.
1
5
FFT OF SINEWAVE HAVING INTEGRAL
NUMBER OF CYCLES IN WINDOW
Figure 8.14
REQUIREMENTS FOR COHERENT SAMPLING
f
s
= Sampling Rate
f
in
= Input Sinewave Frequency
M = Number of Samples in Record (Integer Power of 2)
M
c
= Prime Integer Number of Cycles of Sinewave During
Record (Makes All Samples Unique)
Make f
in
/ f
s
= M
c
/ M
Figure 8.15
Making t he number of cycles wit hin t he r ecor d a pr ime number ensur es a unique set
of sample point s wit hin t he dat a window. An even number of cycles wit hin t he
r ecor d lengt h will cause t he quant izat ion noise ener gy t o be concent r at ed in t he
har monics of t he fundament al (causing a decr ease in SFDR) r at her t han being
r andomly dist r ibut ed over t he Nyquist bandwidt h. Figur e 8.16 shows a 4096-point
FFT out put for a t heor et ically per fect 12-bit sinewave. The spect r um on t he left was
made wit h exact ly 128 samples wit hin t he r ecor d lengt h, cor r esponding t o a
fr equency which is 1/32 t imes f
s
. The SFDR is 78dB. The spect r um on t he r ight was
made wit h exact ly 127 samples wit hin t he r ecor d, and t he SFDR incr eases t o 92dB.
1
6
CHOOSING A PRIME NUMBE OF CYCLES WITHIN THE
FFT RECORD LENGTH ENSURES RANDOMIZATION OF
THE QUANTIZATION NOISE (IDEAL 12-BIT ADC)
Figure 8.16
Coher ent FFT t est ing ensur es t hat t he fundament al signal occupies one discr et e line
in t he out put spect r um. Any leakage or smear ing int o adjacent bins is t he r esult of
aper t ur e jit t er , phase jit t er on t he sampling clock, or ot her unwant ed noise due t o
impr oper layout , gr ounding, or decoupling.
If t he r at io bet ween t he sampling clock and t he sinewave fr equency is such t hat
t her e is and endpoint discont inuit y in t he dat a (shown in Figur e 8.17), t hen spect r al
leakage will occur . The discont inuit ies ar e equivalent t o mult iplying t he sinewave
by a r ect angular windowing pulse which has a sin(x)/x fr equency r esponse. The
discont inuit ies in t he t ime domain r esult in leakage or smear ing in t he fr equency
domain, because many spect r al t er ms ar e needed t o fit t he discont inuit y. Because of
t he endpoint discont inuit y, t he FFT spect r al r esponse shows t he main lobe of t he
sinewave being smear ed, and a lar ge number of associat ed sidelobes which have t he
basic char act er ist ics of t he r ect angular t ime pulse. This leakage must be minimized
using a t echnique called windowing (or weighting) in or der t o obt ain usable r esult s
in non-coher ent t est s.
1
7
FFT OF SINEWAVE HAVING NON-INTEGRAL
NUMBER OF CYCLES IN WINDOW
Figure 8.17
This sit uat ion is exact ly what occur s in r eal-wor ld spect r al analysis applicat ions
wher e t he exact fr equencies being sampled ar e unknown and uncont r ollable.
Sidelobe leakage is r educed by choosing a windowing (or weighting) funct ion ot her
t han t he r ect angular window. The input t ime samples ar e mult iplied by an
appr opr iat e windowing funct ion which br ings t he signal t o zer o at t he edges of t he
window. The select ion of an appr opr iat e windowing funct ion is pr imar ily a t r adeoff
bet ween main-lobe spr eading and sidelobe r olloff.
The t ime-domain and fr equency-domain char act er ist ics of a simple windowing
funct ion (t he Hanning Window) ar e shown in Figur e 8.18. A compar ison of t he
fr equency r esponse of t he Hanning window and t he mor e sophist icat ed Minimum 4-
Ter m Blackman-Har r is window is given in Figur es 8.19 and 8.20. For gener al ADC
t est ing wit h non-coher ent input fr equencies, t he Hanning window will give
sat isfact or y r esult s. For cr it ical spect r al analysis or t wo-t one IMD t est ing, t he
Minimum 4-Ter m Blackman-Har r is window is t he bet t er choice because of t he
incr ease in spect r al r esolut ion.
1
8
TIME AND FREQUENCY
REPRESENTATION OF THE HANNING WINDOW
Figure 8.18
FREQUENCY RESPONSE OF THE HANNING WINDOW
Figure 8.19
1
9
FREQUENCY RESPONSE OF THE
MINIMUM 4-TERM BLACKMAN-HARRIS WINDOW
Figure 8.20
The addit ion of a windowing funct ion t o t he FFT soft war e involves fir st calculat ing
t he pr oper coefficient for each t ime sample wit hin t he r ecor d. These values ar e t hen
st or ed in a memor y file. Each t ime sample is mult iplied by it s appr opr iat e weight ing
coefficient befor e per for ming t he act ual FFT. The soft war e r out ine is easy t o
implement in QuickBasic.
When analyzing t he FFT out put r esult ing fr om windowing t he input dat a samples,
car e must be exer cised in det er mining t he ener gy in t he fundament al signal and t he
ener gy in t he var ious spur ious component s. For example, sidelobe ener gy fr om t he
fundament al signal should not be included in t he r ms noise measur ement . Consider
t he case of t he Hanning Window funct ion being used t o t est a 12-bit ADC wit h a
t heor et ical SNR of 74dB. The sidelobe at t enuat ion of t he Hanning Window is as
follows:
Bins Fr om Sidelobe
Fundament al At t enuat ion
2.5 32dB
5.0 50dB
10.0 68dB
20.0 86dB
Ther efor e, in calculat ing t he r ms value of t he fundament al signal, you should
include at least 20 samples on eit her side of t he fundament al as well as t he
fundament al it self.
If ot her weight ing funct ions ar e used, t heir par t icular sidelobe char act er ist ics must
be known in or der t o accur at ely calculat e signal and noise levels.
2
0
A t ypical Mat hcad™ FFT out put plot is shown in Figur e 8.21 for t he AD9022 12-bit ,
20MSPS ADC using t he Hanning Window and a r ecor d lengt h of 4096.
MATHCAD 4096 POINT FFT OUTPUTS FOR
AD9022 12-BIT, 20 MSPS ADC (HANNING WEIGHTING)
Figure 8.21
The act ual QuickBasic r out ine for t r ansfer r ing t he HP analyzer 's dat a t o a DOS file
in t he PC as well as t he Mat hcad™ r out ine ar e given in Refer ence 3, Sect ion 16.
TROUBLESHOOTI NG THE FFT OUTP UT
Er r oneous r esult s ar e oft en obt ained t he fir st t ime an FFT t est set up is put t oget her .
The most common er r or is impr oper t iming of t he lat ch st r obe t o t he buffer memor y.
The HP1663A logic analyzer accept s par allel dat a and a clock signal. It has an
int er nal DAC which may be used t o examine a r ecor d of t ime samples. Lar ge
glit ches on t he st or ed wavefor m pr obably indicat e t hat t he t iming of t he lat ch st r obe
wit h r espect t o t he dat a should be changed .
Aft er ensur ing cor r ect t iming, t he FFT r out ine should pr oduce a r easonable spect r al
out put . If t her e ar e lar ge values of har monics, t he input signal may be over dr iving
t he ADC at one or bot h ends of t he r ange. Aft er br inging t he signal wit hin t he ADC
r ange (usually about 1dB below fullscale), excess har monic cont ent becomes mor e
difficult t o isolat e.
Make sur e t hat t he sinewave input t o t he ADC is spect r ally pur e. Bandpass filt er s
ar e usually r equir ed t o clean up t he out put of most high fr equency oscillat or s,
especially if wide dynamic r ange is expect ed.
Aft er ensur ing t he spect r al pur it y of t he ADC input , make sur e t he dat a out put lines
ar e not coupling t o eit her t he sampling clock or t o t he ADC analog input . Remember
t hat t he glit ches pr oduced on t he digit al lines ar e signal-dependent and will
t her efor e cont r ibut e t o har monic dist or t ion if t hey couple int o eit her one of t hese t wo
lines. As has been discussed pr eviously, noise or digit al modulat ion on t he sampling
clock can also pr oduce har monic dist or t ion in t he FFT out put . The use of an
evaluat ion boar d wit h separ at e sampling clock and analog input connect or s will
usually pr event t his. The special r ibbon cable used wit h t he logic analyzer t o capt ur e
2
1
t he ADC out put dat a has a cont r olled impedance and should not cause per for mance
degr adat ion.
In addit ion t o t he above har dwar e checks, t he FFT soft war e should be ver ified by
applying a t heor et ically per fect quant ized sinewave t o t he FFT and compar ing t he
r esult s t o t heor et ical SNR, et c. This is easy t o do using t he "r oundoff" funct ion
available in most mat h packages. The effect s of windowing non-coher ent input s
should also be examined befor e r unning act ual ADC t est s.
In per for ming calculat ions wit h t he FFT out put , t he t er m at dc and f
s
/2 should be
omit t ed fr om any calculat ions, as t hey can pr oduce er r oneous r esult s. Input
fr equencies which ar e int eger submult iples of t he sampling clock can also pr oduce
ar t ificially lar ge har monics.
TROUBLESHOOTING THE FFT OUTPUT
Excess harmonic distortion:

Distortion on input signal
Signal outside ADC input range
Digital runs coupling into analog input or sampling clock
Poor layout, decoupling, and grounding
Buffer memory not clocked at correct time
Analog input frequency locked to integer submultiple of
sampling clock
Excess noise floor:

Noise or phase jitter on input signal
Noise or phase jitter on sampling clock
Poor layout, decoupling, and grounding
Eliminate dc and f
s
/2 FFT components from calculations
Figure 8.22
ANALYZI NG THE FFT OUTP UT
Once t he FFT out put is obt ained, it can be analyzed in a number of ways, similar t o
t hat of t he display on an analog spect r um analyzer . The spur ious fr ee dynamic
r ange (SFDR) is t he r at io of t he fundament al signal t o t he wor st fr equency spur .
Tot al har monic dist or t ion (THD) is obt ained by t aking t he r at io of t he signal t o t he
r ms value of t he fir st sever al har monics (and t hen t aking t he logar it hm of t he r at io).
Because of aliasing, however , locat ing t he har monics in t he fr equency spect r um can
be difficult . For inst ance, if a 3MHz signal is sampled at 10MSPS, t he second
har monic (6MHz) act ually appear s in t he FFT out put at 4MHz (10MHz – 6MHz).
The t hir d har monic (9MHz) appear s at 1MHz (10MHz – 9MHz). The four t h
har monic (12MHz) appear s at 2MHz (12MHz – 10MHz). Soft war e r out ines t o
per for m t hese calculat ions ar e easily wr it t en.
2
2
Two t one int er modulat ion dist or t ion can be measur ed by applying t wo spect r ally
pur e t ones t o t he ADC using t he cir cuit pr eviously shown in Figur e 8.9. The concept
of second- or t hir d-or der int er cept point has lit t le meaning when t est ing ADCs for
t wo r easons. Fir st , t he ADC act s as a har d limit er for out -of-r ange signals, while an
amplifier soft limit s. Second, as t he amplit ude of t he t ones is r educed, t he value of
t he signal-r elat ed fr equency spur s t ends t o become somewhat const ant because of
t he discont inuous nat ur e of t he ADC t r ansfer funct ion. A "har d dist or t ion" floor is
r eached beyond which fur t her r educt ion in signal amplit ude has lit t le effect on t he
spur levels.
Finally, signal-t o-noise plus dist or t ion (S/N+D) can be calculat ed by t aking t he r at io
of t he r ms signal amplit ude t o t he r ms value of all ot her spect r al component s
(excluding dc and f
s
/2). Fr om t he S/N+D value, t he effect ive number of bit s (ENOB)
can be calculat ed. In some applicat ions, t he value of S/N+D wit hout t he har monics
included is of int er est .
Because of t he st at ist ical nat ur e of t he FFT analysis, t her e will be some var iabilit y
in t he out put fr om r un t o r un under ident ical t est condit ions. The dat a can be
st abilized by aver aging t he r esult s of sever al FFT r uns. This will not lower t he
aver age noise floor of t he FFT, but will r educe t he var at ion in t he r esult s.
ANALYZING THE FFT OUTPUT
Single-to-Noise including Distortion: S/(N+D)
Effective Number of Bits: (ENOB)
Signal-to-Noise without distortion: SNR
Spurious Free Dynamic Range: SFDR
Harmonic Distortion
Total Harmonic Distortion: THD
THD + Noise (Same as S/N + D)
Two-Tone Intermodulation Distortion
Figure 8.23
2
3
REFERENCES
1. Rober t A. Wit t e, Distortion Measurements Using a S pectrum Analyzer,
RF Desi gn , Sept ember , 1992, pp. 75-84.
2. Walt Kest er , Confused About Amplifier Distortion S pecs?, An a log
Di a logu e, 27-1, 1993, pp. 27-29.
3. Syst em Ap p li ca t i on s Gu i d e, Analog Devices, 1993, Chapt er 16.
4. Fr eder ick J . Har r is, On the Use of Windows for Harmonic Analysis
with the Discrete Fourier Transform, I EEE P r oceed i n gs, Vol. 66, No. 1,
J an. 1978, pp. 51-83.
5. J oey Doer nber g, Hae-Seung Lee, David A. Hodges, Full S peed Testing
of A/ D Converters, I EEE J ou r n a l of Soli d St a t e Ci r cu i t s, Vol. SC-19,
No. 6, Dec. 1984, pp. 820-827.
6. Br endan Coleman, Pat Meehan, J ohn Reidy and Pat Weeks, Coherent
S ampling Helps When S pecifying DS P A/ D Converters, EDN, Oct ober 15,
1987, pp. 145-152.
7. Rober t W. Ramier ez, Th e FFT: Fu n d a men t a ls a n d Con cep t s,
Pr ent ice-Hall, 1985.
8. R. B. Blackman and J . W. Tukey, Th e Mea su r emen t of P ower
Sp ect r a , Dover Publicat ions, New Yor k, 1958.
9. J ames J . Colot t i, “Digit al Dynamic Analysis of A/D Conver sion
Syst ems Thr ough Evaluat ion Soft war e Based on FFT/DFT Analysis”,
RF Exp o Ea st 1987 P r oceed i n gs, Car diff Publishing Co., pp. 245-272.
10. HP J ou r n a l, Nov. 1982, Vol. 33, No. 11.
11. HP P r od u ct Not e 5180A-2.
12. HP J ou r n a l, Apr il 1988, Vol. 39, No. 2.
13. HP J ou r n a l, J une 1988, Vol. 39, No. 3.
14. Dan Sheingold, Edit or , An a log-t o-Di gi t a l Con ver si on Ha n d book ,
Th i r d Ed i t i on , Pr ent ice-Hall, 1986.
15. W. R. Bennet t , “Spect r a of Quant ized Signals”, Bell Syst em Tech n i ca l
J ou r n a l, No. 27, J uly 1948, pp. 446-472.
16. Lawr ence Rabiner and Ber nar d Gold, Th eor y a n d Ap p li ca t i on of
Di gi t a l Si gn a l P r ocessi n g, Pr ent ice-Hall, 1975.
2
4
17. Mat t hew Mahoney, DSP -Ba sed Test i n g of An a log a n d Mi xed -Si gn a l
Ci r cu i t s, IEEE Comput er Societ y Pr ess, Washingt on, D.C., 1987.
18. I EEE Tr i a l-Use St a n d a r d for Di gi t i zi n g Wa vefor m Recor d er s,
No. 1057-1988.
19. Richar d J . Higgins, Di gi t a l Si gn a l P r ocessi n g i n VSLI , Pr ent ice-Hall,
1990.
20. M. S. Ghausi and K. R. Laker , Mod er n Fi lt er Desi gn : Act i ve RC a n d
Swi t ch ed Ca p a ci t or s, Pr ent ice Hall, 1981.
21. Mat hcad™ 4.0 soft war e package available fr om Mat hSoft , Inc.,
201 Br oadway, Cambr idge MA, 02139.
22. Syst em Ap p li ca t i on s Gu i d e, Analog Devices, 1993, Chapt er 8
(Audio Applicat ions), Chapt er 9.
1
SECTION 9
HARDWARE DESIGN TECHNIQUES
Prototyping Analog Circuits
Evaluation Boards
Noise Reduction and Filtering for
Switching Power Supplies
Low Dropout References and Regulators
EMI/RFI Considerations
Sensors and Cable Shielding
2
SECTI ON 9
HARDWARE DESI GN TECHNI QUES
Wa l t Kest er , J a m es Br ya n t , Wa l t J u n g,
Ad ol f o Ga r ci a , J oh n McDon a l d
P ROTOTYP I NG AND SI MULATI NG ANALOG CI RCUI TS
Wa l t Kest er , J a m es Br ya n t
While t her e is no doubt t hat comput er analysis is one of t he most valuable t ools t hat
t he analog designer has acquir ed in t he last decade or so, t her e is equally no doubt
t hat analog cir cuit models ar e not per fect and must be ver ified wit h har dwar e. If t he
init ial t est cir cuit or "br eadboar d" is not cor r ect ly const r uct ed, it may suffer fr om
malfunct ions which ar e not t he fault of t he design but of t he physical st r uct ur e of
t he br eadboar d it self. This sect ion consider s t he ar t of successful br eadboar ding of
high per for mance analog cir cuit s.
Real elect r onic cir cuit s cont ain many "component s" which wer e not pr esent in t he
cir cuit diagr am, but which ar e t her e because of t he physical pr oper t ies of
conduct or s, cir cuit boar ds, IC packages, et c. These component s ar e difficult , if not
impossible, t o incor por at e int o comput er modeling soft war e, and yet t hey have
subst ant ial effect s on cir cuit per for mance at high r esolut ions, or high fr equencies, or
bot h.
It is t her efor e inadvisable t o use SPICE modeling or similar soft war e t o pr edict t he
ult imat e per for mance of such high per for mance analog cir cuit s. Aft er modeling is
complet e, t he per for mance must be ver ified by exper iment .
This is not t o say t hat SPICE modeling is valueless - far fr om it . Most moder n high
per for mance analog cir cuit s could never have been developed wit hout t he aid of
SPICE and similar pr ogr ams, but it must be r emember ed t hat such simulat ions ar e
only as good as t he models used, and t hese models ar e not per fect . We have seen t he
effect s of par asit ic component s ar ising fr om t he conduct or s, insulat or s and
component s on t he PCB, but it is also necessar y t o appr eciat e t hat t he models used
wit hin SPICE simulat ions ar e not per fect models.
Consider an oper at ional amplifier . It cont ains some 20-40 t r ansist or s, almost as
many r esist or s, and a few capacit or s. A complet e SPICE model will cont ain all t hese
component s, and pr obably a few of t he mor e impor t ant par asit ic capacit ances and
spur ious diodes for med by t he diffusions in t he op-amp chip. This is t he model t hat
t he designer will have used t o evaluat e t he device dur ing his design. In simulat ions,
such a model will behave ver y like t he act ual op-amp, but not exact ly.
3
SPICE MODELING
SPICE modeling is a powerful tool for predicting the performance
of analog circuits.
Analog Devices provides macromodels for over 450 ICs
HOWEVER
Models omit real-life effects
No model can simulate all the parasitic effects of discrete
components and a PCB layout

THEREFORE
Prototypes must be built and proven before production.
Figure 9.1
However , t his model is not published, as it cont ains t oo much infor mat ion which
would be of use t o ot her semiconduct or companies who might wish t o copy or
impr ove on t he design. It would also t ake far t oo long for a simulat ion of a syst em
cont aining such models of a number of op-amps t o r each a useful r esult . For t hese,
and ot her r easons, t he SPICE models of analog cir cuit s published by manufact ur er s
or soft war e companies ar e "macr o" models, which simulat e t he major feat ur es of t he
component , but lack some of t he fine det ail. Consequent ly, SPICE modeling does not
always r epr oduce t he exact per for mance of a cir cuit and should always be ver ified
exper iment ally.
The basic pr inciple of a br eadboar d is t hat it is a temporary st r uct ur e, designed t o
t est t he per for mance of a cir cuit or syst em, and must t her efor e be easy t o modify.
Ther e ar e many commer cial br eadboar ding syst ems, but almost all of t hem ar e
designed t o facilit at e t he br eadboar ding of digital syst ems, wher e noise immunit ies
ar e hundr eds of millivolt s or mor e. (We shall discuss t he except ion t o t his gener alit y
lat er .) Non copper -clad Mat r ix boar d (Vect or boar d, et c.), wir e-wr ap, and plug-in
br eadboar d syst ems (Bimboar d, et c.) ar e, wit hout except ion, unsuit able for high
per for mance or high fr equency analog br eadboar ding. They have t oo high r esist ance,
induct ance, and capacit ance. Even t he use of st andar d IC socket s is inadvisable.
P RACTI CAL BREADBOARDI NG TECHNI QUES
The most pr act ical t echnique for analog br eadboar ding uses a copper -clad boar d as a
gr ound plane. The gr ound pins of t he component s ar e solder ed dir ect ly t o t he plane
and t he ot her component s ar e wir ed t oget her above it . This allows HF decoupling
pat hs t o be ver y shor t indeed. All lead lengt hs should be as shor t as possible, and
signal r out ing should separ at e high-level and low-level signals. Ideally t he layout
should be similar t o t he layout t o be used on t he final PCB. This appr oach is oft en
r efer r ed t o as "deadbug" because t he ICs ar e oft en mount ed upside down wit h t heir
4
leads up in t he air (wit h t he except ion of t he gr ound pins, which ar e bent over and
solder ed dir ect ly t o t he gr ound plane). The upside-down ICs look liked deceased
insect s, hence t he name.
Figur e 9.2 shows a hand-wir ed br eadboar d based ar ound t wo high speed op amps
which gives excellent per for mance in spit e of it s lack of est het ic appeal. The IC op
amps ar e mount ed upside down on t he copper boar d wit h t he leads bent over . The
signals ar e connect ed wit h shor t point -t o-point wir ing. The char act er ist ic impedance
of a wir e over a gr ound plane is about 120ohms, alt hough t his may var y as much as
±40% depending on t he dist ance fr om t he plane. The decoupling capacit or s ar e
connect ed dir ect ly fr om t he op amp power pins t o t he copper -clad gr ound. When
wor king at fr equencies of sever al hundr ed MHz, it is a good idea t o use only one side
of t he boar d for gr ound. Many people dr ill holes in t he boar d and connect bot h sides
t oget her wit h shor t pieces of wir e solder ed t o bot h sides of t he boar d. If car e is not
t aken, however , t his may r esult in unexpect ed gr ound loops bet ween t he t wo sides of
t he boar d, especially at RF fr equencies.
"DEADBUG" PROTOTYPE TECHNIQUE
Figure 9.2
Pieces of copper -clad may be solder ed at r ight angles t o t he main gr ound plane t o
pr ovide scr eening, or cir cuit r y may be const r uct ed on bot h sides of t he boar d (wit h
connect ions t hr ough holes) wit h t he boar d it self pr oviding scr eening. In t his case,
t he boar d will need legs t o pr ot ect t he component s on t he under side fr om being
cr ushed.
When t he component s of a br eadboar d of t his t ype ar e wir ed point -t o-point in t he air
(a t ype of const r uct ion st r ongly advocat ed by Rober t A. Pease of Nat ional
Semiconduct or (Refer ence 1) and somet imes known as "bir d's nest " const r uct ion)
t her e is always t he r isk of t he cir cuit r y being cr ushed and r esult ing shor t -cir cuit s.
Also if t he cir cuit r y r ises high above t he gr ound plane, t he scr eening effect of t he
gr ound plane is diminished, and int er act ion bet ween differ ent par t s of t he cir cuit is
mor e likely. Never t heless t he t echnique is ver y pr act ical and widely used because
t he cir cuit may so easily be modified.
5
Anot her "deadbug" pr ot ot ype is shown in Figur e 9.3. The boar d is single-sided
copper clad wit h holes pr e-dr illed on 0.1" cent er s. Power busses ar e at t he t op and
bot t om of t he boar d. The decoupling capacit or s ar e used on t he power pins of each
IC. Because of t he loss of copper ar ea due t o t he pr e-dr illed holes, t his t echnique
does not pr ovide as low a gr ound impedance as a complet ely cover ed copper -clad
boar d.
"DEADBUG" PROTOTYPE USING PRE-DRILLED
SINGLE-SIDED COPPER-CLAD BOARD
Figure 9.3
In a var iat ion of t his t echnique, t he ICs and ot her component s ar e mount ed on t he
non-copper -clad side of t he boar d. The holes ar e used as vias, and t he point -t o-point
wir ing is done on t he copper -clad side of t he boar d. The copper sur r ounding each
hole used for a via must be dr illed out so as t o pr event shor t ing. This appr oach
r equir es t hat all IC pins be on 0.1" cent er s. Low pr ofile socket s can be used for low
fr equency cir cuit s, and t he socket pins allow easy point -t o-point wir ing.
IC socket s can degr ade t he per for mance of high speed or high pr ecision analog ICs.
Even "low-pr ofile" socket s oft en int r oduce enough par asit ic capacit ance and
induct ance t o degr ade t he per for mance of t he cir cuit . If socket s must be used, an IC
socket made of individual "pin socket s" (somet imes called "cage jacks") mount ed in
t he gr ound plane boar d may be accept able (clear t he copper , on bot h sides of t he
boar d, for about 0.5mm ar ound each ungr ounded pin socket and solder t he gr ounded
ones t o gr ound on bot h sides of t he boar d. Bot h capped and uncapped ver sions of
t hese pin socket s ar e available (AMP par t number s 5-330808-3, and 5-330808-6,
r espect ively).
6
PIN SOCKETS (CAGE JACKS) HAVE MINIMUM PARASITIC
RESISTANCE, INDUCTANCE AND CAPACITANCE
Figure 9.4
Ther e is a commer cial br eadboar ding syst em which has most of t he advant ages of
"bir d's nest over a gr ound plane, or deadbug" (r obust gr ound, scr eening, ease of
cir cuit alt er at ion, low capacit ance and low induct ance) and sever al addit ional
advant ages:- it is r igid, component s ar e close t o t he gr ound plane, and wher e
necessar y node capacit ances and line impedances can be calculat ed easily. This
syst em is made by Wainwr ight Inst r ument s and is available in Eur ope as "Mini-
Mount " and in t he USA (wher e t he t r ademar k "Mini-Mount " is t he pr oper t y of
anot her company) as "Solder -Mount "[Refer ence 2].
Solder -Mount consist s of small pieces of PCB wit h et ched pat t er ns on one side and
cont act adhesive on t he ot her . They ar e st uck t o t he gr ound plane, and component s
ar e solder ed t o t hem. They ar e available in a wide var iet y of pat t er ns, including
r eady-made pads for IC packages of all sizes fr om 8-pin SOICs t o 64-pin DILs, st r ips
wit h solder pads at int er vals (which int er vals r ange fr om 0.040" t o 0.25", t he r ange
includes st r ips wit h 0.1" pad spacing which may be used t o mount DIL devices),
st r ips wit h conduct or s of t he cor r ect widt h t o for m micr ost r ip t r ansmission lines
(50ohms, 60ohms, 75ohms or 100ohms) when mount ed on t he gr ound plane, and a
var iet y of pads for mount ing var ious ot her component s. A few of t he many t ypes of
Solder -Mount building-block component s ar e shown in Figur e 9.5.
7
SAMPLES OF "SOLDER-MOUNT" COMPONENTS
Figure 9.5
The main advant age of Solder -Mount const r uct ion over "bir d's nest " or "deadbug" is
t hat t he r esult ing cir cuit is far mor e r igid, and, if desir ed, may be made far smaller
(t he lat est Solder -Mount s ar e for sur face-mount devices and allow t he const r uct ion
of br eadboar ds scar cely lar ger t han t he final PCB, alt hough it is gener ally mor e
convenient if t he pr ot ot ype is somewhat lar ger ). Solder -Mount is sufficient ly dur able
t hat it may be used for small quant it y pr oduct ion as well as pr ot ot yping.
Figur e 9.6 shows an example of a 2.5GHz phase-locked-loop pr ot ot ype built wit h
Solder -Mount . This is a high speed cir cuit , but t he t echnique is equally suit able for
t he const r uct ion of high r esolut ion low fr equency analog cir cuit r y. A par t icular ly
convenient feat ur e of Solder -Mount at VHF is t he ease wit h which it is possible t o
make a t r ansmission line.
8
"SOLDER-MOUNT" PROTOTYPE
Figure 9.6
If a conduct or r uns over a gr ound plane it for ms a micr ost r ip t r ansmission line.
Solder -Mount has st r ips which for m micr ost r ip lines when mount ed on a gr ound
plane (t hey ar e available wit h impedances of 50ohms, 60ohms, 75ohms, and
100ohms). These st r ips may be used as t r ansmission lines, for impedance mat ching,
or simply as power buses. (Glass fiber /epoxy PCB is somewhat lossy at VHF and
UHF, but t he losses will pr obably be t oler able if micr ost r ip r uns ar e shor t .)
Bot h t he "deadbug" and t he "Solder -Mount " br eadboar ding t echniques become
t edious for complex cir cuit s. Lar ger cir cuit s ar e oft en bet t er pr ot ot yped using mor e
for mal layout t echniques.
An appr oach t o pr ot ot yping mor e complex analog cir cuit s is t o act ually lay out a
double-sided boar d using CAD t echniques. PC-based soft war e layout packages offer
ease of layout as well as schemat ic capt ur e t o ver ify connect ions. Alt hough most
layout soft war e has some amount of aut o-r out ing capabilit y, t his feat ur e is best left
t o digit al designs. Aft er t he component s ar e placed in t heir appr oximat e posit ion, t he
int er connect ions should be r out ed manually following good analog layout guidelines.
Aft er t he layout is complet e, t he soft war e ver ifies t he connect ions per t he schemat ic
diagr am net list .
Many design engineer s find t hat t hey can use CAD t echniques (Refer ence 3) t o lay
out simple boar ds t hemselves, or wor k closely wit h a layout per son who has
exper ience in analog cir cuit boar ds. The r esult is a pat t er n-gener at ion t ape (or
Ger ber file) which would nor mally be sent t o a PCB manufact ur ing facilit y wher e
t he final boar d is made. Rat her t han use a PC boar d manufact ur er , however ,
aut omat ic dr illing and milling machines ar e available which accept t he PG t ape
(Refer ence 4). These syst ems pr oduce single and double-sided cir cuit boar ds dir ect ly
by dr illing all holes and using a milling t echnique t o r emove copper and cr eat e
insulat ion pat hs and finally, t he finished boar d. The r esult is a boar d ver y similar t o
t he final manufact ur ed double-sided PC boar d, t he chief except ion being t hat t her e
9
is no "plat ed-t hr ough" hole capabilit y, and any "vias" bet ween t he t wo layer s of t he
boar d must be wir ed and solder ed on bot h sides. Minimum t r ace widt hs of 25 mils (1
mil = 0.001") and 12 mil spacing bet ween t r aces ar e st andar d, alt hough smaller
t r ace widt hs can be achieved wit h car e. The minimum spacing bet ween lines is
dict at ed by t he size of t he milling bit , t ypically 10 t o 12 mils.
An example of such a pr ot ot ype boar d is shown in Figur e 9.7. This is a "daught er "
boar d designed t o int er face an AD9562 Dual Pulse-Widt h Modulat or in a 44-pin
PLCC package t o a "mot her " boar d. The leads ar e on 50 mil cent er s, and t he t r aces
ar e appr oximat ely 25 mils wide.
"MILLED" PROTOTYPE PC BOARD
Figure 9.7
Mult ilayer PC boar ds do not easily lend t hemselves t o st andar d pr ot ot yping
t echniques. One side of a double-sided boar d can be used for gr ound and t he ot her
side for power and signals. Point -t o-point wir ing can be used for addit ional r uns
which would nor mally be placed on t he addit ional layer s pr ovided by a mult i-layer
boar d. However , it is difficult t o cont r ol t he impedance of t he point -t o-point wir ing
r uns, and t he high fr equency per for mance of a cir cuit pr ot ot yped in t his manner
may differ significant ly fr om t he final mult ilayer boar d.
1
0
SUCCESSFUL PROTOTYPING
Always use a ground plane for precision or high frequency
circuits
Minimize parasitic resistance, capacitance, and inductance
If sockets are required, use “pin sockets” (“cage jacks”)
Pay equal attention to signal routing, component placement,
grounding, and decoupling in both the prototype and the final
design
Popular prototyping techiniques:
Freehand “deadbug” using point-to-point wiring
“Solder-Mount”
Milled PC board from CAD layout
Multilayer boards: Double-sided with additional point-to-
point wiring
Figure 9.8
EVALUATI ON BOARDS
Manufact ur er 's evaluat ion boar ds pr ovide a convenient way of evaluat ing high-
per for mance ICs wit hout t he need for const r uct ing labor -int ensive pr ot ot ype boar ds.
Analog Devices pr ovides evaluat ion boar ds for almost all new high speed and
pr ecision pr oduct s. The boar ds ar e designed wit h good layout , gr ounding, and
decoupling t echniques. They ar e complet ely t est ed, and ar t wor k (including PG t ape)
is available t o cust omer s.
Because of t he popular it y of dual pr ecision op amps in 8-pin DIPs, a univer sal
evaluat ion boar d has been developed (see Figur e 9.9). This boar d makes ext ensive
use of pin socket s t o allow r esist or s or jumper s t o configur e t he t wo op amps in just
about any conceivable feedback, input /out put , and load condit ion. The input s and
out put s ar e convenient r ight -angle BNC connect or s. Because of t he use of socket s
and t he less-t han-compact layout , t his boar d is not useful for op amps having gain-
bandwidt h pr oduct s much gr eat er t han 10MHz.
1
1
UNIVERSAL EVALUATION BOARD FOR DUAL
PRECISION OP AMPS IN 8-PIN DIPs
Figure 9.9
A schemat ic of t he AD8001 800MHz 50mW cur r ent feedback op amp evaluat ion
boar d for t he 8-lead SOIC package is shown in Figur e 9.10. The boar d is designed for
a non-inver t ing gain of 2. (Boar ds for inver t ing and non-inver t ing modes ar e
available for bot h t he 8-lead SOIC and t he DIP package).
Decoupling on bot h t he + and – supplies consist s of 1000pF and 0.01µF sur face
mount chip cer amic capacit or s in addit ion t o a 10µF/25V sur face mount t ant alum
elect r olyt ic. The t op view of t he PC boar d is shown in Figur e 9.10, and t he bot t om
view in Figur e 9.12.
1
2
AD8001AR (SOIC) 800MHz OP AMP: NON-INVERTING
MODE EVALUATION BOARD SCHEMATIC
Figure 9.10
AD8001AR (SOIC) EVALUATION BOARD - TOP VIEW
Figure 9.11
1
3
AD8001AR (SOIC) EVALUATION BOARD -BOTTOM VIEW
Figure 9.12
Figur e 9.12 (bot t om side of boar d) shows t he sur face mount r esist or s and capacit or s.
Not ice t hat t he cer amic chip capacit or s ar e mount ed as close as possible t o t he power
pins as possible. The input and out put r uns ar e 50ohm t r ansmission lines. The input
fr om t he SMA connect or is t er minat ed in a 50ohm chip r esist or at t he op amp, and
t he out put has a 50ohm sour ce t er minat ion for dr iving a 50ohm cable t hr ough t he
out put SMA connect or .
All r esist or s ar e sur face mount film r esist or s. Not ice t hat t he gr ound plane is et ched
away fr om t he ar ea immediat ely sur r ounding t he input s of t he op amp t o minimize
st r ay capacit ance.
Slight ly differ ent r esist or values ar e r equir ed t o achieve opt imum per for mance in
t he SOIC and t he DIP packages (see Figur e 9.13), because t he SOIC package has
slight ly lower par asit ic capacit ance and induct ance t han t he DIP. The cr it er ia for
select ion of t he component s was maximum 0.1dB bandwidt h.
1
4
OPTIMUM VALUES OF R
F
AND R
G
FOR AD8001
DIP AND SOIC PACKAGES (MAXIMUM 0.1dB BANDWIDTH)
Figure 9.13
ADC evaluat ion boar ds include mor e suppor t cir cuit r y t han op amp boar ds. An
example is t he AD7714 (22-bit pr ecision measur ement sigma-delt a ADC) evaluat ion
boar d (see Figur e 9.14 for a simplified block diagr am). Included on t he evaluat ion
boar d ar e an AD780 pr ecision r efer ence, a 2.4576MHz cr yst al and digit al buffer s t o
buffer t he signal t o and fr om t he edge connect or s.
AD7714 ADC EVALUATION BOARD
Figure 9.14
Int er facing t o t his boar d is pr ovided eit her t hr ough a 36-Way Cent r onics connect or
or t hr ough a 9-Way D-t ype connect or . The Cent r onics connect or is int ended for
connect ion t o t he pr int er por t of a PC. Ext er nal socket s ar e pr ovided for t he analog
input s, an ext er nal r efer ence input opt ion, and an ext er nal mast er clock opt ion.
Included in t he evaluat ion boar d package is a PC-compat ible DOS-based disk which
cont ains soft war e for cont r olling and evaluat ing t he per for mance of t he AD7714
using t he pr int er por t . Ther e ar e t wo files on t he disk, an execut able file, and a
"r eadme" t ext file which gives det ails of t he funct ions available in t he execut able
1
5
pr ogr am. The evaluat ion soft war e is r un by r unning t he execut able file. The
pr ogr am pr ovides a number of differ ent menu-t ype scr eens, each scr een cont aining
sever al funct ion opt ions.
The fir st menu gives opt ions on t he t ype of PC being used. The next menu in t he
sequence is t he Main Menu which cont ains var ious opt ions. These allow r eading
fr om t he AD7714 Dat a Regist er , configur at ion of t he Communicat ions Regist er , file
opt ions (r ead and wr it e dat a t o files), noise analysis, pr int er por t set up, and
r eset t ing t he AD7714.
The Noise Menu allows t he user t o get st at ist ical r esult s fr om t he dat a, t o plot t he
r aw dat a, plot a hist ogr am of t he dat a on t he scr een, or per for m a r olling aver age of
t he dat a. A phot ogr aph of t he AD7714 evaluat ion boar d is shown in Figur e 9.15.
Not ice t he par allel pr int er connect or on t he left and t he use of low-pr ofile socket s for
convenience. It should be not ed t hat alt hough t he use of socket s is discour aged, any
socket s used on evaluat ion boar ds have been pr oven t o cause minimal per for mance
degr adat ion.
AD7714 EVALUATION BOARD PHOTO
Figure 9.15
Evaluat ion boar ds for high speed sampling ADCs cont ain t he r equir ed suppor t
cir cuit r y for pr oper evaluat ion of t he conver t er . Figur e 9.16 shows a block diagr am of
t he AD9026 (12-bit , 31MSPS) evaluat ion boar d. The analog input is connect ed
dir ect ly t o t he ADC input via an SMA connect or . The sampling clock (Encode Input )
is condit ioned by t he low-jit t er high-speed AD9698 dual compar at or . The par allel
digit al out put s of t he AD9026 ar e buffer ed by lat ches which dr ive t he out put
connect or as well as t he AD9713 12-bit DAC. The DAC out put is connect ed t o an
out put SMA connect or .
1
6
AD9026 12-BIT, 31MSPS ADC EVALUATION BOARD
Figure 9.16
The out put connect or is designed for convenient int er facing t o an ext er nal buffer
memor y or t o a logic analyzer input (a ver y convenient high speed buffer memor y).
The t op side of t he boar d is shown in Figur e 9.17. The boar d is a 3-layer boar d
consist ing of one gr ound plane (out er layer ), one power /signal plane (inner layer ),
and an addit ional signal plane (out er layer ). Pin socket s ar e used t o mount t he
AD9026. Figur e 9.18 shows t he bot t om side of t he boar d and t he sur face mount ed
AD9698 SOIC compar at or and t he AD9713B PLCC DAC.
AD9026 EVALUATION BOARD - TOP VIEW
Figure 9.17
1
7
AD9026 EVALUATION BOARD - BOTTOM VIEW
Figure 9.18
1
8
REFERENCES: P ROTOTYP I NG AND EVALUATI ON
BOARDS
1. Rober t A. Pease, Tr ou blesh oot i n g An a log Ci r cu i t s, But t er wor t h-
Heinemann, 1991.
2. Wainwr ight Inst r ument s Inc., 7770 Regent s Rd., #113, Suit e 371,
San Diego, CA 92122, Tel. 619-558-1057, Fax. 619-558-1019.
Wainwr ight Inst r ument s GmbH, Widder sber ger St r asse 14,
DW-8138 Andechs-Fr ieding, Ger many. Tel: +49-8152-3162,
Fax: +49-8152-40525.
3. Schemat ic Capt ur e and Layout Soft war e:
PADS Soft war e, INC, 165 For est St ., Mar lbor o, MA, 01752
ACCEL Technologies, Inc., 6825 Flander s Dr ., San Diego, CA,
92121
4. Pr ot ot ype Boar d Cut t er s:
LPKF CAD/CAM Syst ems, Inc., 1800 NW 169t h Place,
Beaver t on, OR, 97006
T-Tech, Inc., 5591-B New Peacht r ee Road, At lant a, GA,
34341
1
9
NOI SE REDUCTI ON AND FI LTERI NG FOR SWI TCHI NG
P OWER SUP P LI ES
Wa l t J u n g a n d J oh n McDon a l d
Pr ecision analog cir cuit r y has t r adit ionally been power ed fr om well r egulat ed, low
noise linear power supplies. Dur ing t he last decade however , swit ching power
supplies have become much mor e common in elect r onic syst ems. As a consequence,
t hey also ar e being used for analog supplies. Ther e ar e sever al good r easons for t heir
popular it y, including high efficiency, low t emper at ur e r ise, small size, and light
weight .
Swit ching power supplies, or mor e simply switchers, a cat egor y including swit ching
r egulat or s and swit ching conver t er s, ar e by t heir nat ur e efficient . Oft en t his can be
above 90%, and as a r esult , t hese power supply t ypes use less power and gener at e
less heat t han do equivalent linear supplies.
A swit cher can be as much as one t hir d t he size and weight of a linear supply
deliver ing t he same volt age and cur r ent . Swit ching fr equencies can r ange fr om
20kHz t o 1MHz, and as a r esult , r elat ively small component s can be used in t heir
design.
In spit e of t hese benefit s, swit cher s have t heir dr awbacks, most not ably high out put
noise. This noise gener ally ext ends over a br oad band of fr equencies, and occur s as
bot h conduct ed and r adiat ed noise, and unwant ed elect r ic and magnet ic fields.
Volt age out put noise of swit ching supplies ar e shor t -dur at ion volt age t r ansient s, or
spikes. Alt hough t he fundament al swit ching fr equency can r ange fr om 20kHz t o
1MHz, t he volt age spikes will cont ain fr equency component s ext ending easily t o
100MHz or mor e.
Because of wide var iat ion in t he noise out put char act er ist ics of commer cial
swit cher s, t hey should always be pur chased in accor dance wit h a specificat ion-
cont r ol dr awing. Alt hough specifying swit ching supplies in t er ms of RMS noise is
common vendor pr act ice, as a user you should also specify t he peak (or p-p)
amplit udes of t he swit ching spikes, wit h t he out put loading of your syst em. You
should also insist t hat t he swit ching-supply manufact ur er infor m you of any int er nal
supply design changes t hat may alt er t he spike amplit udes, dur at ion, or swit ching
fr equency. These changes may r equir e cor r esponding changes in ext er nal filt er ing
net wor ks.
2
0
SWITCHING POWER SUPPLY CHARACTERISTICS
ADVANTAGES:
Efficient
Small Size, Light Weight
Low Operating Temperature Rise
Isolation from Line Transients
Wide Input/Output Range
DISADVANTAGES:
Noise: LF, HF, Electric Field, Magnetic Field
Conducted, Radiated
DC regulation and accuracy can be poor
Figure 9.19
This sect ion discusses filt er t echniques for r ender ing a noisy swit cher out put analog
ready, t hat is sufficient ly quiet t o power pr ecision analog cir cuit r y wit h r elat ively
small loss of DC t er minal volt age. These t echniques include char act er izat ion of
swit cher out put noise, ident ificat ion of t he fr equency r ange of int er fer ence pr oduced
by t he swit ching power supply, evaluat ion of passive component s commonly used in
ext er nal power supply filt er s, and t he design and const r uct ion of a swit ching power
supply filt er . The filt er solut ions pr esent ed ar e gener ally applicable t o all power
supply t ypes incor por at ing a swit ch element in t heir ener gy pat h. This includes
var ious DC-DC conver t er s, as well as t he 5V PC t ype supply used in t he example.
A TYPICAL 5V, 150W PC SWITCHING POWER SUPPLY
Figure 9.20
2
1
A t ypical 5V PC t ype swit cher is shown in Figur e 9.20, and t ypifies t he st yle. A
display of t he 5V power buss of an oper at ing deskt op PC (Dell Dimension XPS P-90)
using a similar (but not ident ical) supply is shown in Figur e 9.21. The unfilt er ed
out put shown fr om t his swit cher exhibit s a ~60mV p-p t r ansient component at an
80kHz (r oughly) swit ching fr equency, as seen in t he (A) left phot o wit h t he 5µs t ime
base. The expanded scale phot o for t he same oper at ing condit ions of (B) r ight shows
t he det ail of t he swit ching glit ches on a 100ns t ime base. The fast volt age spikes
pr oduce significant har monics well int o t he high MHz r ange.
OUTPUT OF 5V PC SWITCHING POWER SUPPLY
(UNFILTERED)
Figure 9.21
It is clear t hat t his swit cher is not analog r eady, just as it is shown. Since many
analog ICs show degr aded power supply r eject ion at fr equencies above a few kHz,
some filt er ing is necessar y. This will be par t icular ly t r ue for use wit h low power op
amps, which can show PSRR degr adat ion above a few hundr ed Hz. In gener al, all op
amps, volt age r efer ences, DACs, and ADCs r equir e clean supplies t o meet t heir
design accur acy. Swit cher noise can pr event t his happening, if left unchecked.
Befor e offer ing t echniques t o r educe swit cher noise, a br ief examinat ion of swit ching
supply ar chit ect ur es is helpful, and t wo popular ones ar e shown in Figur e 9.22.
Higher efficiency designs use a pulse widt h modulat ion t echnique for volt age
r egulat ion, while lower efficiency, lower noise designs use linear post r egulat or s.
2
2
BASIC SWITCHING POWER SUPPLY TOPOLOGY
Figure 9.22
The r aw AC line volt age is fir st r ect ified and filt er ed t o a high DC level, t hen
conver t ed t o a 30kHz (or higher ) fr equency squar e wave, which dr ives a t r ansfor mer .
The signal is again r ect ified, and filt er ed at t he t r ansfor mer out put . Some swit cher s
may use a linear r egulat or t o for m t he final out put volt age, as in t he upper diagr am.
Ot her s use pulse widt h r egulat ion t echniques t o cont r ol t he dut y cycle of t he
t r ansfor mer dr ive (lower diagr am). Alt hough mor e efficient , t his r esult s in mor e
noise at t he out put t han linear post -r egulat ion.
It is impor t ant t o under st and t hat noise is gener at ed in ever y st age of t he swit cher .
The fir st st age AC line r ect ificat ion cr eat es cur r ent spikes, which pr oduce line-
r elat ed har monic noise. In t he inver t er st age, fast pulse edges gener at e har monics
ext ending well beyond 5MHz. Fur t her mor e, t he par asit ic capacit ance wit hin t he
pr imar y and secondar y windings of t he t r ansfor mer pr ovide an addit ional pat h
t hr ough which high-fr equency noise can cor r upt t he DC out put volt age. Finally,
high-fr equency noise is also gener at ed by bot h r ect ifier st ages.
An under st anding of t he EMI pr ocess is necessar y t o under st and t he effect s of
supply noise on analog cir cuit s and syst ems. Ever y int er fer ence pr oblem has a
source, a path, and a receptor [Refer ence 1]. In gener al, t her e ar e t hr ee met hods for
dealing wit h int er fer ence. Fir st , sour ce emissions can be minimized by pr oper
layout , pulse-edge r ise t ime cont r ol/r educt ion, filt er ing, and pr oper gr ounding.
Second, r adiat ion and conduct ion pat hs should be r educed t hr ough shielding and
physical separ at ion. Thir d, r ecept or immunit y t o int er fer ence can be impr oved, via
supply and signal line filt er ing, impedance level cont r ol, impedance balancing, and
ut ilizing differ ent ial t echniques t o r eject undesir ed common-mode signals. Fr om t his
ar r ay of gener al noise immunit y appr oaches, t his sect ion focuses on r educing
swit ching power supply noise wit h ext er nal post filt er s.
2
3
THE INTERFERENCE PROCESS
Figure 9.23
Befor e designing a swit ching supply filt er , it is helpful t o det er mine whet her or not
t he supply noise is act ually affect ing t he cir cuit per for mance. If cr it ical node
volt ages in t he cir cuit have t r ansient s synchr onous wit h t he swit cher ’s oper at ing
fr equency, t hen t he supply is t he likely culpr it . A highly r ecommended met hod for
det er mining if t he supply is t he noise sour ce is t o t empor ar ily oper at e t he cir cuit
fr om a clean linear power supply or bat t er y. If t he int er fer ing noise level dr ops
dr amat ically, t he swit cher is guilt y as char ged. Not e t hat lower ing t he power supply
noise level may also help ident ify ot her noise sour ces which wer e masked by t he
higher swit cher noise. Once t he noise sour ce is quant ified and it s pat h (r adiat ed or
conduct ed) ident ified, t he pr ocess of r educing or eliminat ing it can begin.
Tools which can be used t o combat swit cher noise ar e highlight ed by Figur e 9.24.
These t ools differ in t heir elect r ical char act er ist ics as well as t heir pr act icalit y
t owar ds noise r educt ion. For t his r eason t hey ar e list ed r oughly in a suggest ed or der
of pr ior it ies. Of t he t ools, induct ance and capacit ance ar e t he most power ful filt er ing
element s, and can also be t he most cost -effect ive and small in size.
2
4
NOISE REDUCTION TOOLS
Capacitors
Inductors
Ferrites
Resistors
Linear Post Regulation
PHYSICAL SEPARATION FROM SENSITIVE ANALOG
CIRCUITS !!
Figure 9.24
Capacit or s ar e pr obably t he single most impor t ant filt er component for swit cher s.
Ther e ar e many differ ent t ypes of capacit or s, and an under st anding of t heir
individual char act er ist ics is absolut ely mandat or y t o t he design of pr act ical, effect ive
power supply filt er s. Ther e ar e gener ally t hr ee classes of capacit or s useful in filt er s
in t he 10kHz-100MHz fr equency r ange suit able for swit cher s. These ar e br oadly
dist inguished by t heir gener ic dielect r ic t ypes; electrolytic, film, and ceramic. These
dielect r ics can in t ur n can be fur t her sub-divided as discussed below. A t humbnail
sket ch of capacit or char act er ist ics is shown in t he char t of Figur e 9.25. Backgr ound
and t ut or ial infor mat ion on capacit or s can be found in Refer ence 2 and many vendor
cat alogs.
CAPACITOR SELECTION
Figure 9.25
Wit h any dielect r ic, a major pot ent ial filt er loss element is ESR (equivalent ser ies
r esist ance), t he net par asit ic r esist ance of t he capacit or . ESR pr ovides an ult imat e
limit t o filt er per for mance, and r equir es mor e t han casual consider at ion, because it
can var y bot h wit h fr equency and t emper at ur e in some t ypes. Anot her capacit or loss
element is ESL (equivalent ser ies induct ance). ESL det er mines t he fr equency wher e
t he net impedance of t he capacit or swit ches fr om a capacit ive t o induct ive
2
5
char act er ist ic. This var ies fr om as low as 10kHz in some elect r olyt ics t o as high as
100MHz or mor e in chip cer amic t ypes. Bot h ESR and ESL ar e minimized when a
leadless package is used, and all capacit or t ypes discussed her e ar e available in
sur face mount packages, which ar e pr efer able for high speed uses.
The electrolytic family pr ovides an excellent , cost -effect ive low-fr equency filt er
component , because of t he wide r ange of values, a high capacit ance-t o-volume r at io,
and a br oad r ange of wor king volt ages. It includes general purpose aluminum
electrolytic t ypes, available in wor king volt ages fr om below 10V up t o about 500V,
and in size fr om 1 t o sever al t housand µF (wit h pr opor t ional case sizes). All
elect r olyt ic capacit or s ar e polar ized, and t hus cannot wit hst and mor e t han a volt or
so of r ever se bias wit hout damage. They have r elat ively high leakage cur r ent s (t his
can be t ens of µA, but is st r ongly dependent upon specific family design, elect r ical
size and volt age r at ing vs. applied volt age). However , t his is not likely t o be a major
fact or for basic filt er ing applicat ions.
Also included in t he elect r olyt ic family ar e tantalum t ypes, which ar e gener ally
limit ed t o volt ages of 100V or less, wit h capacit ance of 500µF or less[Refer ence 3]. In
a given size, t ant alums exhibit a higher capacit ance-t o-volume r at ios t han do t he
gener al pur pose elect r olyt ics, and have bot h a higher fr equency r ange and lower
ESR. They ar e gener ally mor e expensive t han st andar d elect r olyt ics, and must be
car efully applied wit h r espect t o sur ge and r ipple cur r ent s.
A subset of aluminum elect r olyt ic capacit or s is t he switching t ype, which is designed
and specified for handling high pulse cur r ent s at fr equencies up t o sever al hundr ed
kHz wit h low losses [Refer ence 4]. This t ype of capacit or compet es dir ect ly wit h t he
t ant alum t ype in high fr equency filt er ing applicat ions, and has t he advant age of a
much br oader r ange of available values.
Mor e r ecent ly, high per for mance aluminum elect r olyt ic capacit or s using an or ganic
semiconduct or elect r olyt e have appear ed [Refer ence 5]. These OS -CON families of
capacit or s feat ur e appr eciably lower ESR and higher fr equency r ange t han do t he
ot her elect r olyt ic t ypes, wit h an addit ional feat ur e of low low-t emper at ur e ESR
degr adat ion.
Film capacit or s ar e available in ver y br oad r anges of values and an ar r ay of
dielect r ics, including polyest er , polycar bonat e, polypr opylene, and polyst yr ene.
Because of t he low dielect r ic const ant of t hese films, t heir volumet r ic efficiency is
quit e low, and a 10µF/50V polyest er capacit or (for example) is act ually a handful.
Met alized (as opposed t o foil) elect r odes does help t o r educe size, but even t he
highest dielect r ic const ant unit s among film t ypes (polyest er , polycar bonat e) ar e st ill
lar ger t han any elect r olyt ic, even using t he t hinnest films wit h t he lowest volt age
r at ings (50V). Wher e film t ypes excel is in t heir low dielect r ic losses, a fact or which
may not necessar ily be a pr act ical advant age for filt er ing swit cher s. For example,
ESR in film capacit or s can be as low as 10milliohms or less, and t he behavior of
films gener ally is ver y high in t er ms of Q. In fact , t his can cause pr oblems of
spur ious r esonance in filt er s, r equir ing damping component s.
2
6
Typically using a wound layer -t ype const r uct ion, film capacit or s can be induct ive,
which can limit t heir effect iveness for high fr equency filt er ing. Obviously, only non-
induct ively made film caps ar e useful for swit ching r egulat or filt er s. One specific
st yle which is non-induct ive is t he stacked-film t ype, wher e t he capacit or plat es ar e
cut as small over lapping linear sheet sect ions fr om a much lar ger wound dr um of
dielect r ic/plat e mat er ial. This t echnique offer s t he low induct ance at t r act iveness of a
plat e sheet st yle capacit or wit h convent ional leads [see t ype “V” of Refer ence 4, plus
Refer ence 6]. Obviously, minimal lead lengt h should be used for best high fr equency
effect iveness. Ver y high cur r ent polycar bonat e film t ypes ar e also available,
specifically designed for swit ching power supplies, wit h a var iet y of low induct ance
t er minat ions t o minimize ESL [Refer ence 7].
Dependent upon t heir elect r ical and physical size, film capacit or s can be useful at
fr equencies t o well above 10MHz. At t he ver y high fr equencies, st acked film t ypes
only should be consider ed. Some manufact ur er s ar e also supplying film t ypes in
leadless sur face mount packages, which eliminat es t he lead lengt h induct ance.
Cer amic is oft en t he capacit or mat er ial of choice above a few MHz, due t o it s
compact size, low loss, and availabilit y in values up t o sever al µF in t he high-K
dielect r ic for mulat ions of X7R and Z5U, at volt age r at ings up t o 200V [see cer amic
families of Refer ence 3]. NP0 (also called COG) t ypes use a lower dielect r ic const ant
for mulat ion, and have nominally zer o TC, plus a low volt age coefficient (unlike t he
less st able high-K t ypes). The NP0 t ypes ar e limit ed in available values t o 0.1µF or
less, wit h 0.01µF r epr esent ing a mor e pr act ical upper limit .
Mult ilayer cer amic “chip caps” ar e incr easingly popular for bypassing and filt er ing
at 10MHz or mor e, because t heir ver y low induct ance design allows near opt imum
RF bypassing. In smaller values, cer amic chip caps have an oper at ing fr equency
r ange t o 1GHz. For t hese and ot her capacit or s for high fr equency applicat ions, a
useful value can be ensur ed by select ing a value which has a self-r esonant fr equency
above t he highest fr equency of int er est .
All capacit or s have some finit e ESR. In some cases, t he ESR may act ually be helpful
in r educing r esonance peaks in filt er s, by supplying “fr ee” damping. For example, in
gener al pur pose, t ant alum and swit ching t ype elect r olyt ics, a br oad ser ies r esonance
r egion is not ed in an impedance vs. fr equency plot . This occur s wher e | Z| falls t o a
minimum level, which is nominally equal t o t he capacit or ’s ESR at t hat fr equency.
In an example below, t his low Q r esonance is not ed t o encompass quit e a wide
fr equency r ange, sever al oct aves in fact . Cont r ast ed t o t he ver y high Q shar p
r esonances of film and cer amic caps, t his low Q behavior can be useful in cont r olling
r esonant peaks.
In most elect r olyt ic capacit or s, ESR degr ades not iceably at low t emper at ur e, by as
much as a fact or of 4-6 t imes at –55°C vs. t he r oom t emper at ur e value. For cir cuit s
wher e a high level of ESR is cr it ical, t his can lead t o pr oblems. Some specific
elect r olyt ic t ypes do addr ess t his pr oblem, for example wit hin t he HFQ swit ching
t ypes, t he –10°C ESR at 100kHz is no mor e t han 2× t hat at r oom t emper at ur e. The
OSCON elect r olyt ics have a ESR vs. t emper at ur e char act er ist ic which is r elat ively
flat .
2
7
Figur e 9.26 illust r at es t he high fr equency impedance char act er ist ics of a number of
elect r olyt ic capacit or t ypes, using nominal 100µF/20V samples. In t hese plot s, t he
impedance, | Z| , vs. fr equency over t he 20Hz-200kHz r ange is displayed using a
high r esolut ion 4-t er minal set up [Refer ence 8]. Shown in t his display ar e
per for mance samples for a 100µF/25V gener al pur pose aluminum unit (t op cur ve @
r ight ), a 120µF/25V HFQ unit (next cur ve down @r ight ), a 100µF/20V t ant alum
bead t ype (next cur ve down @r ight ), and a 100µF/20V OS-CON unit (lowest cur ve @
r ight ). While t he HFQ and t ant alum samples ar e close in 100kHz impedance, t he
gener al pur pose unit is about 4 t imes wor se. The OS-CON unit is near ly an or der of
magnit ude lower in 100kHz impedance t han t he t ant alum and swit ching elect r olyt ic
t ypes.
IMPEDANCE Z ( ) VS. FREQUENCY (Hz) FOR 100 F
ELECTROLYITC CAPACITORS (AC CURRENT = 50mA RMS)
Figure 9.26
As not ed above, all r eal capacit or s have par asit ic element s which limit t heir
per for mance. As an insight int o why t he impedance cur ves of Figur e 9.26 appear t he
way t hey do, a (simplified) model for a 100µF/20V t ant alum capacit or is shown in
Figur e 9.27.
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8
SIMPLIFIED SPICE MODEL FOR LEADED
100 F/20V TANTALUM ELECTROLYTIC CAPACITOR
Figure 9.27
The elect r ical net wor k r epr esent ing t his capacit or is shown, and it models t he ESR
and ESL component s wit h simple R and L element s, plus a 1megohm shunt
r esist ance. While t his simple model ignor es t emper at ur e and dielect r ic absor pt ion
effect s which occur in t he r eal capacit or , it is st ill sufficient for t his discussion.
When dr iven wit h a const ant level of AC cur r ent swept fr om 10Hz t o 100MHz, t he
volt age acr oss t his capacit or model is pr opor t ional t o it s net impedance, which is
shown in Figur e 9.28.
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100 F / 20V TANTALUM CAPACITOR SIMPLIFIED MODEL
IMPEDANCE ( ) VS. FREQUENCY (Hz)
Figure 9.28
At low fr equencies t he net impedance is almost pur ely capacit ive, as not ed by t he
100Hz impedance of 15.9ohms. At t he bot t om of t his “bat ht ub” cur ve, t he net
impedance is det er mined by ESR, which is shown t o be 0.12ohms at 125kHz. Above
about 1MHz t his capacit or becomes induct ive, and impedance is dominat ed by t he
effect of ESL. While t his par t icular combinat ion of capacit or char act er ist ics have
been chosen pur posely t o cor r espond t o t he t ant alum sample used wit h Figur e 9.26,
it is also t r ue t hat all elect r olyt ics will display impedance cur ves which ar e similar
in gener al shape. The minimum impedance will var y wit h t he ESR, and t he
induct ive r egion will var y wit h ESL (which in t ur n is st r ongly effect ed by package
st yle). The simulat ion cur ve of Figur e 9.28 can be consider ed as an ext ension of t he
100µF/20V t ant alum capacit or cur ve fr om Figur e 9.26.
Ferrites (non-conduct ive cer amics manufact ur ed fr om t he oxides of nickel, zinc,
manganese, or ot her compounds) ar e ext r emely useful for decoupling in power
supply filt er s [Refer ence 9]. At low fr equencies (<100kHz), fer r it es ar e induct ive;
t hus t hey ar e useful in low-pass LC filt er s. Above 100kHz, fer r it es becomes r esist ive,
an impor t ant char act er ist ic in high-fr equency filt er designs. Fer r it e impedance is a
funct ion of mat er ial, oper at ing fr equency r ange, DC bias cur r ent , number of t ur ns,
size, shape, and t emper at ur e. Figur e 9.29 summar ize a number fer r it e
char act er ist ics.
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CHARACTERISTICS OF FERRITES
Good for frequencies above 25kHz
Many sizes and shapes available including leaded “resistor
style”
Ferrite impedance at high frequencies is primarily resistive –
Ideal for HF filtering
Low DC loss: Resistance of wire passing through ferrite is very
low
High saturation current
Low cost
Figure 9.29
Sever al fer r it e manufact ur er s offer a wide select ion of fer r it e mat er ials fr om which
t o choose, as well as a var iet y of packaging st yles for t he finished net wor k (see
Refer ences 10 and 11). The most simple for m is t he bead of fer r it e mat er ial, a
cylinder of t he fer r it e which is simply slipped over t he power supply lead t o t he st age
being decoupled. Alt er nat ely, t he leaded ferrite bead is t he same bead, mount ed by
adhesive on a lengt h of wir e, and used simply as a component (Refer ence 11 t ypifies
t hese t wo st yles). Mor e complex beads offer mult iple holes t hr ough t he cylinder for
incr eased decoupling, plus ot her var iat ions. Sur face mount bead st yles ar e also
available.
FERRITE IMPEDANCE DEPENDS ON
Material
Permeability
Frequency
Number of Turns
Size
Shape
Temperature
Field Strenght (generated by
current flowing through wire)
Figure 9.30
Recent ly, PSpice fer r it e models for Fair -Rit e mat er ials have become available t hat
allow fer r it e impedance t o be est imat ed [Refer ence 12]. The models of Fair -Rit e
mat er ials #43 and #73 can be downloaded fr om t he Micr oSim bullet in boar d (714-
830-1550). These models have been designed t o mat ch measur ed impedances r at her
t han t heor et ical impedances.
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1
A fer r it e’s impedance is dependent upon a number of int er -dependent var iables, and
is difficult t o quant ify analyt ically, t hus select ing t he pr oper fer r it e is not
st r aight for war d. However , knowing t he following syst em char act er ist ics will make
select ion easier . Fir st , det er mine t he fr equency r ange of t he noise t o be filt er ed. A
spect r um analyzer is useful her e. Second, t he expect ed t emper at ur e r ange of t he
filt er should be known, because fer r it e impedance var ies wit h t emper at ur e. Thir d,
t he DC bias cur r ent flowing t hr ough t he fer r it e must be known, t o ensur e t hat t he
fer r it e does not sat ur at e. Alt hough models and ot her analyt ical t ools may pr ove
useful, t he gener al guidelines given above, coupled wit h some exper iment at ion wit h
t he act ual filt er connect ed t o t he supply out put under syst em load condit ions, should
ult imat ely lead t o t he select ion of t he pr oper fer r it e.
CHOOSING THE RIGHT FERRITE DEPENDS ON
Source of Interference
Interference Frequency Range
Impedance Required at Interference Frequency
Environmental Conditions:
Temperature, AC and DC Field Strength,
Size / Space Available
Don’t fail to Test the Design -------
EXPERIMENT! EXPERIMENT!
Figure 9.31
Maint aining high power supply efficiency r equir es t he int elligent limit ing of ser ies
r esist or s and linear post r egulat or s in t he swit ching supply’s out put . However , small
r esist or s (gener ally less t han 10ohms) can be used in applicat ions wher e load
cur r ent s ar e low and load r egulat ion is not highly cr it ical.
Higher per for mance linear post r egulat or s can pr ovide 60dB and mor e of power
supply r eject ion up t o 100kHz, for example see t he designs of [Refer ence 8]. When
used wit h effect ive input filt er ing, t heir PSRR can be ext ended above 1MHz or
higher . Linear post r egulat ion will gener ally r esult in a net efficiency decr ease,
which can be ser ious if t he r egulat or r equir es sever al volt s of headr oom. The PSRR
vs. fr equency per for mance of a linear post r egulat or should also be car efully
consider ed. For example, some low dr opout linear r egulat or s offer ver y lit t le power
supply r eject ion at fr equencies above a few kHz, a per for mance fact of life which
must be t r aded off against t he efficiency advant ages of t he <100mV level dr opout s
t hey can boast .
Using t he component select ion choices ment ioned above, low and high fr equency
band filt er s can be designed t o smoot h t he noisy swit cher ’s DC out put so as t o
pr oduce an analog ready 5V supply. It is most pr act ical t o do t his over t wo (and
somet imes mor e) st ages, wit h each st age opt imized for a r ange of fr equencies. One
basic st age can be used t o car r y all of t he DC load cur r ent , and filt er noise by 60dB
or mor e up t o about 10MHz. This lar ger filt er is used as a card entry filter pr oviding
br oadband filt er ing for all analog power ent er ing t he PC boar d. Ther eaft er , smaller
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and mor e simple local filt er st ages can be used t o pr ovide ver y high fr equency
decoupling, r ight at t he power pins of t he individual ICs.
Figur e 9.32 illust r at es a car d ent r y filt er suit able for use wit h swit ching supplies.
Because of t he low r olloff point of 1.5kHz and mV level DC er r or s, it will be effect ive
for a wide var iet y of filt er applicat ions just as it is shown. This filt er is a single st age
LC low-pass filt er cover ing t he 1kHz t o 1MHz r ange, using car efully chosen par t s.
Because of component losses, it begins t o lose effect iveness above a few MHz, but is
st ill able t o achieve an at t enuat ion appr oaching 60dB at 1MHz.
The key t o low DC losses is t he use of input choke, L1, a fer r it e-cor e unit select ed for
a low DC r esist ance (DCR) of <0.25ohms at t he 100µH induct ance. The pr ot ot ype
was t est ed wit h an axial lead t ype 5250 choke, but t he r adial st yle 6000-101K should
give compar able r esult s [Refer ence 13]. Bot h chokes have a low induct ance shift due
t o t he 300mA load cur r ent . The low DCR allows t he 300mA t o be passed wit h no
mor e t han 75mV of DC er r or at full load. Alt er nat ely, r esist ive filt er ing might be
used in place of L1, but t he basic t r adeoff her e is t hat load cur r ent capacit y will be
compr omised for compar able DC er r or s. For example, a 1ohm r esist or wit h a 75mV
DC allowable er r or can pass only a 75mA cur r ent .
C1, a 100µF/20V t ant alum t ype, pr ovides t he bulk of t he capacit ive filt er ing,
shunt ed by a 1µF mult ilayer cer amic. The r emaining par t of t he filt er is R1, a
damping r esist or used t o cont r ol r esonant peaks.
“CARD-ENTRY” SWITCHING SUPPLY FILTER
Figure 9.32
Figur e 9.33 shows t he fr equency r esponse of t his filt er , bot h in t er ms of a SPICE
simulat ion as well as lab measur ement s. Ther e is good agr eement bet ween t he
simulat ion and t he measur ement s for t he common r ange below 1MHz.
Measur ement s wer e not made above 1MHz, since higher fr equencies ar e at t enuat ed
by second st age localized high fr equency filt er s.
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3
This filt er has some pot ent ial pit falls, and one of t hem is t he cont r ol of r esonances. If
t he LCR cir cuit for med does not have sufficient ly high r esist ance at t he r esonant
fr equency, amplit ude peaking will r esult . This peaking can be minimized wit h
r esist ance at t wo locat ions: in ser ies wit h L1, or in ser ies wit h C1+C2. Obviously,
limit ed r esist ance is usable in ser ies wit h L1, as t his incr eases t he DC er r or s. Thus
t he use of t he C1+C2 ser ies damping r esist or R1, which should not be eliminat ed.
The 1ohm value used act ually pr ovides a slight ly under damped r esponse, wit h
peaking on t he or der of 1dB. An alt er nat e value of 1.5ohms can also be used for less
peaking, if t his is desir ed, but t he t r adeoff her e is t hat t he at t enuat ion below 1MHz
will t hen suffer .
Not e t hat if t he damping r esist or wer e t o be eliminat ed or an excessively low value
used, it is possible t hat a t r ansient at t he fr equency of L1-(C1+C2) r esonance could
cause t he filt er t o r ing, act ually exacer bat ing what ever peak amplit ude occur s at t he
input . Of cour se, keeping t he basic filt er cor ner fr equency well below t he lowest
commonly used swit cher fr equency of 20kHz also helps t o minimize t his possibilit y.
A side benefit of R1 is t hat it buffer s var iat ions in par asit ic r esist ance in L1 and C1,
by making t hem smaller per cent age of t he t ot al r esist ance, and t hus less likely t o
effect over all per for mance. For wide t emper at ur e applicat ions however , t emper at ur e
changes of t he filt er char act er ist ics will st ill need consider at ion.
OUTPUT RESPONSE OF “CARD-ENTRY” FILTER
LAB VS. SIMULATION
Figure 9.33
Because of t he high sensit ivit y t o sour ce ser ies r esist ance of t his filt er , measur ing it s
fr equency r esponse is not a t r ivial t ask. The low out put impedance high cur r ent
unit y gain buffer of Figur e 9.34 was used for t he dat a of Figur e 9.33. Not e t hat t he
filt er pr esent s a load of ~1ohms t o t he sour ce at r esonance, so t he buffer dr ive level
is kept less t han 100mV RMS, t o pr event buffer cur r ent limit ing.
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TEST SETUP FOR MEASURING
FILTER FREQUENCY RESPONSE
Figure 9.34
A local high fr equency filt er which can be used in conjunct ion wit h t he car d ent r y
filt er is shown in Figur e 9.35. This simple filt er can be consider ed an opt ion, one
which is exer cised dependent upon t he high fr equency char act er ist ics of t he
associat ed IC and t he r elat ive at t enuat ion desir ed. It is composed of Z1, a leaded
fer r it e bead such as t he Panasonic EXCELSA39, which pr ovides a r esist ance of mor e
t han 80ohms at 10MHz, incr easing t o over 100ohms at 100MHz. The fer r it e bead is
best used wit h a local high fr equency decoupling cap r ight at t he IC power pins, such
as a 0.1µF cer amic unit shown.
HIGH FREQUENCY LOCALIZED DECOUPLING
Figure 9.35
Bot h t he car d ent r y filt er and t he local high fr equency decoupling filt er s ar e
designed t o filt er differ ent ial-mode noise only. They use component s commonly
available off t he shelf fr om nat ional dist r ibut or s [Refer ence 14].
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5
The following is a list of swit ching power supply filt er layout and const r uct ion
guidelines which will help guar ant ee t hat t he filt er does t he best job possible:
(1) Pick the highest electrical value and voltage rating for filter capacitors which is
consistent with budget and space limits. This minimizes ES R, and maximizes filter
performance. Pick chokes for low inductance change at the rated DC current, as well
as low DCR.
(2) Use short and wide PCB tracks to decrease voltage drops and minimize
inductance. Make track widths at least 200 mils for every inch of track length for
lowest DCR, and use 1 oz or 2 oz copper PCB traces to further reduce IR drops and
inductance.
(3) Use short leads or leadless components, to minimize lead inductance. This will
minimize the tendency to add excessive ES L and/ or ES R. S urface mount packages
are preferred.
(4) Use a large-area ground plane for minimum impedance.
(5) Know what your components do over frequency, current and temperature
variations! Make use of vendor component models for the simulation of prototype
designs, and make sure that lab measurements correspond reasonably with the
simulation. While simulation is not absolut ely necessary, it does instill confidence in
a design when correlation is achieved (see Refer ence 15).
The discussion of swit ching power supplies so far has focused on filt er ing t he out put
of t he supply. This assumes t hat t he incoming AC power is r elat ively clean, an
assumpt ion not always valid. However , t he AC power can also be an EMI pat h, bot h
ent er ing and exit ing t he equipment . To r emove t his pat h and r educe emissions
caused by t he swit ching power supply and ot her cir cuit s in t he inst r ument , a power
line filt er is r equir ed. Remember that the AC line power can be lethal! Do not
experiment without proper equipment and training!
All component s used in power line filt er s should be UL appr oved, and t he best way
t o pr ovide t his for your equipment is t o specify only a complet e, packaged UL
appr oved filt er . It should be inst alled in such a manner t hat it is t he fir st t hing t he
AC line sees upon ent er ing t he equipment . St andar d t hr ee wir e IEC st yle line cor ds
ar e designed t o mat e wit h t hr ee t er minal male connect or s, which ar e int egr al t o
many line filt er s. This is t he best way t o do t his funct ion, as t his aut omat ically
gr ounds t he t hir d wir e t o t he shell of t he filt er and equipment chassis via a low
induct ance pat h.
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POWER LINE FILTERING IS ALSO IMPORTANT
Figure 9.36
Commer cial power line filt er s, such as t he one shown schemat ically in Figur e 9.37,
can be quit e effect ive in r educing noise. AC power -line noise is gener ally has bot h
common-mode and differ ent ial-mode component s. Common-mode noise is noise t hat
is found on any t wo of t he t hr ee power connect ions (black, whit e, or gr een) wit h t he
same amplit ude and polar it y. In cont r ast , differ ent ial-mode noise is noise found only
bet ween t wo lines.
TYPICAL COMMERCIAL POWER LINE FILTER
Figure 9.37
Common-mode noise is dominant at fr equencies over 1MHz and is gener ally
int r oduced int o t he AC lines t hr ough capacit ive coupling. Fer r it es pr ovide effect ive
filt er ing of t he high fr equency common-mode noise when used as common-mode
chokes. For example, t o cr eat e an effect ive common-mode choke, a few t ur ns of t he
input power leads can be wound ar ound a lar ge fer r it e. This pr ovides a simple and
effect ive solut ion for common-mode noise, but is ineffect ive against differ ent ial-mode
noise. Differ ent ial-mode noise can be minimized by using pr oper LC filt er ing
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t echniques as descr ibed ear lier in t his sect ion, using pr oper UL appr oved acr oss-t he-
line r at ed component s. A power -line filt er must be designed t o minimize bot h
common- and differ ent ial-mode noise t o keep EMI fr om ent er ing and leaving t he
syst em.
POWER LINE NOISE MODES
Common Mode:

Dominates above 1MHz, Primarily Capacitive Coupled
2200 to 4700pF typical shunt capacitor values
0.5 to 10mH typical series ferrite values
Differential Mode:

Dominates below 1MHz
0.1 to 2.2 F typical shunt capacitor values
Molyperm or powdered iron inductors, 100 to 200 H,
typical series values
Figure 9.38
Not ice t he common-mode choke for med by t he induct or s on bot h sides of t he filt er in
Figur e 9.37. These induct or s have a dual r ole, because t hey ar e also par t of t he
differ ent ial-mode LC filt er s. This filt er , using mult iple st ages, is an example of a
higher qualit y t ype.
As not ed, t he AC power line filt er should be in good elect r ical cont act wit h t he
chassis of t he inst r ument . Fur t her mor e, connect ing t he AC power line dir ect ly int o
t he power line filt er r educes t he possibilit y of EMI ent er ing or exit ing t he
inst r ument . If t his is not possible, r out ing t he filt er AC input power lines close t o t he
chassis and t wist ing t hem will help minimize loop ar eas and minimize LF magnet ic
coupling.
The power supply filt er should be locat ed as close as possible t o t he swit ching power
supply; i.e., in commer cial unit s it is always int egr al t o t he supply. Many swit ching
power supplies have st eel enclosur es which can be used for elect r ic and LF magnet ic
shielding (however , t he enclosur e must be connect ed t o chassis gr ound t o act as a
Far aday shield).
If digit al cir cuit r y is pr esent , t he digit al power pick-off point should occur before t he
swit ching power supply filt er . This minimizes t he digit al noise in t he out put of t he
swit ching supply filt er , plus minimizes any pot ent ial DC er r or for m t he higher
cur r ent s.
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POWER LINE FILTER PLACEMENT IS IMPORTANT
Figure 9.39
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9
REFERENCES: NOI SE REDUCTI ON AND FI LTERI NG FOR
SWI TCHI NG P OWER SUP P LI ES
1. EMC Desi gn Wor k sh op Not es, Kimmel-Ger ke Associat es, Lt d.,
St . Paul, MN. 55108, (612) 330-3728.
2. Walt J ung, Dick Mar sh, Picking Capacitors, Parts 1 & 2, Au d i o,
Febr uar y, Mar ch, 1980.
3. Tant alum Elect r olyt ic and Cer amic Capacit or Families, Kemet
Elect r onics, Box 5928, Gr eenville, SC, 29606, (803) 963-6300.
4. Type HFQ Aluminum Elect r olyt ic Capacit or and t ype V St acked
Polyest er Film Capacit or , Panasonic, 2 Panasonic Way, Secaucus,
NJ , 07094, (201) 348-7000.
5. OS-CON Aluminum Elect r olyt ic Capacit or 93/94 Technical Book,
Sanyo, 3333 Sanyo Road, For r est Cit y, AK, 72335, (501) 633-6634.
6. Ian Clelland, Metalized Polyester Film Capacitor Fills High Frequency
S witcher Needs, P CI M, J une 1992.
7. Type 5MC Met allized Polycar bonat e Capacit or , Elect r onic Concept s, Inc.,
Box 1278, Eat ont own, NJ , 07724, (908) 542-7880.
8. Walt J ung, Regulators for High-Performance Audio, Parts 1 and 2,
Th e Au d i o Ama t eu r , issues 1 and 2, 1995.
9. Henr y Ot t , Noi se Red u ct i on Tech n i qu es i n Elect r on i c Syst ems,
2d Ed ., 1988, Wiley.
10. Fair -Rit e Linear Fer r it es Cat alog, Fair -Rit e Pr oduct s, Box J , Wallkill,
NY, 12886, (914) 895-2055.
11. Type EXCEL leaded fer r it e bead EMI filt er , and t ype EXC L leadless
fer r it e bead, Panasonic, 2 Panasonic Way, Secaucus, NJ , 07094,
(201) 348-7000.
12. St eve Hageman, Use Ferrite Bead Models to Analyze EMI S uppression ,
Th e Desi gn Cen t er Sou r ce, Micr oSim Newslet t er , J anuar y, 1995.
13. Type 5250 and 6000-101K chokes, J . W. Miller , 306 E. Alondr a Blvd.,
Gar dena, CA, 90247, (310) 515-1720.
14. DIGI-KEY, PO Box 677, Thief River Falls, MN, 56701-0677,
(800) 344-4539.
15. Tant alum Elect r olyt ic Capacit or SPICE Models, Kemet Elect r onics,
Box 5928, Gr eenville, SC, 29606, (803) 963-6300.
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16. Eichhoff Elect r onics, Inc., 205 Hallene Road, War wick, RI., 02886,
(401) 738-1440.
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LOW DROP OUT REFERENCES AND
REGULATORS
Wa l t J u n g
Many cir cuit s r equir e st able r egulat ed volt ages r elat ively close in pot ent ial t o an
unr egulat ed sour ce. An example would be a linear post r egulat or for a swit ching
power supply, wher e volt age loss is cr it ical. This low dr opout t ype of r egulat or is
r eadily implement ed wit h a r ail-r ail out put op amp. The wide out put swing and low
sat ur at ion volt age enables out put s t o come wit hin a fr act ion of a volt of t he sour ce
for medium cur r ent (<30mA) loads, such as r efer ence applicat ions. For higher out put
cur r ent s, t he r ail-r ail volt age swing feat ur e allows dir ect dr ive t o low sat ur at ion
volt age pass devices, such as power PNPs or P-channel MOSFETs. Op amps which
wor k fr om 3V up wit h t he r ail-r ail feat ur es ar e most suit able her e, pr oviding power
economy and maximum flexibilit y.
BASI C REFERENCES I N LOW P OWER SYSTEMS
Among t he many pr oblems in making st able DC volt age r efer ences wor k fr om 5V
and lower supplies ar e quiescent power consumpt ion, over all efficiency, t he abilit y t o
oper at e down t o 3V, low input /out put (dr opout ) capabilit y, and minimum noise
out put . Because such low volt age supplies can't suppor t 6V zener s, t hese low volt age
r efer ences must necessar ily be bandgap based-- a 1.2V pot ent ial.
One difficult y is simply t o get a r efer ence cir cuit which wor ks well at 3V input s,
condit ions which dict at e a lower volt age r efer ence diode. A wor khor se cir cuit
solut ion is t he r efer ence and appr opr iat e low power scaling buffer shown in Figur e
9.40. Her e a low cur r ent 1.2V diode is used for D1, t he 1.235V AD589. Resist or R1
set s t he cur r ent , chosen for 50µA at t he minimum supply of 2.7V. Obviously, loading
on t he unbuffer ed diode must be minimized at t he V
REF
node.
RAIL-RAIL OUTPUT OP AMPS ALLOW GREATEST
FLEXIBILITY IN LOW DROPOUT REFERENCES
Figure 9.40
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2
The amplifier U1 bot h buffer s and opt ionally scales up t he 1.2V r efer ence, allowing
higher sour ce/sink cur r ent s. A higher op amp quiescent cur r ent is expended in doing
t his, and is a basic design t r adeoff of t his appr oach. This cur r ent can r ange fr om
150-300µA/channel wit h t he OP295/495 and OP191/291/491 ser ies for U1,
620µA/channel using an AD820/822/824 sect ion, or in t he r ange of 1000-
2000µA/channel wit h t he OP284 and OP279. The for mer t wo ser ies ar e most useful
for ver y light loads (<2mA), while t he lat t er t hr ee ser ies pr ovide device dependent
out put s up t o 50mA. All devices ar e simply used in t he cir cuit as shown, and t heir
key specs ar e summar ized in Figur e 9.41.
OP AMPS USEFUL IN LOW VOLTAGE RAIL-RAIL
REFERENCES AND REGULATORS
Figure 9.41
In Figur e 9.40, wit hout gain scaling r esist or s R2-R3, V
OUT
is simply 1.235V. Wit h
t he r esist or s, V
OUT
can be anywher e bet ween t he r ails, due t o t he r ail-r ail out put
swing of t he op amps ment ioned above. Wit h r ail-r ail devices, t his buffer ed r efer ence
is inher ent ly "low dr opout ", allowing a +4.5V r efer ence out put on a +5V supply, for
example. The gener al expr ession for V
OUT
is shown in t he figur e, wher e “V
REF
” is
t he r efer ence volt age, in t his case 1.235V.
Amplifier st andby cur r ent can be opt ionally r educed t o below 20µA if an amplifier
fr om t he OP193/293/493 ser ies is used. This will be at t he expense of cur r ent dr ive
and posit ive r ail sat ur at ion, but does pr ovide t he lowest possible quiescent cur r ent
when necessar y. All devices oper at e fr om volt ages down t o 3V (except t he OP279,
which oper at es at 5V).
Power conser vat ion can be a cr it ical issue wit h r efer ences, as can out put DC
pr ecision. For such applicat ions, simple one-package fixed volt age r efer ences which
simply “dr op in” wit h minimal ext er nal cir cuit r y and deliver high accur acy ar e most
at t r act ive. Two unique feat ur es of t he t hr ee t er minal REF19X bandgap r efer ence
family ar e low power , and shut down capabilit y. The ser ies allows fixed out put s fr om
2.048-5V t o be cont r olled bet ween ON and OFF, via a TTL/CMOS power cont r ol
input . It pr ovides pr ecision r efer ence qualit y for t hose popular volt ages shown in
Figur e 9.42.
4
3
30mA REFERENCE FAMILY WITH OPTIONAL SHUTDOWN
Figure 9.42
The REF19X family can be used as a simple t hr ee t er minal fixed r efer ence as per
t he t able by t ying pins 2 and 3 t oget her , or as an ON/OFF cont r olled device, by
pr ogr amming pin 3 as not ed. In addit ion t o t he shut down capacit y, t he
dist inguishing funct ional feat ur es ar e a low dr opout of 0.5V at 10mA, and a low
cur r ent dr ain for bot h quiescent and shut down st at es, 45 and 15µA (max.),
r espect ively. For example, wor king fr om input s in t he r ange of 6.3 t o 15V, a REF195
used as shown dr ives 5V loads at up t o 30mA, wit h gr ade dependent t oler ances of ±2
t o ±5mV, and max TCs of 5 t o 25ppm/°C. Ot her devices in t he ser ies pr ovide
compar able accur acy specificat ions, and all have low dr opout feat ur es.
To maximize DC accur acy in t his cir cuit , t he out put of U1 should be connect ed
dir ect ly t o t he load wit h shor t heavy t r aces, t o minimize IR dr ops. The common
t er minal (pin 4) is less cr it ical due t o lower cur r ent in t his leg.
LOW DROP OUT REGULATORS
By adding a boost t r ansist or t o t he basic r ail-r ail out put low dr opout r efer ence of
Figur e 9.40, out put cur r ent s of 100mA or mor e ar e possible, while st ill r et aining
feat ur es of low st andby cur r ent and low dr opout volt age. Figur e 9.43 shows a low
dr opout r egulat or wit h 800µA st andby cur r ent , suit able for a var iet y of out put s at
cur r ent levels of 100mA.
4
4
100mA LOW NOISE, LOW DROPOUT REGULATOR
Figure 9.43
The 100mA out put is achieved wit h a cont r olled gain bipolar power t r ansist or for
pass device Q1, an MJ E170. Maximum out put cur r ent cont r ol is pr ovided by limit ing
base dr ive t o Q1 wit h ser ies r esist or R3. This limit s t he base cur r ent t o about 2mA,
so t he max H
FE
of Q1 t hen allows no mor e t han 500mA, t hus limit ing Q1’s shor t
cir cuit dissipat ion t o safe levels.
Over all, t he cir cuit oper at es as a follower wit h gain, as was t r ue in t he case of Figur e
9.40, so V
OUT
has a similar out put expr ession. The cir cuit is adapt ed for differ ent
volt ages simply by pr ogr amming R1 via t he t able. Dr opout wit h a 100mA load is
about 200mV, t hus a 5V out put is maint ained for input s above 5.2V (see t able), and
V
OUT
levels down t o 3V ar e possible. St ep load r esponse of t his cir cuit is quit e good,
and t r ansient er r or is only a few mVp-p for a 30-100mA load change. This is
achieved wit h low ESR swit ching t ype capacit or s at C1-C2, but t he cir cuit also
wor ks wit h convent ional elect r olyt ics (wit h higher t r ansient er r or s).
If desir ed, lowest out put noise wit h t he AD820 is r eached by including t he opt ional
r efer ence noise filt er , R5-C3. Lower cur r ent op amps can also be used for lower
st andby cur r ent , but wit h lar ger t r ansient er r or s due t o r educed bandwidt h.
While t he 30mA r at ed out put cur r ent of t he REF19X ser ies is higher t han most
r efer ence ICs, it can be boost ed t o much higher levels if desir ed, wit h t he addit ion of
a PNP t r ansist or , as shown in Figur e 9.44. This cir cuit uses full t ime cur r ent
limit ing for pr ot ect ion of pass t r ansist or shor t s.
4
5
150mA BOOSTED OUTPUT REGULATOR/REFERENCE
WITH CURRENT LIMITING
Figure 9.44
In t his cir cuit t he supply cur r ent of r efer ence U1 flows in R1-R2, developing a base
dr ive for pass device Q1, whose collect or pr ovides t he bulk of t he out put cur r ent .
Wit h a t ypical gain of 100 in Q1 for 100-200mA loads, U1 is never r equir ed t o
fur nish mor e t han a few mA, and t his fact or minimizes t emper at ur e r elat ed dr ift .
Shor t cir cuit pr ot ect ion is pr ovided by Q2, which clamps dr ive t o Q1 at about 300mA
of load cur r ent . Wit h separ at ion of cont r ol/power funct ions, DC st abilit y is opt imum,
allowing best advant age of pr emium gr ade REF19X devices for U1. Of cour se, load
management should st ill be exer cised. A shor t , heavy, low r esist ance conduct or
should be used fr om U1-6 t o t he V
OUT
sense point “S”, wher e t he collect or of Q1
connect s t o t he load.
Because of t he cur r ent limit ing, dr opout volt age is r aised about 1.1V over t hat of t he
REF19X devices. However , over all dr opout t ypically is st ill low enough t o allow
oper at ion of a 5 t o 3.3V r egulat or /r efer ence using t he 3.3V REF-196 for U1, wit h a
Vs of 4.5V and a load cur r ent of 150mA.
The heat sink r equir ement s of Q1 depend upon t he maximum power . Wit h Vs = 5V
and a 300mA cur r ent limit , t he wor st case dissipat ion of Q1 is 1.5W, less t han t he
TO-220 package 2W limit . If TO-39 or TO-5 packaged devices such as t he 2N4033
ar e used, t he cur r ent limit should be r educed t o keep maximum dissipat ion below
t he package r at ing, by r aising R4. A t ant alum out put capacit or is used at C1 for it s
low ESR, and t he higher value is r equir ed for st abilit y. Capacit or C2 pr ovides input
bypassing, and can be a or dinar y elect r olyt ic.
Shut down cont r ol of t he boost er st age is shown as an opt ion, and when used, some
caut ions ar e in or der . To enable shut down cont r ol, t he connect ion t o U1-2 and U1-3
is br oken at “X”, and diode D1 allows a CMOS cont r ol sour ce t o dr ive U1-3 for
ON/OFF cont r ol. St ar t up fr om shut down is not as clean under heavy load as it is
wit h t he basic REF19X ser ies st and-alone, and can r equir e sever al milliseconds
4
6
under load. Never t heless, it is st ill effect ive, and can fully cont r ol 150mA loads.
When shut down cont r ol is used, heavy capacit ive loads should be minimized.
By combining a REF19X ser ies r efer ence IC wit h a r ail-r ail out put op amp, t he best
of bot h wor lds is r ealized per for mance-wise (see Figur e 9.45). The REF19X basic
r efer ence pr ovides a st able low TC volt age sour ce wit h low cur r ent dr ain, while t he
r ail-r ail out put op amp pr ovides high out put cur r ent wit h bot h sink/sour ce load
capabilit y.
30mA OUTPUT CURRENT REGULATOR/REFERENCE
Figure 9.45
The low dr opout per for mance of t his cir cuit is pr ovided by st age U2, 1/2 of an OP279
connect ed as a follower /buffer for t he V
OUT2
as pr oduced by U1. The low volt age
sat ur at ion char act er ist ic of t he OP279 allows up t o 30 mA of load cur r ent in t he
illust r at ed use, a 5V t o 3.3V conver t er . In t his applicat ion t he st able 3.3V fr om U1 is
applied t o U2 t hr ough a noise filt er , R1-C1. U2 r eplicat es t he U1 volt age wit hin a
few mV, but at a higher cur r ent out put at V
OUT1
. It also has abilit y t o bot h sink
and sour ce out put cur r ent (s), unlike most IC r efer ences. R2 and C2 in t he feedback
pat h of U2 pr ovide bias compensat ion for lowest DC er r or and addit ional noise
filt er ing.
To scale V
OUT2
t o anot her (higher ) out put level, t he opt ional r esist or R3 (shown
dot t ed) is added, causing t he new V
OUT1
t o become:
V
OUT
V
OUT
R
R
1 2
1
2
3
· +

]
]
]
As an example, for a V
OUT1
= 4.5V, and V
OUT2
= 2.5V fr om a REF192, t he gain
r equir ed of U2 is 1.8 t imes, so R3 and R2 would be chosen for a r at io of 1.25/1, or
22.5kohm/18kohm. Not e t hat for t he lowest V
OUT1
DC er r or , R2| | R3 should be
4
7
maint ained equal t o R1 (as her e), and t he R2-R3 r esist or s should be st able, close
t oler ance met al film t ypes.
Per for mance of t he cir cuit is good in bot h AC and DC senses, wit h t he measur ed DC
out put change for a 30mA load change under 1mV, equivalent t o an out put
impedance of <0.03ohm. The t r ansient per for mance for a st ep change of 0-10mA of
load cur r ent is det er mined lar gely by t he R5-C5 out put net wor k. Wit h t he values
shown, t he t r ansient is about 10mV peak, and set t les t o wit hin 2mV in 8µs, for
eit her polar it y. Fur t her r educt ion in t r ansient amplit ude is possible by r educing R5
and possibly incr easing C3, but t his should be ver ified by exper iment t o minimize
excessive r inging wit h some capacit or t ypes. Load cur r ent st ep changes smaller t han
10mA will of cour se show less t r ansient er r or .
The cir cuit can be used eit her as shown as a 5 t o 3.3V r efer ence/r egulat or , or it can
also be used wit h ON/OFF cont r ol. By dr iving pin 3 of U1 wit h a logic cont r ol signal
as not ed, t he out put is swit ched ON/OFF. Not e t hat when ON/OFF cont r ol is used,
r esist or R4 must be used wit h U1, t o speed ON-OFF swit ching.
As not ed, t he “low dr opout ” st yle of r egulat or is r eadily implement ed wit h a r ail-r ail
out put op amps such as t hose of Figur e 9.41, as t heir wide out put swing allows easy
dr ive t o a low sat ur at ion volt age pass device. Fur t her , it is most useful when t he op
amp has a r ail-r ail input feat ur e, as t his allows high-side cur r ent sensing, for
posit ive r ail cur r ent limit ing. Typical applicat ions ar e volt ages developed fr om a 3-
9V r ange syst em sour ces, or anywher e wher e low dr opout per for mance is r equir ed
for power efficiency. The 4.5V case her e wor ks fr om 5V nominal sour ces, wit h wor st -
case levels down t o 4.6V or less.
Figur e 9.46 shows such a r egulat or using an OP284 plus a low R
ds(on)
P-channel
MOSFET pass device. Low dr opout per for mance is pr ovided by Q1, wit h a r at ing of
0.11ohm wit h a gat e dr ive of 2.7V. This r elat ively low gat e dr ive allows oper at ion on
supplies as low as 3V wit hout compr omise t o over all per for mance.
4
8
300mA LOW DROPOUT REGULATOR
WITH HIGH-SIDE CURRENT SENSING
Figure 9.46
The cir cuit ’s main volt age cont r ol loop oper at ion is pr ovided by U1B, half of t he
OP284. This volt age cont r ol amplifier amplifies t he 2.5V r efer ence volt age pr oduced
by U2, a REF192. The r egulat ed out put volt age V
OUT
is t hen of t he same for m as
not ed in t he pr evious cir cuit .
Not e t hat for t he lowest V
OUT
DC er r or , R2| | R3 should be maint ained equal t o R1
(as her e), and t he R2-R3 r esist or s should be st able, close t oler ance met al film t ypes.
The t able suggest s R1-R3 values for popular out put volt ages. In gener al, V
OUT
can
be anywher e bet ween V
OUT2
and t he 12V maximum r at ing of Q1.
While t he low volt age sat ur at ion char act er ist ic of Q1 is par t of t he low dr opout key,
t he ot her advant age is a low and accur at e cur r ent -sense compar ison. Her e, t his is
pr ovided by cur r ent sense amplifier U1A, which is pr ovided a 20mV r efer ence fr om
t he 1.235V AD589 r efer ence diode D2 and t he R7-R8 divider . When t he pr oduct of
t he out put cur r ent and Rs mat ch t his t hr eshold, cur r ent cont r ol is act ivat ed, and
U1A dr ives Q1’s gat e via D1. Over all cir cuit oper at ion is t hen under cur r ent mode
cont r ol, wit h a cur r ent limit I
limit
defined as:
I
it
V
R D
Rs
R
R R
lim
( )
·

]
]
]
]
+

]
]
]
2 7
7 8
Obviously t he compar ison volt age should be small, since it becomes a significant
por t ion of t he over all dr opout volt age. Her e, t he 20mV value used is higher t han t he
t ypical offset of t he OP284, but st ill r easonably low as a per cent age of V
OUT
(<0.5%). For ot her I
limit
levels, sense r esist or Rs should be set along wit h R7-R8, t o
maint ain t his t hr eshold volt age bet ween 20 and 50mV.
For a 4.5V out put ver sion, measur ed DC out put change for a 225mA load change
was on t he or der of a few µV, while t he dr opout volt age at t his same cur r ent level
4
9
was about 30mV. The cur r ent limit as shown is 400mA, allowing oper at ion at levels
up t o 300mA or mor e. While t he Q1 device can suppor t cur r ent s of sever al amper es,
a pr act ical cur r ent r at ing t akes int o account t he SO-8 device’s 2.5W 25°C
dissipat ion. A shor t -cir cuit cur r ent of 400mA at an input level of 5V will cause a 2W
dissipat ion in Q1, so ot her input condit ions should be consider ed car efully in t er ms
of Q1’s pot ent ial over heat ing. If higher power ed devices ar e used for Q1, t he cir cuit
will suppor t out put s of t ens of amper es as well as t he higher V
OUT
levels not ed
above.
The cir cuit can be used eit her as shown for a st andar d low dr opout r egulat or , or it
can also be used wit h ON/OFF cont r ol. Not e t hat when t he out put is OFF in t his
cir cuit , it is st ill act ive (i.e., not an open cir cuit ). This is because t he OFF st at e
simply r educes t he volt age input t o R1, leaving t he U1A/B amplifier s and Q1 st ill
act ive.
When ON/OFF cont r ol is used, r esist or R10 should be used wit h U1, t o speed ON-
OFF swit ching, and t o allow t he out put of t he cir cuit t o set t le t o a nominal zer o
volt age. Component s D3 and R11 also aid in speeding up t he ON-OFF t r ansit ion, by
pr oviding a dynamic dischar ge pat h for C2. OFF-ON t r ansit ion t ime is less t han
1ms, while t he ON-OFF t r ansit ion is longer , but under 10ms.
5
0
REFERENCES: LOW DROP OUT REFERENCES AND
REGULATORS

1. Walt J ung, Build an Ultra-Low-Noise Voltage Reference,
Elect r on i c Desi gn An a log Ap p li ca t i on s I ssu e, J une 24, 1993.
2. Walt J ung, Getting the Most from IC Voltage References, An a log
Di a logu e 28-1, 1994.
3. Walt J ung, The Ins and Outs of ‘Green’ Regulators/ References ,
Elect r on i c Desi gn An a log Ap p li ca t i on s I ssu e, J une 27, 1994.
4. Walt J ung, Very-Low-Noise 5-V Regulator, Elect r on i c Desi gn ,
J uly 25, 1994.
5
1
EMI /RFI CONSI DERATI ONS
Ad ol f o A. Ga r ci a
Elect r omagnet ic int er fer ence (EMI) has become a hot t opic in t he last few year s
among cir cuit designer s and syst ems engineer s. Alt hough t he subject mat t er and
pr ior ar t have been in exist ence for over t he last 50 year s or so, t he advent of
por t able and high-fr equency indust r ial and consumer elect r onics has pr ovided a
comfor t able st andar d of living for many EMI t est ing engineer s, consult ant s, and
publisher s. Wit h t he help of EDN Magazine and Kimmel Ger ke Associat es, t his
sect ion will highlight gener al issues of EMC (elect r om agnet ic compat ibilit y) t o
familiar ize t he syst em/cir cuit designer wit h t his subject and t o illust r at e pr oven
t echniques for pr ot ect ion against EMI.
A P RI MER ON EMI R EGULATI ONS
The int ent of t his sect ion is t o summar ize t he differ ent t ypes of elect r omagnet ic
compat ibilit y (EMC) r egulat ions imposed on equipment manufact ur er s, bot h
volunt ar y and mandat or y. Published EMC r egulat ions apply at t his t ime only t o
equipment and syst ems, and not t o component s. Thus, EMI hardened equipment
does not necessar ily imply t hat each of t he component s used (int egr at ed cir cuit s,
especially) in t he equipment must also be EMI hardened.
Commer ci a l Equ i p men t
The t wo dr iving for ces behind commer cial EMI r egulat ions ar e t he FCC (Feder al
Communicat ions Commission) in t he U. S. and t he VDE (Ver band Deut scher
Elect r ot echniker ) in Ger many. VDE r egulat ions ar e mor e r est r ict ive t han t he FCC’s
wit h r egar d t o emissions and r adiat ion, but t he Eur opean Communit y will be
adding immunit y t o RF, elect r ost at ic dischar ge, and power -line dist ur bances t o t he
VDE r egulat ions, and will r equir e mandat or y compliance in 1996. In J apan,
commer cial EMC r egulat ions ar e cover ed under t he VCCI (Volunt ar y Cont r ol
Council for Int er fer ence) st andar ds and, implied by t he name, ar e much looser t han
t heir FCC and VDE count er par t s.
All commer cial EMI r egulat ions pr imar ily focus on radiated emissions, specifically
t o pr ot ect near by r adio and t elevision r eceiver s, alt hough bot h FCC and VDE
st andar ds ar e less st r ingent wit h r espect t o conducted int er fer ence (by a fact or of 10
over r adiat ed levels). The FCC Par t 15 and VDE 0871 r egulat ions gr oup commer cial
equipment int o t wo classes: Class A, for all pr oduct s int ended for business
envir onment s; and Class B, for all pr oduct s used in r esident ial applicat ions. For
example, Table 9.1 illust r at es t he elect r ic-field emission limit s of commer cial
comput er equipment for bot h FCC Par t 15 and VDE 0871 compliance.
5
2
Radiated Emission Limits for Commercial Computer Equipment
Fr equ en cy (MHz) Cla ss A
( a t 3 m)
Cla ss B
(a t 3 m)
30 - 88 300 µV/m 100 µV/m
88 - 216 500 µV/m 150 µV/m
216 - 1000 700 µV/m 200 µV/m
Repr int ed fr om EDN Magazine (J anuar y 20, 1994), © CAHNERS PUBLISHING
COMPANY 1995, A Division of Reed Publishing USA.
Table 9.1
In addit ion t o t he alr eady st r ingent VDE emission limit s, t he Eur opean Communit y
EMC st andar ds (IEC and IEEE) will r equir e mandat or y compliance in 1996 t o t hese
addit ional EMI t hr eat s: Immunit y t o RF fields, elect r ost at ic dischar ge, and power -
line dist ur bances. All equipment /syst ems mar ket ed in Eur ope must exhibit an
immunit y t o RF field st r engt hs of 1-10V/m (IEC st andar d 801-3), elect r ost at ic
dischar ge (gener at ed by human cont act or t hr ough mat er ial movement ) in t he r ange
of 10-15kV (IEC st andar d 801-2), and power -line dist ur bances of 4kV EFTs
(ext r emely fast t r ansient s, IEC st andar d 801-4) and 6kV light ning sur ges (IEEE
st andar d C62.41).
Mi li t a r y Equ i p men t
The defining EMC specificat ion for milit ar y equipment is MIL-STD-461 which
applies t o r adiat ed equipment emissions and equipment suscept ibilit y t o
int er fer ence. Radiat ed emission limit s ar e ver y t ypically 10 t o 100 t imes mor e
st r ingent t han t he levels shown in Table 9.1. Requir ed limit s on immunit y t o RF
fields ar e t ypically 200 t imes mor e st r ingent (RF field st r engt hs of 5-50mV/m) t han
t he limit s for commer cial equipment .
Med i ca l Equ i p men t
Alt hough not yet mandat or y, EMC r egulat ions for medical equipment ar e pr esent ly
being defined by t he FDA (Food and Dr ug Administ r at ion) in t he USA and t he
Eur opean Communit y. The pr imar y focus of t hese EMC r egulat ions will be on
immunit y t o RF fields, elect r ost at ic dischar ge, and power -line dist ur bances, and
may ver y well be mor e st r ingent t han t he limit s spelled out in MIL-STD-461. The
pr imar y object ive of t he medical EMC r egulat ions is t o guar ant ee safet y t o humans.
I n d u st r i a l- a n d P r ocess-Con t r ol Equ i p men t
Pr esent ly, equipment designed and mar ket ed for indust r ial- and pr ocess-cont r ol
applicat ions ar e not r equir ed t o meet pr e-exist ing mandat or y EMC r egulat ions. In
fact , manufact ur er s ar e exempt fr om complying t o any st andar d in t he USA.
However , since indust r ial envir onment s ar e ver y much elect r ically hostile, all
5
3
equipment manufact ur er s will be r equir ed t o comply wit h all Eur opean Communit y
EMC r egulat ions by 1996.
Au t omot i ve Equ i p men t
Per haps t he most difficult and host ile envir onment in which elect r ical cir cuit s and
syst ems must oper at e is t hat found in t he aut omobile. All of t he key EMI t hr eat s t o
elect r ical syst ems exist her e. In addit ion, oper at ing t emper at ur e ext r emes, moist ur e,
dir t , and t oxic chemicals fur t her exacer bat e t he pr oblem. To complicat e mat t er s
fur t her , st andar d t echniques (fer r it e beads, feed-t hr ough capacit or s, induct or s,
r esist or s, shielded cables, wir es, and connect or s) used in ot her syst ems ar e not
gener ally used in aut omot ive applicat ions because of t he cost of t he addit ional
component s.
Pr esent ly, aut omot ive EMC r egulat ions, defined by t he ver y compr ehensive SAE
St andar ds J 551 and J 1113, ar e not yet mandat or y. They ar e, however , ver y r igor ous.
SAE st andar d J 551 applies t o vehicle-level EMC specificat ions, and st andar d J 1113
(funct ionally similar t o MIL-STD-461) applies t o all aut omot ive elect r onic modules.
For example, t he J 1113 specificat ion r equir es t hat elect r onic modules cannot r adiat e
elect r ic fields gr eat er t han 300nV/m at a dist ance of 3 met er s. This is r oughly 1000
t imes mor e st r ingent t han t he FCC Par t 15 Class A specificat ion. In many
applicat ions, aut omot ive manufact ur er s ar e imposing J 1113 RF field immunit y
limit s on each of the active components used in t hese modules. Thus, in t he ver y near
fut ur e, aut omot ive manufact ur er s will r equir e t hat IC pr oduct s comply wit h exist ing
EMC st andar ds and r egulat ions.
EMC Regu la t i on s’ I mp a ct on Desi gn
In all t hese applicat ions and many mor e, complying wit h mandat or y EMC
r egulat ions will r equir e car eful design of individual cir cuit s, modules, and syst ems
using est ablished t echniques for cable shielding, signal and power -line filt er ing
against bot h small- and lar ge-scale dist ur bances, and sound mult i-layer PCB
layout s. The key t o success is t o incor por at e sound EMC pr inciples ear ly in t he
design phase t o avoid t ime-consuming and expensive r edesign effor t s.
P ASSI VE COMP ONENTS: YOUR ARSENAL AGAI NST EMI
Minimizing t he effect s of EMI r equir es t hat t he cir cuit /syst em designer be
complet ely awar e of t he pr imar y ar senal in t he bat t le against int er fer ence: passive
components. To successfully use t hese component s, t he designer must under st and
t heir non-ideal behavior . For example, Figur e 9.47 illust r at es t he real behavior of
t he passive component s used in cir cuit design. At ver y high fr equencies, wir es
become t r ansmission lines, capacit or s become induct or s, induct or s become
capacit or s, and r esist or s behave as r esonant cir cuit s.
5
4
ALL PASSIVE COMPONENTS EXHIBIT
“NON IDEAL” BEHAVIOR
Repr int ed fr om EDN Magazine (J anuar y 20, 1994), © CAHNERS PUBLISHING
COMPANY 1995, A Division of Reed Publishing USA.
Figure 9.47
A specific case in point is t he fr equency r esponse of a simple wir e compar ed t o t hat
of a gr ound plane. In many cir cuit s, wir es ar e used as eit her power or signal r et ur ns,
and t her e is no gr ound plane. A wir e will behave as a ver y low r esist ance (less t han
0.02ohm/ft for 22-gauge wir e) at low fr equencies, but because of it s par asit ic
induct ance of appr oximat ely 20nH/ft , it becomes induct ive at fr equencies above
160kHz. Fur t her mor e, depending on size and r out ing of t he wir e and t he fr equencies
involved, it ult imat ely becomes a t r ansmission line wit h an uncont r olled impedance.
Fr om our knowledge of RF, unt er minat ed t r ansmission lines become ant ennas wit h
gain, as illust r at ed in Figur e 9.48. On t he ot her hand, lar ge ar ea gr ound planes ar e
much mor e well-behaved, and maint ain a low impedance over a wide r ange of
fr equencies. Wit h a good under st anding of t he behavior of real component s, a
st r at egy can now be developed t o find solut ions t o most EMI pr oblems.
5
5
IMPEDANCE COMPARISON: WIRE VS. GROUND PLANE
Figure 9.48
Wit h any pr oblem, a st r at egy should be developed befor e any effor t is expended
t r ying t o solve it . This appr oach is similar t o t he scient ific met hod: init ial cir cuit
misbehavior is not ed, t heor ies ar e post ulat ed, exper iment s designed t o t est t he
t heor ies ar e conduct ed, and r esult s ar e again not ed. This pr ocess cont inues unt il all
t heor ies have been t est ed and expect ed r esult s achieved and r ecor ded. Wit h r espect
t o EMI, a pr oblem solving fr amewor k has been developed. As shown in Figur e 9.49,
t he model suggest ed by Kimmel-Ger ke in [Refer ence 1] illust r at es t hat all t hr ee
element s (a source, a receptor or victim, and a path bet ween t he t wo) must exist in
or der t o be consider ed an EMI pr oblem. The sour ces of elect r omagnet ic int er fer ence
can t ake on many for ms, and t he ever -incr easing number of por t able
inst r ument at ion and per sonal communicat ions/comput at ion equipment only adds
t he number of possible sour ces and r ecept or s.
Int er fer ing signals r each t he r ecept or by conduction (t he cir cuit or syst em
int er connect ions) or radiation (par asit ic mut ual induct ance and/or par asit ic
capacit ance). In gener al, if t he fr equencies of t he int er fer ence ar e less t han 30MHz,
t he pr imar y means by which int er fer ence is coupled is t hr ough t he interconnects.
Bet ween 30MHz and 300MHz, t he pr imar y coupling mechanism is cable radiation
and connector leakage. At fr equencies gr eat er t han 300MHz, t he pr imar y
mechanism is slot and board radiation. Ther e ar e many cases wher e t he
int er fer ence is br oadband, and t he coupling mechanisms ar e combinat ions of t he
above.
5
6
A DIAGNOSTIC FRAMEWORK FOR EMI
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.49
When all t hr ee element s exist t oget her , a fr amewor k for solving any EMI pr oblem
can be dr awn fr om Figur e 9.50. Ther e ar e t hr ee t ypes of int er fer ence wit h which t he
cir cuit or syst em designer must cont end. The fir st t ype of int er fer ence is t hat
gener at ed by and emit t ed fr om an inst r ument ; t his is known as cir cuit /syst em
emission and can be eit her conducted or radiated. An example of t his would be t he
per sonal comput er . Por t able and deskt op comput er s must pass t he st r ingent FCC
Par t 15 specificat ions pr ior t o gener al use.
The second t ype of int er fer ence is cir cuit or syst em immunity. This descr ibes t he
behavior of an inst r ument when it is exposed t o lar ge elect r omagnet ic fields,
pr imar ily elect r ic fields wit h an int ensit y in t he r ange of 1 t o 10V/m at a dist ance of
3 met er s. Anot her t er m for immunit y is susceptibility, and it descr ibes cir cuit /syst em
behavior against r adiat ed or conduct ed int er fer ence.
The t hir d t ype of int er fer ence is internal . Alt hough not dir ect ly shown on t he figur e,
int er nal int er fer ence can be high-speed digit al cir cuit r y wit hin t he equipment which
affect s sensit ive analog (or ot her digit al cir cuit r y), or noisy power supplies which can
cont aminat e bot h analog and digit al cir cuit s. Int er nal int er fer ence oft en occur s
bet ween digit al and analog cir cuit s, or bet ween mot or s or r elays and digit al cir cuit s.
In mixed signal envir onment s, t he digit al por t ion of t he syst em oft en int er fer es wit h
analog cir cuit r y. In some syst ems, t he int er nal int er fer ence r eaches such high levels
t hat even ver y high-speed digit al cir cuit r y can affect ot her low-speed digit al cir cuit r y
as well as analog cir cuit s.
5
7
THREE TYPES OF INTERFERENCE
EMISSIONS - IMMUNITY - INTERNAL
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.50
In addit ion t o t he sour ce-pat h-r ecept or model for analyzing EMI-r elat ed pr oblems,
Kimmel Ger ke Associat es have also int r oduced t he FAT-ID concept [Refer ence 1].
FAT-ID is an acr onym t hat descr ibes t he five key element s inher ent in any EMI
pr oblem. These five key par amet er s ar e: frequency, amplitude, time, impedance, and
distance.
The frequency of t he offending signal suggest s it s pat h. For example, t he pat h of low-
fr equency int er fer ence is oft en t he cir cuit conduct or s. As t he int er fer ence fr equency
incr eases, it will t ake t he pat h of least impedance, usually st r ay capacit ance. In t his
case, t he coupling mechanism is r adiat ion.
Time and fr equency in EMI pr oblems ar e int er changeable. In fact , t he physics of
EMI have shows t hat t he t ime r esponse of signals cont ains all t he necessar y
infor mat ion t o const r uct t he spect r al r esponse of t he int er fer ence. In digit al syst ems,
bot h t he signal r ise t ime and pulse r epet it ion r at e pr oduce spect r al component s
accor ding t o t he following r elat ionship:
f
EMI
1
t
rise
·
⋅ π
Eq. 9.1
For example, a pulse having a 1ns r ise t ime is equivalent t o an EMI fr equency of
over 300MHz. This t ime-fr equency r elat ionship can also be applied t o high-speed
analog cir cuit s, wher e slew r at es in excess of 1000V/µs and gain-bandwidt h pr oduct s
gr eat er t han 500MHz ar e not uncommon.
When t his concept is applied t o inst r ument s and syst ems, EMI emissions ar e again
funct ions of signal r ise t ime and pulse r epet it ion r at es. Spect r um analyzer s and high
5
8
speed oscilloscopes used wit h volt age and cur r ent pr obes ar e ver y useful t ools in
quant ifying t he effect s of EMI on cir cuit s and syst ems.
Anot her impor t ant par amet er in t he analysis of EMI pr oblems is t he physical
dimensions of cables, wir es, and enclosur es. Cables can behave as eit her passive
ant ennas (r ecept or s) or ver y efficient t r ansmit t er s (sour ces) of int er fer ence. Their
physical lengt h and t heir shield must be car efully examined wher e EMI is a concer n.
As pr eviously ment ioned, t he behavior of simple conduct or s is a funct ion of lengt h,
cr oss-sect ional ar ea, and fr equency. Openings in equipment enclosur es can behave
as slot ant ennas, t her eby allowing EMI ener gy t o affect t he int er nal elect r onics.
Ra d i o Fr equ en cy I n t er fer en ce
The wor ld is r ich in r adio t r ansmit t er s: r adio and TV st at ions, mobile r adios,
comput er s, elect r ic mot or s, gar age door opener s, elect r ic jackhammer s, and
count less ot her s. All t his elect r ical act ivit y can affect cir cuit /syst em per for mance
and, in ext r eme cases, may r ender it inoper able. Regar dless of t he locat ion and
magnit ude of t he int er fer ence, cir cuit s/syst ems must have a minimum level of
immunit y t o r adio fr equency int er fer ence (RFI). The next sect ion will cover t wo
gener al means by which RFI can disr upt nor mal inst r ument oper at ion: t he dir ect
effect s of RFI sensit ive analog cir cuit s, and t he effect s of RFI on shielded cables.
Two t er ms ar e t ypically used in descr ibing t he sensit ivit y of an elect r onic syst em t o
RF fields. In communicat ions, r adio engineer s define immunity t o be an
inst r ument ’s susceptibility to the applied RFI power density at the unit. In mor e
gener al EMI analysis, t he electric-field intensity is used t o descr ibe RFI st imulus.
For compar at ive pur poses, Equat ion 9.2 can be used t o conver t elect r ic-field
int ensit y t o power densit y and vice-ver sa:
E
V
m
61.4 P
T
mW
cm
2
|
.

`
,

·
|
.

`
,

Eq. 9.2
wher e E = Elect r ic Field St r engt h, in volt s per met er , and
P
T
= Tr ansmit t ed power , in milliwat t s per cm^2.
5
9
Fr om t he st andpoint of t he sour ce-pat h-r ecept or model, t he strength of the electric
field, E, sur r ounding t he r ecept or is a funct ion of transmitted power, antenna gain,
and distance fr om t he sour ce of t he dist ur bance. An appr oximat ion for t he elect r ic-
field int ensit y (for bot h near - and far -field sour ces) in t hese t er ms is given by
Equat ion 9.3:
E
V
m
5.5
P
T |
.

`
,

·

|
.

`
,

G
A
d
Eq. 9.3
wher e E = Elect r ic field int ensit y, in V/m;
P
T
= Tr ansmit t ed power , in mW/cm^2;
G
A
= Ant enna gain (numer ical); and
d = dist ance fr om sour ce, in met er s
For example, a 1W hand-held r adio at a dist ance of 1 met er can gener at e an elect r ic-
field of 5.5V/m, wher eas a 10kW r adio t r ansmission st at ion locat ed 1km away
gener at es a field smaller t han 0.6V/m.
Analog cir cuit s ar e gener ally mor e sensit ive t o RF fields t han digit al cir cuit s because
analog cir cuit s, oper at ing at high gains, must be able t o r esolve signals in t he
micr ovolt /millivolt r egion. Digit al cir cuit s, on t he ot her hand, ar e mor e immune t o
RF fields because of t heir lar ger signal swings and noise mar gins. As shown in
Figur e 9.51, RF fields can use induct ive and/or capacit ive coupling pat hs t o gener at e
noise cur r ent s and volt ages which ar e amplified by high-impedance analog
inst r ument at ion. In many cases, out -of-band noise signals ar e det ect ed and r ect ified
by t hese cir cuit s. The r esult of t he RFI r ect ificat ion is usually unexplained offset
volt age shift s in t he cir cuit or in t he syst em.
6
0
RFI CAN CAUSE RECTIFICATION IN
SENSITIVE ANALOG CIRCUITS
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.51
Ther e ar e t echniques t hat can be used t o pr ot ect analog cir cuit s against int er fer ence
fr om RF fields (see Figur e 9.52). The t hr ee gener al point s of RFI coupling ar e signal
inputs, signal outputs, and power supplies. At a minimum, all power supply pin
connect ions on analog and digit al ICs should be decoupled wit h 0.1µF cer amic
capacit or s. As was shown in Refer ence 3, low-pass filt er s, whose cut off fr equencies
ar e set no higher t han 10 t o 100 t imes t he signal bandwidt h, can be used at t he
input s and t he out put s of signal condit ioning cir cuit r y t o filt er noise.
KEEPING RFI AWAY FROM ANALOG CIRCUITS
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.52
6
1
Car e must be t aken t o ensur e t hat t he low pass filt er s (LPFs) ar e effect ive at t he
highest RF int er fer ence fr equency expect ed. As illust r at ed in Figur e 9.53, r eal low-
pass filt er s may exhibit leakage at high fr equencies. Their induct or s can lose t heir
effect iveness due t o par asit ic capacit ance, and capacit or s can lose t heir effect iveness
due t o par asit ic induct ance. A r ule of t humb is t hat a convent ional low-pass filt er
(made up of a single capacit or and induct or ) can begin t o leak when t he applied
signal fr equency is 100 t o 1000 higher t han t he filt er ’s cut off fr equency. For
example, a 10kHz LPF would not be consider ed ver y efficient at filt er ing fr equencies
above 1MHz.
A SINGLE LOW PASS FILTER LOSES EFFECTIVENESS
AT 100 - 1000 f
3dB
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.53
Rat her t han use one LPF st age, it is r ecommended t hat t he int er fer ence fr equency
bands be separ at ed int o low-band, mid-band, and high-band, and t hen use
individual filt er s for each band. Kimmel Ger ke Associat es use t he st er eo speaker
analogy of woofer-midrange-tweeter for RFI low-pass filt er design illust r at ed in
Figur e 9.54. In t his appr oach, low fr equencies ar e gr ouped fr om 10kHz t o 1MHz,
mid-band fr equencies ar e gr ouped fr om 1MHz t o 100MHz, and high fr equencies
gr ouped fr om 100MHz t o 1GHz. In t he case of a shielded cable input /out put , t he
high fr equency sect ion should be locat ed close t o t he shield t o pr event high-
fr equency leakage at t he shield boundar y. This is commonly r efer r ed t o as feed-
through pr ot ect ion. For applicat ions wher e shields ar e not r equir ed at t he
input s/out put s, t hen t he pr efer r ed met hod is t o locat e t he high fr equency filt er
sect ion as close t he analog cir cuit as possible. This is t o pr event t he possibilit y of
pickup fr om ot her par t s of t he cir cuit .
6
2
MULTISTAGE FILTERS ARE MORE EFFECTIVE
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
STEREO SPEAKER ANALOGY
Figure 9.54
Anot her cause of filt er failur e is illust r at ed in Figur e 9.55. If t her e is any impedance
in t he gr ound connect ion (for example, a long wir e or nar r ow t r ace connect ed t o t he
gr ound plane), t hen t he high-fr equency noise uses t his impedance pat h t o bypass t he
filt er complet ely. Filt er gr ounds must be br oadband and t ied t o low-impedance
point s or planes for opt imum per for mance. High fr equency capacit or leads should be
kept as shor t as possible, and low-induct ance sur face-mount ed cer amic chip
capacit or s ar e pr efer able.
NON-ZERO (INDUCTIVE AND/OR RESISTIVE) FILTER
GROUND REDUCES EFFECTIVENESS
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.55
In t he fir st par t of t his discussion on RF immunit y, cir cuit level t echniques wer e
discussed. In t his next sect ion, t he second st r at egic concept for RF immunit y will be
discussed: all cables behave as antennas. As shown in Figur e 9.56, pigt ail
t er minat ions on cables ver y oft en cause syst ems t o fail r adiat ed emissions t est s
because high-fr equency noise has coupled int o t he cable shield, gener ally t hr ough
6
3
st r ay capacit ance. If t he lengt h of t he cable is consider ed electrically long (a concept
t o be explained lat er ) at t he int er fer ence fr equency, t hen it can behave as a ver y
efficient quar t er -wave ant enna. The cable pigt ail for ms a mat ching net wor k, as
shown in t he figur e, t o r adiat e t he noise which coupled int o t he shield. In gener al,
pigt ails ar e only r ecommended for applicat ions below 10kHz, such as 50/60Hz
int er fer ence pr ot ect ion. For applicat ions wher e t he int er fer ence is gr eat er t han
10kHz, shielded connect or s, elect r ically and physically connect ed t o t he chassis,
should be used. In applicat ions wher e shielding is not used, filt er s on input /out put
signal and power lines wor k well. Small fer r it es and capacit or s should be used t o
filt er high fr equencies, pr ovided t hat : (1) t he capacit or s have shor t leads and ar e t ied
dir ect ly t o t he chassis gr ound, and (2) t he filt er s ar e physically locat ed close t o t he
connect or s t o pr event noise pickup.
“SHIELDED” CABLE CAN CARRY HIGH FREQUENCY
CURRENT AND BEHAVES AS AN ANTENNA
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
I
CM
= COMMON-MODECURRENT
Figure 9.56
The key issues and t echniques descr ibed in t his sect ion on solving RFI r elat ed
pr oblems ar e summar ized in Figur e 9.57. Some of t he issues wer e not discussed in
det ail, but ar e equally impor t ant . For a complet e t r eat ment of t his issue, t he
int er est ed r eader should consult Refer ences 1 and 2. The main t hr ust of t his sect ion
was t o pr ovide t he r eader wit h a pr oblem-solving st r at egy against RFI and t o
illust r at e solut ions t o commonly encount er ed RFI pr oblems.
6
4
SUMMARY OF RADIO FREQUENCY INTERFERENCE
AND PROTECTION TECHNIQUES
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Radio-Frequency Interference is a Serious Threat
Equipment causes interference to nearby radio and
televison
Equipment upset by nearby transmitters
RF-Failure Modes
Digital circuits prime source of emissions
Analog circuits more vulnerable to RF than digital circuits
Two Strategic Concepts
Treat all cables as antennas
Determine the most critical circuits
RF Circuit Protection
Filters and multilayer boards
Multistage filters often needed
RF Shielding
Slots and seams cause the most problems
RF Cable Protection
High-quality shields and connectors needed for RF
protection
Figure 9.57
Solu t i on s for P ower -Li n e Di st u r ba n ces
The goal of t his next sect ion is not t o descr ibe in det ail all t he cir cuit /syst em failur e
mechanisms which can r esult fr om power -line dist ur bances or fault s. Nor is it t he
int ent of t his sect ion t o descr ibe met hods by which power -line dist ur bances can be
pr event ed. Inst ead, t his sect ion will descr ibe t echniques t hat allow cir cuit s and
syst ems t o accommodat e transient power -line dist ur bances.
Figur e 9.58 is an example of a hybr id power t r ansient pr ot ect ion net wor k commonly
used in many applicat ions wher e light ning t r ansient s or ot her power -line
dist ur bances ar e pr evalent . These net wor ks can be designed t o pr ovide pr ot ect ion
against t r ansient s as high as 10kV and as fast as 10ns. Gas dischar ge t ubes
(cr owbar s) and lar ge geomet r y zener diodes (clamps) ar e used t o pr ovide bot h
differ ent ial and common-mode pr ot ect ion. Met al-oxide var ist or s (MOVs) can be
subst it ut ed for t he zener diodes in less cr it ical, or in mor e compact designs. Chokes
ar e used t o limit t he sur ge cur r ent unt il t he gas dischar ge t ubes fir e.
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5
POWER LINE DISTURBANCES CAN GENERATE EMI
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.58
Commer cial EMI filt er s, as illust r at ed in Figur e 9.59, can be used t o filt er less
cat ast r ophic t r ansient s or high-fr equency int er fer ence. These EMI filt er s pr ovide
bot h common-mode and differ ent ial mode filt er ing as in Figur e 9.58. An opt ional
choke in t he safet y gr ound can pr ovide addit ional pr ot ect ion against common-mode
noise. The value of t his choke cannot be t oo lar ge, however , because it s r esist ance
may affect power -line fault clear ing.
SCHEMATIC FOR A COMMERCIAL POWER LINE FILTER
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.59
Tr ansfor mer s pr ovide t he best common-mode power line isolat ion. They pr ovide good
pr ot ect ion at low fr equencies (<1MHz), or for t r ansient s wit h r ise and fall t imes
gr eat er t han 300ns. Most mot or noise and light ning t r ansient s ar e in t his r ange, so
isolat ion t r ansfor mer s wor k well for t hese t ypes of dist ur bances. Alt hough t he
isolat ion bet ween input and out put is galvanic, isolat ion t r ansfor mer s do not pr ovide
sufficient pr ot ect ion against ext r emely fast t r ansient s (<10ns) or t hose caused by
high-amplit ude elect r ost at ic dischar ge (1 t o 3ns). As illust r at ed in Figur e 9.60,
isolat ion t r ansfor mer s can be designed for var ious levels of differ ent ial- or common-
mode pr ot ect ion. For differ ent ial-mode noise r eject ion, t he Far aday shield is
connect ed t o t he neut r al, and for common-mode noise r eject ion, t he shield is
connect ed t o t he safet y gr ound.
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6
FARADAY SHIELDS IN ISOLATION TRANSFORMERS
PROVIDE INCREASING LEVELS OF PROTECTION
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.60
P r i n t ed Ci r cu i t Boa r d Desi gn for EMI P r ot ect i on
This sect ion will summar ize gener al point s r egar ding t he most cr it ical por t ion of t he
design phase: t he pr int ed cir cuit boar d layout . It is at t his st age wher e t he
per for mance of t he syst em is most oft en compr omised. This is not only t r ue for
signal-pat h per for mance, but also for t he syst em’s suscept ibilit y t o elect r omagnet ic
int er fer ence and t he amount of elect r omagnet ic ener gy r adiat ed by t he syst em.
Failur e t o implement sound PCB layout t echniques will ver y likely lead t o
syst em/inst r ument EMC failur es.
Figur e 9.61 is a r eal-wor ld pr int ed cir cuit boar d layout which shows all t he pat hs
t hr ough which high-fr equency noise can couple/r adiat e int o/out of t he cir cuit .
Alt hough t he diagr am shows digit al cir cuit r y, t he same point s ar e applicable t o
pr ecision analog, high-speed analog, or mixed analog/digit al cir cuit s. Ident ifying
cr it ical cir cuit s and pat hs helps in designing t he PCB layout for bot h low emissions
and suscept ibilit y t o r adiat ed and conduct ed ext er nal and int er nal noise sour ces.
A key point in minimizing noise pr oblems in a design is t o choose devices no faster
than actually required by the application. Many designer s assume t hat fast er is
bet t er : fast logic is bet t er t han slow, high bandwidt h amplifier s ar e clear ly bet t er
t han low bandwidt h ones, and fast DACs and ADCs ar e bet t er , even if t he speed is
not r equir ed by t he syst em. Unfor t unat ely, fast er is not bet t er , but wor se wher e EMI
is concer ned.
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7
METHODS BY WHICH HIGH FREQUENCY ENERGY
COUPLES AND RADIATES INTO CIRCUITRY VIA PLACEMENT
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.61
Many fast DACs and ADCs have digit al input s and out put s wit h r ise and fall t imes
in t he nanosecond r egion. Because of t heir wide bandwidt h, t he sampling clock and
t he digit al input s and can r espond t o any for m of high fr equency noise, even glit ches
as nar r ow as 1 t o 3ns. These high speed dat a conver t er s and amplifier s ar e easy
pr ey for t he high fr equency noise of micr opr ocessor s, digit al signal pr ocessor s,
mot or s, swit ching r egulat or s, hand-held r adios, elect r ic jackhammer s, et c. Wit h
some of t hese high-speed devices, a small amount of input /out put filt er ing may be
r equir ed t o desensit ize t he cir cuit fr om it s EMI/RFI envir onment . Adding a small
fer r it e bead just befor e t he decoupling capacit or as shown in Figur e 9.62 is ver y
effect ive in filt er ing high fr equency noise on t he supply lines. For t hose cir cuit s t hat
r equir e bipolar supplies, t his t echnique should be applied t o bot h posit ive and
negat ive supply lines.
To help r educe t he emissions gener at ed by ext r emely fast moving digit al signals at
DAC input s or ADC out put s, a small r esist or or fer r it e bead may be r equir ed at each
digit al input /out put .
6
8
POWER SUPPLY FILTERING AND SIGNAL LINE
SNUBBING GREATLY REDUCES EMI EMISSIONS
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.62
Once t he syst em’s cr it ical pat hs and cir cuit s have been ident ified, t he next st ep in
implement ing sound PCB layout is t o par t it ion t he pr int ed cir cuit boar d accor ding t o
cir cuit funct ion. This involves t he appr opr iat e use of power , gr ound, and signal
planes. Good PCB layout s also isolat e cr it ical analog pat hs fr om sour ces of high
int er fer ence (I/O lines and connect or s, for example). High fr equency cir cuit s (analog
and digit al) should be separ at ed fr om low fr equency ones. Fur t her mor e, aut omat ic
signal r out ing CAD layout soft war e should be used wit h ext r eme caut ion, and
cr it ical pat hs r out ed by hand.
Pr oper ly designed mult ilayer pr int ed cir cuit boar ds can r educe EMI emissions and
incr ease immunit y t o RF fields by a fact or of 10 or mor e compar ed t o double-sided
boar ds. A mult ilayer boar d allows a complet e layer t o be used for t he gr ound plane,
wher eas t he gr ound plane side of a double-sided boar d is oft en disr upt ed wit h signal
cr ossover s, et c.
The pr efer r ed mult i-layer boar d ar r angement is t o embed t he signal t r aces bet ween
t he power and gr ound planes, as shown in Figur e 9.63. These low-impedance planes
for m ver y high-fr equency stripline t r ansmission lines wit h t he signal t r aces. The
r et ur n cur r ent pat h for a high fr equency signal on a t r ace is locat ed dir ect ly above
and below t he t r ace on t he gr ound/power planes. The high fr equency signal is t hus
cont ained inside t he PCB, t her eby minimizing emissions. The embedded signal t r ace
appr oach has an obvious disadvant age: debugging cir cuit t r aces t hat ar e hidden
fr om plain view is difficult .
6
9
“TO EMBED OR NOT TO EMBED”
THAT IS THE QUESTION
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.63
Much has been wr it t en about t er minat ing pr int ed cir cuit boar d t r aces in t heir
char act er ist ic impedance t o avoid r eflect ions. A good r ule-of-t humb t o det er mine
when t his is necessar y is as follows: Terminate the line in its characteristic
impedance when the one-way propagation delay of the PCB track is equal to or
greater than one-half the applied signal rise/ fall time (whichever edge is faster). A
conser vat ive appr oach is t o use a 2 inch (PCB t r ack lengt h)/nanosecond (r ise-, fall-
t ime) cr it er ion. For example, PCB t r acks for high-speed logic wit h r ise/fall t ime of
5ns should be t er minat ed in t heir char act er ist ic impedance and if t he t r ack lengt h is
equal t o or gr eat er t han 10 inches (including any meander s). The 2 inch/nanosecond
t r ack lengt h cr it er ion is summar ized in Figur e 9.64 for a number of logic families.
7
0
LINE TERMINATION SHOULD BE USED WHEN
LENGTH OF PCB TRACK EXCEEDS 2 inches / ns
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.64
This same 2 inch/nanosecond r ule of t humb should be used wit h analog cir cuit s in
det er mining t he need for t r ansmission line t echniques. For inst ance, if an amplifier
must out put a maximum fr equency of f
max
, t hen t he equivalent r iset ime, t
r
, can be
calculat ed using t he equat ion t
r
= 0.35/f
max
. The maximum PCB t r ack lengt h is
t hen calculat ed by mult iplying t he r iset ime by 2 inch/nanosecond. For example, a
maximum out put fr equency of 100MHz cor r esponds t o a r iset ime of 3.5ns, and a
t r ack car r ying t his signal gr eat er t han 7 inches should be t r eat ed as a t r ansmission
line.
Equat ion 9.4 can be used t o det er mine t he char act er ist ic impedance of a PCB t r ack
separ at ed fr om a power /gr ound plane by t he boar d’s dielect r ic (micr ost r ip
t r ansmission line):
( ) Z
o
r
+1.41
5.98d
0.89w + t
Ω ·

]
]
]
87
ε
ln Eq. 9.4
wher e e
r
= dielect r ic const ant of pr int ed cir cuit boar d mat er ial;
d = t hickness of t he boar d bet ween met al layer s, in mils;
w = widt h of met al t r ace, in mils; and
t = t hickness of met al t r ace, in mils.
The one-way t r ansit t ime for a single met al t r ace over a power /gr ound plane can be
det er mined fr om Eq. 9.5:
( ) t
pd
ns/ ft 1.017 0.475
r
0.67 · + ε Eq. 9.5
For example, a st andar d 4-layer PCB boar d might use 8-mil wide, 1 ounce (1.4 mils)
copper t r aces separ at ed by 0.021" FR-4 (e
r
=4.7) dielect r ic mat er ial. The
char act er ist ic impedance and one-way t r ansit t ime of such a signal t r ace would be
7
1
88ohms and 1.7ns/ft (7"/ns), r espect ively. Tr ansmission lines can be effect ively
t er minat ed in sever al ways depending on t he applicat ion, as descr ibed in Sect ion 2
of t his book.
Figur e 9.65 is a summar y of t echniques t hat should be applied t o pr int ed cir cuit
boar d layout s t o minimize t he effect s of elect r omagnet ic int er fer ence, bot h emissions
and immunit y.
CIRCUIT BOARD DESIGN AND EMI
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
“ALL EMI PROBLEMS BEGIN AND END AT A CURCUIT”
Identify critical, sensitive circuits

Where appropriate, choose ICs no faster than needed

Consider and implement sound PCB design

Spend time on the initial layout (by hand, if necessary)

Power supply decoupling (digital and analog circuits)

High-speed digital and high-accuracy analog don’t mix

Beware of connectors for input / output circuits

Test, evaluate, and correct early and often
Figure 9.65
A REVI EW OF SHI ELDI NG CONCEP TS
The concept s of shielding effect iveness pr esent ed next ar e backgr ound mat er ial.
Int er est ed r eader s should consult Refer ences 1,3, and 4 cit ed at t he end of t he
sect ion for mor e det ailed infor mat ion.
Applying t he concept s of shielding r equir es an under st anding of t he sour ce of t he
int er fer ence, t he envir onment sur r ounding t he sour ce, and t he dist ance bet ween t he
sour ce and point of obser vat ion (t he r ecept or or vict im). If t he cir cuit is oper at ing
close t o t he sour ce (in t he near -, or induct ion-field), t hen t he field char act er ist ics ar e
det er mined by t he sour ce. If t he cir cuit is r emot ely locat ed (in t he far -, or r adiat ion-
field), t hen t he field char act er ist ics ar e det er mined by t he t r ansmission medium.
A cir cuit oper at es in a near -field if it s dist ance fr om t he sour ce of t he int er fer ence is
less t han t he wavelengt h (lambda) of t he int er fer ence divided by 2pi, or lambda/2pi.
If t he dist ance bet ween t he cir cuit and t he sour ce of t he int er fer ence is lar ger t han
t his quant it y, t hen t he cir cuit oper at es in t he far field. For inst ance, t he int er fer ence
caused by a 1ns pulse edge has an upper bandwidt h of appr oximat ely 350MHz. The
wavelengt h of a 350MHz signal is appr oximat ely 32 inches (t he speed of light is
appr oximat ely 12"/ns). Dividing t he wavelengt h by 2pi yields a dist ance of
7
2
appr oximat ely 5 inches, t he boundar y bet ween near - and far -field. If a cir cuit is
wit hin 5 inches of a 350MHz int er fer ence sour ce, t hen t he cir cuit oper at es in t he
near -field of t he int er fer ence. If t he dist ance is gr eat er t han 5 inches, t he cir cuit
oper at es in t he far -field of t he int er fer ence.
Regar dless of t he t ype of int er fer ence, t her e is a char act er ist ic impedance associat ed
wit h it . The char act er ist ic, or wave impedance of a field is det er mined by t he r at io of
it s elect r ic (or E-) field t o it s magnet ic (or H-) field. In t he far field, t he r at io of t he
elect r ic field t o t he magnet ic field is t he char act er ist ic (wave impedance) of fr ee
space, given by Z
o
= 377ohms. In t he near field, t he wave-impedance is det er mined
by t he nat ur e of t he int er fer ence and it s dist ance fr om t he sour ce. If t he int er fer ence
sour ce is high-cur r ent and low-volt age (for example, a loop ant enna or a power -line
t r ansfor mer ), t he field is pr edominat ely magnet ic and exhibit s a wave impedance
which is less t han 377ohms. If t he sour ce is low-cur r ent and high-volt age (for
example, a r od ant enna or a high-speed digit al swit ching cir cuit ), t hen t he field is
pr edominat ely elect r ic and exhibit s a wave impedance which is gr eat er t han
377ohms.
Conduct ive enclosur es can be used t o shield sensit ive cir cuit s fr om t he effect s of
t hese ext er nal fields. These mat er ials pr esent an impedance mismat ch t o t he
incident int er fer ence because t he impedance of t he shield is lower t han t he wave
impedance of t he incident field. The effect iveness of t he conduct ive shield depends
on t wo t hings: Fir st is t he loss due t o t he reflection of t he incident wave off t he
shielding mat er ial. Second is t he loss due t o t he absorption of t he t r ansmit t ed wave
within t he shielding mat er ial. Bot h concept s ar e illust r at ed in Figur e 9.66. The
amount of r eflect ion loss depends upon t he t ype of int er fer ence and it s wave
impedance. The amount of absor pt ion loss, however , is independent of t he t ype of
int er fer ence. It is t he same for near - and far -field r adiat ion, as well as for elect r ic or
magnet ic fields.
REFLECTION AND ABSORPTION ARE THE TWO
PRINCIPAL SHIELDING MECHANISMS
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.66
7
3
Reflect ion loss at t he int er face bet ween t wo media depends on t he differ ence in t he
char act er ist ic impedances of t he t wo media. For elect r ic fields, r eflect ion loss
depends on t he fr equency of t he int er fer ence and t he shielding mat er ial. This loss
can be expr essed in dB, and is given by:
( ) R
e
dB = 322+ 10log
10
r
r
f
3
r
2
σ
µ

]
]
]
]
Eq. 9.6
wher e sigma r

= r elat ive conduct ivit y of t he shielding mat er ial, in Siemens per
met er ;
µ [sub] r = r elat ive per meabilit y of t he shielding mat er ial, in Henr ies per
met er ;
f = fr equency of t he int er fer ence, and
r = dist ance fr om sour ce of t he int er fer ence, in met er s
For magnet ic fields, t he loss depends also on t he shielding mat er ial and t he
fr equency of t he int er fer ence. Reflect ion loss for magnet ic fields is given by:
( ) R
m
dB = 14.6 +10log
10
f r
2
r
r
σ
µ

]
]
]
]
Eq. 9.7
and, for plane waves ( r > lambda/2pi), t he r eflect ion loss is given by:
( ) R
pw
dB =168 +10log
10
r
r
f
σ
µ

]
]
]
Eq. 9.8
Absorption is t he second loss mechanism in shielding mat er ials. Wave at t enuat ion
due t o absor pt ion is given by:
( ) A dB = 3.34 t
r r
f σ µ Eq. 9.9
wher e t = t hickness of t he shield mat er ial, in inches. This expr ession is valid for
plane waves, elect r ic and magnet ic fields. Since t he int ensit y of a t r ansmit t ed field
decr eases exponent ially r elat ive t o t he t hickness of t he shielding mat er ial, t he
absor pt ion loss in a shield one skin-dept h t hick is 9dB. Since absor pt ion loss is
pr opor t ional t o t hickness and inver sely pr opor t ional t o skin dept h, incr easing t he
t hickness of t he shielding mat er ial impr oves shielding effect iveness at high
fr equencies.
Reflect ion loss for plane waves in t he far field decr eases wit h incr easing fr equency
because t he shield impedance, Z
s
, incr eases wit h fr equency. Absor pt ion loss, on t he
ot her hand, incr eases wit h fr equency because skin dept h decr eases. For elect r ic
fields and plane waves, t he pr imar y shielding mechanism is r eflect ion loss, and at
high fr equencies, t he mechanism is absor pt ion loss. For t hese t ypes of int er fer ence,
high conduct ivit y mat er ials, such as copper or aluminum, pr ovide adequat e
7
4
shielding. At low fr equencies, bot h r eflect ion and absor pt ion loss t o magnet ic fields
is low; t hus, it is ver y difficult t o shield cir cuit s fr om low-fr equency magnet ic fields.
In t hese applicat ions, high-per meabilit y mat er ials t hat exhibit low-r eluct ance
pr ovide t he best pr ot ect ion. These low-r eluct ance mat er ials pr ovide a magnet ic
shunt pat h t hat diver t s t he magnet ic field away fr om t he pr ot ect ed cir cuit . Some
char act er ist ics of met allic mat er ials commonly used for shielded enclosur es ar e
shown in Table 9.2.
Impedance and Skin Depths for Various Shielding Materials
Ma t er i a l Con d u ct i vi t y
r
P er mea bi li t y
r
Sh i eld
I mp ed a n ce
| Z
s
|
Sk i n
d ep t h
(i n ch )
Cu 1 1
3.68E- 7 f ⋅

2.6
f

Al 1 0.61
4.71E-7 f ⋅

3.3
f

St eel 0.1 1000
3.68E- 5 f ⋅

0.26
f

µ Met al 0.03 20,000
3E -4 f ⋅

0.11
f

Table 9.2
wher e sigma 0 = 5.82 x 10^7 S/m
µo = 4pi x 10^-7 H/m
eo = 8.85 x 10^-12 F/m
A pr oper ly shielded enclosur e is ver y effect ive at pr event ing ext er nal int er fer ence
fr om disr upt ing it s cont ent s as well as confining any int er nally-gener at ed
int er fer ence. However , in t he r eal wor ld, openings in t he shield ar e oft en r equir ed t o
accommodat e adjust ment knobs, swit ches, connect or s, or t o pr ovide vent ilat ion (see
Figur e 9.67). Unfor t unat ely, t hese openings may compr omise shielding effect iveness
by pr oviding pat hs for high-fr equency int er fer ence t o ent er t he inst r ument .
7
5
ANY OPENING IN AN ENCLOSURE CAN ACT AS
AN EMI WAVEGUIDE BY COMPROMISING
SHIELDING EFFECTIVENESS
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.67
The longest dimension (not t he t ot al ar ea) of an opening is used t o evaluat e t he
abilit y of ext er nal fields t o ent er t he enclosur e, because t he openings behave as slot
ant ennas. Equat ion 9.10 can be used t o calculat e t he shielding effect iveness, or t he
suscept ibilit y t o EMI leakage or penet r at ion, of an opening in an enclosur e:
( ) Shielding Effectiven ess dB = 20log
10
2 L
λ

|
.

`
,

Eq. 9.10
wher e lambda = wavelengt h of t he int er fer ence and
L = maximum dimension of t he opening
Maximum r adiat ion of EMI t hr ough an opening occur s when t he longest dimension
of t he opening is equal t o one half-wavelengt h of t he int er fer ence fr equency (0dB
shielding effect iveness). A r ule-of-t humb is t o keep t he longest dimension less t han
1/20 wavelengt h of t he int er fer ence signal, as t his pr ovides 20dB shielding
effect iveness. Fur t her mor e, a few small openings on each side of an enclosur e is
pr efer r ed over many openings on one side. This is because t he openings on differ ent
sides r adiat e ener gy in differ ent dir ect ions, and as a r esult , shielding effect iveness is
not compr omised. If openings and seams cannot be avoided, t hen conduct ive gasket s,
scr eens, and paint s alone or in combinat ion should be used judiciously t o limit t he
longest dimension of any opening t o less t han 1/20 wavelengt h. Any cables, wir es,
connect or s, indicat or s, or cont r ol shaft s penet r at ing t he enclosur e should have
cir cumfer ent ial met allic shields physically bonded t o t he enclosur e at t he point of
ent r y. In t hose applicat ions wher e unshielded cables/wir es ar e used, t hen filt er s ar e
r ecommended at t he point of shield ent r y.
7
6
Gen er a l P oi n t s on Ca bles a n d Sh i eld s
Alt hough cover ed in mor e det ail lat er , t he impr oper use of cables and t heir shields is
a significant cont r ibut or t o bot h r adiat ed and conduct ed int er fer ence. Rat her t han
developing an ent ir e t r eat ise on t hese issues, t he int er est ed r eader should consult
Refer ences 1,2, 4, and 5. As illust r at ed in Figur e 9.68, effect ive cable and enclosur e
shielding confines sensit ive cir cuit r y and signals wit hin t he ent ir e shield wit hout
compr omising shielding effect iveness.
LENGTH OF SHIELDED CABLES DETERMINES AN
“ELECTRICALLY LONG” OR “ELECTRICALLY SHORT”
APPLICATION
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.68
Depending on t he t ype of int er fer ence (pickup/r adiat ed, low/high fr equency), pr oper
cable shielding is implement ed differ ent ly and is ver y dependent on t he lengt h of t he
cable. The fir st st ep is t o det er mine whet her t he lengt h of t he cable is electrically
short or electrically long at t he fr equency of concer n. A cable is consider ed
electrically short if t he lengt h of t he cable is less t han 1/20 wavelengt h of t he highest
fr equency of t he int er fer ence, ot her wise it is electrically long. For example, at
50/60Hz, an electrically short cable is any cable lengt h less t han 150 miles, wher e
t he pr imar y coupling mechanism for t hese low fr equency elect r ic fields is capacit ive.
As such, for any cable lengt h less t han 150 miles, t he amplit ude of t he int er fer ence
will be t he same over t he ent ir e lengt h of t he cable. To pr ot ect cir cuit s against low-
fr equency elect r ic-field pickup, only one end of t he shield should be r et ur ned t o a
low-impedance point . A gener alized example of t his mechanism is illust r at ed in
Figur e 9.69.
7
7
CONNECT THE SHIELD AT ONE POINT AT THE LOAD
TO PROTECT AGAINST LOW FREQUENCY (50/60Hz) THREATS
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Figure 9.69
In t his example, t he shield is gr ounded at t he r eceiver . An except ion t o t his
appr oach (which will be highlight ed again lat er ) is t he case wher e line-level
(>1Vr ms) audio signals ar e t r ansmit t ed over long dist ances using t wist ed pair ,
shielded cables. In t hese applicat ions, t he shield again offer s pr ot ect ion against low-
fr equency int er fer ence, and an accept ed appr oach is t o gr ound t he shield at t he
dr iver end (LF and HF gr ound) and gr ound it at t he r eceiver wit h a capacit or (HF
gr ound only).
In t hose applicat ions wher e t he lengt h of t he cable is electrically long, or pr ot ect ion
against high-fr equency int er fer ence is r equir ed, t hen t he pr efer r ed met hod is t o
connect t he cable shield t o low-impedance point s at bot h ends (dir ect connect ion at
t he dr iving end, and capacit ive connect ion at t he r eceiver ). Ot her wise, unt er minat ed
t r ansmission lines effect s can cause r eflect ions and st anding waves along t he cable.
At fr equencies of 10MHz and above, cir cumfer ent ial (360°) shield bonds and met al
connect or s ar e r equir ed t o main low-impedance connect ions t o gr ound.
In summar y, for pr ot ect ion against low-fr equency (<1MHz), elect r ic-field
int er fer ence, gr ounding t he shield at one end is accept able. For high-fr equency
int er fer ence (>1MHz), t he pr efer r ed met hod is gr ounding t he shield at bot h ends,
using 360° cir cumfer ent ial bonds bet ween t he shield and t he connect or , and
maint aining met al-t o-met al cont inuit y bet ween t he connect or s and t he enclosur e.
Low-fr equency gr ound loops can be eliminat ed by r eplacing one of t he DC shield
connect ions t o gr ound wit h a low induct ance 0.01µF capacit or . This capacit or
pr event s low fr equency gr ound loops and shunt s high fr equency int er fer ence t o
gr ound.
7
8
EMI TROUBLE SHOOTI NG P HI LOSOP HY
Syst em EMI pr oblems oft en occur aft er t he equipment has been designed and is
oper at ing in t he field. Mor e oft en t han not , t he or iginal designer of t he inst r ument
has r et ir ed and is living in Tahit i, so t he r esponsibilit y of r epair ing it belongs t o
someone else who may not be familiar wit h t he pr oduct . Figur e 9.70 summar izes t he
EMI pr oblem solving t echniques discussed in t his sect ion and should be useful in
t hese sit uat ions.
EMI TROUBLESHOOTING PHILOSOPHY
Reprinted from EDN Magazine (January 20, 1994), © CAHNERS PUBLISHING COMPANY 1995,
A Division of Reed Publishing USA
Diagnose before you fix

Ask yourself:
What are the symptoms?
What are the causes?
What are the constraints?
How will you know you have fixed it?
Use available models for EMI to identify source - path - victim

Start at low frequency and work up to high frequency

EMI doctor’s bag of tricks:
Aluminum foil
Conductive tape
Bulk ferrites
Power line ferrites
Signal filters
Resistors, capacitors, inductors, ferrites
Physical separation
Figure 9.70
7
9
REFERENCES ON EMI /RFI
1. EDN’s Designer’s Guide to Electromagnetic Compatibility, EDN,
J anuar y, 20, 1994, mat er ial r epr int ed by per mission of Cahner s Publishing
Company, 1995.
2. Designing for EMC (Workshop Notes), Kimmel Ger ke Associat es, Lt d., 1994.
3. Syst ems Ap p li ca t i on Gu i d e, Chapt er 1, pg. 21-55, Analog Devices,
Incor por at ed, Nor wood, MA, 1994.
4. Henr y Ot t , Noi se Red u ct i on Tech n i qu es I n Elect r on i c Syst ems,
Secon d Ed i t i on , New Yor k, J ohn Wiley & Sons, 1988.
5. Ralph Mor r ison, Gr ou n d i n g An d Sh i eld i n g Tech n i qu es I n
I n st r u men t a t i on , Th i r d Ed i t i on , New Yor k, J ohn Wiley & Sons, 1986.
6. Amp li fi er Ap p li ca t i on s Gu i d e, Chapt er XI, pg. 61, Analog Devices,
Incor por at ed, Nor wood, MA, 1992.
7. B.Slat t er y and J .Wynne, Design and Layout of a Video Graphics
S ystem for Reduced EMI , An a log Devi ces Ap p li ca t i on Not e AN-333.
8. Paul Br okaw, An IC Amplifier User Guide To Decoupling, Grounding,
And Making Things Go Right For A Change, An a log Devi ces
Ap p li ca t i on Not e, Or der Number E1393-5-590.
9. A. Rich, Understanding Interference-Type Noise, An a log Di a logu e, 16-3,
1982, pp. 16-19.
10. A. Rich, S hielding and Guarding, An a log Di a logu e, 17-1, 1983, pp. 8-13.
11. EMC Test & Desi gn , Car diff Publishing Company, Englewood, CO.
An excellent , gener al pur pose t r ade jour nal on issues of EMI and EMC.
8
0
SENSORS AND CABLE SHI ELDI NG
J oh n McDon a l d
The envir onment s in which analog syst ems oper at e ar e oft en r ich in sour ces of EMI.
Common EMI noise sour ces include power lines, logic signals, swit ching power
supplies, r adio st at ions, elect r ic light ing, and mot or s. Noise fr om t hese sour ces can
easily couple int o long analog signal pat hs, such as cables, which act as efficient
ant ennas. Shielded cables pr ot ect signal conduct or s fr om elect r ic field (E-field)
int er fer ence by pr oviding low impedance pat hs t o gr ound at t he offending
fr equencies. Aluminum foil, copper , and br aided st ainless st eel ar e mat er ials ver y
commonly used for cable shields due t o t heir low impedance pr oper t ies.
Simply incr easing t he separ at ion bet ween t he noise sour ce and t he cable will yield
significant addit ional at t enuat ion due t o r educed coupling, but shielding is st ill
r equir ed in most applicat ions involving r emot e sensor s.
PRECISION SENSORS AND CABLE SHIELDING
Figure 9.71
8
1
WHY SHIELD CABLES?
Figure 9.72
Ther e ar e t wo pat hs fr om an EMI sour ce t o a suscept ible cable: capacit ive (or E-
field) and magnet ic (or H-field) coupling (see Figur e 9.73). Capacit ive coupling
occur s when par asit ic capacit ance exist s bet ween a noise sour ce and t he cable. The
amount of par asit ic capacit ance is det er mined by t he separ at ion, shape, or ient at ion,
and t he medium bet ween t he sour ce and t he cable.
Magnet ic coupling occur s t hr ough par asit ic mut ual induct ance when a magnet ic
field is coupled fr om one conduct or t o anot her as shown in Figur e 9.73. Par asit ic
mut ual induct ance depends on t he shape and r elat ive or ient at ion of t he cir cuit s in
quest ion, t he magnet ic pr oper t ies of t he medium, and is dir ect ly pr opor t ional t o
conduct or loop ar ea. Minimizing conduct or loop ar ea r educes magnet ic coupling
pr opor t ionally.
Shielded twisted pair cables offer fur t her noise immunit y t o magnet ic fields.
Twist ing t he conduct or s t oget her r educes t he net loop ar ea, which has t he effect of
canceling any magnet ic field pickup, because t he sum of posit ive and negat ive
incr ement al loop ar eas is ideally equal t o zer o.
8
2
HOW DOES INTERFERENCE ENTER THE SYSTEM?
Figure 9.73
To st udy t he shielding pr oblem, a pr ecision RTD (Resistance Temperature Detector)
amplifier cir cuit was used as t he basis for a ser ies of exper iment s. A r emot e 100ohm
RTD was connect ed t o t he br idge, br idge dr iver , and t he br idge amplifier cir cuit
(Figur e 9.74) using 10 feet of a shielded t wist ed pair cable. The RTD is one element
of a 4-element br idge (t he t hr ee ot her r esist or element s ar e locat ed in t he br idge and
br idge dr iver cir cuit ). The gain of t he inst r ument at ion amplifier was adjust ed so
t hat t he sensit ivit y at t he out put was 10mV/°C, wit h a 5V full scale. Measur ement s
wer e made at t he out put of t he inst r ument at ion amplifier wit h t he shield gr ounded
in var ious ways. The exper iment s wer e conduct ed in lab st andar d envir onment
wher e a consider able amount of elect r onic equipment was in oper at ion.
The fir st exper iment was conduct ed wit h t he shield ungr ounded. As shown in Figur e
9.74, shields left float ing ar e not useful and offer no at t enuat ion t o EMI-induced
noise, in fact , t hey act as ant ennas. Capacit ive coupling is unaffect ed, because t he
float ing shield pr ovides a coupling pat h t o t he signal conduct or s. Most cables exhibit
par asit ic capacit ances bet ween 10-30pF/ft . Likewise, HF magnet ically coupled noise
is not at t enuat ed because t he float ing cable shield does not alt er eit her t he geomet r y
or t he magnet ic pr oper t ies of t he cable conduct or s. LF magnet ic noise is not
at t enuat ed significant ly, because most shield mat er ials absor b ver y lit t le magnet ic
ener gy.
8
3
UNGROUNDED SHIELDED CABLES ACT AS ANTENNAS
Figure 9.74
To implement effect ive EMI/RFI shielding, t he shield must be gr ounded. A gr ounded
shield r educes t he value of t he impedance of t he shield t o gr ound (Z in Figur e 9.73)
t o small values. Implement ing t his change will r educe t he amplit ude of t he E-Field
noise subst ant ially.
Designer s oft en gr ound bot h ends of a shield in an at t empt t o r educe shield
impedance and gain fur t her E-Field at t enuat ion. Unfor t unat ely, t his appr oach can
cr eat e a new set of pot ent ial pr oblems. The AC and DC gr ound pot ent ials ar e
gener ally differ ent at each end of t he shield. Figur e 9.75 illust r at es how low-
fr equency gr ound loop cur r ent is cr eat ed when bot h ends of a shield ar e gr ounded.
This low fr equency cur r ent flows t hr ough t he lar ge loop ar ea of t he shield and
couples int o t he cent er conduct or s t hr ough t he par asit ic mut ual induct ance. If t he
t wist ed pair s ar e pr ecisely balanced, t he induced volt age will appear as a common-
mode r at her t han a differ ent ial volt age. Unfor t unat ely, t he conduct or s may not be
per fect ly balanced, t he sensor and excit at ion cir cuit may not be fully balanced, and
t he common mode r eject ion at t he r eceiver may not be sufficient . Ther e will
t her efor e be some differ ent ial noise volt age developed bet ween t he conduct or s at t he
out put end, which is amplified and appear s at t he final out put of t he
inst r ument at ion amplifier . Wit h t he shields of t he exper iment al cir cuit gr ounded at
bot h ends, t he r esult s ar e shown in Figur e 9.76.
8
4
SIGNAL GROUND AND EARTH GROUND HAVE DIFFERENT
POTENTIALS WHICH MAY INDUCE GROUND LOOP CURRENT
Figure 9.75
GROUNDING BOTH ENDS OF A SHIELD PRODUCES
LOW FREQUENCY GROUND LOOPS
Figure 9.76
Figur e 9.77 illust r at es a pr oper ly gr ounded syst em wit h good elect r ic field shielding.
Not ice t hat t he gr ound loop has been eliminat ed. The shield has a single point
gr ound, locat ed at t he signal condit ioning cir cuit r y, and noise coupled int o t he shield
is effect ively shunt ed int o t he r eceiver gr ound and does not appear at t he out put of
t he inst r ument at ion amplifier .
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5
GROUNDING SHIELD AT RECEIVER END SHUNTS LOW- AND
HIGH-FREQUENCY NOISE INTO RECEIVER GROUND
Figure 9.77
Figur e 9.78 shows an example of a r emot ely locat ed, ungr ounded, passive sensor
(EEG elect r odes) which is connect ed t o a high-gain, low power AD620
inst r ument at ion amplifier t hr ough a shielded t wist ed pair cable. Not e t hat t he
shield is pr oper ly gr ounded at t he signal condit ioning cir cuit r y. The AD620 gain is
1000× , and t he amplifier is oper at ed on ±3V supplies. Not ice t he absence of 60Hz
int er fer ence in t he amplifier out put .
8
6
FOR UNGROUNDED PASSIVE SENSORS,
GROUND SHIELD AT THE RECEIVING END
Figure 9.78
Most high impedance sensor s gener at e low-level cur r ent or volt age out put s, such as
a phot odiode r esponding t o incident light . These low-level signals ar e especially
suscept ible t o EMI, and oft en ar e of t he same or der of magnit ude as t he par asit ic
par amet er s of t he cable and input amplifier .
Even pr oper ly shielded cables can degr ade t he signals by int r oducing par asit ic
capacit ance t hat limit s bandwidt h, and leakage cur r ent s t hat limit sensit ivit y. An
example is shown in Figur e 9.79, wher e a high-impedance phot odiode is connect ed t o
a pr eamp t hr ough a long shielded t wist ed pair cable. Not only will t he cable
capacit ance limit bandwidt h, but cable leakage cur r ent limit s sensit ivit y. A pr e-
amplifier , locat ed close t o t he high-impedance sensor , is r ecommended t o amplify t he
signal and t o minimize t he effect of cable par asit ics.
SHIELDS ARE NOT EFFECTIVE WITH
HIGH IMPEDANCE REMOTE SENSORS
Figure 9.79
8
7
Figur e 9.80 is an example of a high-impedance phot odiode det ect or and pr e-
amplifier , dr iving a shielded t wist ed pair cable. Bot h t he amplifier and t he shield
ar e gr ounded at a r emot e locat ion. The shield is connect ed t o t he cable dr iver
common, G1, ensur ing t hat t he signal and t he shield at t he dr iving end ar e bot h
r efer enced t o t he same point . The capacit or on t he r eceiving side of t he cable shunt s
high fr equency noise on t he shield int o gr ound G2 wit hout int r oducing a low-
fr equency gr ound loop. This popular gr ounding scheme is known as hybrid
gr ounding.
REMOTELY LOCATED HIGH IMPEDANCE
SENSOR WITH PREAMP
Figure 9.80
Figur e 9.81 illust r at es a balanced act ive line dr iver wit h a hybr id shield gr ound
implement at ion. When a syst em’s oper at ion calls for a wide fr equency r ange, t he
hybr id gr ounding t echnique oft en pr ovides t he best choice (Refer ence 8). The
capacit or at t he r eceiving end shunt s high-fr equency noise on t he shield int o G2
wit hout int r oducing a low-fr equency gr ound loop. At t he r eceiver , a common-mode
choke can be used t o help pr event RF pickup ent er ing t he r eceiver , and subsequent
RFI r ect ificat ion (see Refer ences 9 and 10). Car e should be t aken t hat t he shields ar e
gr ounded t o t he chassis ent r y point s t o pr event cont aminat ion of t he signal gr ound
(Refer ence 11).
8
8
HYBRID (LF AND HF) GROUNDING WITH ACTIVE DRIVER
Figure 9.81
To summar ize t his discussion, shield gr ounding t echniques must t ake int o account
t he t ype and t he configur at ion of t he sensor as well as t he nat ur e of t he int er fer ence.
When a low-impedance passive sensor is used, gr ounding t he shield t o t he r eceiving
end is t he best choice. Act ive sensor shields should gener ally be gr ounded at t he
sour ce (dir ect connect ion t o sour ce gr ound) and at t he r eceiver (connect t o r eceiver
gr ound using a capacit or ). This hybr id appr oach minimizes high-fr equency
int er fer ence and pr event s low-fr equency gr ound loops. Shielded t wist ed conduct or s
offer addit ional pr ot ect ion against shield noise because t he coupled noise occur s as a
common-mode, and not a differ ent ial signal.
The best shield can be compr omised by poor connect ion t echniques. Shields oft en use
“pig-t ail” connect ions t o make t he connect ion t o gr ound. A “pig-t ail” connect ion is a
single wir e connect ion fr om shield t o eit her chassis or cir cuit gr ound. This t ype of
connect ion is inexpensive, but at high fr equency, it does not pr ovide low impedance.
Qualit y shields do not leave lar ge gaps in t he cable/inst r ument shielding syst em.
Shield gaps pr ovide pat hs for high fr equency EMI t o ent er t he syst em. The cable
shielding syst em should include t he cable end connect or s. Ideally, cable shield
connect or s should make 360° cont act wit h t he chassis gr ound.
This sect ion has highlight ed t he mor e common t echniques used in cable shielding.
Ther e ar e ot her t echniques which involve t he use of dr iven shields, t win-shields,
common-mode chokes, et c. Refer ences 1, 2, 5, 6, 7, and 8 pr ovide an exhaust ive st udy
of t he ent ir e t opic of noise r educt ion t echniques including cable shielding.
8
9
SUMMARY OF CABLE SHIELDING TECHNIQUES
Do not let the shield “float”
Do not connect both ends of directly to ground
No LF current should flow in the shield
Use the hybrid approach for LF and HF electric field interference
The shield includes the connector, therefore avoid using pigtails
to connect shields to ground. Use chassis ground to prevent
signal ground contamination
Use Common-Mode chokes at receiver to enhance RF rejection
Other techniques exist:
Driven Shields
Twin-Shields
Figure 9.82
9
0
REFERENCES: SENSORS AND CABLE SHI ELDI NG
1. H.W. Ot t , Noi se Red u ct i on Tech n i qu es i n Elect r on i c Syst ems,
Secon d Ed i t i on , J ohn Wiley & Sons, Inc., New Yor k, 1988.
2. Ralph Mor r ison, Gr ou n d i n g a n d Sh i eld i n g Tech n i qu es i n
I n st r u men t a t i on , Th i r d Ed i t i on , J ohn Wiley & Sons, Inc.,
New Yor k, 1988.
3. Syst ems Ap p li ca t i on Gu i d e, Sect ion 1, Analog Devices, Inc.,
Nor wood, MA, 1993.
4. AD620 Inst r ument at ion Amplifier , Dat a Sheet , Analog Devices, Inc.
5. A. Rich, Understanding Interference-Type Noise, An a log Di a logu e,
16-3, 1982, pp. 16-19.
6. A. Rich, S hielding and Guarding, An a log Di a logu e, 17-1, 1983,
pp. 8-13.
7. EDN’s Designer’s Guide to Electromagnetic Compatibility, EDN,
J anuar y, 20, 1994, mat er ial r epr int ed by per mission of Cahner s
Publishing Company, 1995.
8. Designing for EMC (Workshop Notes), Kimmel Ger ke Associat es,
Lt d., 1994.
9. J ames Br yant and Her man Gelbach, High Frequency S ignal
Contamination, An a log Di a logu e, Vol. 27-2, 1993.
10. Walt J ung, S ystem RF Interference Prevention, An a log Di a logu e,
Vol. 28-2, 1994.
11. Neil Muncy, Noise S usceptibility in Analog and Digital S ignal
Processing S ystems, pr esent ed at 97t h Au d i o En gi n eer i n g Soci et y
Con ven t i on , Nov. 1994.
9
1
GENERAL REFERENCES: HARDWARE
DESI GN TECHNI QUES
1. Li n ea r Desi gn Semi n a r , Sect ion 11, Analog Devices, Inc., 1995.
2. E.S.D. P r even t i on Ma n u a l
Available fr ee fr om Analog Devices, Inc.
3. B.I. & B. Bleaney, Elect r i ci t y & Ma gn et i sm, OUP 1957, pp 23,24, & 52.
4. Paul Br okaw, An I.C. Amplifier User's Guide to Decoupling, Grounding
and Making Things Go Right for a Change, An a log Devi ces Ap p li ca t i on
Not e, Available fr ee of char ge fr om Analog Devices, Inc.
5. J eff Bar r ow, Avoiding Ground Problems in High S peed Circuits,
R.F. Desi gn , J uly 1989.
AND
Paul Br okaw & J eff Bar r ow, Grounding for Low- and High-Frequency
Circuits, An a log Di a logu e, 23-3 1989.
Fr ee fr om Analog Devices.
6. Int er nat ional EMI Emission Regulat ions
Canada CSA C108.8-M1983 FDR VDE 0871/VDE 0875
J apan CISPR (VCCI)/PUB 22 USA FCC-15 Par t J
7. Bill Slat t er y & J ohn Wynne, Design & Layout of a Video Graphics S ystem
for Reduced EMI, Analog Devices Applicat ion Not e (E1309-15-10/89)
Fr ee fr om Analog Devices.
8. William R. Blood, J r ., MECL Syst em Desi gn Ha n d book
(HB205, Rev. 1), Mot or ola Semiconduct or Pr oduct s, Inc., 1988.
9. Wainwr ight Inst r ument s Inc., 7770 Regent s Rd., #113, Suit e 371,
San Diego, CA 92122, Tel. 619-558-1057, Fax. 619-558-1019.
Wainwr ight Inst r ument s GmbH, Widder sber ger St r asse 14,
DW-8138 Andechs-Fr ieding, Ger many. Tel: +49-8152-3162,
Fax: +49-8152-40525.
10. Ralph Mor r ison, Gr ou n d i n g a n d Sh i eld i n g Tech n i qu es i n
I n st r u men t a t i on , Th i r d Ed i t i on , J ohn Wiley, Inc., 1986.
11. Henr y W. Ot t , Noi se Red u ct i on Tech n i qu es i n Elect r on i c Syst ems,
Secon d Ed i t i on , J ohn Wiley, Inc., 1988.
9
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12. Rober t A. Pease, Tr ou blesh oot i n g An a log Ci r cu i t s, But t er wor t h-
Heinemann, 1991.
13. J im Williams, Edit or , An a log Ci r cu i t Desi gn : Ar t , Sci en ce, a n d
P er son a li t i es, But t er wor t h-Heinemann, 1991.
14. Doug Gr ant and Scot t Wur cer , Avoiding Passive Component Pitfalls,
Th e Best of An a log Di a logu e, pp. 143-148, Analog Devices, Inc., 1991.
15. Walt J ung and Richar d Mar sh, Picking Capacitors, Part I., Au d i o,
Febr uar y, 1980.
16. Walt J ung and Richar d Mar sh, Picking Capacitors, Part II., Au d i o,
Mar ch, 1980.
17. Dar yl Ger ke and Bill Kimmel, The Designer's Guide to Electromagnetic
Compatibility, EDN Su p p lemen t , J anuar y 20, 1994.
18. Walt Kest er , Basic Characteristics Distinguish S ampling A/ D Converters ,
EDN, Sept ember 3, 1992, pp.135-144.
19. Walt Kest er , Peripheral Circuits Can Make or Break S ampling ADC
S ystem, EDN, Oct ober 1, 1992, pp. 97-105.
20. Walt Kest er , Layout, Grounding, and Filtering Complete S ampling
ADC S ystem, EDN, Oct ober 15, 1992, pp. 127-134.

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