CALIFORNIA MICRO DEVICES

CM8870/70C

CMOS Integrated DTMF Receiver
Features
• Full DTMF receiver • Less than 35mW power consumption • Industrial temperature range • Uses quartz crystal or ceramic resonators • Adjustable acquisition and release times • 18-pin DIP, 18-pin DIP EIAJ, 18-pin SOIC, 20-pin PLCC • CM8870C — — — Power down mode Inhibit mode Buffered OSC3 output (PLCC package only)

Applications
• PABX • Central office • Mobile radio • Remote control • Remote data entry • Call limiting • Telephone answering systems • Paging systems

• CM8870C is fully compatible with CM8870 for 18-pin devices by grounding pins 5 and 6

Product Description
The CAMD CM8870/70C provides full DTMF receiver capability by integrating both the bandsplit filter and digital decoder functions into a single 18-pin DIP, SOIC, or 20-pin PLCC package. The CM8870/70C is manufactured using state-of-the-art CMOS process technology for low power consumption (35mW, max.) and precise data handling. The filter section uses a switched capacitor technique for both high and low group filters and dial tone rejection. The CM8870/70C decoder uses digital counting techniques for the detection and decoding of all 16 DTMF tone pairs into a 4-bit code. This DTMF receiver minimizes external component count by providing an on-chip differential input amplifier, clock generator, and a latched three-state interface bus. The on-chip clock generator requires only a low cost TV crystal or ceramic resonator as an external component.

© 2000 California Micro Devices Corp. All rights reserved. 9/28/2000

+##' Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com

215 Topaz Street, Milpitas, California 95035

1

VDD=5. DC Characteristics: All voltages referenced to VSS. All rights reserved.0V Max VSS-0.0V @ 1K H z VDD = 5.0 10 0 50 2.0V.3V 10mA Max -40°C to +85°C -65°C to +150°C CM8870/70C This device contains input protection against damage due to high static voltages or electric fields. Milpitas.CALIFORNIA MICRO DEVICES Absolute Maximum Ratings: (Note 1) ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage (VDDV SS) Voltage on any Pin Current on any Pin Operating Temperature Storage Temperature Symbol VDD Vdc ID D TA TS Value 6.0V VDD=5.com 9/28/2000 . functional operation under these conditions is not implied.7 8 2.0V ± 5%.97 1.1 6.4 10 2.0V VIN = VSS = VDD (Note 1) TOE=0V.5 Units V mA µA mW V V µA µA MΩ V V V mA mA V ΚΩ PD =VDD f=3. VDD=5.0V ± 5%. TA = -40°C to +85°C unless otherwise noted. No Load Test Conditions VREF Operating Characteristics: All voltages referenced to VSS.4V VOUT = 4.8 2.0V.0 Max 5. IN-) Steering Threshold Voltage Low Level Output Voltage High Level Output Voltage Output Low (Sink) Current Output High (Source) Current Output Voltage Output Resistance DC CHARACTE RISTICS Symbol Min Typ V DD I DD I DDQ PO V IL V IH I I H/ L I L I so R IN V Tst V OL V OH I OL I OH V R EF R OR 4. Parameter Operating Supply Voltage Operating Supply Current Standby Supply Current Power Consumption Low Level Input Voltage High Level Input Voltage Input Leakage Current Pull Up (Source) Current on TOE Input Impedance.5 0. VDD = 5.calmicro. Symbol IIN R IN V OS PSRR CMR R A V OL fc VO CL RL Vcm Min 10 Typ Max ±100 ±25 Units nA MΩ mV dB dB dB MHz VP-P Test Conditions V S S < V IN < V D D 50 40 32 0. No Load VDD = 5.0V.5 1KHz (Note 12) -3.0V < VIN < 3.0 25 35 1.2 3.3V to VDD+0. precautions should be taken to avoid application of voltages higher than the maximum rating. Notes: 1.25 7.4 2. No Load VOUT = 0.3 4. (IN+. Exceeding these ratings may cause permanent damage. California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www. VDD = 5.03 20 15 4.0 0.0V VDD = 5.0V VDD=5. Gain Setting Amplifier OPERATING CHARACTERISTICS Parameter Input Leakage Current Input Resistance Input Offset Voltage Power Supply Rejection Common Mode Rejection D C Open Loop Voltage Gain Open Loop Unity Gain Bandwidth Output Voltage Swing Maximum Capacitive Load (GS) Maximum Resistive Load (GS) Common Mode Range (No Load) ©2000 California Micro Devices Corp. however.5 0. TA = -40°C to +85°C unless otherwise noted.0V RL ≥ 100KW to VSS pF KΩ VP-P N o L o ad 2 215 Topaz Street.579 MHz.75 3.6V VDD = 5.5 0.5 10 2.

Bandwidth limited (0 to 3 KHz) Gaussian Noise. 7.8 2. and TOE.5.9 2.3. Minimum signal acceptance level is measured with specified maximum frequency deviation.4. Interdigit Pause Reject Propagation D elay (St to Q) Propagation D elay (St to StD ) Output D ata Set Up (Q to StD ) Propagation D elay (TOE to Q) Crystal/Clock Frequency Clock Output (OSC 2) Capacitive L o ad Enable D isable t DP t DA t R EC t R EC t ID t DO t PQ t PSt D t QSt D t PTE t PTD f CL K C LO 3.4. All rights reserved. Tone pause = 40 mS.3. 1) unless otherwise noted.14 2. fCLK=3. TA=-40°C to +85°C.8.calmicro. dBm = decibels above or below a reference power of 1 mW into a 600 ohm load.3. 13. 5.5 ±3. IN-. 8. D eviation Reject Limit Third Tone Tolerance Noise Tolerance D ial Tone Tolerance Tone Present D etection Time Tone Absent D etection Time Min Tone D uration Accept Max Tone D uration Reject Min. © 2000 California Micro Devices Corp.5. 14.6.8. The precise dial tone frequencies are (350 Hz and 440 Hz) ±2%.579545 MHz using test circuit (Fig.10 2. 3.3. AC CHARACTERISTICS Parameter Valid Input Signal Levels (each tone of composite signal) Positive Twist Accept Negative Twist Accept Freq. 1) TOE = VDD R L = 10 K Ω CL = 50pF Notes: 1.5 Typ Max +1 869 10 10 1. 12.5% -16 -12 +22 8 3 14 8.4 50 300 3. VDD=5. dB dB dB mS mS mS mS mS µS µS µS µS nS nS MHz pF Notes 1. 2. Nominal DTMF frequencies are used.CALIFORNIA MICRO DEVICES CM8870/70C AC Characteristics: All voltages referenced to VSS.3.5.2.8. Input pins defined as IN+.5%±2Hz Units dBm mVRMS dB dB Nom.5831 30 11 16 20 40 5 0. Digit sequence consists of all 16 DTMF tones. External voltage source used to bias VREF. 4. Input DTMF tone level at -28 dBm.5 40 Symbol Min -29 27.com 3 .7.4. Referenced to lowest level frequency component in DTMF signal. Interdigit Pause Accept Max.4. Nom.13.8. Referenced to Figure 1.9 Refer to Timing D iagram (User Adjustable) Times shown are obtained with circuit in Fig.5. 6.4. D eviation Accept Limit Freq. For an error rate of better than 1 in 10. This parameter also applies to a third tone injected onto the power supply.0V ±5%.3. 9/28/2000 215 Topaz Street. Milpitas. 11. Tone duration = 40mS.5759 20 6 9 3.5.9.3. California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www. Both tones in the composite signal have an equal amplitude. 10.000 9.5 2.5795 3.8 2.

tDO Maximum allowable drop-out during valid DTMF signal. tDA Time to detect the absence of valid DTMF signals.calmicro. tGTA Guard time. outputs not updated. StD Delayed Steering Output. Drives external RC timing circuit.CALIFORNIA MICRO DEVICES CM8870/70C Explanation of Events A) Tone bursts detected. tREC Maximum DTMF signal duration not detected as valid. outputs remain latched until next valid tone. ©2000 California Micro Devices Corp. 4 215 Topaz Street. D) Outputs switched to high impedance state. tGTP Guard time. A low level shifts Q1-Q4 to its high impedance state. tone decoded and latched in outputs (currently high impedance). tone decoded and latched in outputs. thus constituting a valid signal. Indicates that valid frequencies have been present/absent for the required guard time. All rights reserved. F) Acceptable dropout of tone #n + 1. B) Tone #n detected. tREC Minimum DTMF signal duration required for valid recognition. tone present. California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www. G) End of tone #n + 1 detected. tone duration invalid. Indicates detection of valid tone frequencies. Explanation of Symbols VIN ESt St/GT DTMF composite input signal. outputs remain latched until next valid tone. tID Minimum time between valid DTMF signals. C) End of tone #n detected. outputs remain latched. tone absent duration valid. tone duration valid. tone absent.com 9/28/2000 . TOE Tone Output Enable (input). Milpitas. Early Steering Output. E) Tone #n + 1 detected. Steering input/guard time output. tone absent duration valid. tDP Time to detect the presence of valid DTMF signals. tone absent duration invalid. tone duration valid. Q1-Q4 4-bit decoded tone output.

On the other hand. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop-outs would be requirements. The filter section also incorporates notches at 350 Hz and 440 Hz which provides excellent dial tone rejection. the receiver will tolerate signal interruptions (drop outs) too short to be © 2000 California Micro Devices Corp. The bandwidths of these filters correspond to the bands enclosing the low-group and high-group tones (See Figure 3). Figure 6 shows the differential configuration. Multiple CM8870/70Cs can be connected as shown in figure 8 such that only one crystal or resonator is required.67 RC The value of tDP is a parameter of the device and tREC is the minimum signal duration to be recognized by the receiver. as well as rejecting signals too short to be considered valid. Any subsequent loss of signal condition will cause ESt to fall. This check is performed by an external RC time constant driven by ESt. VC reaches the threshold (VTSt) of the steering logic to register the tone pair. A complex averaging algorithm is used to protect against tone simulation by extraneous signals (such as voice) while providing tolerance to small frequency variations. A logic high on ESt causes VC (See Figure 4) to rise as the capacitor discharges. The steering circuit works in reverse to validate the interdigit pause between signals.579545 MHz. but high performance in a small 18-pin DIP. At this point. leaving R to be selected by the designer. the input pins are connected as shown in Figure 1. followed by a digital decode (counting) section which verifies both the frequency and duration of the received tones before passing the resultant 4-bit code to the output bus. it raises the “Early Steering” flag (ESt). Increasing tREC improves talk-off performance. GT continues to drive high as long as ESt remains high. Thus. The averaging algorithm has been developed to ensure an optimum combination of immunity to “talk-off” and tolerance to the presence of interfering signals (third tones) and noise. The CM8870C in a PLCC package has a buffered oscillator output (OSC3) that can be used to drive clock inputs of other devices such as a microprocessor or other CM887X’s as shown in Figure 7. Design information for guard time adjustment is shown in Figure 5. Filter Section Separation of the low-group and high-group tones is achieved by applying the dual-tone signal to the inputs of two 9th-order switched capacitor bandpass filters. A typical circuit using this steering configuration is shown in Figure 1. For example.CALIFORNIA MICRO DEVICES Functional Description The CAMD CM8870/70C DTMF Integrated Receiver provides the design engineer with not only low power consumption. The CM8870/70C’s internal architecture consists of a bandsplit filter section which separates the high and low tones of the received pair. The contents of the output latch are made available on the 4-bit output bus by raising the three-state control input (TOE) to a logic high. When the detector recognizes the simultaneous presence of two valid tones (known as “signal condition”). with the op-amp connected for unity gain and VREF biasing the input at ½ VDD. California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www. All rights reserved.1 uF is recommended for most applications. Steering Circuit Before the registration of a decoded tone pair. Milpitas. Component values are chosen according to the following formula: tREC = tDP + tGTP tGTP » 0. These comparators are provided with a hysteresis to prevent detection of unwanted low-level signals and noise. a suitable value of R for a tREC of 40 milliseconds would be 300K. In a single-ended configuration. the receiver checks for a valid signal duration (referred to as “characterrecognition-condition”). Each filter output is followed by a single order switched capacitor section which smooths the signals prior to limiting. SOIC. CM8870/70C considered a valid pause. the simple steering circuit of Figure 4 is applicable. Input Configuration The input arrangement of the CM8870/70C provides a differential input operational amplifier as well as a bias source (VREF) which is used to bias the inputs at mid-rail. Guard Time Adjustment In situations which do not require independent selection of receive and pause. Different steering arrangements may be used to select independently the guardtimes for tone-present (tGTP) and tone absent (tGTA). The timing requirements for most telecommunication applications are satisfied with this circuit. 9/28/2000 Clock Circuit The internal clock circuit is completed with the addition of a standard television color burst crystal or ceramic resonator having a resonant frequency of 3. Signal limiting is performed by highgain comparators. 215 Topaz Street. This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigit pause. thus latching its corresponding 4-bit code (See Figure 2) into the output latch. allows the designer to tailor performance to meet a wide variety of system requirements. Decoder Section The CM8870/70C decoder uses a digital counting technique to determine the frequencies of the limited tones and to verify that these tones correspond to standard DTMF frequencies. or 20-pin PLCC package configuration. Guard time adjustment also allows the designer to tailor system parameters such as talk-off and noise immunity. which permits the adjustment of gain with the feedback resistor R5. signaling that a received tone pair has been registered. The outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones.com 5 . since it reduces the probability that tones simulated by speech will maintain signal condition for long enough to be registered. A value for C of 0. the GT output is activated and drives VC to VDD.calmicro. This capability together with the capability of selecting the steering time constants externally. Providing signal condition is maintained (ESt remains high) for the validation period (tGTP).

CALIFORNIA MICRO DEVICES Pin Function Table PIN FUNCTION CM8870/70C N am e IN + IN GS VREF IN H OSC3 PD OSC1 OSC2 V SS TOE Q1 Q2 Q3 Q4 StD ESt St/Gt VDD IC Non-inverting Input I n v e rti n g I n p u t Gain Select D escription Connection to the front-end differential amplifier Gives access to output of front-end differential amplifier for connection of feedback resistor. 2) Positive power supply. Steering input/guard time output (bidirectional). Negative power supply (normally connected to OV). (See Fig. A voltage greater than VTSt detected a St causes the device to register the detected tone pair . 2). Power D own Clock Input Clock Output Logic high powers down the device and inhibits the oscillator. 6 215 Topaz Street. B. H = Logic High. R e f e r e n c e v o l ta g e o u tp u t ( n o mi n a l l y V D D /2 ) . The GT output acts to reset the external steering time constant.com 9/28/2000 .calmicro. and D D igital buffered oscillator output. Presents a logic high when a received tone pair has been registered and the output latch is updated. T h r e e -s t a t e o u t p u t e n a b l e ( i n p u t ) . Any momentary loss of signal condition will cause ESt to return to a logic low. L o g i c h i g h e n a b l e s t h e o u t p u t s Q1 -Q4 . D elayed steering output. 1477 3 H 0 12 0 9 4 H 0 13 3 6 5 H 0 147 7 6 H 0 12 0 9 7 H 0 13 3 6 8 H 1 147 7 9 H 1 12 0 9 0 H 1 13 3 6 · H 1 147 7 # H 1 16 3 3 A H 1 16 3 3 B H 1 16 3 3 C H 1 16 3 3 D H 0 ANY L Z L = logic Low. Z = High Figure 2. California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www. 3. Early steering output. All rights reserved. Functional Diode Table 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 Z Z Impedance Figure 1. Must be tied to VSS (for 8870 configuration only) FLOW 697 697 697 770 770 770 8 52 8 52 8 52 9 41 9 41 9 41 697 770 8 52 9 41 - F H IGH 1209 13 36 KE Y 1 2 TOW H H Q4 0 0 Q3 0 0 Q2 0 1 Q1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z All resistors are ± 1%tolerance. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (signal condition). I n t e r n a l p u l l -u p . When enabled by TOE. Three-state outputs. and its state is a function of ESt and the voltage on St. M a y b e u s e d to b i a s th e i n p u ts a t mi d -r a i l . provides the code corresponding to the last valid tone pair received. Internal Connection. Returns to logic low when the voltage on St/GT falls below VTSt. Inhibits detection of tones represents keys A. C. Single Ended Input Configuration ©2000 California Micro Devices Corp. Milpitas.579545 MHz crystal connected between these pins completes internal oscillator. (See Fig. All capacitors are ± 5% tolerance.

California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www. Guard Time Adjustment Figure 6. 9/28/2000 215 Topaz Street.calmicro. Basic Steering Circuit Figure 5.com 7 . All rights reserved. Differential Input Configuration © 2000 California Micro Devices Corp. Milpitas. Typical Filter Characteristic Figure 4.CALIFORNIA MICRO DEVICES CM8870/70C Figure 3.

calmicro. All rights reserved. Tol. Tol.com VSS Q1 Q2 Q1 9/28/2000 . Milpitas. I — -40OC to +85OC.S. ©2000 California Micro Devices Corp. ±5% P.CALIFORNIA MICRO DEVICES CM8870/70C OSC1 OSC2 OSC3 OSC1 OSC2 OSC1 OSC2 OSC1 OSC2 OSC1 of other CM887X’s Clock input of other devices 30pF 3.S. ±5% P.58 Mhz 30pF 30pF Figure 7. CM8870/70C Crystal Connection St/GT 3 3 2 2 1 1 20 20 IN+ INGS VREF INH IC* OSC1 OSC2 VSS 1 2 18 17 VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE IN+ INGS VREF IC* IC* OSC1 OSC2 VSS 1 2 3 18 17 16 VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE GS VREF 4 5 3 4 5 6 7 8 9 CM8870C 16 15 14 13 12 11 10 4 5 6 7 8 9 CM8870 15 14 13 12 11 10 19 18 ESt StD NC Q4 Q3 VREF INH PD OSC3 OSC1 4 5 6 7 8 19 18 St/GT VDD VDD ININ+ IN+ IN- ININ+ IN+ IN- NC GS Est StD NC Q4 Q3 IC * 6 IC * 7 OSC1 8 CM8870 10 11 12 13 9 17 16 15 14 CM8870C 10 11 12 13 Q2 9 17 16 15 14 OSC2 TOE OSC2 TOE VSS P — Plastic DIP (18) F — Plastic SOP EIAJ (18) S — SOIC (18) P — Plastic DIP (18) F — Plastic SOP EIAJ (18) S — SOIC (18) PE — PLCC (20) * — Connect To VSS PE — PLCC (20) Ordering Information Example: Product Identification Number Package P — F — PE — S — CM8870 CM8870C P I Plastic DIP (18) Plastic SOP EIAJ (18) PLCC (20) SOIC (18) Temperature/Processing None — 0OC to +70OC. 8 215 Topaz Street. CM8870C Crystal Connection (PLCC Package Only) Pin Assignments Figure 8. California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.

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