Features

• High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 8K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles – 512 Bytes Internal SRAM – Programming Lock for Software Security Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels for TQFP Package Only 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x for TQFP Package Only – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages – 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF Operating Voltages – 2.7 - 5.5V for ATmega8535L – 4.5 - 5.5V for ATmega8535 Speed Grades – 0 - 8 MHz for ATmega8535L – 0 - 16 MHz for ATmega8535

8-bit Microcontroller with 8K Bytes In-System Programmable Flash ATmega8535 ATmega8535L Summary

• • •

2502KS–AVR–10/06

Note: This is a summary document. A complete document is available on our Web site at www.atmel.com.

Pin Configurations

Figure 1. Pinout ATmega8535
(XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 PC4 PC3 PC2 PC1 (SDA) PC0 (SCL) PD7 (OC2)

PLCC
PB4 (SS) PB3 (AIN1/OC0) PB2 (AIN0/INT2) PB1 (T1) PB0 (XCK/T0) GND VCC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PB4 (SS) PB3 (AIN1/OC0) PB2 (AIN0/INT2) PB1 (T1) PB0 (XCK/T0) GND VCC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3)
33 32 31 30 29 28 27 26 25 24 23 PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 PC4

44 43 42 41 40 39 38 37 36 35 34

(MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2

1 2 3 4 5 6 7 8 9 10 11

12 13 14 15 16 17 18 19 20 21 22

PD3 PD4 PD5 PD6 PD7 VCC GND (SCL) PC0 (SDA) PC1 PC2 PC3

(INT1) (OC1B) (OC1A) (ICP1) (OC2)

NOTE: MLF Bottom pad should be soldered to ground.

Disclaimer

Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

2

ATmega8535(L)
2502KS–AVR–10/06

(INT1) (OC1B) (OC1A) (ICP1) (OC2)

PD3 PD4 PD5 PD6 PD7 VCC GND (SCL) PC0 (SDA) PC1 PC2 PC3

18 19 20 21 22 23 24 25 26 27 28

(MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2

7 8 9 10 11 12 13 14 15 16 17

6 5 4 3 2 1 44 43 42 41 40

39 38 37 36 35 34 33 32 31 30 29

PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 PC4

Block Diagram PA0 .PD7 3 2502KS–AVR–10/06 . Figure 2.PC7 Block Diagram PORTA DRIVERS/BUFFERS PORTC DRIVERS/BUFFERS GND PORTA DIGITAL INTERFACE PORTC DIGITAL INTERFACE AVCC MUX & ADC AREF PROGRAM COUNTER ADC INTERFACE TWI STACK POINTER TIMERS/ COUNTERS OSCILLATOR PROGRAM FLASH SRAM INTERNAL OSCILLATOR XTAL1 INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X WATCHDOG TIMER OSCILLATOR XTAL2 MCU CTRL. By executing instructions in a single clock cycle. INTERFACE PORTB DIGITAL INTERFACE PORTD DIGITAL INTERFACE PORTB DRIVERS/BUFFERS PORTD DRIVERS/BUFFERS PB0 .PA7 VCC PC0 . & TIMING RESET INSTRUCTION DECODER Y Z CONTROL LINES ALU INTERRUPT UNIT INTERNAL CALIBRATED OSCILLATOR AVR CPU STATUS REGISTER EEPROM PROGRAMMING LOGIC SPI USART + - COMP.ATmega8535(L) Overview The ATmega8535 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture.PB7 PD0 . the ATmega8535 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The Idle mode stops the CPU while allowing the SRAM. AVR UART – Compatibility” on page 146 for details. However. allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The double buffering of the USART Receive Register is disabled. program debugger/simulators. a byte oriented Two-wire Serial Interface. The ATmega8535 AVR is supported with a full suite of program and system development tools including: C compilers. internal and external interrupts. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC. and six software selectable power saving modes. an SPI serial port. 32 general purpose working registers. 512 bytes SRAM. The boot program can use any interface to download the application program in the Application Flash memory. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip. AT90S8535 Compatibility The ATmega8535 provides all the features of the AT90S8535. a serial programmable USART. some incompatibilities between the two microcontrollers exist. SPI port. In Standby mode. a programmable Watchdog Timer with Internal Oscillator. the asynchronous timer continues to run. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface. Software in the Boot Flash section will continue to run while the Application Flash section is updated. an AT90S8535 compatibility mode can be selected by programming the S8535C fuse. To solve this problem. by a conventional nonvolatile memory programmer. 10-bit ADC with optional differential input stage with programmable gain in TQFP package. 512 bytes EEPROM. the Atmel ATmega8535 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. See “AVR USART vs. This allows very fast start-up combined with low-power consumption. 32 general purpose I/O lines. ATmega8535 is pin compatible with AT90S8535. to minimize switching noise during ADC conversions. The ATmega8535 is backward compatible with AT90S8535 in most cases. the location of fuse bits and the electrical characteristics differs between the two devices. and evaluation kits. The ATmega8535 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. and interrupt system to continue functioning. an 8-channel. Timer/Counters. several new features are added. macro assemblers. However. • 4 ATmega8535(L) 2502KS–AVR–10/06 . providing true Read-While-Write operation. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU). both the main Oscillator and the asynchronous timer continue to run. InCircuit Emulators. In Extended Standby mode. three flexible Timer/Counters with compare modes. The device is manufactured using Atmel’s high density nonvolatile memory technology. The Power-down mode saves the register contents but freezes the Oscillator. allowing the user to maintain a timer base while the rest of the device is sleeping. In addition.The AVR core combines a rich instruction set with 32 general purpose working registers. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45 for details. the crystal/resonator Oscillator is running while the rest of the device is sleeping. AT90S8535 Compatibility Mode Programming the S8535C fuse will change the following functionality: • The timed sequence for changing the Watchdog Time-out period is disabled. or by an On-chip Boot program running on the AVR core. In Power-save mode. and can replace the AT90S8535 on current Printed Circuit Boards. disabling all other chip functions until the next interrupt or Hardware Reset.

As inputs. Port D also serves the functions of various special features of the ATmega8535 as listed on page 64. even if the clock is not running. Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The minimum pulse length is given in Table 15 on page 37. Port pins can provide internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. Port B (PB7. even if the clock is not running.PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). Port C (PC7. Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.. If the ADC is used.. Port A serves as the analog inputs to the A/D Converter.PA0) Digital supply voltage. even if the clock is not running. Port B also serves the functions of various special features of the ATmega8535 as listed on page 60. Port D (PD7.. When pins PA0 to PA7 are used as inputs and are externally pulled low. even if the clock is not running. The Port A pins are tri-stated when a reset condition becomes active. The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. even if the ADC is not used. if the A/D Converter is not used.PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). RESET Reset input. The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. AREF is the analog reference pin for the A/D Converter. The Port D pins are tri-stated when a reset condition becomes active. Port B pins that are externally pulled low will source current if the pull-up resistors are activated. they will source current if the internal pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active. It should be externally connected to VCC. Ground. A low level on this pin for longer than the minimum pulse length will generate a reset. The Port A output buffers have symmetrical drive characteristics with both high sink and source capability.PD0) XTAL1 XTAL2 AVCC AREF 5 2502KS–AVR–10/06 . Port C pins that are externally pulled low will source current if the pull-up resistors are activated. As inputs. Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). Output from the inverting Oscillator amplifier. The Port B pins are tri-stated when a reset condition becomes active. As inputs..ATmega8535(L) Pin Descriptions VCC GND Port A (PA7. even if the clock is not running. it should be connected to VCC through a low-pass filter. Shorter pulses are not guaranteed to generate a reset. Port A also serves as an 8-bit bi-directional I/O port. AVCC is the supply voltage pin for Port A and the A/D Converter.

6 ATmega8535(L) 2502KS–AVR–10/06 . application notes and datasheets are available for download on http://www.Resources A comprehensive set of development tools.com/avr.atmel.

Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.ATmega8535(L) About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Please confirm with the C Compiler documentation for more details. 7 2502KS–AVR–10/06 .

Register Summary Address 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20(1) (0x40)(1) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) Name SREG SPH SPL OCR0 GICR GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUCSR TCCR0 TCNT0 OSCCAL SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRRL ACSR ADMUX ADCSRA ADCH ADCL TWDR TWAR TWSR Bit 7 I – SP7 INT1 INTF1 OCIE2 OCF2 SPMIE TWINT SM2 – FOC0 Bit 6 T – SP6 INT0 INTF0 TOIE2 TOV2 RWWSB TWEA SE ISC2 WGM00 Bit 5 H – SP5 INT2 INTF2 TICIE1 ICF1 – TWSTA SM1 – COM01 Bit 4 S – Bit 3 V – Bit 2 N – Bit 1 Z SP9 SP1 IVSEL – OCIE0 OCF0 PGERS – ISC01 EXTRF CS01 Bit 0 C SP8 SP0 IVCE – TOIE0 TOV0 SPMEN TWIE ISC00 PORF CS00 Page 10 12 12 85 49.223 110 113 114 114 114 114 114 114 114 114 Timer/Counter1 – Counter Register High Byte Timer/Counter1 – Counter Register Low Byte Timer/Counter1 – Output Compare Register A High Byte Timer/Counter1 – Output Compare Register A Low Byte Timer/Counter1 – Output Compare Register B High Byte Timer/Counter1 – Output Compare Register B Low Byte Timer/Counter1 – Input Capture Register High Byte Timer/Counter1 – Input Capture Register Low Byte FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register – – URSEL URSEL – – – – UMSEL – – – – UPM1 – – WDCE – UPM0 – USBS – – AS2 WDE TCN2UB WDP2 UCSZ1 OCR2UB WDP1 UBRR[11:8] UCSZ0 – UCPOL EEAR8 TCR2UB WDP0 128 130 131 131 42 169 167 19 19 19 EEPROM Address Register Low Byte EEPROM Data Register – PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPIF SPIE RXC RXCIE ACD REFS1 ADEN – PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC TXCIE ACBG REFS0 ADSC – PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 – DORD UDRE UDRIE ACO ADLAR ADATE – PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 – MSTR FE RXEN ACI MUX4 ADIF EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 – CPOL DOR TXEN ACIE MUX3 ADIE EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 – CPHA PE UCSZ2 ACIC MUX2 ADPS2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 – SPR1 U2X RXB8 ACIS1 MUX1 ADPS1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM TXB8 ACIS0 MUX0 ADPS0 19 66 66 66 66 66 67 67 67 67 67 67 67 143 143 141 164 165 166 169 203 219 221 222 222 183 SPI Data Register USART I/O Data Register USART Baud Rate Register Low Byte ADC Data Register High Byte ADC Data Register Low Byte Two-wire Serial Interface Data Register TWA6 TWS7 TWA5 TWS6 TWA4 TWS5 TWA3 TWS4 TWA2 TWS3 TWA1 – TWA0 TWPS1 TWGCE TWPS0 183 183 8 ATmega8535(L) 2502KS–AVR–10/06 .203. 134 228 181 32.88. 115. 68 40.. 133 86. 69 83 85 30 SP4 SP3 SP2 Timer/Counter0 Output Compare Register – – OCIE1A OCF1A RWWSRE TWSTO SM0 – COM00 – – OCIE1B OCF1B BLBSET TWWC ISC11 WDRF WGM01 – – TOIE1 TOV1 PGWRT TWEN ISC10 BORF CS02 Timer/Counter0 (8 Bits) Oscillator Calibration Register ADTS2 COM1A1 ICNC1 ADTS1 COM1A0 ICES1 ADTS0 COM1B1 – – COM1B0 WGM13 ACME FOC1A WGM12 PUD FOC1B CS12 PSR2 WGM11 CS11 PSR10 WGM10 CS10 59. 69 70 85.135. 116.

Note that the CBI and SBI instructions will operate on all bits in the I/O Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. Some of the status flags are cleared by writing a logical one to them. 9 2502KS–AVR–10/06 . reserved bits should be written to zero if accessed. 3.ATmega8535(L) Register Summary (Continued) Address 0x00 (0x20) Name TWBR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 181 Two-wire Serial Interface Bit Rate Register Notes: 1. The CBI and SBI instructions work with registers 0x00 to 0x1F only. writing a one back into any flag read as set. thus clearing the flag. Reserved I/O memory addresses should never be written. For compatibility with future devices.

N.C.H Z. Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal.C.K .N. K Rd.Rr Rd. K Rd. N.N.C. Rr Rd Rd Rd.N.C. Rr Rd.N. N. Rr Rd.V.N.S Z.C Rdh:Rdl ← Rdh:Rdl .Rr Rd ← Rd .V.Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd.N.V None Z.V Z.C.Rr . Rr Rd. K Rd.Rr Rd.N.V Z. Rr Rd. Rr k Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg.N.K Rd Rd Rd Rd Rd Rd.N.V. b P.V.V.H None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS 1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 PC ← PC + k + 1 PC ← Z PC ← PC + k + 1 PC ← Z PC ← STACK PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 R1:R0 ← (Rd x Rr) << BRANCH INSTRUCTIONS DATA TRANSFER INSTRUCTIONS 10 ATmega8535(L) 2502KS–AVR–10/06 .S Z.K Rd.C. Rr Rd.V Z.V.C.V. b Rr.C.N.K Rd.V Z.V Z.V. Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Operation Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd . Rr Rd.K Rd.C Rd ← Rd .V.H Z.K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr Flags Z.V Z.N.H Z. K Rdl.N.H Z.C Z.H Z.N.V Z.V Z. Rr Rd.H Z.C.N.N.V.C. Rr Rdl. Rr Rd. b P.K Rd ← Rd .Rr Rd.K Rr.C Z.H Z.C Z.C None None None None None I None Z.H Z.K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF .C.V.V Z.N.V Z.N. b s. Signed Branch if Less Than Zero.V Z. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare. Rr Rd.C. k k k k k k k k k k k k k k k k k k k k Operands Rd.H Z.C.C Z.C Z.N. k s. Rr Rd.N.V.N. N.

Load Indirect and Pre-Dec. b Rd.Rd(n)← Rd(n+1). Rr Rd. Load Indirect and Pre-Dec. Rr Rr Rd P.4)←Rd(3.ATmega8535(L) Mnemonics MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH MCU CONTROL INSTRUCTIONS NOP No Operation None 1 Rd.1.C.C. Load Indirect and Pre-Dec.Rd(7. k X. (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← (Z) Rd ← (Z). b Rd... Rr . X ← X + 1 X ← X .b P.V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H #Clocks 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT AND BIT-TEST INSTRUCTIONS 11 2502KS–AVR–10/06 . Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG Operation Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ← K Rd ← (X) Rd ← (X).N. Rr Y. Rr Z+. K Rd.Rr Z. Rd(7) ← 0 Rd(0)←C. Store Indirect and Pre-Dec.Y Rd. Rr . Rd ← (X) Rd ← (Y) Rd ← (Y). Y ← Y + 1 Y ← Y .. Z+q Rd. -Z Rd. Store Indirect and Pre-Dec.1. Rr Y+. Rr Description Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc.Y+q Rd.6 Rd(3.4). . Z ← Z+1 Z ← Z .b) ← 0 Rd(n+1) ← Rd(n).N. X Rd. Rr Y+q. Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z).N. Rr X+.C←Rd(0) Rd(n) ← Rd(n+1).1.b Rd Rd Rd Rd Rd Rd s s Rr. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow.V Z.V Z. (X) ← Rr (Y) ← Rr (Y) ← Rr.X. Load Indirect Load Indirect and Post-Inc. (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr. Y ← Y + 1 Y ← Y . Rr Rd.b) ← 1 I/O(P. Y+ Rd. Z Rd. Z+ Rd. Z+ Operands Rd.C. Store Indirect and Pre-Dec.C←Rd(7) Rd(7)←C. n=0.1. Z ← Z + 1 Z ← Z . X ← X + 1 X ← X .Rr k. X+ Rd. Rd(0) ← 0 Rd(n) ← Rd(n+1)..1.X Rd.C. Z Rd.Rd(n+1)← Rd(n). . Store Indirect Store Indirect and Post-Inc.V Z.N. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc.0)←Rd(7.0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I←0 S←1 S←0 V←1 V←0 T←1 T←0 H←1 H←0 Flags None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z. Z ← Z+1 (Z) ← R1:R0 Rd ← P P ← Rr STACK ← Rr Rd ← STACK I/O(P. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc.1.Y.N..C.V Z. Rr Z+q. Y Rd. P P. Rr -Z.

Mnemonics SLEEP WDR BREAK Operands Description Sleep Watchdog Reset Break Operation (see specific descr. for Sleep function) (see specific descr. for WDR/Timer) For On-chip Debug Only Flags None None None #Clocks 1 1 N/A 12 ATmega8535(L) 2502KS–AVR–10/06 .

7 x 7 x 1. Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 13 2502KS–AVR–10/06 .5V Industrial (-40°C to 85°C) Note: 1. Package Type 44A 40P6 44J 44M1-A 44-lead.5. Plastic J-leaded Chip Carrier (PLCC) 44-pad. Thin (1.5.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40-pin.7 . lead pitch 0. This device can also be supplied in wafer form.600” Wide. Pb-free packaging alternative. Plastic Dual Inline Package (PDIP) 44-lead. 2.0 mm body.5V Industrial (-40°C to 85°C) Commercial (0°C to 70°C) 16 4.ATmega8535(L) Ordering Information Speed (MHz) Power Supply Ordering Code ATmega8535L-8AC ATmega8535L-8PC ATmega8535L-8JC ATmega8535L-8MC ATmega8535L-8AI ATmega8535L-8PI ATmega8535L-8JI ATmega8535L-8MI ATmega8535L-8AU(2) ATmega8535L-8PU(2) ATmega8535L-8JU(2) ATmega8535L-8MU(2) ATmega8535-16AC ATmega8535-16PC ATmega8535-16JC ATmega8535-16MC ATmega8535-16AI ATmega8535-16PI ATmega8535-16JI ATmega8535-16MI ATmega8535-16AU(2) ATmega8535-16PU(2) ATmega8535-16JU(2) ATmega8535-16MU(2) Package(1) 44A 40P6 44J 44M1 44A 40P6 44J 44M1 44A 40P6 44J 44M1 44A 40P6 44J 44M1 44A 40P6 44J 44M1 44A 40P6 44J 44M1 Operation Range Commercial (0°C to 70°C) 8 2. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.50 mm. complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).5 .Also Halide free and fully Green.. 0.

2. This package conforms to JEDEC reference MS-026.00 12. 44-lead.00 10.45 0. Lead coplanarity is 0.0 mm Body Thickness.90 11.90 0. 44A REV.30 0. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.25 mm per side. Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 1.05 0.10 mm maximum.75 9.25 10.75 Note 2 Note 2 NOTE A2 A Notes: 1.45 NOM – – 1. B R 14 ATmega8535(L) 2502KS–AVR–10/06 .05 12.09 0.10 0.Packaging Information 44A PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN – 0.10 12.00 12.8 mm Lead Pitch. CA 95131 TITLE 44A. Allowable protrusion is 0.20 0. Variation ACB. Dimensions D1 and E1 do not include mold protrusion. 10 x 10 mm Body Size.15 1.95 11.20 0. 3. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose.80 TYP MAX 1.00 10. 0.25 10.00 – – – 0.75 9.

ATmega8535(L) 40P6 D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eB 0º ~ 15º REF SYMBOL A A1 D E E1 B COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.875 13.826 – 52.578 15. B R 15 2502KS–AVR–10/06 .462 0. 40P6 REV. Dimensions D and E1 do not include mold Flash or Protrusion.381 17.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. CA 95131 TITLE 40P6.651 3.970 0.556 0.381 52.041 3.600"/15.356 1. Mold Flash or Protrusion shall not exceed 0.240 13. This package conforms to JEDEC reference MS-011. Variation AC.010"). 2.203 15.25 mm (0.540 TYP MAX 4.070 15. 40-lead (0. B1 L C eB e 09/28/01 2325 Orchard Parkway San Jose.494 NOM – – – – – – – – – – 2.526 Note 2 Note 2 NOTE Notes: 1.559 1.048 0.

653 16. E1 D2/E2 B B1 e MIN 4. 2.813 0.14(0.14(0.102 mm) maximum.399 16.191 2. Dimensions D1 and E1 do not include mold protrusion. B R 16 ATmega8535(L) 2502KS–AVR–10/06 .318(0. 44-lead.662 16. 1 IDENTIFIER 1.254 mm) per side.653 16.662 17.045) X 45˚ PIN NO. Allowable protrusion is .0125) 0. This package conforms to JEDEC reference MS-018. Plastic J-leaded Chip Carrier (PLCC) DRAWING NO.045) X 45˚ 0. 44J REV.660 0. CA 95131 TITLE 44J.191(0.004" (0.399 16.508 17.286 0.330 NOM – – – – – – – – – – 1.048 – 17. Variation AC.270 TYP MAX 4. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line.533 Note 2 Note 2 NOTE 10/04/01 2325 Orchard Parkway San Jose.010"(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1.510 14.510 17. 3.44J 1.986 0.51(0.0075) E1 B E B1 D2/E2 e D1 D A A2 A1 0.572 3. Lead coplanarity is 0.002 0.

CA 95131 TITLE 44M1. 5.02 0.20 mm Exposed Pad.0 mm Body.80 – NOM 0. G R 17 2502KS–AVR–10/06 . L K 0.90 5.90 5.05 NOTE A A1 A3 b 0.50 BSC 0.00 0.20 0. Micro Lead Frame Package (MLF) DRAWING NO. 1 (SAW Singulation) VKKD-3.30 7.41 5/27/06 2325 Orchard Parkway San Jose.90 0.20 R) D2 E E2 e BOTTOM VIEW Note: JEDEC Standard MO-220.10 5. Fig.00 6.40 K b e Option C D Pin #1 Notch (0.00 0.26 0.40 7. Lead Pitch 0.00 5.50 mm.00 5. 7 x 7 x 1.ATmega8535(L) 44M1-A D Marked Pin# 1 ID E SEATING PLANE TOP VIEW A1 A3 K L D2 Pin #1 Corner A SIDE VIEW 1 2 3 Option A Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL Option B Pin #1 Chamfer (C 0. 44M1 REV.10 5.23 7.18 6.64 0.20 7.20 0.69 0.30) E2 MIN 0.59 0. 44-pad.25 REF MAX 1.

Asynchronous Oscillator does not stop in Power-down The asynchronous oscillator does not stop when entering Power-down mode. disable then enable the Analog Comparator before the first conversion. • First Analog Comparator conversion may be delayed • Asynchronous Oscillator does not stop in Power-down 1. 2. A and B The revision letter refer to the device revision. Problem Fix/Workaround Manually disable the asynchronous timer before entering Power-down. This leads to higher power consumption than expected. Problem Fix/Workaround When the device has been powered or reset.Errata ATmega8535 Rev. 18 ATmega8535(L) 2502KS–AVR–10/06 . the first Analog Comparator conversion will take longer than expected on some devices. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC.

2502I. 2502K. Updated “Errata” on page 18. 2502G.06/06 Changes from Rev. 3. Changes from Rev. 2502G. 2502J. Updated “Errata” on page 18. Changes from Rev. 4.ATmega8535(L) Datasheet Revision History Changes from Rev. Updated “Serial Peripheral Interface – SPI” on page 136. Updated “Reset Characteristics” on page 37. Updated “Ordering Information” on page 13. 1. Updated “Calibrated Internal RC Oscillator” on page 29. 2502E-12/03 to Rev. 2502I.10/06 Please note that the referring page numbers in this section are referring to this document. Changes from Rev. Updated SPH in “Stack Pointer” on page 12. 2502J. Updated Table 7 on page 29. 2502G-06/04 Changes from Rev.04/05 1.06/06 to Rev. 2. Updated Table 37 on page 69 and Table 113 on page 261. Updated TOP/BOTTOM description for all Timer/Counters Fast PWM mode.06/04 to Rev. The referring revision in this section are referring to the document revision.04/06 1. 2502F-06/04 1. 2502H. Updated code example “USART Initialization” on page 150. 3. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF”.08/06 to Rev. 3. 2. Table 17 on page 42 and Table 111 on page 258. Updated “Ordering Information” on page 13. Added “Resources” on page 6. 2. Removed “Preliminary” and TBD’s. 2502E-12/03 to Rev. 2502D-09/03 to Rev.04/05 to Rev. 2502F. 1. 2. 2502E-12/03 1. Updated C code in “USART Initialization” on page 150. 2502H.04/06 to Rev. Updated “Electrical Characteristics” on page 255. 1. Changes from Rev. 4.08/06 Changes from Rev. Added section “Errata” on page 18. 19 2502KS–AVR–10/06 . Updated note in “Bit Rate Generator Unit” on page 180. 1. 4. 2.

Added note to “Pinout ATmega8535” on page 2. Table 77 on page 196. Updated Figure 1 on page 2. Updated “Absolute Maximum Ratings” and “DC Characteristics” in “Electrical Characteristics” on page 255. Updated “Electrical Characteristics” on page 255. Changes from Rev. Table 76 on page 193. 4. 7. 6. Updated code examples on page 44. Removed ADHSM bit. Removed the references to the application notes “Multi-purpose Oscillator” and “32 kHz Crystal Oscillator”. 2502B-09/02 to Rev. 11. Added the section “EEPROM Write During Power-down Sleep Mode” on page 22.Changes from Rev. Updated Table 68 on page 169. Updated “Packaging Information” on page 14. Table 75 on page 190. Removed CALL and JMP instructions from code examples and “Instruction Set Summary” on page 10. Updated “ATmega8535 Typical Characteristics” on page 266. Updated “Reset Characteristics” on page 37. Updated “ADC Characteristics” on page 263. 8. Added information about PWM symmetry for Timer 0 on page 79 and Timer 2 on page 126. 5. 7. Figure 87 on page 191. 2. 9. 8. Figure 85 on page 185. 2502C-04/03 to Rev. 13. Removed the section description in “SPI Serial Programming Characteristics” on page 254. 12. 2502C-04/03 1. 3. Renamed Port D pin ICP to ICP1. Updated the description in “Filling the Temporary Buffer (Page Loading)” and “Performing a Page Write” on page 231. Table 113 on page 261. 5. 2. Figure 98 on page 207. Table 108 on page 253. 10. 20 ATmega8535(L) 2502KS–AVR–10/06 . See “Alternate Functions of Port D” on page 64. which do not exist. 3. Updated description on “Bit 5 – TWSTA: TWI START Condition Bit” on page 182. 2502D-09/03 1. Removed “Advance Information” and some TBD’s from the datasheet. 4. Updated Table 111 on page 258. Figure 84 on page 179. 6.

Updated “ADC Characteristics” on page 263. Various Timer 1 corrections. Added WD_FUSE period in Table 108 on page 253. Canged the Endurance on the Flash to 10. 15. 2502A-06/02 to Rev. 16. Changes from Rev. 21 2502KS–AVR–10/06 . 2502B-09/02 1. 14.ATmega8535(L) 14. Updated “Register Summary” on page 8.000 Write/Erase Cycles.

AVR ®. Atmel’s products are not intended.Atmel Corporation 2325 Orchard Parkway San Jose. to any intellectual property right is granted by this document or in connection with the sale of Atmel products. Colorado Springs. or warranted for use as components in applications intended to support or sustain life. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. authorized. USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose. USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn. No license. PUNITIVE. CA 95131. EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS. and others are the trademarks or registered trademarks of Atmel Corporation or its subsidiaries. BUSINESS INTERRUPTION. Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F. logo and combinations thereof. All rights reserved. INDIRECT. FITNESS FOR A PARTICULAR PURPOSE. 1-24-8 Shinkawa Chuo-ku. USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR. © 2006 Atmel Corporation. WITHOUT LIMITATION. by estoppel or otherwise. SPECIAL OR INCIDENTAL DAMAGES (INCLUDING. Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT. CO 80906. OR NON-INFRINGEMENT. Colorado Springs. USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE. CONSEQUENTIAL. Atmel does not make any commitment to update the information contained herein. Blvd. Other terms and product names may be trademarks of others.atmel. USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3. Tonetsu Shinkawa Bldg. Blvd. Everywhere You Are ®. BUT NOT LIMITED TO. THE IMPLIED WARRANTY OF MERCHANTABILITY. express or implied. Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www. DAMAGES FOR LOSS OF PROFITS. CA 95131. IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING. Atmel®. CA 95131. 2502KS–AVR–10/06 . France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex. CO 80906.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex. France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn.

Sign up to vote on this title
UsefulNot useful