# LOW POWER VLSI

By, K.Nagendra 06S11A0421

Why worry about power? --Heat Dissipation
Microprocessor power Consumption

. Reduced weight. Low cost operation High Performance: Low-cost cooling. Reduced volume.Why we go to Low Power. Low-cost operation RELIABILITY: Avoid thermal problems Avoid scaling related problems . Low-cost packaging. PORTABILITY: Enhanced run-time.

Speed/Power performance for available Technologies .

Where Does Power Go In CMOS  Dynamic Power Consumption : Charging and Discharging Capacitors  Short Circuit Currents : Short circuit path between supply rails during switching  Leakage: Leakage diodes and transistors Ptotal = PDYN + PSC + PLeakage =CLVDDF+VDDIPEAK{(Tr + Tf)/2}F+VDD ILEAK .

Dynamic Power Consumption L dd 2 Energy/transition = C * V .

CL  Power dissipation is data dependent Function of switching activity .Dynamic Power Consumption  Power = Energy / Transition * transition rate = CL* V 2 * f dd  So. f . power is proportional to Vdd .

«  Further decreasing may cause affect to Threshold voltage  Relatively independent of logic function and style. 3.2. 1.0.8. 1. 1.Reducing Vdd  Power P is proportional to square of V  VDD has decreased in modern processes ± High VDD would damage modern tiny transistors ± Lower VDD saves power  VDD = 5.  By reducing Vdd Noise margin will be affected . 1.3.5.5. 2.  Power Delay Product Improves with lowering Vdd.

VOL  NMH = VOH .Noise Margin  NML = VIL .VIH .

Power Consumption is Data Dependent Ex: Static 2 i/p NOR Gate A B Y A B Y 0 0 1 1 0 1 0 1 1 0 0 0 P(A=1) = ½ P(B=1) = ½ Then P(out=1) = ¼ P(out=0) = 1-P(out=1) =1-1/4 = ¾ P(0->1) = P(out=1).P(out=0) = ¾ * ¼ = 3/16 .

Transition Probability of 2-input NOR Gate .

2Pa * Pb)) (Pa + Pb 2Pa * Pb) Switching Activity for Static CMOS P0 -> 1 = P0 * P1 .Transition Probabilities for Basic Gates P0 -> 1 (1-Pa * Pb) Pa Pb AND (1-Pa)(1-Pb)(1-(1-Pa)(1-Pb)) OR EXOR (1-(Pa + Pb .

? Clk In1 In2 In3 Clk Mp Out CL PDN  Power is only dissipated when out=0  Ceff = P(out=0) * CL Me Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1) .How about Dynamic Circuits..

2 input NOR gate A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0  Switching activity is always Higher in Dynamic Circuits P(A=1) = ½ P(B=1) = ½ P(out=0) = ¾ Ceff = ¾ * CL .

Transition Probabilities For Dynamic GATES P0 -> 1 AND OR (1-Pa * Pb) (1-Pa)(1-Pb) EXOR (1-(Pa + Pb .2Pa * Pb)) Switching Activity for Precharged Dynamic Gates .

.  Glitching often arises when paths with unbalanced propagation delay converges at the same point in the circuit.Glitching«  Glitching refers to spurious and unwanted transitions that occur before a node settle down to its final steady-state value.  The dissipation caused by the spurious transitions can reach up to 25% of the total dissipation for some circuits.

 No glitching in dynamic circuits .Glitching in Static CMOS  Each gate has Unit delay  Input A. B. C arrive at same time.

? .How to Cope With Glitching..

 In static CMOS circuits the flow current from VDD to GND during Switching when both NMOS and PMOS conducting Simultaneously.  Such path never exists in a dynamic circuits.Short Circuit Currents  Short circuit currents are encountered only in static design. .

5 0.0 1 1.0 1.15 NMOS sat PMOS sat NMOS res PMOS sat IV D D ( m A ) 0.05 NMOS res PMOS off 2 .5 NMOS off PMOS res NMOS s at PMOS res 2 0.10 1 1.0 5.5 2 .0 V in (V) 4.0 2.5 0.Short Circuit Currents Vdd Vo u t Vin CL Vout 2.0 3.5 Vin 0.5 0.

Impact of rise/fall time on ShortCircuit Currents V DD V DD V in V out CL V in V out CL Large Capacitive Load  The input through the transient region before the output start to change Small capacitive Load  Output fall time is Substantially smaller than the input rise time .

 Short-Circuit reduced by lower the Supply Voltage. .Short-Circuit energy as a function of slope ratio  Short-Circuit energy dissipation (normalized with respect to zero i/p rise time energy) for a static CMOS.  The power dissipation due to short circuit currents is minimized by matching the rise/fall times of the input and output signals.

Leakage Vd d Vo u t D ra in J u n c tio n L eak ag e S u b -T h r e s h o ld C u r ren t Sub-Threshold current Dominant factor S u b -T h r e s h o ld C u r r e n t D o m i n a n t F a c t o r .

 Reduce switching activity  Reduce physical capacitance Vin =5V P s ta t = P (In =1 ) .V d d . I s t a t m inates o ver d yn am ic c on su m p tion .Static Power Consumption Vdd  Dominates over dynamic consumption Istat Vout CL  Not a function of Switching Frequency.

large amounts of power are wasted while the system is in idlemode.System-Level optimization : Power Management  In event-driven application. .  The power consumption can be reduced significantly by using power management scheme to shunt down idle component.

 As leakage current cannot be reduced.  The power dissipation due to short circuit currents is minimized by matching the rise/fall times of the input and output signals  Glitching makes power to dissipate so it is reduced by cope process .Conclusion  Thus the low power can be achieved by decreasing Vdd to certain level. the short circuit currents are eliminated by dynamic circuits.

Allen.Aprill 1992´. .  VLSI Design Techniques for Analog and Digital Circuits ±Randall L.RABAEY  Encyclopedia of computer science and technology.  Low-Power CMOS Design ³IEEE journal of solid state circuit -pages 472-484.  Basic VLSI Design A. Phillip E.PUCKNELL.1995.References  Digital Integrated Circuits ±JAN M.Geiger.

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